Etching method for silicon-containing organic dielectric layer and semiconductor process apparatus

Abstract

This application discloses an etching method for a silicon-containing organic dielectric layer and a semiconductor process apparatus. The silicon-containing organic dielectric layer is etched by at least two alternating etching steps, wherein the at least two etching steps include a first etching step and a second etching step, the etching gas used in the first etching step includes at least an oxygen-containing gas, and the etching gas used in the second etching step includes at least an oxygen-containing gas and a fluorine-containing gas.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and specifically relates to an etching method for a silicon-containing organic dielectric layer and a semiconductor processing apparatus.

Background Art

[0002] With the rapid development of integrated circuits, silicon-containing organic materials such as benzocyclobutene (abbreviated as BCB) have wide curing temperature range, low curing temperature, low dielectric constant, excellent adhesiveness and excellent hydrophobicity, and thus are widely used as dielectric materials in electronic devices in various fields. However, when etching a silicon-containing organic dielectric layer made of a silicon-containing organic material such as BCB, sub-trench or concave-convex morphology is easily formed at the bottom of an etched trench or via hole, which as a result causes excessive concentration of electric field stress at the bottom of the trench or via hole and affects the performance of the electronic device.

Summary of the Invention

Problem to be Solved by the Invention

[0003] The present application discloses an etching method for a silicon-containing organic dielectric layer and a semiconductor processing apparatus, which are configured to reduce sub-trenches or protrusions at the bottom of a trench or via hole etched in the silicon-containing organic dielectric layer, so as to obtain a smooth morphology at the bottom of the trench or via hole.

Means for Solving the Problem

[0004] In a first embodiment, the present application discloses an etching method for a silicon-containing organic dielectric layer, comprising etching the silicon-containing organic dielectric layer by at least two alternating etching steps, wherein the at least two etching steps comprise a first etching step and a second etching step, the etching gas used in the first etching step comprises at least an oxygen-containing gas, and the etching gas used in the second etching step comprises at least an oxygen-containing gas and a fluorine-containing gas.

[0005] In some selectable examples, in a process in which at least two etching steps are repeated alternately, the ratio range of fluorine and oxygen is greater than 0 and 15 or less, or the fluorine content is 0, or in the first etching step, the ratio of fluorine and oxygen is less than 0.01, or the fluorine content is 0.

[0006] In some selectable examples, the gas flow rate range of the oxygen-containing gas used in the first etching step is 5 sccm to 200 sccm, and / or the gas flow rate range of the oxygen-containing gas used in the second etching step is 5 sccm to 200 sccm, and the gas flow rate range of the fluorine-containing gas used in the second etching step is 5 sccm to 20 sccm.

[0007] In some selectable examples, the silicon-containing organic dielectric layer material comprises BCB, the oxygen-containing gas comprises at least one of O2, CO2, CO, and SO2, and the fluorine-containing gas comprises SF6, CF4, C4F8, CHF3, and NF3. 、 It includes at least one of CH2F2 and C2F6.

[0008] In some selectable examples, the etching gas used in the first etching step and the second etching step further comprises an inert gas, the inert gas comprising at least one of Ar, He, and Ne.

[0009] In some selectable examples, the gas flow rate range of the inert gas used in the first etching step is 5 sccm to 200 sccm, and the gas flow rate range of the inert gas used in the second etching step is 5 sccm to 200 sccm.

[0010] In some selectable examples, in a process in which at least two etching steps are repeated alternately, the ratio range of fluorine to inert elements is greater than 0 and 60 or less, or the content of fluorine is 0, or in the first etching step, the ratio of fluorine to inert elements is less than 0.01, or the content of fluorine is 0.

[0011] In several selectable examples, the gas flow rate of the oxygen-containing gas is kept constant during the process in which at least two etching steps are repeated alternately, the gas flow rate of the inert gas is kept constant, and the gas flow rate change curve of the fluorine-containing gas exhibits a pulsed waveform.

[0012] In some selectable examples, the process time range used in the first etching step is 0.2s to 8s, and / or the process time range used in the second etching step is 0.2s to 5s.

[0013] In some selectable examples, the chamber pressure range used in the first etching step is 2 mTorr to 30 mTorr, and / or the chamber pressure range used in the second etching step is 2 mTorr to 30 mTorr.

[0014] In some selectable examples, the at least two etching steps further include at least one third etching step, the at least one third etching step performed between the first etching step and the second etching step, and the flow rate of the etching gas used in the third etching step is smaller than the flow rate of the etching gas used in the first etching step and the second etching step.

[0015] In a second embodiment, the present application discloses a semiconductor process apparatus comprising a process chamber, a gas supply assembly, an upper electrode assembly, a lower electrode assembly, and a control device, wherein the control device comprises at least one memory and at least one processor, the memory storing a computer program, and the processor executing the computer program to realize the etching method for the silicon-containing organic dielectric layer. [Effects of the Invention]

[0016] In the etching method and semiconductor process apparatus for a silicon-containing organic dielectric layer disclosed in this application, the silicon-containing organic dielectric layer is etched by at least two alternating etching steps, where the at least two etching steps include a first etching step and a second etching step, the etching gas used in the first etching step includes at least an oxygen-containing gas, and the etching gas used in the second etching step includes at least an oxygen-containing gas and a fluorine-containing gas. By alternating the first etching step and the second etching step, the gas flow rate ratio of the fluorine-containing gas and the oxygen-containing gas can be adjusted, thereby adjusting the etching rate of different elements in the silicon-containing organic dielectric layer. This reduces sub-trenches and protrusions at the bottom of trenches or via holes in the silicon-containing organic dielectric layer, thereby making the bottom of the trenches or via holes smoother and preventing excessive concentration of electric field stress at the bottom of the trenches or via holes, which would affect the performance of the electronic device. [Brief explanation of the drawing]

[0017] To more clearly explain the technical concepts in the embodiments or background art of this application, the drawings necessary for the embodiments or background art of this application are described below.

[0018] [Figure 1] This is a SEM image of a trench in a silicon-containing organic dielectric layer etched using the current etching method. [Figure 2] These are schematic diagrams of the cross-sectional structure of an electronic device in each flow of the etching method for a silicon-containing organic dielectric layer disclosed in the embodiments of this application. [Figure 3] These are schematic diagrams of the cross-sectional structure of an electronic device in each flow of the etching method for a silicon-containing organic dielectric layer disclosed in the embodiments of this application. [Figure 4] These are schematic diagrams of the cross-sectional structure of an electronic device in each flow of the etching method for a silicon-containing organic dielectric layer disclosed in the embodiments of this application. [Figure 5] It is a schematic diagram of a cross-sectional structure of an electronic device in each step of the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 6] It is a schematic diagram of a cross-sectional structure of an electronic device in each step of the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 7] It is a schematic diagram of a cross-sectional structure of an electronic device in each step of the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 8] It is a schematic diagram of a cross-sectional structure of an electronic device in each step of the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 9] It is an SEM image of a trench having an uneven bottom disclosed in an example of the present application. [Figure 10] It is an SEM image of a trench having a sub-trench shaped bottom disclosed in an example of the present application. [Figure 11] It is an SEM image of a trench etched by the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 12] It is an SEM image of a trench having an arched sidewall disclosed in an example of the present application. [Figure 13] It is a schematic diagram of a time-dependent change curve for the flow rates of an oxygen-containing gas (e.g., O₂), a fluorine-containing gas (e.g., SF₆) and an inert gas (e.g., Ar) in the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 14] It is a schematic diagram showing a time-dependent change curve of the flow rate ratio of the fluorine-containing gas (e.g., SF₆) to the inert gas (e.g., Ar), and a time-dependent change curve of the flow rate ratio of the fluorine-containing gas (e.g., SF₆) to the oxygen-containing gas (e.g., O₂) in the etching method for a silicon-containing organic dielectric layer disclosed in an example of the present application. [Figure 15] It is a schematic structural diagram of a semiconductor processing apparatus disclosed in an example of the present application. Mode for Carrying Out the Invention

[0019] The technical inventions of the embodiments of this application will be clearly and completely described below with reference to the drawings of the embodiments of this application, although obviously the embodiments described are only a part of the embodiments of this application, not all of them. All other embodiments that a person skilled in the art could obtain without creative effort based on the embodiments of this application are within the scope of protection of this application.

[0020] As shown in Figure 1, when etching a silicon-containing organic dielectric layer made of silicon-containing organic material such as BCB using current etching methods, sub-trenches or irregularities tend to form at the bottom of the etched trenches or via holes. As a result, the electric field stress at the bottom of the trenches or via holes becomes excessively concentrated, affecting the performance of the electronic device.

[0021] The inventors have discovered through research that an imbalance in the etching rates of different elements in a silicon-containing organic dielectric layer is the main cause of the appearance of subtrench or uneven surface morphology. For example, if the etching rate of Si in a silicon-containing organic dielectric layer is faster than the etching rate of CH, uneven surface morphology appears at the bottom of the silicon-containing organic dielectric layer, and if the etching rate of Si is slower than the etching rate of CH, subtrench morphology appears at the bottom of the silicon-containing organic dielectric layer.

[0022] Based on this, the present application discloses an etching method for a silicon-containing organic dielectric layer, comprising the step of etching the silicon-containing organic dielectric layer by at least two alternating etching steps, further comprising the step of etching the silicon-containing organic dielectric layer by at least two alternating etching steps, wherein the etching gas used in at least one of the at least two alternating etching steps contains an oxygen-containing gas, and the etching gas used in at least one etching step contains an oxygen-containing gas and a fluorine-containing gas, thereby making the bottom of the trenches or via holes in the silicon-containing organic dielectric layer into a smooth shape.

[0023] As one selectable embodiment of the disclosure of this application, an embodiment of this application discloses a method for etching a silicon-containing organic dielectric layer, the etching method comprising etching the silicon-containing organic dielectric layer by at least two alternating etching steps, the at least two etching steps comprising a first etching step and a second etching step, wherein the etching gas used in the first etching step comprises at least an oxygen-containing gas, and the etching gas used in the second etching step comprises at least an oxygen-containing gas and a fluorine-containing gas.

[0024] In the embodiments of this application, the electronic device fabricated from a silicon-containing organic dielectric layer is applicable to fields such as wireless communication base stations, satellite navigation, and mobile communications, and the electronic device may be a power amplifier, rectifier, oscillator, phase-locked loop, controller, memory, etc.

[0025] As shown in Figure 2, the electronic device may include, for example, a substrate 101 and a silicon-containing organic dielectric layer 11 located on one side of the substrate 101. In some select embodiments, a metal layer 102 and an isolation layer 103 may be included between the substrate 101 and the silicon-containing organic dielectric layer 11.

[0026] Here, the substrate 101 may include a gallium arsenide (GaAs) substrate, a silicon substrate, a germanium substrate, or a silicon germanium substrate, the metal layer 102 may include an Au metal layer, the isolation layer 103 may include a silicon nitride layer, and the material of the silicon-containing organic dielectric layer 11 includes BCB.

[0027] In some embodiments of this application, when etching the silicon-containing organic dielectric layer 11, first, as shown in Figure 3, an anti-reflective layer 12 and a patterned photoresist layer 13 are sequentially formed on the surface of the silicon-containing organic dielectric layer 11 away from the substrate 101, and the material of the anti-reflective layer 12 may be silicon nitride or silicon oxynitride. Here, by exposing the entire surface of the photoresist layer using a mask plate having a pre-set mask pattern, the mask pattern can be transferred to the photoresist layer, and then the photoresist layer can be developed to form the patterned photoresist layer 13.

[0028] Next, as shown in Figure 4, the mask pattern is transferred to the anti-reflective layer 12 by etching the anti-reflective layer 12 using the patterned photoresist layer 13 as a mask. Here, the anti-reflective layer 12 can reduce or eliminate the standing wave effect of the photoresist layer 13 and improve the accuracy of transferring the mask pattern from the mask plate to the photoresist layer. Of course, in some embodiments of this application, the anti-reflective layer 12 may not be included and will not be described in detail here.

[0029] Subsequently, as shown in Figure 5, the silicon-containing organic dielectric layer 11 is etched in a first etching step using the patterned photoresist layer 13 as a mask, and the depth of the trench 110 is set to a first predetermined depth h1. Next, as shown in Figure 6, the silicon-containing organic dielectric layer 11 is etched in a second etching step, and the depth of the trench 110 is set to a second predetermined depth h2, where h2 is greater than h1. Next, as shown in Figure 7, the silicon-containing organic dielectric layer 11 is etched in a first etching step, and the depth of the trench 110 is set to a third predetermined depth h3, where h3 is greater than h2. Next, as shown in Figure 8, the silicon-containing organic dielectric layer 11 is etched in a second etching step, and the depth of the trench 110 is set to a fourth predetermined depth h4, where h4 is greater than h3. This process is repeated until the depth of the trench 110 reaches the required depth, forming the necessary trenches or via holes. In the embodiments of this application, a dry etching process, such as a plasma etching process, is used in at least one of the two etching steps for etching the silicon-containing organic dielectric layer 11.

[0030] In some embodiments, the anti-reflective layer 12 can be etched first, and then the silicon-containing organic dielectric layer 11 can be etched in the first etching step. Of course, this application is not limited thereto, and in some other embodiments, the silicon-containing organic dielectric layer 11 can be etched in the first etching step while the anti-reflective layer 12 can be etched simultaneously, but these will not be described in detail here.

[0031] In some embodiments of this application, the silicon-containing organic dielectric layer 11 can be etched first by a first etching step, and then by a second etching step. However, this application is not limited thereto, and in some other embodiments, the silicon-containing organic dielectric layer 11 can be etched first by a second etching step, and then by a first etching step, which will not be described in detail here.

[0032] In some embodiments of this application, the oxygen-containing gas includes at least one of O2, CO2, CO, and SO2, and the fluorine-containing gas includes SF6, CF4, C4F8, CHF3, and NF3. 、 It contains at least one of CH2F2 and C2F6. Furthermore, in some examples, the oxygen-containing gas contains O2 and the fluorine-containing gas contains SF6. Based on this, in some examples, the etching gas in the first etching step contains O2, and the etching gas in the second etching step contains O2 and SF6.

[0033] The etching gas used in the first etching step contains at least an oxygen-containing gas (e.g., O2), and the etching gas used in the first etching step basically does not contain fluorine, with a flow rate ratio of fluorine to oxygen elements being less than 0.01, or with a fluorine element content of 0. The etching gas used in the second etching step contains at least an oxygen-containing gas (e.g., O2) and a fluorine-containing gas (e.g., SF6), and the first and second etching steps are repeated alternately. By repeating the first and second etching steps alternately, for example, by intermittently introducing a fluorine-containing gas and adjusting the gas flow rate ratio of fluorine-containing gas and oxygen-containing gas in the process chamber, the ratio of fluorine and oxygen elements in the process chamber can be adjusted. This makes it possible to adjust the etching rate of different elements in the silicon-containing organic dielectric layer 11, thereby reducing sub-trenches and protrusions at the bottom of trenches or via holes etched in the silicon-containing organic dielectric layer 11. This makes the bottom of the trenches or via holes smoother and prevents excessive concentration of electric field stress at the bottom of the trenches or via holes, which can affect the performance of the electronic device.

[0034] In some embodiments of this application, in a process in which at least two etching steps are repeated alternately, the ratio range of fluorine and oxygen elements in the process chamber is greater than 0 and 15 or less, or the fluorine content is 0. This results in a smooth shape at the bottom of the trench or via hole. In some embodiments, the first etching step does not contain fluorine-containing gas, i.e., the fluorine content is 0, so in a process in which at least two etching steps are repeated alternately, the ratio range of fluorine and oxygen elements is 0 when the first etching step is performed. In some other embodiments, the first etching step may contain a small amount of fluorine-containing gas, for example, the ratio of fluorine to oxygen elements may be less than 0.01. In some embodiments, by setting the gas flow rate ratio range of SF6 and O2 to greater than 0 and 5 or less, or by setting the gas flow rate of SF6 to 0, the ratio range of fluorine and oxygen elements can be set to greater than 0 and 15 or less, or the fluorine content can be set to 0. Naturally, this application is not limited thereto, and in actual applications, the flow rate ratio range of the fluorine-containing gas and the oxygen-containing gas can be adjusted according to the components of the fluorine-containing gas and the oxygen-containing gas, which will not be explained in detail here.

[0035] In some embodiments, the etching gas used in the first etching step does not contain a fluorine-containing gas (e.g., SF6), or in other words, the gas flow rate of the fluorine-containing gas (e.g., SF6) used in the first etching step is understood to be 0. However, this application is not limited thereto, and in some other embodiments, the etching gas used in the first etching step may contain a fluorine-containing gas (e.g., SF6), but it is necessary to ensure that the gas flow rate of the fluorine-containing gas (e.g., SF6) in the etching gas used in the first etching step is smaller than the gas flow rate of the fluorine-containing gas (e.g., SF6) in the etching gas used in the second etching step. In other words, in a process in which at least two etching steps are repeated alternately, it is sufficient to ensure that the ratio range of fluorine and oxygen elements in the process chamber is greater than 0 and 15 or less, or that the fluorine element content is 0.

[0036] The principle for adjusting the etching rates of different elements in the silicon-containing organic dielectric layer 11 is explained below, using BCB material as an example. The molecular formula of BCB is C4H 12 In OSi2, the etching process of BCB involves etching of CH elements and Si elements. When F ions and F-containing radicals dissociated from a fluorine-containing gas (e.g., SF6) in a high-frequency electromagnetic field etch Si elements, the product is gaseous SiFx. When F ions and F-containing radicals etch CH elements, the products are gaseous CFx and HFx. When O ions and O-containing radicals dissociated from an oxygen-containing gas (e.g., O2) etch Si elements, the product is a non-volatile SiOx deposit that inhibits Si etching. When O ions and O-containing radicals etch CH elements, they produce volatile gaseous substances CO, CO2, and HO. In other words, the etching rate of Si by an oxygen-containing gas (e.g., O2) is slower than the etching rate of Si by a fluorine-containing gas (e.g., SF6).

[0037] From the molecular formula of BCB, it can be seen that the Si element content in BCB is relatively low, the CH element content is relatively high, and the formation rate of SiFx is faster than that of CFx and HFx. Therefore, when etching BCB with only a fluorine-containing gas such as SF6, or when the gas flow rate ratio of fluorine-containing gas (e.g., SF6) to oxygen-containing gas (e.g., O2) is greater than 5, the etching rate of Si element becomes faster than that of CH element, not only significantly slowing down the etching rate of the BCB material, but also causing an uneven morphology as shown in Figure 9 to appear at the bottom of the trench or via hole in the BCB. As a result, the electric field stress at the bottom of the trench or via hole becomes excessively concentrated, affecting the performance of the electronic device.

[0038] When etching BCB with oxygen-containing gas (e.g., O2) alone, or when the gas flow rate ratio of fluorine-containing gas (e.g., SF6) to oxygen-containing gas (e.g., O2) is greater than and close to 0, or when the gas flow rate of fluorine-containing gas (e.g., SF6) is 0, the etching rate of Si elements becomes slower than that of CH elements, resulting in the appearance of sub-trench morphology as shown in Figure 10 at the bottom of the trench or via hole in the BCB. As a result, the electric field stress at the bottom of the trench or via hole becomes excessively concentrated, affecting the performance of the electronic device.

[0039] When etching the BCB by alternating first and second etching steps, the ratio of fluorine and oxygen elements can be adjusted by alternating the first and second etching steps, for example by intermittently introducing a fluorine-containing gas (e.g., SF6), and adjusting the gas flow rate ratio of the fluorine-containing gas (e.g., SF6) and oxygen-containing gas (e.g., O2) in the process chamber. For example, by setting the flow rate ratio range of SF6 to O2 to greater than 0 and less than or equal to 15, or by setting the SF6 gas flow rate to 0, the ratio of fluorine and oxygen elements can be adjusted, thereby balancing the etching rate of Si and CH elements. This not only ensures that the etching rate of the BCB meets the requirements, but also allows the bottom of the trenches or via holes in the BCB to have a smooth shape as shown in Figure 11, thereby avoiding excessive concentration of electric field stress at the bottom of the trenches or via holes, which would affect the performance of the electronic device.

[0040] Alternatively, the etching rates of Si by oxygen and fluorine differ, and the etching rates of CH by oxygen and fluorine also differ. For example, the etching rate of Si by fluorine is faster than that of Si by oxygen, and the etching rate of CH by fluorine is slower than that of CH by oxygen. Therefore, by intermittently introducing a fluorine-containing gas (e.g., SF6) and adjusting the gas flow rate ratio of fluorine-containing gas (e.g., SF6) to oxygen-containing gas (e.g., O2) in the process chamber, the flow rate ratio of fluorine and oxygen can be adjusted, thereby adjusting the etching rates of Si and CH and balancing the etching rates of Si and CH.

[0041] Naturally, in some embodiments, the gas flow rate ratio of fluorine-containing gas (e.g., SF6) and oxygen-containing gas (e.g., O2) in the process chamber can be further adjusted by adjusting the gas flow rate and / or process time in the first etching step and / or second etching step, or the flow rate ratio of fluorine and oxygen elements in the process chamber can also be adjusted.

[0042] Furthermore, when etching BCB in the second etching step, the etching rates of Si and CH can be adjusted by adjusting the gas flow rate ratio of fluorine-containing gas (e.g., SF6) and oxygen-containing gas (e.g., O2) in the second etching step. However, as shown in Figure 12, a bowing shape appears on the sidewall of the trench or via hole, creating a risk of cross-connection or short circuit between adjacent trenches or via holes. By repeating the first and second etching steps alternately, the constant presence of F ions and F-containing radicals in the chamber can be effectively avoided, thereby preventing the appearance of the bowing shape on the sidewall of the trench or via hole.

[0043] In some embodiments of this application, the gas flow rate range of the oxygen-containing gas (e.g., O2) used in the first etching step is 5 sccm to 200 sccm, and / or the gas flow rate range of the oxygen-containing gas (e.g., O2) used in the second etching step is 5 sccm to 200 sccm, and the gas flow rate range of the fluorine-containing gas (e.g., SF6) is 5 sccm to 20 sccm.

[0044] In some embodiments of this application, the process time range used in the first etching step is 0.2 s to 8 s, and / or the process time range used in the second etching step is 0.2 s to 5 s. This is advantageous not only for controlling the etching gas but also for creating a smooth shape at the bottom of the trenches or via holes in the silicon-containing organic dielectric layer.

[0045] Furthermore, if the process time used in the first and second etching steps is less than 0.2 s, the gas supply will be below the shortest controllable time, which is unfavorable for gas control. If the process time used in the second etching step is longer than 5 s, the flow rate ratio of SF6 to O2 will be greater than 5, and an uneven surface will appear at the bottom of the trenches or via holes in the BCB. If the process time used in the first etching step is longer than 8 s, the flow rate ratio of SF6 to O2 will be greater than 0 and close to 0, or the gas flow rate of SF6 will be 0, and a sub-trench will appear at the bottom of the trenches or via holes in the BCB.

[0046] In some embodiments of this application, the chamber pressure range used in the first etching step is 2 mTorr to 30 mTorr, and / or the chamber pressure range used in the second etching step is 2 mTorr to 30 mTorr. Based on this, it is possible to avoid the chamber pressure being too high or too low and affecting the etching effect of the silicon-containing organic dielectric layer. In some embodiments, the chamber pressure used in the first etching step is the same as the chamber pressure used in the second etching step.

[0047] In some embodiments of this application, the upper RF power range used in the first etching step is 300W to 2500W, and the lower RF power range is 100W to 1200W, and / or the upper RF power range used in the second etching step is 300W to 2500W, and the lower RF power range is 100W to 1200W. In some embodiments, the upper RF power used in the first etching step is the same as the upper RF power used in the second etching step, and the lower RF power used in the first etching step is the same as the lower RF power used in the second etching step.

[0048] In some specific examples, the gas flow rate of the oxygen-containing gas (e.g., O2) used in the first etching step is 32 sccm, and during the process... The interval, 3s, chamber pressure Power , 4mTorr, upper RF power Power , 300W, lower RF power Power The power is 100W. The gas flow of the oxygen-containing gas (e.g., O2) used in the second etching step. Quantity The gas flow rate is 32 sccm, and it is a gas flow rate for fluorine-containing gases (e.g., SF6). Quantity , 8sccm, process time The interval , 2s, chamber pressure Power , 4mTorr, upper RF power Power , 300W, lower RF power Power It is 100W.

[0049] In some embodiments of this application, the etching gas used in the first etching step and the second etching step further comprises an inert gas, the inert gas comprising at least one of Ar, He, and Ne. In some embodiments, the etching gas used in the first etching step and the second etching step further comprises the inert gas Ar. In this case, the etching gas used in the first etching step comprises Ar and O2, and 2 The etching gases used in the etching step include Ar, O2, and SF6.

[0050] In a high-frequency electromagnetic field, Ar radicals and Ar ions dissociated from inert gases such as Ar act as physical collisions and do not participate in chemical reactions. This not only removes polymers generated during the etching process, but also improves the verticality of the side walls of the trenches or via holes formed by etching, preventing short circuits that can occur in signal transmission by conductors within the trenches or via holes due to insufficient verticality causing adjacent via holes to intersect and connect.

[0051] In some embodiments of this application, the gas flow rate range for the oxygen-containing gas (e.g., O2) used in the first etching step is 5 sccm to 200 sccm, the gas flow rate range for the inert gas such as Ar is 5 sccm to 200 sccm, the process time range is 0.2 s to 8 s, the chamber pressure range is 2 mTorr to 30 mTorr, the upper RF power range is 300 W to 2500 W, and the lower RF power range is 100 W to 1200 W. The gas flow rate range for the oxygen-containing gas (e.g., O2) used in the second etching step is 5 sccm to 200 sccm, the gas flow rate range for the fluorine-containing gas (e.g., SF6) is 5 sccm to 20 sccm, the gas flow rate range for the inert gas such as Ar is 5 sccm to 200 sccm, the process time range is 0.2 s to 5 s, the chamber pressure range is 2 mTorr to 30 mTorr, the upper RF power range is 300 W to 2500 W, and the lower RF power range is 100 W to 1200 W.

[0052] In some specific examples, the gas flow rate of the oxygen-containing gas (e.g., O2) used in the first etching step is 32 sccm, the gas flow rate of the inert gas such as Ar is 10 sccm, the process time is 3 s, the chamber pressure is 4 m Torr, the upper RF power is 300 W, and the lower RF power is 100 W. Quantity The flow rate of the fluorine-containing gas (e.g., SF6) is 32 sccm, the flow rate of the inert gas (e.g., Ar) is 8 sccm, the process time is 2 s, the chamber pressure is 4 m Torr, the upper RF power is 300 W, and the lower RF power is 100 W.

[0053] In some embodiments, during a process in which at least two etching steps are repeated alternately, the ratio range of fluorine elements to inert elements in the process chamber is greater than 0 and 60 or less, or the fluorine element content is 0. This results in a smoother, rounded corner shape at the bottom of the trenches or via holes. Similarly, the first etching step does not contain fluorine-containing gas, or the fluorine element content is extremely low, i.e., the ratio of fluorine elements to inert elements is less than 0.01, or the fluorine element content is 0. During a process in which at least two etching steps are repeated alternately, if the first etching step is performed, the ratio range of fluorine elements to inert elements is greater than 0 and 0.01 or less, or the fluorine element content is 0. In some embodiments, by setting the flow rate ratio range of fluorine-containing gas (e.g., SF6) to inert gas (e.g., Ar) to greater than 0 and 10 or less, or by setting the gas flow rate of fluorine-containing gas (e.g., SF6) to 0, the ratio range of fluorine elements to inert elements can be set to greater than 0 and 60 or less, or the fluorine element content can be set to 0.

[0054] In a process in which at least two etching steps are repeated alternately, the time-dependent curves of the gas flow rates of oxygen-containing gas (e.g., O2), fluorine-containing gas (e.g., SF6), and inert gas (e.g., Ar) are as shown in Figure 13. Here, V1 represents the gas flow rate of SF6, V2 represents the gas flow rate of Ar, V3 represents the gas flow rate of O2, T1 represents the process time of the second etching step, and T2 represents the process time of the first etching step. In a process in which at least two etching steps are repeated alternately, the time-dependent curves of the flow rate ratio between fluorine-containing gas (e.g., SF6) and inert gas (e.g., Ar), and the time-dependent curves of the flow rate ratio between fluorine-containing gas (e.g., SF6) and oxygen-containing gas (e.g., O2) are as shown in Figure 14. Here, during the process in which at least two etching steps are repeated alternately, the gas flow rate of the oxygen-containing gas (e.g., O2) is kept constant, the gas flow rate of the inert gas (e.g., Ar) is kept constant, and the gas flow rate change curve of the fluorine-containing gas (e.g., SF6) exhibits a pulsed waveform.

[0055] After stopping the introduction of gas into the process chamber, a certain amount of time is required for the gas in the process chamber to be consumed and become zero. Therefore, the flow rate ratio of fluorine-containing gas (e.g., SF6) to inert gas (e.g., Ar) and the flow rate ratio of fluorine-containing gas (e.g., SF6) to oxygen-containing gas (e.g., O2) change dynamically. The slope of the time-dependent curve of the flow rate ratio of fluorine-containing gas (e.g., SF6) to inert gas (e.g., Ar) is greater than 0 and within the range of 10 or less, or the gas flow rate of fluorine-containing gas (e.g., SF6) becomes 0. The slope of the time-dependent curve of the flow rate ratio of fluorine-containing gas (e.g., SF6) to oxygen-containing gas (e.g., O2) is greater than 0 and within the range of 5 or less, or the gas flow rate of fluorine-containing gas (e.g., SF6) becomes 0.

[0056] In some embodiments of this application, at least two etching steps include only a first etching step and a second etching step, that is, the silicon-containing organic dielectric layer 11 is etched only by the first etching step and the second etching step repeated alternately. However, this application is not limited thereto, and in some other embodiments, at least two etching steps may further include at least one third etching step, at least one third etching step located between the first etching step and the second etching step, or between the second etching step and the first etching step, wherein the flow rate of the etching gas used in the third etching step is smaller than the flow rate of the etching gas used in the first and second etching steps. Here, the flow rate of the etching gas in the third etching step may be zero, that is, no gas is introduced into the process chamber in the third etching step, or a vacuum step is performed in the process chamber in the third etching step.

[0057] As another optional embodiment of the disclosures of this application, the embodiments of this application further disclose semiconductor process apparatus, which includes, but is not limited to, inductively coupled plasma etching apparatus or capacitively coupled plasma etching apparatus.

[0058] In several selectable embodiments, taking an inductively coupled plasma etching apparatus as an example, as shown in Figure 15, the semiconductor process apparatus includes a process chamber 1, a gas supply assembly 2, an extraction assembly (not shown), an upper electrode assembly, a lower electrode assembly, and a control device (not shown), etc.

[0059] Here, the gas supply assembly 2 is used to introduce a gas, including process gas, into the process chamber 1. The control device is used to control the gas supply assembly 2 to start or stop the introduction of gas into the process chamber 1 by controlling the opening and closing of the electronic valve of the gas supply assembly 2.

[0060] The extraction assembly is used to draw gas from within the process chamber 1, and this gas includes by-product gases generated after the etching reaction. The control device may be used to control the extraction assembly to start or stop the draw of gas from within the process chamber 1 by controlling the opening and closing of the electronic valve of the extraction assembly. Furthermore, the control device may be used to control the magnitude of the chamber pressure in the process chamber 1 by controlling the opening of the electronic valve of the gas supply assembly 2 and the opening of the electronic valve of the extraction assembly.

[0061] The upper electrode assembly includes an upper RF power supply 31, a first matcher 32 electrically connected to the upper RF power supply 31, and an RF coil 33 electrically connected to the first matcher 32. Here, the upper RF power supply 31 may also be electrically connected to the RF coil 33 in the process chamber 1 via the first matcher 32 and is used to apply RF power to the RF coil 33. This causes the RF coil 33 to couple the RF power to the process chamber 1 through the dielectric window 5, ionizing the gas in the process chamber 1 into plasma 6. A control device may be used to control the magnitude of the RF power applied from the upper RF power supply 31 to the RF coil 33 via the first matcher 32.

[0062] The lower electrode assembly includes a lower RF power supply 41, a second matcher 42 electrically connected to the lower RF power supply 41, and a carrier device electrically connected to the second matcher 42, including an electrostatic chuck. Here, the lower RF power supply 41 is electrically connected to the carrier device 43 via the second matcher 42 and is used to apply bias power to the carrier device 43 to accelerate the plasma. The carrier device 43 is used to carry the device to be manufactured 7 and to heat or cool the device to be manufactured 7.

[0063] The technical features of the above embodiments can be combined in any way, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, these combinations of technical features should be considered to be within the scope described herein, provided that no inconsistencies exist.

[0064] The above examples illustrate only a few embodiments of this specification, and although their descriptions are relatively detailed and specific, they should not be understood as limiting the scope of the claims of this application. Those skilled in the art will point out that several modifications and improvements can be made without departing from the concepts of this specification, and all of these fall within the scope of protection of this specification. Therefore, the scope of protection of the patents of this specification should be based on the appended claims.

Claims

1. A method for etching a silicon-containing organic dielectric layer, The process includes etching the silicon-containing organic dielectric layer by at least two alternating etching steps, The at least two etching steps include a first etching step and a second etching step, wherein the etching gas used in the first etching step includes at least an oxygen-containing gas, and the etching gas used in the second etching step includes at least an oxygen-containing gas and a fluorine-containing gas. A method for etching a silicon-containing organic dielectric layer, characterized in that, in the first etching step, the ratio of fluorine element to oxygen element is less than 0.01, or the content of fluorine element is 0.

2. The etching method according to claim 1, characterized in that, in a process in which at least two etching steps are repeated alternately, the ratio range of fluorine element to oxygen element is greater than 0 and 15 or less, or the content of the fluorine element is 0.

3. The gas flow rate range of the oxygen-containing gas used in the first etching step is 5 sccm to 200 sccm. The etching method according to claim 1, characterized in that the gas flow rate range of the oxygen-containing gas used in the second etching step is 5 sccm to 200 sccm, and the gas flow rate range of the fluorine-containing gas used in the second etching step is 5 sccm to 20 sccm.

4. A material of the silicon-containing organic dielectric layer comprises BCB, and the oxygen-containing gas is O ２ , CO ２ , CO and SO ２ comprises at least one selected from the group consisting of the above, and the fluorine-containing gas is SF ６ , CF ４ , C ４ F ８ , CHF ３ , NF ３ , CH ２ F ２ and C ２ F ６ comprises at least one selected from the group consisting of the above. The etching method according to claim 1, characterized in that.

5. The etching method according to claim 1, wherein the etching gas used in the first etching step and the second etching step further comprises an inert gas, and the inert gas comprises at least one of Ar, He, and Ne.

6. The etching method according to claim 5, characterized in that the gas flow rate range of the inert gas used in the first etching step is 5 sccm to 200 sccm, and the gas flow rate range of the inert gas used in the second etching step is 5 sccm to 200 sccm.

7. In a process in which at least two etching steps are repeated alternately, the ratio range of fluorine element to inert element is greater than 0 and 60 or less, or the content of the fluorine element is 0, The etching method according to claim 5, characterized in that, in the first etching step, the ratio of fluorine element to inert element is less than 0.

01.

8. The etching method according to claim 5, characterized in that, during a process in which at least two etching steps are alternately repeated, the gas flow rate of the oxygen-containing gas is kept constant, the gas flow rate of the inert gas is kept constant, and the gas flow rate change curve of the fluorine-containing gas shows a pulse waveform.

9. The process time range used in the first etching step is 0.2 s to 8 s, and / or The etching method according to claim 1, characterized in that the process time range used in the second etching step is 0.2 s to 5 s.

10. The chamber pressure range used in the first etching step is 2 mTorr to 30 mTorr, and / or The etching method according to claim 1, characterized in that the chamber pressure range used in the second etching step is 2 mTorr to 30 mTorr.

11. The etching method according to claim 1, wherein the at least two etching steps further include at least one third etching step, the at least one third etching step is performed between the first etching step and the second etching step, and the flow rate of the etching gas used in the third etching step is smaller than the flow rate of the etching gas used in the first etching step and the second etching step.

12. A semiconductor process apparatus comprising a process chamber, a gas supply assembly, an upper electrode assembly, a lower electrode assembly, and a control device, wherein the control device comprises at least one memory and at least one processor, the memory storing a computer program, and the processor executing the computer program to realize the etching method for a silicon-containing organic dielectric layer according to any one of claims 1 to 11.

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