Semiconductor equipment

Abstract

To provide a semiconductor device that reduces a local temperature rise caused by a void of a joint material.SOLUTION: A semiconductor device comprises a conductive member, a semiconductor element, a joint part and a lead frame. The semiconductor element includes a switching element. The semiconductor element is held via a first joint material by a conductive member. The joint part is provided on a top surface of the semiconductor element. The joint part is electrically connected to an electrode except a gate electrode of a switching element. The lead frame is joined to the joint part via a second joint material. The joint part and the second joint material are provided in a region including a central part on the top surface of the semiconductor element.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 describes a semiconductor device in which the back surface of a switching element is bonded to a metal member, and the front surface of the switching element is bonded to an intermediate terminal. A semiconductor device wired by an intermediate terminal formed of a plate-shaped metal achieves a small area and is excellent in current capacity characteristics. Therefore, semiconductor devices having such a configuration are widely used in various power control devices such as control devices for air conditioners.

Prior Art Literature

Patent Literature

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] A semiconductor element such as a switching element and a metal member are fixed to each other by a bonding material. When bonding a semiconductor element to a metal member, voids are generated in the bonding material with a certain probability. When voids exist in the bonding material, cooling of the semiconductor element directly above the voids is inhibited, causing a local temperature rise in the semiconductor element.

[0005] In order to solve the above problem, the present disclosure provides a semiconductor device that reduces local temperature rise caused by voids in a bonding material.

Means for Solving the Problem

[0006] The semiconductor device according to this disclosure comprises a conductive member, a semiconductor element, a junction, and leads. The semiconductor element includes a switching element. The semiconductor element is held by the conductive member via a first junction. The junction is provided on the upper surface of the semiconductor element. The junction is electrically connected to electrodes other than the gate electrode of the switching element. The leads are bonded to the junction via a second junction. The junction and the second junction are provided in a region including the central part of the upper surface of the semiconductor element, the aspect ratio of the semiconductor element in a plan view is 1.5 or more and 2.5 or less, and the area of ​​the semiconductor element is 150 mm². 2 Below The semiconductor element includes, in a plan view, an element formation portion corresponding to the region where the switching element is formed, and a plurality of signal pads provided in the region other than the element formation portion on the upper surface of the semiconductor element for transmitting or receiving signals to control the switching element or signals to protect the switching element, wherein the plurality of signal pads are provided along one side of the semiconductor element in a plan view, and a part of the element formation portion is provided along one side of the semiconductor element in a plan view, alongside the plurality of signal pads. ru. [Effects of the Invention]

[0007] This disclosure provides a semiconductor device that reduces localized temperature rise caused by voids in the bonding material.

[0008] The purpose, features, aspects, and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing the configuration of the semiconductor device in Embodiment 1. [Figure 2] This is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 1. [Figure 3] This is a plan view showing the configuration of the upper surface of the switching semiconductor element in Embodiment 1. [Figure 4] This is a bottom view showing the configuration of the lower surface of the switching semiconductor element in Embodiment 1. [Figure 5] This is a plan view showing the configuration of the upper surface of the freewheeling semiconductor element in Embodiment 1. [Figure 6] This is a bottom view showing the configuration of the lower surface of the reflux semiconductor element in Embodiment 1. [Figure 7] This is a flowchart showing a method for manufacturing a semiconductor device. [Figure 8]It is a cross-sectional view showing the configuration after completion of the semiconductor device in Embodiment 1. [Figure 9] It is a plan view showing the configuration of the semiconductor device in Embodiment 2. [Figure 10] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 2. [Figure 11] It is a plan view showing the configuration of the top surface of the switching semiconductor element in Embodiment 2. [Figure 12] It is a plan view showing the configuration of the semiconductor device in Embodiment 3. [Figure 13] It is a plan view showing the configuration of the semiconductor device in Embodiment 4. [Figure 14] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 4. [Figure 15] It is a plan view showing the configuration of the semiconductor device in Embodiment 5. [Figure 16] It is a plan view showing the configuration of the top surface of the switching semiconductor element in Embodiment 5. MODE FOR CARRYING OUT THE INVENTION

[0010] <Embodiment 1> Figure 1 is a plan view showing the configuration of a semiconductor device 101 according to Embodiment 1. Figure 2 is a cross-sectional view showing the configuration of the semiconductor device 101 according to Embodiment 1, which corresponds to the cross-section taken along line A-A shown in Figure 1.

[0011] The semiconductor device 101 includes an insulating material 3, a front-side circuit pattern 4, a back-side circuit pattern 5, a first bonding material 2, a switching semiconductor element 6, a freewheeling semiconductor element 7, a second bonding material 1, a wiring frame 8, a signal terminal 10, a wire 9, and a sealing material 11. In Figure 1, the sealing material 11 is omitted from illustration to make the internal structure of the semiconductor device 101 easier to understand.

[0012] The insulating material 3 is made of resin or ceramic. The insulating resin mainly consists of, for example, epoxy resin. The ceramic mainly consists of, for example, Al2O3, Si3N4, or AlN. From the viewpoint of heat dissipation, the insulating material 3 is preferably made of a material with high thermal conductivity and is also preferably a thin member. On the other hand, considering the assurance of insulating properties and structural strength in the manufacturing process, the thickness of the insulating material 3 is preferably 100 μm or more.

[0013] The front-side circuit pattern 4 is provided on the surface of the insulating material 3. The front-side circuit pattern 4 is a conductive member and is made of a metal such as aluminum, aluminum alloy, copper, or copper alloy. The front-side circuit pattern 4 holds the switching semiconductor element 6 and the freewheeling semiconductor element 7 via the first bonding material 2. The front-side circuit pattern 4 has the function of not only an electrical circuit but also of diffusing the heat generated by the switching semiconductor element 6 and the freewheeling semiconductor element 7. The front-side circuit pattern 4 has sufficient thickness to adequately dissipate heat in its planar direction. Depending on the planar layout, the thickness of the front-side circuit pattern 4 is preferably 0.4 mm or more. To improve adhesion with the sealing material 11, the front-side circuit pattern 4 preferably has irregularities such as dimples and slits as needed.

[0014] The back-side circuit pattern 5 is provided on the back surface of the insulating material 3. The back-side circuit pattern 5 is made of a metal such as aluminum, aluminum alloy, copper, or copper alloy.

[0015] The first bonding material 2 bonds the front circuit pattern 4 to the lower surface of the switching semiconductor element 6. The first bonding material 2 also bonds the front circuit pattern 4 to the lower surface of the freewheeling semiconductor element 7. The first bonding material 2 is, for example, lead-free solder mainly composed of Sn. The first bonding material 2 may also be a sintered material mainly composed of Ag or Cu.

[0016] The switching semiconductor element 6 is held in the front circuit pattern 4 via the first bonding material 2. The switching semiconductor element 6 includes a switching element (not shown). The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching semiconductor element 6 is formed from a semiconductor such as Si, or from a so-called wide-bandgap semiconductor such as SiC, GaN, gallium oxide, or diamond.

[0017] The freewheeling semiconductor element 7 is held in the front-side circuit pattern 4 via the first bonding material 2. The freewheeling semiconductor element 7 includes a diode element. The diode element may be an SBD (Schottky Barrier Diode) or a rectifier diode having a PN junction. The freewheeling semiconductor element 7 is formed, for example, from a semiconductor such as Si, or from a so-called wide-bandgap semiconductor such as SiC, GaN, gallium oxide, or diamond.

[0018] The wiring frame 8 is a lead and is the wiring through which the main current flows inside the semiconductor device 101. The wiring frame 8 is bonded to the switching semiconductor element 6 and the freewheeling semiconductor element 7 via the second bonding material 1. A portion of the wiring frame 8 functions as a main terminal (not shown) that can be connected to a circuit provided outside the semiconductor device 101. In Embodiment 1, the wiring frame 8 is a metal plate or a component made from such a metal plate. The wiring frame 8 is made of a metal such as aluminum, aluminum alloy, copper, or copper alloy. The thickness of the wiring frame 8 depends on the specified current of the semiconductor device 101 or the width of the main terminal. To suppress self-heating of the main terminal when current is applied, the thickness of the wiring frame 8 is preferably 0.5 mm or more and 2.0 mm or less. A metal wire may be used as a lead instead of the wiring frame 8.

[0019] The second bonding material 1 joins the switching semiconductor element 6 and the wiring frame 8. The second bonding material 1 also joins the freewheeling semiconductor element 7 and the wiring frame 8. The second bonding material 1 is, for example, lead-free solder mainly composed of Sn. The second bonding material 1 may also be a sintered material mainly composed of Ag or Cu.

[0020] One end of the signal terminal 10 functions as a terminal that can be connected to a circuit provided outside the semiconductor device 101. The signal terminal 10 is made of copper, a copper alloy, or the like. For weight reduction, the signal terminal 10 may be made of aluminum or an aluminum alloy. The thickness of the signal terminal 10 is, for example, 0.2 mm or more and 1.0 mm or less.

[0021] Wire 9 connects each of the five signal pads 6C located on the upper surface of the switching semiconductor element 6 to the signal terminal 10. The detailed configuration of the signal pads 6C will be described later. Wire 9 is made of aluminum, aluminum alloy, copper, copper alloy, etc. The diameter of wire 9 is, for example, 100 μm to 400 μm.

[0022] The sealing material 11 seals the insulating material 3, the front circuit pattern 4, the first bonding material 2, the switching semiconductor element 6, the freewheeling semiconductor element 7, the second bonding material 1, a portion of the wiring frame 8, the wires 9, and a portion of the signal terminals 10. The main terminal of the wiring frame 8, one end of the signal terminals 10, and the back circuit pattern 5 are exposed from the sealing material 11. The sealing material 11 is formed of, for example, epoxy resin. The coefficient of thermal expansion of the sealing material 11 is preferably 18 ppm / °C or more and 24 ppm / °C or less. This suppresses delamination between the sealing material 11 and the front circuit pattern 4 and prevents crack formation in the first bonding material 2. When the switching semiconductor element 6 is driven, the switching semiconductor element 6 generates heat, causing the temperature of the sealing material 11 to rise. To prevent the coefficient of thermal expansion of the sealing material 11 from fluctuating due to this temperature rise, the glass transition temperature Tg is preferably 175°C or higher.

[0023] Figure 3 is a plan view showing the configuration of the top surface of the switching semiconductor element 6 in Embodiment 1. Figure 4 is a bottom view showing the configuration of the bottom surface of the switching semiconductor element 6 in Embodiment 1.

[0024] The switching semiconductor element 6 includes an element formation portion 6A, a junction portion 6B, five signal pads 6C, and a plurality of gate lines (not shown) on its upper surface. The switching semiconductor element 6 also includes a junction portion 6D on its lower surface.

[0025] The element formation section 6A corresponds to the region where switching elements are formed in a plan view. This region includes the central part (not shown) of the upper surface of the switching semiconductor element 6. The central part includes the center of its upper surface. In Embodiment 1, a plurality of switching elements, each having a channel, are formed in the element formation section 6A.

[0026] The junction 6B is provided in a region including the central part of the upper surface of the switching semiconductor element 6. For example, in a plan view, the junction 6B is provided in a region including the center of the switching semiconductor element 6. The junction 6B is joined to the wiring frame 8 by a second bonding material 1. The second bonding material 1 is also provided in a region including the central part in a plan view.

[0027] The junction 6B is located inside the element formation section 6A, but the size relationship between the junction 6B and the element formation section 6A is not limited to this. The size of the junction 6B may be the same as the size of the element formation section 6A. The junction 6B is formed of a highly wettable metal film such as Ni, Au, Cu, or Ag. The junction 6B is electrically connected to electrodes other than the gate electrode of the switching element. If the switching element is an IGBT, the junction 6B is electrically connected to, for example, the emitter electrode. In other words, the junction 6B itself functions as the emitter electrode.

[0028] Five signal pads 6C are provided on the upper surface of the switching semiconductor element 6. Each signal pad 6C is provided in an area on the upper surface of the switching semiconductor element 6 other than the element formation area 6A. In Embodiment 1, the five signal pads 6C are arranged in a row along one side of the outer shape of the switching semiconductor element 6 in a plan view. Each signal pad 6C is formed of a metal film. Each signal pad 6C is a pad for transmitting or receiving signals to control the switching element or signals to protect the switching element. These signals are, for example, a gate signal (G), an emitter signal (E), a current sense signal (Cs), and a temperature sense signal (K,A). In other words, one of the five signal pads 6C is a gate pad. This gate pad is electrically connected to the gate electrode of each switching element via a plurality of gate lines (not shown). The number of signal pads 6C is not limited to five; it may be four or fewer, or six or more.

[0029] Multiple gate lines are arranged to cross the upper surface of the switching semiconductor element 6. Each gate line is arranged so as not to pass through the center of the switching semiconductor element 6. For example, the gate lines are arranged so as not to pass through the center of the switching semiconductor element 6. Each gate line is electrically connected to the gate electrode of each switching element.

[0030] The junction 6D is provided on the lower surface of the switching semiconductor element 6. In Embodiment 1, the junction 6D is provided over the entire lower surface of the switching semiconductor element 6. The junction 6D is formed of a metal film with good wettability, such as Ni, Au, Cu, or Ag. The junction 6D is electrically connected to electrodes other than the gate electrode of the switching element that are not connected to the junction 6B. If the switching element is an IGBT, the junction 6D is electrically connected to, for example, the collector electrode. In other words, the junction 6D itself functions as the collector electrode. The junction 6D is bonded to the front circuit pattern 4 by the first bonding material 2.

[0031] When the switching element is an IGBT, a main current corresponding to the gate signal applied to the gate electrode flows between the collector electrode formed at junction 6D and the emitter electrode formed at junction 6B.

[0032] Figure 5 is a plan view showing the configuration of the upper surface of the reflux semiconductor element 7 in Embodiment 1. Figure 6 is a bottom view showing the configuration of the lower surface of the reflux semiconductor element 7 in Embodiment 1.

[0033] The recirculating semiconductor element 7 includes an element formation portion 7A and a junction portion 7B on its upper surface. The recirculating semiconductor element 7 also includes a junction portion 7D on its lower surface.

[0034] The element formation section 7A corresponds to the region where the diode element is formed in a plan view.

[0035] The junction 7B is provided on the upper surface of the recirculating semiconductor element 7. The junction 7B is joined to the wiring frame 8 by the second bonding material 1. The junction 7B is provided inside the element formation section 7A, but the size relationship between the junction 7B and the element formation section 7A is not limited to this. The size of the junction 7B may be the same as the size of the element formation section 7A. The junction 7B is formed of a metal film with good wettability such as Ni, Au, Cu, or Ag.

[0036] The junction 7D is provided on the lower surface of the freewheeling semiconductor element 7. In Embodiment 1, the junction 7D is provided over the entire lower surface of the freewheeling semiconductor element 7. The junction 7D is formed of a metal film with good wettability, such as Ni, Au, Cu, or Ag. The junction 7D is bonded to the front circuit pattern 4 by the first bonding material 2.

[0037] The junctions 7B and 7D of the recirculating semiconductor element 7 may be formed from the same material as the junctions 6B and 6D of the switching semiconductor element 6.

[0038] Figure 7 is a flowchart showing the manufacturing method of the semiconductor device 101.

[0039] In step S1, an insulating material 3 is prepared, which includes the front circuit pattern 4 and the back circuit pattern 5.

[0040] In step S2, the switching semiconductor element 6 and the freewheeling semiconductor element 7 are mounted on the front circuit pattern 4 via the first bonding material 2. In step S2, the first bonding material 2 is first placed between the junction 6D of the switching semiconductor element 6 and the front circuit pattern 4, and between the junction 7D of the freewheeling semiconductor element 7 and the front circuit pattern 4. The switching semiconductor element 6, the freewheeling semiconductor element 7, the first bonding material 2, and the front circuit pattern 4 are bonded together under predetermined atmosphere, temperature, and pressure. As a result, the junctions 6D, 7D and the front circuit pattern 4 are bonded together by the first bonding material 2.

[0041] In step S3, the switching semiconductor element 6 and the freewheeling semiconductor element 7 are joined to the wiring frame 8 via the second bonding material 1. In step S3, the second bonding material 1 is first placed between the joint portion 6B of the switching semiconductor element 6 and the wiring frame 8, and between the joint portion 7B of the freewheeling semiconductor element 7 and the wiring frame 8. The switching semiconductor element 6, the freewheeling semiconductor element 7, the second bonding material 1, and the wiring frame 8 are joined under predetermined atmosphere, temperature, and pressure. As a result, the joint portions 6B, 7B and the wiring frame 8 are joined by the second bonding material 1. Furthermore, in step S3, the connection portion (not shown) between the wiring frame 8 and the front-side circuit pattern 4 may also be joined with the second bonding material 1. Alternatively, the switching semiconductor element 6 and the wiring frame 8 may be joined by ultrasonic (US) bonding without using the second bonding material 1.

[0042] In step S4, each of the five signal pads 6C is connected to the signal terminal 10 by a wire 9.

[0043] In step S5, the insulating material 3, the front circuit pattern 4, the first bonding material 2, the switching semiconductor element 6, the freewheeling semiconductor element 7, the second bonding material 1, a portion of the wiring frame 8, the wires 9, and a portion of the signal terminals 10 are sealed with the sealing material 11.

[0044] The semiconductor device 101 is completed by the above steps S1 to S5. In steps S2 and S3, the joining of junctions 6D and 7D to the front circuit pattern 4, and the joining of junctions 6B and 7B to the wiring frame 8 can be performed simultaneously. Performing the joining process simultaneously improves productivity.

[0045] Figure 8 is a cross-sectional view showing the completed configuration of the semiconductor device 101 in Embodiment 1. Figure 8 corresponds to the cross-section of line AA shown in Figure 1.

[0046] The semiconductor device 101 contains a void 2A inside the first bonding material 2 of the switching semiconductor element 6. Hereinafter, it is assumed that the void 2A is located, for example, below the central part of the switching semiconductor element 6. The void 2A is formed, for example, when the switching semiconductor element 6 is bonded to the front circuit pattern 4 via the first bonding material 2. Factors contributing to the formation of the void 2A include, for example, degassing from the bonding portion 6B or the front circuit pattern 4, and air trapping when the switching semiconductor element 6 is placed on the first bonding material 2.

[0047] The switching semiconductor element 6 generates heat when it is in operation, i.e., when power is applied. The amount of temperature rise due to this heat generation is not uniform across the plane of the switching semiconductor element 6. The temperature rise in the central part of the switching semiconductor element 6 is greater than the temperature rise in the outer periphery. Voids 2A also contribute to the temperature rise. That is, when voids 2A are formed in the first bonding material 2, the thermal conductivity of the voids 2A is almost zero. Therefore, assuming the void position in Figure 8, a localized temperature rise occurs in the central part directly above the voids 2A. In other words, the temperature rise in the central part is doubled.

[0048] In the semiconductor device 101 of this embodiment, a bonding portion 6B is provided in the region directly above the void 2A, that is, the region including the central part. Furthermore, a second bonding material 1 is provided on the bonding portion 6B. Therefore, even if the void 2A is located below the central part of the switching semiconductor element 6, the heat generated in the central part is absorbed and dispersed by the second bonding material 1. As a result, a localized temperature rise of the switching semiconductor element 6 is suppressed.

[0049] In summary, the semiconductor device 101 in Embodiment 1 includes a front circuit pattern 4, a switching semiconductor element 6, a junction 6B, and a wiring frame 8. The switching semiconductor element 6 includes a switching element. The switching semiconductor element 6 is held in the front circuit pattern 4 via a first bonding material 2. The junction 6B is provided on the upper surface of the switching semiconductor element 6. The junction 6B is electrically connected to electrodes of the switching element other than the gate electrode. The wiring frame 8 is bonded to the junction 6B via a second bonding material 1. The junction 6B and the second bonding material 1 are provided in a region including the central part of the upper surface of the switching semiconductor element 6.

[0050] Such a semiconductor device 101 reduces localized temperature rise caused by voids 2A formed in the first bonding material 2.

[0051] The switching semiconductor element 6 and the freewheeling semiconductor element 7 have upper temperature limits set to ensure the reliability of the semiconductor device 101, including its lifespan. Since voids 2A cause localized temperature increases, it is necessary to manage voids 2A so that the temperatures of the switching semiconductor element 6 and the freewheeling semiconductor element 7 do not exceed their preset upper temperatures. In particular, since the heat generated by the switching semiconductor element 6 is greater than that of the freewheeling semiconductor element 7, stricter void 2A management is required for the switching semiconductor element 6 than for the freewheeling semiconductor element 7. For example, the specifications for voids 2A generated in the switching semiconductor element 6 are stricter than those for voids 2A generated in the freewheeling semiconductor element 7. Therefore, the deterioration of productivity due to voids 2A, i.e., the increase in the defect rate, is more likely to be a problem for the switching semiconductor element 6.

[0052] In the semiconductor device 101 of this embodiment, the joint 6B and the second jointing material 1 are provided directly above the void 2A. Heat generated in the central part of the switching semiconductor element 6 is transferred to and dispersed by the second jointing material 1 and the wiring frame 8. As a result, localized temperature rise of the switching semiconductor element 6 is suppressed. The semiconductor device 101 in Embodiment 1 expands the specified tolerance range for void 2A, that is, it enables a relaxation of the standard. The semiconductor device 101 facilitates the management of void 2A and improves reliability and productivity.

[0053] Void 2A can be formed in either the switching semiconductor element 6 or the freewheeling semiconductor element 7. However, since the heat generated by the switching semiconductor element 6 is greater than that generated by the freewheeling semiconductor element 7, the above effect is particularly pronounced in the configuration in which void 2A is formed in the first bonding material 2 of the switching semiconductor element 6.

[0054] In the semiconductor device 101, there is only one junction 6B provided on the upper surface of the switching semiconductor element 6. This configuration simplifies the supply of the second bonding material 1 during the manufacturing process, thereby improving manufacturability.

[0055] Furthermore, the gate line is positioned so as not to pass through the central part of the switching semiconductor element 6. With this configuration, a junction 6B is formed in the central part of the switching semiconductor element 6 where heat is concentrated. As a result, heat dissipation is improved and temperature rise is suppressed.

[0056] Because the switching semiconductor element 6 and the freewheeling semiconductor element 7 are formed from wide-bandgap semiconductors, the voltage withstand capability of the switching element and diode element is improved. The allowable current density is also high, enabling miniaturization of the switching element and diode element. The use of these miniaturized switching element and diode element enables miniaturization of the semiconductor device 101.

[0057] (Modification 1 of Embodiment 1) The area of ​​the first bonding material 2 is 50% or more of the area of ​​the second bonding material 1. This configuration improves the balance between the front-side bonding portion 6B and the back-side bonding portion 6D of the switching semiconductor element 6. As a result, the convex warping in the front direction that may occur in the switching semiconductor element 6 is reduced. This reduction in convex warping prevents voids 2A generated within the first bonding material 2 from converging in the central part of the switching semiconductor element 6.

[0058] (Modification 2 of Embodiment 1) The aspect ratio of the switching semiconductor element 6 in a plan view is between 1.5 and 2.5. With this configuration, the void 2A in the center of the switching semiconductor element 6 is more easily released to the outside from the longer side of the switching semiconductor element 6.

[0059] In addition to the aspect ratio mentioned above, the area of ​​the switching semiconductor element 6 is 150 mm². 2 The following applies. In this configuration, the distance from the center of the switching semiconductor element 6 to its longer side becomes shorter. Voids 2A generated in the center are more easily released to the outside from their longer sides. On the other hand, in addition to the above aspect ratio, the area of ​​the switching semiconductor element 6 is 150 mm². 2The above dimensions may also be used. In the case of this size, it is necessary to arrange multiple gate lines in order to uniformly apply voltage to the gate, but by applying the above aspect ratio in addition to the configuration of this embodiment, the effect of voids can be mitigated.

[0060] (Modification 3 of Embodiment 1) The thickness of the switching semiconductor element 6 is 150 μm or less. In this configuration, the bending rigidity of the switching semiconductor element 6 decreases, making it prone to warping. Even if a void 2A occurs in the center due to this warping, a localized temperature rise is unlikely to occur because the joint 6B and the second joint material 1 are provided directly above the void 2A.

[0061] (Modification 4 of Embodiment 1) In Embodiment 1, the switching semiconductor element 6 and the freewheeling semiconductor element 7 are separate elements, but they may be an integrated element formed on the same semiconductor substrate. For example, the switching semiconductor element 6 may include an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a diode element are formed on a single semiconductor substrate. When the switching element is an RC-IGBT, the number of elements is reduced, and manufacturability is improved.

[0062] <Embodiment 2> Figure 9 is a plan view showing the configuration of the semiconductor device 102 in Embodiment 2. Figure 10 is a cross-sectional view showing the configuration of the semiconductor device 102 in Embodiment 2. Figure 10 corresponds to the cross-section of line BB shown in Figure 9.

[0063] The semiconductor device 102 includes a switching semiconductor element 16 instead of the switching semiconductor element 6 shown in Embodiment 1.

[0064] Figure 11 is a plan view showing the configuration of the upper surface of the switching semiconductor element 16 in Embodiment 2.

[0065] The switching semiconductor element 16 includes a first element formation portion 16A, two second element formation portions 26A, a first junction portion 16B, two second junction portions 26B, five signal pads 16C, and a plurality of gate lines (not shown) on its upper surface. The first element formation portion 16A and the two second element formation portions 26A correspond to the configuration in which the element formation portion 6A of Embodiment 1 is divided into three regions. Similarly, the first junction portion 16B and the two second junction portions 26B correspond to the configuration in which the junction portion 6B of Embodiment 1 is divided into three regions. The configuration of the lower surface of the switching semiconductor element 16 is the same as the configuration of the switching semiconductor element 6 of Embodiment 1.

[0066] The first element formation section 16A and the two second element formation sections 26A correspond to the regions where switching elements are formed in a plan view. The first element formation section 16A includes the central portion (not shown) on the upper surface of the switching semiconductor element 6. The two second element formation sections 26A are arranged on both sides of the first element formation section 16A.

[0067] The first junction 16B is provided in a region including the central part of the switching semiconductor element 16. Preferably, the center of the first junction 16B is positioned so that it overlaps with the central part of the switching semiconductor element 16. The two second junctions 26B are provided in a region other than the first junction 16B. Here, the two second junctions 26B are positioned on both sides of the first junction 16B.

[0068] The first joint 16B and the second joint 26B are joined to the wiring frame 8 by the second joining material 1. The second joining material 1 is also provided in a region including the central part when viewed in plan.

[0069] The configuration of signal pad 16C is the same as that of signal pad 6C in Embodiment 1.

[0070] Multiple gate lines are provided so as to cross the upper surface of the switching semiconductor element 16. However, each gate line is provided so as not to pass through the central part of the switching semiconductor element 16. Each gate line is located in a region other than the first junction 16B.

[0071] One possible measure to improve the current capacity of the switching semiconductor element 16 is to increase its area. However, as the area increases, the balance of gate voltage application within the plane of the switching semiconductor element 16 deteriorates, and the short-circuit withstand capability decreases. If the gate line is arranged to cross the center, the balance of gate voltage application may improve, but the junction 6B and the second junction material 1 cannot be placed in the center. Therefore, if a void 2A is formed in the center, a localized temperature rise occurs in that center.

[0072] In the semiconductor device 102, the gate line is not located in the center of the switching semiconductor element 16, but since multiple gate lines are arranged in areas other than the center, the balance of gate voltage application is improved. In addition, a first junction 16B and a first bonding material 2 are provided in the center of the switching semiconductor element 16. Therefore, even when the area of ​​the switching semiconductor element 16 is enlarged, the semiconductor device 102 prevents deterioration of the balance of gate voltage application and suppresses temperature rise due to void 2A formed below the center.

[0073] The number of divisions of the joint 6B is not limited to three. It is preferable to divide it into three or more odd numbers as needed. In other words, it is preferable that the semiconductor device 102 includes a first joint 16B provided in the central part and an even number of second joints 26B provided around it.

[0074] (Modification 1 of Embodiment 2) The aspect ratio of the switching semiconductor element 16 in a plan view is between 1.5 and 2.5. With this configuration, the void 2A in the central part is more easily released to the outside from the longer side of the switching semiconductor element 16.

[0075] Furthermore, the area of ​​the switching semiconductor element 16 is 150 mm². 2 This concludes the explanation. The current capacity is increased by increasing the area of ​​the switching semiconductor element 16. Since the first junction 16B and the second bonding material 1 are located in the center, the temperature rise due to the void 2A is reduced. Furthermore, since multiple gate lines are arranged, the uniformity of the gate voltage is improved.

[0076] <Embodiment 3> Figure 12 is a plan view showing the configuration of the semiconductor device 103 in Embodiment 3.

[0077] The semiconductor device 103 includes a switching semiconductor element 26 and a switching semiconductor element 36. The switching semiconductor elements 26 and 36 have the same configuration. The switching semiconductor elements 26 and 36 are connected in parallel to each other. The number of switching semiconductor elements connected in parallel is not limited to two. Three or more switching semiconductor elements may be connected in parallel as needed.

[0078] The emitter signal (E), current sense signal (Cs), and temperature sense signal (K,A) are extracted only from the switching semiconductor element 26. The gate signal (G) is extracted from both the switching semiconductor element 26 and the switching semiconductor element 36. To improve the protection function, the emitter signal (E), current sense signal (Cs), and temperature sense signal (K,A) may be extracted from both the switching semiconductor element 26 and the switching semiconductor element 36.

[0079] By using multiple small elements instead of one large element, it is possible to increase the current capacity while improving the balance of the applied gate voltage. In addition, voids 2A are less likely to occur in the second bonding material 1. Furthermore, since the bonding portion 6B is unified, the occurrence of voids 2A is further reduced, and the defect rate is improved.

[0080] <Embodiment 4> Figure 13 is a plan view showing the configuration of the semiconductor device 104 in Embodiment 4. Figure 14 is a cross-sectional view showing the configuration of the semiconductor device 104 in Embodiment 4. Figure 14 corresponds to the cross-section of line CC shown in Figure 13.

[0081] The wiring frame 8 includes a through hole 8A on the joint surface with the joint portion 6B. The through hole 8A is positioned so as not to overlap with the central portion of the switching semiconductor element 6 in a plan view.

[0082] In the joining process between the wiring frame 8 and the joint 6B, if the amount of second joining material 1 supplied between the wiring frame 8 and the joint 6B is excessive, there is a risk that the excess second joining material 1 may overflow outside the joint 6B. The through hole 8A guides the excess second joining material 1 between the wiring frame 8 and the joint 6B into the hole, thereby preventing the second joining material 1 from overflowing outside the joint 6B.

[0083] However, if a highly fluid bonding material such as solder is used for the second bonding material 1, the shape of the second bonding material 1 directly below the through hole 8A will not be stable. For example, if the amount of solder supplied is small, the thickness of the second bonding material 1 will be thinner directly below the through hole 8A than around the through hole 8A due to the effects of surface tension, etc. In that case, the effect of reducing the temperature rise due to the void 2A will be smaller directly below the through hole 8A.

[0084] In the semiconductor device 104, the through-hole 8A is positioned so as not to overlap with the central part of the switching semiconductor element 6. Therefore, the thickness of the second bonding material 1 is ensured even in the central part of the switching semiconductor element 6. The second bonding material 1 suppresses the temperature rise caused by the void 2A that forms in the central part of the switching semiconductor element 6.

[0085] <Embodiment 5> Figure 15 is a plan view showing the configuration of the semiconductor device 105 in Embodiment 5.

[0086] The semiconductor device 105 includes a switching semiconductor element 46 instead of the switching semiconductor element 6 shown in Embodiment 1.

[0087] Figure 16 is a plan view showing the configuration of the upper surface of the switching semiconductor element 46 in Embodiment 5.

[0088] The switching semiconductor element 46 includes an element formation portion 46A, a junction portion 46B, four signal pads 46C, and a plurality of gate lines (not shown) on its upper surface.

[0089] The element formation section 46A corresponds to the region where the switching element is formed in a plan view. A portion of the element formation section 46A is provided on one side of the switching semiconductor element 46, alongside the four signal pads 46C, in a plan view.

[0090] The joint 46B is the same as the joint 6B in Embodiment 1.

[0091] The four signal pads 46C are located on the upper surface of the switching semiconductor element 46 in an area other than the element formation portion 46A. In a plan view, the four signal pads 46C are located along one side of the switching semiconductor element 46. Each signal pad 46C is a pad for transmitting or receiving signals to control the switching element or to protect the switching element. These signals are a gate signal (G), a current sense signal (Cs), and a temperature sense signal (K,A).

[0092] Of the four signal pads 46C, an element formation section 46A extends from the center between two adjacent signal pads. Along one side, the signal pads 46C and the element formation section 46A are arranged side by side.

[0093] The element formation section 46A functions as a signal pad for the emitter signal (E) on one side of the switching semiconductor element 46. Therefore, the wire 9 connects the signal terminal 10 and the element formation section 46A on one side of the switching semiconductor element 46.

[0094] Compared to the element formation section 6A shown in Embodiment 1, the area of ​​the element formation section 46A is enlarged. Therefore, even if the areas of the switching semiconductor elements 6 and 46 are the same, the loss of the semiconductor device 105 is improved compared to the loss of the semiconductor device 101 in Embodiment 1. A highly efficient semiconductor device 105 is realized.

[0095] This disclosure allows for the free combination of each embodiment, and enables the modification or omission of each embodiment as appropriate.

[0096] The various aspects of this disclosure are summarized below as an appendix.

[0097] (Note 1) Conductive material and A semiconductor element including a switching element, which is held in the conductive member via a first bonding material, A junction provided on the upper surface of the semiconductor element and electrically connected to an electrode other than the gate electrode of the switching element, The joint portion comprises a lead that is joined to the joint portion via a second joining material, A semiconductor device wherein the aforementioned joint and the second joint material are provided in a region including the central part of the upper surface of the semiconductor element.

[0098] (Note 2) The semiconductor device according to Appendix 1, further comprising the conductive member, the first bonding material, the semiconductor element, the bonding portion, the second bonding material, and a sealing material for sealing a portion of the lead.

[0099] (Note 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the number of junctions provided on the upper surface of the semiconductor element is only one.

[0100] (Note 4) The semiconductor element further comprises a plurality of gate lines provided so as to cross the upper surface of the semiconductor element and electrically connected to the gate electrode of the switching element, The semiconductor device according to any one of the appendices 1 to 3, wherein the plurality of gate lines are arranged so as not to pass through the central portion.

[0101] (Note 5) The semiconductor element further comprises a plurality of gate lines provided so as to cross the upper surface of the semiconductor element and electrically connected to the gate electrode of the switching element, The joint includes a first joint provided in the region including the central portion, and a plurality of second joints provided in regions other than the first joint. The semiconductor device according to any one of the appendices 1 to 3, wherein the plurality of gate lines are arranged so as not to pass through the central portion.

[0102] (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein the area of ​​the first bonding material is 50% or more of the area of ​​the second bonding material.

[0103] (Note 7) The aspect ratio of the semiconductor element in a plan view is 1.5 or more and 2.5 or less, and the area of ​​the semiconductor element is 150 mm². 2 The following semiconductor device as described in any of the appendices 1 to 6.

[0104] (Note 8) The aspect ratio of the semiconductor element in a plan view is 1.5 or more and 2.5 or less, and the area of ​​the semiconductor element is 150 mm². 2 The semiconductor device described in any of the appendices 1 to 6.

[0105] (Note 9) A semiconductor device according to any one of the appendices 1 to 8, wherein the thickness of the semiconductor element is 150 μm or less.

[0106] (Note 10) The aforementioned semiconductor device is In a plan view, the element forming section corresponds to the region where the switching element is formed, The semiconductor element includes a plurality of signal pads provided in a region other than the element forming portion on the upper surface of the semiconductor element for transmitting or receiving signals for controlling the switching element or signals for protecting the switching element, The plurality of signal pads are arranged along one side of the semiconductor element in a plan view. A semiconductor device according to any one of the appendices 1 to 9, wherein a part of the element forming portion is provided in a plan view on one side of the semiconductor element, alongside the plurality of signal pads.

[0107] (Note 11) The lead includes a through hole in the joint surface with the joint, The semiconductor device according to any one of the appendices 1 to 10, wherein the through hole is provided so as not to overlap with the central portion in a plan view.

[0108] (Note 12) The semiconductor device is a semiconductor device according to any one of the appendices 1 to 11, wherein the switching element includes an RC-IGBT.

[0109] (Note 13) The semiconductor device is formed of a wide-bandgap semiconductor, as described in any of Appendix 1 to Appendix 12.

[0110] (Note 14) The wide-bandgap semiconductor is the semiconductor device described in Appendix 13, comprising silicon carbide, gallium nitride-based material, or diamond.

[0111] (Note 15) The first bonding material includes voids, The void is located below the central portion, and is a semiconductor device according to any one of the appendices 1 to 14.

[0112] (Note 16) Conductive material and A plurality of semiconductor elements, each including a switching element, are held in the conductive member via a first bonding material, A junction is provided on the upper surface of each of the plurality of semiconductor elements and is electrically connected to an electrode other than the gate electrode of the switching element, The joint portion comprises a lead that is joined to the joint portion via a second joining material, The aforementioned plurality of semiconductor elements are connected in parallel to one another. A semiconductor device in which the aforementioned joint and the second joint material are provided in a region including the central portion of the upper surface of each of the plurality of semiconductor elements. [Explanation of Symbols]

[0113] 1 Second bonding material, 2 First bonding material, 2A Void, 3 Insulating material, 4 Front side circuit pattern, 5 Back side circuit pattern, 6 Switching semiconductor element, 6A Element formation area, 6B Bonding area, 6C Signal pad, 6D Bonding area, 7 Backflow semiconductor element, 7A Element formation area, 7B Bonding area, 7D Bonding area, 8 Wiring frame, 8A Through hole, 9 Wire, 10 Signal terminal, 11 Encapsulation material, 16 Switching semiconductor element, 16A First element formation area, 16B First Bonding area, 16C Signal pad, 26 Switching semiconductor element, 26A Second element formation area, 26B Second Bonding area, 36 Switching semiconductor element, 46 Switching semiconductor element, 46A Element formation area, 46B Bonding area, 46C Signal pad, 101-105 Semiconductor device.

Claims

1. Conductive material and A semiconductor element including a switching element, which is held in the conductive member via a first bonding material, A junction provided on the upper surface of the semiconductor element and electrically connected to an electrode other than the gate electrode of the switching element, The joint portion comprises a lead that is joined to the joint portion via a second joining material, The aforementioned joint and the second joint material are provided in a region including the central part of the upper surface of the semiconductor element. The aspect ratio of the semiconductor element in a plan view is 1.5 or more and 2.5 or less, and the area of ​​the semiconductor element is 150 mm². ２ The following: The aforementioned semiconductor device is In a plan view, the element forming section corresponds to the region where the switching element is formed, The semiconductor element includes a plurality of signal pads provided in a region other than the element forming portion on the upper surface of the semiconductor element for transmitting or receiving signals for controlling the switching element or signals for protecting the switching element, The plurality of signal pads are arranged along one side of the semiconductor element in a plan view. A semiconductor device in which a part of the element forming portion is provided in a plan view on one side of the semiconductor element, alongside the plurality of signal pads.

2. The semiconductor device according to claim 1, further comprising the conductive member, the first bonding material, the semiconductor element, the bonding portion, the second bonding material, and a sealing material for sealing a portion of the lead.

3. The semiconductor device according to claim 1, wherein the number of junctions provided on the upper surface of the semiconductor element is only one.

4. The semiconductor element further comprises a plurality of gate lines provided so as to cross the upper surface of the semiconductor element and electrically connected to the gate electrode of the switching element, The semiconductor device according to claim 1, wherein the plurality of gate lines are arranged so as not to pass through the central portion.

5. The semiconductor element further comprises a plurality of gate lines provided so as to cross the upper surface of the semiconductor element and electrically connected to the gate electrode of the switching element, The joint includes a first joint provided in the region including the central portion, and a plurality of second joints provided in regions other than the first joint. The semiconductor device according to claim 1, wherein the plurality of gate lines are arranged so as not to pass through the central portion.

6. The semiconductor device according to claim 1, wherein the area of ​​the first bonding material is 50% or more of the area of ​​the second bonding material.

7. The semiconductor device according to claim 1, wherein the thickness of the semiconductor element is 150 μm or less.

8. The lead includes a through hole in the joint surface with the joint, The semiconductor device according to claim 1, wherein the through hole is provided so as not to overlap with the central portion in a plan view.

9. The semiconductor device according to claim 1, wherein the semiconductor element includes an RC-IGBT as the switching element.

10. The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide-bandgap semiconductor.

11. The semiconductor device according to claim 10, wherein the wide-bandgap semiconductor includes silicon carbide, gallium nitride-based material, or diamond.

12. The first bonding material includes voids, The semiconductor device according to claim 1, wherein the void may be located below the central portion.

13. Conductive material and A plurality of semiconductor elements, each including a switching element, are held in the conductive member via a first bonding material, A junction is provided on the upper surface of each of the plurality of semiconductor elements and is electrically connected to an electrode other than the gate electrode of the switching element, The joint portion comprises a lead that is joined to the joint portion via a second joining material, The aforementioned plurality of semiconductor elements are connected in parallel to one another. The aforementioned joint and the second joint material are provided in a region including the central portion of the upper surface of each of the plurality of semiconductor elements. Each of the aforementioned plurality of semiconductor elements has an aspect ratio of 1.5 or more and 2.5 or less in a plan view, and an area of ​​150 mm². ２ The following: Each semiconductor element, in a plan view, has an element formation portion corresponding to the region where the switching element is formed, Each of the above semiconductor elements includes a plurality of signal pads provided in a region other than the element formation portion on the upper surface of the above semiconductor element for transmitting or receiving signals for controlling the switching element or for protecting the switching element, The plurality of signal pads are provided along one side of each of the semiconductor elements in a plan view. A semiconductor device in which a part of the element forming portion is provided in a plan view on one side of each of the semiconductor elements, alongside the plurality of signal pads.

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