Image sensor and method for manufacturing an image sensor

Abstract

To provide an image sensor with an improved junction structure, and a manufacturing method for the same.SOLUTION: An image sensor 100 includes: a first layer 110 including a first semiconductor substrate 111 including a pixel part PX, and a first wiring layer 115; a second layer 120 including a second semiconductor substrate 121 where a plurality of transistors for performing a global shutter operation are formed, and a second wiring layer 125; a plurality of first junction structures 150 where a first bonding metal 116 exposed on one surface of the first wiring layer and a second bonding metal 126 exposed on one surface of the second wiring layer are in contact with each other to join the first layer and the second layer; a third layer 130 including a third semiconductor substrate 131 where a logic circuit is formed, and a third wiring layer 135; and a plurality of second junction structures 160 where a junction veer 127 penetrating the second semiconductor substrate in contact with a second wire 122 and a third bonding metal 136 are in contact with each other to join the second layer and the third layer.SELECTED DRAWING: Figure 2

Description

[[Technical Field]]

[0001] The present invention relates to an image sensor and a method for manufacturing an image sensor. [[Background Art]]

[0002] An image sensor is a semiconductor-based sensor that receives light and generates electrical signals, and includes a pixel array having a plurality of unit pixels, a circuit for driving the pixel array to generate an image, and the like. The plurality of unit pixels include a photodiode that generates electric charge in response to external light, and a pixel circuit that converts the electric charge generated by the photodiode into an electrical signal. Image sensors are widely applied to smartphones, tablet PCs, laptop computers, TVs, automobiles, and the like, in addition to cameras for capturing still images and moving images. Recently, research has been conducted on methods of arranging a plurality of elements to improve the performance of image sensors. [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] Japanese Unexamined Patent Publication No. 2017-98533 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] A problem to be solved by the present invention is to provide an image sensor having a stacked structure of a first layer where a pixel portion is formed, a second layer where a circuit for realizing a global shutter operation is formed, and a third layer where a logic circuit is formed, the image sensor having an improved bonding structure. [[Means for Solving the Problem]]

[0005] An image sensor according to one aspect of the present invention includes a first semiconductor substrate including a pixel portion in which a plurality of unit pixels are arranged, and a first layer including a first wiring layer laminated on the first semiconductor substrate, a second semiconductor substrate on which a plurality of transistors for realizing global shutter operation are formed, and a second layer including a second wiring layer laminated on the second semiconductor substrate, the second layer being bonded to the first layer such that the first wiring layer and the second wiring layer face each other in a first direction, and a first bonding metal exposed on one surface of the first wiring layer and a second bonding metal exposed on one surface of the second wiring layer facing each other The invention is characterized by comprising a plurality of first bonding structures that join the first layer and the second layer by bringing them into contact with each other, a third semiconductor substrate on which logic circuits are formed, and a third wiring layer laminated on the third semiconductor substrate, wherein the third layer is bonded to the second layer such that the second semiconductor substrate and the third wiring layer face each other in a first direction, and a plurality of second bonding structures that join the second layer and the third layer by bringing into contact a bonding via that contacts a second wiring contained in the second wiring layer and penetrates the second semiconductor substrate and a third bonding metal exposed on one surface of the third wiring layer.

[0006] An image sensor according to one embodiment of the present invention includes a first semiconductor substrate including a pixel portion in which a plurality of unit pixels are arranged, and a first layer including a first wiring layer laminated on the first semiconductor substrate; a second semiconductor substrate on which a predetermined circuit is formed, and a second layer including a second wiring layer laminated on the second semiconductor substrate, which is bonded to the first layer such that the first wiring layer and the second wiring layer face each other in a first direction; a third semiconductor substrate on which a predetermined circuit is formed, and a third layer including a third wiring layer laminated on the third semiconductor substrate, which is bonded to the second layer by bringing a third bonding metal exposed on one surface of the third wiring layer into contact with a bonding via that penetrates the second semiconductor substrate in a first direction, wherein the bonding via may include an upper via region that contacts a second wiring included in the second wiring layer and has a first width in a second direction perpendicular to the first direction, and a lower via region that contacts the third bonding metal and has a second width greater than the first width in the second direction.

[0007] An image sensor according to another aspect of the present invention is characterized in that a first layer, a second layer, and a third layer sequentially bonded in a first direction each include a semiconductor substrate and a wiring layer laminated on the semiconductor substrate in the first direction, and are divided into a plurality of regions in a second and third direction perpendicular to the first direction, the plurality of regions including: a first region in which the first layer includes a first semiconductor substrate on which pixel portions are formed and the second layer includes a second semiconductor substrate on which predetermined circuits are formed; a second region in which the first layer and the second layer are bonded by a first bonding structure and the second layer and the third layer are bonded by a second bonding structure; and a third region including at least one first through-via extending from one exposed surface of the first semiconductor substrate and connected to a first wiring included in the first wiring layer included in the first layer, and a second through-via extending from one exposed surface of the third semiconductor substrate included in the third layer and connected to a third wiring included in the third wiring layer included in the third layer.

[0008] A method for manufacturing an image sensor according to one aspect of the present invention is characterized by comprising the steps of: forming a first layer including a first semiconductor substrate having a pixel portion in which a plurality of unit pixels are arranged, and a first wiring layer laminated on the first semiconductor substrate; forming a second layer including a second semiconductor substrate on which a plurality of transistors for realizing global shutter operation are formed, and a second wiring layer laminated on the second semiconductor substrate; forming a first bonding metal exposed on one surface of the first wiring layer and a second bonding metal exposed on one surface of the second wiring layer; joining the first bonding metal and the second bonding metal to form a first bonding structure; forming bonding vias that contact wiring included in the second wiring layer and penetrate the second semiconductor substrate; forming a third layer including a third semiconductor substrate on which a logic circuit is formed, and a third wiring layer laminated on the third semiconductor substrate; forming a third bonding metal exposed on one surface of the third wiring layer; and joining the bonding vias and the third bonding metal to form a second bonding structure. [Effects of the Invention]

[0009] The image sensor according to the present invention is composed of a stacked structure of a first layer, a second layer, and a third layer, and the second and third layers are joined by a bonding structure in which bonding vias and bonding metal made of copper are in direct contact. This makes it possible to reduce noise in the image sensor and improve the bonding structure, and further improve the integration density of the image sensor. [Brief explanation of the drawing]

[0010] [Figure 1] This is a simplified block diagram showing an image sensor according to one embodiment of the present invention. [Figure 2] This is a simplified cross-sectional view showing an image sensor according to one embodiment of the present invention. [Figure 3] This is a circuit diagram illustrating the circuitry included in an image sensor according to one embodiment of the present invention. [Figure 4]This is a circuit diagram illustrating the circuitry included in an image sensor according to one embodiment of the present invention. [Figure 5] This diagram illustrates the effect of an image sensor based on one embodiment of the present invention. [Figure 6] This diagram illustrates the effect of an image sensor based on one embodiment of the present invention. [Figure 7] This is a simplified cross-sectional view showing an image sensor according to one embodiment of the present invention. [Figure 8a] This is a diagram illustrating the first junction structure included in an image sensor according to one embodiment of the present invention. [Figure 8b] This is a diagram illustrating the first junction structure included in an image sensor according to one embodiment of the present invention. [Figure 9] This figure illustrates a second junction structure included in an image sensor according to one embodiment of the present invention. [Figure 10] This figure illustrates a second junction structure included in an image sensor according to one embodiment of the present invention. [Figure 11a] This is a cross-sectional view illustrating the structure of an input / output region included in an image sensor according to one embodiment of the present invention. [Figure 11b] This is a cross-sectional view illustrating the structure of an input / output region included in an image sensor according to one embodiment of the present invention. [Figure 11c] This is a cross-sectional view illustrating the structure of an input / output region included in an image sensor according to one embodiment of the present invention. [Figure 12a] This is a cross-sectional view illustrating the structure of an input / output region included in an image sensor according to one embodiment of the present invention. [Figure 12b] This is a cross-sectional view illustrating the structure of an input / output region included in an image sensor according to one embodiment of the present invention. [Figure 12c] This is a cross-sectional view illustrating the structure of an input / output region included in an image sensor according to one embodiment of the present invention. [Figure 13]It is a top view for explaining the structure of a barrier region included in an image sensor according to an embodiment of the present invention. [Figure 14] It is a cross-sectional view for explaining the structure of a barrier region included in an image sensor according to an embodiment of the present invention. [Figure 15] It is a flowchart for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16a] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16b] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16c] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16d] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16e] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 17] It is a diagram schematically illustrating an electronic device including an image sensor according to an embodiment of the present invention. [Figure 18] It is a diagram schematically illustrating an electronic device including an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a block diagram schematically illustrating an image sensor according to an embodiment of the present invention.

[0013] Referring to FIG. 1, an image sensor 1 according to an embodiment of the present invention includes a pixel array 10, a logic circuit 20, and the like.

[0014] The pixel array 10 includes a plurality of unit pixels PX arranged in an array along a plurality of rows and a plurality of columns. Each unit pixel PX includes at least one photoelectric conversion element that generates an electric charge in response to light, and a pixel circuit that generates a pixel signal corresponding to the charge generated by the photoelectric conversion element.

[0015] Photoelectric conversion elements include photodiodes formed from semiconductor materials and / or organic photodiodes formed from organic materials. In one embodiment, each unit pixel PX includes two or more photoelectric conversion elements, and the two or more photoelectric conversion elements in one unit pixel PX receive light of different colors and generate an electric charge. In one embodiment of the present invention, each of a plurality of unit pixels PX includes a photodiode that receives light and generates an electric charge. However, this is only one embodiment and is not limited thereto.

[0016] Depending on the embodiment, the pixel circuit includes a transfer transistor, a drive transistor, a selection transistor, and a reset transistor. When each unit pixel PX has one photoelectric conversion element, each unit pixel PX includes a pixel circuit for processing the charge generated by the photoelectric conversion element. As an example, each of the multiple unit pixels PX included in the image sensor 1 according to one embodiment of the present invention includes a photodiode. In this case, the pixel circuit corresponding to each unit pixel PX includes a transfer transistor, a drive transistor, a selection transistor, and a reset transistor.

[0017] However, this is merely one embodiment and is not limited thereto. As an example, a plurality of unit pixels PX included in an image sensor 1 according to one embodiment of the present invention share a floating diffusion region in a predetermined unit, thereby allowing at least a portion of the photoelectric conversion element to share a portion of the drive transistor, selection transistor, and reset transistor.

[0018] The logic circuit 20 includes circuits for controlling the pixel array 10. For example, the logic circuit 20 includes a row driver 21, a readout circuit 22, a column driver 23, and control logic 24.

[0019] The row driver 21 drives the pixel array 10 row by row. For example, the row driver 21 generates transfer control signals to control the transfer transistors of the pixel circuit, reset control signals to control the reset transistors, and selection control signals to control the selection transistors, and inputs them to the pixel array 10 row by row.

[0020] The readout circuit 22 includes a Correlated Double Sampler (CDS), an Analog-to-Digital Converter (ADC), and the like. The Correlated Double Sampler is connected via unit pixels PX and column lines. The Correlated Double Sampler performs correlated double sampling by receiving pixel signals from unit pixels PX connected to row lines selected by the row line selection signal of the row driver 21. The pixel signals are received via column lines. The Analog-to-Digital Converter converts the pixel signals detected by the Correlated Double Sampler into digital pixel signals and transmits them to the column driver 23.

[0021] The column driver 23 includes a latch or buffer circuit and an amplifier circuit for temporarily storing the digital pixel signal, and processes the digital pixel signal received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 are controlled by control logic 24. The control logic 24 includes a timing controller for controlling the operating timing of the row driver 21, the readout circuit 22, and the column driver 23.

[0022] Unit pixels PX located at the same position horizontally share the same column line. For example, unit pixels PX located at the same position vertically are simultaneously selected by the row driver 21 and output a pixel signal via the column line. In one embodiment, the readout circuit 22 simultaneously acquires pixel signals from the unit pixels PX selected by the row driver 21 via the column line. The pixel signal includes a reset voltage and a pixel voltage, the pixel voltage being a voltage in which the charge generated from each unit pixel PX in response to light is reflected in the reset voltage. However, the image sensor may include other configurations and may be driven in various ways, although it is not limited to the configuration described with reference to Figure 1.

[0023] Figure 2 is a simplified cross-sectional view showing an image sensor according to one embodiment of the present invention.

[0024] Referring to Figure 2, an image sensor 100 according to one embodiment of the present invention includes a first layer 110, a second layer 120, and a third layer 130. The first layer 110 and the second layer 120 are connected by a first bonding structure 150, and the second layer 120 and the third layer 130 are connected by a second bonding structure 160.

[0025] Figure 2 shows one first joint structure 150 and one second joint structure 160, but this is only one embodiment and is not limited to this; multiple first joint structures 150 and second joint structures 160 can each be formed.

[0026] The first layer 110 includes a first semiconductor substrate 111 containing a pixel portion PX in which a plurality of unit pixels are arranged, and a first wiring layer 115 stacked on the first semiconductor substrate 111.

[0027] The pixel section PX includes a photodiode PD that converts light incident from the outside into an electrical signal, and the gate VTG of a transfer transistor included in the pixel circuit. As an example, the gate of the transfer transistor has a vertical structure in which at least a portion of the region is embedded in the first semiconductor substrate 111. However, this is only one embodiment and is not limited thereto.

[0028] The first wiring layer 115 includes a transistor 118 formed in a region adjacent to the first semiconductor substrate 111. For example, the transistor 118 formed in the first wiring layer 115 is a transfer transistor. On the other hand, the first wiring layer 115 includes a plurality of first wirings 112. However, the structure of the first wiring layer 115 shown in Figure 2 is only one embodiment and is not limited thereto.

[0029] The second layer 120 includes a second semiconductor substrate 121 on which a predetermined circuit is formed, and a second wiring layer 125 stacked on the second semiconductor substrate 121. For example, the predetermined circuit formed on the second semiconductor substrate 121 is a circuit that includes a plurality of transistors 128 for realizing global shutter operation.

[0030] Multiple transistors 128 formed on the second semiconductor substrate 121, together with multiple capacitors 129 included in the second wiring layer 125, realize global shutter operation. For example, the multiple transistors 128 and multiple capacitors 129 operate to expose all pixels on the image sensor 100 to light simultaneously and perform a readout operation row by row. Meanwhile, the second wiring layer 125 includes multiple second wirings (122, 123).

[0031] The second layer 120 is connected to the first layer 110 by the first bonding structure 150, and the first wiring layer 115 and the second wiring layer 125 face each other in a first direction (e.g., the Z direction) perpendicular to the upper surface of the second layer 120.

[0032] The third layer 130 includes a third semiconductor substrate 131 on which a predetermined circuit is formed, and a third wiring layer 135 stacked on the third semiconductor substrate 131. For example, the predetermined circuit formed on the third semiconductor substrate 131 is the logic circuit of the image sensor 100. The predetermined circuit formed on the third semiconductor substrate 131 includes a plurality of transistors 138, which embody the logic circuit 20 of the image sensor 1 shown in Figure 1. On the other hand, the third wiring layer 135 includes a plurality of third wirings 132.

[0033] The third layer 130 is connected to the second layer 120 by the second bonding structure 160, and the second semiconductor substrate 121 and the third wiring layer 135 face each other in the first direction.

[0034] Referring to the first and second bonding structures 150 and 160 shown in Figure 2, each of the first wiring layer 115, the second wiring layer 125, and the third wiring layer 135 extends in a second direction (e.g., the X direction) perpendicular to the first direction and includes bonding metal exposed on one surface of each wiring layer (115, 125, 135). For example, one surface of the first wiring layer 115 is exposed with first bonding metal 116, one surface of the second wiring layer 125 is exposed with second bonding metal 126, and one surface of the third wiring layer 135 is exposed with third bonding metal 136.

[0035] The first bonding metal 116, the second bonding metal 126, and the third bonding metal 136 are each connected to a portion of a plurality of wires (112, 122, 132) located inside the wiring layers (115, 125, 135). For example, the first bonding metal 116 is connected to the wire located at the bottom of the first wire 112 contained in the first wiring layer 115, the second bonding metal 126 is connected to the wire located at the top of the second upper wire 122 contained in the second wiring layer 125, and the third bonding metal 136 is connected to the wire located at the top of the third wire 132 contained in the third wiring layer 135.

[0036] On the other hand, the multiple wirings (112, 122, 132) are made of copper (Cu), and a barrier metal 101 is formed between the multiple wirings (112, 122, 132) and the wiring layers (115, 125, 135). However, this is only one embodiment and is not limited thereto.

[0037] In an image sensor 100 according to one embodiment of the present invention, the first bonding metal 116, the second bonding metal 126, and the third bonding metal 136 are each formed by a process separate from the process of forming the first wiring layer 115, the second wiring layer 125, and the third wiring layer 135. As a result, each of the regions 180 surrounding the first bonding metal 116, the second bonding metal 126, and the third bonding metal 136 is formed by a process separate from the wiring layers (115, 125, 135). However, this is merely one embodiment and is not limited thereto.

[0038] In an image sensor 100 according to one embodiment of the present invention, a plurality of first bonding structures 150 bond a first layer 110 and a second layer 120 by bringing a first bonding metal 116 and a second bonding metal 126 into contact with each other. In this case, the first bonding metal 116 and the second bonding metal 126 are made of Cu. That is, the plurality of first bonding structures 150 are bonding structures consisting of Cu-Cu bonding.

[0039] On the other hand, the second bonding structure 160 bonds the second layer 120 and the third layer 130 by bringing bonding vias 127 and third bonding metal 136, which penetrate the second semiconductor substrate 121, into contact with each other. In this case, the bonding vias 127 and third bonding metal 136 are made of Cu. That is, multiple second bonding structures 160 are also bonding structures made of Cu-Cu bonding, and the bonding vias 127 and third bonding metal 136 are arranged to overlap in the first direction.

[0040] The junction via 127 is separated from the second semiconductor substrate 121 by the spacer layer 170. On the other hand, the junction via 127 penetrates the second semiconductor substrate 121 and connects to the second lower wiring 123 included in the second wiring layer 125. For example, the second lower wiring 123 is a wiring that is formed before the multiple capacitors 129.

[0041] The manufacturing process for the multiple capacitors 129 includes a step of forming a dielectric film. The step of forming the dielectric film to improve the leakage characteristics of the multiple capacitors 129 is performed at a relatively high temperature. When forming the dielectric film at a high temperature, the second lower wiring 123, which is formed before the capacitors, is made of tungsten W.

[0042] As a result, the second lower wiring 123 is made of a different material from the first wiring 112, the second upper wiring 122, and the third wiring 132. However, this is only one embodiment and is not limited thereto. For example, the second lower wiring 123 may be made of copper (Cu). Tungsten has a relatively high resistivity and low reflectivity compared to other metals, such as copper (Cu). Therefore, when the second lower wiring 123 is made of tungsten, the characteristics of the image sensor 100 may be reduced compared to when it is made of copper.

[0043] Figures 3 and 4 are circuit diagrams illustrating the circuitry included in an image sensor according to one embodiment of the present invention.

[0044] Each circuit (100a, 100b) shown in Figures 3 and 4 includes circuits formed on the first layer 110 and the second layer 120 included in the image sensor 100 shown in Figure 2, as well as the first bonding structure 150.

[0045] The circuits formed in the first layer 110 and the second layer 120 of the image sensor 100 include a photodiode PD and a plurality of semiconductor elements for processing the charge generated by the photodiode PD. As an example, the first layer 110 and the second layer 120 are formed with a pixel circuit for converting light into an electrical signal using the photodiode PD, and a global shutter circuit for causing the pixel circuit to operate in a global shutter manner.

[0046] In an image sensor 100 according to one embodiment of the present invention, the transistors included in each circuit (100a, 100b) are formed on a semiconductor substrate (111, 121), and the wiring included in each circuit (100a, 100b) is formed within a wiring layer (115, 125) and corresponds to the first wiring 112 and the second wiring (122, 123).

[0047] Referring to Figures 3 and 4, each circuit (100a, 100b) includes a photodiode PD, a transfer transistor TX, a reset transistor RX, drive transistors (DX1, DX2), and a selection transistor SX. A floating diffusion region FD is formed between the electrode of the transfer transistor TX and the gate electrode of the first drive transistor DX1, and a switch element SW is connected between the floating diffusion region FD and the reset transistor RX to dynamically adjust the conversion gain of the pixel circuit. Each gate electrode of the transistors included in each circuit (100a, 100b) is connected to a drive signal line.

[0048] The photodiode PD generates and stores an electric charge in proportion to the amount of light incident from the outside. The transfer transistor TX is connected to the photodiode PD and transfers the charge stored in the photodiode PD to the floating diffusion region FD.

[0049] The reset transistor RX periodically resets the charge accumulated in the floating diffusion region FD. For example, when the switch element SW is turned on, the reset transistor RX is turned on, and the charge accumulated in the floating diffusion region FD is discharged due to the potential difference with the power supply voltage, resetting the floating diffusion region FD, and the voltage in the floating diffusion region FD becomes the same as the power supply voltage.

[0050] The operation of the drive transistors (DX1, DX2) is controlled according to the amount of charge accumulated in the region connected to the gate electrodes of the drive transistors (DX1, DX2). The drive transistors (DX1, DX2), in combination with a current source located outside the pixel, function as a source-follower buffer amplifier. For example, the first drive transistor DX1 amplifies and outputs a potential change due to the accumulation of charge in the floating diffusion region FD.

[0051] The selection transistor SX selects the pixels to read row by row. When the selection transistor SX is turned on, the electrical signal output from the second drive transistor DX2 is transmitted to the selection transistor SX.

[0052] On the other hand, the global shutter circuits included in each circuit (100a, 100b) contain multiple transistors and multiple capacitors to operate the pixel circuit in a global shutter manner. For example, the global shutter circuit stores electrical signals in the voltage domain and efficiently performs correlated double sampling (CDS).

[0053] Referring to Figure 3, in a circuit 100a included in an image sensor 100 according to one embodiment of the present invention, the first junction structure 150a is formed at the boundary between a first region 112a including a pixel circuit and a second region 122a including a global shutter circuit. For example, the first region 112a is a region included in the first layer 110, and the second region 122a is a region included in the second layer 120. That is, transistors included in the first region 112a are formed on the first semiconductor substrate 111, and transistors included in the second region 122a are formed on the second semiconductor substrate 121.

[0054] In an image sensor 100 according to one embodiment of the present invention, a transfer transistor TX, a reset transistor RX, and a first drive transistor DX1 are formed on a first semiconductor substrate 111. A switch element SW is further formed on the first semiconductor substrate 111. On the other hand, a second drive transistor DX2 and a selection transistor SX are formed on a second semiconductor substrate 121, along with a plurality of transistors (PC, PSX1, PSX2, S1, S2) included in the global shutter circuit.

[0055] Referring to Figure 4, in the circuit 100b included in the image sensor 100 according to one embodiment of the present invention, the first junction structure 150b is formed in a floating diffusion region FD. As a result, the first region 112b included in the first layer 110 contains a transfer transistor TX, and the second region 122b included in the second layer 120 contains a pixel circuit and a global shutter circuit excluding the transfer transistor TX. That is, the transfer transistor TX is formed on the first semiconductor substrate 111, and other transistors excluding the transfer transistor TX are formed on the second semiconductor substrate 121.

[0056] Figures 5 and 6 illustrate the effect of an image sensor according to one embodiment of the present invention.

[0057] Referring together to Figures 3 and 4, an image sensor 100 according to one embodiment of the present invention includes 11 transistors per pixel to embody a pixel circuit and a global shutter circuit. For example, the 11 transistors can be distributed across a first semiconductor substrate 111 and a second semiconductor substrate 121 to improve scaling efficiency.

[0058] Referring to Figure 5, an image sensor 100 according to one embodiment of the present invention, in which the pixel circuit and global shutter circuit are distributed, can secure a higher capacitance compared to the image sensor of the comparative example in which the circuits are not distributed.

[0059] The capacitance of a pixel is directly related to RTS (Random Telegraph Signal) noise. For example, to maintain RTS noise below 10 ppm, the image sensor needs to have a capacitance of approximately 0.15 pF or more per pixel. Image sensor 100 according to one embodiment of the present invention can secure the capacitance necessary to maintain RTS noise below 10 ppm while reducing the pixel size compared to the comparative example. However, the graph shown in Figure 5 is only one embodiment and is not limited to the illustrated example, and the pixel width (pitch) required to secure a predetermined capacitance will differ depending on the embodiment.

[0060] Referring to Figure 6, an image sensor 100 according to one embodiment of the present invention, in which the pixel circuit and global shutter circuit are distributed, can secure a larger area per transistor compared to the image sensor of the comparative example in which the circuits are not distributed.

[0061] The area occupied by transistors within a pixel is directly related to RTS (Random Telegraph Signal) noise. For example, to maintain RTS noise below 10 ppm, the image sensor requires approximately 0.175 μm per transistor. 2It is necessary to secure the above area. An image sensor 100 according to one embodiment of the present invention can secure the transistor area necessary to maintain RTS noise of 10 ppm or less while reducing the pixel size compared to the comparative example. However, the graph shown in Figure 6 is only one embodiment and is not limited as shown, and the pixel width (pitch) required to secure a predetermined transistor area differs depending on the embodiment.

[0062] Figure 7 is a simplified cross-sectional view showing an image sensor according to one embodiment of the present invention.

[0063] Referring to Figure 7, an image sensor 200 according to one embodiment of the present invention includes a first layer 210, a second layer 220, and a third layer 230 that are sequentially bonded in a first direction (for example, the Z direction). The first layer 210 includes a first semiconductor substrate 211 and a first wiring layer 215 laminated on the first semiconductor substrate 211; the second layer 220 includes a second semiconductor substrate 221 and a second wiring layer 225 laminated on the second semiconductor substrate 221; and the third layer 230 includes a third semiconductor substrate 231 and a third wiring layer 235 laminated on the third semiconductor substrate 231.

[0064] On the other hand, the image sensor 200 is divided into multiple regions according to their structure and role in a second direction (e.g., the X direction) and a third direction (e.g., the Y direction) perpendicular to the first direction. As an example, the multiple regions include a first region 200a, a second region 200b, a third region 200c, and a fourth region 200d. However, although Figure 7 shows the multiple regions arranged in a line in the second direction, this is merely one embodiment for the sake of clarity and is not limited thereto. Furthermore, the structure of each of the multiple regions is also merely one embodiment and is not limited to what is shown in the figure.

[0065] The first region 200a includes a pixel area and is a region for connecting regions in which predetermined circuits for driving the pixel area are formed. For example, the pixel area is formed on the first semiconductor substrate 211 and includes a configuration for injecting light into a photodiode PD such as a microlens ML and a color filter CF. On the other hand, semiconductor elements for driving the pixel area are formed on the second semiconductor substrate 221.

[0066] Referring to Figures 3 and 4, at least the transfer transistor TX of the image sensor 200 is formed on the first semiconductor substrate 211. As a result, the first layer 210, which includes the first semiconductor substrate 211, and the second layer 220, which includes the second semiconductor substrate 221, are joined by the first bonding structure 250.

[0067] The first bonding structure 250 corresponds to the first bonding structure 150 of the image sensor 100 shown in Figure 2. As an example, the first bonding structure 250 includes a first bonding metal 216 and a second bonding metal 226 that are exposed on one surface of the first wiring layer 215 and the second wiring layer 225, respectively, and are connected to the first wiring 212 contained in the first wiring layer 215 and the second upper wiring 222 contained in the second wiring layer 225, respectively.

[0068] The second region 200b does not include the pixel area and is a region for connecting the first layer 210, the second layer 220, and the third layer 230. For example, the second region 200b corresponds to the case where the pixel area is excluded from the image sensor 100 shown in Figure 2.

[0069] In an image sensor 200 according to one embodiment of the present invention, the first bonding structure 250 and the second bonding structure 260 correspond to the first bonding structure 150 and the second bonding structure 160 shown in Figure 2. As an example, the second bonding structure 260 includes a third bonding metal 236 exposed on one surface of the third wiring layer 235 and connected to a third wiring 232 included in the third wiring layer 235, and a bonding via 227 that penetrates the second semiconductor substrate 221 and is connected to a second lower wiring 223 included in the second wiring layer 225. The bonding via 227 is separated from the second semiconductor substrate 221 by a spacer layer 270.

[0070] The third region 200c is an input / output region that includes input / output terminals for connecting the image sensor 200 to an external device. For example, the third region 200c includes a first bonding structure 250 and a second bonding structure 260, and includes a through-via 290 used as an input / output terminal.

[0071] The through-via 290 penetrates the first semiconductor substrate 211 and connects to the first wiring 212 included in the first wiring layer 215. For example, the through-via 290 is connected to the wiring located at the top of the first wiring 212. However, this is only one embodiment and is not limited thereto, and the through-via 290 may be arranged to penetrate the third semiconductor substrate 231 depending on the embodiment. Embodiments relating to the internal structure of the third region 200c will be described later.

[0072] The fourth region 200d is a barrier region included to prevent problems that occur during the manufacturing process of the image sensor 200. For example, the fourth region 200d includes a first bonding structure 250 and a second bonding structure 260, and has the same structure as the second region 200b. However, this is only one embodiment and is not limited thereto. For example, the fourth region 200d includes a first bonding structure 250 and a second bonding structure 260, but the arrangement of the first bonding structure 250 and the second bonding structure 260 is different from the arrangement of the bonding structure 250 and the second bonding structure 260 in the second region 200b. A detailed explanation of the fourth region 200d will be given later.

[0073] Figures 8a and 8b are diagrams illustrating a first bonding structure included in an image sensor according to one embodiment of the present invention.

[0074] Referring to Figure 8a, the first bonding structure 250a includes a first bonding metal 216a connected to the first wiring 212 contained in the first wiring layer 215, and a second bonding metal 226a connected to the second upper wiring 222 contained in the second wiring layer 225.

[0075] The first bonding metal 216a and the second bonding metal 226a are formed by a process separate from the first wiring layer 215 and the second wiring layer 225. For example, the first wiring layer 215 and the second wiring layer 225 are distinguished from the region 280 surrounding the first bonding metal 216a and the second bonding metal 226a. However, this is only one embodiment and is not limited thereto, and each of the first bonding metal 216a and the second bonding metal 226a is defined as being exposed on one surface of the first wiring layer 215 and the second wiring layer 225.

[0076] The first wiring 212 and the second upper wiring 222 are enclosed by a barrier metal 201. For example, the barrier metal 201 acts as a barrier separating the wiring (212, 222) from the wiring layers (215, 225). However, this is only one embodiment and is not limited thereto. For example, the configuration of the wiring (212, 222) and wiring layers (215, 225) may vary depending on the embodiment, and the barrier metal 201 may be omitted as a result.

[0077] The first bonding metal 216a and the second bonding metal 226a extend in a second direction (for example, the X direction). For example, the extended length of the first bonding metal 216a is X1, and the extended length of the second bonding metal 226a is X2. X1 and X2 are different values. In Figure 8a, the length X1 of the first bonding metal 216a is shown to be longer than the length X2 of the second bonding metal 226a, but this is only one embodiment and is not limited thereto. For example, in some embodiments, X1 may be a smaller value than X2.

[0078] In an image sensor 200 according to one embodiment of the present invention, a bonding metal that is relatively short in length in the second direction completely overlaps with a bonding metal that is relatively long in length in the first direction (for example, the Z direction).

[0079] The image sensor 200 includes a plurality of first bonding structures 250a. This allows the first bonding metals 216a and second bonding metals 226a included in the plurality of first bonding structures 250a to be formed to have different configurations. For example, the lengths of the first bonding metals 216a and second bonding metals 226a constituting at least one of the plurality of first bonding structures 250a are identical in the second direction.

[0080] Referring to Figure 8b, the first bonding structure 250b includes a first bonding metal 216b connected to the first wiring 212 contained in the first wiring layer 215, and a second bonding metal 226b connected to the second upper wiring 222 contained in the second wiring layer 225.

[0081] The image sensor 200 includes a plurality of first bonding structures 250b. As a result, the first bonding metals 216b and second bonding metals 226b included in the plurality of first bonding structures 250b are formed to have different shapes. For example, the length of the first bonding metals 216b and 226b constituting at least one of the plurality of first bonding structures 250b extended in the second direction is X3. On the other hand, the length of the first bonding metals 216b and 226b constituting at least one of the plurality of first bonding structures 250b extended in the second direction is X4. X3 and X4 are different values.

[0082] The first bonding structures (250a, 250b) shown in Figures 8a and 8b are merely one embodiment and are not limited to those shown. For example, the first bonding structures (250a, 250b) included in the image sensor 200 include various forms of bonding structures having a Cu-Cu bonding structure.

[0083] Figures 9 and 10 illustrate a second junction structure included in an image sensor according to one embodiment of the present invention.

[0084] Referring to Figure 9, the second bonding structure 260a includes a third bonding metal 236a connected to a third wiring 232 included in the third wiring layer 235, and a bonding via 227a that penetrates the second semiconductor substrate 221 and is connected to a second lower wiring 223 included in the second wiring layer 225. For example, the second lower wiring 223 contains tungsten (W) and / or copper (Cu), and the second lower wiring 223 has a different configuration from the wiring included in the other wiring layers. However, this is only one embodiment and is not limited thereto.

[0085] The third bonding metal 236a is formed by a process separate from that of the third wiring layer 235. For example, the third wiring layer 235 is distinguished from the region 280 surrounding the third bonding metal 236a. However, this is only one embodiment and is not limited thereto, and the third bonding metal 236a is defined as being exposed on one surface of the third wiring layer 235.

[0086] In an image sensor 200 according to one embodiment of the present invention, a process is performed to thin the second semiconductor substrate 221 after forming a first junction structure in order to reduce the size of the image sensor and minimize noise. For example, through the thinning process, the second semiconductor substrate 221 is polished to have a predetermined thickness. As a result, the second semiconductor substrate 221 has a width (thickness) Z1 in the first direction. For example, Z1 has a value between approximately 10 nm and 2 μm.

[0087] In an image sensor 200 according to one embodiment of the present invention, the bonded via 227a includes an upper via region 227a' that contacts the second lower wiring 223 and has a first width in a second direction perpendicular to the first direction, and a lower via region 227a'' that contacts the third bonding metal 236a and has a second width greater than the first width in the second direction.

[0088] The junction via 227a and the second semiconductor substrate 221 are separated by a spacer layer 270. The spacer layer 270 includes a first spacer layer 271 placed between the second semiconductor substrate 221 and the junction via 227a, and a second spacer layer 272 placed between the second semiconductor substrate 221 and the third wiring layer 235.

[0089] In an image sensor 200 according to one embodiment of the present invention, the first spacer layer 271 and the second spacer layer 272 are composed of different materials. For example, the first spacer layer is composed of a composite film containing SiCN, and the second spacer layer is composed of a composite film containing a metal oxide. For example, the composite film constituting the second spacer layer contains a metal oxide such as HfOx, TaOx, or AlOx. However, this is merely one embodiment and is not limited thereto.

[0090] The upper via region 227a' has a first thickness a in the first direction. For example, the first thickness is between approximately 100 nm and 800 nm. On the other hand, the second spacer layer 272 has a second thickness b in the first direction. In the image sensor according to one embodiment of the present invention, the first thickness a is greater than the second thickness b.

[0091] Referring to Figure 10, the configuration of the second junction structure 260b corresponds to the configuration of the second junction structure 260a shown in Figure 9. As an example, the second junction structure 260b joins a second layer, which includes a second semiconductor substrate 221 and a second wiring layer 225, to a third layer, which includes a third semiconductor substrate 231 and a third wiring layer 235. The second lower wiring 223, junction via 227b, third bonding metal 236b, and third wiring 232 are sequentially connected to join the second and third layers. The junction via 227b includes an upper via region 227b' and a lower via region 227b'', and is separated from the second semiconductor substrate 221 by a spacer layer 270, which includes a first spacer layer 271 and a second spacer layer 272.

[0092] The image sensor 200 includes a plurality of second bonding structures 260b, and the plurality of second bonding structures 260b included in the image sensor 200 are formed into various structures depending on the embodiment.

[0093] In an image sensor 200 according to one embodiment of the present invention, the extended length of the third bonding metal 236b constituting at least one of the plurality of second bonding structures 260b in the second direction is different from the extended length of the third bonding metal 236b constituting one of the other of the plurality of second bonding structures 260b.

[0094] As a result, the length of the extension of the third bonding metal 236b in the second direction is different from the width of the lower via region 227b''. For example, the length of the extension of the third bonding metal 236b in the second direction is X6, and the width of the lower via region 227b'' is X5. Figure 10 shows that X5 is smaller than X6, but this is only one embodiment and is not limited thereto.

[0095] Figures 11a to 11c are cross-sectional views illustrating the structure of the input / output region included in an image sensor according to one embodiment of the present invention. Figures 12a to 12c are cross-sectional views illustrating the structure of the input / output region included in an image sensor according to one embodiment of the present invention.

[0096] Figures 11a to 11c and 12a to 12c show an embodiment of the third region 200c, which includes a through-via 290 used as an input / output terminal, in the image sensor 200 shown in Figure 7. On the other hand, the other configurations correspond to the configurations included in the image sensor 200.

[0097] As an example, Figures 11a to 11c show the input / output areas (300c-1, 300c-2, 300c-3) of an image sensor with input / output terminals formed in the direction of the first layer 310, and Figures 12a to 12c show the input / output areas (400c-1, 400c-2, 400c-3) of an image sensor with input / output terminals formed in the direction of the third layer 430.

[0098] Referring to Figures 11a to 11c, the input / output regions of the image sensor (300c-1, 300c-2, 300c-3) include a first through-via 390 that extends from one exposed surface of the first semiconductor substrate 311 and connects to the wiring located at the top of the first wiring 312 of the first wiring layer 315 included in the first layer 310.

[0099] Referring to Figure 11a, in the input / output region 300c-1 of the image sensor, the first bonding structure 350 and the second bonding structure 360 ​​are arranged so as not to overlap each other in the first direction (for example, the Z direction). The first bonding structure 350 and the second bonding structure 360 ​​play a role in bonding and supporting the layers. Therefore, by arranging the first bonding structure 350 and the second bonding structure 360 ​​so as not to overlap, stability can be improved, such as minimizing bending that may occur during the operation of the image sensor.

[0100] On the other hand, the input / output region 300c-1 of the image sensor shown in Figure 11a can be further improved in terms of stability by arranging the first through via 390 so that it does not overlap with the first bonding structure 350 in the first direction. However, this is only one embodiment, and the arrangement of the first through via 390, the first bonding structure 350, and the second bonding structure 360 ​​is not limited to the one shown.

[0101] As an example, referring to Figure 11b, the first joint structure 350 and the second joint structure 360 ​​are positioned to overlap each other in the first direction. On the other hand, referring to Figure 11c, multiple instances of each of the first joint structure 350 and the second joint structure 360 ​​are positioned at arbitrary locations, independent of the first through via 390. Although not shown in Figures 11a to 11c, the first through via 390 may be positioned to overlap with the first joint structure 350 in the first direction.

[0102] Referring to Figures 12a to 12c, the input / output regions of the image sensor (400c-1, 400c-2, 400c-3) include a second through-via 490 that extends from one exposed surface of the third semiconductor substrate 431 and connects to the lowest wiring of the third wiring 432 of the third wiring layer 435 included in the third layer 430. For example, unlike the first through-via 390, the second through-via 490 only serves to penetrate the third semiconductor substrate 431 and is connected to the outside by a separate solder ball 495. However, this is only one embodiment and is not limited thereto.

[0103] Referring to Figure 12a, similar to Figure 11a, in the input / output region 400c-1 of the image sensor, the first bonding structure 450, the second bonding structure 460, and the solder ball 495 are arranged in a zigzag pattern (so as not to overlap) in the first direction to improve the stability of the image sensor. However, this is only one embodiment and is not limited thereto, and referring to Figures 12b and 12c, in the embodiment, the first bonding structure 450 and the second bonding structure 460 are arranged to overlap in the first direction or are arranged arbitrarily. An image sensor according to one embodiment of the present invention includes an input / output region including at least one of a first through via 390 and a second through via 490.

[0104] Figures 13 and 14 are a top view and a cross-sectional view illustrating the structure of a barrier region included in an image sensor according to one embodiment of the present invention.

[0105] Figure 13 is a top view of the manufacturing process of an image sensor according to one embodiment of the present invention. The image sensor manufacturing process includes a dicing process to separate multiple image sensors after they have been manufactured on a substrate. As an example, the multiple image sensors formed on the substrate are separated into separate image sensors along cut surfaces L1 and L2.

[0106] Referring to Figure 13, the separate image sensors 500 separated by the dicing process may develop cracks C on their cut surfaces. Meanwhile, moisture may penetrate the integrated circuit through the cut surfaces. Cracks C that occur in the image sensor and / or moisture that penetrates the image sensor will cause defects in the image sensor.

[0107] An image sensor according to one embodiment of the present invention includes a barrier region 500d positioned adjacent to the cut surfaces L1 and L2. As an example, the barrier region 500d shown in Figure 13 corresponds to the fourth region 200d included in the image sensor 200 shown in Figure 7. The barrier region 500d protects the integrated circuit, which includes multiple transistors, from moisture penetration and from the occurrence of cracks C. As a result, the fourth region 200d corresponding to the barrier region 500d is positioned to surround the first region 200a to the third region 200c.

[0108] Referring together to Figures 7 and 14, the barrier region 600d included in the image sensor 600 according to one embodiment of the present invention is a region that serves as a CS (Crack Stopper) and / or MOB (Moisture Oxidation Barrier). For example, the configuration of the barrier region 600d corresponds to the fourth region 200d included in the image sensor 200. On the other hand, the arrangement of the first bonding structure 650 and the second bonding structure 660 included in the barrier region 600d is the same as the arrangement of the first bonding structure 250 and the second bonding structure 260 included in the second region 200b included in the image sensor 200. However, this is only one embodiment and is not limited thereto.

[0109] Figure 15 is a flowchart illustrating a method for manufacturing an image sensor according to one embodiment of the present invention.

[0110] Referring to Figure 15, the first layer (PIXEL wafer), the second layer (CAP wafer), and the third layer (LOGIC wafer) are manufactured into a single image sensor by joining them through a plurality of processes included in the image sensor manufacturing method according to one embodiment of the present invention.

[0111] The image sensor includes a first layer (PIXEL wafer) containing a pixel section in which multiple unit pixels are arranged, a second layer (CAP wafer) containing multiple transistors and multiple capacitors for realizing global shutter operation, and a third layer (LOGIC wafer) containing logic circuits. As an example, a method for manufacturing an image sensor according to one embodiment of the present invention begins with forming the first layer (PIXEL wafer), the second layer (CAP wafer), and the third layer (LOGIC wafer), which each contain a semiconductor substrate and a wiring layer, respectively.

[0112] Meanwhile, on one side of the first wiring layer included in the formed first layer (PIXEL wafer), a plurality of first bonding metals exposed to the outside are formed (S110). Furthermore, on one side of the second wiring layer included in the second layer (CAP wafer), a plurality of second bonding metals exposed to the outside are formed (S120), and on one side of the third wiring layer included in the third layer (LOGIC wafer), a plurality of third bonding metals exposed to the outside are formed (S160). As an example, the plurality of bonding metals are Cu pads (Cu PADs).

[0113] Multiple bonding metals formed on the first layer (PIXEL wafer) and multiple bonding metals formed on the second layer (CAP wafer) are joined to each other by a primary bonding process (S130). As an example, the primary bonding process forms a first bonded structure between the first layer (PIXEL wafer) and the second layer (CAP wafer). The primary bonding process joins the first wiring layer contained in the first layer (PIXEL wafer) and the second wiring layer contained in the second layer (CAP wafer) facing each other.

[0114] After forming the first bonding structure, a primary thinning process is performed on the second semiconductor substrate contained in the second layer (CAP wafer) (S140). As an example, the primary thinning process is performed by polishing the back surface of the semiconductor substrate where the second wiring layer is not laminated. The primary thinning process polishes the second semiconductor substrate to a predetermined thickness. As an example, in an image sensor according to one embodiment of the present invention, the second semiconductor substrate has a thickness between approximately 10 nm and 2 μm. However, this is only one embodiment and is not limited thereto.

[0115] After the primary thinning process is completed, bonding vias are formed on the second layer (CAP wafer) (S150). The bonding vias are formed to contact the second lower wiring of the second wiring layer and penetrate the second semiconductor substrate. Meanwhile, the bonding vias are bonded to the third bonding metal formed on the third layer (LOGIC wafer) to form a second bonding structure (S170). As an example, the process of forming the second bonding structure is a secondary bonding process.

[0116] After forming the second bonding structure, a secondary thinning process is performed on the first semiconductor substrate contained in the first layer (PIXEL wafer) (S180). As an example, the secondary thinning process is performed by polishing the back surface of the semiconductor substrate where the first wiring layer is not laminated. Through the secondary thinning process, the first semiconductor substrate is polished to a predetermined thickness.

[0117] After the secondary thinning process is completed, a process is carried out to form a BSI (Back Side Illumination) type image sensor on the back surface of the polished first semiconductor substrate, where microlenses for injecting light are placed (S190). Steps S110 to S190 manufacture an image sensor in which the first layer (PIXEL wafer), the second layer (CAP wafer), and the third layer (LOGIC wafer) are bonded together.

[0118] Figures 16a to 16e are diagrams illustrating a method for manufacturing an image sensor according to one embodiment of the present invention.

[0119] Figures 16a to 16e are cross-sectional views of the image sensor, showing the S150 step of forming the bonded vias shown in Figure 15, subdivided into individual steps. Referring to Figure 16a, the second layer 120 includes a second semiconductor substrate 121 and a second wiring layer 125 laminated on the second semiconductor substrate 121. The second wiring layer 125 includes a second lower wiring 123.

[0120] Referring to Figure 16b, after the primary thinning process is completed, a first etching is performed on the second semiconductor substrate 121 at the location where the bonding vias are to be formed. For example, the first etching is performed until the second wiring layer 125 is exposed to the outside.

[0121] Referring to Figure 16c, a spacer layer 170 is formed on the second semiconductor substrate 121 and the second wiring layer 125 exposed by the first etching. Although not shown in Figure 16c, other layers with a different configuration from the spacer layer 170 may be formed on the second semiconductor substrate 121 before the spacer layer 170 is formed.

[0122] Referring to Figure 16d, a second etching is performed on a portion of the spacer layer 170 and the second wiring layer 125. For example, the second etching is performed until the second lower wiring 123 is exposed to the outside. The width in the second direction where the second etching is performed is smaller than the width where the first etching is performed.

[0123] Referring to Figure 16e, via structures 127 are formed on the spacer layer 170 and the second wiring layer 125 after the second etching is completed. For example, the via structures 127 are connected to the second lower wiring 123 exposed by the second etching. The via structures 127 are made of Cu and are polished along the machined surface P. For example, the polished via structures 127 are bonded vias.

[0124] However, the image sensor manufacturing process shown in Figures 16a to 16e is merely one embodiment and is not limited thereto. For example, to manufacture an image sensor according to one embodiment of the present invention, other steps may be added between steps, or some of the existing steps may be omitted.

[0125] Figures 17 and 18 are simplified diagrams showing an electronic device including an image sensor according to one embodiment of the present invention.

[0126] Referring to Figure 17, the electronic device 1000 includes a group of camera modules 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

[0127] The camera module group 1100 includes a plurality of camera modules (1100a, 1100b, 1100c). The figure shows an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, but the embodiment is not limited thereto. In some embodiments, the camera module group 1100 is modified to include only two camera modules. Also, in some embodiments, the camera module group 1100 is modified to include n camera modules (where n is a natural number greater than or equal to 4). Furthermore, in one embodiment, at least one of the plurality of camera modules (1100a, 1100b, 1100c) included in the camera module group 1100 includes an image sensor according to any of the embodiments described earlier with reference to Figures 1 to 16e.

[0128] The detailed configuration of camera module 1100b will be described in more detail below with reference to Figure 18, but the following description can also be applied to camera modules (1100a, 1100c) which differ depending on the embodiment.

[0129] Referring to Figure 18, the camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and storage 1150.

[0130] The prism 1105 includes a reflective surface 1107 made of a light-reflecting material, which alters the path of light L incident from an external source.

[0131] In some embodiments, the prism 1105 changes the path of light L incident in the X-axis direction to the Y-axis direction perpendicular to the X-axis direction. The prism 1105 also rotates the reflective surface 1107 of the light-reflecting material in the A direction around the central axis 1106, or rotates the central axis 1106 in the B direction, thereby changing the path of light L incident in the X-axis direction to the perpendicular Y-axis direction. At this time, the OPFE 1110 also moves in the Z-axis direction perpendicular to the X-axis and Y-axis directions.

[0132] In some embodiments, as illustrated, the maximum rotation angle of the prism 1105 in the A direction is 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, but the embodiments are not limited thereto.

[0133] In some embodiments, the prism 1105 can move approximately 20 degrees in the positive (+) or negative (-)B direction, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be the same angle in the positive (+) or negative (-)B direction, or to approximately similar angles within a range of about 1 degree.

[0134] In some embodiments, the prism 1105 can move the reflective surface 1107 of the light-reflecting material in the Z-axis direction parallel to the extension direction of the central axis 1106.

[0135] The OPFE1110 includes, for example, m (where m is a natural number) optical lenses. The m lenses move in a second direction Y to change the optical zoom ratio of the camera module 1100b. For example, if the basic optical zoom ratio of the camera module 1100b is Z, moving the m optical lenses included in the OPFE1110 will change the optical zoom ratio of the camera module 1100b to 3Z, 5Z, or 5Z or greater.

[0136] The actuator 1130 moves the OPFE 1110 or optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the sensor 1142 is positioned at the focal length of the optical lens for accurate sensing. As an example, the sensor 1142 is an image sensor.

[0137] The image sensing device 1140 includes a sensor 1142, control logic 1144, and memory 1146. The sensor 1142 senses the image to be sensed using light L provided through an optical lens. The control logic 1144 controls the overall operation of the camera module 1100b. For example, the control logic 1144 controls the operation of the camera module 1100b in response to control signals provided via the control signal line CSLb.

[0138] Memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. Calibration data 1147 includes information necessary for the camera module 1100b to generate image data using light L supplied from an external source. Calibration data 1147 includes, for example, information on the degree of rotation, focal length, and optical axis as described above. If the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, calibration data 1147 includes focal length values ​​for each position (or state) of the optical lens and information on autofocusing.

[0139] The storage 1150 stores image data sensed via the sensor 1142. The storage 1150 is located outside the image sensing device 1140 and is implemented in a stacked form with the sensor chips that make up the image sensing device 1140. In some embodiments, the storage 1150 is implemented as EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto.

[0140] Referring together to Figures 17 and 18, in some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. Thus, each of the multiple camera modules (1100a, 1100b, 1100c) includes the same or different calibration data 1147 depending on the operation of the actuator 1130 contained within it.

[0141] In some embodiments, one of the camera modules (1100a, 1100b, 1100c) (e.g., 1100b) is a folded lens type camera module including the prism 1105 and OPFE 1110 described above, while the remaining camera modules (e.g., 1100a, 1100c) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiments are not limited thereto.

[0142] In some embodiments, one of the camera modules (1100a, 1100b, 1100c), for example, 1100c, is a vertical depth camera that extracts depth information using, for example, infrared (IR). In this case, the application processor 1200 merges the image data provided by such a depth camera with the image data provided by the other camera modules (for example, 1100a or 1100b) to generate a 3D depth image.

[0143] In some embodiments, at least two of the multiple camera modules (1100a, 1100b, 1100c) (e.g., 1100a, 1100b) have different fields of view (angles of view). In this case, for example, the optical lenses of at least two of the multiple camera modules (1100a, 1100b, 1100c) (e.g., 1100a, 1100b) are different from each other, but are not limited to this.

[0144] Furthermore, in some embodiments, the field of view of each of the multiple camera modules (1100a, 1100b, 1100c) differs from one another. In this case, the optical lenses included in each of the multiple camera modules (1100a, 1100b, 1100c) also differ from one another, but are not limited to this.

[0145] In some embodiments, the multiple camera modules (1100a, 1100b, 1100c) are physically separated from each other. That is, the sensing area of ​​a single sensor 1142 is not divided and used by the multiple camera modules (1100a, 1100b, 1100c), but rather an independent sensor 1142 is located inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0146] Referring again to Figure 17, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 is implemented separately from the multiple camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the multiple camera modules (1100a, 1100b, 1100c) are implemented separately on different semiconductor chips.

[0147] The image processing unit 1210 includes a plurality of subprocessors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216.

[0148] The image processing device 1210 includes multiple subprocessors (1212a, 1212b, 1212c) in a number corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0149] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding subprocessor (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to subprocessor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to subprocessor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to subprocessor 1212c via image signal line ISLc. Such transfer of image data is performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0150] On the other hand, in some embodiments, one subprocessor is arranged to support multiple camera modules. For example, instead of subprocessors 1212a and 1212c being implemented separately from each other as shown in the figure, they are implemented integrated into a single subprocessor, and the image data provided from camera modules 1100a and 1100c are selected via a selection element (e.g., a multiplexer) and then provided to the integrated subprocessor.

[0151] The image data provided to each subprocessor (1212a, 1212b, 1212c) is provided to the image generator 1214. The image generator 1214 generates an output image using the image data provided from each subprocessor (1212a, 1212b, 1212c) based on generating information or a mode signal.

[0152] Specifically, the image generator 1214 generates an output image by merging at least a portion of the image data generated from camera modules (1100a, 1100b, 1100c) having different field of view angles, according to the image generation information or mode signal. Alternatively, the image generator 1214 may select one of the image data generated from camera modules (1100a, 1100b, 1100c) having different field of view angles, according to the image generation information or mode signal, to generate an output image.

[0153] In some embodiments, the image generation information includes a zoom signal (or zoom factor). In some embodiments, the mode signal is, for example, a signal based on a mode selected by the user.

[0154] If the image generation information is a zoom signal (zoom factor), and each camera module (1100a, 1100b, 1100c) has a different field of view (field of view angle), the image generator 1214 performs different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image data output from camera module 1100a and the image data output from camera module 1100c are merged, and then the merged image signal and the image data output from camera module 1100b, which was not used in the merging, are used to generate the output image. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not merge such image data, but instead selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate the output image. However, the embodiment is not limited to this, and the method of processing the image data can be modified in any way as needed.

[0155] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of a plurality of subprocessors (1212a, 1212b, 1212c), and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0156] The camera module controller 1216 provides control signals to each camera module (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via mutually isolated control signal lines (CSLa, CSLb, CSLc).

[0157] One of the multiple camera modules (1100a, 1100b, 1100c) is designated as the master camera (e.g., 1100b) depending on image generation information including a zoom signal or a mode signal, while the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. This information is included in the control signals and provided to the corresponding camera modules (1100a, 1100b, 1100c) via isolated control signal lines (CSLa, CSLb, CSLc).

[0158] Depending on the zoom factor or operating mode signal, the camera module operating as the master camera and the camera module operating as the slave camera are changed. For example, if the field of view of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a lower zoom magnification, camera module 1100b operates as the master camera and camera module 1100a operates as the slave camera. Conversely, if the zoom factor indicates a higher zoom magnification, camera module 1100a operates as the master camera and camera module 1100b operates as the slave camera.

[0159] In some embodiments, the control signals provided from the camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sync enable signal. For example, if camera module 1100b is the master camera and camera modules (1100a, 1100c) are slave cameras, the camera module controller 1216 forwards a sync enable signal to camera module 1100b. Upon receiving such a sync enable signal, camera module 1100b generates a sync signal based on the provided sync enable signal and provides the generated sync signal to camera modules (1100a, 1100c) via the sync signal line SSL. Camera modules 1100b and (1100a, 1100c) forward image data to the application processor 1200 in synchronization with such sync signals.

[0160] In some embodiments, the control signals provided from the camera module controller 1216 to a plurality of camera modules (1100a, 1100b, 1100c) include mode information corresponding to a mode signal. Based on such mode information, the plurality of camera modules (1100a, 1100b, 1100c) operate in a first operating mode and a second operating mode in relation to the sensing speed.

[0161] Multiple camera modules (1100a, 1100b, 1100c) generate an image signal at a first speed in the first operating mode (for example, an image signal at a first frame rate), encode it at a second speed higher than the first speed (for example, encode an image signal at a second frame rate higher than the first frame rate), and transfer the encoded image signal to the application processor 1200. At this time, the second speed is 30 times or less the first speed.

[0162] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in its internal memory 1230 or external memory 1400. It then reads the encoded image signal from the internal memory 1230 or external memory 1400, decodes it, and displays the image data generated based on the decoded image signal. For example, one of the multiple subprocessors (1212a, 1212b, 1212c) of the image processing device 1210 performs the decoding and also processes the decoded image signal.

[0163] Multiple camera modules (1100a, 1100b, 1100c) generate image signals at a third speed lower than the first speed in the second operating mode (for example, generating image signals at a third frame rate lower than the first frame rate) and transfer the image signals to the application processor 1200. The image signals provided to the application processor 1200 are unencoded signals. The application processor 1200 either performs image processing on the received image signals or stores the image signals in internal memory 1230 or external memory 1400.

[0164] The PMIC1300 supplies power, such as a power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC1300 supplies first power to camera module 1100a via power signal line PSLa, second power to camera module 1100b via power signal line PSLb, and third power to camera module 1100c via power signal line PSLc.

[0165] The PMIC 1300 generates and adjusts the power levels for each of the multiple camera modules (1100a, 1100b, 1100c) in response to a power control signal PCON from the application processor 1200. The power control signal PCON includes power adjustment signals for each operating mode of the multiple camera modules (1100a, 1100b, 1100c). For example, the operating mode includes a low power mode, in which case the power control signal PCON includes information about the camera modules operating in low power mode and the power levels to be set. The power levels provided to each of the multiple camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Furthermore, the power levels are dynamically changed.

[0166] The present invention is not limited by the embodiments and drawings described above. Therefore, various forms of substitution, modification, and alteration are possible by those with ordinary skill in the art without departing from the technical spirit of the present invention, and these also fall within the scope of the present invention. [Explanation of Symbols]

[0167] 1, 100, 200 Image Sensors 10-pixel array 20 Logic Circuits 21 Low Driver 22. Lead-out circuit 23 Column Driver 24 Control Logic 101, 201 Barrier Metal 110, 210, 310 First Layer 111, 211, 311 First Semiconductor Substrate 112, 212, 312 1st wiring 115, 215, 315 1st wiring layer 116, 216, 216a, 216b First bonding metal 118, 128, 138 transistors 120, 220 Second Layer 121, 221 Second Semiconductor Substrate 122 2nd wiring (2nd upper wiring) 123, 223 Second Lower Wiring 125, 225 2nd wiring layer 126, 226, 226a, 226b Second bonding metal 127, 227, 227a, 227b junction vias 129 Capacitors 130, 230, 430 Third Layer 131, 231, 431 Third Semiconductor Substrate 132, 232, 432 3rd wiring 135, 235, 435 3rd wiring layer 136, 236, 236a, 236b Third bonding metal 150, 250, 250a, 250b, 350, 450, 650 1st joint structure 160, 260, 260a, 260b, 360, 460, 660 2nd joint structure 170, 270 spacer layer 180 areas 222 Second Upper Wiring 227a', 227b' Upper via region 227a”, 227b” Lower via area 271 First Spacer Layer 272 Second Spacer Layer 280 (Region) Fourth insulating layer 290 through vias 390 First Through Via 490 Second Through Via 495 Solder ball 500d, 600d barrier area 1000 electronic devices 1100 Camera Module Group 1100a~1100c Camera Module 1105 Prism 1106 Center axis 1107 Reflective surface 1110 OPFE 1130 Actuator 1140 Image Sensing Device 1142 (Image) Sensor 1144 Control Logic 1146 memory 1147 Calibration data 1150 storage 1200 application processors 1210 Image Processing Device 1212a~1212c Subprocessors 1214 Image Generator 1216 Camera Module Controller 1220 Memory Controller 1230 internal memory 1300 PMIC 1400 External memory PX Pixel area

Claims

1. A first semiconductor substrate including a pixel portion in which multiple unit pixels are arranged, and a first layer including a first wiring layer stacked on the first semiconductor substrate, A second semiconductor substrate on which a plurality of transistors for realizing global shutter operation are formed, and a second wiring layer laminated on the second semiconductor substrate, the second layer being laminated on the first layer such that the first wiring layer and the second wiring layer face each other in a first direction, A plurality of first bonding structures that join the first layer and the second layer by bringing into contact a first bonding metal exposed on one surface of the first wiring layer and a second bonding metal exposed on one surface of the second wiring layer, A third semiconductor substrate on which a logic circuit is formed, and a third wiring layer laminated on the third semiconductor substrate, the third layer being bonded to the second layer such that the second semiconductor substrate and the third wiring layer face each other in the first direction, A plurality of second bonding structures that bond the second layer and the third layer by bringing into contact a bonding via extending from the second wiring layer and penetrating the second semiconductor substrate with a third bonding metal exposed on one surface of the third wiring layer, The second semiconductor substrate and the junction via are included, The spacer layer includes a first region disposed between the second semiconductor substrate and the bonding via and a second region extending from the first region and disposed between the second semiconductor substrate and the third wiring layer from a first direction. An image sensor characterized in that the first region and the second region are a single continuous region.

2. The image sensor according to claim 1, characterized in that a transfer transistor is formed on the first semiconductor substrate, and transistors of a pixel circuit excluding the transfer transistor are formed on the second semiconductor substrate.

3. The image sensor according to claim 1, characterized in that the first semiconductor substrate has transistors forming a pixel circuit including a transfer transistor, a reset transistor, and an operating transistor.

4. The image sensor according to claim 1, characterized in that the bonding via includes an upper via region that contacts the second wiring included in the second wiring layer and has a first width in a second direction perpendicular to the first direction, and a lower via region that contacts the third bonding metal and has a second width greater than the first width in the second direction.

5. The image sensor according to claim 4, characterized in that the thickness of the upper via region is greater than the thickness of the second region in the first direction.

6. The image sensor according to claim 5, characterized in that the first region and the second region are composed of different materials.

7. A first layer, a second layer, and a third layer, which are sequentially bonded in the first direction, each include a semiconductor substrate and a wiring layer laminated on the semiconductor substrate in the first direction, and are divided into a plurality of regions in the second and third directions perpendicular to the first direction. The aforementioned multiple regions are, The first layer includes a first semiconductor substrate on which pixel portions are formed, The second layer includes a first region which includes a second semiconductor substrate on which a predetermined circuit is formed, A second region in which the first layer and the second layer are joined by a first joining structure, and the second layer and the third layer are joined by a second joining structure, An image sensor characterized by including a third region which includes at least one of a first through-via extending from an exposed surface of the first semiconductor substrate and connected to a first wiring included in a first wiring layer included in the first layer, and a second through-via extending from an exposed surface of a third semiconductor substrate included in the third layer and connected to a third wiring included in a third wiring layer included in the third layer.

8. The image sensor according to claim 7, wherein the plurality of regions include the first bonding structure and the second bonding structure, and further include a fourth region arranged to surround the first region, the second region and the third region.

9. The steps include forming a first semiconductor substrate including a pixel portion in which a plurality of unit pixels are arranged, and a first layer including a first wiring layer stacked on the first semiconductor substrate, The steps include forming a second semiconductor substrate on which multiple transistors for realizing global shutter operation are formed, and a second layer including a second wiring layer stacked on the second semiconductor substrate, The steps include forming a first bonding metal exposed on one surface of the first wiring layer and a second bonding metal exposed on one surface of the second wiring layer, The steps include: joining the first bonding metal and the second bonding metal to form a first bonding structure; The steps include forming a bonding via that contacts the wiring contained in the second wiring layer and penetrates the second semiconductor substrate, The steps include forming a third semiconductor substrate on which a logic circuit is formed, and a third layer including a third wiring layer stacked on the third semiconductor substrate, The steps include forming a third bonding metal exposed on one surface of the third wiring layer, The step includes joining the aforementioned bonding via and the third bonding metal to form a second bonding structure, The step of forming the aforementioned joint via is: The first step of etching the second semiconductor substrate, The steps include forming a spacer layer on one surface of the second semiconductor substrate and on the second wiring layer exposed by the first etching, The steps include second etching of a portion of the spacer layer and the second wiring layer, A method for manufacturing an image sensor, comprising the step of forming via structures that contact wiring contained in the second wiring layer exposed by the second etching.

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