Switching power supply control circuit

Abstract

To suppress ripple on an output voltage during burst operation at light load condition.SOLUTION: A switching power supply control circuit 1 of the embodiment controls a switching power supply 100 which outputs a target voltage by switching an electric path between input / output according to a comparison result between signals Ser, Sin based on an output voltage Vout with a predetermined signal Sc and which performs burst operation in which the switching is intermittent with a halt period according to load current. The switching power supply control circuit 1 includes a detection circuit 6 for detecting predetermined light load condition at the switching power supply 100, and a switching limit circuit 7 for reducing the number of switching in the burst operation when the light load condition by the detection circuit 6 is being detected.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a switching power supply control circuit.

Background Art

[0002] Conventionally, switching power supplies such as switching regulators that convert DC power obtained from conversion of an AC power system into DC or from a battery or the like into a voltage of a desired magnitude corresponding to a device to be used have been widely used. In a switching power supply, a feedback signal based on an output voltage is compared with a predetermined signal, and energy supplied from an input side to an output side is adjusted by feedback control in which an electric path between input and output is opened and closed (switched) during a time corresponding to the comparison result. The energy supplied to the output side is stored in a capacitor of a smoothing circuit and output as a load current at a voltage of a desired magnitude. When the electric path is cut off by switching, the current required by the load is supplied by discharging of the capacitor. Accordingly, in a switching power supply, the output voltage fluctuates according to the magnitude of the load current. For this reason, the magnitude of the load current affects switching time based on the output voltage, for example, the on-time of a switching element used for switching, the switching frequency, and the like.

[0003] In PWM (Pulse Width Modulation) control, a feedback control method in which the on-time of the switching element is adjusted according to the output voltage, a constant switching loss occurs because the number of switching cycles per unit time remains constant regardless of the output voltage. Therefore, the conversion efficiency decreases under light load conditions where the load current is small and thus the output power is small. Furthermore, even in a pseudo-resonant switching power supply, such as the one disclosed in Patent Document 1, the switching frequency increases under light load conditions, resulting in increased switching loss and a decrease in conversion efficiency. In the switching power supply control circuit disclosed in Patent Document 1, a switching stop period corresponding to the load is provided under light load conditions to suppress the increase in switching frequency in order to suppress the decrease in conversion efficiency. In Patent Document 1, furthermore, in order to prevent the increase in switching noise and the decrease in efficiency due to the increase in switching loss under extremely light load conditions, burst switching is performed, which involves repeating a period of continuous switching a predetermined number of times and a period of stopping switching. Note that in Patent Document 1, switching by PWM control is referred to as burst switching, but in the following explanation, switching that repeats a period of continuous switching and a period of stopping switching, as performed in Patent Document 1, will be referred to as "burst switching" or "burst operation". [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2007-215316 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, burst switching under light load conditions, as performed by the switching power supply control circuit described in Patent Document 1, can increase the output ripple voltage. This point will be explained with reference to Figures 10 and 11, using a PWM-controlled switching power supply as an example. Figure 10 shows a schematic configuration of a switching power supply Psw, which is an example of a conventional PWM-controlled switching power supply, and Figure 11 shows an example of the signal waveforms of each part in Figure 10. The upper part of Figure 11 shows the error signal Ser, which is the output signal of the error amplifier 92, along with the comparison signal Sc shown in Figure 10, the middle part shows the output signal S of the PWM comparator 94, and the lower part shows the output voltage Vout of the switching power supply Psw.

[0006] The switching power supply Psw includes a transistor 96 and a control circuit Pc. The control circuit Pc includes an oscillator circuit 91 that outputs a comparison signal Sc, an error amplifier 92, a reference voltage Vref generation circuit 93, and a PWM comparator 94. The error amplifier 92 outputs an error signal Ser that increases or decreases depending on the magnitude of the inverting input voltage relative to the reference voltage Vref applied to the non-inverting input. A resistor 921 and a capacitor 922 are inserted in the negative feedback loop of the error amplifier 92 to stabilize its negative feedback operation. The PWM comparator 94 outputs a signal S that includes a pulse that is high level while the level of the error signal Ser is higher than the level of the comparison signal Sc. Transistor 96 switches the input voltage Vin according to the duty cycle of the signal S input via the driver 95 and supplies it to the smoothing circuit 98. The driver 95 is configured to drive transistor 96 with the inverted signal of signal S, and transistor 96 is turned on when signal S is high level. The smoothing circuit 98 is charged via transistor 96 and diode 97 at the duty cycle of signal S, and outputs a smoothed output voltage Vout. The output voltage Vout is divided by a series resistor 99 and returned to the error amplifier 92 as a feedback voltage Vfb. Through this feedback control, the desired output voltage Vout is output to the load Lo.

[0007] Figure 11 shows the waveforms of each signal in the switching power supply Psw of Figure 10 under light load conditions. Because the load current is small, the decrease in output voltage Vout is gradual even when signal S is at a low level (transistor 96 is in the off state), and therefore, throughout the period shown in Figure 11, the output voltage Vout remains around the target voltage Vta. During the period up to time T1 in Figure 11, the output voltage Vout is either above or slightly below the target voltage Vta, and the error signal Ser is below the minimum value of the sawtooth comparison signal Sc throughout the entire period up to time T1. Therefore, during the period up to time T1, signal S does not contain high-level pulses, meaning that transistor 96 remains in the off state, but because the decrease in output voltage Vout is gradual, the error signal Ser rises slowly at a level lower than the level of the comparison signal Sc.

[0008] Subsequently, when the error signal Ser reaches the minimum value of the comparison signal Sc at time T1, and the level of the error signal Ser becomes greater than the level of the comparison signal Sc, a high-level pulse is output as signal S from the PWM comparator 94. Transistor 96 is turned on for the duration of that pulse width, and during that time, the output voltage Vout rises. At time T2, the level of the error signal Ser falls below the level of the comparison signal Sc, so transistor 96 turns off. However, because the load current is small, the output voltage Vout does not drop significantly during this off period, and at time T3, transistor 96 turns on again, causing the output voltage Vout to rise further.

[0009] The fluctuation in the output voltage Vout is normally fed back to the error amplifier 92, causing the error signal Ser, which is its output, to decrease. However, due to the actions of the smoothing circuit 98 and capacitor 922 on the feedback loop, the error signal Ser does not immediately decrease at time points T1 and T3, but only after a delay period based on their actions. For example, in Figure 11, the error signal Ser finally begins to decrease at time point T5. Therefore, at time point T4, as at time points T1 and T3, transistor 96 turns on and the output voltage Vout increases in accordance with the pulse width of signal S. Furthermore, transistor 96 remains on at time points T6 and T7, and the output voltage Vout increases, until the error signal Ser, which began to decrease at time point T5, falls below the minimum amplitude of the comparison signal Sc at time point T8. Then, from time point T8 onward, while the error signal Ser remains below the minimum amplitude of the comparison signal Sc, transistor 96 remains off without switching. This switching stop continues until the decreasing output voltage Vout drops to approximately the same level as the voltage at time T1 and the error signal Ser reaches the lowest value of the comparison signal Sc.

[0010] Thus, in switching power supplies that can easily enter a light-load state where switching is stopped for a certain period due to the small load current, burst operation may occur, which involves repeatedly alternating between periods of continuous switching and periods of switching stoppage. In the light-load state, a large ripple voltage may be generated due to the accumulation of the increase in output voltage Vout caused by switching during burst operation. For example, in Figure 11, a ripple voltage Vop is generated based on the accumulation of the increase in output voltage Vout over five cycles.

[0011] Such ripple voltages not only hinder the stable supply of voltage to the load but can also be a source of noise that can affect the switching power supply and its surrounding circuits. In particular, under light load conditions, the switching stop period accounts for a large portion of the operating period of the switching power supply, so ripple and noise are inherently less likely to occur in the output voltage. Therefore, the increase in ripple voltage and noise generation due to burst operation under such light load conditions is likely to be problematic. Furthermore, in recent years, with the increasing sophistication of control systems for various devices, there has been an increase in applications for devices that operate with relatively small currents, such as peripheral circuits for sensors, whose application fields and number of users are expanding and increasing. For this reason, the generation of large ripple voltages under light load conditions as described above in switching power supplies is likely to become an increasingly problematic issue.

[0012] In view of these problems, the present invention aims to provide a switching power supply control circuit that can suppress ripple in the output voltage during burst operation under light load conditions. [Means for solving the problem]

[0013] A switching power supply control circuit of one embodiment of the present invention outputs a target voltage by switching the circuit between the input and output based on the result of comparing a signal based on the output voltage with a predetermined signal, and also controls the fluctuation of the output voltage. 、 The output voltage The error is fed back and output from the error amplification circuit. A switching power supply control circuit controls a switching power supply that performs burst operation in which the switching is intermittently interrupted with a stop period in accordance with the load current due to a delay between the signal and the power supply, and includes a detection circuit for detecting a predetermined light load state in the switching power supply, and a switching limiting circuit for reducing the number of switching operations in the burst operation while the light load state is detected by the detection circuit. Furthermore, a switching power supply control circuit in another embodiment of one embodiment of the present invention controls a switching power supply that outputs a target voltage by switching an input / output circuit to open and close based on a comparison result between a signal based on an output voltage and a predetermined signal, and performs burst operation in which the switching is intermittent with a stop period in accordance with the load current, wherein the switching power supply control circuit includes a detection circuit for detecting a predetermined light load state in the switching power supply, and a switching limiting circuit for reducing the number of switching operations in the burst operation while the detection circuit is detecting the light load state, wherein the switching limiting circuit is configured to perform a level shift of the signal based on the output voltage while the light load state is detected. Furthermore, a switching power supply control circuit in yet another embodiment of one embodiment of the present invention controls a switching power supply that outputs a target voltage by switching an input / output circuit to open and close based on a comparison result between a signal based on an output voltage and a predetermined signal, and performs burst operation in which the switching is intermittent with a stop period in accordance with the load current, wherein the switching power supply control circuit includes a detection circuit for detecting a predetermined light load state in the switching power supply, and a switching limiting circuit for reducing the number of switches in the burst operation while the light load state is detected by the detection circuit, wherein the switching limiting circuit is configured to skip a portion of a series of pulses generated based on the comparison result and input to the switching limiting circuit and to output a pulse, and is configured to increase the number of portions skipped between pulse outputs each time a pulse output is produced. Furthermore, a switching power supply control circuit in yet another embodiment of one embodiment of the present invention controls a switching power supply that outputs a target voltage by switching an input / output circuit to open and close based on a comparison result between a signal based on an output voltage and a predetermined signal, and performs burst operation in which the switching is intermittent with a stop period in accordance with the load current, wherein the switching power supply control circuit includes a detection circuit for detecting a predetermined light load state in the switching power supply, a switching limiting circuit for reducing the number of switching operations in the burst operation while the detection circuit is detecting the light load state, and a comparison circuit for comparing a signal based on an output voltage and the predetermined signal and outputting a pulse that causes the switching, wherein the predetermined signal is a periodic signal that oscillates with a predetermined amplitude, the detection circuit is configured to detect the light load state when the level of the signal based on the output voltage is less than or equal to a first threshold which is less than or equal to the minimum amplitude of the periodic signal, and the switching limiting circuit is configured to perform a level shift of the signal based on the output voltage while the light load state is detected, and is configured to stop the level shift when the level of the signal based on the output voltage becomes less than or equal to a second threshold which is less than or equal to the minimum amplitude of the periodic signal. [Effects of the Invention]

[0014] According to the switching power supply control circuit of the present invention, ripple in the output voltage during burst operation under light load conditions can be suppressed. [Brief explanation of the drawing]

[0015] [Figure 1] This is a circuit diagram showing an example of a switching power supply control circuit of one embodiment of the present invention. [Figure 2] This is a timing chart showing an example of the signal waveforms for each part of the switching power supply control circuit in the example shown in Figure 1. [Figure 3] This is a circuit diagram showing an example of a detection circuit included in the switching power supply control circuit of one embodiment of the present invention (Figure 1). [Figure 4]It is a circuit diagram showing an example of a level shift circuit included in the switching power supply control circuit of Fig. 1 [Figure 5] It is a circuit diagram showing another example of the switching power supply control circuit according to an embodiment of the present invention [Figure 6] It is a timing chart showing an example of signal waveforms at various parts of the switching power supply control circuit of the example in Fig. 5 [Figure 7] It is a circuit diagram showing an example of a switching limiting circuit included in the switching power supply control circuit of Fig. 5 [Figure 8] It is a circuit diagram showing another example of a switching limiting circuit included in the switching power supply control circuit of Fig. 5 [Figure 9] It is a timing chart showing an example of signal waveforms at various parts of the switching limiting circuit of the example in Fig. 8 [Figure 10] It is a circuit diagram showing a schematic configuration of a conventional switching power supply [Figure 11] It is a timing chart showing an example of signal waveforms at various parts of Fig. 10 DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0016] Embodiments of the switching power supply control circuit of the present invention are described with reference to the drawings. However, the present invention is not limited to the embodiments described below.

[0017] <Configuration and Basic Operation of the Switching Power Supply Control Circuit of the Present Embodiment> Fig. 1 shows a switching power supply control circuit 1 (hereinafter simply referred to as "control circuit 1") which is an example of the switching power supply control circuit according to one embodiment. A main part of a switching power supply 100 is constituted by the control circuit 1, a transistor T connected to an output terminal 1a of the control circuit 1, a diode D and a smoothing circuit LC connected to the transistor T, and two voltage dividing resistors R1 and R2 connected to the smoothing circuit LC. The switching power supply 100 in Fig. 1 is a step-down switching regulator configured to output a target voltage not higher than an input voltage Vin as an output voltage Vout.

[0018] The switching power supply 100 outputs a target voltage as the output voltage Vout by switching the circuit between the input and output based on the comparison result between a signal based on the output voltage Vout (an error signal Ser output from the error amplifier circuit 3 in the example of Figure 1) and a predetermined signal (a comparison signal Sc output from the oscillator circuit 2 in the example of Figure 1). In the switching power supply 100 of Figure 1, this switching is performed by a transistor T. That is, the transistor T intermittently switches the conduction state between the input terminal 101 and the output terminal 102 of the switching power supply 100 by switching between a conduction state and a non-conduction state. The control circuit 1 controls the switching power supply 100 by controlling the timing of the switching of this transistor T using feedback control.

[0019] The output terminal 1a of the control circuit 1 is connected to the control terminal (gate in the example of Figure 1) of transistor T, and one controlled terminal of transistor T (source in the example of Figure 1) is connected to the input terminal 101 of the switching power supply 100, to which the input voltage Vin is input. The other controlled terminal of transistor T (drain in the example of Figure 1) is connected to the cathode of diode D, whose anode is connected to GND. The smoothing circuit LC includes a coil L and a capacitor C connected in series, with one end of coil L connected to the other controlled terminal of transistor T and the cathode of diode D, and one end of capacitor C connected to GND. The connection node of coil L and capacitor C is connected to the output terminal 102 of the switching power supply 100, and the output voltage Vout is output from the output terminal 102 to the load Lo. A series circuit of voltage divider resistors R1 and R2 is connected between the output terminal 102 and GND, and the connection node of voltage divider resistor R1 and voltage divider resistor R2 is connected to the inverting input of the error amplifier circuit 3, providing the feedback voltage Vfb.

[0020] The control circuit 1 in Figure 1 includes an oscillator circuit 2, an error amplifier circuit 3, a reference voltage generation circuit 31, a comparator circuit 4 (PWM comparator), and a driver 5. In the example in Figure 1, the output terminal of the oscillator circuit 2, which outputs a comparison signal Sc, is connected to the inverting input of the comparator circuit 4, and the output terminal of the error amplifier circuit 3, which outputs an error signal Ser, is connected to the non-inverting input of the comparator circuit 4 via a resistor 71. The reference voltage Vref is input to the non-inverting input of the error amplifier circuit 3, and the feedback voltage Vfb of the output voltage Vout of the switching power supply 100 is input to the inverting input of the error amplifier circuit 3. A resistor 32 and a capacitor 33 are inserted in series between the inverting input and output of the error amplifier circuit 3 for stable operation (phase compensation). The output signal S of the comparator circuit 4 is input to the driver 5, and the output of the driver 5 is output from the output terminal 1a of the control circuit 1.

[0021] The oscillator circuit 2, reference voltage generation circuit 31, error amplification circuit 3, comparator circuit 4, and driver 5 included in the control circuit 1 may have the same functions as the oscillator circuit 91, reference voltage Vref generation circuit 93, error amplifier 92, PWM comparator 94, and driver 95 included in the conventional switching power supply control circuit Pc illustrated in Figure 10. A general overview is given below.

[0022] The oscillator circuit 2 generates a comparison signal Sc. The comparison signal Sc may be a periodic signal that oscillates with a predetermined amplitude, causing the signal waveform to repeat at a constant period. For example, the oscillator circuit 2 generates a ramp signal such as a triangular wave signal or a sawtooth wave signal as the comparison signal Sc. The oscillator circuit 2 is not particularly limited in its circuit configuration as long as it can generate a comparison signal Sc such as a ramp signal. The oscillator circuit 2 may be an integrated circuit (IC) configured to generate such a periodic signal, or it may be an oscillator circuit configured by a combination of discrete semiconductor elements and passive components to generate a periodic signal.

[0023] The reference voltage generation circuit 31 generates a reference voltage Vref that is input to the non-inverting input of the error amplification circuit 3. The reference voltage generation circuit 31 can be composed of any circuit capable of generating a constant voltage, such as a bandgap reference. Preferably, the reference voltage generation circuit 31 generates a reference voltage Vref that is (r2 / (r1+r2)) times the target voltage required for the output voltage Vout of the switching power supply 100. r1 and r2 are the resistance values ​​of the voltage divider resistors R1 and R2, respectively. Note that the control circuit 1 does not necessarily have to include the reference voltage generation circuit 31, and the reference voltage Vref may be input from outside the control circuit 1.

[0024] The error amplifier circuit 3 can be configured as an operational amplifier, as shown by the circuit symbol in Figure 1. The error amplifier circuit 3 may be an IC that constitutes an operational amplifier, or it may be realized by a combination of discrete semiconductor elements and passive components. As mentioned above, a reference voltage Vref, which is (r2 / (r1+r2)) times the target voltage of the switching power supply 100, can be input to the non-inverting input of the error amplifier circuit 3 configured as an operational amplifier. On the other hand, a feedback voltage Vfb, which is (r2 / (r1+r2)) times the currently output output voltage Vout, is input to the inverting input. The error amplifier circuit 3 then outputs an error signal Ser that increases or decreases its signal level according to the difference between the target voltage of the switching power supply 100 and the currently output output voltage Vout of the switching power supply 100. In other words, the error amplifier circuit 3 outputs an error signal Ser that is based on the output voltage Vout and indicates the difference between the target voltage and the output voltage Vout.

[0025] The comparator circuit 4 may be composed of a comparator, as shown by the circuit symbol in Figure 1. The comparator circuit 4 may be an IC that constitutes a comparator, or it may be realized by a combination of discrete semiconductor elements and passive components. In the example in Figure 1, the comparator circuit 4 compares the signal S obtained by shifting the level of the error signal Ser based on the output voltage Vout with the comparison signal Sc input from the oscillator circuit 2. The comparator circuit 4 outputs a signal S to the driver 5 that contains a pulse with a time width approximately the same as the duration that the level of signal S is greater than the level of comparison signal Sc. A pulse with approximately the same time width as the pulse contained in signal S is input from the driver 5 to the transistor T, switching the conduction state of the transistor T. In this way, the comparator circuit 4 outputs a pulse that causes the transistor T to switch by comparing the comparison signal Sc with the signal S based on the error signal Ser, i.e., also based on the output voltage Vout.

[0026] The driver 5 outputs a drive signal that switches the conduction state of transistor T based on the signal S input from the comparator circuit 4. The driver 5 is not particularly limited as long as it can supply an appropriate voltage and current to switch the conduction state of the transistor, and can be composed of any buffer circuit or transistor circuit. In the example in Figure 1, the driver 5 may be an inverting buffer that inverts and outputs the high and low levels of the input signal. The driver 5 does not have to be an inverting buffer, and depending on the connection configuration of the reference voltage generation circuit 31, error amplification circuit 3, oscillator circuit 2, and comparator circuit 4, it may be a non-inverting type buffer, for example. Also, the driver 5 may not be present if the comparator circuit 4 has sufficient driving capability for transistor T.

[0027] In the example in Figure 1, transistor T is a P-type FET. However, transistor T may also be an N-type FET. In that case, as mentioned above, the driver 5 may or may not be a non-inverting type buffer circuit. Transistor T may also be a bipolar transistor. Diode D, coil L, and capacitor C can be composed of any diode, coil, and capacitor having characteristics, ratings, and constants suitable for the characteristics and ratings that the switching power supply 100 should have. The resistance values ​​of the voltage divider resistors R1 and R2 can be appropriately selected according to the target voltage and reference voltage Vref of the switching power supply 100, as mentioned above.

[0028] The output voltage Vout of the switching power supply 100 is divided by voltage divider resistors R1 and R2 and input as a feedback voltage Vfb to the inverting input of the error amplifier circuit 3. A negative feedback circuit is formed including the error amplifier circuit 3, comparator circuit 4, driver 5, transistor T, smoothing circuit LC, and voltage divider resistor R1. When the error amplifier circuit 3 operates, the error signal Ser decreases / increases depending on whether the output voltage Vout is high or low relative to the target voltage, so the duty cycle of signal S increases / decreases, and consequently the conduction time of transistor T decreases / increases, causing the output voltage Vout to decrease / increase. As a result, the target voltage is continuously output as the output voltage Vout.

[0029] The control circuit 1 of this embodiment further includes a detection circuit 6 and a switching limiting circuit 7. The control circuit 1 differs from a conventional switching power supply control circuit, an example of which is shown in Figure 10, in that it includes a detection circuit 6 and a switching limiting circuit 7. The detection circuit 6 detects a predetermined light load state in the switching power supply 100. The switching limiting circuit 7 reduces the number of switches based on the comparison result between a signal based on the output voltage Vout and a predetermined signal (signal Sin and comparison signal Sc in Figure 1) in the burst operation described above that occurs while the light load state is detected by the detection circuit 6, as will be described later. Specifically, the switching limiting circuit 7 is configured to suppress the generation of pulses based on the comparison result of the comparison circuit 4 that result in the switching of transistor T.

[0030] The switching limiting circuit 7 reduces the number of switching cycles of transistor T based on the comparison result by the comparator circuit 4 compared to when the switching limiting circuit 7 is not provided. The switching limiting circuit 7 in the example in Figure 1 includes a resistor 71 and a level shift circuit 72. Node N, which is the connection node between resistor 71 and level shift circuit 72, is connected to the non-inverting input of comparator circuit 4. Comparator circuit 4 compares the signal Sin, which is the signal of the error signal Ser after passing through resistor 71, with the comparison signal Sc. The switching limiting circuit 7 in Figure 1 generates a signal Sin, which is a signal in which the level of the error signal Ser has been shifted in the decreasing direction, so that the number of switching cycles is reduced when signal Sin and comparison signal Sc are compared compared.

[0031] In other words, the level shift circuit 72 in the example of Figure 1 is configured to draw current Ish from the error amplifier circuit 3 side of resistor 71 in order to generate such a signal Sin. The voltage drop across resistor 71 due to current Ish generates a signal Sin that has a level lower than the level of the error signal Ser output from the error amplifier circuit 3. Thus, the switching limit circuit 7 in the example of Figure 1 is configured to perform a level shift of the error signal Ser based on the output voltage Vout while a light load state is detected by the detection circuit 6.

[0032] As mentioned above, the oscillator circuit 2, reference voltage generation circuit 31, error amplification circuit 3, comparator circuit 4, and driver 5 included in the control circuit 1 can each have the same functions as the corresponding components of a conventional switching power supply control circuit as illustrated in Figure 10. Therefore, the switching power supply 100 in Figure 1 also performs burst operation in which the switching by transistor T is intermittent with a stop period in between, depending on its load current. However, since the control circuit 1 of this embodiment includes a detection circuit 6 and a switching limiting circuit 7, the number of switches based on the comparison result in the comparator circuit 4 during burst operation under light load conditions is reduced compared to the conventional design. Consequently, the ripple in the output voltage Vout during burst operation under light load conditions can be reduced. The operation of the detection circuit 6 and the switching limiting circuit 7 under light load conditions will be explained further with reference to Figure 1 and Figure 2.

[0033] <Operation and Function of Detection Circuit and Switching Limiting Circuit> Figure 2 shows an example of the signal waveforms of each part of the control circuit 1 in the example shown in Figure 1. The upper part of Figure 2 shows the comparison signal Sc and the error signal Ser, as in Figure 10 which was referred to earlier, as well as the signal Sin, which is obtained by shifting the level of the error signal Sr by the switching limiting circuit 7. Below these, in order, are the detection signal Sd output by the detection circuit 6, the current Ish flowing into the level shift circuit 72 through the resistor 71, the signal S output by the comparison circuit 4, and the output voltage Vout of the switching power supply 100.

[0034] The detection circuit 6 detects that the switching power supply 100 is in a predetermined light load state and outputs a detection signal Sd according to the detection result. The "predetermined light load state" means a state in which the value of the load current supplied from the switching power supply 100 to the load Lo is less than a specific value. For example, the "specific value" may be the value of the load current when the operating mode switches from the current critical mode to the current discontinuous mode in the step-down switching regulator shown in Figure 1. Alternatively, the value of the load current immediately before burst operation starts from the current discontinuous mode can also be selected as the "specific value".

[0035] In a light load state where not much load current flows, the output voltage Vout is unlikely to fall below the target voltage, so a signal at a level that does not cause transistor T to conduct is easily input to the non-inverting input of comparator circuit 4. Therefore, in the control circuit 1 shown in Figure 1, a state in which the level of the error signal Ser output from the error amplifier circuit 3 based on the output voltage Vout is less than or equal to the minimum value of the comparator signal Sc may be detected as a light load state. In the example of Figure 1, the detection circuit 6 shown in Figure 2, where the detection signal Sd is displayed, is configured to detect a light load state when the level of the error signal Sc is less than or equal to a threshold (first threshold) which is less than or equal to the minimum value of the amplitude of the comparator signal Sc, which is a periodic signal. In the example of Figure 2, the detection circuit 6 outputs the detection signal Sd, which becomes high level when a light load state is detected, to the switching limit circuit 7 (specifically, the level shift circuit 72).

[0036] As shown in Figure 2, when the decreasing error signal Ser drops to the first threshold voltage Vth1 at time T11, the detection circuit 6 detects the light load state and causes the detection signal Sd to transition to a high level. In Figure 2, the first threshold voltage Vth1 is set to a value lower than the minimum amplitude of the comparison signal Sc. Note that the reason the error signal Ser changes in the downward direction during the period up to time T11 is that the output voltage Vout changed in the upward direction at an earlier time, which is not shown in Figure 2.

[0037] After time point T11, the error signal Ser begins to rise and exceeds the first threshold voltage Vth1 at time point T12, but the detection circuit 6 maintains the light load state detection state and outputs a high-level detection signal Sd. In this way, even when the detection circuit 6 detects a light load state when the error signal Ser is below the first threshold voltage Vth1, it does not necessarily release the light load state detection state when the error signal Ser subsequently exceeds the first threshold voltage Vth1. Maintaining the light load state detection state can reduce the number of switches in subsequent burst operation.

[0038] Subsequently, at point T13, when the level of the error signal Ser exceeds the level of the comparison signal Sc, the comparison circuit 4 outputs a pulse P1 with signal S based on the comparison result of the two signals. As a result, transistor T becomes conductive, the output voltage Vout begins to rise, and continues to rise while pulse P1 is being output. Then, in the example in Figure 2, at point T13 when this pulse P1 is output, that is, at the rising edge of pulse P1, the level shift circuit 72 begins to flow current Ish. As current Ish flows, a signal Sin is generated, which is the result of shifting the level of the error signal Ser. That is, a signal Sin, whose level is lower than the level of the error signal Ser by the product of the current Ish and the resistance value of resistor 71, is input to the non-inverting input of the comparison circuit 4. The level shift circuit 72 continues to flow current Ish as long as the detection state of the light load state by the detection circuit 6 is maintained.

[0039] Subsequently, at time T14, pulse P2 is output based on the comparison result between signal Sin and comparison signal Sc. However, since the level of signal Sin is shifted downwards compared to the level of error signal Ser, the duration of pulse P2 is shorter than the duration of pulse P3, which would be output if error signal Ser and comparison signal Sc were compared. The output voltage Vout rises only for a duration corresponding to this short duration of pulse P2. Therefore, the increase in output voltage Vout due to switching based on pulse P2 is smaller than the increase in output voltage Vout due to pulse P3.

[0040] Subsequently, at time points T15 and T16, the level of the error signal Ser exceeds the level of the comparison signal Sc. However, the level of the signal Sin is lower than the level of the error signal Ser, and is approximately the same as or lower than the level of the comparison signal Sc. Therefore, pulses P4 and P5, which would be output when the error signal Ser and the comparison signal Sc are compared, are not output. Consequently, the number of switching cycles of transistor T can be reduced. As a result, the ripple voltage Vop of the output voltage Vout can be made smaller than the ripple voltage in conventional switching power supplies.

[0041] In the example shown in Figure 2, after the start of current Ish suction, the current value of Ish gradually increases from approximately zero amperes. Therefore, as shown by the vertical axis spacing between the error signal Ser and signal Sin in Figure 2, the amount of the level shift of the error signal Ser increases. Because the amount of the shift increases in this way, the level of the error signal Ser, which rises over time as shown in Figure 2, can be shifted so that the level of signal Sin remains continuously below the level of the comparison signal Sc. Furthermore, if the level shift of the error signal Ser is performed with current Ish at a constant value, even if the error signal Ser is not very large immediately after the start of current Ish suction, if the amount of the level shift is too large, the pulse P1 to make transistor T conduct will not be output from the comparison circuit 4, preventing the output voltage Vout from further decreasing and increasing the ripple of the output voltage Vout. Thus, in this embodiment, the switching limiting circuit 7 may be configured to gradually increase the amount of the level shift of the error signal Ser by the level shift circuit 72.

[0042] In Figure 2, between time points T15 and T16, the effects of switching at time point T13 and other points appear in the error signal Ser after a delay, and the error signal Ser begins to decrease. Subsequently, at time point T17, when the error signal Ser drops below the second threshold voltage Vth2, the detection circuit 6 releases the detection state for the light load condition and transitions the detection signal Sd to a low level. Accordingly, the level shift circuit 72 stops suctioning current Ish. That is, the level shift of the error signal Ser is stopped, and the level of the error signal Ser is input to the comparator circuit 4 almost unchanged.

[0043] In the example in Figure 2, the second threshold voltage Vth2 is set to a voltage approximately equal to the minimum amplitude of the periodic comparison signal Sc. When the error signal Ser has dropped to a voltage level below the minimum amplitude of the comparison signal Sc, switching that increases the ripple of the output voltage Vout cannot occur even without shifting the level of the error signal Ser. Therefore, unnecessary power consumption due to current Ish can be prevented by stopping the level shift. Note that the second threshold voltage Vth2 may be a voltage lower than the minimum amplitude of the comparison signal Sc. In that case, even if the signal Ser is near the minimum amplitude of the comparison signal Sc when the level shift due to current Ish stops, no pulse will be output to the signal S, thus more reliably preventing the occurrence of switching that increases the ripple of the output voltage Vout. Thus, the switching limiting circuit 7 may be configured to stop the level shift of the error signal Ser when the level of the error signal Ser based on the output voltage falls below a threshold (second threshold) that is below the minimum amplitude of the comparison signal Sc.

[0044] Subsequently, at time T18, when the error signal Ser drops to below the first threshold voltage Vth1, the detection circuit 6 detects the light load state again and causes the detection signal Sd to transition to a high level. Although not shown in the figure, the level shift of the error signal Ser may occur in accordance with the change in the error signal Ser, as in the period from time T13 to time T17. In the example in Figure 2, the first threshold voltage Vth1 (first threshold) is smaller than the second threshold voltage Vth2 (second threshold). Therefore, even if there are temporary fluctuations in the error signal Ser due to noise, the operation of the switching limiting circuit 7 is less likely to become unstable. Furthermore, by appropriately setting the voltage difference between the first threshold voltage Vth1 and the second threshold voltage Vth2, when the load current increases and the system switches from current discontinuous mode to current continuous mode, it is possible to prevent the detection circuit 6 from mistakenly detecting the light load state, and to prevent an excessive drop in the output voltage due to the rapid resumption of current Ish suction and excessive suppression of switching.

[0045] As mentioned above, in the example in Figure 2, after the detection of a light load state, the level shift of the error signal Ser is started at time T13 in conjunction with the output of pulse P1. In other words, the switching limit circuit 7 is configured to start flowing current Ish and starting the level shift of the error signal Ser when transistor T makes its first switch after the detection circuit 6 detects a light load state. With the switching limit circuit 7 configured in this way, compared to the case where current Ish is started to flow at the same time as the detection circuit 6 detects a light load state, the pulse P1 that causes transistor T to conduct is not output, which can suppress the increase in ripple of the output voltage Vout and the power consumption caused by unnecessarily flowing current Ish. To enable the start of the level shift at such a timing, in the example in Figure 1, the output terminal of the comparison circuit 4 is connected to the level shift circuit 72 and the signal S is input to the level shift circuit 72.

[0046] Furthermore, the switching limiting circuit 7 may be configured to start a level shift when the level of the error signal Ser, based on the output voltage Vout, becomes equal to or greater than the minimum amplitude of the comparison signal Sc (the second threshold voltage Vth2 in the example of Figure 2), after the detection circuit 6 has detected a light load state. Even in this case, it may be possible to suppress the increase in ripple of the output voltage Vout and power consumption compared to the case where the current Ish is started to flow at least as soon as the detection circuit 6 detects a light load state. Also, if the level of the error signal Ser has risen to or greater than the minimum amplitude of the comparison signal Sc, a pulse P1 will soon be output in signal S, so the power loss is not considered to be so great compared to the start of the level shift in Figure 2. In this case, the output terminal of the comparison circuit 4 and the level shift circuit 72 do not need to be connected as shown in Figure 1.

[0047] In the examples shown in Figures 1 and 2, the detection circuit 6 monitors a signal (error signal Ser) to detect a light load state, and the comparison circuit 4 compares this signal (signal Sin) with the comparison signal Sc. This makes it possible to appropriately detect a predetermined light load state while reducing the number of switches that increase the ripple voltage.

[0048] <Examples of detection circuits and level shift circuits> Figures 3 and 4 show examples of the detection circuit 6 and level shift circuit 72 included in the control circuit 1 of Figure 1, respectively. Note that the circuits shown in Figures 3 and 4 are merely examples of the detection circuit 6 and level shift circuit 72, and the circuits are not limited to those shown in Figure 3 or Figure 4.

[0049] The detection circuit 6 in the example shown in Figure 3 includes two comparators 6a and 6b, a D flip-flop 6c with an asynchronous reset terminal, a first threshold voltage generation circuit 6d, and a second threshold voltage generation circuit 6e. An error signal Ser is input to the non-inverting inputs of each of the comparators 6a and 6b. A detection signal Sd is output from the inverting output terminal QB of the D flip-flop 6c.

[0050] When the error signal Ser falls below the first threshold voltage Vth1, a low-level signal is input to the reset terminal RES of the D flip-flop 6c, and a high-level detection signal Sd is output from its inverted output terminal QB. A high-level signal is also input to the input terminal D from the inverted output terminal QB. Note that even if the error signal Ser subsequently rises above the first threshold voltage Vth1, the high-level signal from comparator 6a does not affect the operation of the D flip-flop 6c. Subsequently, when the error signal Ser rises and then falls below the second threshold voltage Vth2, the output of comparator 6b inverts and the falling edge is input to the clock terminal CK of the D flip-flop 6c, so a low-level detection signal Sd, which is the inverted signal of the high-level signal that was input to input terminal D, is output from the inverted output terminal QB of the D flip-flop 6c. In this way, for example, the circuit shown in Figure 3 can be used to configure a detection circuit 6 that outputs the detection signal Sd as in the example in Figure 2.

[0051] The level shift circuit 72 in the example shown in Figure 4 includes a D flip-flop 7a with an asynchronous reset terminal, MOS field-effect transistors (MOSFETs) 7b and 7c, a constant current source 7d, a capacitor 7e, an operational amplifier 7f, and a resistor 7g. A detection signal Sd is input from the detection circuit 6 to the input terminal D and reset terminal RES of the D flip-flop 7a, and a signal S is input from the comparator circuit 4 to the clock terminal CK. The drain of MOSFET 7c is connected to node N of the control circuit 1 in Figure 1, and a current Ish is drawn in from the error amplifier circuit 3 between the drain and source of MOSFET 7c.

[0052] When the detection circuit 6 does not detect a light load state, a low-level detection signal Sd is input to the input terminal D and reset terminal RES of the D flip-flop 7a, so the D flip-flop 7a is reset and a high-level signal is output from the inverting output terminal QB. MOSFET 7b turns on, causing capacitor 7e to discharge, and the source of MOSFET 7c becomes approximately GND potential, resulting in almost no current Ish flowing, in order to create an imaginary short between the inputs of the operational amplifier 7f. Even if the detection circuit 6 detects a light load state, this state does not change; only a high-level signal is input to the input terminal D and reset terminal RES of the D flip-flop 7a. When the rising edge of a pulse like pulse P1 in Figure 2 is input to the clock terminal CK by signal S, a low-level signal, which is the inverse of the level of input terminal D, is output from the inverting output terminal QB, turning MOSFET 7b off. Charging of capacitor 7e by current from constant current source 7d begins, and an increasing current Ish flows so that a potential difference corresponding to the voltage between its two terminals appears between the terminals of resistor 7g. Subsequently, when detection circuit 6 releases the light load detection state, a low-level input to reset terminal RES by detection signal Sd causes a high-level signal to be output from inverting output terminal QB, and as MOSFET 7b transitions to the off state, capacitor 7e is rapidly discharged, and the absorption of current Ish stops. In this way, for example, the circuit shown in Figure 4 can be used to configure a level shift circuit 72 that flows current Ish as in the example in Figure 2. Note that if a constant current is to flow when the level shift of error signal Ser begins, for example, a resistor can be connected between the current source 7d and GND instead of capacitor 7e in Figure 4, and the level shift circuit 72 may be more simply configured with a combination of a logic circuit that takes detection signal Sd and signal S as inputs, a switching element such as a transistor, and a constant current source.

[0053] <Other examples of switching power supply control circuits of this embodiment> Figure 5 shows another example of the switching power supply control circuit of this embodiment, a switching power supply control circuit 10 (hereinafter also simply referred to as "control circuit 10"). The control circuit 10 in Figure 5 includes a switching limiting circuit 70 instead of the switching limiting circuit 7 in the example in Figure 1. The control circuit 10 differs from the control circuit 1 in Figure 1 only in the configuration relating to the switching limiting circuit 70. For components similar to those in the control circuit 1 in Figure 1, the same reference numerals as in Figure 1 are used in Figure 5, or they are omitted as appropriate, and repeated explanations of these similar components are also omitted as appropriate.

[0054] In the control circuit 10 of Figure 5, the switching limiting circuit 70 is inserted between the comparator circuit 4 and the driver 5. The switching limiting circuit 70 is connected to the detection circuit 6, similar to the switching limiting circuit 7 in Figure 1, and receives a detection signal Sd from the detection circuit 6. The switching limiting circuit 70 is configured to skip a portion of the series of pulses Ps that are generated based on the comparison result between the error signal Ser from the comparator circuit 4 and the comparison signal Sc, and to output pulses. That is, in the example of Figure 5, while the detection circuit 6 detects a light load state, the switching limiting circuit 70 decimates a portion of the series of pulses Ps included in the signal S output from the comparator circuit 4, and outputs a signal St to the driver 5 that includes pulses Pt corresponding to the pulses that were not decimated from the series of pulses Ps. Since the pulses output from the comparator circuit 4 are decimated, and the transistor T switches based only on the pulses that were not decimated, the number of switches is reduced. Therefore, ripple in the output voltage Vout during burst operation at light load can be suppressed.

[0055] Figure 6 shows an example of the signal waveforms of each part of the control circuit 10 in the example shown in Figure 5. The upper part of Figure 5 shows the comparison signal Sc and the error signal Ser, as previously referenced in Figure 2. Below that, in order, are the detection signal Sd output by the detection circuit 6, the signal S output by the comparison circuit 4, the signal St output by the switching limiting circuit 7, and the output voltage Vout of the switching power supply 100. Note that in Figure 6, a light load condition has already been detected before the time period shown in Figure 6.

[0056] In Figure 6, when the error signal Ser exceeds the comparison signal Sc at time T21, pulse P1 is output from the comparison circuit 4 in signal S. Subsequently, the comparison circuit 4 sequentially outputs pulses P2 to P5 based on the comparison result between the error signal Ser and the comparison signal Sc. The switching limit circuit 7 skips a portion of the series of pulses Ps, including these pulses P1 to P5, and outputs a signal St that includes pulses Pt corresponding to the pulses that were not skipped. Note that "pulses corresponding to the pulses that were not skipped" means pulses that rise and fall approximately simultaneously with the pulses that were not skipped.

[0057] In the example in Figure 6, at time T21, pulse Pt1 corresponding to pulse P1 is output, but at time T22, pulse P2 is skipped, and no pulse is output in signal S. Then, at time T23, pulse Pt2 corresponding to pulse P3 is output. In other words, the switching limiting circuit 7 skips one of the pulses Ps in the sequence between the output of pulse Pt1 and the output of pulse Pt2. Therefore, at time T22, the output voltage Vout continues to change in the downward direction without rising. As a result, the output voltage Vout at time T23 can reach a lower voltage level than when the pulse was not skipped at time T22. At time T23, the output voltage Vout starts to rise based on pulse Pt2, but in this rise, the output voltage Vout can only reach a lower voltage than when the pulse was not skipped at time T22. Therefore, the ripple voltage Vop generated in the output voltage Vout can be made smaller than the ripple voltage in conventional switching power supplies.

[0058] After time point T23, not only is pulse P4, which follows pulse P3, skipped, but at time point T24, the next pulse P5 is also skipped. Subsequently, at time point T25, the light load detection state is released. In other words, the switching limit circuit 7 skips at least two pulses sent from the comparator circuit 4 between the output of pulse Pt2 and the output of the next pulse. Thus, the number of pulses that the switching limit circuit 7 skips between its two consecutive pulse outputs can be any number other than 1.

[0059] Furthermore, the number of pulses skipped may be constant or vary during one detection period of a light load state. In the example in Figure 6, the switching limiting circuit 7 increases the number of pulses skipped between the output of pulse Pt2 and, if there is another pulse output (not shown), compared to the number of pulses skipped between pulse Pt1 and pulse Pt2. In this way, the switching limiting circuit 7 may increase the number of pulses it skips between pulse outputs such as pulse Pt1 and pulse Pt2 based on a series of pulses Ps from the comparator circuit 4 during one detection period of a light load state by the detection circuit 6. By gradually increasing the number of pulses skipped, it is possible to effectively suppress the rise in output voltage Vout in response to the increase in the time width of each pulse in a series of pulses Ps, thereby reducing the ripple voltage Vop.

[0060] The switching limiting circuit 7 may increase the number of skipped pulses sequentially by 1, starting from 1, or by any number of 2 or more. The switching limiting circuit 7 may increase the number of skipped pulses from any specific number of 2 or more. Furthermore, if the switching limiting circuit 7 increases the number of skipped pulses during one detection period of a light load state, it may increase the number of skipped pulses from the number before the increase during the next detection period of a light load state. The number of skipped pulses and the increase in the number of skipped pulses can be appropriately selected according to the magnitude of the load current used to detect the light load state, the input voltage Vin and output voltage Vout, etc.

[0061] <Example of a switching limiting circuit that skips pulses> Figure 7 shows a switching limiting circuit 701, which is an example of a switching limiting circuit 70 that skips pulses, included in the control circuit 10 of Figure 5. The switching limiting circuit 701 is an example of a switching limiting circuit 70 that skips one pulse at a time in the series of pulses Ps shown in Figure 6, each time a pulse is output. The switching limiting circuit 701 includes a D flip-flop 70a with an asynchronous set terminal, two inverters 70b and 70c, and an AND gate 70d. The detection signal Sd from the detection circuit 6 is input to inverter 70b, and the signal S output by the comparator circuit 4 is input to inverter 70c and also to one input terminal of the AND gate 70d. The AND gate 70d outputs a signal St containing the pulse corresponding to the pulse that was not skipped. The inverting output terminal QB and input terminal D of the D flip-flop 70a are connected, and an inverted signal is output from the output terminal Q for each rising edge input to the clock terminal CK, and input to the other input terminal of the AND gate 70d.

[0062] While the detection circuit 6 does not detect a light load state, a low-level detection signal Sd is input, so a high-level signal is input from inverter 70b to the SET terminal of D flip-flop 70a. Since the output terminal Q of D flip-flop 70a is set to a high level, the AND gate 70d outputs a signal St at the same level as signal S. In other words, the pulse of signal S is not skipped.

[0063] On the other hand, when a light load condition is detected, the output terminal Q of the D flip-flop 70a, which has its clock terminal CK connected to the output terminal of inverter 70c, outputs a signal to the AND gate 70d that is invariant on the rising edge of signal S and inverted on the falling edge. The logical AND of this input signal from the D flip-flop 70a and signal S is output as signal St from the AND gate 70d. As a result, a series of pulses of signal S are skipped one by one, and signal St, which includes the pulses corresponding to the unskipped pulses, is output from the AND gate 70d. In this way, for example, the circuit shown in Figure 7 can be used to configure a switching limiting circuit that skips a series of input pulses one by one each time a pulse is output.

[0064] Figure 8 shows a switching limiting circuit 702, which is another example of a switching limiting circuit 70 that skips pulses, included in the control circuit 10 of Figure 5. Switching limiting circuit 702 is an example of a switching limiting circuit 70 that sequentially increases the number of pulses to skip by one each time a pulse is output, starting from 1. Switching limiting circuit 702 includes a ring counter 71a, an edge detection circuit 71b, a group of D flip-flops (DFFs) 71c, a group of AND gates 71d, and an AND gate 71e. The signal S from the comparison circuit 4 is input to one input terminal 71f of the AND gate 71e and is also inverted and input to the clock terminal CK of each DFF group 71c. The detection signal Sd from the detection circuit 6 is inverted and then input to the reset terminal RES of each DFF group 71c as a logical OR with the output signal Sf of the edge detection circuit 71b. The signal St, which is the output signal of the switching limiting circuit 702, is output from the AND gate 71e and is also input to the edge detection circuit 71b. Each time a falling edge of signal St is detected, a signal Sf that remains high for a predetermined period of time is output from the edge detection circuit 71b.

[0065] The operation of the switching limiting circuit 702 will be explained with reference to Figures 8 and 9. Figure 9 shows, in order from the top, the signal S output from the comparator circuit 4, the output signal St from the switching limiting circuit 702, the signal Sf output from the edge detection circuit, the signals SH1 to SH4 which are the output signals of each FF in the DFF group 71c, and the outputs Q1 to Q4 of the ring counter 71a. Note that each pulse of signal S is shown with the same time width for ease of understanding. Figure 9 also shows the waveforms of each signal when a light load state is detected by the detection circuit 6. In the state not shown, where a light load state is not detected, the ring counter 71a is reset by the inverted signal of the detection signal Sd, so a high level is always input to the input terminal 71g of the AND gate 71e, which is not the input terminal of signal S. Therefore, a signal St containing pulses that are approximately the same as those of signal S is output. In other words, the pulses of signal S are not skipped.

[0066] On the other hand, when a light load state is detected, the ring counter 71a shifts the high-level pulse output in the order of output signals Q1→Q2→Q3→Q4 each time a pulse is output at the output signal St of the switching limit circuit 702 and that pulse falls (at times T31, T33, T35, and T37). The DFFs in the DFF group 71c are cascaded together, and the input terminal D of the first-stage DFF (the DFF that outputs signal SH1) is connected to its inverting output terminal QB. Furthermore, at each falling edge of signal St, a high-level signal is input to the reset terminal RES of each DFF by signal Sf. Therefore, in the DFF group 71c, the first-stage DFF shifts the output signal SH1 to a high level each time signal S falls, which does not coincide with the falling edge of signal St (at time T32, etc.). Each subsequent DFF transitions output signals SH2-SH4 to a high level each time the falling edge of signal S does not coincide with the falling edge of signal St, while the preceding DFF is outputting high-level output signals SH1-SH3 (at points T34, T36, and T38). Then, at each falling edge of signal St, each DFF transitions output signals SH1-SH4 to a low level.

[0067] The logical AND of the signals SH1, SH2, SH3, and SH4, whose levels transition in this manner, with signals Q1, Q2, Q3, and Q4, respectively, is output from each AND gate in the AND gate group 71d. The logical OR of all these AND gate outputs is input to the other terminal 71g of the AND gate 71e. Therefore, the other terminal 71g of the AND gate 71e receives a signal that is high only during the periods when both signals SH1 and Q1, both signals SH2 and Q2, both signals SH3 and Q3, or both signals SH4 and Q4 are at a high level (times T32 to T33, T34 to T35, T36 to T37, and T38 to T39). The number of pulses of signal S included in each period when this signal is at a low level increases by 1 as time progresses from T31 to T39. The logical AND of the signal input to terminal 71g of this AND gate 71e and the signal S input to terminal 71f is output as signal St. Therefore, the number of pulses to skip from the pulses contained in signal S can be increased by 1 each time a pulse is output.

[0068] Thus, for example, the circuit shown in Figure 8 can skip a series of input pulses, and a switching limiting circuit can be configured that increases the number of pulses to be skipped by 1 each time a pulse is output. Although Figure 8 is an example of a switching limiting circuit that can increase the number of pulses to be skipped up to 4, the number of pulses to be skipped can be increased to any number other than 4 by increasing or decreasing the number of outputs of the ring counter 71a, the number of DFFs in the DFF group 71c, and the number of AND gates in the AND gate group 71d.

[0069] Note that the switching limiting circuits 701 and 702 shown in Figures 7 and 8 are merely examples of the switching limiting circuit 70 in the example of Figure 5. The circuit that skips the pulses output from the comparison circuit 4, as shown in Figures 5 and 6, can be composed of any circuit capable of thinning out a portion of the input pulses and outputting them.

[0070] The switching control circuits of this embodiment have been described using PWM-controlled switching control circuits 1 and 10 as examples with reference to Figures 1 and 5, but the application of the concept of this embodiment is not limited to PWM-controlled switching control circuits. That is, the concept of reducing the number of switches during burst operation at light loads to reduce output voltage ripple can be applied to switching power supplies with any control method that performs burst operation at light loads. [Explanation of Symbols]

[0071] 1.10 Switching power supply control circuit (control circuit) 100 Switching Power Supply 2. Oscillator Circuit 3. Error Amplifier Circuit 4. Comparator Circuit (PWM Comparator) 6. Detection circuit 7, 70, 701, 702 Switching limiting circuits 71 Resistors 72 Level Shift Circuit Ps series of pulses S is the output signal of the comparator circuit (the signal that causes switching). Sc comparison signal (predetermined signal) Ser error signal (a signal based on output voltage) The signal obtained by level-shifting the sine error signal (a signal based on the output voltage). St Switching Limiting Circuit Output Signal Vout output voltage Vop ripple voltage

Claims

1. A switching power supply control circuit controls a switching power supply that outputs a target voltage by switching the circuit between the input and output based on the comparison result between a signal based on the output voltage and a predetermined signal, and performs burst operation in which the switching is intermittently interrupted with a stop period in accordance with the load current due to the delay between the fluctuation of the output voltage and the error signal output from the error amplification circuit, which is fed back from the output voltage, A detection circuit for detecting a predetermined light load state in the switching power supply, A switching limiting circuit that reduces the number of switching operations during the burst operation while the detection circuit is detecting the light load state, A switching power supply control circuit that includes this.

2. The switching power supply control circuit according to claim 1, wherein the switching limiting circuit is configured to suppress the generation of pulses based on the comparison result that brings about the switching.

3. The system further includes a comparison circuit that compares a signal based on the output voltage with a predetermined signal and outputs a pulse that brings about the switching, The aforementioned predetermined signal is a periodic signal that oscillates with a predetermined amplitude. The switching power supply control circuit according to claim 1 or 2, wherein the detection circuit is configured to detect the light load state when the level of the signal based on the output voltage is less than or equal to a first threshold which is less than or equal to the minimum amplitude of the periodic signal.

4. A switching power supply control circuit controls a switching power supply that outputs a target voltage by switching open and closed the circuit between the input and output based on the result of comparing a signal based on the output voltage with a predetermined signal, and also performs a burst operation in which the switching is interrupted with a stop period in accordance with the load current, The aforementioned switching power supply control circuit is A detection circuit for detecting a predetermined light load state in the switching power supply, A switching limiting circuit that reduces the number of switching operations during the burst operation while the detection circuit is detecting the light load state, Includes, A switching power supply control circuit is configured to perform a level shift of the signal based on the output voltage while the light load state is detected.

5. The switching power supply control circuit according to claim 4, wherein the switching limiting circuit is configured to gradually increase the amount of the level shift.

6. The switching power supply control circuit according to claim 1 or 2, wherein the switching limiting circuit is configured to skip a portion of the series of pulses generated based on the comparison result and input to the switching limiting circuit, and to output pulses.

7. A switching power supply control circuit controls a switching power supply that outputs a target voltage by switching open and closed the circuit between the input and output based on the result of comparing a signal based on the output voltage with a predetermined signal, and also performs a burst operation in which the switching is interrupted with a stop period in accordance with the load current, The aforementioned switching power supply control circuit is A detection circuit for detecting a predetermined light load state in the switching power supply, A switching limiting circuit that reduces the number of switching operations during the burst operation while the detection circuit is detecting the light load state, Includes, A switching power supply control circuit is configured to skip a portion of a series of pulses generated based on the comparison result and input to the switching limit circuit, and to increase the number of the portion skipped between pulse outputs each time a pulse output is generated.

8. A switching power supply control circuit controls a switching power supply that outputs a target voltage by switching open and closed the circuit between the input and output based on the result of comparing a signal based on the output voltage with a predetermined signal, and also performs a burst operation in which the switching is interrupted with a stop period in accordance with the load current, The aforementioned switching power supply control circuit is A detection circuit for detecting a predetermined light load state in the switching power supply, A switching limiting circuit that reduces the number of switching operations during the burst operation while the detection circuit is detecting the light load state, A comparison circuit that compares a signal based on the output voltage with a predetermined signal and outputs a pulse that causes the switching, Includes, The aforementioned predetermined signal is a periodic signal that oscillates with a predetermined amplitude. The detection circuit is configured to detect the light load state when the level of the signal based on the output voltage is below a first threshold that is less than or equal to the minimum amplitude of the periodic signal. The aforementioned switching limiting circuit is The system is configured to perform a level shift of the signal based on the output voltage while the light load condition is detected, and The system is configured to stop the level shift when the level of the signal based on the output voltage falls below a second threshold, which is less than or equal to the minimum amplitude of the periodic signal. Switching power supply control circuit.

9. The switching power supply control circuit according to claim 8, wherein the first threshold is smaller than the second threshold.

10. The switching power supply control circuit according to claim 8, wherein the switching limiting circuit is configured to initiate the level shift during the first switching after the detection of the light load state by the detection circuit.

11. The switching power supply control circuit according to claim 8, wherein the switching limiting circuit is configured to start the level shift when the level of the signal based on the output voltage becomes equal to or greater than the minimum amplitude of the periodic signal after the detection circuit has detected the light load state.

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