Communication device

Abstract

To provide a communication device and a communication method, capable of diagnosing a failure of a signal line without stopping a transmission signal through the signal line.SOLUTION: According to the present embodiment, a communication device includes a transmission unit and a reception unit. The transmission unit is capable of transmitting a transmission signal that includes at least one predetermined signal value of two values and that complies with a first rule, through a signal line. The reception unit outputs a first signal when the signal received through the signal line includes a transmission signal according to the first rule, and outputs a second signal indicating that the signal line is valid when a signal having the same value as the signal value is received.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a communication device and a communication method. [Background Art]

[0002] Along with miniaturization, the occurrence frequency of signal line failures has increased, and the impact thereof has become greater. For this reason, there is a demand for diagnosing failures (open, short, bridge, crosstalk, etc.) including signal lines connecting each device or each circuit. [Prior Art Document] [Patent Document]

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2012-242338 [Summary of Invention] [Problem to be Solved by Invention]

[0004] A problem to be solved by the present invention is to provide a communication device and a communication method that enable failure diagnosis of a signal line without stopping a transmission signal transmitted through the signal line. [Means for Solving Problem]

[0005] According to the present embodiment, a communication device includes a transmission unit and a reception unit. The transmission unit is capable of transmitting, via a signal line, a transmission signal that includes at least one predetermined signal value among two binary values and conforms to a first rule. When a signal received via the signal line includes the transmission signal conforming to the first rule, the reception unit outputs a first signal, and when a signal having the same value as the signal value is received, outputs a second signal indicating that the signal line is valid. [Brief Description of Drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a configuration example of the communication device according to the first embodiment. [Figure 2]A time chart showing examples of transmission path failures. [Figure 3] A time chart showing each signal generated by the communication device according to this embodiment. [Figure 4] A block diagram showing an example configuration of a communication device according to the second embodiment. [Figure 5] A block diagram showing an example of a filter circuit configuration. [Figure 6] A time chart showing each signal generated by the communication device according to the second embodiment. [Figure 7] A time chart showing each signal when the period of the diagnostic pulse signal S12 is 4 clock cycles. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the characteristic configurations and operations of the communication device and communication method will be described, but there may be other configurations and operations of the communication device and communication method that are omitted in the following description.

[0008] (First Embodiment) Figure 1 is a block diagram showing an example configuration of a communication device according to the first embodiment. As shown in Figure 1, the communication device 1a is capable of fault diagnosis of the signal line L30 and comprises a transmitting unit 10 and a receiving unit 20. Faults in the signal line L30 include, for example, open circuits, short circuits, bridges, and crosstalk. Further details of the communication device 1a will be described later.

[0009] The transmitting unit 10 is configured in one device or circuit. The receiving unit 20 is configured in the other device or circuit. These two devices or circuits can perform coordinated processing. Therefore, if an abnormal situation such as a failure or shutdown occurs in one device or circuit while the coordinated processing is being performed, the other device or circuit may not be able to perform normal processing unless the related functions of the other device or circuit are stopped. For this reason, when an abnormal situation such as a failure or shutdown occurs in one device or circuit, a transmission signal indicating the abnormality is sent to the other device or circuit via the signal line L30. This allows the other device or circuit to stop the coordinated processing, for example.

[0010] Such abnormal transmission signals are generally high-level signals when the normal state of the signal line is low-level, or low-level signals when the normal state of the signal line is high-level. In other words, a transmission signal has at least one of the values ​​of a binary signal, either high-level or low-level.

[0011] However, when a signal line transmission path typically maintains a high-level signal state or a low-level signal state, it becomes difficult to determine whether this state is due to a transmission path failure or simply because the transmission signal is not being transmitted. For this reason, a diagnostic signal, which has at least the same value as the transmission signal among the binary signals, is transmitted to the signal line for transmission path fault diagnosis. In other words, like the transmission signal, the diagnostic signal is a high-level signal when the normal state is low-level, and a low-level signal when the normal state of the signal line is high-level.

[0012] Figure 2 is a time chart showing a fault diagnosis example using a comparative example of the transmission path. It shows the clock signal S10 and the transmission signal S14. The horizontal axis represents time. Each signal is composed of a binary signal, for example, a high-level signal and a low-level signal. The transmitting unit 10 and the receiving unit 20 receive a common clock signal S10.

[0013] As shown in Figure 2, in the fault diagnosis example using the comparative example, a diagnostic signal having at least one value of the binary signal is transmitted during the operating period. For example, if the normal state is low level, the diagnostic signal is a high level signal. During the diagnostic period, if a high level signal is received during the operating period, it is diagnosed as no fault; if a high level signal is not received, it is diagnosed as a fault. In this embodiment, the normal state of signal line L30 is described as low level, but this is not the only way. For example, equivalent processing can be performed by inverting the high level signal and the low level signal. That is, in the communication device 1a according to this embodiment, it is possible to generate signals using negative logic instead of positive logic.

[0014] In the fault diagnosis example using the comparative example, the duration of the fault detection cycle is predetermined between the two devices or circuits. However, because it is not possible to distinguish between a diagnostic signal and a transmission signal, performing such a diagnosis requires stopping the function of the transmission path during the fault detection cycle and allocating that time to diagnosing signal line faults. Therefore, even if an abnormality actually occurs during the fault detection cycle, the transmission of the transmission signal is temporarily stopped. As a result, in the fault diagnosis example using the comparative example, if an abnormality occurs during the fault detection cycle, a delay occurs in the transmission of the transmission signal.

[0015] To solve these problems, the communication device 1a according to this embodiment has the configuration shown in Figure 1 and generates the signals shown in Figure 3. Specifically, the transmitting unit 10 of the communication device 1a has a signal transmitting unit 100, a pulse generation circuit 102, and a logical OR circuit 104. The receiving unit 20 has a signal receiving unit 200 and a pulse confirmation circuit 202.

[0016] FIG. 3 is a time chart showing each signal generated by the communication apparatus 1a according to the present embodiment. The clock signal S10, the diagnostic pulse signal S12, the transmission signal S14, the OR output signal S16, the diagnostic point P10 of the pulse confirmation circuit, and the receiving unit sampling point P12 are shown. The horizontal axis represents time. Each signal is constituted by, for example, a binary signal of a high-level signal and a low-level signal. The transmitting unit 10 and the receiving unit 20 receive the common clock signal S10.

[0017] As shown in FIG. 1 and FIG. 3, the signal transmitting unit 100 generates a binary transmission signal S14 in accordance with a first rule. That is, according to the present embodiment, the first rule related to the transmission signal S14 is defined such that a signal of one predetermined value among the two binary values is included at a predetermined time point.

[0018] For example, the signal transmitting unit 100 generates, as the transmission signal S14 conforming to the first rule, a signal having a high-level signal at the rising edge of the clock signal S10. As described above, the first rule according to the present embodiment is to generate the transmission signal S14 such that a signal of one predetermined value among the two binary values is included at a predetermined time point.

[0019] On the other hand, the pulse generation circuit 102 periodically generates the diagnostic pulse signal S12 that does not conform to the first rule. That is, the pulse generation circuit 102 generates a binary signal that does not have a high-level signal at the rising edge of the clock signal S10. More specifically, the pulse generation circuit 102 generates the diagnostic pulse signal S12 that has a low-level signal at the rising edge of the clock signal S10 and a high-level signal at the falling edge of the clock signal S10. The period of this diagnostic pulse signal S12 can be made equal to, for example, the period of the clock signal S10. As described above, the pulse generation circuit 102 periodically generates the diagnostic pulse signal S12 that does not conform to the first rule and has a predetermined one of a high level and a low level signal value.

[0020] Note that the signal transmission unit 100 generates, as the first rule, a transmission signal S14 having a high-level signal at the rising edge of the clock signal S10, but the present invention is not limited thereto. For example, when the signal transmission unit 100 generates a signal by negative logic instead of positive logic, the signal transmission unit 100 may generate, as the first rule, a transmission signal S14 having a high-level signal at the falling edge of the clock signal S10. In this case, the pulse generation circuit 102 generates a low-level signal at the falling edge of the clock signal S10, and generates a diagnostic pulse signal S12 having a high-level signal at the rising edge of the clock signal S10. Note that the diagnostic pulse signal S12 according to the present embodiment corresponds to a diagnostic signal.

[0021] The OR circuit 104 outputs, as an OR output signal S16, a logical OR signal of the binary transmission signal S14 generated by the signal transmission unit 100 and the binary diagnostic pulse signal S12 generated by the pulse generation circuit 102, to the signal line L30.

[0022] If the signal value at the receiving unit sampling point P12 is a high level, the signal receiving unit 200 outputs a high-level signal indicating that the transmission signal S14 has been transmitted. This receiving unit sampling point P12 is timing of the rising edge of the clock S10. On the other hand, if the transmission signal S14 has not been transmitted, the signal receiving unit 200 outputs a low-level signal. Note that the high-level signal of the signal receiving unit 200 according to the present embodiment corresponds to a first signal.

[0023] The signal receiving unit 200 has, for example, a D flip-flop. The clock signal S10 is input to the D flip-flop, and the OR output signal S16 is read at the D terminal at the rising edge of the clock signal S10. That is, since the receiving unit sampling point P12 is the rising edge of the clock signal S10, when the OR output signal S16 includes the transmission signal S14 that conforms to the first rule, a high-level signal is captured, and the high-level signal is output from the Q terminal.

[0024] On the other hand, if the OR output signal S16 does not contain the transmission signal S14 that conforms to the first rule, a low-level signal is captured on the rising edge of the clock signal S10, and a low-level signal is output from the Q terminal. In other words, the signal receiving unit 200 outputs a signal that indicates a high level when the transmission signal S14 that conforms to the first rule is included, and a low level when it is not included. This makes it possible for the device or circuit on the receiving unit 20 side to perform control such as stopping processing when the output signal of the signal receiving unit 200 is high level.

[0025] The pulse confirmation circuit 202 outputs a high-level signal indicating that the signal line L30 is valid if the signal value at the pulse confirmation circuit diagnostic point P10 is high-level. In other words, the pulse confirmation circuit 202 outputs a high-level signal indicating that the signal line L30 is valid if it receives a signal with the same value as the transmission signal S14 within a predetermined period. For example, the predetermined period is one clock cycle. Thus, the pulse confirmation circuit 202 outputs a high-level signal if a high-level signal is included in the OR output signal S16 within one clock cycle.

[0026] On the other hand, if the signal value at the pulse confirmation circuit diagnostic point P10 is not high level, a low level signal is output. That is, the pulse confirmation circuit 202 outputs a low level signal if a signal with the same value as the transmission signal S14 is not included within a predetermined period. As described above, the predetermined period is one clock cycle. Thus, the pulse confirmation circuit 202 outputs a low level signal if a high level signal is not included within one clock cycle. As a result, the pulse confirmation circuit 202 outputs a low level signal when the signal line L30 is broken and a high level signal cannot be received. In this embodiment, the high level signal of the pulse confirmation circuit 202 corresponds to the second signal.

[0027] For example, the pulse verification circuit 202 has a D flip-flop that receives the inverted clock signal S10 as input. The clock signal S10 is input inverted to this D flip-flop, and the OR output signal S16 is read at the D terminal at the pulse verification circuit diagnostic point P10, which is the falling edge of the clock signal S10. That is, since the pulse verification circuit diagnostic point P10 is the falling edge of the clock signal S10, if the falling edge of the clock signal S10 contains a high-level signal in the OR output signal S16, the high-level signal is captured and output, for example, from the Q terminal. In this embodiment, the OR output signal S16 is always a high-level signal at the falling edge of the clock signal S10, so the pulse verification circuit 202 always outputs a high-level signal if there is no fault in the signal line L30.

[0028] Furthermore, the pulse verification circuit 202 takes in a low-level signal if the falling edge of the clock signal S10 in the OR output signal S16 and outputs a low-level signal from, for example, the Q terminal. In other words, the pulse verification circuit 202 outputs a low-level signal if the falling edge of the clock signal S10 in the OR output signal S16 does not contain a high-level signal. As a result, the pulse verification circuit 202 always outputs a low-level signal if the signal line L30 is broken or otherwise malfunctioning. Thus, the pulse verification circuit 202 outputs a high-level signal if the falling edge of the clock signal S10 contains a high-level diagnostic pulse signal S12 or a transmission signal S14, and outputs a low-level signal if neither is present.

[0029] As can be seen from the above, the signal receiving unit 200 outputs a high-level signal as the first signal when the OR output signal S16 contains the transmission signal S14 that conforms to the first rule. In this case, the diagnostic pulse signal S12, which is a diagnostic signal, does not conform to the first rule, so even if the signal receiving unit 200 receives only the diagnostic pulse signal S12, it outputs a low-level signal. On the other hand, even if the periods of high-level signals of the transmission signal S14 that conforms to the first rule and the diagnostic pulse signal S12 overlap, the signal receiving unit 200 outputs a high-level signal as the first signal because the OR output signal S16 contains the transmission signal S14 that conforms to the first rule.

[0030] Thus, even when a diagnostic pulse signal S12, which is a diagnostic signal, is periodically transmitted to the signal line L30, the signal receiving unit 200 can still determine the transmission of the transmission signal S14. This allows the transmission signal S14 to be transmitted without delay, even when the fault detection cycle is constantly being repeated.

[0031] On the other hand, the pulse confirmation circuit 202 outputs a high-level signal as a second signal if the falling edge of the clock signal S10 in the OR output signal S16 contains a high-level signal. As a result, the pulse confirmation circuit 202 always outputs a high level as a second signal if the signal line L30 is not broken, so the device or circuit on the receiving unit 20 side can determine that the signal line L30 is normal.

[0032] Furthermore, the pulse confirmation circuit 202 outputs a low-level signal if the falling edge of the clock signal S10 in the OR output signal S16 does not contain a high-level signal. In other words, if the signal line L30 is broken or otherwise disconnected, it will always output a low-level signal. This allows the device or circuit on the receiving unit 20 side to perform control such as stopping processing when the second signal is low level.

[0033] As described above, according to this embodiment, the transmitting unit 10 is capable of transmitting an OR output signal S16 including a transmission signal S14 conforming to the first rule via the signal line L30, and the receiving unit 20 outputs a high-level signal (first signal) when the OR output signal S16 received via the signal line L30 includes a transmission signal S14 conforming to the first rule. As a result, the receiving unit 20 can be configured not to output a high-level signal (first signal) even if it receives only a diagnostic pulse signal S12 that does not conform to the first rule. Furthermore, even if the periods of high-level signals of the transmission signal S14 conforming to the first rule and the diagnostic pulse signal S12 overlap, it is possible to output a high-level signal (first signal) when the OR output signal S16 includes a transmission signal S14 conforming to the first rule.

[0034] Thus, even when a diagnostic pulse signal S12, which is a diagnostic signal, is periodically transmitted to the signal line L30, the signal receiving unit 200 can still determine the transmission of the transmission signal S14. This allows the transmission signal S14 to be transmitted without delay, even when the fault detection cycle is constantly being repeated.

[0035] Furthermore, when the receiving unit 20 receives a high-level signal, it outputs a high-level signal (second signal) indicating that the transmission signal S14 is valid. Therefore, even if the transmission signal S14 and the diagnostic pulse signal S12 are signals with the same high-level value, it is possible to confirm the validity of the signal line L30.

[0036] Furthermore, the transmitting unit 10 periodically transmits a diagnostic pulse signal S12, which does not conform to the first rule and has a high-level signal, to the signal line L30. As a result, the receiving unit 20 periodically receives the diagnostic pulse signal S12, enabling periodic fault diagnosis of the signal line L30 without interfering with the transmission signal S14.

[0037] (Second Embodiment) The communication device 1b according to the second embodiment differs from the communication device 1a according to the first embodiment in that it can perform diagnostic operations at only one of the points of the rising or falling edge of the clock signal S10. The differences from the communication device 1a according to the first embodiment will be explained below.

[0038] Figure 4 is a block diagram showing an example configuration of the communication device 1b according to the second embodiment. The receiving unit 20 differs from the communication device 1a according to the first embodiment in that it further includes a filter circuit 204.

[0039] Figure 5 is a block diagram showing an example configuration of the filter circuit 204. The filter circuit 204 consists of a first circuit 204a and a second circuit 204b, 204c logical AND circuit It also includes a first exclusive OR circuit 204d and a second exclusive OR circuit 204e.

[0040] The first circuit 204a is, for example, a D flip-flop. The first circuit 204a delays the OR output signal S16 received via the signal line L30 by one clock cycle. This D flip-flop reads the OR output signal S16 at the D terminal on the rising edge of the clock signal S10 and outputs it from the Q terminal on the rising edge of the next lock signal S10.

[0041] The second circuit 204b is, for example, a D flip-flop. The second circuit 204b delays the output signal of the first circuit 204a by one clock cycle. This D flip-flop reads the output signal of the first circuit 204a at the D terminal on the rising edge of the clock signal S10 and outputs it from the Q terminal on the rising edge of the next lock signal S10.

[0042] 204c logical AND circuit This refers to the output signals of the first circuit 204a and the second circuit 204b. Logical AND The result signal is output to the signal receiving unit 200. The first exclusive OR circuit 204d performs an exclusive OR operation on the output signals of the first circuit 204a and the second circuit 204b. logic It outputs the result signal of the sum (exOR). The second exclusive OR circuit 204e is the exclusive OR of the outputs of the first exclusive OR circuit 204d and the second circuit 204b. logicThe sum result signal is output to the pulse verification circuit 202.

[0043] Figure 6 is a time chart showing the signals generated by the communication device 1b according to the second embodiment. It shows the clock signal S10, diagnostic pulse signal S12, transmission signal S14, OR output signal S16, receiver input signal S18, first stage output signal S20 of exOR, and pulse confirmation circuit input signal S22. The horizontal axis represents time. Each signal is composed of a binary signal, for example, a high-level signal and a low-level signal.

[0044] As shown in Figure 6, the signal transmission unit 100 generates a binary transmission signal S14 according to the first rule. That is, the first rule in the second embodiment is that the transmission signal S14 maintains one of two predetermined values, either high or low, for a predetermined first period. For example, the transmission signal S14 in the second embodiment maintains a high value for a first period of two clock cycles or more.

[0045] On the other hand, the pulse generation circuit 102 periodically generates a diagnostic pulse signal S12 that does not conform to the first rule. For example, the diagnostic pulse signal S12 has twice the period of the clock signal S10. In other words, the diagnostic pulse signal S12 maintains a high level during a second period that is shorter than a predetermined first period. In this way, the pulse generation circuit 102 periodically generates a diagnostic pulse signal S12 that is different from the transmission signal S14.

[0046] As shown in Figure 5, 204c logical AND circuit This refers to the output signals of the first circuit 204a and the second circuit 204b. Logical AND The resulting signal is output to the signal receiving unit 200 as the receiving unit input signal S18 (see Figure 6). The output signal of the second circuit 204b is the OR output signal S16 with a delay of 2 clock cycles. Therefore, 204c logical AND circuit For OR output signals S16 that maintain a high level signal for two clock cycles, a high-level signal is output, and for OR output signals S16 that cannot maintain a high level signal for two clock cycles, a low-level signal is output.

[0047] As you will see from this, 204c logical AND circuit It outputs a high-level signal if the transmission signal S14, which conforms to the first rule, is included in the OR output signal S16. On the other hand, 204c logical AND circuit The device outputs a low-level signal if the OR output signal S16 contains only the diagnostic pulse signal S12 that does not conform to the first rule. Similarly, if the signal line L30 is broken, the OR output signal S16 is always low level. in In some cases, the first rule is not followed, so a low-level signal is output. Also, the transmission signal S14 that follows the first rule and the diagnostic pulse signal S12 are superimposed, and a high-level signal is output for a period of 2 clock cycles or more. but Even if it is maintained, it will still follow Rule 1, 204c logical AND circuit It outputs a high-level signal.

[0048] As mentioned above, 204c logical AND circuit The receiving unit input signal S18, which is the output signal of the receiver, is input to the signal receiving unit 200. The signal receiving unit 200 then outputs a value equivalent to the receiving unit input signal S18, synchronized with the clock signal S10. That is, the signal receiving unit 200 outputs a high-level signal when the transmission signal S14 that conforms to the first rule is included in the OR output signal S16, and outputs a low-level signal when only the diagnostic pulse signal S12 that does not conform to the first rule is included in the OR output signal S16.

[0049] The first exclusive OR circuit 204d outputs the first stage output signal S20 of the exOR. 204c logical AND circuit The same signal is input. In other words, the first exclusive OR circuit 204d outputs a low-level signal when the transmission signal S14 that follows the first rule is included in the OR output signal S16. It also outputs a high-level signal when only the diagnostic pulse signal S12 is included in the OR output signal S16. Furthermore, it also outputs a low-level signal if the low-level signal persists for a period of 2 clock cycles or more. In other words, the first exclusive OR circuit 204d outputs a low-level signal when the signal line L30 is broken and the OR output signal S16 is always low-level. Ru de a Even in this case, it outputs a low-level signal.

[0050] As described above, the second exclusive OR circuit 204e outputs the result signal of the exclusive OR of the outputs of the first exclusive OR circuit 204d and the second circuit 204b to the pulse verification circuit 202. In other words, if the signal line L30 is broken and the OR output signal S16 is always at a low level, the outputs of both the first exclusive OR circuit 204d and the second circuit 204b are at a low level, so the second exclusive OR circuit 204e outputs a low-level signal to the pulse verification circuit 202.

[0051] On the other hand, the two-exclusive OR circuit 204e outputs a high-level signal to the pulse confirmation circuit 202 if the transmission signal S14 that conforms to the first rule is included in the OR output signal S16, or if only the diagnostic pulse signal S12 is included in the OR output signal S16.

[0052] As can be seen from the above, the signal receiving unit 200 outputs a high-level signal as the first signal when the OR output signal S16 includes the transmission signal S14 that conforms to the first rule. In this case, the diagnostic pulse signal S12, which is a diagnostic signal, does not conform to the first rule, so even if the signal receiving unit 200 receives only the diagnostic pulse signal S12, it outputs a low-level signal. On the other hand, the signal receiving unit 200 also outputs a high-level signal even if the periods of high-level signals of the transmission signal S14 that conforms to the first rule and the diagnostic pulse signal S12 overlap.

[0053] Thus, even when a diagnostic pulse signal S12, which is a diagnostic signal, is periodically transmitted to the signal line L30, the signal receiving unit 200 can still determine the transmission of the transmission signal S14. This allows the transmission signal S14 to be transmitted without delay, even when the fault detection cycle is constantly being repeated.

[0054] On the other hand, the pulse confirmation circuit 202 outputs a high-level signal to the pulse confirmation circuit 202 when the transmission signal S14 that conforms to the first rule is included in the OR output signal S16, or when only the diagnostic pulse signal S12 is included in the OR output signal S16. As a result, if the signal line L30 is not broken or otherwise disconnected, a high level is always output as the second signal, so the device or circuit on the receiving unit 20 side can determine that the signal line L30 is normal.

[0055] Furthermore, the pulse confirmation circuit 202 also outputs a low-level signal if a low-level signal persists for a period of two clock cycles or more. In other words, the pulse confirmation circuit 202 also outputs a low-level signal if the signal line L30 is broken and the OR output signal S16 is always at a low level. This allows the device or circuit on the receiving unit 20 side to determine that an abnormality has occurred in the signal line L30.

[0056] Figure 7 is a time chart showing each signal when the period of the diagnostic pulse signal S12 is 4 clock cycles. As shown in the receiver input signal S18 in Figure 7, the function of the filter circuit 204 is the same, 204c logical AND circuit The device outputs a high-level signal if the transmission signal S14, which conforms to the first rule, is included in the OR output signal S16.

[0057] On the other hand, as shown in the receiving unit input signal S18 in Figure 7, 204c logical AND circuit The system outputs a low-level signal even when only the 4-clock period diagnostic pulse signal S12, which does not conform to the first rule, is included in the OR output signal S16. Therefore, as in Figure 6, the signal receiving unit 200 outputs a high-level signal when the transmission signal S14, which conforms to the first rule, is included in the OR output signal S16, and outputs a low-level signal when only the diagnostic pulse signal S12, which does not conform to the first rule, is included in the OR output signal S16.

[0058] As described above, the first exclusive OR circuit 204d outputs the first stage output signal S20 of the exOR. The first exclusive OR circuit 204d outputs a low-level signal if the transmission signal S14 that conforms to the first rule is included in the OR output signal S16. It also outputs a high-level signal if only the diagnostic pulse signal S12 is included in the OR output signal S16. Furthermore, it also outputs a low-level signal if the low-level signal persists for two clock cycles or more.

[0059] As described above, the second exclusive OR circuit 204e outputs the result signal of the exclusive OR of the outputs of the first exclusive OR circuit 204d and the second circuit 204b to the pulse verification circuit 202. In other words, if the diagnostic pulse signal S12 is low level for more than two clock cycles, the outputs of both the first exclusive OR circuit 204d and the second circuit 204b are low level, so the second exclusive OR circuit 204e outputs the low level signal to the pulse verification circuit 202 as the pulse verification circuit input signal S22.

[0060] On the other hand, the two-exclusive OR circuit 204e outputs a high-level signal to the pulse confirmation circuit 202 as the pulse confirmation circuit input signal S22 when the transmission signal S14 that conforms to the first rule is included in the OR output signal S16, or when only the diagnostic pulse signal S12 is included in the OR output signal S16. Furthermore, when only the diagnostic pulse signal S12 is included in the OR output signal S16, the two-exclusive OR circuit 204e outputs a high-level signal synchronized with the period of the diagnostic pulse signal S12 and with a delay of 2 clock cycles, as shown at point P14 of the pulse confirmation circuit input signal S22. Therefore, the pulse confirmation circuit 202 can determine a fault in the signal line L30 in synchronization with the period of the diagnostic pulse signal S12 by receiving the pulse confirmation circuit input signal S22 in synchronization with the period of the diagnostic pulse signal S12 and with a delay of 2 clock cycles.

[0061] As a result, the device or circuit on the receiving unit 20 side can determine that there is no abnormality in the signal line L30 when a high-level signal is continuously output in synchronization with the 4-clock period of the diagnostic pulse signal S12 and with a delay of 2 clock periods. In this way, even if the period of the diagnostic pulse signal S12 is set to more than three times the clock period, diagnosis of the signal line L30 becomes possible.

[0062] As explained above, according to this embodiment, the first rule relating to the transmission signal S14 is set so that a high level value continues for a first period of two or more cycles of a predetermined clock signal S10. As a result, the receiving unit 20 can be configured not to output a high-level signal (first signal) even if it receives only the diagnostic pulse signal S12, which does not have a high-level value continuing for more than the first period. Furthermore, even if the periods of high-level signals of the transmission signal S14 and the diagnostic pulse signal S12, which follow the first rule, overlap, the receiving unit 200 can still output a high-level signal (first signal) because it follows the first rule. Therefore, even when the diagnostic pulse signal S12, which is a diagnostic signal, is periodically transmitted to the signal line L30, the signal receiving unit 200 can still determine the transmission of the transmission signal S14. As a result, even when the fault detection cycle is constantly being repeated, the transmission signal S14 can be transmitted without delay.

[0063] Furthermore, the transmitting unit 10 periodically transmits a diagnostic pulse signal S12, which does not conform to the first rule and has a high-level signal, to the signal line L30. The two-exclusive OR circuit 204e of the filter circuit 204 outputs a high-level signal as the pulse confirmation circuit input signal S22, synchronized with the period of the diagnostic pulse signal S12 and delayed by two clock cycles, when only the diagnostic pulse signal S12 is included in the OR output signal S16. As a result, the pulse confirmation circuit 202 of the receiving unit 20 receives the pulse confirmation circuit input signal S22, synchronized with the period of the diagnostic pulse signal S12 and delayed by two clock cycles, thereby enabling it to determine a fault in the signal line L30 in synchronization with the period of the diagnostic pulse signal S12.

[0064] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0065] 1a, 1b: Communication device, 10: Transmitter, 20: Receiver, 100: Signal transmitter, 102: Pulse generation circuit, 200: Signal Receiving unit , 202: pulse confirmation circuit, 204: filter circuit, 204a: first circuit, 204b: second circuit, 204c: AND gate 204d: First exclusive OR circuit, 204e: Second exclusive OR circuit, L30: Signal line, S10: Clock signal, S12: Diagnostic pulse signal, S14: Transmission signal.

Claims

1. A communication device that communicates binary signals via signal lines, A transmitting unit capable of transmitting via the signal line a logical OR signal of a transmission signal including at least one predetermined signal value from the two aforementioned values, and a diagnostic pulse signal that does not have the one signal value at a first time point that is repeated periodically, but has the one signal value at a second time point that is repeated periodically and is different from the first time point, A receiving unit that receives the logical OR signal via the signal line, Equipped with, The receiving unit is At a first measurement time point that is periodically repeated in accordance with the first time point that is periodically repeated, if the logical OR signal has one of the signal values, a first signal is output indicating that the transmission signal is included. At a second measurement time point that is periodically repeated in accordance with the second time point that is periodically repeated, if the OR signal has the value of one of the signals, a second signal is output indicating that the signal line is valid. Communication device.

2. The communication device according to claim 1, wherein the transmitting unit and the receiving unit receive a common clock signal, and the first time point and the first measurement time point are the rising or falling edge timings of the clock signal.

3. A communication method for transmitting binary signals via a signal line, A transmission step that enables the transmission of a logical OR signal of a transmission signal including at least one predetermined signal value among the two values, and a diagnostic pulse signal that does not have the one signal value at a first time point that is repeated periodically, but has the one signal value at a second time point that is repeated periodically and is different from the first time point, via the signal line, A receiving step of receiving the logical OR signal via the signal line, Equipped with, In the aforementioned receiving process, At a first measurement time point that is periodically repeated in accordance with the first time point that is periodically repeated, if the logical OR signal has one of the signal values, a first signal is output indicating that the transmission signal is included. At a second measurement time point that is periodically repeated in accordance with the second time point that is periodically repeated, if the OR signal has the value of one of the signals, a second signal is output indicating that the signal line is valid. Communication method.

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