Semiconductor integrated circuits and electronic equipment

Abstract

To provide a semiconductor integrated circuit and electronic equipment which provide both of high quality and high-speed activation.SOLUTION: A semiconductor integrated circuit according to an embodiment of the present invention is a semiconductor integrated circuit for generating a predetermined voltage which has a first circuit which can output a first current based on the predetermined voltage, a second circuit which can output a second current larger than the first current based on the predetermined voltage, a filter circuit which has a capacitor and can filter an output of the first circuit, and a control circuit which controls the first circuit and the second circuit to make the capacitor output the first current from the first circuit and the second current from the second circuit in parallel and which can stop an output of the second current to the capacitor after passage of a first time after output of the second current to the capacitor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This embodiment relates to semiconductor integrated circuits and electronic devices. [Background technology]

[0002] In semiconductor integrated circuits, Band Gap Reference (BGR) circuits are used to generate reference voltages. Because BGR circuits generate the reference potential used in semiconductor integrated circuits, they require low temperature dependence and high voltage stability.

[0003] In mobile communication devices and similar applications, high-speed startup of power supply circuits, including BGR circuits, is required. Furthermore, to improve communication quality, a high power supply rejection ratio (PSRR) is required for the BGR circuits included in the power supply circuits.

[0004] Generally, in power supply circuits, a low-pass filter (LPF) is placed in the output stage to stabilize the power supply voltage. However, because the LPF's capacitive component causes a delay in the rise of the output voltage, it has been difficult to achieve high-speed startup of the power supply circuit. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-114325 [Overview of the project] [Problems that the invention aims to solve]

[0006] One embodiment aims to provide semiconductor integrated circuits and electronic devices that achieve both high quality and high-speed startup. [Means for solving the problem]

[0007] The semiconductor integrated circuit of the embodiment is a semiconductor integrated circuit that generates a predetermined voltage, comprising: a first circuit capable of outputting a first current based on the predetermined voltage; a second circuit capable of outputting a second current greater than the first current and based on the predetermined voltage; a smoothing circuit having a capacitor and capable of smoothing the output of the first circuit; and a control circuit that controls the first circuit and the second circuit to output the first current from the first circuit and the second current from the second circuit to the capacitor in parallel, and to stop outputting the second current to the capacitor after a first time has elapsed since outputting the second current to the capacitor. The control circuit further comprises a third circuit capable of outputting a third current that is greater than the first current, less than the second current, and based on a predetermined voltage, and the control circuit can further control the third circuit to output the first current from the first circuit, the second current from the second circuit, and the third current from the third circuit to the capacitor in parallel, and can stop outputting the third current after a second time has elapsed which is longer than a first time after the third current is output to the capacitor. . [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram showing an example of a semiconductor integrated circuit according to an embodiment. [Figure 2] This flowchart shows an example of control operation in a semiconductor integrated circuit according to an embodiment. [Figure 3] This is a timing chart showing an example of control operation in a semiconductor integrated circuit of an embodiment. [Figure 4] This is a timing chart showing the control operation of a modified example in the semiconductor integrated circuit of the embodiment. [Figure 5] This is a block diagram showing the configuration of the electronic device in the embodiment. [Modes for carrying out the invention]

[0009] (Configuration of the embodiment) Figure 1 shows an example of a semiconductor integrated circuit of an embodiment. The semiconductor integrated circuit 1, which serves as a BGR circuit, includes a voltage source circuit 10, an output circuit 12, a scaling circuit 20, a low-pass filter (LPF) 14, a voltage divider circuit 30, and a control circuit 40. The voltage source circuit 10 includes the output circuit 12. Part of the LPF 14 is included in the scaling circuit 20.

[0010] The voltage source circuit 10 generates a reference voltage. In the example shown in Figure 1, the voltage source circuit 10 includes MOSFETs Q1, Q2, Q5, operational amplifier U, transistors Q3, Q4, and resistors R1 to R4. Each of the MOSFETs Q1 to Q2 has a source connected to the power supply wiring Vdd, gates connected to each other, and drains connected to the ground wiring via resistors R1 to R2. The power supply wiring Vdd is the wiring that supplies the potential that becomes the power supply voltage when the semiconductor integrated circuit 1 is operating. The ground wiring is the wiring that supplies the reference potential when the semiconductor integrated circuit 1 is operating.

[0011] Operational amplifier U has outputs connected to the gates of MOSFETs Q1 and Q2, an inverting input connected to the drain of MOSFET Q1, and a non-inverting input connected to the drain of MOSFET Q2. Transistor Q3 has a base, an emitter connected to the inverting input and base of operational amplifier U, and a collector connected to the ground wire. Transistor Q4 has a base, an emitter connected to the base, and a collector connected to the ground wire. The emitter and base of transistor Q4 are further connected to the non-inverting input of operational amplifier U via resistor R3.

[0012] The operational amplifier U negatively feeds back the difference between the drain voltages of MOSFET Q1 and MOSFET Q2 to the gates of MOSFET Q1 and MOSFET Q2. This helps to keep the drain voltages of MOSFET Q1 and MOSFET Q2 equal. In other words, the operational amplifier U can stabilize the output voltage.

[0013] MOSFET Q5 has a source connected to power supply wiring Vdd, a gate connected to the gates of MOSFETs Q1 to Q2, and a drain connected to ground wiring via resistor R4. MOSFETs Q1, Q2 and Q5 constitute a current mirror. The current mirror and operational amplifier U cooperatively act as a constant current circuit that keeps the drain currents of MOSFETs Q1, Q2 and Q5 constant. MOSFET Q5 and resistor R4 constitute an output circuit 12 included in the voltage source circuit 10.

[0014] In FIG. 1, the emitter-collector voltage of transistor Q3 has a negative coefficient with respect to temperature. Therefore, the drain voltage of MOSFET Q1 decreases as temperature rises. Due to the action of the current mirror and operational amplifier U, the drain voltage of MOSFET Q1 is equal to the drain voltage of MOSFET Q2, so the drain voltage of MOSFET Q2 decreases with temperature. Therefore, the current flowing through resistor R2 to which the drain voltage of MOSFET Q2 is applied also has a negative coefficient with respect to temperature. On the other hand, the current flowing through resistor R3 increases with temperature. Accordingly, the temperature dependence of the current flowing through resistor R2 and the temperature dependence of the current flowing through resistor R3 are canceled out, and the drain current of MOSFET Q5 included in output circuit 12 becomes a temperature-independent current. That is, transistors Q3 and Q4 and resistors R1 to R3 act as a temperature compensation circuit.

[0015] As described above, the voltage source circuit 10 can output a stabilized voltage with no temperature dependence.

[0016] The scaling circuit 20 scales (enlarges) the output current of the voltage source circuit 10. That is, the scaling circuit 20 increases the output current of the voltage source circuit 10. In the example shown in FIG. 1, the scaling circuit 20 includes a MOSFET Q6, switches SW1 to SW4, and resistors R5 and R6. The MOSFET Q6 has a source connected to a power supply wiring Vdd, a gate connected to switches SW1 and SW2, and a drain connected to a ground wiring via the resistor R5 and a switch SW3. The switches SW1 and SW4 can be implemented by, for example, transfer gates. The switches SW2 and SW3 can be implemented by, for example, a switching element such as a MOSFET.

[0017] The gate of the MOSFET Q6 is connected to the gate of the MOSFET Q5 of the voltage source circuit 10 (output circuit 12) via the switch SW1. That is, when the switch SW1 is on, the MOSFETs Q1, Q2, Q5, and Q6 form a current mirror. The gate of the MOSFET Q6 is connected to the power supply wiring Vdd via the switch SW2. The drain of the MOSFET Q6 is connected to the drain of the MOSFET Q5. Further, the drain of the MOSFET Q6 is connected to the switch SW4 and the LPF 14.

[0018] Here, the MOSFET Q6 of the scaling circuit 20 has a wiring width at least twice that of the MOSFET Q5 of the voltage source circuit 10. This means that the MOSFET Q6 can pass at least twice as much current as the MOSFET Q5. That is, the scaling circuit 20 functions to scale the output current of the voltage source circuit 10.

[0019] Switches SW1, SW2, and SW3 can be turned on or off by external control signals Bypass and / Bypass. The control signal / Bypass is the inverse signal of the control signal Bypass. Here, when switch SW1 is on, switch SW2 is off and switch SW3 is on, and when switch SW1 is off, switch SW2 is on and switch SW3 is off.

[0020] LPF14 smooths the voltage (output voltage) of the output BGRout of the semiconductor integrated circuit 1. LPF14 has a resistor R6 and a capacitor C, and constitutes a so-called CR filter. One end of resistor R6 is connected to the drains of MOSFET Q5 and MOSFET Q6, and the other end of resistor R6 is connected to one end of capacitor C. The other end of capacitor C is connected to the ground wire. The intersection of the other end of resistor R6 and one end of capacitor C is connected to the drain of MOSFET Q6 via switch SW4. The intersection of the other end of resistor R6 and one end of capacitor C is connected to the output BFRout.

[0021] When switches SW1, SW3, and SW4 are ON and switch SW2 is OFF, the gates of MOSFET Q5 and MOSFET Q6 are connected, and the drain of MOSFET Q6 is connected to the ground wire via resistor R5. In this state, the scaling circuit 20 starts operating, and the output of the voltage source circuit 10 and the output of the scaling circuit 20 are input to the capacitor C of the LPF 14 via switch SW4. This operation has the effect of stabilizing the output voltage of output BGRout at an early stage.

[0022] On the other hand, when switches SW1, SW3, and SW4 are off and switch SW2 is on, the gates of MOSFET Q5 and MOSFET Q6 are disconnected, and the scaling circuit 20 stops operating. In this state, the output of the voltage source circuit 10 is input to the resistor R6 of the LPF 14.

[0023] The voltage divider circuit 30 quickly raises the output voltage of output BGRout. The voltage divider circuit 30 has resistors R7 and R8 connected in series, and switches SW5 and SW6. One end of resistor R7 is connected to one end of resistor R8. The other end of resistor R7 is connected to the power supply wiring Vdd. The other end of resistor R8 is connected to the ground wiring via switch SW6. The intersection of resistors R7 and R8 is connected via switch SW5 to the intersection of the other end of resistor R6 and one end of capacitor C. Switches SW5 and SW6 can be turned on or off by an external control signal FWAKE.

[0024] When switches SW5 and SW6 are ON, resistors R7 and R8 act as voltage dividers for the power supply wiring Vdd, and the divided voltage is input to capacitor C of LPF14 via switch SW5. This operation causes the output voltage of output BGRout to rise rapidly.

[0025] The control circuit 40 generates control signals Bypass and FWAKE for controlling switches SW1 to SW6 at predetermined timings. The control circuit 40 may also generate a control signal / Bypass along with the control signal Bypass. The control signal / Bypass may be generated based on the control signal Bypass by a separate circuit, rather than by the control circuit 40. Switch SW5 can be implemented by a transfer gate. Switch SW6 can be implemented by a switching element such as a MOSFET.

[0026] (Operation of the embodiment) Next, the operation of the semiconductor integrated circuit 1 of the embodiment will be described with reference to Figures 1 to 3. Figure 2 is a flowchart showing the control operation in the semiconductor integrated circuit of the embodiment. Figure 3 is a timing chart showing the control operation in the semiconductor integrated circuit of the embodiment.

[0027] When the control circuit 40 receives a BGR enable signal at time t1 (S100), the control circuit 40 outputs a signal (for example, a high-level signal) that enables the control signals Bypass and FWAKE (S110). As a result, as shown in Figure 1, switches SW1, SW3, and SW4 are turned on, switch SW2 is turned off, and switches SW5 and SW6 are turned on.

[0028] At this time, the voltage source circuit 10 outputs a predetermined voltage, and current I1 flows from the drain of MOSFET Q5 to the switch SW4. Current I1 flows through the capacitor C of LPF14 and the output BGRout.

[0029] Furthermore, the scaling circuit 20 starts operating upon receiving the control signal Bypass. In addition, switch SW4 is turned on upon receiving the control signal Bypass. At this time, current I2 flows from the drain of MOSFET Q6 through switch SW4 to the capacitor C of LPF14 and the output BGRout.

[0030] Furthermore, the voltage divider circuit 30 starts operating upon receiving the control signal FWAKE. The voltage of the power supply wiring Vdd is divided by resistors R7 and R8. At this time, current I3 flows from the intersection of one end of resistors R7 and R8 toward the capacitor C of the LPF14 and the output BGRout.

[0031] As shown in Figure 3, at time t1, when the BGR enable signal reaches a high level, the control signals FWAKE and Bypass also reach a high level. The voltage source circuit 10, scaling circuit 20, and voltage divider circuit 30 are activated, and an output voltage appears at output BGRout. At this time, the current I1 from the voltage source circuit 10 is added to the current I2 from the scaling circuit 20 and the current I3 from the voltage divider circuit 30, and the capacitor C of the LPF 14 is charged.

[0032] As a result, the output voltage rises more quickly when the scaling circuit 20 and voltage divider circuit 30 are started in parallel compared to when only the voltage source circuit 10 is started, approaching the target voltage more rapidly. As shown in Figure 3, when the voltage of the power supply wiring Vdd is at its minimum condition (Min) (dashed line in Figure 3), the rise is slower than when the voltage of the power supply wiring Vdd is at its maximum condition (Max) (solid line in Figure 3), but it is faster than the output voltage rise when only the voltage source circuit 10 is started.

[0033] As shown in Figure 2, at time t2, the control circuit 40 outputs a signal (e.g., an L-level signal) that keeps the Bypass control signal active while disabling the FWAKE control signal (S120). As a result, switches SW1, SW3, and SW4 remain ON, switch SW2 remains OFF, and switches SW5 and SW6 are turned OFF. This causes the voltage divider circuit 30 to stop operating, so the current I3 becomes zero, and the current flowing to the capacitor C of the LPF14 and the output BGRout decreases.

[0034] As shown in Figure 3, at time t2, when the control signal FWAKE is controlled to the L level, the current I3 is no longer added to the current flowing through output BGRout. As a result, when the voltage of the power supply wiring Vdd is at its maximum condition (Max), the output voltage of output BGRout changes from rising to falling. That is, due to the control of the current I3 from the voltage divider circuit 30, the output voltage of output BGRout rises rapidly, exceeds the target voltage, and then falls. The time t during which the control signal FWAKE maintains the H level. FWAKE This is set to a timing that prevents the output voltage of output BGRout from exceeding the target voltage too much and allows it to drop quickly. Also, when the voltage of the power supply wiring Vdd is at the minimum condition (Min), the slope of the rise in output voltage becomes slightly gentler.

[0035] As shown in Figure 2, at time t3, the control circuit 40 outputs a signal (e.g., an L-level signal) that disables the control signals Bypass and FWAKE (S130). As a result, switches SW1, SW3, and SW4 are turned off, switch SW2 is turned on, and switches SW5 and SW6 remain off. The scaling circuit 20 stops operating, the current I2 becomes zero, and the current flowing to the capacitor C of the LPF 14 and the output BGRout decreases further.

[0036] As shown in Figure 3, at time t3, when the control signals Bypass and FWAKE are controlled to the L level, the drain voltage of MOSFET Q5 of the voltage source circuit 10 is directly applied to the resistor R6 of LPF14, and the current appearing in the capacitor C of LPF14 and the output BGRout is only current I1. The output voltage of the output BGRout, which rose rapidly at time t1, begins to decrease or rises slowly at time t2, and converges to the target voltage at time t3. The time t when the control signal Bypass maintains the H level Bypass This is set to the timing when the output voltage converges to the target voltage. For example, time t Bypass This should be set to a duration not exceeding 50 μs.

[0037] At time t3, after the control circuit 40 controls the control signals Bypass and FWAKE to L level, the semiconductor integrated circuit 1 outputs a stable voltage (S140).

[0038] In Figure 1, the output current I1 of the voltage source circuit 10, the output current I2 of the scaling circuit 20, and the output current I3 of the voltage divider circuit 30 have the following relationships. I1 <I2<I3 In other words, the voltage divider circuit 30 can charge the capacitor C of the LPF 14 most quickly. However, the voltage of the output current of the voltage divider circuit 30 is generated by dividing the voltage of the power supply wiring Vdd, so the voltage value varies greatly.

[0039] On the other hand, the scaling circuit 20 has a smaller output current than the voltage divider circuit 30, so the charging speed of the LPF 14's capacitor C is slower than that of the voltage divider circuit 30. However, since the output voltage of the scaling circuit 20 is obtained by scaling the output current of the voltage source circuit 10, the voltage value is stable.

[0040] The semiconductor integrated circuit 1 of this embodiment, in order to quickly raise the output voltage of output BGRout when the voltage source circuit 10 is started, in the initial stage (time t) FWAKE and time t Bypass During the AND period of time t, both the output of the scaling circuit 20 and the output of the voltage divider circuit 30 are added to the output of the voltage source circuit 10. On the other hand, because the output current of the voltage divider circuit 30 is large, the output voltage of output BGRout may exceed the target voltage. Therefore, the semiconductor integrated circuit 1, FWAKE After the specified period, the operation of the voltage divider circuit 30 and its output are stopped.

[0041] The output current of the scaling circuit 20 is smaller than the output current of the voltage divider circuit 30. However, if the rise time delay of the output voltage BGRout is eliminated, a stable output can be obtained using only the voltage source circuit 10 even if the operation of the scaling circuit 20 is stopped. Therefore, the timing at which the output voltage of output BGRout converges to the target voltage, that is, the semiconductor integrated circuit 1, is set to time t Bypass After the specified period, the operation of the scaling circuit 20 and its output are stopped.

[0042] Time t Bypass After the specified time has elapsed, switch SW4 is turned off. Consequently, the output of the voltage source circuit 10 is smoothed by LPF14 and output from output BGRout.

[0043] Thus, the semiconductor integrated circuit 1 of this embodiment includes a scaling circuit 20 and a voltage divider circuit 30 in addition to the voltage source circuit 10, which allows the output voltage to rise quickly and converge quickly to the target voltage.

[0044] (Action of the modified version) In this embodiment, when the voltage source circuit 10 starts up, the outputs of the scaling circuit 20 and the voltage dividing circuit 30 are added to the output of the voltage source circuit 10, but the present invention is not limited thereto. The configuration may be such that only the output of the voltage dividing circuit 30 is added when the voltage source circuit 10 starts up. Hereinafter, with reference to FIG. 1 and FIG. 4, a modified example in which only the output of the voltage dividing circuit 30 is added when the voltage source circuit 10 starts up will be described.

[0045] As shown in FIG. 4, at time t4, when the BGR enable signal becomes high level, the control signal FWAKE becomes high level. At this time point, the control signal Bypass remains at low level. The voltage source circuit 10 and the voltage dividing circuit 30 start up, and an output voltage appears at the output BGRout. At this time, the current I3 from the voltage dividing circuit 30 is added to the current I1 from the voltage source circuit 10, and the capacitor C of the LPF 14 is charged.

[0046] Accordingly, compared with the rising of the output voltage when only the voltage source circuit 10 starts up, the rising of the output voltage when the voltage dividing circuit 30 starts up in parallel approaches the target voltage more quickly.

[0047] Subsequently, at time t5, when the control signal FWAKE is controlled to low level, the current I3 is no longer added to the current flowing through the output BGRout. Meanwhile, at time t5, the control signal Bypass is controlled to high level. As a result, when the voltage of the power supply line Vdd is at the maximum condition (Max), the output voltage of the output BGRout changes from increasing to decreasing. That is, by switching to the current I2 from the scaling circuit 20 that is smaller than the current I3 from the voltage dividing circuit 30, the output voltage decreases after exceeding the target voltage. The time for which the control signal FWAKE maintains high level FWAKE is set to such a timing that the output voltage of the output BGRout does not exceed the target voltage excessively and decreases quickly. In addition, when the voltage of the power supply line Vdd is at the minimum condition (Min), the slope of the rise of the output voltage becomes slightly gentler.

[0048] Furthermore, at time t6, when the control signal Bypass is controlled to the L level, the drain voltage of MOSFET Q5 of the voltage source circuit 10 is directly applied to the resistor R6 of LPF14, and the current appearing in the capacitor C of LPF14 and the output BGRout becomes only current I1. The output voltage of the output BGRout, which rose rapidly at time t4, begins to decrease or rises slowly at time t5, and converges to the target voltage at time t6. The time t when the control signal Bypass maintains the H level Bypass This is set to the timing when the output voltage converges to the target voltage. For example, time t Bypass This should be set to a duration not exceeding 50 μs.

[0049] (Second Embodiment) Next, with reference to Figure 5, the electronic device of the second embodiment will be described. In the following description, elements common to the first embodiment will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0050] As shown in Figure 5, the electronic device 2 in this embodiment constitutes a memory system. The electronic device 2 comprises a semiconductor integrated circuit 1 as a BGR circuit according to the first embodiment, a controller 200, a memory 210, and a power management IC (PMIC) 220. The electronic device 2 can be connected to the host 3 via a signal line B and a power wiring Vdd. The signal line B is, for example, a bus line for sending and receiving signals between the electronic device 2 and the host 3. The power wiring Vdd is, for example, a power line capable of supplying a predetermined voltage from the host 3 to the electronic device 2.

[0051] The controller 200 is a functional element that receives commands from the host 3 and performs operations such as reading, writing, erasing, and initializing data to the memory 210. The memory 210 is a semiconductor storage device, for example, a NAND flash memory. The memory 210 is connected to the controller 200, for example, by a bus line.

[0052] The PMIC220 is a circuit element capable of generating multiple output voltages, each with a different voltage value. The PMIC220 receives the output BGRout from the semiconductor integrated circuit 1, generates various output voltages V+, and supplies them to the controller 200, memory 210, and other devices.

[0053] Upon receiving a voltage supply via the power supply wiring Vdd, the semiconductor integrated circuit 1, acting as a BGR circuit, supplies a fast-rising, high-voltage-quality output BGRout to the PMIC 220 according to the operation of the first embodiment. Upon receiving the output BGRout, the PMIC 220 generates an output voltage V+ and supplies it to the controller 200 and memory cell 210.

[0054] According to the electronic device 2 of this embodiment, since it is equipped with a semiconductor integrated circuit 1 as a BGR circuit according to the first embodiment, it is possible to achieve high quality and high-speed startup with respect to the power supply voltage used inside the device.

[0055] Although several embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0056] 1...Semiconductor integrated circuit, 2...Electronic device, 3...Host, 10...Voltage source circuit, 12...Output circuit, 14...LPF, 20...Scaling circuit, 30...Voltage divider circuit, 40...Control circuit, Q1~2, Q5~Q6...MOSFET, Q3~Q4...Transistor, SW1~SW6...Switch, R1~R8...Resistor, U...Operational amplifier, C...Capacitor, 200...Controller, 210...Memory cell, 220...Power management IC.

Claims

1. A semiconductor integrated circuit that generates a predetermined voltage, A first circuit capable of outputting a first current based on the predetermined voltage, A second circuit capable of outputting a second current that is greater than the first current and based on the predetermined voltage, A smoothing circuit having a capacitor and capable of smoothing the output of the first circuit, A control circuit that controls the first circuit and the second circuit to output the first current from the first circuit and the second current from the second circuit to the capacitor in parallel, and to stop outputting the second current to the capacitor after a first time has elapsed since outputting the second current to the capacitor, The system comprises a third circuit capable of outputting a third current that is greater than the first current, less than the second current, and based on the predetermined voltage, The control circuit further controls the third circuit to output the first current from the first circuit, the second current from the second circuit, and the third current from the third circuit to the capacitor in parallel, and to stop the output of the third current after a second time period longer than the first time period has elapsed since the output of the third current to the capacitor. A semiconductor integrated circuit characterized by the following features.

2. A semiconductor integrated circuit that generates a predetermined voltage, A first circuit capable of outputting a first current based on the predetermined voltage, A second circuit capable of outputting a second current that is greater than the first current and based on the predetermined voltage, A smoothing circuit having a capacitor and capable of smoothing the output of the first circuit, A control circuit that controls the first circuit and the second circuit to output the first current from the first circuit and the second current from the second circuit to the capacitor in parallel, and to stop outputting the second current to the capacitor after a first time has elapsed since outputting the second current to the capacitor, The system comprises a third circuit capable of outputting a third current that is greater than the first current, less than the second current, and based on the predetermined voltage, The control circuit can further control the third circuit to output the first current from the first circuit and the second current from the second circuit to the capacitor in parallel, to output the third current from the third circuit to the capacitor in parallel with the first current after a first time has elapsed since the second current was output to the capacitor, and to stop outputting the third current after a second time has elapsed which is longer than the first time since the third current was output to the capacitor. A semiconductor integrated circuit characterized by the following features.

3. A semiconductor integrated circuit that generates a predetermined voltage, A first circuit capable of outputting a first current based on the predetermined voltage, A second circuit capable of outputting a second current that is greater than the first current and based on the predetermined voltage, A smoothing circuit having a capacitor and capable of smoothing the output of the first circuit, The device comprises a control circuit that controls the first circuit and the second circuit to output the first current from the first circuit and the second current from the second circuit to the capacitor in parallel, and which can stop outputting the second current to the capacitor after a first time has elapsed since outputting the second current to the capacitor, The first circuit includes a constant current circuit and a temperature compensation circuit. The second circuit has a voltage divider circuit that generates the predetermined voltage from the power supply voltage. A semiconductor integrated circuit characterized by the following features.

4. The semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that the first time is determined based on the timing at which the output of the first current from the first circuit exceeds a target voltage.

5. Non-volatile memory and A memory controller that controls the aforementioned memory, A semiconductor integrated circuit according to any one of claims 1 to 3, which generates the predetermined voltage that serves as a reference voltage for the power supply supplied to at least one of the memory and the memory controller, An electronic device equipped with the following features.

6. The electronic device according to claim 5, wherein the first time is determined based on the timing at which the output of the first current from the first circuit exceeds the target voltage.

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