Manufacturing method for semiconductor devices

Abstract

To provide a method for manufacturing a semiconductor device with improved yield.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a SiC layer 10 on a single-crystal SiC layer of a substrate having a polycrystalline SiC substrate 2 and a single-crystal SiC layer 6 thereon; forming, on the SiC layer, a first insulating film 40 and a second insulating film 32 separated from each other in an X-direction by a third width W3; removing a first portion 5 of the single-crystal SiC layer extending in a Y-direction intersecting the X-direction and a second portion 7 of the SiC layer provided on the first portion and extending in the Y-direction, below and between the first insulating film and the second insulating film, to form a second groove 72 having a second width W2 narrower than the third width in the X-direction, extending in the Y-direction, cutting the single-crystal SiC layer and the SiC layer, and having the polycrystalline SiC substrate exposed on its bottom; and forming, by dicing, a first groove 82 provided below the second groove, having a first width W1 narrower than the second width in a first direction, extending in the Y-direction, and cutting the polycrystalline SiC substrate.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a promising material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has a band gap approximately three times larger, a breakdown field strength approximately ten times greater, and a thermal conductivity approximately three times greater. Therefore, by using SiC, it is possible to realize semiconductor devices that are low-loss and capable of high-temperature operation. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-034255 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a method for manufacturing semiconductor devices with improved yield. [Means for solving the problem]

[0005] The manufacturing method of the semiconductor device of the embodiment includes the steps of forming a SiC layer on a single-crystal SiC layer of a polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface, forming a first insulating film and a second insulating film on the SiC layer, spaced apart from each other by a third width in a first direction parallel to the second surface, and below the space between the first insulating film and the second insulating film, a first portion of a single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a first A method for manufacturing a semiconductor device comprising: a step of removing a second portion of a SiC layer provided on a portion and extending in a second direction, thereby forming a second groove having a second width narrower than the third width in the first direction, extending in the second direction, cutting through the single crystal SiC layer and the SiC layer, and exposing a polycrystalline SiC substrate at the bottom; and a step of forming a first groove provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting through the polycrystalline SiC substrate, by dicing. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic cross-sectional view of the substrate according to the first embodiment. [Figure 2] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 7] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 8] This is a schematic cross-sectional view showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 9] This is a flowchart showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 10]It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 11] It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 12] It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 13] It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 14] It is a flowchart showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 15] It is a schematic view of a predetermined layer according to the third embodiment. [Figure 16] It is a schematic view of a predetermined layer according to the third embodiment. [Figure 17] It is a schematic view of a predetermined layer of a comparative example of the third embodiment. [Figure 18] It is a schematic view of a predetermined layer of a comparative example of the third embodiment. DESCRIPTION OF EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are denoted by the same reference signs, and the description of members and the like that have already been described will be omitted as appropriate.

[0008] In the following description, when notations n + , n, n - and p + , p, p - are used, these notations represent the relative magnitude of the impurity concentration in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that n + -type, n - -type are simply n-type, p + -type, p -In some cases, the conductivity type is simply referred to as p-type.

[0009] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). In addition, the relative magnitude of the impurity concentration can also be determined from, for example, the magnitude of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). Further, distances such as the depth of an impurity region can be obtained by, for example, SIMS. Furthermore, distances such as the width and depth of an impurity region can be obtained from, for example, an SCM image.

[0010] Hereinafter, the first conductivity type will be described as n-type and the second conductivity type as p-type.

[0011] In this specification, in order to indicate the positional relationship of components and the like, the upward direction in the drawings is described as "upper" and the downward direction in the drawings as "lower". In this specification, the concepts of "upper" and "lower" do not necessarily indicate a relationship with the direction of gravity.

[0012] (First Embodiment) A method for manufacturing a semiconductor device according to the present embodiment comprises: a step of forming a SiC layer on a single-crystal SiC layer of a substrate, the substrate having a polycrystalline SiC substrate having a first surface and a second surface, and the single-crystal SiC layer provided on the second surface; a step of forming a first insulating film and a second insulating film that are spaced apart from each other by a third width in a first direction parallel to the second surface on the SiC layer; a step of removing a first portion of the single-crystal SiC layer that extends in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, below and between the first insulating film and the second insulating film, thereby forming a second groove that has a second width narrower than the third width in the first direction, extends in the second direction, cuts through the single-crystal SiC layer and the SiC layer, and has the polycrystalline SiC substrate exposed at the bottom; and a step of forming, by dicing, a first groove that is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts through the polycrystalline SiC substrate.

[0013] Figures 1 to 8 are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to this embodiment. Figure 9 is a flowchart showing the manufacturing process of the semiconductor device according to this embodiment.

[0014] The semiconductor device 100 in this embodiment is a semiconductor chip. The semiconductor device 100 in this embodiment is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the semiconductor device 100 is not limited to this, and may be, for example, a PIN diode.

[0015] First, prepare the circuit board 4 as shown in Figure 1.

[0016] The substrate 4 comprises a polycrystalline SiC substrate 2 and a single-crystal SiC layer 6.

[0017] The polycrystalline SiC substrate 2 has a first surface 1 and a second surface 3. The second surface 3 is located on the opposite side of the first surface 1.

[0018] Here, we define the X direction, the Y direction perpendicular to the X direction, and the Z direction perpendicular to both the X and Y directions. The first surface 1 and the second surface 3 are provided parallel to the XY plane. The X direction is an example of the first direction. The Y direction is an example of the second direction. The X direction is an example of the third direction.

[0019] The thickness of the polycrystalline SiC substrate 2 in the Z direction is, for example, about 350 μm.

[0020] The single-crystal SiC layer 6 is provided on the second surface 3 of the polycrystalline SiC substrate 2. The thickness of the single-crystal SiC layer 6 in the Z direction is, for example, 0.4 μm or more and 0.7 μm or less.

[0021] The substrate 4 is, for example, a substrate in which a single-crystal SiC layer 6 is attached to a polycrystalline SiC substrate 2.

[0022] Voids (vacancies) V may be formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6. These voids (vacancies) V are thought to be formed, for example, when the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 are not properly bonded together. Note that the illustration of voids (vacancies) V between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 is omitted in Figure 2 and subsequent figures.

[0023] Next, a SiC layer 10 is formed on the single-crystal SiC layer 6 by epitaxial growth, for example, using the CVD (Chemical Vapor Deposition) method (Figure 2, S102 in Figure 9). The SiC layer 10 is an epitaxial SiC layer. As shown in Figure 2, a portion of the SiC layer 10 may be formed directly on the polycrystalline SiC substrate 2.

[0024] Next, the device structure of the semiconductor device 100 is formed on the SiC layer 10. For example, conductive films 20, 22, 24, and 26 are formed. For example, if the semiconductor device 100 is a MOSFET, conductive films 20, 22, 24, and 26 are the source electrodes of the MOSFET. Conductive films 20, 22, 24, and 26 contain conductive materials such as Al (aluminum), Au (gold), Ag (silver), and Cu (copper).

[0025] Next, insulating films 30 and 40 are formed on the SiC layer 10 such that the conductive film 20 is provided between insulating films 30 and 40. Also, insulating films 32 and 42 are formed on the SiC layer 10 such that the conductive film 22 is provided between insulating films 32 and 42. Also, insulating films 34 and 44 are formed on the SiC layer 10 such that the conductive film 24 is provided between insulating films 34 and 44. Also, insulating films 36 and 46 are formed on the SiC layer 10 such that the conductive film 26 is provided between insulating films 36 and 46. Insulating films 30, 32, 34, 36, 40, 42, 44, and 46 are, for example, interlayer insulating films of the semiconductor device 100. Insulating films 30, 32, 34, 36, 40, 42, 44, and 46 include, for example, an insulating material such as polyimide (Figures 3 and 9, S104).

[0026] As shown in Figure 7 later, for example, one semiconductor device 100 includes a conductive film 20, an insulating film 30, and an insulating film 40. Also, for example, one semiconductor device 100 includes a conductive film 22, an insulating film 32, and an insulating film 42. Also, for example, one semiconductor device 100 includes a conductive film 24, an insulating film 34, and an insulating film 44. Also, for example, one semiconductor device 100 includes a conductive film 26, an insulating film 36, and an insulating film 46.

[0027] The insulating film 40 (an example of the first insulating film) and the insulating film 32 (an example of the second insulating film) are spaced three widths apart from each other in the X direction. The spaced portion between insulating film 40 and insulating film 32 is the dicing line 52. The insulating film 42 (an example of the first insulating film) and the insulating film 34 (an example of the second insulating film) are spaced three widths apart from each other in the X direction. The spaced portion between insulating film 42 and insulating film 34 is the dicing line 54. The insulating film 44 (an example of the first insulating film) and the insulating film 36 (an example of the second insulating film) are spaced three widths apart from each other in the X direction. The spaced portion between insulating film 44 and insulating film 36 is the dicing line 56. In addition, a dicing line 50 is provided on the -X side of insulating film 30. In addition, a dicing line 58 is provided on the +X side of insulating film 46. The third width is shown as "W3" in Figure 8, which will be described later.

[0028] Dicing lines 50, 52, 54, 56, and 58 are the parts that will be diced in a later process, for example, using a blade. Dicing lines 50, 52, 54, 56, and 58 each extend in the Y direction.

[0029] Similarly, dicing lines (not shown) extending in the X direction may also be provided.

[0030] Next, a photomask (mask) 60, for example, a photoresist, is formed on the polycrystalline SiC substrate 2, SiC layer 10, conductive film 20, conductive film 22, conductive film 24 and conductive film 26, insulating film 30, insulating film 32, insulating film 34, insulating film 36, insulating film 40, insulating film 42, insulating film 44 and insulating film 46 (Figure 4). The photomask 60 in the areas of dicing line 52, dicing line 54, dicing line 56 and dicing line 58 is made to have openings parallel to the Y direction.

[0031] Next, using a photomask (mask) 60, portions of the single-crystal SiC layer 6 and SiC layer 10 extending in the Y direction, located between the insulating film 40 and the insulating film 32, are removed along the dicing line 52. The portion of the single-crystal SiC layer 6 extending in the Y direction that is removed is the first portion 5 of the single-crystal SiC layer 6, as shown in Figure 8. The portion of the SiC layer 10 extending in the Y direction that is removed is the second portion 7 of the SiC layer 10, as shown in Figure 8. This forms a second groove 72 that cuts through the single-crystal SiC layer 6 and the SiC layer 10 (S106 in Figures 5 and 9). The width of the second groove 72 is the second width. The second width is narrower than the third width. The second width is shown as "W2" in Figure 8.

[0032] Similarly, a second groove 74 is formed below the insulating film 42 and the insulating film 34, along the dicing line 54. Also, a second groove 76 is formed below the insulating film 44 and the insulating film 36, along the dicing line 56. Furthermore, a second groove 78 is formed along the dicing line 58. Also, a second groove 70 is formed.

[0033] Here, the formation of the second grooves 70, 72, 74, 76, and 78 is carried out using reactive ion etching (RIE) with a fluorine-based gas such as SF6 (sulfur hexafluoride). Note that the fluorine-based gas such as SF6 may be diluted with Ar (argon) or the like.

[0034] In this case, it is preferable that the polycrystalline SiC substrate 2 is exposed at the bottom of the second groove 70, second groove 72, second groove 74, second groove 76, and second groove 78.

[0035] The formation of the second grooves 70, 72, 74, 76, and 78 may be carried out using plasma dicing, wet etching, or chemical dry etching (CDE).

[0036] Next, remove the photomask 60 (Figure 6).

[0037] Next, a first groove 82 is formed below the second groove 72, having a first width narrower than the second width in the X direction, extending in the Y direction, and cutting the polycrystalline SiC substrate 2, for example by dicing using blade B. Similarly, a first groove 80 is formed below the second groove 70. Similarly, a first groove 84 is formed below the second groove 74. In addition, first grooves not shown are also formed below the second groove 76 and the second groove 78 (S108 in Figures 7 and 9). The first groove 82 may be formed by laser dicing or plasma dicing. The first width is shown as "W1" in Figure 8.

[0038] In this case, the first surface 1 of the polycrystalline SiC substrate 2 is attached to, for example, a dicing tape S.

[0039] The semiconductor device 100 of this embodiment is obtained by peeling off each portion separated by the first groove from the dicing tape S.

[0040] Figure 8 is a schematic cross-sectional view of the enlarged first groove 82 and second groove 72.

[0041] The width of the first groove 82 in the X direction is the first width W1. The width of the second groove 72 in the X direction is the second width W2. In the X direction, the insulating film 40 and the insulating film 32 are spaced apart by a third width W3.

[0042] The second width W2 is preferably larger than the first width W1 by a width W1b in the X direction and a width W1a in the -X direction. Here, the widths W1b and W1a are preferably 10 μm or more and 25 μm or less. Therefore, the second width W2 is preferably 10 μm or more and 25 μm or less larger than the first width W1 in both the X direction and the -X direction.

[0043] The third width W3 is preferably larger than the second width W2 by a width W2b in the X direction and a width W2a in the -X direction. Here, the widths W2a and W2b are preferably 5 μm or more and 10 μm or less. Therefore, the third width W3 is preferably larger than the second width W2 by 5 μm or more and 10 μm or less in both the X direction and the -X direction.

[0044] Next, the effects and advantages of this embodiment will be described.

[0045] Manufacturing high-quality single-crystal SiC substrates is difficult. Therefore, one possible approach is to manufacture a bonded substrate by thermally delaminating a SiC single-crystal matrix onto a polycrystalline SiC substrate 2 to create a thin sheet, and then attaching a single-crystal SiC layer to the polycrystalline SiC substrate 2.

[0046] However, there was a problem in that voids (vacancies) were formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6.

[0047] When dicing such bonded substrates, there was a problem in that chipping and peeling occurred in the single-crystal SiC layer.

[0048] In areas where voids (vacancies) are formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, for example, the single-crystal SiC layer is lifted away from the polycrystalline SiC substrate 2. Furthermore, in areas where voids (vacancies) are formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, the single-crystal SiC layer and the polycrystalline SiC substrate 2 are partially bonded over a very small area. When machining such void areas, the single-crystal SiC layer, which is relatively thinner than the polycrystalline SiC substrate 2, is peeled off due to contact and friction with the blade, resulting in chipping and delamination. Such chipping and delamination can lead to a decrease in the electrical characteristics and reliability of the semiconductor device. Similar chipping and delamination can occur when laser dicing or plasma dicing is performed.

[0049] Furthermore, since such bonded substrates may have a multilayer substrate structure with different crystal structures, there was a problem of substrate warping occurring due to stress differences between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, and strain at the bonding interface between the polycrystalline SiC substrate 2 and the single-crystal SiC layer.

[0050] Therefore, the semiconductor device manufacturing method of this embodiment comprises the steps of: forming a SiC layer on a single-crystal SiC layer of a substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface; forming a first insulating film and a second insulating film on the SiC layer, spaced apart by a third width from each other in a first direction parallel to the second surface; forming a second groove having a second width narrower than the third width in the first direction, extending in the second direction, cutting the single-crystal SiC layer and the SiC layer, with the polycrystalline SiC substrate exposed at the bottom, by removing a first portion of the single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, between the first insulating film and the second insulating film; and forming a first groove provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate, by dicing.

[0051] In the semiconductor device manufacturing method of this embodiment, a second groove is formed to cut the single-crystal SiC layer 6 and the SiC layer 10 before dicing. Therefore, chipping and peeling of the single-crystal SiC layer 6 and the SiC layer 10 that occur when the first groove is formed by dicing can be suppressed. As a result, the semiconductor device manufacturing method of this embodiment makes it possible to provide a semiconductor device manufacturing method with improved yield.

[0052] Furthermore, since the single-crystal SiC layer and the SiC layer are divided into small areas during the manufacturing process, the aforementioned substrate warping can be suppressed.

[0053] The second width W2 is preferably 10 μm to 25 μm larger than the first width W1 in both the X and -X directions. The widths W1a and W1b (Figure 8) are preferably larger than the kerf deviation width, which is caused by a combination of factors such as the mechanical precision of the dicing device, the specifications of blade B (blade thickness, strength), and the cutting speed of the dicing device, resulting in meandering of the cut line of the substrate. This kerf deviation width is approximately 10 μm in both the X and -X directions. Therefore, the second width W2 is preferably 10 μm or more larger than the first width W1 in both the X and -X directions. On the other hand, if the difference between the second width W2 and the first width W1 in the X and -X directions is greater than 25 μm, the number of semiconductor chips that can be obtained will decrease, which is undesirable.

[0054] The third width W3 is preferably 5 μm to 10 μm larger than the second width W2 in both the X and -X directions. During dry etching, the SiC layer beneath the insulating film may be etched and receded, causing the insulating film to protrude in an overhang shape. To suppress this, the third width W3 is preferably 5 μm or more larger than the second width W2 in both the X and -X directions. On the other hand, it is sufficient for the third width W3 to be 10 μm larger than the second width W2.

[0055] It is preferable that the polycrystalline SiC substrate 2 is exposed at the bottom of the second grooves 70, 72, 74, 76, and 78. In other words, it is preferable to form a portion of the second groove so that it penetrates into the polycrystalline SiC substrate 2.

[0056] Let's take the example of forming a first groove by dicing with a blade. When the void V and the blade come into contact and further cutting of the polycrystalline SiC substrate 2 occurs, it is sometimes not possible to cut the polycrystalline SiC substrate 2 smoothly. For example, it is presumed that the gas inside the void V applies some unintended pressure to the surrounding polycrystalline SiC substrate 2, single-crystal SiC layer 6, and SiC layer 10. If a portion of the second groove is formed so as to bite into the polycrystalline SiC substrate 2, contact between the SiC layer 10, single-crystal SiC layer 6, and void V and the blade can be reliably avoided during dicing to form the first groove.

[0057] The semiconductor device manufacturing method of this embodiment makes it possible to provide a semiconductor device manufacturing method with improved yield.

[0058] (Second Embodiment) The semiconductor device manufacturing method of this embodiment includes the steps of: forming a SiC layer on a single-crystal SiC layer of a substrate having a polycrystalline SiC substrate having a second surface and a single-crystal SiC layer provided on the second surface; forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, spaced apart from each other by a second width in a first direction parallel to the second surface; and below the space between the third insulating film and the fourth insulating film, forming a first portion of a single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of a SiC layer provided on the first portion and extending in the second direction. The method comprises the steps of: forming a second groove having a second width in a first direction and extending in a second direction, which cuts through a single-crystal SiC layer and a SiC layer, by removing a portion of the material; removing a third insulating film and a fourth insulating film; forming a first insulating film and a second insulating film on the SiC layer, spaced apart by a third width greater than the second width in a first direction, and sandwiching the second groove; and forming a first groove by dicing, which is located below the second groove, has a first width narrower than the second width in a first direction, extends in a second direction, and cuts through a polycrystalline SiC substrate.

[0059] Here, we will omit descriptions that overlap with those of the first embodiment.

[0060] Figures 10 to 13 are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to this embodiment. Figure 14 is a flowchart showing the manufacturing process of the semiconductor device according to this embodiment.

[0061] The process of forming the SiC layer 10 on the single-crystal SiC layer 6 by, for example, an epitaxial growth method using CVD (Chemical Vapor Deposition) (S202 in Figure 14) is the same as in the first embodiment.

[0062] Next, an oxide-containing insulating film 62, an oxide-containing insulating film 63 (an example of a third insulating film), an oxide-containing insulating film 64 (an example of a fourth insulating film), an oxide-containing insulating film 65, an oxide-containing insulating film 66, and an oxide-containing insulating film 67 are formed on the SiC layer 10. Insulating films 62 and 63 are spaced two widths apart from each other in the X direction. Insulating films 63 and 64 are spaced two widths apart from each other in the X direction. Insulating films 64 and 65 are spaced two widths apart from each other in the X direction. Insulating films 65 and 66 are spaced two widths apart from each other in the X direction. Insulating films 66 and 67 are spaced two widths apart from each other in the X direction (S204 in Figures 10 and 14).

[0063] The spaced-out portion between insulating film 62 and insulating film 63 is the dicing line 50. The spaced-out portion between insulating film 63 and insulating film 64 is the dicing line 52. The spaced-out portion between insulating film 64 and insulating film 65 is the dicing line 54. The spaced-out portion between insulating film 65 and insulating film 66 is the dicing line 56. The spaced-out portion between insulating film 66 and insulating film 67 is the dicing line 58.

[0064] Next, insulating films 62, 63, 64, 65, 66, and 67 are used as masks to form a second groove 70 on dicing line 50, a second groove 72 on dicing line 52, a second groove 74 on dicing line 54, a second groove 76 on dicing line 56, and a second groove 78 on dicing line 58 (S206 in Figures 11 and 14).

[0065] Here, insulating film 62, insulating film 63, insulating film 64, insulating film 65, insulating film 66, and insulating film 67 include, for example, an oxide. Insulating film 62, insulating film 63, insulating film 64, insulating film 65, insulating film 66, and insulating film 67 include, for example, silicon oxide.

[0066] Next, insulating films 62, 63, 64, 65, 66, and 67 are removed (S14, S208).

[0067] Next, the device structure of the semiconductor device 100 is formed on the SiC layer 10. For example, conductive films 20, 22, 24, and 26 are formed. Next, insulating films 30 and 40 are formed on the SiC layer 10 such that the conductive film 20 is provided between the insulating films 30 and 40. Also, insulating films 32 and 42 are formed on the SiC layer 10 such that the conductive film 22 is provided between the insulating films 32 and 42. Also, insulating films 34 and 44 are formed on the SiC layer 10 such that the conductive film 24 is provided between the insulating films 34 and 44. Also, insulating films 36 and 46 are formed on the SiC layer 10 such that the conductive film 26 is provided between the insulating films 36 and 46.

[0068] Here, insulating film 40 (an example of the first insulating film) and insulating film 32 (an example of the second insulating film) are spaced three widths apart from each other in the X direction. Insulating film 42 (an example of the first insulating film) and insulating film 34 (an example of the second insulating film) are spaced three widths apart from each other in the X direction. Insulating film 44 (an example of the first insulating film) and insulating film 36 (an example of the second insulating film) are spaced three widths apart from each other in the X direction (S210 in Figures 12 and 14).

[0069] Next, a first groove 82 is formed below the second groove 72, having a first width narrower than the second width in the X direction, extending in the Y direction, and cutting the polycrystalline SiC substrate 2, for example by dicing using blade B. Similarly, the first groove 80 is formed below the second groove 70. Similarly, the first groove 84 is formed below the second groove 74. In addition, first grooves (not shown) are also formed below the second groove 76 and the second groove 78 (S212 in Figures 13 and 14).

[0070] In this case, the first surface 1 of the polycrystalline SiC substrate 2 is attached to, for example, a dicing tape S.

[0071] The semiconductor device 100 of this embodiment is obtained by peeling off each portion separated by the first groove from the dicing tape S.

[0072] For example, if the SiC layer 10 is thick, it may be necessary to ensure the durability of the photomask during dry etching. In such cases, a manufacturing method that uses insulating films 62, 63, 64, 65, 66, and 67 as masks, as in the semiconductor device manufacturing method of this embodiment, is suitable.

[0073] The semiconductor device manufacturing method of this embodiment makes it possible to provide a semiconductor device manufacturing method with improved yield.

[0074] (Third embodiment) The semiconductor device manufacturing method of this embodiment differs from the semiconductor device manufacturing methods of the first and second embodiments in that, in the step of forming the second groove, a predetermined layer is formed within the second groove, having a third portion which is part of the first portion, and a fourth portion which is provided on the third portion and is part of the second portion. Here, descriptions that overlap with the first and second embodiments are omitted.

[0075] Figure 15 is a schematic top view showing the manufacturing process of the semiconductor device of this embodiment. The schematic cross-sectional view shown in Figure 6 corresponds, for example, to the A-A' section in Figure 15.

[0076] Figure 16 is a schematic diagram of the predetermined layer 102 of this embodiment. Figure 16(a) is a schematic top view of the predetermined layer 102 of this embodiment. Figure 16(b) is a schematic cross-sectional view of the predetermined layer 102 of this embodiment in the B-B' section of Figure 16(a).

[0077] In the process of forming the second grooves 70, 72, 74, 76, and 78, a predetermined layer 102 is formed within each of the second grooves. Here, the portion of the single-crystal SiC layer 6 extending in the Y direction that is removed in the process of forming the second grooves is the first portion 5 of the single-crystal SiC layer 6 (Figure 8). Also, the portion of the SiC layer 10 extending in the Y direction that is removed in the process of forming the second grooves is the second portion 7 of the SiC layer 10 (Figure 8). The predetermined layer 102 has a third portion 9 which is part of the first portion 5 that is left in the second groove without being removed, and a fourth portion 11 which is part of the second portion that is left in the second groove without being removed. The fourth portion 11 is provided on top of the third portion 9.

[0078] Furthermore, if parts of the second grooves 70, 72, 74, 76, and 78 are formed in the polycrystalline SiC substrate 2, then a portion of the polycrystalline SiC substrate 2 surrounding the predetermined layer 102 is also removed.

[0079] In Figure 16(a), the shape of the predetermined layer 102 is cross-shaped when viewed from above. However, the shape of the predetermined layer 102 when viewed from above is not limited to a cross shape. For example, the shape of the predetermined layer 102 when viewed from above may be a rectangle.

[0080] In the dicing apparatus, a camera captures the pattern placed on the dicing line to perform the alignment operation of the substrate 4. The predetermined layer 102 is used as a reference (alignment mark) for the alignment of the substrate 4.

[0081] Figure 17 is a schematic cross-sectional view showing the manufacturing process of a semiconductor device of the comparative form of this embodiment. Figure 18 is a schematic diagram of the predetermined layer 1002 of the comparative form of this embodiment. Figure 18(a) is a schematic top view of the predetermined layer 1002 of the comparative form. Figure 18(b) is a schematic cross-sectional view of the predetermined layer 1002 of the comparative form in the A-A' section of Figure 18(a).

[0082] The predetermined layer 1002 has a metal layer 1004 provided on the single-crystal SiC layer 6 and the SiC layer 10. Here, the metal layer 1004 contains a metallic material such as Al (aluminum). The metal layer 1004 corresponds to, for example, the conductive film 20 shown in the first and second embodiments. The single-crystal SiC layer 6 and the SiC layer 10 surrounding the metal layer 1004 have not been removed by dry etching or the like.

[0083] The comparative metal layer 1004, like the conductive film 20, contains a conductive material such as Al. In this case, surface roughness and shape changes could occur due to the influence of post-formation manufacturing processes such as sintering heat treatment, developing solutions used in photolithography, or chemicals used to strip photoresist. Furthermore, if light is scattered due to surface roughness or the shape deviates from the predetermined shape, there is a problem of reduced alignment accuracy.

[0084] In the semiconductor device manufacturing method of this embodiment, a predetermined layer 102 having a single crystal SiC layer 6 and a portion of the SiC layer 10 is formed. Therefore, compared to the case where a predetermined layer 1002 having a metal layer is formed, as in the comparative embodiment, the number of manufacturing steps can be reduced. Furthermore, since the predetermined layer 102 is formed of SiC, it is less affected by process steps compared to the predetermined layer 1002 containing a metal material. Therefore, the alignment of the substrate 4 can be performed more accurately.

[0085] The semiconductor device manufacturing method of this embodiment makes it possible to provide a semiconductor device manufacturing method with improved yield.

[0086] While several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0087] Furthermore, the above embodiments can be summarized in the following technical proposal. (Technical proposal 1) A polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface, a step of forming a SiC layer on the single-crystal SiC layer of the substrate, A step of forming a first insulating film and a second insulating film on the SiC layer, spaced apart from each other by a third width in a first direction parallel to the second surface, A step of forming a second groove having a second width narrower than the third width in the first direction, extending in the second direction, cutting the single crystal SiC layer and the SiC layer, with the polycrystalline SiC substrate exposed at the bottom, by removing a first portion of the single crystal SiC layer extending in the second direction parallel to the second surface and intersecting the first direction, located between the first insulating film and the second insulating film, and a second portion of the SiC layer provided on top of the first portion and extending in the second direction, A step of forming a first groove by dicing, which is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the same equipment. (Technical proposal 2) A polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface, a step of forming a SiC layer on the single-crystal SiC layer of the substrate, A step of forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, spaced apart from each other by a second width in a first direction parallel to the second surface, A step of forming a second groove having the second width in the first direction, extending in the second direction, and cutting through the single crystal SiC layer and the SiC layer, by removing a first portion of the single crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, between the third insulating film and the fourth insulating film; A step of removing the third insulating film and the fourth insulating film, A step of forming a first insulating film and a second insulating film on the SiC layer, spaced apart in the first direction by a third width greater than the second width, and sandwiching the second groove, A step of forming a first groove by dicing, which is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the same equipment. (Technical proposal 3) The second width is 10 μm or more and 25 μm or less than the first width in the first direction and in the third direction opposite to the first direction. A method for manufacturing a semiconductor device as described in Technical Proposal 1 or Technical Proposal 2. (Technical proposal 4) The third width is greater than the second width by 5 μm or more and 10 μm or less in the first direction and the third direction opposite to the first direction. A method for manufacturing a semiconductor device as described in any one of Technical Proposals 1 to 3. (Technical proposal 5) The second groove is formed by dry etching using the first insulating film and the photoresist provided on the second insulating film as a mask. A method for manufacturing a semiconductor device as described in any one of Technical Proposal 1, Technical Proposal 3, or Technical Proposal 4. (Technical proposal 6) In the process of forming the two grooves, within the two grooves, The third part, which is part of the first part mentioned above, A fourth part is provided on the third part and is part of the second part, Forming a predetermined layer having A method for manufacturing a semiconductor device as described in any one of Technical Proposals 1 to 5. [Explanation of Symbols]

[0088] 1 Page 1 2 Polycrystalline SiC substrate 3 Side 2 4 circuit boards 6. Single-crystal SiC layer 7 Part 3 10 SiC layer 11 Part 4 20 Conductive film 22 Conductive film 24 Conductive film 26 Conductive film 30 insulating film 32 Insulating film 34 Insulating Film 36 Insulating Film 40 insulating film 42 Insulating film 44 insulating film 46 Insulating film 50 dicing lines 52 Dicing Lines 54 Dicing Lines 56 Dicing Lines 58 Dicing Lines 60 Photomasks 62 Insulating film 63 Insulating film 64 Insulating film 65 Insulating film 66 Insulating film 67 Insulating film 70 Second groove 72 Second groove 74 Second groove 76 Second groove 78 Second groove 80 1st groove 82 First groove 84 First groove 100 Semiconductor Equipment 102 Predetermined layer 1002 Predetermined layer B Blade S Dicing Tape V Void W1 1st width W2, 2nd width W3 3rd width

Claims

1. A polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface, a step of forming a SiC layer on the single-crystal SiC layer of the substrate, A step of forming a first insulating film and a second insulating film on the SiC layer, spaced apart from each other by a third width in a first direction parallel to the second surface, A step of forming a second groove having a second width narrower than the third width in the first direction, extending in the second direction, cutting the single crystal SiC layer and the SiC layer, and exposing the polycrystalline SiC substrate at the bottom, by removing a first portion of the single crystal SiC layer extending in the second direction parallel to the second surface and intersecting the first direction, located between the first insulating film and the second insulating film, and a second portion of the SiC layer provided on top of the first portion and extending in the second direction, A step of forming a first groove by dicing, which is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the same equipment.

2. A polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface, a step of forming a SiC layer on the single-crystal SiC layer of the substrate, A step of forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, spaced apart from each other by a second width in a first direction parallel to the second surface, A step of forming a second groove having the second width in the first direction, extending in the second direction, and cutting through the single crystal SiC layer and the SiC layer, by removing a first portion of the single crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, between the third insulating film and the fourth insulating film. A step of removing the third insulating film and the fourth insulating film, A step of forming a first insulating film and a second insulating film on the SiC layer, spaced apart in the first direction by a third width greater than the second width, and sandwiching the second groove, A step of forming a first groove by dicing, which is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate; A method for manufacturing a semiconductor device comprising the same equipment.

3. The second width is 10 μm to 25 μm larger than the first width in the first direction and in the third direction opposite to the first direction. A method for manufacturing a semiconductor device according to claim 1 or claim 2.

4. The third width is greater than the second width by 5 μm or more and 10 μm or less in the first direction and the third direction opposite to the first direction. A method for manufacturing a semiconductor device according to claim 1 or claim 2.

5. The second groove is formed by dry etching using the first insulating film and the photoresist provided on the second insulating film as a mask. A method for manufacturing a semiconductor device according to claim 1.

6. In the process of forming the two grooves mentioned above, within the two grooves mentioned above, The third part, which is part of the first part mentioned above, A fourth part is provided on the third part and is part of the second part, Forming a predetermined layer having A method for manufacturing a semiconductor device according to claim 1 or claim 2.

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