Image sensors, electronic devices

Abstract

The present technology relates to an imaging element and an electronic apparatus in which the dynamic range of a photodiode is increased. The imaging element comprises: a photoelectric conversion unit for converting light into electrical charge; three or more storage units for storing electrical charge temporarily; a transfer unit for transferring electrical charge from the photoelectric conversion unit to the storage unit; and a conversion efficiency switching unit for controlling the state of electrical continuity between the storage units. Of the three or more storage units, at least two are capacitive elements. The three or more storage units store electrical charge that has overflowed from the photoelectric conversion unit. The present technology is applicable, for example, to an imaging element for capturing an image.

Description

Technical Field

[0001] The present technology relates to image sensors and electronic devices, and for example, relates to an image sensor and an electronic device configured to expand a dynamic range and obtain higher-quality images.

Background Art

[0002] Generally, image sensors such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charge Coupled Device) image sensors are widely used in digital still cameras, digital video cameras, and the like. Improvements in the characteristics of image sensors are desired, and for example, expansion of the dynamic range is desired. Patent Document 1 proposes expanding the dynamic range by providing a plurality of storage capacitance elements that store charge overflowed from a photodiode.

Prior Art Literature

Patent Literature

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] In order to allow charge overflowed from a photodiode to be stored in a storage capacitance element, it is necessary to set the overflow barrier of a transfer transistor that transfers charge from the photodiode to a low level. In such a case, there is a possibility that the Qs (saturated charge amount) of the photodiode will decrease. It is desired to be able to expand the dynamic range without reducing the saturated charge amount of the photodiode.

[0005] The present technology has been made in view of such circumstances, and is intended to enable expansion of the dynamic range. [Means for solving the problem]

[0007] One aspect of this technology imaging The element comprises a photoelectric conversion unit, a transfer transistor connected to the photoelectric conversion unit, a floating diffusion connected to the transfer transistor, a first conversion efficiency switching transistor connected to the floating diffusion, a second conversion efficiency switching transistor connected to the first conversion efficiency switching transistor, a reset transistor connected to the second conversion efficiency switching transistor, and a first storage unit and a second storage unit, wherein the first storage unit is connected between the first conversion efficiency switching transistor and the second conversion efficiency switching transistor, the second storage unit is connected between the second conversion efficiency switching transistor and the reset transistor, and the floating diffusion stores the charge overflowing from the photoelectric conversion unit. The photoelectric conversion unit is composed of a region of a first conductor and a region of a second conductor surrounding the region of the first conductor, and the transfer transistor is connected to the first conductor, which is provided as an extension. It is an image sensor.

[0008] One aspect of this technology is an electronic device comprising: a photoelectric conversion unit; a transfer transistor connected to the photoelectric conversion unit; a floating diffusion connected to the transfer transistor; a first conversion efficiency switching transistor connected to the floating diffusion; a second conversion efficiency switching transistor connected to the first conversion efficiency switching transistor; a reset transistor connected to the second conversion efficiency switching transistor; and a first storage unit and a second storage unit, wherein the first storage unit is connected between the first conversion efficiency switching transistor and the second conversion efficiency switching transistor, and the second storage unit is connected between the second conversion efficiency switching transistor and the reset transistor, and the floating diffusion stores the charge overflowing from the photoelectric conversion unit. The photoelectric conversion unit is composed of a region of a first conductor and a region of a second conductor surrounding the region of the first conductor, and the transfer transistor is connected to the first conductor, which is provided as an extension. This is an electronic device comprising an image sensor and a processing unit that processes signals from the image sensor.

[0010] One aspect of this technology imagingThe element comprises a photoelectric conversion unit, a transfer transistor connected to the photoelectric conversion unit, a floating diffusion connected to the transfer transistor, a first conversion efficiency switching transistor connected to the floating diffusion, a second conversion efficiency switching transistor connected to the first conversion efficiency switching transistor, a reset transistor connected to the second conversion efficiency switching transistor, and a first storage unit and a second storage unit, wherein the first storage unit is connected between the first conversion efficiency switching transistor and the second conversion efficiency switching transistor, the second storage unit is connected between the second conversion efficiency switching transistor and the reset transistor, and the floating diffusion stores the charge overflowing from the photoelectric conversion unit. The photoelectric conversion unit is composed of a region of a first conductor and a region of a second conductor surrounding the region of the first conductor, and the transfer transistor is connected to the first conductor, which is provided as an extension. .

[0011] In electronic devices, which are one aspect of this technology, The aforementioned IM It is configured to include elements.

[0012] Furthermore, electronic devices may be independent devices or internal blocks that make up a single device. [Brief explanation of the drawing]

[0013] [Figure 1] This figure shows an example configuration of one embodiment of an imaging device to which this technology is applied. [Figure 2] This figure shows an example of a pixel circuit configuration. [Figure 3] This figure shows an example of the cross-sectional configuration of a pixel. [Figure 4] This figure shows an example of the cross-sectional configuration of a pixel in the second embodiment. [Figure 5] This figure shows an example of the pixel circuit configuration in the second embodiment. [Figure 6] This figure shows an example of the pixel circuit configuration in the third embodiment. [Figure 7] This figure shows an example of the cross-sectional configuration of a pixel in the third embodiment. [Figure 8] This is a diagram to explain the operation of pixels. [Figure 9] It is a diagram illustrating an example of the circuit configuration of a pixel in the fourth embodiment. [Figure 10] It is a diagram illustrating an example of the cross-sectional configuration of a pixel in the fourth embodiment. [Figure 11] It is a diagram for explaining the configuration of wiring capacitance. [Figure 12] It is a diagram illustrating an example of the circuit configuration of a pixel in the fifth embodiment. [Figure 13] It is a diagram illustrating an example of the cross-sectional configuration of a pixel in the fifth embodiment. [Figure 14] It is a diagram illustrating an example of the cross-sectional configuration of a pixel in the sixth embodiment. [Figure 15] It is a diagram illustrating an example of the circuit configuration of a pixel in the sixth embodiment. [Figure 16] It is a diagram illustrating an example of the circuit configuration of a pixel in the seventh embodiment. [Figure 17] It is a diagram for explaining the manufacturing of pixels. [Figure 18] It is a diagram illustrating an example of an electronic device. [Figure 19] It is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 20] It is a block diagram illustrating an example of the functional configuration of a camera head and a CCU. MODE FOR CARRYING OUT THE INVENTION

[0014] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0015] <Configuration Example of Imaging Device> FIG. 1 shows a configuration example of an embodiment of an imaging device to which the present technology is applied.

[0016] The imaging device 1 shown in Figure 1 is composed of a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit section surrounding it. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0017] Pixel 2 consists of a photodiode as a photoelectric conversion element and multiple pixel transistors. The multiple pixel transistors are, for example, transfer transistors, selection transistors, reset transistors, and amplification transistors, and are composed of MOS transistors.

[0018] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the imaging device 1. Specifically, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0019] The vertical drive circuit 4 is composed of, for example, a shift register, and selects a predetermined pixel drive line 10, supplies pulses to the selected pixel drive line 10 to drive the pixels 2, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a pixel signal based on the signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0020] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from one row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) or DDS (double data sampling) to remove pixel-specific fixed pattern noise, and AD conversion.

[0021] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0022] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0023] The imaging device 1 configured as described above is a CMOS image sensor called a column AD type, in which a column signal processing circuit 5 that performs CDS processing or DDS processing and AD conversion processing is arranged for each pixel row.

[0024] <Example of pixel circuit configuration> The configuration of the unit pixels provided in the pixel array section 3 will now be described. The unit pixels provided in the pixel array section 3 are configured as shown in Figure 2, for example. In the explanation from Figure 2 onward, the same reference numerals are used for parts corresponding to those in Figure 1, and their explanations will be omitted as appropriate. Figure 2 is a diagram showing an example of the circuit configuration of pixel 2.

[0025] Referring to Figure 2, the unit pixel 2 includes a photoelectric conversion unit 51, a transfer transistor 52, an FD (Floating Diffusion) unit 53, a first conversion efficiency switching transistor 54, a MIM (Metal-Insulator-Metal) capacitance element 55, a second conversion efficiency switching transistor 56, an MIM capacitance element 57, a reset transistor 58, an amplification transistor 59, and a selection transistor 60.

[0026] For each pixel row, for example, multiple drive lines are wired as pixel drive lines 10 to each pixel row. Then, the drive signals TG, FDG, FCG, RST, and SEL are supplied from the vertical drive circuit 4 via the multiple drive lines to the transfer transistor 52, the first conversion efficiency switching transistor 54, the second conversion efficiency switching transistor 56, the reset transistor 58, and the selection transistor 60, respectively.

[0027] These drive signals are pulse signals in which a high level (e.g., power supply voltage VDD) indicates an active state, and a low level (e.g., negative potential) indicates an inactive state. In other words, when each drive signal TG through SEL is set to a high level, the transistor to which it is supplied becomes conductive, i.e., on, and when each drive signal is set to a low level, the transistor to which it is supplied becomes non-conductive, i.e., off.

[0028] The photoelectric conversion unit 51 consists of, for example, a PN junction photodiode. The photoelectric conversion unit 51 receives incident light, performs photoelectric conversion, and stores the resulting charge.

[0029] The transfer transistor 52 is located between the photoelectric conversion unit 51 and the FD unit 53, and a drive signal TG is supplied to the gate electrode of the transfer transistor 52. When this drive signal TG reaches a high level, the transfer transistor 52 is turned on, and the charge stored in the photoelectric conversion unit 51 is transferred to the FD unit 53 via the transfer transistor 52.

[0030] The FD section 53 is a floating diffusion region called a floating diffusion region, and functions as an accumulation section that temporarily stores transferred charges and charges that have overflowed from the photoelectric conversion section 51.

[0031] The first conversion efficiency switching transistor 54 is located between the FD unit 53 and the MIM capacitance element 55, and a drive signal FDG is supplied to the gate electrode of the first conversion efficiency switching transistor 54. When this drive signal FDG reaches a high level, the first conversion efficiency switching transistor 54 is turned on, and charge from the FD unit 53 is transferred to the MIM capacitance element 55 via the first conversion efficiency switching transistor 54. The MIM capacitance element 55 also functions as a storage unit that temporarily stores charge that has overflowed from the photoelectric conversion unit 51.

[0032] When the first conversion efficiency switching transistor 54 is turned on, the region where charge is accumulated becomes the combined region of the FD section 53 and the MIM capacitance element 55, allowing the conversion efficiency when converting the charge generated in the photoelectric conversion section 51 into voltage to be switched. The first conversion efficiency switching transistor 54 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0033] The second conversion efficiency switching transistor 56 is located between the MIM capacitance element 55 and the MIM capacitance element 57, and a drive signal FCG is supplied to the gate electrode of the second conversion efficiency switching transistor 56. When this drive signal FCG reaches a high level, the second conversion efficiency switching transistor 56 is turned on, and charge from the MIM capacitance element 55 is transferred to the MIM capacitance element 57 via the second conversion efficiency switching transistor 56.

[0034] When the second conversion efficiency switching transistor 56 is turned on, the region where charge is accumulated becomes the combined region of the FD section 53, the MIM capacitance element 55, and the MIM capacitance element 57, allowing the conversion efficiency when converting the charge generated in the photoelectric conversion section 51 into voltage to be switched. The second conversion efficiency switching transistor 56 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0035] The MIM capacitance elements 55 and 57 achieve high capacitance without sacrificing the surface area of ​​the Si (silicon) substrate on which the pixel transistors are placed, and have a larger capacitance compared to the FD section 53.

[0036] The reset transistor 58 is connected between the power supply VDD and the MIM capacitor element 57, and a drive signal RST is supplied to the gate electrode of the reset transistor 58. When the drive signal RST is at a high level, the reset transistor 58 is turned on and the potential of the MIM capacitor element 57 is reset to the level of the power supply voltage VDD.

[0037] The amplifying transistor 59 has its gate electrode connected to the FD section 53 and its drain connected to the power supply VDD, and serves as the input to a readout circuit, a so-called source follower circuit, which reads out a signal corresponding to the charge held in the FD section 53. In other words, the source of the amplifying transistor 59 is connected to the vertical signal line 9 via the selection transistor 60, thereby forming a source follower circuit with a constant current source (not shown) connected to one end of the vertical signal line 9.

[0038] The selection transistor 60 is connected between the source of the amplification transistor 59 and the vertical signal line 9, and the gate electrode of the selection transistor 60 is supplied with the drive signal SEL. When the drive signal SEL is at a high level, the selection transistor 60 is turned on and pixel 2 is selected. As a result, the pixel signal output from the amplification transistor 59 is output to the vertical signal line 9 via the selection transistor 31.

[0039] In the following, when each drive signal is active, i.e., at a high level, it will be referred to as the drive signal being turned on, and when each drive signal is inactive, i.e., at a low level, it will be referred to as the drive signal being turned off.

[0040] The pixel 2 shown in Figure 2 comprises an FD section 53, a MIM capacitance element 55, and a MIM capacitance element 57. These capacitances are connected in series, and the conversion efficiency when converting the charge generated in the photoelectric conversion section into voltage can be switched in three stages.

[0041] High conversion efficiency (HCG) is composed of the FD section 53. Medium conversion efficiency (MCG) is composed of (FD section 53 + MIM capacitive element 55). Low conversion efficiency (LCG) is composed of (FD section 53 + MIM capacitive element 55 + MIM capacitive element 57).

[0042] The charge accumulated in the photoelectric conversion unit 51 is received by the FD unit 53 (high conversion efficiency), (FD unit 53 + MIM capacitive element 55) (medium conversion efficiency), or (FD unit 53 + MIM capacitive element 55 + MIM capacitive element 57) (low conversion efficiency) when the transfer transistor 52 is turned on, and then output.

[0043] Under high illumination conditions, the charge accumulated in the photoelectric conversion unit 51 overflows beyond the transfer transistor 52 to the FD unit 53 side and is accumulated in the FD unit 53, MIM capacitance element 55, and MIM capacitance element 57.

[0044] When the amount of received light is small, the FD section 53 is configured to have a high conversion efficiency in which charge is accumulated, and when the amount of received light is large, the (FD section 53 + MIM capacitive element 55 + MIM capacitive element 57) is configured to have a low conversion efficiency in which charge is accumulated. Here, an intermediate conversion efficiency is provided between the high and low conversion efficiency, and a conversion efficiency is provided in which charge is accumulated in the (FD section 53 + MIM capacitive element 55).

[0045] The charge that overflows from the photoelectric conversion unit 51 and accumulates in the FD unit 53, MIM capacitance element 55, and MIM capacitance element 57 is received together with the charge accumulated in the photoelectric conversion unit 51 by (FD unit 53 + MIM capacitance element 55 + MIM capacitance element 57) and output.

[0046] High, medium, and low conversion efficiency readouts are each converted separately using AD conversion, and the choice of which readout signal to use is determined by the amount of each readout signal. At the transition points between high and medium conversion efficiency signals, and between medium and low conversion efficiency signals, the two readout signals may be blended. Using a blended signal suppresses image quality degradation at the transition points.

[0047] <Example of pixel cross-sectional configuration> Figure 3 shows an example of the cross-sectional configuration of pixel 2.

[0048] The N-type semiconductor region 105 constituting the photoelectric conversion unit 51 of pixel 2 receives incident light that enters from the back side (top side in the figure) of the semiconductor substrate 100. The N-type semiconductor region 105 is embedded inside the semiconductor substrate 100, and there is almost no N-type semiconductor region 105 on the surface of the substrate.

[0049] Above the N-type semiconductor region 105 (photoelectric conversion unit 51), a CF (color filter) 102 and an on-chip lens 101 are provided. In the photoelectric conversion unit 51, incident light that enters sequentially through each part is received at the light-receiving surface and photoelectric conversion is performed.

[0050] For example, in the photoelectric conversion unit 51, the N-type semiconductor region 105 is formed as a charge storage region for accumulating electric charge (electrons). In the photoelectric conversion unit 51, the N-type semiconductor region 105 is provided inside the P-type semiconductor region 104 of the semiconductor substrate 100.

[0051] Inside the semiconductor substrate 100, there is a pixel isolation section 106 that electrically isolates multiple pixels 2, and a photoelectric conversion section 51 is provided in the region partitioned by this pixel isolation section 106. When viewed from the perspective of the pixels 2, the pixel isolation section 106 is formed in a grid pattern, for example, interposed between multiple pixels 2, and the photoelectric conversion section 51 is formed within the region partitioned by this pixel isolation section 106.

[0052] The pixel isolation section 106 can be an FFTI (Front Full Trench Isolation). When the pixel isolation section 106 is formed with an FFTI, the FFTI is configured as a trench penetrating the semiconductor substrate 100 (Figure 7). The pixels 2 are separated by an insulator by the FFTI, and each pixel 2 is electrically isolated. An STI (Shallow Trench Isolation) is provided between each transistor. The STI has a structure in which a shallow trench is formed in the element isolation region and an insulating film is embedded within it.

[0053] The wiring layer 120 is located on the front surface (bottom surface) of the semiconductor substrate 100, opposite to the back surface (top surface) where the light-shielding film 103, CF102, on-chip lens 101, and other components are provided.

[0054] The wiring layer 120 includes wiring 122 and an insulating layer 123, and within the insulating layer 123, the wiring 122 is formed to be electrically connected to each element. The wiring layer 120 is a so-called multilayer wiring layer, and is formed by alternately stacking the interlayer insulating film constituting the insulating layer 123 and the wiring 122 multiple times. In this case, the wiring 122 includes wiring to transistors for reading charge from the photoelectric conversion unit 51, such as the transfer transistor 52, and various wirings such as VSL9, which are stacked via the insulating layer 123.

[0055] A support substrate (not shown) can also be provided on the side of the wiring layer 120 opposite to the side where the photoelectric conversion unit 51 is located. For example, a substrate made of silicon semiconductor with a thickness of several hundred micrometers can be provided as the support substrate.

[0056] In the configuration shown in Figure 3, an example is shown in which a logic circuit board 130 on which a logic circuit is formed is laminated on the wiring layer 120. The logic circuit board 130 includes wiring 131 and an insulating layer 133, and within the insulating layer 133, the wiring 131 is formed to be electrically connected to each element. The logic circuit board 130 is also a so-called multilayer wiring layer, and is formed by alternately laminating the interlayer insulating film constituting the insulating layer 133 and the wiring 131 multiple times.

[0057] The light-shielding film 103 is provided on the back side (top side in the figure) of the semiconductor substrate 100 and is located within the CF 102. The light-shielding film 103 is configured to block a portion of the incident light that travels from above the semiconductor substrate 100 to below the semiconductor substrate 100. The light-shielding film 103 is made of a light-shielding material that blocks light. For example, the light-shielding film 103 is formed by sequentially laminating a titanium (Ti) film and a tungsten (W) film. Alternatively, the light-shielding film 103 can be formed by sequentially laminating, for example, a titanium nitride (TiN) film and a tungsten (W) film. The light-shielding film 103 may also be coated with nitride (N) or the like.

[0058] A fixed charge film (SCF) or a P-type semiconductor region (solid-phase diffusion layer) may be formed on the side surface of the pixel separation portion 106 (FFTI). The fixed charge film is formed using a high dielectric material with negative fixed charge so that a positive charge (Hole) accumulation region is formed at the interface with the semiconductor substrate 100, thereby suppressing the generation of dark current. Because the fixed charge film is formed with negative fixed charge, an electric field is applied at the interface with the semiconductor substrate 100 due to the negative fixed charge, and a positive charge (Hole) accumulation region is formed.

[0059] The fixed charge film can be formed, for example, as a hafnium oxide film (HfO2 film). Alternatively, the fixed charge film can be formed to include at least one oxide of other elements, such as hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, or lanthanide elements.

[0060] The sidewall of the FFTI can also be configured to have a layer formed therein as a solid-phase diffused solid-phase layer in which a P-type semiconductor region is conformally formed.

[0061] Here, we will explain using the example of a case where a PN junction is formed between an N-type semiconductor region 105 contained within a semiconductor substrate 100 and a P-type semiconductor region 104 formed around it, thereby forming a photodiode. However, the N-type and P-type can be reversed. If the N-type and P-type are reversed, the pixel 2 can be constructed by substituting N-type for P-type and P-type for N-type in the above and below explanations.

[0062] The structure may also involve embedding SiO2 or the like inside the pixel separation section 106. By embedding SiO2 or the like inside the pixel separation section 106 (a trench formed as FFTI), a configuration can be achieved that more reliably separates adjacent pixels 2.

[0063] By providing such a pixel isolation unit 106, the pixels 2 are electrically isolated, preventing charge leaking from the photoelectric conversion unit 51 (PD: Photo Diode) from leaking into adjacent pixels 2. Therefore, the overflow barrier on the transfer transistor 52 side can be tightened, and the Qs (saturation charge amount) of the photoelectric conversion unit 51 can be increased.

[0064] In the example cross-sectional configuration of pixel 2 shown in Figure 3, the transfer transistor 52 is formed on the right side of the figure, and the transfer transistor 52 is connected to an N-type semiconductor region 105 formed by extending a part of the N-type semiconductor region 105 formed in the semiconductor substrate 100. In the central part of the semiconductor substrate 100, an FD section 53 formed of an N+ region is formed. The FD section 53 is connected to the amplification transistor 59 shown on the left side of the figure by local wiring 121.

[0065] The local wiring 121 is formed from polysilicon or advanced contacts (MIS contacts). Advanced contacts are contacts that use high dielectric constant insulating films. When the local wiring 121 is an advanced contact composed of a high dielectric constant insulating film, in the example shown in Figure 7, it is a metallic insulating film inserted between the FD section 53 and the gate electrode of the amplification transistor 59. For example, the high dielectric constant insulating film is formed from a metal oxide with a high dielectric constant, such as titanium dioxide (TiO2), so as to be a thin film with a thickness of about 2.0 nm to 3.0 nm.

[0066] If the local wiring 121 uses advanced contacts, the N-type density of the FD section 53 can be reduced, thereby lowering the contact resistance. By lowering the N-type density of the FD section 53, the electric field strength at the PN junction with the semiconductor substrate 100 (P-type semiconductor region 104) is weakened, suppressing the generation of dark current. As a result, the pixel 2 avoids the inclusion of dark current in the charge signal, preventing Fixed Pattern Noise (FPN) caused by variations in FD dark current leakage, improving the signal-to-noise ratio at the junction of multiple conversion efficiencies associated with FPN, and thus improving image quality.

[0067] In this example, the FD section 53 and the amplification transistor 59 are connected by local wiring 121. However, in addition to the contacts of the FD section 53, the local wiring 121 (advanced contact) may also be used in other configurations.

[0068] In the wiring layer 120 of pixel 2 shown in Figure 3, six layers of wiring 122 are formed. If we consider the layers from the top (semiconductor substrate 100 side) in order as the 1st layer, 2nd layer, 3rd layer, 4th layer, 5th layer, and 6th layer, then a MIM capacitance element 55 is formed three-dimensionally between the wiring 122 of the 4th layer and the wiring 122 of the 5th layer. The MIM capacitance element 55 is a three-dimensionally formed capacitance with a trench and a capacitance film formed on its sidewall.

[0069] One electrode of the MIM capacitive element 55 is connected to the wiring 122 of the fourth layer, and the other electrode is connected to the wiring 122 of the fifth layer via a via 124. The wiring 122 of the sixth layer is used as a terminal connected to the logic circuit board 130.

[0070] The wiring 122 on the bottom layer of the wiring layer 120 and the wiring 131 on the top layer of the logic circuit board 130 are connected by a metallic bond. Here, copper (Cu) can be used as the metal for the metallic bond, and this is sometimes referred to as a Cu-Cu bond. In the figure, the surfaces that are Cu-Cu bonded are indicated by the symbol CCC.

[0071] The logic circuit board 130 also has a configuration in which multiple wirings 131 are stacked, and Figure 3 shows the case where it is formed of 5 layers. If the layers are numbered 1st layer, 2nd layer, 3rd layer, 4th layer, and 5th layer from the top side (wiring layer 120 side) in the figure, then the wiring 131 of the 1st layer is connected to the wiring 122 of the bottommost layer of wiring layer 120, as described above. The wiring 131 of the 1st layer and the wiring 131 of the 2nd layer are connected by vias.

[0072] A three-dimensional MIM capacitance element 57 is formed between the second layer wiring 131 and the third layer wiring 131. Like the MIM capacitance element 55, this MIM capacitance element 57 is a three-dimensionally formed capacitance with a trench and a capacitance film formed on its side walls.

[0073] Thus, the pixel 2 has capacitances from the FD portion 53, MIM capacitive element 55, and MIM capacitive element 57. The MIM capacitive element 55 is formed in the wiring layer 120 of the semiconductor substrate 100, and the MIM capacitive element 57 is formed in the logic circuit board 130.

[0074] As shown in Figure 3, pixel 2 has a configuration in which a semiconductor substrate 100 including a wiring layer 120 and a logic circuit board 130 are stacked. Referring again to Figure 2, the semiconductor substrate 100 has a configuration including a photoelectric conversion unit 51, a transfer transistor 52, an FD unit 53, a first conversion efficiency switching transistor 54, a MIM capacitance element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplification transistor 59, and a selection transistor 60. The logic circuit board 130 has a configuration including a MIM capacitance element 57.

[0075] Pixel 2 has three capacitances: an FD section 53, an MIM capacitive element 55, and an MIM capacitive element 57. By using these to achieve three conversion efficiencies and reading in three steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0076] <Pixel configuration in the second embodiment> Figure 4 shows an example of the cross-sectional configuration of pixel 2b in the second embodiment, and Figure 5 shows an example of the circuit configuration of pixel 2b. In the following description, pixel 2 described with reference to Figures 2 and 3 will be referred to as pixel 2a in the first embodiment. In the following description, the same reference numerals will be used for parts identical to pixel 2a in the first embodiment, and explanations will be omitted as appropriate.

[0077] The pixel 2b in the second embodiment differs from the pixel 2a in the first embodiment in that it has a configuration in which three substrates are stacked; otherwise, it is basically the same.

[0078] Referring to Figure 4, pixel 2b has a configuration in which a first semiconductor substrate 150, a second semiconductor substrate 160, and a logic circuit board 130 are stacked. Pixel 2 is manufactured by the first semiconductor substrate 150, the second semiconductor substrate 160, and the logic circuit board 130 being manufactured in separate processes, stacked in wafer form, and then separated into individual pieces. Alternatively, it is manufactured by stacking the individual pieces after they have been separated.

[0079] The first semiconductor substrate 150 and the second semiconductor substrate 160 correspond to the semiconductor substrate 100 including the wiring layer 120 in the pixel 2a shown in Figure 3, and have the same configuration as the semiconductor substrate 100 including the wiring layer 120. The first semiconductor substrate 150 is configured to include a photoelectric conversion unit 51.

[0080] The second semiconductor substrate 160 has wiring 162 formed in the insulating layer 163, corresponding to the wiring 122 that was formed in the wiring layer 120 (Figure 3). Transistors are also formed on the second semiconductor substrate 160, and in the example shown in Figure 4, the first conversion efficiency switching transistor 54 and the amplification transistor 59 are formed and connected to the FD section 53 formed in the first semiconductor substrate 150 via TCV (Through-CIS-Via) 161.

[0081] The wiring 162 of the second semiconductor substrate 160 of pixel 2b shown in Figure 4 is formed of 6 layers. If we consider the layers to be the 1st, 2nd, 3rd, 4th, 5th, and 6th layers in order from the top side (the side of the first semiconductor substrate 150) in the figure, the wiring of the 1st layer is connected to the TCV 161 and is connected to the contacts that are connected to the first conversion efficiency switching transistor 54 and the amplification transistor 59, respectively.

[0082] A three-dimensional MIM capacitive element 55 is formed between the wiring 162 of the fourth layer and the wiring 162 of the fifth layer. One electrode of the MIM capacitive element 55 is connected to the wiring 162 of the fourth layer, and the other electrode is connected to the wiring 162 of the fifth layer via a via 124. The wiring 162 of the fifth layer and the wiring 162 of the sixth layer are connected by wiring formed in the vertical direction, and the wiring 162 of the sixth layer is used as a connection terminal that is Cu-Cu bonded to the logic circuit board 130.

[0083] The logic circuit board 130 has the same configuration as the logic circuit board 130 shown in Figure 3, and the MIM capacitive element 57 is formed three-dimensionally between the second layer wiring 131 and the third layer wiring 131.

[0084] Referring to the example circuit configuration of pixel 2b shown in Figure 5, the circuit configuration is the same as that of pixel 2a shown in Figure 2. The first semiconductor substrate 150 has a configuration that includes a photoelectric conversion unit 51, a transfer transistor 52, and an FD unit 53.

[0085] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, an MIM capacitance element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplification transistor 59, and a selection transistor 60. The transfer transistor 52 included in the first semiconductor substrate 150 and the first conversion efficiency switching transistor 54 and amplification transistor 59 included in the second semiconductor substrate 160 are connected by a TCV.

[0086] The logic circuit board 130 is configured to include MIM capacitive elements 57. The logic circuit board 130 and the second semiconductor substrate 160 are connected by a Cu-Cu junction.

[0087] Pixel 2 has three capacitances: an FD section 53, an MIM capacitive element 55, and an MIM capacitive element 57. By using these to achieve three conversion efficiencies and reading in three steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0088] <Pixel configuration in the third embodiment> Figure 6 shows an example of the circuit configuration of pixel 2c in the third embodiment, and Figure 7 shows an example of the cross-sectional configuration of pixel 2c. In the following description, the same reference numerals are used for parts identical to those of pixel 2b in the second embodiment, and explanations are omitted as appropriate.

[0089] The pixel 2c in the third embodiment differs from the pixel 2b in the second embodiment in that the MIM capacitive elements 55 and 57 are formed within the second semiconductor substrate 160c, but otherwise it is basically the same.

[0090] Referring to the example circuit configuration of pixel 2c shown in Figure 6, the first semiconductor substrate 150 is configured to include a photoelectric conversion unit 51, a transfer transistor 52, and an FD unit 53.

[0091] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, an MIM capacitance element 55, a second conversion efficiency switching transistor 56, an MIM capacitance element 57, a reset transistor 58, an amplification transistor 59, and a selection transistor 60. The FD section 53 included in the first semiconductor substrate 150 and the first conversion efficiency switching transistor 54 and amplification transistor 59 included in the second semiconductor substrate 160 are connected by a TCV.

[0092] Referring to the example of the cross-sectional configuration of pixel 2c shown in Figure 7, MIM capacitance elements 55 and 57 are provided within the second semiconductor substrate 160c. MIM capacitance elements 55 and 57 are formed between the fourth layer wiring 162 and the fifth layer wiring 162 of the second semiconductor substrate 160c.

[0093] The MIM capacitance element 55 is formed near the center of the second semiconductor substrate 160c in the figure. One electrode of the MIM capacitance element 55 is connected to the wiring 162 of the fourth layer, and the other electrode is connected to the wiring 162 of the fifth layer via a via 124. Similarly, the MIM capacitance element 57 is formed on the left side of the second semiconductor substrate 160c in the figure. One electrode of the MIM capacitance element 57 is connected to the wiring 162 of the fourth layer, and the other electrode is connected to the wiring 162 of the fifth layer via a via 124.

[0094] Thus, the second semiconductor substrate 160c can be configured to have multiple MIM capacitive elements, in the example shown in Figures 6 and 7, two MIM capacitive elements 55 and one MIM capacitive element 57. When the size of the pixel 2 is large, even if multiple MIM capacitive elements are provided on a single semiconductor substrate, the MIM capacitive elements can be formed to a size that ensures the capacitance of each MIM capacitive element. A configuration in which multiple MIM capacitive elements are provided on the second semiconductor substrate 160c can be applied to pixels 2 of relatively large size.

[0095] Figures 6 and 7 illustrate an example where two MIM capacitance elements 55 and 57 are provided on the second semiconductor substrate 160. However, it is also possible to configure the system to provide multiple MIM capacitance elements on the logic circuit board 130.

[0096] The third embodiment may be combined with the first embodiment to provide a configuration in which multiple MIM capacitive elements are formed within the semiconductor substrate 100. The third embodiment may also be combined with the second embodiment to provide a configuration in which multiple MIM capacitive elements are provided within the second semiconductor substrate 160, and MIM capacitive elements are also provided within the logic circuit board 130.

[0097] Pixel 2c has three capacitances: an FD section 53, a MIM capacitive element 55, and a MIM capacitive element 57. By using these to achieve three conversion efficiencies and reading in three steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0098] In the first to third embodiments, the capacitance of MIM capacitance element 55 and the capacitance of MIM capacitance element 57 may be the same or different.

[0099] <Regarding the operation of pixel 2> The operation of pixel 2 in the first to third embodiments will be described with reference to Figure 8. In Figure 8, PD represents the photoelectric conversion unit 51, FD represents the FD unit 53, MIM1 represents the MIM capacitive element 55, and MIM2 represents the MIM capacitive element 57.

[0100] At time t1, a reset operation is performed on pixel 2. The reset operation is performed, for example, when the shutter is operated, and the drive signal TG supplied to the transfer transistor 52, the drive signal FDG supplied to the first conversion efficiency switching transistor 54, the drive signal FCG supplied to the second conversion efficiency switching transistor 56, and the drive signal RST supplied to the reset transistor 58 are turned on. Each drive signal is turned on for a predetermined period of time and then turned off.

[0101] During the exposure period at time t2, the drive signals TG and RST are in the off state, while the drive signals FDG and FCG are in the on state. Charge is accumulated in the photoelectric conversion unit 51 during the exposure period. During the exposure period, any charge that overflows from the photoelectric conversion unit 51 via the transfer transistor 52 is transferred to the FD unit 53, the MIM capacitive element 55, and the MIM capacitive element 57.

[0102] At time t3, an MCG (medium conversion efficiency) reset period is provided. During the MCG reset period, the drive signals FCG and FDG are turned on for a predetermined period of time, after which the MCG reset is performed by turning off the drive signal FCG while the drive signal FDG remains on, and turning on the drive signal SEL. The MCG (medium conversion efficiency) is the case when the FD unit 53 and the MIM capacitive element 55 are used, and during the MCG reset period, the FD unit 53 and the MIM capacitive element 55 are reset.

[0103] At time t4, an HCG (High Conversion Efficiency) reset period is provided. The high conversion efficiency is comprised of the FD unit 53. During the HCG reset period, drive signals TG, FDG, FCG, and RST are in the off state. When drive signal SEL is turned on, the FD unit 53 is reset.

[0104] When reading from the photoelectric conversion unit 51 (PD: photodiode) begins, the drive signal TG supplied to the transfer transistor 52 is turned on for a predetermined period of time. Reading from the photodiode is performed by CDS (correlated double sampling) drive. CDS drive resets the FD to a predetermined potential, reads out this predetermined potential as the reset potential, then transfers the signal charge stored in the PD to the FD, and reads out the signal charge of the FD as the signal level.

[0105] As described later, after reading from the photodiode using CDS drive, reading from the photodiode and MIM capacitor element is performed using DDS (double data sampling) drive. DDS drive reads the signal charge held or stored in the FD as a signal level, then resets the FD to a predetermined potential and reads that predetermined potential as the reset level.

[0106] Since reading from the PD is performed by CDS drive, as described above, an MCG reset period and an HCG reset period are provided, and during each period, a reset signal for medium conversion efficiency and a reset signal for high conversion efficiency are acquired.

[0107] At time t5, an HCG readout period is established. For a predetermined time before the start of the HCG readout period, the drive signal TG is turned on, which turns on the transfer transistor 52 and transfers charge from the photoelectric conversion unit 51 to the FD unit 53. After the drive signal TG is turned off, the drive signal SEL is turned on, which turns on the selection transistor 60. Since the high conversion efficiency is formed in the FD unit 53, the charge accumulated in the FD unit 53 is read out during the HCG readout period.

[0108] At time t6, an MCG readout period is established. When the HCG readout period ends, the drive signal SEL is turned off and the drive signal FDG is turned on, thereby turning on the first conversion efficiency switching transistor 54. When the first conversion efficiency switching transistor 54 is turned on, the drive signal TG is turned on, thereby turning on the transfer transistor 52. With the transfer transistor 52 and the first conversion efficiency switching transistor 54 turned on, charge flows to the FD section 53 and the MIM capacitance element 55.

[0109] After the drive signal TR is turned off, the drive signal SEL is turned on, which turns on the selection transistor 60, and the charge stored in the FD section 53 and the MIM capacitance element 55 is read out.

[0110] At time t7, an LCG readout period is provided. After the MCG readout period ends, the drive signals FCG and TG are turned ON. Since the drive signal FDG remains ON, the transfer transistor 52, the first conversion efficiency switching transistor 54, and the second conversion efficiency switching transistor 56 are turned ON, and charge is transferred to the FD unit 53, the MIM capacitance element 55, and the MIM capacitance element 57.

[0111] Since the low conversion efficiency is formed by (FD section 53 + MIM capacitive element 55 + MIM capacitive element 57), during the LCG readout period, the charge accumulated in (FD section 53 + MIM capacitive element 55 + MIM capacitive element 57) is read out.

[0112] At time t8, an LCG reset period is provided. At the end of the LCG readout period, the drive signal SEL is turned off. After the drive signal SEL is turned off, the drive signal RST is turned on for a predetermined time, which turns on the reset transistor 58 and resets the FD section 53, MIM capacitance element 55, and MIM capacitance element 57.

[0113] Once the LCG reset period ends, the drive signal SEL is turned off. Through this series of operations, the signals for HCG (high conversion efficiency), MCG (medium conversion efficiency), and LCG (low conversion efficiency) are read out, respectively.

[0114] With the configuration and operation of pixel 2 as described above, the Qs (saturation charge amount) can be increased by overflow driving using the MIM capacitive element 57 as the capacitive element. Since the pixels are separated by through trenches (pixel separation section 106) that penetrate the semiconductor substrate 100, blooming to adjacent pixels can be prevented, and the potential under the transfer transistor can be tightened. As a result, the Qs of the photodiode (photoelectric conversion section 51) is large, and the S / N step difference in the high-illumination junction can be suppressed.

[0115] By using a configuration that reads the data in three steps using three different conversion efficiencies, it is possible to suppress the deterioration of the signal-to-noise ratio step at the connection point.

[0116] <Pixel configuration in the fourth embodiment> Figure 9 shows an example of the circuit configuration of pixel 2d in the fourth embodiment, and Figure 10 shows an example of the cross-sectional configuration of pixel 2d. In the following description, the same reference numerals are used for parts identical to those of pixel 2b in the second embodiment, and explanations are omitted as appropriate.

[0117] In the fourth embodiment, pixel 2d is configured in which a wiring capacitance 201 is further added to pixel 2b in the second embodiment.

[0118] Referring to the example circuit configuration of pixel 2d shown in Figure 9, the first semiconductor substrate 150 is configured to include a photoelectric conversion unit 51, a transfer transistor 52, and an FD unit 53.

[0119] The second semiconductor substrate 160 has a configuration that includes a first conversion efficiency switching transistor 54, an MIM capacitance element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplification transistor 59, a selection transistor 60, a wiring capacitance 201, and a third conversion efficiency switching transistor 202.

[0120] The logic circuit board 130 is configured to include a MIM capacitive element 57.

[0121] The wiring capacitance 201 is provided between the first conversion efficiency switching transistor 54 and the third conversion efficiency switching transistor 202. The pixel 2d has a configuration that includes four components: an FD section 53, a wiring capacitance 201, a MIM capacitance element 55, and a MIM capacitance element 57, as a storage unit for accumulating charge from the photoelectric conversion unit 51.

[0122] Referring to the example of the cross-sectional configuration of pixel 2d shown in Figure 10, a MIM capacitance element 55 and a wiring capacitance 201 are provided within the second semiconductor substrate 160d. The MIM capacitance element 55 is formed between the fourth layer wiring 162 and the fifth layer wiring 162 of the second semiconductor substrate 160d. The wiring capacitance 201 is provided between the first layer wiring 162 and the second layer wiring 162.

[0123] Figure 11 is an enlarged view of the wiring capacitance 201. The wiring capacitance 201 is assigned to wiring 161-2, which is formed in a predetermined layer of wiring 161, which is composed of multiple layers of the second semiconductor substrate 160d. Wiring 161-2, which forms the wiring capacitance 201, is connected to wiring 162-1. This wiring 162-1 is connected to an N+ diffusion layer formed in the layer in which the first conversion efficiency switching transistor 54 and the third conversion efficiency switching transistor 202 are formed.

[0124] The wiring capacitance 201 is formed by using a portion of the wiring 161 which is composed of multiple layers of the second semiconductor substrate 160d. The pixel 2d further includes such wiring capacitance 201 as a storage unit.

[0125] Pixel 2d has four capacitances: FD section 53, MIM capacitive element 55, MIM capacitive element 57, and wiring capacitance 201. By using these to achieve four conversion efficiencies and reading in four steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0126] Figures 9 and 10 illustrate the case where the wiring capacitance 201 is provided on the second semiconductor substrate 160d, but it can also be provided on the logic circuit board 130.

[0127] The fourth embodiment may be combined with the first embodiment to form a wiring capacitance 201 within the semiconductor substrate 100. The fourth embodiment may also be combined with the third embodiment to form a configuration in which a plurality of MIM capacitance elements and wiring capacitance 201 are provided within the second semiconductor substrate 160.

[0128] <Pixel configuration in the fifth embodiment> Figure 12 shows an example of the circuit configuration of pixel 2e in the fifth embodiment, and Figure 13 shows an example of the cross-sectional configuration of pixel 2e. In the following description, the same reference numerals are used for parts identical to those of pixel 2b in the second embodiment, and explanations are omitted as appropriate.

[0129] The pixel 2e in the fifth embodiment differs from the pixel 2 in the other embodiments in that multiple pixels share the FD section 53 to the selection transistor 60. Here, we will explain using the case where four pixels 2e share the FD section 53 to the selection transistor 60 as an example.

[0130] Referring to the example circuit configuration of pixel 2e shown in Figure 12, the photoelectric conversion unit 51-1 and transfer transistor 52-1, the photoelectric conversion unit 51-2 and transfer transistor 52-2, the photoelectric conversion unit 51-3 and transfer transistor 52-3, and the photoelectric conversion unit 51-4 and transfer transistor 52-4 are formed within the first semiconductor substrate 150e. The FD unit 53 to the selection transistor 60 are connected (shared) to these four photoelectric conversion units 51-1 to 51-4.

[0131] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, an MIM capacitance element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplification transistor 59, and a selection transistor 60. The logic circuit board 130 is configured to include an MIM capacitance element 57.

[0132] The FD section 53 and the selection transistor 60 are shared by four photoelectric conversion sections 51 (pixels 2e). Figure 13 shows an example of the cross-sectional configuration of two pixels 2e arranged side by side among the four pixels 2e. An FD section 53 is formed at the bottom of the first semiconductor substrate 150e of pixels 2e-1 and 2e-2, and the FD section 53 is connected to a first conversion efficiency switching transistor 54 and an amplification transistor 59 formed in the second semiconductor substrate 160 by a TCV 161 formed in the second semiconductor substrate 160.

[0133] In the first semiconductor substrate 150e of pixel 2e-1, near the lower center in the figure, a transfer transistor 52-1 (gate) for reading charge from the N-type semiconductor region 105 (photoelectric conversion unit 51-1) is formed. Similarly, in the first semiconductor substrate 150e of pixel 2e-2, near the lower center in the figure, a transfer transistor 52-2 (gate) for reading charge from the N-type semiconductor region 105 (photoelectric conversion unit 51-1) is formed.

[0134] The photoelectric conversion unit 51 and transfer transistor 52 formed in the first semiconductor substrate 150e are formed for each pixel 2e, but the first conversion efficiency switching transistor 54 to selection transistor 60 (excluding the MIM capacitive element 57) formed in the second semiconductor substrate 160 and the MIM capacitive element 57 formed in the logic circuit board 130 are shared by 4 pixels 2e.

[0135] As in the first embodiment, a configuration can also be applied in which the first semiconductor substrate 150e and the second semiconductor substrate 160 shown in Figure 13 are formed within the semiconductor substrate 100, as in pixel 2 of the first embodiment.

[0136] The second to fourth embodiments can be applied to the configuration of the second semiconductor substrate 160 and the logic circuit board 130. In other words, the fifth embodiment can also be implemented in combination with the second to fourth embodiments. The example shown in Figures 12 and 13 is an example of combining the second and fifth embodiments.

[0137] The third and fifth embodiments may be combined to form a configuration in which multiple MIM capacitance elements are formed on the second semiconductor substrate 160 or logic circuit board 130. The fourth and fifth embodiments may be combined to provide wiring capacitance 201 on the second semiconductor substrate 160 or logic circuit board 130. The third to fifth embodiments may be combined to provide a configuration in which multiple MIM capacitance elements and wiring capacitance 201 are provided on the second semiconductor substrate 160 or logic circuit board 130, and these multiple MIM capacitance elements and wiring capacitance 201 are shared by multiple pixels 2.

[0138] Pixel 2e has three capacitances: an FD section 53, an MIM capacitive element 55, and an MIM capacitive element 57. By using these to achieve three conversion efficiencies and reading in three steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0139] In pixel 2e, multiple pixels 2e share the FD section 53 or the selection transistor 60, which allows for miniaturization of the pixels.

[0140] <Pixel configuration in the sixth embodiment> Figure 14 shows an example of the cross-sectional configuration of pixel 2f in the sixth embodiment, and Figure 15 shows an example of the circuit configuration of pixel 2f. In the following description, the same reference numerals are used for parts identical to those of pixel 2b in the second embodiment, and explanations are omitted as appropriate.

[0141] The pixel 2f in the sixth embodiment differs from the pixel 2 in the other embodiments in that it is configured to have multiple photoelectric conversion units 51 within a single pixel. Here, we will explain using the case where there are two photoelectric conversion units 51 within a single pixel as an example. If the area enclosed by the pixel separation unit 106 is defined as one pixel 2f, then one pixel 2f has two light-receiving units.

[0142] In the pixel 2f shown in Figure 14, a P-type semiconductor region 301 is formed in the central part of the N-type semiconductor region 105, dividing it into two regions: N-type semiconductor region 105-1 and N-type semiconductor region 105-2. N-type semiconductor region 105-1 and N-type semiconductor region 105-2 each form a PD (photoelectric conversion unit 51).

[0143] A transfer transistor 52-1 is provided in the N-type semiconductor region 105-1 (photoelectric conversion section 51-1), and a transfer transistor 52-2 is provided in the N-type semiconductor region 105-2 (photoelectric conversion section 51-2). An FD section 53 is formed between the transfer transistors 52-1 and 52-2, and the FD section 53 is connected to a first conversion efficiency switching transistor 54 and an amplification transistor 59 formed in the second semiconductor substrate 160 by a TCV 161 formed in the second semiconductor substrate 160.

[0144] The configurations of the second semiconductor substrate 160 and the logic circuit board 130 can be configured in the same way as the configurations of the second semiconductor substrate 160 and the logic circuit board 130 shown in Figure 4.

[0145] Referring to the example circuit configuration of pixel 2f shown in Figure 15, a photoelectric conversion unit 51-1 and a transfer transistor 52-1, a photoelectric conversion unit 51-2 and a transfer transistor 52-2, and an FD unit 53 are formed within the first semiconductor substrate 150. Each pixel 2f includes a photoelectric conversion unit 51-1 and a photoelectric conversion unit 51-2, and one FD unit 53 is connected to these two photoelectric conversion units 51-1 and 51-2.

[0146] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, an MIM capacitance element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplification transistor 59, and a selection transistor 60. The logic circuit board 130 is configured to include an MIM capacitance element 57.

[0147] The FD section 53 and the selection transistor 60 are configured to be shared by two photoelectric conversion sections 51 included in one pixel.

[0148] As in the first embodiment, a configuration can also be applied in which the first semiconductor substrate 150f and the second semiconductor substrate 160 shown in Figure 14 are formed within the semiconductor substrate 100, as in pixel 2 of the first embodiment.

[0149] The second to fourth embodiments can be applied to the configuration of the second semiconductor substrate 160 and the logic circuit board 130. In other words, the sixth embodiment can also be implemented in combination with the second to fourth embodiments. The example shown in Figures 14 and 15 is an example of combining the second and sixth embodiments.

[0150] The third and sixth embodiments may be combined to form a configuration in which multiple MIM capacitance elements are formed on the second semiconductor substrate 160 or logic circuit board 130. The fourth and sixth embodiments may be combined to provide wiring capacitance 201 on the second semiconductor substrate 160 or logic circuit board 130. The third to sixth embodiments may be combined to provide multiple MIM capacitance elements and wiring capacitance 201 on the second semiconductor substrate 160 or logic circuit board 130, and these multiple MIM capacitance elements and wiring capacitance 201 may be shared by multiple pixels 2.

[0151] Pixel 2f has three capacitances: an FD section 53, an MIM capacitance element 55, and an MIM capacitance element 57. By using these to achieve three conversion efficiencies and reading in three steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0152] Pixel 2f can be applied, for example, to a pixel used for phase difference detection.

[0153] <Pixel configuration in the seventh embodiment> Figure 16 shows an example of the circuit configuration of pixel 2g in the seventh embodiment. In the following description, the same reference numerals are used for parts identical to those of pixel 2b in the second embodiment, and their descriptions are omitted as appropriate.

[0154] The pixel 2g in the seventh embodiment differs from the pixel 2 in the other embodiments in that it is configured to have multiple photoelectric conversion units 51 within a single pixel. Here, we will explain using the case where there are two photoelectric conversion units 51 within a single pixel as an example.

[0155] Furthermore, the pixel 2g in the seventh embodiment differs from the pixel 2 in the other embodiments in that multiple pixels share the FD section 53 to the selection transistor 60. Here, we will explain using the case where four pixels 2g share the FD section 53 to the selection transistor 60 as an example.

[0156] One pixel 2g, like pixel 2f shown in Figure 14, is configured to be divided into two regions, N-type semiconductor region 105-1 and N-type semiconductor region 105-2, by forming a P-type semiconductor region 301 in the central part of the N-type semiconductor region 105. N-type semiconductor region 105-1 and N-type semiconductor region 105-2 each form a PD (photoelectric converter 51).

[0157] A transfer transistor 52-1 is provided in the photoelectric conversion unit 51-1, and a transfer transistor 52-2 is provided in the photoelectric conversion unit 51-2, and these two photoelectric conversion units 51 form one pixel 2g-1. A transfer transistor 52-3 is provided in the photoelectric conversion unit 51-3, and a transfer transistor 52-4 is provided in the photoelectric conversion unit 51-4, and these two photoelectric conversion units 51 form one pixel 2g-2.

[0158] A transfer transistor 52-5 is provided in the photoelectric conversion unit 51-5, and a transfer transistor 52-6 is provided in the photoelectric conversion unit 51-6, and these two photoelectric conversion units 51 form one pixel 2g-3. A transfer transistor 52-7 is provided in the photoelectric conversion unit 51-7, and a transfer transistor 52-8 is provided in the photoelectric conversion unit 51-8, and these two photoelectric conversion units 51 form one pixel 2g-4.

[0159] The configurations of the second semiconductor substrate 160 and the logic circuit board 130 can be configured in the same way as the configurations of the second semiconductor substrate 160 and the logic circuit board 130 shown in Figure 4.

[0160] Referring to the example circuit configuration of pixel 2g shown in Figure 16, the photoelectric conversion units 51-1 to 51-8, transfer transistors 52-1 to 52-8, and FD unit 53 are formed within the first semiconductor substrate 150g. One FD unit 53 is connected to each of the eight photoelectric conversion units 51 (four pixels 2g, pixels 2g-1 to 2g-4).

[0161] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, an MIM capacitance element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplification transistor 59, and a selection transistor 60. The logic circuit board 130 is configured to include an MIM capacitance element 57.

[0162] The FD section 53 to the selection transistor 60 are configured to be shared by the eight photoelectric conversion sections 51 included in the four pixels 2g.

[0163] As in the first embodiment, a configuration can also be applied in which the first semiconductor substrate 150g and the second semiconductor substrate 160 shown in Figure 16 are formed within the semiconductor substrate 100, as in pixel 2 of the first embodiment.

[0164] The second to fourth embodiments can be applied to the configuration of the second semiconductor substrate 160 and the logic circuit board 130. In other words, the seventh embodiment can also be implemented in combination with the second to fourth embodiments. The example shown in Figure 16 is an example of combining the second and seventh embodiments.

[0165] The third and seventh embodiments may be combined to form a configuration in which multiple MIM capacitance elements are formed on the second semiconductor substrate 160 or logic circuit board 130. The fourth and seventh embodiments may be combined to provide wiring capacitance 201 on the second semiconductor substrate 160 or logic circuit board 130. The third to sixth embodiments may be combined to provide a configuration in which multiple MIM capacitance elements and wiring capacitance 201 are provided on the second semiconductor substrate 160 or logic circuit board 130, and these multiple MIM capacitance elements and wiring capacitance 201 are shared by multiple pixels 2.

[0166] Pixel 2g has three capacitances: FD section 53, MIM capacitive element 55, and MIM capacitive element 57. By using these to achieve three conversion efficiencies and reading in three steps, it is possible to suppress deterioration of the S / N step at the connection point.

[0167] In the case of pixel 2g, the FD section 53 to the selection transistor 60 are shared among multiple pixels 2g, which allows for miniaturization of the pixels.

[0168] Pixel 2g can be applied, for example, to pixels used for phase difference detection.

[0169] <Regarding pixel manufacturing> Referring to Figure 17, the manufacturing of pixel 2 will be explained. Figure 17 uses the case of manufacturing pixel 2b shown in Figure 4 as an example.

[0170] In step S11, various parts included in the first semiconductor substrate 150, such as the photoelectric conversion unit 51, the transfer transistor 52, and the FD unit 53, are formed on the first semiconductor substrate 150.

[0171] In step S12, transistors are formed in the second semiconductor substrate 160. For example, the first conversion efficiency switching transistor 54 and the amplification transistor 59 are formed.

[0172] In step S13, wiring 122 and MIM capacitance elements 55 are further formed on the second semiconductor substrate 160. When multiple MIM capacitance elements are formed on the second semiconductor substrate 160, multiple MIM capacitance elements are formed within the second semiconductor substrate 160 in step S13. When wiring capacitance 201 is formed on the second semiconductor substrate 160, the wiring capacitance 201 is formed within the second semiconductor substrate 160 in step S13.

[0173] While the first semiconductor substrate 150 and the second semiconductor substrate 160 are being manufactured, processing of the logic circuit board 130 is performed in processes S21 and S22. In process S21, for example, the first conversion efficiency switching transistor 54 and wiring 131 are formed on the logic circuit board 130.

[0174] In step S22, MIM capacitance elements 57 are formed within the logic circuit board 130. If multiple MIM capacitance elements are to be formed on the logic circuit board 130, multiple MIM capacitance elements are formed within the logic circuit board 130 in step S22. If wiring capacitance is to be formed on the logic circuit board 130, wiring capacitance is formed within the logic circuit board 130 in step S22. If MIM capacitance elements or wiring capacitance are not to be formed within the logic circuit board 130, the step of forming MIM capacitance elements or wiring capacitance can be skipped in step S22.

[0175] In step S14, the logic circuit board 130 manufactured in steps S21 and S22 is laminated onto the first semiconductor substrate 150 and the second semiconductor substrate 160 manufactured in steps S11 to S13. The logic circuit board 130 is bonded to the second semiconductor substrate 160. In step S15, the on-chip lens 101, CF102, and light-shielding film 103 are formed on the first semiconductor substrate 150, thereby manufacturing the pixel 2 shown in Figure 3.

[0176] Pixel 2 in other embodiments can also be manufactured using essentially the same manufacturing process.

[0177] According to this technology, by using a pixel structure that includes multiple MIM capacitive elements, the dynamic range can be greatly expanded, the conversion efficiency can be changed in steps, and the step in the signal-to-noise ratio when switching conversion efficiency can be reduced.

[0178] <Examples of application to electronic devices> This technology is not limited to application to image sensors. In other words, this technology can be applied to all electronic devices that use an image sensor in the image acquisition unit (photoelectric conversion unit), such as imaging devices like digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use an image sensor in the image reading unit. The image sensor may be formed as a single chip, or it may be in the form of a module with imaging functions in which the imaging unit and signal processing unit or optical system are packaged together.

[0179] Figure 18 is a block diagram showing an example configuration of an imaging device as an electronic device to which this technology is applied.

[0180] The image sensor 1000 in Figure 18 comprises an optical unit 1001 consisting of a lens group and the like, an image sensor (imaging device) 1002 employing the configuration of the imaging device 1 in Figure 1, and a DSP (Digital Signal Processor) circuit 1003 which is a camera signal processing circuit. The image sensor 1000 also includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, operation unit 1007, and power supply unit 1008 are interconnected via a bus line 1009.

[0181] The optical unit 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the image sensor 1002. The image sensor 1002 converts the amount of incident light formed on the imaging surface by the optical unit 1001 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal. The imaging device 1 shown in Figure 1 can be used as this image sensor 1002.

[0182] The display unit 1005 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays video or still images captured by the image sensor 1002. The recording unit 1006 records the video or still images captured by the image sensor 1002 onto a recording medium such as a hard disk or semiconductor memory.

[0183] The control unit 1007 issues operation commands for various functions of the image sensor 1000 under user operation. The power supply unit 1008 appropriately supplies various power sources to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and control unit 1007.

[0184] <Examples of application to endoscopic surgical systems> The technology described herein (the Technology) can be applied to a variety of products. For example, the Technology described herein may be applied to an endoscopic surgical system.

[0185] Figure 19 shows an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0186] Figure 19 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0187] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0188] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0189] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0190] The CCU11201 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU11201 receives image signals from the camera head 11102 and performs various image processing operations on these image signals, such as development processing (demosaic processing), to display the image based on those image signals.

[0191] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0192] The light source device 11203 consists of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0193] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0194] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or vascular sealing. The insufflation device 11206 delivers gas into the patient's body cavity via the insufflation tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing a field of view by the endoscope 11100 and securing the operator's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0195] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical area, can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to time-divisionally capture images corresponding to each of the RGB light sources by irradiating the observation target with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0196] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0197] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used during normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0198] Figure 20 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 19.

[0199] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with one another.

[0200] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0201] The imaging unit 11402 may consist of one image sensor (a so-called single-chip system) or multiple image sensors (a so-called multi-chip system). If the imaging unit 11402 is configured as a multi-chip system, for example, each image sensor may generate image signals corresponding to RGB, and these signals may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip system, multiple lens units 11401 may be provided corresponding to each image sensor.

[0202] Furthermore, the imaging unit 11402 does not necessarily have to be located in the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0203] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0204] The communication unit 11404 consists of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0205] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 to control the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals include information regarding imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0206] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0207] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0208] The communication unit 11411 consists of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0209] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0210] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0211] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates control signals to control the driving of the camera head 11102.

[0212] Furthermore, the control unit 11413 displays the captured image showing the surgical area on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery with confidence.

[0213] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0214] In the illustrated example, communication was performed via a wired connection using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0215] In this specification, "system" refers to an entire apparatus composed of multiple devices.

[0216] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0217] It should be noted that the embodiments of this technology are not limited to those described above, and various modifications are possible without departing from the spirit of this technology.

[0218] Furthermore, this technology can also be configured as follows. (1) A photoelectric conversion unit that converts light into electric charge, Three or more storage units for temporarily storing electric charge, A transfer unit that transfers charge from the photoelectric conversion unit to the storage unit, A conversion efficiency switching unit that controls the conductivity between the storage units. Equipped with, At least two of the three or more storage units are capacitive elements. The three or more storage units store the charge that overflows from the photoelectric conversion unit. Image sensor. (2) The aforementioned capacitance element is a MIM (Metal-Insulator-Metal) capacitance element. The image sensor described in (1) above. (3) The aforementioned storage unit is equipped with wiring capacity. The image sensor described in (1) or (2) above. (4) It also features through trenches to separate the pixels. The image sensor according to any one of (1) to (3) above. (5) The photoelectric conversion unit is provided within the first semiconductor substrate, The capacitive element and the conversion efficiency switching unit are provided within the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are stacked. The image sensor described in any of (1) to (4) above. (6) The second semiconductor substrate is provided with a plurality of the capacitive elements. The image sensor described in (5) above. (7) A logic circuit board on which a logic circuit is formed is stacked on the second semiconductor substrate. The capacitive element is provided within the logic circuit board. The image sensor described in (5) above. (8) The capacitive element and the conversion efficiency switching unit are shared by multiple photoelectric conversion units. The image sensor described in any of (1) to (7) above. (9) Each pixel contains two of the aforementioned photoelectric conversion units, The capacitive element and the conversion efficiency switching unit are shared by the two photoelectric conversion units. The image sensor described in any of (1) to (7) above. (10) Each pixel contains two of the aforementioned photoelectric conversion units, The capacitive element and the conversion efficiency switching unit are shared by four pixels. The image sensor described in any of (1) to (7) above. (11) The three or more storage units consist of an FD (Floating Diffusion) and two MIM capacitance elements, and by controlling the conversion efficiency switching unit, charge is read out from the photoelectric conversion unit at high conversion efficiency, medium conversion efficiency, and low conversion efficiency, respectively. The image sensor according to any one of (2) to (10) above. (12) Photoelectric conversion unit, A transfer transistor connected to the aforementioned photoelectric conversion unit, A floating diffusion connected to the transfer transistor, A first conversion efficiency switching transistor connected to the floating diffusion, A second conversion efficiency switching transistor connected to the first conversion efficiency switching transistor, A reset transistor connected to the second conversion efficiency switching transistor, It comprises a first storage unit and a second storage unit, The first storage unit is connected between the first conversion efficiency switching transistor and the second conversion efficiency switching transistor. The second storage unit is connected between the second conversion efficiency switching transistor and the reset transistor, The floating diffusion accumulates the charge that overflows from the photoelectric conversion unit. Image sensor. (13) The charge overflowing from the photoelectric conversion unit is stored in the floating diffusion and the first storage unit. The image sensor described in (12) above. (14) The charge overflowing from the photoelectric conversion unit is stored in the floating diffusion, the first storage unit, and the second storage unit. The image sensor described in (12) or (13) above. (15) The capacities of the first storage unit and the second storage unit are, respectively, larger than the capacity of the floating diffusion. The image sensor according to any one of (12) to (14) above. (16) The system further comprises an amplifying transistor connected to the floating diffusion and a selection transistor connected to the amplifying transistor. The image sensor according to any one of (12) to (15) above. (17) A photoelectric conversion unit that converts light into electric charge, Three or more storage units for temporarily storing electric charge, A transfer unit that transfers charge from the photoelectric conversion unit to the storage unit, A conversion efficiency switching unit that controls the conductivity between the storage units. Equipped with, At least two of the three or more storage units are capacitive elements. The three or more storage units store the charge that overflows from the photoelectric conversion unit. Image sensor and A processing unit that processes signals from the image sensor and Electronic devices equipped with these features. [Explanation of Symbols]

[0219] 1 Imaging device, 2 Pixel, 3 Pixel array section, 4 Vertical drive circuit, 5 Column signal processing circuit, 6 Horizontal drive circuit, 7 Output circuit, 8 Control circuit, 9 Vertical signal line, 10 Pixel drive line, 11 Horizontal signal line, 13 Input / output terminal, 31 Selection transistor, 51 Photoelectric conversion section, 52 Transfer transistor, 53 FD section, 54 First conversion efficiency switching transistor, 55 MIM capacitance element, 56 Second conversion efficiency switching transistor, 57 MIM capacitance element, 58 Reset transistor, 59 Amplification transistor, 60 Selection transistor, 100 Semiconductor substrate, 101 On-chip lens, 103 Light-shielding film, 104 P-type semiconductor region, 105 N-type semiconductor region, 106 Pixel separation section, 120 Wiring layer, 121 Local wiring, 122 Wiring, 123 Insulating layer, 124 Via, 130 Logic circuit board, 131 Wiring, 133 Insulating layer, 150 First semiconductor substrate, 160 Second semiconductor substrate, 161 Wiring, 162 Wiring, 163 Insulating layer, 201 Wiring capacitance, 202 Third conversion efficiency switching transistor, 301 P-type semiconductor region

Claims

1. Photoelectric conversion unit, A transfer transistor connected to the aforementioned photoelectric conversion unit, A floating diffusion connected to the transfer transistor, A first conversion efficiency switching transistor connected to the floating diffusion, A second conversion efficiency switching transistor connected to the first conversion efficiency switching transistor, A reset transistor connected to the second conversion efficiency switching transistor, It comprises a first storage unit and a second storage unit, The first storage unit is connected between the first conversion efficiency switching transistor and the second conversion efficiency switching transistor. The second storage unit is connected between the second conversion efficiency switching transistor and the reset transistor, The floating diffusion accumulates the charge that overflows from the photoelectric conversion unit. The photoelectric conversion unit is composed of a region of a first conductor and a region of a second conductor surrounding the region of the first conductor. The transfer transistor is connected to the first conductor, which is provided as an extension. Image sensor.

2. The charge overflowing from the photoelectric conversion unit is stored in the floating diffusion and the first storage unit. The image sensor according to claim 1.

3. The charge overflowing from the photoelectric conversion unit is stored in the floating diffusion, the first storage unit, and the second storage unit. The image sensor according to claim 1.

4. The capacities of the first storage unit and the second storage unit are, respectively, larger than the capacity of the floating diffusion. The image sensor according to claim 1.

5. The system further comprises an amplifying transistor connected to the floating diffusion and a selection transistor connected to the amplifying transistor. The image sensor according to claim 1.

6. At least one of the first storage unit and the second storage unit is a MIM (Metal-Insulator-Metal) capacitance element. The image sensor according to claim 1.

7. At least one of the first storage unit and the second storage unit is equipped with wiring capacity. The image sensor according to claim 1.

8. It also features through trenches to separate the pixels. The image sensor according to claim 1.

9. The photoelectric conversion unit is provided within the first semiconductor substrate, The first storage unit, the second storage unit, the first conversion efficiency switching transistor, and the second conversion efficiency switching transistor are provided within a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are stacked. The image sensor according to claim 1.

10. The second semiconductor substrate is provided with the first storage unit and the second storage unit. The image sensor according to claim 9.

11. A logic circuit board on which a logic circuit is formed is stacked on the second semiconductor substrate. The first storage unit and the second storage unit are provided within the logic circuit board. The image sensor according to claim 9.

12. By controlling the first and second conversion efficiency switching transistors, the charge from the photoelectric conversion unit is read out at high, medium, and low conversion efficiency levels, respectively. The image sensor according to claim 1.

13. In the junction between the high-conversion-efficiency signal and the medium-conversion-efficiency signal, and in the junction between the medium-conversion-efficiency signal and the low-conversion-efficiency signal, the two readout signals are blended and used. The image sensor according to claim 12.

14. Photoelectric conversion unit, A transfer transistor connected to the aforementioned photoelectric conversion unit, A floating diffusion connected to the transfer transistor, A first conversion efficiency switching transistor connected to the floating diffusion, A second conversion efficiency switching transistor connected to the first conversion efficiency switching transistor, A reset transistor connected to the second conversion efficiency switching transistor, It comprises a first storage unit and a second storage unit, The first storage unit is connected between the first conversion efficiency switching transistor and the second conversion efficiency switching transistor. The second storage unit is connected between the second conversion efficiency switching transistor and the reset transistor, The floating diffusion accumulates the charge that overflows from the photoelectric conversion unit. The photoelectric conversion unit is composed of a region of a first conductor and a region of a second conductor surrounding the region of the first conductor. The transfer transistor is connected to the first conductor, which is provided as an extension. Image sensor and A processing unit that processes signals from the image sensor and Electronic devices equipped with the following features.

Images