System and method for simulating quantum processors

Abstract

To propose a system for testing, developing and calibrating a quantum computing system and confirming a design object model without resort to the availability of a user-compatible quantum processor.SOLUTION: A digital processor carries out a QPU model including a representation-model set and a device-connectivity representation and simulates a quantum-processor design or physical quantum processor, thereby simulating a quantum computing system. The digital processor receives an analog waveform and generates a digital-waveform representation including a waveform-value set corresponding to a bias to be applied to a programmable device in the quantum processor. The digital processor selects a subset of waveform values based on a channel in the device-connectivity representation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] field This disclosure generally relates to systems and methods for simulating quantum processors. The disclosed systems and techniques can be applied to digital processors, or computing systems including digital processors and quantum processors. Digital processors can be operated to generate digital waveform representations based on analog waveforms and to compute responses based on sets of waveform values ​​and physical parameter values ​​via representation models. Furthermore, systems and methods for generating and verifying device connectivity representations are described. [Background technology]

[0002] background quantum computing A quantum computer is a system that uses at least one quantum mechanical phenomenon (e.g., superposition, tunneling, and entanglement) directly to perform operations on data. The elements of a quantum computer are qubits. Quantum computers can speed up certain types of computational problems (e.g., computational problems that simulate quantum physics).

[0003] Quantum annealing Quantum annealing is a computational method that can be used to find the low-energy states of a system, typically and preferably the ground state of the system. Conceptually similar to classical simulated annealing, this method relies on the fundamental principle that natural systems tend to move towards lower energy states because lower energy states are more stable. Quantum annealing may also use quantum effects (e.g., quantum tunneling) as sources of delocalization to reach the energy minimum more accurately and / or faster than classical annealing.

[0004] Adiabatic quantum computation may be considered a special case of quantum annealing. In adiabatic quantum computation, ideally, the system starts out and remains in the ground state of the system throughout the entire adiabatic evolution. Accordingly, those skilled in the art will appreciate that quantum annealing systems and methods may generally be implemented on an adiabatic quantum computer. Throughout this specification and the claims, any reference to quantum annealing is intended to include adiabatic quantum computation, unless the context requires otherwise.

[0005] Quantum annealing uses quantum mechanics as a source of disorder during the annealing process. An objective function (e.g., for an optimization problem) is encoded in a Hamiltonian H P and the algorithm introduces quantum effects by adding a disorder Hamiltonian H P that does not commute with H D An example is as follows. H E ∝A(t)H D +B(t)H P where A(t) and B(t) are time-dependent envelope functions. For example, A(t) may vary from a large value to substantially zero during evolution, and H E may be considered an evolution Hamiltonian. By removing H D that is, by decreasing A(t), disorder is slowly removed.

[0006] Accordingly, in quantum annealing, the system starts with an initial Hamiltonian and evolves through an evolution Hamiltonian to a final "problem" Hamiltonian H P whose ground state encodes the solution to the problem.

[0007] A general problem Hamiltonian includes a first component proportional to diagonal single-qubit terms and a second component proportional to diagonal multi-qubit terms, and may be of the following form: [Mathematical formula] where N is the number of qubits,

number

[0008] Here,

number

number

number

number

[0009] Throughout this specification, the terms “problem Hamiltonian” and “final Hamiltonian” are used interchangeably unless the context requires otherwise. Certain states of the quantum processor are energetically preferred, or simply preferred, by the problem Hamiltonian. These states include the ground state, but may also include excited states.

[0010] Hybrid computing systems including quantum processors A hybrid computing system may include a digital computer communicatively coupled to an analog computer. In some implementations, the analog computer is a quantum computer and the digital computer is a classical computer. The quantum computer may be a gate-model quantum computer or a quantum computer that performs adiabatic quantum computation. The digital computer may include a digital processor usable to perform the classical digital processing tasks described in the present systems and methods. The digital computer may include at least one system memory usable to store various sets of computer or processor-readable instructions, application programs and / or data.

[0011] A quantum computer may include a quantum processor having programmable elements (e.g., qubits, couplers, and other programmable devices). Qubits may be read out via a readout system, and the result thereof is transmitted to the digital computer. Qubits and couplers may be respectively characterized by qubit control systems and coupler control systems. In some implementations, quantum annealing may be performed on an analog computer using qubit control systems and coupler control systems.

[0012] The computing system may include a server that receives a problem Hamiltonian and compiles the problem Hamiltonian into commands transmitted to a digital processor or an analog processor. Including more than one server to reduce variation in problem solving throughput may be advantageous for the system.

[0013] The testing, development, verification, and calibration of quantum computing systems typically require quantum processors installed in cryogenic coolers. However, the installation of quantum processors can be time- and resource-intensive, limiting the number of user-required quantum processors. Furthermore, quantum processors are typically shared among many users. Some users may present large problems to computationally expensive quantum processors, which take a long time to solve and thus further reduce the availability of quantum processors. In some cases, if one user needs to develop a time-constrained experiment and other users are using quantum processors, the limited availability of quantum processors can be a problem. One approach to address this problem is to implement a quantum processor scheduler that allocates time to quantum processors based on priority. However, pausing or stopping an ongoing problem to run a different experiment instead can be impractical. Another approach is to increase the number of accessible quantum processors. However, the manufacturing and installation of quantum processors can be expensive and time-consuming. Furthermore, in some cases, the number of programmable parameters for each quantum processor device may be limited, which can make calibration processes and complete verification of algorithms difficult.

[0014] The limited availability of quantum processors can reduce the efficiency of processor design. Processor design methods may require design object models generated based on device connectivity representations. Device connectivity representations include representations of devices in the processor, the interconnections of devices extracted from device connectivity data, and the interconnections of devices to global bias lines.

[0015] The existence, various properties, biases, and connectivity of devices (e.g., qubits, couplers, and readout devices) can be programmatically extracted from the device connectivity representation. Typically, the device connectivity representation is manually generated from the design intent, and its accuracy is verified by testing the processor structure after manufacturing. However, such manual verification methods are time-consuming and highly error-prone. Furthermore, manual verification methods are expensive and require manufacturing processors that are not suitable for design verification.

[0016] Quantum processor calibration may include calibration rules used for dependency resolution and progress tracking. In some cases, the calibration rules require describing and verifying the relationships between programmable devices, device connectivity, and bias mechanisms. One approach is to generate a suitable representation of such data, which in turn involves independently devising data structures for each calibration rule. However, designing a suitable data structure for each calibration algorithm is time-consuming, especially if there is considerable overlap in the requirements of the set of calibration algorithms. Furthermore, designing a suitable continuation and version control mechanism for each calibration algorithm is time-consuming, inefficient, and prone to errors.

[0017] Therefore, there is a general need for systems and methods to test the foundations of quantum computing systems, develop experiments for characterization and calibration, and verify design object models associated with processor designs without relying on available user-enabled quantum processors.

[0018] The above examples of related technologies and limitations relating to related technologies are illustrative and not intended to be exclusive. Other limitations relating to related technologies will become apparent to those skilled in the art upon reading the specification and examining the drawings. [Overview of the Initiative] [Problems that the invention aims to solve]

[0019] overview A quantum computing system includes one or more quantum computers and / or digital computers, as well as the infrastructure that helps build and operate the quantum computing system. The quantum computing infrastructure may include servers, device connectivity, software APIs, etc. Typically, having an existing quantum processor is beneficial for testing the quantum computing system infrastructure (e.g., test server capacity, device connectivity validity, software connectivity, etc.). Similarly, having an existing quantum processor is beneficial for developing experiments for characterization and calibration purposes and for verifying the accuracy and robustness of calibration algorithms. Furthermore, it is worthwhile to test design ideas before designing and manufacturing actual processors.

[0020] A quantum computing system may be shared among users, including those who perform routine calibration and maintenance. Since only one user can access the quantum computing system at a time, developing time-constrained experiments or those requiring extensive research can be inefficient. Furthermore, developing and testing calibration processes for future quantum processor creation may be postponed until new processor chips are installed in the quantum computing system, potentially causing delays in operating the new quantum computer system.

[0021] Therefore, there is a need for systems and methods to test, develop, and calibrate quantum computing systems and to verify design object models without relying on the availability of user-responsive quantum processors.

[0022] A device object model representing the physical design of a device can be generated by reading a device connectivity representation. The existence, various characteristics, biases, and device connectivity in the processor can be programmatically extracted from the device connectivity representation. Existing methods for verifying design object models and / or device connectivity representations require the relevant processor to be manufactured, and the verification step is manual and consequently prone to errors. Therefore, a system and method are needed to generate a device connectivity representation and verify the design object model without requiring the manufacture of the relevant processor.

[0023] Processor calibration can include a set of calibration rules that require describing the relationships between programmable devices, device connectivity, and bias mechanisms for each calibration instance. Designing appropriate data structures for each calibration rule is time-consuming, especially if there is considerable overlap in the requirements of the calibration rules. Designing appropriate continuation and version control mechanisms separately for each calibration rule is time-consuming, inefficient, and prone to errors. Therefore, a data structure suitable for representing a processor across many calibration instances is needed. [Means for solving the problem]

[0024] Embodiment 1. A method of operation of at least one digital processor can be summarized as generating a digital waveform representation for a set of programmable devices of a quantum processor topology, the quantum processor topology including specifying a set of control lines that can bias at least one of the set of programmable devices; decomposing the digital waveform representation into a set of waveform values ​​based on a device connectivity representation including a set of channels; identifying a subset of the set of channels in the device connectivity representation; selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels; setting a plurality of physical parameter values ​​that characterize at least one of the set of programmable devices of the quantum processor topology; and computing a response via a representation model.

[0025] Embodiment 2. The method of Embodiment 1, wherein generating a digital waveform representation includes generating a digital waveform representation based on an analog waveform received from a server coupled to a quantum processor.

[0026] Embodiment 3. The method of Embodiment 1, wherein decomposing a digital waveform representation into a set of waveform values ​​comprises decomposing a digital waveform representation into a set of waveform values ​​based on a set of channels in a device connectivity representation, the set of channels representing many communicable couplings of a set of programmable devices to a set of control lines in a quantum processor topology.

[0027] Embodiment 4. The method of Embodiment 1, wherein identifying a subset of the set of channels in a device connectivity representation includes identifying a subset of the set of channels representing a subset of the set of programmable devices that are communicatively coupled to a subset of the set of control lines in a quantum processor topology.

[0028] Embodiment 5. The method of Embodiment 1, wherein selecting a subset of waveform values ​​corresponding to a subset of a set of channels includes selecting a subset of waveform values ​​each representing a bias applied to each qubit or coupler in a quantum processor topology.

[0029] Embodiment 6. The method of Embodiment 1, wherein setting a plurality of physical parameter values ​​characterizing at least one of a set of programmable devices in a quantum processor topology includes setting a plurality of physical parameter values ​​for at least one of the critical current, object inductance, and capacitance of a programmable device in a quantum processor topology.

[0030] Embodiment 7. The method of Embodiment 1, wherein the calculation of the response via a representation model includes calculating the response based on a subset of sets of multiple physical parameter values ​​and waveform values.

[0031] Embodiment 8. The method of Embodiment 1, wherein computing a response via a representation model includes computing a set of output values.

[0032] Embodiment 9. The method of Embodiment 1 may further include converting the response to a classical state.

[0033] Embodiment 10. The method of Embodiment 1 may further include returning a response to the user.

[0034] Embodiment 11. The method of Embodiment 1, wherein the method for embodying a quantum processor topology in at least one physical instance of a physical quantum processor and generating a digital waveform representation of the quantum processor topology for a set of programmable devices comprises generating a digital waveform representation for at least one physical instance of a physical quantum processor.

[0035] Embodiment 12. The method of Embodiment 1, wherein the embodiment of a quantum processor topology in at least one non-physical instance of a theoretical quantum processor and the generation of a digital waveform representation of the quantum processor topology for a set of programmable devices comprises generating a digital waveform representation for at least one non-physical instance of a theoretical quantum processor.

[0036] Embodiment 13. The system can be summarized to include at least one digital processor and at least one persistent computer-readable storage medium communicably coupled to the at least one digital processor, which stores processor-executable instructions that, when executing processor-executable instructions, cause the at least one digital processor to execute any of the methods in Embodiments 1 to 12.

[0037] Embodiment 14. The system of Embodiment 13 may further include at least one server operable to generate a waveform based on a received Hamiltonian characterizing or representing a problem, which is communicatively coupled to at least one digital processor and supplies the generated waveform to at least one digital processor, and is communicatively coupled to at least one quantum processor.

[0038] Embodiment 15. A method for simulating a quantum processor, the quantum processor comprising a set of programmable devices communically coupled to a set of control lines, each of which one of the set of control lines is operable to bias at least one of the set of programmable devices, and the method performed by the digital processor can be summarized to include generating a digital waveform representation, decomposing the digital waveform representation into a set of waveform values ​​based on a device connectivity representation comprising a set of channels, identifying a subset of the set of channels in the device connectivity representation, selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels, setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices of the quantum processor, and computing a response through a representation model.

[0039] Embodiment 16. The method of Embodiment 15, wherein generating a digital waveform representation includes generating a digital waveform representation based on an analog waveform received from a server coupled to a quantum processor.

[0040] Embodiment 17. Decomposing a digital waveform representation into a set of waveform values ​​comprises decomposing a digital waveform representation into a set of waveform values ​​based on a set of channels in a device connectivity representation, wherein the set of channels represents many communicable couplings of a set of programmable devices to a set of control lines in a quantum processor, according to the method of Embodiment 15.

[0041] Embodiment 18. The method of Embodiment 15, wherein identifying a subset of the set of channels in a device connectivity representation includes identifying a subset of the set of channels representing a subset of the set of programmable devices that are communicatively coupled to a subset of the set of control lines in a quantum processor.

[0042] Embodiment 19. The method of Embodiment 15, wherein selecting a subset of waveform values ​​corresponding to a subset of a set of channels includes selecting a subset of waveform values ​​that each represent a bias applied to each programmable device in the quantum processor.

[0043] Embodiment 20. The method of Embodiment 19, wherein selecting a subset of sets of waveform values ​​representing the bias applied to each programmable device in a quantum processor includes selecting a subset of sets of waveform values ​​representing the bias applied to each qubit in a quantum processor.

[0044] Embodiment 21. The method of Embodiment 19, wherein selecting a subset of sets of waveform values ​​representing the bias applied to each programmable device in a quantum processor includes selecting a subset of sets of waveform values ​​representing the bias applied to each coupler in a quantum processor.

[0045] Embodiment 22. The method of Embodiment 15, wherein setting a plurality of physical parameter values ​​characterizing at least one of a set of programmable devices in a quantum processor includes setting a plurality of physical parameter values ​​for at least one of the critical current, object inductance, and capacitance of a programmable device in a quantum processor.

[0046] Embodiment 23. The method of Embodiment 15, wherein the calculation of the response via a representation model includes calculating the response based on a subset of a set of multiple physical parameter values ​​and waveform values.

[0047] Embodiment 24. The method of Embodiment 15, wherein computing the response via a representation model includes computing a set of output values.

[0048] Embodiment 25. The method of Embodiment 15 may further include converting the response to a classical state.

[0049] Embodiment 26. The method of Embodiment 150 may further include returning a response to the user.

[0050] Embodiment 27. A system for simulating a quantum processor, the quantum processor comprising a set of programmable devices communicatively coupled to a set of control lines, each of which one of the control lines is operable to bias one of the set of programmable devices. The system can be summarized to include a digital processor and a persistent computer-readable storage medium storing processor-executable instructions that cause the digital processor to perform any of the methods in Embodiments 15 to 26 when executing processor-executable instructions.

[0051] Embodiment 28. A method for extracting a device object model from an integrated circuit layout, which is performed by a digital processor, can be summarized to include, autonomously by the digital processor, extracting a device schematic from a design schematic, extracting device connectivity data from the device schematic, writing the device connectivity data to a device connectivity representation, extracting a set of biases from the device connectivity data, and writing the set of biases to a device connectivity representation.

[0052] Embodiment 29. The method of Embodiment 28, wherein extracting a device schematic from a design schematic includes extracting a device schematic from a design schematic that can be verified by a layout versus schematic tool.

[0053] Embodiment 30. The method of Embodiment 28, wherein extracting a device schematic from a design schematic includes extracting a device schematic corresponding to a directed acyclic graph.

[0054] Embodiment 31. The method of Embodiment 30, wherein extracting a device schematic diagram corresponding to a directed acyclic graph includes extracting a device schematic diagram that includes at least one atomic device node corresponding to a directed acyclic graph.

[0055] Embodiment 32. The method of Embodiment 28, wherein extracting device connectivity data includes extracting at least one of a device designation, a characteristic annotation, and at least one adjacent device connection.

[0056] Embodiment 33. The method of Embodiment 28, wherein extracting a set of biases from device connectivity data includes extracting a set of global biases.

[0057] Embodiment 34. The method of Embodiment 33, wherein extracting a set of global biases includes extracting a set of connections that electrically couple pads to at least one programmable device.

[0058] Embodiment 35. The method of Embodiment 28 may further include performing a device connectivity representation to compute a device object model.

[0059] Embodiment 36. The computing system can be summarized to include at least one digital processor and at least one persistent processor-readable storage medium communicably coupled to the at least one digital processor, which stores at least one processor-executable instruction that causes the at least one digital processor to execute any of the methods in Embodiments 28 to 35 when the at least one digital processor executes a processor-executable instruction.

[0060] Embodiment 37. A method for verifying the design of an analog processor including a set of programmable devices, the method being performed by a digital processor, which autonomously loads a device connectivity representation based on at least a part of the design implementation form, the device connectivity representation including a set of characteristics characterizing at least one programmable device, identifying a set of n rules, iteratively selecting an i-th rule (where 1 ≤ i ≤ n) from the set of rules until the device connectivity representation passes the n-th rule, and determining whether the device connectivity representation has passed or failed the i-th rule.

[0061] Embodiment 38. The method of Embodiment 37 may further include, in response to a determination that the device connectivity representation has failed to meet the i-th rule, iteratively identifying at least one characteristic from the set of characteristics that have failed to meet the i-th rule, identifying a portion of the design implementation configuration corresponding to the at least one characteristic that has failed to meet the i-th rule, and adjusting the design implementation configuration until the device connectivity representation meets the i-th rule.

[0062] Embodiment 39. The method of Embodiment 37, wherein identifying a set of rules includes identifying a set of rules for inspecting many programmable devices.

[0063] Embodiment 40. The method of Embodiment 37, wherein identifying a set of rules includes identifying a set of rules for inspecting many control devices.

[0064] Embodiment 41. The method of Embodiment 37, wherein identifying a set of rules includes identifying a set of rules that examine a set of device connectivity data characteristics.

[0065] Embodiment 42. The method of Embodiment 37, wherein identifying a set of rules includes identifying a set of rules for examining a set of addressing line characteristics.

[0066] Embodiment 43. The computing system can be summarized to include at least one digital processor and at least one persistent processor-readable storage medium communicably coupled to the at least one digital processor, which stores at least one processor-executable instruction that causes the at least one digital processor to execute any of the methods in Embodiments 37 to 42 when the at least one digital processor executes a processor-executable instruction.

[0067] A brief explanation of some of the figures in the drawing. In drawings, the same reference numerals identify similar elements or actions. The size and relative position of elements in drawings are not necessarily proportional to the actual size. For example, the shapes and angles of various elements are not necessarily proportional to the actual size, and some of these elements may be arbitrarily enlarged and positioned to improve the visibility of the drawing. Furthermore, the specific shapes of the illustrated elements are not necessarily intended to convey any information about the actual shape of the particular element, and may simply be selected for ease of recognition in the drawing. [Brief explanation of the drawing]

[0068] [Figure 1] This is a schematic diagram of an example of a computing system according to the present system and method, which includes a digital processor communicating with a storage medium that stores instructions associated with a quantum processor and a quantum processing unit (QPU) model. [Figure 2] This flowchart illustrates a method for simulating a quantum processor using this system and method. [Figure 3] This is a schematic diagram of an exemplary computing system, including a digital computer and an analog computer, based on this system and method. [Figure 4] This is a flowchart illustrating an example of a method for generating a device connectivity representation using a processor, based on this system and method. [Figure 5]This is a flowchart illustrating an example of how the system and method allow a processor to verify a device object model based on a device connectivity representation. [Figure 6] This is a schematic diagram illustrating an example of a system for extracting and verifying design object models using this system and method. [Figure 7] This is a schematic diagram showing an example of a data structure 700 that can be operated to represent a processor in operation. [Modes for carrying out the invention]

[0069] Detailed explanation In the following description, certain details are given to give a complete understanding of the various implementations of the disclosure. However, those skilled in the art will see that the implementations can be carried out without one or more of these specific details, or using other methods, components, materials, etc. In other cases, well-known structures associated with computer systems, server computers, and / or communication networks are not shown or described in detail in order to avoid unnecessarily ambiguous descriptions of the implementations.

[0070] Unless the context requires otherwise, throughout the following specification and claims, the term “comprising” is synonymous with, inclusive of, or unrestrictive of, “including” (i.e., does not exclude additional non-enumerated elements or method operations).

[0071] Throughout this specification, any reference to “one implementation” or “an implementation” means that the specific features, structures, or characteristics described in relation to an implementation are included in at least one implementation. Therefore, the phrases “in one implementation” or “in an implementation” in various places throughout this specification do not necessarily all refer to the same implementation. Furthermore, specific features, structures, or characteristics may be combined in any appropriate manner in one or more implementations.

[0072] As used in this specification and the attached claims, the singular forms “a,” “an,” and “the” refer to multiple objects unless otherwise explicitly stated in the context. It should also be noted that the term “or” is generally used to mean “and / or” unless otherwise explicitly stated in the context.

[0073] The headings and summaries provided herein are for convenience only and do not imply any interpretation of the scope or meaning of the implementation.

[0074] The term “representation model” is used in this specification and the attached claims to include, for example, numerical or analytical methods, mathematical models, and physical simulations.

[0075] The term "output value" is used in this specification and the attached claims to include, for example, eigenvalues ​​and eigenvectors output from lookup tables, mathematical models, waveforms, etc.

[0076] The term “device connectivity representation” is used in this specification and the attached claims to include, for example, device connectivity files, databases, graphs, etc.

[0077] Typically, quantum processors can only be accessed by one user at a time, which can make developing time-constrained experiments or experiments requiring extensive research where many users need the quantum processor relatively inefficient for users. One approach to address this problem is to use a digital processor that implements a quantum processing unit (QPU) model to represent quantum processors for time-constrained or research-intensive experiments.

[0078] QPU models that simulate existing physical quantum processors A QPU model includes a set of representation models executable by a digital computer. In some cases, a QPU model can be considered a software foundation that is a digital representation of a physical quantum processor. For example, a QPU model can be a digital representation of a physical quantum processor installed in a cryostat, and the QPU model can be used to develop test and calibration algorithms for the physical quantum processor while the physical quantum processor is unavailable. When the physical quantum processor becomes available, the test and calibration algorithms developed via the QPU model can be executed on the physical quantum processor.

[0079] A physical quantum processor includes programmable devices (e.g., qubits and couplers) in the form of superconducting quantum interference devices (SQUIDs). A QPU model may include a set of representation models (e.g., device models) that characterize the response from each device or combination of devices in the physical quantum processor. Each representation model can digitally represent each device in the physical quantum processor. For example, a first representation model can represent a qubit in the physical quantum processor, and a second representation model can represent a coupler in the physical quantum processor. Representation models can digitally represent qubits, including composite Josephson junctions (JJs). An example of a qubit in the form of a JJ SQUID is described in U.S. Patent No. 9,152,923.

[0080] QPU model for simulating quantum processor design In some cases, a QPU model can be considered a software foundation that is a digital representation of a theoretical quantum processor (i.e., a quantum processor design that has not yet been manufactured as a physical quantum processor). Because QPU models can circumvent some of the challenges associated with conventional methods of calibrating and testing physical quantum processors, QPU models implemented on digital processors can be useful for simulating quantum processor designs.

[0081] Conventional calibration techniques require the quantum processor to be manufactured. Due to manufacturing defects, variations in the programmable devices of a physical quantum processor (e.g., qubits, couplers, etc.) can exist, leading to poor results when performing computations. A typical approach to address this is to tune a set of physical parameters to homogenize the programmable devices at least partially across physical quantum processors. Examples of such physical parameters include (but are not limited to) physical inductance, capacitance, and critical current. However, tuning these physical parameters in a physical quantum processor can be difficult. For example, biasing a qubit while controlling critical current and inductance can be direct but challenging. In such cases where controlling physical parameters is difficult, values ​​for these physical parameters are obtained from the response of the quantum processor. However, having these values ​​as outputs rather than controllable inputs can significantly limit the capabilities of the quantum processor, because control of these physical parameters is essential for the proper operation of the quantum processor.

[0082] Therefore, the aforementioned limitations on physical quantum processors can be advantageous for the calibration and design of digital representations of quantum processors (e.g., QPU models).

[0083] In the context of calibration, a digital processor running a QPU model can be used to simulate an existing physical quantum processor so that a calibration algorithm can be executed. For example, a digital processor can simulate a quantum processor that is unavailable due to use by a high-priority experiment. Instead of interrupting an experiment running on a physical quantum processor, a digital processor running a QPU model can be used to test the computing infrastructure (e.g., server capacity, device connectivity verification, solution connectivity, etc.) and develop a calibration algorithm.

[0084] From a design perspective, using a digital processor to implement a QPU model to design a theoretical processor can be more flexible than using a physical quantum processor. This is because the user can input values ​​for physical parameters into the device model included in the QPU model implemented on the digital processor. However, tuning these physical parameters on a physical quantum processor is difficult. A digital processor implementing a QPU model allows the user to model a quantum processor design and then manufacture and test a physical quantum processor without expending resources. Furthermore, the ability to tune physical parameters in a QPU model can be useful in developing calibration algorithms for future quantum processor designs before manufacturing them. For example, using a digital processor implementing a QPU model, an algorithm can be developed to characterize how device response is affected by changing physical parameters. Once the relationships are better understood, learning can be applied to optimize the quantum processor design, for example, by determining specifications and device characteristics.

[0085] This system and method describes a digital processor that implements a QPU model simulating a quantum processor. The digital processor is coupled to a server capable of operating to serve the digital processor or quantum processor. The digital processor is capable of receiving analog waveforms executable by the quantum processor. The digital processor is capable of generating a digital representation of the waveform (here called the "waveform representation") upon receiving the waveform. The waveform representation can be decomposed by the digital processor into a set of waveform values. Each waveform value represents a bias applied to a programmable device in the quantum processor. The waveform values ​​can be in the form of numerical values ​​readable by the digital processor. Decomposing the waveform representation into waveform values ​​can be based on a device connectivity representation implemented by the digital processor.

[0086] A device connectivity representation can be a strictly accurate representation of a quantum processor (e.g., an existing physical quantum processor or quantum processor design) and may include data characterizing the response of programmable devices in the quantum processor. A device connectivity representation may include data describing programmable device specifications and connections (also called "channels") between programmable devices. For example, a device connectivity representation may include channels describing control lines that bias a composite Josephson junction (CJJ) of a particular qubit.

[0087] A digital processor can implement a QPU model that decomposes a waveform representation into waveform values ​​based on a device connectivity representation. In one implementation, this may include determining many channels in the device connectivity representation for a particular programmable device, selecting a set of waveform values ​​corresponding to the bias applied to the programmable device, and sending the set of waveform values ​​to a representation model.

[0088] The digital processor can be configured to set many physical parameter values ​​to be implemented in the representation model. Based on the physical parameter values ​​and waveform values, the digital processor can implement a representation model that computes a set of output values ​​that characterize the response. In some cases, values ​​for annealing parameters, including persistent current and tunneling energy, can be obtained from the set of output values.

[0089] A physical instance of a quantum processor or design for a physical or even theoretical quantum processor has an associated topology (e.g., qubits, coupler collection and arrangement, programming or bias interface, control lines, and / or readout (e.g., SQUIDS)) that essentially defines the quantum processor and defines the operation of the quantum processor based on applied values ​​(e.g., bias). The quantum processor topology specifies, for example, a set of control lines that can bias at least one device of a set of programmable devices.

[0090] Figure 1 is a schematic diagram of an example computing system 100 that includes a digital processor 102 implementing a QPU model 104 that simulates a quantum processor 106. The digital processor 102 communicates with a persistent computer-readable storage medium (not shown in Figure 1, see Figure 3). The system 100 includes a server 108 that can operate to serve the digital processor 102 and the quantum processor 106. The server 108 is communicatively coupled to both the digital processor 102 and the quantum processor 106. The server 108 is coupled to the quantum processor 106 via a set of input / output (I / O) electronics 110 (e.g., signal conductors, filters, switches, etc.) that can operate to transfer analog waveforms 112 to the quantum processor 106.

[0091] Server 108 may be a hardware-based or software-based server running on a processor-based device. Server 108 can receive a Hamiltonian characterizing or representing a problem (e.g., a problem presented by a user) and is operable to generate a waveform 112 based on the Hamiltonian. The waveform 112 is executable by the quantum processor 106 and receivable by the digital processor 102.

[0092] In some cases, if the quantum processor 106 is unavailable, the waveform 112 is sent to the digital processor 102. For example, if the quantum processor 106 is unavailable for another user, the waveform 112 is sent to the digital processor 102, which is communicating with a persistent processor-readable storage medium (e.g., a memory circuit, magnetic medium, or optical medium) that stores processor-executable instructions associated with the QPU model 104.

[0093] In other cases, if the user is interested in simulating a theoretical quantum processor or quantum processor design, the waveform 112 is sent to the digital processor 102. For example, if the user is designing a theoretical quantum processor, it is desirable to tune the physical parameter values ​​114 of the theoretical quantum processor device, present the problem to the server 108, and observe the response of the QPU model 104 to optimize the theoretical quantum processor. In such a case, the quantum processor 106 of system 100 is the theoretical quantum processor or quantum processor design. Before manufacturing the physical quantum processor, the cycles can be designed by applying what has been learned from simulating the theoretical quantum processor with the tuned physical parameter values ​​114.

[0094] If the problem is to be solved by the quantum processor 106, the waveform 112 follows the order illustrated by the dashed arrows in Figure 1. If the problem is to be solved by the digital processor 102, the waveform 112 follows the order illustrated by the solid arrows in Figure 1. The order illustrated by the solid arrows will be explained shortly.

[0095] Waveform 112 is executable by the quantum processor 106 and receivable by the digital processor 102. The digital processor 102 communicates with at least one persistent storage medium that stores processor-executable instructions for implementing the QPU model 104. During operation, upon receiving waveform 112, the digital processor 102 generates a digital waveform representation 116 that characterizes or represents a set of programmable devices 118 of the quantum processor 106. The digital processor 102 decomposes the digital waveform representation 116 into a set of waveform values ​​120a, 120b, and 120c (collectively and individually). For simplicity of explanation, only three waveform values ​​120 are shown in Figure 1. However, those skilled in the art will see that the digital waveform representation 116 can be decomposed into fewer than three or more than three waveform values ​​120. The waveform values ​​120 can be a set of numbers representing the biases applied to the programmable devices 118 of the quantum processor 106.

[0096] The digital processor 102 is operable to identify the programmable device 118 to be simulated and to implement a device connectivity representation 122. The device connectivity representation 122 includes many channels 124a, 124b, 124c (collectively referred to as 124), each channel representing a biasing control line or a communicable coupling of the programmable device 118 to another programmable device 118. For simplicity of explanation, only three channels 124 are shown in Figure 1. However, those skilled in the art will see that the device connectivity representation 122 may contain fewer than three or more channels 124. Furthermore, the device connectivity representation 122 includes data characterizing or representing the device designation, device connectivity, and the bias applied to the programmable device 118 in the quantum processor 106. In some implementations, the quantum processor 106 is a quantum processor design (i.e., a theoretical quantum processor). The digital processor 102 is operable to identify a subset of channel 124 in the device connectivity representation 122 that controls the simulated programmable device, and is operable to select a corresponding subset of waveform values ​​120 and transmit them to the representation model 126.

[0097] Each waveform value 120 corresponds to one of a set of biases 128 (128a, 128b, and 128c, respectively) applied to the programmable device 118 of the quantum processor 106. For simplicity, only three biases 128 are shown in Figure 1. However, those skilled in the art will see that fewer than three or more than three biases 128 can be applied to the programmable device 118. In one implementation, the waveform value 120a can correspond to the bias 128a applied to the qubit, and h in the system Hamiltonian i It can correspond to the term. In one implementation, the waveform value 120b can correspond to the bias 128b applied to the coupler that sets the coupling strength, and the J in the system Hamiltonian. ij This can correspond to a term (i.e., the coupling strength of a coupler in a quantum processor).

[0098] When executing instructions associated with the QPU model 104, the digital processor 102 sets several physical parameter values ​​114. These physical parameter values ​​114 include macroscopic (i.e., directly measurable) parameter values ​​that characterize the behavior of the programmable device 118. In some cases, the physical parameter values ​​114 can be tuned to at least partially homogenize the programmable device 118 across the quantum processor 106. The physical parameter values ​​114 may include values ​​for critical current, inductance, capacitance, or a combination thereof. In one implementation, the physical parameter is the critical current transmitted by the Josephson junction of the programmable device. In one implementation, the physical parameter value is the capacitance across the Josephson junction of the programmable device. In one implementation, the physical parameter value is the inductance in the object loop of the programmable device. At least some of the physical parameter values ​​114 are obtained from the design of the quantum processor 106 and the programmable device 118. In some implementations, if the quantum processor 106 is a theoretical quantum processor, at least some of the physical parameter values ​​114 are defined by an external user.

[0099] The digital processor 102 uses a representation model 126 to compute a response in the form of a set of output values ​​130 based on physical parameter values ​​114 and waveform values ​​120. In some implementations, the representation model 126 characterizes or represents each response of individual programmable devices 118. In some implementations, the representation model 126 characterizes the responses of many programmable devices 118. Annealing parameters of programmable devices can be obtained from the output values ​​130. The annealing parameters can provide information about the energy measure of the quantum processor 106. For example, annealing parameters such as tunneling energy and persistent current of a qubit can be obtained from the output values ​​130. In some cases, the quantum processor 106 is a theoretical quantum processor or quantum processor design. In some implementations, the digital processor 102 converts the output values ​​130 into classical states (e.g., +1 or -1 states) and returns the classical states to the user via the digital processor 102.

[0100] In an example application of the operating system 100, the user sends a request to the server 108 to simulate biasing a programmable device 118 named "qubit A" in a quantum processor 106 for calibration experiments. The server 108 generates a waveform 112 and sends it to the digital processor 102. Upon receiving the waveform 112, the digital processor 102 generates a digital waveform representation 116 that characterizes or represents all the programmable devices 118 of the quantum processor 106 (e.g., "qubit A", "qubit B", etc.). The digital processor 102 decomposes the digital waveform representation 116 into a set of waveform values ​​120 that represent the bias applied to all the programmable devices 118 of the quantum processor 106. The device connectivity representation 122 includes a first channel 124a "qubit-cjj-A" representing the bias applied to the CJJ of "qubit A", a second channel 124b "qubit-fb-A" representing the bias applied to the object loop of "qubit A", and a third channel 124c "qubit-cjj-B" representing the bias applied to the CJJ of "qubit B" (note that implementations can typically use a substantially larger number of channels 124, but for simplicity of explanation, we will select only three channels here). To simulate "qubit A", the digital processor 102 identifies a subset of channels (e.g., channel "qubit-cjj-A" 124a and channel "qubit-fb-A" 124b) that represent lines communicatively coupled to "qubit A" in the device connectivity representation 122. The digital processor selects corresponding subsets of waveform values ​​120a and 120b from waveform value 120, representing instructions to bias channels "qubit-cjj-A" and "qubit-fb-A". The digital processor 102 uses the representation model 126 to calculate the response based on the waveform values ​​120a, 120b and the physical parameter values ​​114.

[0101] In some cases, the server 108 may transmit a waveform 112 to be executed by the quantum processor 106. If the problem is to be solved by the quantum processor 106, the waveform 112 can be operated in the order illustrated by the dashed arrows in Figure 1.

[0102] In the example of the implementation configuration illustrated by the dashed arrows, waveform 112 is executable by the quantum processor 106. The quantum processor 106 is operable to receive waveform 112 via the I / O electronics 110. The quantum processor 106 is operable to execute waveform 112 and may include applying a bias 128 to the programmable device 118. The bias 128 can be applied to the programmable device 118 via control lines 132. The control lines 132 are communicatively coupled to the programmable device 118. For example, the h of the system Hamiltonian i A bias can be applied to the qubits through control lines inductively coupled to the qubits that realize the term. In another example, the J of the system Hamiltonian ij A bias can be applied to the coupler via an inductive coupling control line that realizes the term.

[0103] The quantum processor 106 is operable to compute a response in the form of an output value 130. Annealing parameters, which provide information about the quantum annealing process and energy measures (e.g., transverse energy A(s) and the energy added to the problem Hamiltonian B(s)), can be obtained from the output value 130. Examples of annealing parameters may include the persistent current, tunneling energy, and other parameters of the programmable device 118. In some implementations, the quantum processor 106 is not operable to set physical parameter values ​​114 and therefore obtains physical parameter values. Physical parameter values ​​114 can be obtained from the output value 130. Examples of physical parameters may include the critical current, inductance, and capacitance. In some cases, the output value 130 computed by the QPU model 104 is within the range of magnitude of the output value 130 computed by the quantum processor 106, or is equal to the output value 130 computed by the quantum processor 106.

[0104] Figure 2 is a flowchart illustrating method 200 for simulating a quantum processor using the present system and method. Method 200 includes operations 202-216, although in other implementations certain operations may be omitted and / or additional operations may be added. Method 200 can be executed in response to instructions or problems presented by a user by a computing system including one or more digital processors, one or more persistent computer-readable storage media (hereinafter also called persistent processor-readable storage media), and optionally a physical analog processor.

[0105] Method 200 starts at 202, for example, in response to a call from another routine.

[0106] In step 204, a digital waveform representation is generated. Generating a digital waveform representation may include generating a digital waveform representation based on analog waveforms received from a server coupled to both the digital processor and the quantum processor. In one implementation, the digital waveform representation characterizes or represents a set of programmable devices in the quantum processor. In one implementation, the digital waveform representation characterizes or represents all programmable devices in a theoretical quantum processor (e.g., a quantum processor design).

[0107] In 206, the digital waveform representation is decomposed into a set of waveform values. The digital waveform representation can be decomposed into a set of waveform values ​​based on a device connectivity representation that includes many channels. The device connectivity representation may include data characterizing the device designation, device connectivity, and the bias applied to the programmable device in the quantum processor. In one implementation, decomposing the digital waveform representation into a set of waveform values ​​may include decomposing the digital waveform representation into a set of waveform values ​​based on many channels representing the communicable coupling of the programmable device to the control lines that bias the quantum processor.

[0108] Section 208 identifies a subset of channels in the device connectivity representation. Identifying a subset of channels in the device connectivity representation may include identifying a subset of channels that control a subset of programmable devices in a quantum processor. In one implementation, identifying a subset of channels in the device connectivity representation includes identifying a subset of channels that control a subset of programmable devices in a theoretical quantum processor (i.e., a quantum processor design).

[0109] In step 210, a subset of waveform values ​​corresponding to a subset of channels is selected from a set of waveform values. Selecting a subset of waveform values ​​corresponding to a subset of channels may include selecting a subset of waveform values ​​that each represents the bias applied to each programmable device in the quantum processor. The waveform values ​​are the h of the system Hamiltonian. i The bias applied to each qubit that realizes a term, or the J of the system Hamiltonian. ij This can be a set of many or a number of sets corresponding to each bias applied to the coupler that realizes a term (i.e., coupling strength). In one implementation, selecting a subset of waveform values ​​corresponding to a subset of channels includes selecting a subset of waveform values ​​each representing a bias applied to a qubit in a quantum processor. In one implementation, selecting a subset of waveform values ​​corresponding to a subset of channels includes selecting a subset of waveform values ​​each representing a bias applied to a programmable device in a theoretical quantum processor (i.e., a quantum processor design).

[0110] In 212, many physical parameter values ​​are set. These physical parameters include macroscopic (i.e., directly measurable) parameters that characterize the behavior of the programmable device. Setting physical parameter values ​​can at least partially homogenize the programmable device across the quantum processor. Examples of physical parameters may include the critical current transmitted by the JJ of the programmable device, the inductance of the object loop of the programmable device, the capacitance across the JJ of the programmable device, or a combination thereof. In one implementation, setting many physical parameter values ​​may include setting values ​​for critical current, inductance, capacitance, or a combination thereof.

[0111] In 214, the response is calculated. Calculating the response may involve implementing a representation model that calculates a set of output values ​​based on the number of physical parameter values ​​set in 212 and a subset of waveform values ​​selected in 210. The representation model characterizes the response of a programmable device, or the interaction between many programmable devices in a quantum processor. In some implementations, calculating the response may involve calculating a set of output values ​​that characterize the response of a set of programmable devices in a quantum processor. In some implementations, calculating the response may involve calculating a set of output values ​​that characterize the response of a set of programmable devices in a theoretical quantum processor (i.e., a quantum processor design). In some implementations, calculating the response may further involve converting the set of output values ​​into a classical state and returning the classical state to the user.

[0112] In step 216, method 200 terminates until it is called again, for example.

[0113] Figure 3 illustrates a computing system 300 including a digital computer 302. An example of the digital computer 302 includes one or more digital processors 304 that can be used to perform classic digital processing tasks. The digital computer 302 may further include at least one system memory 306 and at least one system bus 308 that connects various system components, including the system memory 306, to the digital processors 304. The system memory 306 may store a QPU model instruction module 310 and other instructions. Other instructions may include methods for extracting device object models and verifying processor designs. The system memory 306 may also store processor-executable instructions that cause one or more processors to perform methods for collecting and modifying devices, for aggregating and retrieving data from object device models, and for continuously managing aggregated data. The system memory 306 can store methods applicable to multiple algorithms (e.g., calibration algorithms), each of which is applicable.

[0114] The system memory 306 can store data structures representing a processor in operation. A processor in operation may include a processor being calibrated or tested. The data structures can be applied to multiple calibration algorithms. The data structures may include representations of sets of devices, connectivity between each set of devices, unique characteristics of each device, and bias information for each device. The system memory 306 can store data structures and interfaces for loading predefined sets for each device (e.g., device connectivity representation 614 in Figure 6).

[0115] The digital processor 304 may be any logic processing unit or circuit (e.g., an integrated circuit) such as one or more central processing units ("CPU"), graphics processing units ("GPU"), digital signal processors ("DSP"), application-specific integrated circuits ("ASIC"), programmable gate arrays ("FPGA"), programmable logic controllers ("PLC"), and / or any combination thereof.

[0116] In some implementations, the computing system 300 includes an analog computer 312 which may include one or more quantum processors 314. The digital computer 302 may communicate with the analog computer 312, for example, via a controller 316. As described in more detail here, the analog computer 312 may perform specific calculations at the instruction of the digital computer 302.

[0117] The digital computer 302 may include a user input / output subsystem 318. In some implementations, the user input / output subsystem includes one or more user input / output components (e.g., a display 320, a mouse 322, and / or a keyboard 324).

[0118] The system bus 308 can use any known bus structure or architecture, including a memory bus, peripheral bus, and local bus, each having a memory controller. The system memory 306 may include non-volatile memory (e.g., read-only memory ("ROM"), static random-access memory ("SRAM"), flash NAND), and volatile memory (e.g., random-access memory (RAM) (not shown)), and may include a persistent computer or processor-readable storage medium.

[0119] Furthermore, the digital computer 302 may include other persistent computer or processor-readable storage media, or non-volatile memory 326. The non-volatile memory 326 may take various forms, including a hard disk drive for reading and writing hard disks (e.g., magnetic disks), an optical disk drive for reading and writing removable optical disks, and / or a solid-state drive (SSD) for reading and writing solid-state media (e.g., NAND-based flash memory). The optical disk may be a CD-ROM or DVD, while the magnetic disk may be a hard rotating magnetic disk, or a magnetic floppy disk or diskette. The non-volatile memory 326 may communicate with the digital processor via the system bus 308 and may include a suitable interface or controller 316 coupled to the system bus 308. The non-volatile memory 326 may function as long-term storage for processor- or computer-readable instructions, data structures, or other data for the digital computer 302 (also known as program modules).

[0120] Although the digital computer 302 is described to use hard disks, optical disks and / or solid-state storage media, it will be apparent to those skilled in the art that other types of persistent and non-volatile computer-readable media (e.g., magnetic cassettes, flash memory cards, flash memory, ROM, smart cards, etc.) may be used. It will be apparent to those skilled in the art that some computer architectures use persistent volatile memory and persistent non-volatile memory. For example, data in volatile memory can be cached in non-volatile memory. Alternatively, a solid-state disk may use an integrated circuit to provide non-volatile memory.

[0121] Various processor or computer-readable instructions, data structures, or other data can be stored in the system memory 306. For example, the system memory 306 may store instructions for communicating with a remote client and scheduling the use of resources, including resources on the digital computer 302 and the analog computer 312. Furthermore, for example, the system memory 306 may store at least one of various algorithms that cause at least one processor to execute instructions for performing the quantum processor simulation method described herein, when at least one processor executes the processor-executable instructions or data. For example, the system memory 306 may store a quantum processor simulation instruction module 310 that includes processor or computer-readable instructions for generating a digital waveform representation, selecting waveform values ​​corresponding to channels in a device connectivity representation, and / or calculating a response. Such provisions may include, for example, decomposing the waveform representation into a set of waveform values ​​and calculating a set of output values, as described in more detail herein.

[0122] In some implementations, the system memory 306 may store processor or computer-readable computation instructions and / or data for performing pre-processing, interaction, and post-processing for the analog computer 312. The system memory 306 may also store a set of analog computer interface instructions for interacting with the analog computer 312. The analog computer 312 may include at least one analog processor (e.g., a quantum processor 314). The analog computer 312 can be provided in an isolated environment, for example, an isolated environment that shields the internal elements of the quantum computer from heat, magnetic fields, and other external noise (not shown). The isolated environment may include, for example, a cooler (e.g., a dilution cooler) capable of cooling the analog processor to a low temperature of less than about 1°K (Kelvin).

[0123] The analog computer 312 may include programmable elements (e.g., qubits, couplers, and other programmable devices). Qubits can be read out via the readout system 328. The readout results can be received by other computer or processor-readable instructions of the digital computer 302. Qubits can be controlled via the qubit control system 330. The qubit control system 330 may include an on-chip digital-to-analog converter (DAC) and analog lines that can be operated to bias the target device. Couplers that couple qubits can be controlled via the coupler control system 332. The coupler control system 332 may include tuning elements (e.g., an on-chip DAC and analog lines).

[0124] A design object model is a data representation of a system (e.g., a computing system) that clearly indicates the design intent of the system and may include a description of the input / output ports of a device in a processor (e.g., a quantum processor). A device object model representing the physical design of a device can be generated by reading a device connectivity representation. Existence, various characteristics, biases, and device connectivity in a processor can be programmatically extracted from the device connectivity representation. Existing methods for verifying design object models and / or device connectivity representations require the relevant processor to be manufactured, and the verification step is manual and consequently prone to errors. Figures 4, 5, and 6 illustrate a system and method for generating a device connectivity representation and verifying a design object model without requiring the manufacture of the relevant processor.

[0125] Figure 4 is a flowchart of an example of method 400, which generates a device connectivity representation in a processor according to the present system and method. In some implementations, the device connectivity representation generated by method 400 can be implemented using the device connectivity representation 122 in Figure 1 or method 200 in Figure 2. In some implementations, method 400 may be followed by method 500 in Figure 5. Method 400 includes operations 402-420, although certain operations may be omitted and / or additional operations may be added in other implementations. Method 400 can be executed by a processor (e.g., digital processor 304 in Figure 3).

[0126] Method 400 starts at 402, for example, in response to a call from another routine.

[0127] In step 404, a conceptual design is generated. The conceptual design can be an expression of the user's intent regarding the processor design. The conceptual design may include a simulation of at least one structure or feature of the processor design. For example, the conceptual design may include a simulation of a Josephson junction in a superconducting integrated circuit.

[0128] In step 406, a design implementation configuration is generated to realize the conceptual design. The design implementation configuration can be an integrated circuit layout. In one implementation configuration, generating the design implementation configuration involves designing the analog processor layout in an analog design and simulation environment.

[0129] In step 408, a design schematic diagram is generated. The design schematic diagram may be generated based on the design implementation configuration (i.e., analog processor layout). In one implementation configuration, the design schematic diagram may be generated based on the conceptual design. The design schematic diagram can be verified using a layout versus schematic diagram tool. In some implementation configurations, the design schematic diagram can be verified using other conventional electronic design automation tools. In one implementation configuration, the design schematic diagram can be generated in the same analog design and simulation environment as the design implementation configuration.

[0130] In step 410, a device schematic is extracted. The device schematic may also be extracted from the design schematic. The device schematic may correspond to a directed acyclic graph. In one implementation, the device schematic includes at least one atomic device node corresponding to an element (e.g., vertex, leaf, etc.) of the directed acyclic graph.

[0131] In 412, device connectivity data is extracted from the device schematic. Device connectivity data may also be represented in a device connectivity graph. Device connectivity data can be extracted by a netlist device or a tool that writes the device schematic to a text file, and each feature of the device connectivity data is represented. In one implementation, device connectivity data is extracted by a custom-written netlist device. Device connectivity data may include device characteristics and the connectivity of each device to at least one neighboring device. One example of a device characteristic is a device designation that indicates the type or function of the device. For example, a device designation may indicate that the device is a qubit. Another example of a device characteristic is a characteristic annotation that may include metadata attached to the device. A characteristic annotation may include at least one default characteristic. In one implementation, extracting device connectivity data includes extracting device designations, characteristic annotations, neighboring device connectivity (i.e., local bias), or a combination thereof.

[0132] Optionally, in 414, device connectivity data is written to a device connectivity representation stored in a persistent computer-readable medium.

[0133] In 416, bias information is extracted. Bias information can be extracted from device connectivity data by an algorithm. Extracting bias information may include extracting a set of global biases. The global bias includes biases applied to at least one device by a set of global bias lines. Global bias lines can successively bias a set of devices. In a quantum processor, global bias lines electrically couple pads (e.g., bonding pads) to a set of devices and apply each bias to each device. Bias information includes a representation of the electrical coupling of pads to each set of devices in a quantum processor. In one implementation, extracting bias information includes extracting a set of local biases, which include biases applied to a device by at least one neighboring device.

[0134] In step 418, the bias information is written to the device connectivity representation. If operation 414 is omitted in method 400, both the device connectivity data and the bias information are written to the device connectivity representation in step 418.

[0135] In step 420, method 400 terminates until it is called again, for example.

[0136] In some cases, a device object model can be considered an accurate conceptual representation of a processor design. Therefore, it is desirable to perform specific checks on the device object model to verify the accuracy and completeness of the processor design. In one implementation, checking the device object model may include checking that it contains a specific number of qubits. Since a device object model can be generated by reading a device connectivity representation in memory, the device object model can be verified by checking the characteristics of the device connectivity representation, including device connectivity data characteristics, against a list of rules. These rules are dependent on the specific design of the processor and indicate the design intent. An example of a rule is a processor with a specific number of qubits. The device connectivity representation is part of a chain that includes the design implementation. Therefore, if a characteristic does not pass the rules, the failing characteristic can be identified and traced back to the design implementation, allowing the design implementation to be adjusted until the characteristic passes the rules.

[0137] Figure 5 is a flowchart of an example of Method 500, which verifies the device object model based on the device connectivity representation in the processor, according to the present system and method. In some implementations, Method 400 in Figure 4 may precede Method 500. Method 500 includes operations 502-520, although in other implementations, certain operations may be omitted and / or additional operations may be added. Method 500 can be executed by a processor (e.g., the digital processor 304 in Figure 3).

[0138] Method 500 starts at 502, for example, in response to a call from another routine.

[0139] In step 504, a device connectivity representation is loaded. The device connectivity representation may be based on at least a portion of the design implementation (e.g., design layout). The device connectivity representation may include a set of characteristics that characterize at least one programmable device. In one implementation, loading a device connectivity representation includes loading the device connectivity representation in a calibration environment. In several implementations, loading a device connectivity representation may include loading a device object model (e.g., device object model 622 in Figure 6).

[0140] In 506, a set of n rules is identified. This set of n rules can examine the characteristics of a device connectivity representation. In some implementations, the set of n rules can examine the characteristics of a device schematic, device connectivity data, bias information, or a combination thereof. The set of n rules can examine at least one of the following: The presence and / or number of programmable devices (e.g., qubits, couplers, shift register elements, readout elements, etc.). The completeness and / or number of control devices (e.g., digital-to-analog converters (DACs)) associated with each programmable device. Device connectivity data characteristics, including the order of the qubit and the connection between the control device and the programmable device. Examination of the visual representation of a shift register graph, including the coupling from qubits to readout elements (e.g., readout routes). Addressing line characteristics, including the presence of uniquely addressable DACs, the speed of parallel programming, and the efficiency of the filled addressable space. Device bias coloration (e.g., the ability of each qubit to anneal independently of neighboring qubits).

[0141] In some implementations, identifying a set of n rules can include identifying a set of n rules that check for properties different from those described above.

[0142] In 508, the i-th rule is selected from a set of n rules (where 1 ≤ i ≤ n). For example, the first rule is selected from a set of n rules.

[0143] In operation 510, it is determined whether the device connectivity representation passes or fails the i-th rule. For example, a digital processor can determine whether the device connectivity representation passes or fails the first rule. For example, a digital processor can determine whether the device connectivity representation contains a specific number of qubits. The device connectivity representation includes a representation of the device written from the device connectivity data. Furthermore, the device connectivity representation includes a representation of the bias written from the bias information. Each element of the device connectivity representation can be associated with each device connectivity data characteristic. Each device connectivity data characteristic can correspond to a part of the design implementation form of operation 504. If the device connectivity representation passes the i-th rule, operation 518 is performed. If the device connectivity representation fails the i-th rule, operation 512 is performed. For example, if the device connectivity representation fails the first rule which indicates that the device connectivity representation requires a specific number of qubits, operation 512 is performed.

[0144] In step 512, a failing device connectivity data characteristic is identified. A failing device connectivity data characteristic may not pass the first rule. For example, if the first rule indicates that the device connectivity data requires a specific number of qubits, the digital processor may identify the failing device connectivity data characteristic as the number of qubits. Device connectivity data can be extracted from a device schematic, which is based on a design schematic. The design schematic can then be generated based on the design implementation configuration. Thus, a chain containing the above elements (as shown in system 600 in Figure 6) can be traced from the device connectivity data to the design implementation configuration.

[0145] In 514, a portion of the design implementation configuration corresponds to a failing device connectivity data characteristic. For example, in the first rule indicating that the device connectivity representation requires a specific number of qubits, the design implementation configuration could be an analog processor layout, and the failing device connectivity data characteristic is the number of qubits. Thus, a digital processor can identify a portion of the analog processor layout corresponding to the number of qubits.

[0146] In 516, at least a portion of the design implementation configuration is modified until the device connectivity representation passes the i-th rule. For example, if the first rule indicates that the device connectivity representation requires a specific number of qubits, a portion of the analog processor layout may be modified. Modifying the analog processor layout can directly or indirectly change the device connectivity representation, for example, by changing the failing device connectivity data characteristics. The analog processor layout may be modified until the device connectivity representation includes the number of qubits indicated by the first rule. In some implementation configurations, modifying at least a portion of the design implementation configuration can directly or indirectly change the device connectivity representation by changing the design schematic, device schematic, bias information, or a combination thereof.

[0147] In 518, it is determined whether the device connectivity representation has passed the entire set of n rules. If the device connectivity representation has passed the entire set of n rules, method 500 exits with operation 520 until method 500 is called again, for example. If the device connectivity representation has not passed the entire set of n rules, or if not all rules in the set of n rules have been checked, operation 508 is performed. In such a case, operation 508 selects the next rule (i.e., the (i+1)th rule) and performs the next operation of method 500. For example, in at least one implementation, n=2 and the set of n rules may include a first rule indicating that the device connectivity representation requires a certain number of qubits, and a second rule indicating that the device connectivity representation requires a certain number of DACs. The digital processor may determine whether the device connectivity representation has passed these two rules. If the device connectivity representation has passed these two rules, method 500 exits with 520. If the device connectivity representation passes the first rule but fails the second rule (i.e., it contains the required number of qubits but does not contain the required number of DACs, or the number of DACs has not been checked), perform operation 508. Then, identify the second rule indicating the number of DACs and perform the next operation of method 500.

[0148] In some implementations, the device connectivity representation in method 500 can be replaced with a device object model. In such cases, operation 504 is replaced with an operation to load a device object model. Loading a device object model may include extracting representations of device connectivity data and bias information from a device schematic diagram. Loading a device object model may also include loading device connectivity data and bias information in a calibration software environment. The device connectivity data may include the local bias of a device relative to adjacent devices, and the bias information may include the global bias of analog lines relative to a set of devices.

[0149] A device connectivity representation can be generated using method 400 in Figure 4, and a device object model can be verified using method 500 in Figure 5. At least one of methods 400 and 500 can be executed by a digital processor that stores instructions, including system 600 in Figure 6.

[0150] Figure 6 is a schematic diagram of an example of system 600 for extracting and verifying a design object model. The elements of system 600 can be stored in a persistent computer-readable storage medium. When executed, the persistent computer-readable storage medium causes a digital processor to perform operations involving the elements of system 600.

[0151] System 600 includes a conceptual design 602, which can be an expression of the user's intent for a processor design. In one implementation, the conceptual design 602 may include a simulation of a structure (e.g., a Josephson junction) that constitutes part of a superconducting integrated circuit. The conceptual design 602 can be realized in a design implementation 604. The design implementation 604 may be at least part of a design layout. In one implementation, the design implementation 604 is at least part of an integrated circuit design layout. In one implementation, the design implementation 604 is at least part of an analog processor (e.g., a quantum processor) layout. The design implementation 604 can be generated in an analog design and simulation environment. System 600 includes a design schematic 606 based on the design implementation 604. In several implementations, the design schematic 606 is based on the conceptual design 602. The design schematic 606 can be validated against the design implementation 604 using a layout-to-schematic tool 608 or other electronic design automation tools. In a single implementation configuration, the design implementation configuration 604 and the design schematic diagram 606 can be generated using the same analog design and simulation environment.

[0152] System 600 includes a device schematic diagram 610. The device schematic diagram 610 can be extracted from the design schematic diagram 606. In some implementations, the device schematic diagram 610 can be in the form of a directed acyclic graph. For example, the device schematic diagram 610 may include at least one atomic device node corresponding to an element (e.g., vertex, leaf, etc.) of the directed acyclic graph.

[0153] System 600 includes device connectivity data 612. Device connectivity data 612 includes device characteristics and the connectivity of each device to at least one neighboring device. In one implementation, device connectivity data 612 can be a graph. In one implementation, device connectivity data 612 includes a set of local biases, which include biases applied to a device by at least one neighboring device. One example of a device characteristic is a device designation, which can indicate the type or function of a device. For example, a device designation may indicate that a device is a qubit. Another example of a device characteristic is a characteristic annotation, which may include metadata attached to a device. Device connectivity data 612 can also be known as a netlist. Device connectivity data 612 can be written to a device connectivity representation 614.

[0154] System 600 includes bias information 616. Bias information 616 can be extracted from device connectivity data 612. Bias information 616 includes a set of global biases, which include biases applied to at least one device by a set of global bias lines. In a quantum processor, global bias lines electrically couple pads (e.g., bonding pads) to a set of devices, applying each bias to each device. Global bias lines can successively bias a set of devices. Bias information 616 includes a representation of the electrical coupling of pads to each set of devices. Bias information 616 can be written to the device connectivity representation 614.

[0155] The device connectivity representation 614 includes a representation of the programmable device 618 written from the device connectivity data 612, and a representation of the bias 620 written from the bias information 616. The device connectivity representation 614 can be read by a digital processor. In response to reading the device connectivity representation 614, the digital processor can compute the device object model 622. In some implementations, the device object model 622 can be computed by extracting the device connectivity data 612 and bias information 616 from the device schematic diagram 610 (i.e., without the device connectivity representation 614). The device connectivity data 612 and bias information 616 are operable to be loaded in a calibration software environment.

[0156] The elements of system 600 constitute a reference chain from the conceptual design 602 to the device object model 622. The conceptual design 602 can be verified against the device object model 622. Verification 624 may include checking the device object model 622 to evaluate the conceptual accuracy of the conceptual design 602. Errors can be identified by tracing back the reference chain. The method of verification 624 is illustrated by method 500 in Figure 5. In some implementations, the device object model 622 is a representation of the quantum processor.

[0157] Processor calibration can include a set of calibration rules that require a description of the relationship between programmable devices, device connectivity, and bias mechanisms for each calibration instance. Figure 7 illustrates a data structure suitable for representing a processor in many calibration instances, containing specific elements of system 600 in Figure 6.

[0158] Figure 7 is a schematic diagram showing an example of a data structure 700 that can be operated to represent a processor in operation. The elements of the data structure 700 can be stored in a persistent computer-readable storage medium. When executed, the persistent computer-readable storage medium causes the digital processor to perform an operation that includes the elements of the data structure 700.

[0159] The data structure 700 includes a device connectivity representation 702 which contains a programmable device description and bias information extracted from a device schematic diagram (e.g., device schematic diagram 610 in Figure 6). The device connectivity representation 702 is an interface for loading the programmable device description into memory, thereby computing a device object model. The programmable device description may include device specifications, device connectivity, intrinsic characteristics of each device, and local biases on each device by neighboring devices. The programmable device description can represent a processor (e.g., an analog processor or a quantum processor) in operation. In particular, the programmable device description can represent a quantum process in calibration. Examples of programmable devices include (but are not limited to) qubits, couplers, DACs, shift register stages, readout elements, inductance tuners, process control monitoring devices, and heaters.

[0160] The data structure 700 includes a representation of continuous calibration data 704. Calibration data 704 may be data aggregated in and retrieved from the device object model 710. The data structure 700 includes a representation of programmable device definition 706. Programmable device definition 706 includes configuration characteristic annotations, bias annotations, and connectivity annotations for each programmable device. Programmable device definition 706 includes at least one set of meta-objects (e.g., structures and classes). Furthermore, the data structure 700 includes instructions for programmable device method 708, which includes a method for collecting and modifying devices. Some examples of programmable device method 708 may include, but are not limited to, the following: Identifying a set of qubits coupled to a specific qubit. Identifying the bias that addresses a specific DAC. Identifying the set of DACs associated with a specific device. Identifying the shift register stage that forms at least part of the path from the qubit to the readout.

[0161] The device object model 710 includes a programmable device representation based on the device connectivity representation 702. The data structure 700 includes instructions for the calibration algorithm 712. The calibration algorithm 712 may include methods for aggregating data and retrieving data from the programmable device representation contained in the device object model 710. For example, the calibration algorithm 712 can be used to aggregate data from the device object model 710 to the device representation during calibration. The calibration algorithm 712 may include methods for continuously managing versions of the calibration data 704.

[0162] The methods, processes, or techniques described above can be implemented by a series of processor-readable instructions stored in one or more persistent processor-readable media. Some examples of the methods, processes, or techniques described above can be partially implemented by a dedicated device such as an adiabatic quantum computer or quantum annealer or system that programs or otherwise controls the operation of an adiabatic quantum computer or quantum annealer (e.g., a computer including at least one digital processor). The methods, processes, or techniques described above may include a variety of operations, although in alternative examples certain operations may be omitted and / or additional operations may be added. The order of the examples of operations is shown for illustrative purposes only and may vary in alternative examples, as will be seen by those skilled in the art. Some exemplary acts or operations of the methods, processes, or techniques described above can be performed iteratively. Some operations of the methods, processes, or techniques described above can be performed during each iteration, after multiple iterations, or at the end of all iterations.

[0163] The above description of exemplary implementations, including those described in the abstract, is not exhaustive or intended to limit implementations to the exact forms of the disclosure. Certain implementations and examples are provided herein for illustrative purposes, but various modifications of equivalents can be made without departing from the spirit and scope of the disclosure, as will be apparent to those skilled in the art. The teachings provided herein for various implementations can be applied to other methods of quantum computing (not necessarily limited to the exemplary methods for quantum computing described herein).

[0164] Further implementation forms can be provided by combining the various implementation forms described above. All U.S. Patent Publications, U.S. Patent Applications, Foreign Patents, and Foreign Patent Applications of the Same Applicant referenced in this Specification and / or listed in the Application Data Sheet, including U.S. Patent No. 9,152,923, U.S. Patent Application Publication No. 2007 / 0239366, U.S. Patent Application No. 62 / 873,711 filed on 12 July 2019, and U.S. Patent Application No. 62 / 879,946 filed on 29 July 2019 (but not limited to these), are incorporated herein by reference as a whole.

[0165] In light of the above description, these and other modifications may be made to the implementation. In general, the terms used in the following claims should not be interpreted to limit the claims to any particular implementation disclosed in the specification and claims, but rather to include all possible implementations together with the entire range of equivalents granting rights to such claims. Accordingly, the claims are not limited by the disclosure.

Claims

1. A method for extracting a device object model representing the physical design of a device from a quantum processor layout, the method being performed by a digital processor and autonomously by the digital processor, Extracting a device schematic from a design schematic that includes at least one qubit and one coupler, Extracting device connectivity data from the device schematic diagram, Writing the aforementioned device connectivity data to the device connectivity representation, Extracting a set of qubit biases from the device connectivity data, Writing the aforementioned set of qubit biases to the device connectivity representation A method that includes this.

2. The method according to claim 1, wherein extracting a device schematic from a design schematic includes extracting a device schematic from a design schematic that can be verified by an electronic design automation tool.

3. The method according to claim 1, wherein extracting a device schematic from a design schematic includes extracting a device schematic corresponding to a directed acyclic graph.

4. The method according to claim 3, wherein extracting a device schematic diagram corresponding to a directed acyclic graph includes extracting a device schematic diagram that includes at least one atomic device node corresponding to a directed acyclic graph.

5. The method according to claim 1, wherein the extraction of the device connectivity data includes extracting at least one of a device designation, a characteristic annotation, and at least one adjacent device connection.

6. The method according to claim 1, wherein extracting a set of qubit biases from the device connectivity data includes extracting a set of global biases.

7. The method according to claim 6, wherein extracting a set of global biases includes extracting a set of connections that electrically couple a pad to at least one programmable device.

8. The method according to claim 1, further comprising performing the device connectivity representation to compute a device object model representing the physical design of the device.

9. At least one digital processor, At least one persistent processor-readable storage medium that can be communicatively coupled to the at least one digital processor, wherein when the at least one digital processor executes a processor-executable instruction, Extracting a device schematic from a design schematic that includes at least one qubit and one coupler, Extracting device connectivity data from the device schematic diagram, Writing the aforementioned device connectivity data to the device connectivity representation, Extracting a set of qubit biases from the device connectivity data, Writing the aforementioned set of qubit biases to the device connectivity representation, A persistent processor-readable storage medium storing at least one processor-executable instruction that causes the at least one digital processor to execute, A computing system that includes this.

10. A calculation system according to claim 9, wherein the device schematic diagram is verifiable by an electronic design automation tool.

11. A calculation system according to claim 9, wherein the device schematic diagram corresponds to a directed acyclic graph.

12. A computing system according to claim 11, wherein the device schematic diagram includes at least one atomic device node corresponding to a directed acyclic graph.

13. A calculation system according to claim 9, wherein the device connectivity data includes at least one of a device designation, a characteristic annotation, and at least one adjacent device connection.

14. A computing system according to claim 9, wherein the set of qubit biases from the device connectivity data includes a set of global biases.

15. A calculation system according to claim 14, wherein the set of global biases includes a set of connections that electrically couple pads to at least one programmable device.

16. A computing system according to claim 9, further comprising causing the at least one digital processor to perform a device connectivity representation for computing a device object model representing the physical design of a device.

Images