Memory device and method for forming the same

Abstract

The memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure includes word line driver circuitry and sense amplifier circuitry. A first area including the word line driver circuitry and sense amplifier circuitry at least partially overlaps a second area including the memory blocks in a plan view of the memory device.

Description

[[Technical Field]]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application Publication No. PCT / CN2023 / 109534 filed on Jul. 27, 2023, which claims the benefit of priority from U.S. Provisional Application No. 63 / 436,430 filed on Dec. 30, 2022, and the entire contents of both of these applications are incorporated herein by reference.

[0002] The present disclosure relates to a memory device and a method of manufacturing the same. [[Background Art]]

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing techniques have become difficult and costly. As a result, the memory density of planar memory cells approaches the upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density constraint in planar memory cells. A 3D memory architecture includes a memory array and peripheral circuits for supporting operation of the memory array. [[Summary of Invention]] [[Means for Solving the Problems]]

[0005] In one aspect, a memory device is disclosed. The memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, and each memory bank includes a plurality of memory blocks. The peripheral structure includes a word line driver circuit and a sense amplifier circuit. A first area including the word line driver circuit and the sense amplifier circuit at least partially overlaps a second area including the memory blocks in a top plan view of the memory device.

[0006] In some implementations, the first area includes a first sub-area containing a word line driver circuit and a second sub-area containing a sense amplifier circuit. The first and second sub-areas are arranged alternately within the first area.

[0007] In some implementations, the first area includes two first sub-areas and two second sub-areas. The two first sub-areas are located at diagonal corners of the first area, and the two second sub-areas are located at diagonal corners of the first area.

[0008] In some implementations, the first area completely overlaps with the second area in the plan view of the memory device.

[0009] In some implementations, the word line driver circuit in one of the two first sub-areas is coupled to the odd-numbered word lines in the memory block, and the word line driver circuit in the other of the two first sub-areas is coupled to the even-numbered word lines in the memory block.

[0010] In some implementations, the first area includes a first sub-area containing a word line driver circuit and two second sub-areas, each containing a sense amplifier circuit. The two second sub-areas are located on two sides of the first sub-area.

[0011] In some implementations, the sense amplifier circuit in one of the two second sub-areas is shared by two adjacent memory blocks.

[0012] In some implementations, the sense amplifier circuits in the two second sub-areas are coupled to the word lines in the memory block.

[0013] In some implementations, the sense amplifier circuit in one of the two second sub-areas is coupled to the odd-numbered word lines in the memory block and the odd-numbered word lines in the first adjacent memory block, while the sense amplifier circuit in the other of the two second sub-areas is coupled to the even-numbered word lines in the memory block and the even-numbered word lines in the second adjacent memory block.

[0014] In some implementations, the word line driver circuit in the first sub-area is coupled to either the odd-numbered or even-numbered word lines in the memory block.

[0015] In some implementations, the word line driver circuit in the first sub-area is coupled to an odd-numbered or even-numbered word line in an adjacent memory block.

[0016] In some implementations, the first area includes a first sub-area containing a word line driver circuit, a second sub-area containing a sense amplifier circuit, and a third sub-area containing a decoder circuit. The first sub-area is located between adjacent memory blocks in the plan view of the memory device, and the second and third sub-areas overlap with the second area of ​​the memory block in the plan view of the memory device.

[0017] In some implementations, the first area further includes a fourth sub-area containing a control circuit for the sense amplifier circuit, the fourth sub-area being located between the second and third sub-areas.

[0018] In some implementations, the second, third, and fourth sub-areas overlap with the second area of ​​the memory block in the plan view of the memory device.

[0019] In some implementations, the first area includes a first sub-area containing a word line driver circuit and two second sub-areas, each containing a sense amplifier circuit. The first sub-area is located between adjacent memory blocks in the plan view of the memory device, and the two second sub-areas overlap with the second area of ​​the memory block in the plan view of the memory device.

[0020] In some implementations, the first area further includes a third sub-area containing a control circuit for the sense amplifier circuit, and the third sub-area is located between two second sub-areas.

[0021] In some implementation configurations, the memory array structure is disposed on a first substrate, while the peripheral structure is disposed on a second substrate that is different from the first substrate.

[0022] In some implementation configurations, the memory array structure, which is disposed on the first substrate, is connected to the peripheral structure, which is disposed on the second substrate.

[0023] In some implementations, the memory array structure includes dynamic random access memory (DRAM).

[0024] In another embodiment, a memory device is disclosed. The memory device includes a memory array structure and a peripheral structure. The memory array structure is disposed on a first substrate which includes at least one memory bank, each memory bank which includes a plurality of memory blocks. The peripheral structure is disposed on a second substrate which is different from the first substrate which includes a sense amplifier circuit and a word line driver circuit. The sense amplifier circuit overlaps with the memory blocks in a plan view of the memory device.

[0025] In some implementations, the word line driver circuit is located between adjacent memory blocks in the plan view of the memory device.

[0026] In some implementations, the peripheral structure further includes decoder circuits that overlap with the memory block in the plan view of the memory device.

[0027] In some implementations, the peripheral structure further comprises a control circuit for a sense amplifier circuit that overlaps with the memory block in a plan view of the memory device.

[0028] In some implementations, the word line driver circuit overlaps with the memory block in a plan view of the memory device.

[0029] In some implementations, the sense amplifier circuit comprises a first sub-area and a second sub-area disposed on two sides of the word line driver circuit in a plan view of the memory device.

[0030] In some implementations, the sense amplifier circuit comprises a first sub-area and a second sub-area, and the word line driver circuit comprises a third sub-area and a fourth sub-area. The first sub-area and the third sub-area are disposed at opposite diagonal corners overlapping the memory block in a plan view of the memory device, and the second sub-area and the fourth sub-area are disposed at the other opposite diagonal corners overlapping the memory block in a plan view of the memory device.

[0031] In some implementations, the memory array structure comprises dynamic random access memory (DRAM).

[0032] In yet another aspect, a method for forming a memory device is disclosed. A memory array structure is formed on a first substrate. The memory array structure comprises at least one memory bank, and each memory bank comprises a plurality of memory blocks. A peripheral structure is formed on a second substrate different from the first substrate. The peripheral structure comprises a word line driver circuit and a sense amplifier circuit. The memory array structure and the peripheral structure are bonded such that the word line driver circuit and the sense amplifier circuit at least partially overlap the memory block in a plan view of the memory device.

[0033] In some implementations, the word line driver circuit is formed in a first sub-area, and the sense amplifier circuit is formed in a second sub-area.

[0034] In some implementations, the first and second sub-areas are located at diagonal corners of the memory block in the plan view of the memory device.

[0035] In some implementations, the word line driver circuit is formed in the first sub-area, and the sense amplifier circuit is formed in the second and third sub-areas.

[0036] In some implementations, the second and third sub-areas are located on two sides of the first sub-area in the plan view of the memory device.

[0037] In some implementations, the first sub-area is located between adjacent memory blocks in the plan view of the memory device, while the second and third sub-areas overlap with memory blocks in the plan view of the memory device.

[0038] In some implementations, the word line driver circuit is formed in the first sub-area, the sense amplifier circuit is formed in the second sub-area, and the decoder circuit is formed in the third sub-area.

[0039] In some implementations, the first sub-area is located between adjacent memory blocks in the plan view of the memory device, while the second and third sub-areas overlap with memory blocks in the plan view of the memory device.

[0040] In yet another embodiment, a system is disclosed. The system includes a memory device and a memory controller coupled to the memory device. The memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure includes a word line driver circuit and a sense amplifier circuit. The first area including the word line driver circuit and the sense amplifier circuit at least partially overlaps with a second area including the memory blocks in a plan view of the memory device. The memory controller is configured to control the operation of the memory array structure through the peripheral structure.

[0041] In yet another embodiment, a system is disclosed. The system includes a memory device and a memory controller coupled to the memory device. The memory device includes a memory array structure and peripheral structures. The memory array structure is disposed on a first substrate which includes at least one memory bank, each memory bank which includes a plurality of memory blocks. The peripheral structures are disposed on a second substrate which is different from the first substrate which includes a sense amplifier circuit and a word line driver circuit. The sense amplifier circuit overlaps with the memory blocks in a plan view of the memory device. The memory controller is configured to control the operation of the memory array structure through the peripheral structures.

[0042] The accompanying drawings incorporated herein and forming part thereof illustrate aspects of the present disclosure and, together with the description, further serve to illustrate the principles of the present disclosure and enable those skilled in the art to prepare and use the present disclosure. [Brief explanation of the drawing]

[0043] [Figure 1A] These are schematic diagrams of cross-sections of memory devices according to some aspects of this disclosure. [Figure 1B] This is a schematic diagram of a cross-section of another memory device according to some aspects of the present disclosure. [Figure 2]This is a schematic diagram of a memory device, according to some aspects of the present disclosure, which includes an array of memory cells having peripheral circuits and vertical transistors, respectively. [Figure 3] This is a schematic circuit diagram of a memory device including peripheral circuits and an array of dynamic random access memory (DRAM) cells, according to some aspects of the present disclosure. [Figure 4] This is a schematic circuit diagram of a memory device including peripheral circuits and an array of phase-change memory (PCM) cells, according to some aspects of the present disclosure. [Figure 5] This is a schematic perspective view of a memory device according to several aspects of this disclosure. [Figure 6] These are schematic plan views of memory devices according to some aspects of the present disclosure. [Figure 7] This is a schematic diagram of the arrangement of memory devices according to some aspects of the present disclosure. [Figure 8] This is a schematic diagram of a word line driver circuit for a memory device according to some aspects of the present disclosure. [Figure 9] These are schematic diagrams of sense amplifier circuits for memory devices according to some aspects of the present disclosure. [Figure 10] These are schematic plan views of memory devices according to some aspects of the present disclosure. [Figure 11] This is a schematic diagram of the arrangement of memory devices according to some aspects of the present disclosure. [Figure 12] These are schematic diagrams of sense amplifier circuits for memory devices according to some aspects of the present disclosure. [Figure 13] These are schematic plan views of memory devices according to some aspects of the present disclosure. [Figure 14] This is a schematic diagram of a memory device connection circuit according to some aspects of the present disclosure. [Figure 15] These are schematic plan views of memory devices according to some aspects of the present disclosure. [Figure 16] This is a schematic plan view of a peripheral circuit according to some aspects of the present disclosure. [Figure 17]These are schematic diagrams of decoders and control logic for memory devices according to some aspects of the present disclosure. [Figure 18] This is a flowchart of a method for forming a memory device according to some aspects of the present disclosure. [Figure 19] This is a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure. [Modes for carrying out the invention]

[0044] This disclosure will be described with reference to the attached drawings.

[0045] While specific configurations and arrangements are discussed, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be used in various other applications. Functional and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically shown in the drawings, such that their combinations, adjustments, and modifications remain within the scope of this disclosure.

[0046] In general, terms can be understood at least partially from their usage in context. For example, in this specification, the term “one or more” may be used, at least partially depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” can be understood, at least partially depending on the context, to convey either a singular or plural usage. In addition, the term “based on” may be understood not necessarily to convey an exclusive set of factors, and instead, at least partially depending on the context, may allow for the presence of additional factors, which are also not necessarily explicitly described.

[0047] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, so as “on” not only means “directly in contact” with something, but also include the meaning of “in contact” with something accompanied by an intermediate object or layer, and “above” or “over” not only means being “on” something or “covering” it, but can also include the meaning of being “on” something or “covering” it (directly in contact with something) without an intermediate object or layer.

[0048] Furthermore, spatial relation terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to simplify explanations in describing the relationship between one element or object and another, as shown in the drawings. The spatial relation terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawings. The device may be facing a different direction (rotated 90 degrees, or in any other orientation), and the spatial relation descriptors used herein may be interpreted accordingly.

[0049] In this specification, the term “substrate” refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made from a non-conductive material such as glass, plastic, or a sapphire wafer.

[0050] In this specification, the term “layer” refers to a portion of a material that includes a region of thickness. A layer may extend to cover the entirety of a behind or overlapping structure, or it may have a smaller extent than the extent of the behind or overlapping structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or on the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along tapered surfaces. A substrate may be a single layer, contain one or more layers, and / or have one or more layers in contact with, on, and / or below it. A layer may include multiple layers. For example, an interconnection layer may include one or more conductor and contact layers (in which interconnection lines and / or vertical interconnection access (via) contacts are formed) and one or more dielectric layers.

[0051] Transistors are used as switch or selector devices in memory cells of several memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM®). However, planar transistors commonly used in existing memory cells typically have a horizontal structure where the word line is embedded in the substrate and the bit line is on top of the substrate. Because the source and drain of a planar transistor are arranged laterally in different positions, this increases the area occupied by the transistor. This design of planar transistors also complicates the arrangement of interconnected structures such as word lines and bit lines coupled to the memory cell, for example, by limiting the pitch of the word line and / or bit line, thereby increasing manufacturing complexity and lowering manufacturing yield. Moreover, because the bit line and memory units (e.g., capacitors or PCM elements) are located on the same side of the planar transistor (on top of the transistor and substrate), the process margin of the bit line is limited by the memory unit, and the coupling capacitance between the bit line and memory units such as capacitors increases. In addition, planar transistors can have high leakage current as the saturated drain current continues to increase, which is undesirable for the performance of the memory device.

[0052] On the other hand, the memory cell array and the peripheral circuits for controlling the memory cell array are usually arranged side by side on the same plane. As the number of memory cells continues to increase, the dimensions of the components within the memory cell array, such as transistors, word lines, and / or bit lines, must continue to shrink in order to maintain the same chip size and not significantly reduce the efficiency of the memory cell array.

[0053] To address one or more of the aforementioned problems, this disclosure introduces a policy such that vertical transistors replace planar transistors as switch and select devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM®). Compared to planar transistors, vertically arranged transistors (e.g., drain and source overlap in the planar view) reduce the area of ​​the transistor and simplify the layout of interconnect structures, such as word lines and bit lines in metal wiring, which can reduce manufacturing complexity and improve yield. For example, the pitch of word lines and / or bit lines can be reduced to simplify manufacturing. The vertical arrangement of transistors also allows bit lines and memory units, capacitors, etc., to be located on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and the other below the transistor), thus increasing the process margin of the bit lines and reducing the coupling capacitance between the bit lines and memory units.

[0054] Without inconsistency with the scope of this disclosure, according to some aspects of this disclosure, memory cell arrays having vertical transistors and peripheral circuits of memory cell arrays may be formed on different wafers and bonded together face to face. Thus, the thermal budget for fabricating the memory cell array does not affect the fabrication of the peripheral circuits. Stacked memory cell arrays and peripheral circuits can also reduce the chip size compared to adjacent arrangements, thereby improving array efficiency. In some implementations, more than one memory cell array is stacked on top of each other using bonding techniques to further increase array efficiency. In some implementations, word lines and bit lines are located near the bonding boundary due to the vertical arrangement of the transistors, and they may be coupled to the peripheral circuits through a large number (e.g., millions) of parallel bonding contacts spanning the bonding boundary, which can establish direct, short-range (e.g., micron-level) electrical connections between the memory cell array and the peripheral circuits, increasing the throughput and input / output (I / O) speed of the memory device.

[0055] In some implementations, the vertical transistors disclosed herein include multi-gate transistors (e.g., gate-all-around (GAA) transistors, tri-gate transistors, or double-rate transistors), which may have a wider gate control area to achieve better channel control with smaller subthreshold swings. Since the channel is completely exhausted, the leakage current of multi-gate transistors can also be greatly reduced. Therefore, by using multi-gate transistors instead of planar transistors, much higher speed (saturated drain current) / leakage current performance can be achieved.

[0056] In some implementations, the vertical transistors disclosed herein include single-gate transistors (also known as single-side-gate transistors) that are arranged symmetrically with respect to adjacent transistors in the bit-line direction as a result of dividing a multi-gate transistor (e.g., a double-gate transistor) using trench isolation extending in the word-line direction. Thus, the memory cell density in the bit-line direction can be greatly increased (e.g., doubled) without excessively complicating the fabrication process compared to using processes such as self-aligned double patterning (SADP). Furthermore, the line-symmetric single-gate transistors have a larger process window for word-line, bit-line, and transistor pitch reductions compared to planar transistors or multi-gate vertical transistors with, for example, dual-side-gate or all-around-gate configurations.

[0057] Figure 1A shows a schematic cross-sectional view of a memory device 100 according to several aspects of the present disclosure. The memory device 100 represents an example of a bonded chip. The components of the memory device 100 (e.g., a memory cell array and peripheral circuits) may be formed separately on different substrates and then bonded together to form a bonded chip. The memory device 100 may include a first semiconductor structure 102 containing peripheral circuits for a memory cell array. The memory device 100 may also include a second semiconductor structure 104 containing a memory cell array. The peripheral circuits (also known as control and sensing circuits) may include any suitable digital circuits, analog circuits, and / or mixed-signal circuits used to assist the operation of the memory cell array. For example, peripheral circuits may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuits, charge pumps, voltage sources or generators, current or voltage references, any part of the functional circuits mentioned above (e.g., subcircuits), or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). According to some implementation forms, peripheral circuits in the first semiconductor structure 102 use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented, for example, in logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0058] As shown in Figure 1A, the memory device 100 may also include a second semiconductor structure 104 which includes an array of memory cells (memory cell array) that can use transistors as switch and select devices. In some implementations, the memory cell array includes an array of DRAM cells. For simplicity of explanation, in this disclosure, a DRAM cell array may be used as an example to describe a memory cell array. However, it will be understood that a memory cell array is not limited to a DRAM cell array and may include any other suitable type of memory cell that can use transistors as switch and select devices, such as PCM cell arrays, static random access memory (SRAM) cell arrays, FRAM® cell memory, resistive memory cell arrays, magnetic memory cell arrays, spin-transfer torque (STT) memory cell arrays, or any combination thereof.

[0059] The second semiconductor structure 104 may be a DRAM device in which memory cells are provided in the form of an array of DRAM cells. In some implementations, each DRAM cell includes a capacitor for storing bits of data as positive or negative charge, as well as one or more transistors (also known as pass transistors) that control access to it (e.g., by switching and selecting). In some implementations, each DRAM cell is a 1-transistor 1-capacitor (1T1C) cell. Since transistors constantly leak small amounts of charge, capacitors slowly discharge and lose the stored information. Therefore, according to some implementations, DRAM cells must be refreshed to retain data, for example, by peripheral circuits in the first semiconductor structure 102.

[0060] As shown in Figure 1A, the memory device 100 further includes a bonding boundary 106 perpendicularly (in the vertical direction, for example, in the Z direction in Figure 1A) between the first semiconductor structure 102 and the second semiconductor structure 104. As will be described in detail below, the first semiconductor structure 202 and the second semiconductor structure 204 may be fabricated separately (or in parallel in some implementations) so that the thermal budget for fabricating one of the first semiconductor structure 202 and the second semiconductor structure 204 does not limit the process for fabricating the other of the first semiconductor structure 202 and the second semiconductor structure 204. Furthermore, since numerous interconnections (e.g., bonding contacts) can be formed through bonding boundaries 106 to establish direct, short-range (e.g., micron-level) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, rather than long-range (e.g., millimeter or centimeter-level) interchip data buses on circuit boards such as printed circuit boards (PCBs), chip interface delays are eliminated, and high-speed I / O throughput is achieved with low power consumption. Data movement between the memory cell array in the second semiconductor structure 104 and the peripheral circuits in the first semiconductor structure 102 can be performed through interconnections (e.g., bonding contacts) spanning the bonding boundaries 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and the memory cell density can be increased.

[0061] It is understood that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Figure 1B shows a schematic cross-section of another exemplary memory device 101 according to several implementation configurations. Unlike the memory device 100 in Figure 1A, where the second semiconductor structure 104 containing the memory cell array is on top of the first semiconductor structure 102 containing the peripheral circuitry, in the memory device 101 in Figure 1B, the first semiconductor structure 102 containing the peripheral circuitry is on top of the second semiconductor structure 104 containing the memory cell array. Nevertheless, according to several implementation configurations, a bonding boundary 106 is formed perpendicularly between the first semiconductor structure 102 and the second semiconductor structure 104 in the memory device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are perpendicularly bonded through bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal / dielectric hybrid bonding," is a direct bonding technique (for example, forming a bond between surfaces without using an intermediate layer such as solder or adhesive) that can simultaneously achieve metal-metal (e.g., copper to copper) bonding and dielectric-dielectric (e.g., silicon oxide to silicon oxide) bonding. Data transfer between the memory cell array in the second semiconductor structure 104 and the peripheral circuit in the first semiconductor structure 102 can be performed through interconnects (e.g., bonding contacts) spanning the bonding boundary 106.

[0062] Note that the X, Y, and Z axes are included in Figures 1A and 1B to further illustrate the spatial relationships of the components of memory devices 100 and 101. The substrate of the memory device includes two transversely elongated surfaces extending laterally in the XY plane: the top surface of the front side of the wafer on which the semiconductor device may be formed, and the bottom surface of the back side of the wafer opposite to the front side. The Z axis is orthogonal to each of the X and Y axes. In this specification, whether one component (e.g., a layer or device) is "in contact" with, "on top of," or "below" another component (e.g., a layer or device) of the memory device is determined relative to the substrate of the memory device in the Z direction (a perpendicular direction to the XY plane, e.g., the thickness direction of the substrate) when the substrate is positioned on the bottommost surface of the memory device in the Z direction. The same concept for describing spatial relationships applies throughout this disclosure.

[0063] Figure 2 shows a schematic diagram of a memory device 200 according to several embodiments of the present disclosure, including peripheral circuits and an array of memory cells, each having a vertical transistor. The memory device 200 may include a memory cell array 201 and peripheral circuits 202 coupled to the memory cell array 201. Memory devices 100 and 101 may be examples of memory devices 200, such that the memory cell array 201 and peripheral circuits 202 may be contained in a second semiconductor structure 104 and a first semiconductor structure 102, respectively. The memory cell array 201 may be any suitable memory cell array, such that each memory cell 208 includes a vertical transistor 210 and a storage unit 212 coupled to the vertical transistor 210. In some implementations, the memory cell array 201 is a DRAM cell array, and the storage unit 212 is a capacitor for storing charge as binary information stored by each DRAM cell. In some implementations, the memory cell array 201 is a PCM cell array, and the storage unit 212 is a PCM element for storing binary information of each PCM cell based on the different resistances of the PCM elements (e.g., including chalcogenide alloys) in amorphous and crystalline phases. In some implementations, the memory cell array 201 is a FRAM® cell array, and the storage unit 212 is a ferroelectric capacitor for storing binary information of each FRAM® cell based on the switching of two polarization states of a ferroelectric material under an external electric field.

[0064] As shown in Figure 2, the memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 200 may include word lines 204 connecting the peripheral circuitry 202 to the memory cell array 201 for controlling the switching of vertical transistors 210 in the memory cells 208 located in the rows, and bit lines 206 connecting the peripheral circuitry 202 to the memory cell array 201 for transmitting data to and / or receiving data from the memory cells 208 located in the columns. That is, each word line 204 is connected to each row of the memory cells 208, and each bit line is connected to each column of the memory cells 208.

[0065] Without inconsistency with the scope of this disclosure, as will be described in detail below, a vertical transistor 210, such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), can replace a planar transistor as a pass transistor for a memory cell 208, reducing the area occupied by the pass transistor, coupled capacitance, and complexity of interconnect routing. As shown in Figure 2, in some implementations, unlike a planar transistor where the active region is formed within the substrate, the vertical transistor 210 includes a semiconductor body 214 extending perpendicularly (in the Z direction) above the substrate (not shown). That is, the semiconductor body 214 can extend above the top surface of the substrate to allow channels to be formed not only on the top surface of the semiconductor body 214 but also on one or more of its sides. As shown in Figure 2, for example, the semiconductor body 214 may have a cubic shape to expose its four faces. It will be understood that the semiconductor body 214 may have any suitable 3D shape, such as a polyhedron or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in a plan view (e.g., the XY plane) may have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other suitable shape. Without being inconsistent with the scope of this disclosure, even for semiconductor bodies whose cross-section is circular or elliptical in a plan view, the semiconductor body may be considered to have multiple sides, so it is understood that the gate structure is in contact with more sides than one of the semiconductor body. As the manufacturing process is described below, the semiconductor body 214 may be formed from a substrate (e.g., by etching or epitaxy), so it has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0066] As shown in Figure 2, the vertical transistor 210 may also include a gate structure 216 in contact with one or more sides of the semiconductor body 214, for example, on one or more planes of the sides of the active region. In other words, the active region of the vertical transistor 210, for example, the semiconductor body 214, may be at least partially surrounded by the gate structure 216. As shown in Figure 2, the gate structure 216 may include a gate dielectric 218 that covers one or more sides of the semiconductor body 214, for example, in contact with four sides of the semiconductor body 214. The gate structure 216 may also include a gate electrode 220 that covers and is in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide in the form of a gate oxide. The gate electrode 220 may include any suitable conductive material such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metallic compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, the gate electrode 220 may include doped polysilicon in the form of gate poly. In some implementations, the gate electrode 220 includes multiple conductive layers, such as a W layer covering a TiN layer. In some examples, it is understood that the gate electrode 220 and the word line 204 may be a continuous conductive structure. In other words, the gate electrode 220 may be considered as part of the word line 204 forming the gate structure 216, or the word line 204 may be considered as an extension of the gate electrode 220 to be coupled to the peripheral circuit 202.

[0067] As shown in Figure 2, the vertical transistor 210 may further include source and drain pairs (also known as S / D, doped regions, source electrodes, and drain electrodes) formed at the two ends of the semiconductor body 214 in the vertical direction (z direction). The source and drain may be doped with any suitable P-type dopant such as boron (B) or gallium (Ga), or any suitable N-type dopant such as phosphorus (P) or arsenic (As). The source and drain may be separated in the vertical direction (z direction) by a gate structure 216. In other words, the gate structure 216 is formed perpendicularly between the source and drain. As a result, when the gate voltage applied to the gate electrode 220 of the gate structure 216 exceeds the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed perpendicularly between the source and drain in the semiconductor body 214. That is, according to some implementations, each channel of the vertical transistor 210 may also be formed in the vertical direction along which the semiconductor body 214 extends.

[0068] In some implementations, as shown in Figure 2, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can contact more than one side (e.g., four sides in Figure 2) of the semiconductor body 214 to form more than one gate, so that more than one channel can be formed between the source and drain during operation. In other words, unlike a planar transistor which contains only a single planar gate (and results in a single planar channel), the vertical transistor 210 shown in Figure 2 can contain multiple vertical gates on multiple sides of the semiconductor body 214 due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214. As a result, compared to a planar transistor, the vertical transistor 210 shown in Figure 2 may have a wider gate control area to achieve better channel control with a smaller subthreshold swing. Since the channel is completely exhausted, the leakage current of the vertical transistor 210 ( Ioff) can also be significantly reduced. As will be explained in detail below, multi-gate vertical transistors may include double-gate vertical transistors (e.g., dual-side gate vertical transistors), tri-gate vertical transistors (e.g., tri-side gate vertical transistors), and GAA vertical transistors.

[0069] Although the vertical transistor 210 is shown as a multi-gate transistor in Figure 2, it will be understood that the vertical transistors disclosed herein may also include single-gate transistors, as will be described in detail below. That is, the gate structure 216 may be in contact with a single side of the semiconductor body 214, for example, to increase the transistor and memory cell density. Although the gate dielectric 218 is shown as separate (a separate structure) from other gate dielectrics of adjacent vertical transistors (not shown), it will be understood that the gate dielectric 218 may also be part of a continuous dielectric layer having multiple gate dielectrics of the vertical transistor.

[0070] In planar transistors and some transverse multi-gate transistors (e.g., FinFETs), the active region, such as the semiconductor body (e.g., Fin), extends transversely (in the XY plane), and the source and drain are located at different positions in the same transverse plane (XY plane). In contrast, in a vertical transistor 210, according to some implementations, the semiconductor body 214 extends vertically (in the Z direction), and the source and drain are located in different transverse planes. In some implementations, the source and drain are formed at the two ends of the semiconductor body 214 in the vertical direction (Z direction), respectively, and thus overlap in the plan view. As a result, the area occupied by the vertical transistor 210 (in the XY plane) can be reduced compared to planar transistors and transverse multi-gate transistors. Also, since interconnections can be routed in different planes, the metal wiring coupled to the vertical transistor 210 can be simplified. For example, the bit line 206 and memory unit 212 can be formed on the opposite side of the vertical transistor 210. In one example, bit line 206 may be coupled to a source or drain at the upper end of the semiconductor body 214, while memory unit 212 may be coupled to another source or drain at the lower end of the semiconductor body 214.

[0071] As shown in Figure 2, the memory unit 212 may be coupled to the source or drain of the vertical transistor 210. The memory unit 212 may include, but is not limited to, any device capable of storing binary data (e.g., 0s and 1s), including capacitors for DRAM cells and FRAM® cells, and PCM elements for PCM cells. In some implementations, the vertical transistor 210 controls the selection and / or state switching of each memory unit 212 coupled to the vertical transistor 210.

[0072] Figure 3 shows a schematic diagram of a memory device 200, including an array of memory cells, each having peripheral circuits and vertical transistors, according to some aspects of the present disclosure. In some implementations as shown in Figure 3, each memory cell 208 is a DRAM cell 302 including a transistor 304 (for example, implemented using a vertical transistor 210 as shown in Figure 2) and a capacitor 306 (for example, the example of a memory unit 212 in Figure 2). The gate of transistor 304 (for example, corresponding to a gate electrode 220) may be coupled to a word line 204, one of the source and drain of transistor 304 may be coupled to a bit line 206, the other of the source and drain of transistor 304 may be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 may be coupled to ground.

[0073] Figure 4 shows a schematic diagram of a memory device 200, including an array of memory cells, each having peripheral circuits and vertical transistors, according to some aspects of the present disclosure. In some implementations shown in Figure 4, each memory cell 208 is a PCM cell 402, including a transistor 404 (for example, implemented using the vertical transistor 210 in Figure 2) and a PCM element 406 (for example, the example of the memory unit 212 in Figure 2). The gate of transistor 404 (for example, corresponding to the gate electrode 220) may be coupled to a word line 204, one of the source and drain of transistor 404 may be coupled to ground, the other of the source and drain of transistor 404 may be coupled to one electrode of the PCM element 406, and the other electrode of the PCM element 406 may be coupled to a bit line 206.

[0074] Figure 5 shows a schematic perspective view of a memory device 200 according to several embodiments of the present disclosure. As shown in Figure 5, the memory device 200 includes a memory cell array 201 and peripheral circuits 202 coupled to the memory cell array 201. A number of interconnects (e.g., bonding contacts) may be formed through a bonding boundary 106 to establish direct, short-distance (e.g., micron-level) electrical connections between the memory cell array 201 and the peripheral circuits 202. Interconnections may be formed at the bonding boundary 106 to bond the two wafers together during the wiring-end-of-life (BEOL) process of a first semiconductor structure 102 including the peripheral circuits 202 and a second semiconductor structure 104 including the memory cell array 201. In some implementations, the conductive layers of the conductive layers of the word lines 204 and bit lines 206 of the memory cell array 201, such as metal layers, may be connected to a word line driver (WLD), a sense amplifier (SA), and other related circuits of the peripheral circuits 202 through interconnections formed at the bonding boundary 106.

[0075] Figure 6 shows a schematic plan view of a memory device 600 according to several aspects of the present disclosure. As shown in Figure 6, the memory device 600 may include one or more memory array structures 602, for example, memory dies. Each memory array structure 602 may include a plurality of memory banks 604. For example, as shown in Figure 6, the memory array structure 602 may include eight memory banks 604. Each memory bank 604 may include a plurality of memory blocks 606. For example, as shown in Figure 6, the memory bank 604 may include (n × m) memory blocks 606.

[0076] In some implementations, the memory device 600 may further include a plurality of peripheral structures 612. In some implementations, each peripheral structure 612 may include at least one word line driver circuit (WLD circuit) 614 and at least one sense amplifier circuit (SA circuit) 616. In some implementations, as shown in Figure 6, the peripheral structure 612 may include one WLD circuit 614 and two SA circuits 616. Note that in Figure 6, the memory block 606 and peripheral structures 612 are shown side by side to illustrate the size of the area covered by the memory block 606 and peripheral structures 612. However, in actual structures, in a plan view of the memory device 600, the memory block 606 and peripheral structures 612 may overlap each other at least partially. In some implementations, the memory block 606 and peripheral structures 612 are formed separately on two different wafers or substrates and joined to each other with a relationship of at least partial overlap. In some implementations, the memory block 606 and peripheral structures 612 may completely overlap each other.

[0077] In some implementations, peripheral structures 612 are formed on the first wafer, and one peripheral structure 612 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, memory blocks 606 are formed on the second wafer, and one memory block 606 occupies a second area on the second wafer in a plan view of the second wafer. After the first wafer is bonded to the second wafer, the first area including the WLD circuit 614 and SA circuit 616 at least partially overlaps with the second area including the memory block 606 in a plan view of the memory device 600. In some implementations, the first area may include a first sub-area having one WLD circuit 614 and two second sub-areas each having one SA circuit 616. In some implementations, the two second sub-areas may be located on two sides of the first sub-area. In other words, as shown in Figure 6, the two SA circuits 616 can be arranged on two sides of a single WLD circuit 614.

[0078] In some implementations, when a memory block 606 contains M word lines and N bit lines, a WLD circuit 614 may be used to control the M word lines in the corresponding memory block 606, and each SA circuit 616 located on one side of the WLD circuit 614 may be used to control N / 2 bit lines in the corresponding memory block 606. In some implementations, an SA circuit 616 may be shared by two adjacent memory blocks 606, and one SA circuit 616 may be used to control the odd-numbered or even-numbered bit lines in the two adjacent memory blocks 606.

[0079] Figure 7 shows a schematic diagram of the arrangement of the memory device 600 according to several embodiments of the present disclosure. As shown in Figure 7, SA circuit 616 includes SA circuit 616a and SA circuit 616b. SA circuit 616a may be used to control the even-numbered bit lines in memory blocks 606a and 606b. As shown in Figure 7, SA circuit 616a includes two outputs, one output connected to the even-numbered bit lines of memory block 606a and the other output connected to the even-numbered bit lines of memory block 606b which is above memory block 606a in the X direction and adjacent to memory block 606a. Similarly, in some implementations, SA circuit 616b includes two outputs, one output connected to the odd-numbered bit lines of memory block 606a and the other output connected to the odd-numbered bit lines of memory block 606c which is below memory block 606a in the X direction and adjacent to memory block 606a.

[0080] In some implementations, the WLD circuit 614 may further include WLD circuits 614a and 614b. In some implementations, the WLD circuit 614a may be used to control even-numbered word lines in memory block 606a, and the WLD circuit 614b may be used to control odd-numbered word lines in memory block 606a. In some implementations, the WLD circuit 614a may be shared by memory block 606a and an adjacent memory block (not shown) located to the left of memory block 606a, and the WLD circuit 614b may be shared by memory block 606a and another adjacent memory block (not shown) located to the right of memory block 606a. In some implementations, WLD circuit 614a may be used to control even-numbered word lines in memory block 606a and even-numbered word lines in adjacent memory blocks, and WLD circuit 614b may be used to control odd-numbered word lines in memory block 606a and odd-numbered word lines in other adjacent memory blocks.

[0081] In other words, the SA circuit 616, which includes SA circuits 616a and 616b, and the WLD circuit 614, which includes WLD circuits 614a and 614b, may be arranged in memory blocks 606a that partially overlap or that completely overlap. Furthermore, the SA circuit 616 and the WLD circuit 614 may control only memory block 606a, or they may control memory block 606a together with memory blocks adjacent in the X and / or Y directions.

[0082] Figure 7 further illustrates schematic diagrams of word line routing and bit line routing. As shown in Figure 7, word line routing may include both horizontal (Y direction) and vertical (X direction), while bit line routing may include only the vertical direction.

[0083] Figure 8 shows a schematic diagram of a WLD circuit 614 of a memory device 600 according to several embodiments of the present disclosure, and Figure 9 shows a schematic diagram of an SA circuit 616 of a memory device 600 according to several embodiments of the present disclosure. The WLD circuits 614 and SA circuits 616 shown in Figures 8 and 9 are for illustrative purposes only, and it should be understood that other designs or structures of the WLD circuits 614 and SA circuits 616 may also be applied to the present applications.

[0084] Figure 10 shows a schematic plan view of a memory device 1000 according to several aspects of the present disclosure. As shown in Figure 10, the memory device 1000 may include one or more memory array structures 1002, for example, memory dies. Each memory array structure 1002 may include a plurality of memory banks 1004. For example, as shown in Figure 10, the memory array structure 1002 may include eight memory banks 1004. Each memory bank 1004 may include a plurality of memory blocks 1006. For example, as shown in Figure 10, the memory bank 1004 may include (n × m) memory blocks 1006.

[0085] In some implementations, the memory device 1000 may further include a plurality of peripheral structures 1012. In some implementations, each peripheral structure 1012 may include at least one word line driver circuit (WLD circuit) 1014 and at least one sense amplifier circuit (SA circuit) 1016. In some implementations, as shown in Figure 10, the peripheral structure 1012 may include two WLD circuits 1014 and two SA circuits 1016. Note that in Figure 10, the memory block 1006 and the peripheral structures 1012 are shown side by side to illustrate the size of the area covered by the memory block 1006 and the peripheral structures 1012. However, in actual applications and actual structures, the memory block 1006 and the peripheral structures 1012 may overlap each other at least partially in the plan view of the memory device 1000. In some implementations, the memory block 1006 and the peripheral structures 1012 are formed separately on two different wafers or substrates and joined to each other with at least a partially overlapping relationship. In some implementations, the memory block 1006 and the peripheral structure 1012 may completely overlap with each other.

[0086] In some implementations, the peripheral structure 1012 is formed on the first wafer, and one peripheral structure 1012 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, the memory block 1006 is formed on the second wafer, and one memory block 1006 occupies a second area on the second wafer in a plan view of the second wafer. After the first wafer is bonded to the second wafer, the first area including the WLD circuit 1014 and SA circuit 1016 at least partially overlaps with the second area including the memory block 1006 in a plan view of the memory device 1000. In some implementations, the first area may include two first sub-areas, each having one WLD circuit 1014, and two second sub-areas, each having one SA circuit 1016. In some implementations, as shown in Figure 10, the first and second sub-areas are arranged alternately within the first area. In other words, as shown in Figure 10, the first area (peripheral structure 1012) includes two first sub-areas (WLD circuits 1014) and two second sub-areas (SA circuits 1016), with the two first sub-areas located at diagonal corners within the first area and the two second sub-areas located at diagonal corners within the first area.

[0087] In some implementations, when a memory block 1006 contains M word lines and N bit lines, one WLD circuit 1014 may be used to control M / 4 word lines in the corresponding memory block 1006, and one SA circuit 1016 may be used to control N / 2 bit lines in the corresponding memory block 1006. In some implementations, the SA circuit 1016 may be shared by two adjacent memory blocks 1006, and one SA circuit 1016 may be used to control odd-numbered or even-numbered bit lines in the two adjacent memory blocks 1006. In some implementations, as shown in Figure 11, the WLD circuit 1014 may be shared by two adjacent memory blocks 1006, and one WLD circuit 1014 may be used to control odd-numbered or even-numbered word lines in the two adjacent memory blocks 1006. In some implementations, the WLD circuit 614 and SA circuit 616 shown in Figures 8 and 9 can also be applied to the memory device 1000.

[0088] Figure 11 shows a schematic diagram of the arrangement of the memory device 1000 according to several aspects of the present disclosure. As shown in Figure 11, memory blocks 1006a and 1006b are two adjacent memory blocks. WLD circuit 1014a is located on a peripheral wafer, for example, a CMOS wafer, corresponding to the location of memory block 1006a on the memory array wafer. WLD circuit 1014a provides corresponding signals to the odd-numbered word lines (WL1, WL3, WL5, and WL7) of the two memory blocks 1006a and 1006b. WLD circuit 1014b is located on a peripheral wafer, for example, a CMOS wafer, corresponding to the location of memory block 1006b on the memory array wafer. WLD circuit 1014b provides corresponding signals to the even-numbered word lines (WL2, WL4, WL6, and WL8) of the two memory blocks 1006a and 1006b. It should be understood that the number of word lines or word line drivers in each WLD circuit 1014 is for illustrative purposes only, and the actual routing pattern may differ.

[0089] Figure 12 shows a schematic diagram of an SA circuit 1016 of a memory device 1000 according to several embodiments of the present disclosure. As shown in Figure 12, one SA circuit 1016 may include a plurality of sense amplifiers 1022, at least one sense amplifier driver 1024, and at least one decoder and control logic 1026. In some implementations, the SA circuit 1016 may control only one memory block, for example, memory block 1006a. In some implementations, two SA circuits 1016 in a peripheral structure 1012 may each control N / 2 bit lines of memory block 1006.

[0090] Figure 13 shows a schematic plan view of a memory device 1300 according to several aspects of the present disclosure. As shown in Figure 13, the memory device 1300 may include one or more memory array structures 1302, for example, memory dies. Each memory array structure 1302 may include a plurality of memory banks 1304. For example, as shown in Figure 13, the memory array structure 1302 may include eight memory banks 1304. Each memory bank 1304 may include a plurality of memory blocks 1306. For example, as shown in Figure 13, the memory bank 1304 may include (n × m) memory blocks 1306.

[0091] In some implementations, the memory device 1300 may further include a plurality of peripheral structures 1312. In some implementations, each peripheral structure 1312 may include at least one word line driver circuit (WLD circuit) 1314 and at least one sense amplifier circuit (SA circuit) 1316. In some implementations, as shown in Figure 13, the peripheral structure 1312 may include one WLD circuit 1314 and two SA circuits 1316. Note that in Figure 13, the memory block 1306 and the peripheral structures 1312 are shown side by side to illustrate the size of the area covered by the memory block 1306 and the peripheral structures 1312. However, in actual applications and actual structures, the memory block 1306 and the peripheral structures 1312 may overlap each other at least partially in a plan view of the memory device 1300. In some implementations, the memory block 1306 and the peripheral structures 1312 are formed separately on two different wafers or substrates and joined to each other with at least a partially overlapping relationship.

[0092] In some implementations, the peripheral structure 1312 is formed on the first wafer, and one peripheral structure 1312 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, the memory block 1306 is formed on the second wafer, and one memory block 1306 occupies a second area on the second wafer in a plan view of the second wafer. After the first wafer is bonded to the second wafer, the first area including the WLD circuit 1314 and SA circuit 1316 at least partially overlaps with the second area including the memory block 1306 in a plan view of the memory device 1300. In some implementations, the first area may include one first sub-area having one WLD circuit 1314 and two second sub-areas each having one SA circuit 1316. In some implementations, a first sub-area having one WLD circuit 1314 may be located between two adjacent memory blocks 1306. In some implementations, the first sub-area may not overlap with a second area having memory blocks 1306. In some implementations, a second sub-area, each having one SA circuit 1316, may at least partially overlap with a second area having memory blocks 1306. In some implementations, the second sub-area may completely overlap with a second area having memory blocks 1306. In some implementations, an SA circuit 1316 may be shared by two adjacent memory blocks 1306, and one SA circuit 1316 may be used to control odd-numbered or even-numbered bit lines in the two adjacent memory blocks 1306. For example, the SA circuit 1316 may include two outputs, one of which is connected to the even-numbered bit lines of memory block 1306, and the other output is connected to the even-numbered bit lines of memory blocks adjacent to memory block 1306 in the X direction. In some implementations, the WLD circuit 614 and SA circuit 616 shown in Figures 8 and 9 can also be applied to memory device 1300.

[0093] In some implementations, the WLD circuit 1314 is located on a peripheral wafer, such as a CMOS wafer, corresponding to the position between two memory blocks 1306 on the memory array wafer. In some implementations, the WLD circuit 1314 provides the corresponding signal to the odd-numbered or even-numbered word lines of the two adjacent memory blocks 1306. For example, the WLD circuit 1314 may provide the corresponding signal to the odd-numbered word lines of the two adjacent memory blocks 1306.

[0094] In some implementations, the peripheral structure 1312 may further include a connection circuit 1318 containing a control circuit for the SA circuit 1316. Figure 14 shows a schematic diagram of the connection circuit 1318 of the memory device 1300 according to some aspects of the present disclosure. In some implementations, the connection circuit 1318 occupies a third sub-area within a first area. In some implementations, the third sub-area is located between the second sub-areas. In some implementations, the connection circuit 1318 may include at least three parts, including a data line circuit (DL / LDL circuit) 1322 for transmitting data out from the bit lines to the data lines, a switch circuit 1324 for generating switching voltages and control timing sequences for switching operation, and a sense amplifier driver (SA driver) 1326 for generating SA-related control signals. The DL / LDL circuit 1322, switch circuit 1324, and SA driver 1326 shown in Figure 14 are for illustrative purposes only, and it should be understood that other circuit structures may also be applicable to the present applications.

[0095] Figure 15 shows a schematic plan view of a memory device 1500 according to several aspects of the present disclosure. As shown in Figure 15, the memory device 1500 may include one or more memory array structures 1502, for example, memory dies. Each memory array structure 1502 may include a plurality of memory banks 1504. For example, as shown in Figure 15, the memory array structure 1502 may include eight memory banks 1504. Each memory bank 1504 may include a plurality of memory blocks 1506. For example, as shown in Figure 15, the memory bank 1504 may include (n × m) memory blocks 1506.

[0096] In some implementations, the memory device 1500 may further include multiple peripheral structures 1512. In some implementations, each peripheral structure 1512 may include at least one word line driver circuit (WLD circuit) 1514 and at least one sense amplifier circuit (SA circuit) 1516. In some implementations, as shown in Figure 15, the peripheral structure 1512 may include one WLD circuit 1514 and one SA circuit 1516. Note that in Figure 15, the memory block 1506 and the peripheral structures 1512 are shown side by side to illustrate the size of the area covered by the memory block 1506 and the peripheral structures 1512. However, in actual applications and actual structures, the memory block 1506 and the peripheral structures 1512 may overlap each other at least partially in the plan view of the memory device 1500. In some implementation configurations, the memory block 1506 and the peripheral structure 1512 are formed separately on two different wafers or substrates and joined to each other with at least partial overlap.

[0097] In some implementations, the peripheral structure 1512 is formed on the first wafer, and one peripheral structure 1512 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, the memory block 1506 is formed on the second wafer, and one memory block 1506 occupies a second area on the second wafer in a plan view of the second wafer. After the first wafer is bonded to the second wafer, the first area including the WLD circuit 1514 and SA circuit 1516 at least partially overlaps with the second area including the memory block 1506 in a plan view of the memory device 1500. In some implementations, the first area may include one first sub-area having one WLD circuit 1514 and one second sub-area each having one SA circuit 1516. In some implementations, a first sub-area having one WLD circuit 1514 may be located between two adjacent memory blocks 1506. In some implementations, the first sub-area may not overlap with a second area having a memory block 1506. In some implementations, a second sub-area having one SA circuit 1516 may at least partially overlap with a second area having a memory block 1506. In some implementations, the second sub-area may completely overlap with a second area having a memory block 1506. In some implementations, the WLD circuit 614 and SA circuit 616 shown in Figures 8 and 9 may also be applied to a memory device 1500.

[0098] Figure 16 shows a schematic plan view of a peripheral structure 1512 according to several embodiments of the present disclosure. In some implementations, the WLD circuit 1514 is located on a peripheral wafer, such as a CMOS wafer, corresponding to the position between two memory blocks 1506 on the memory array wafer. In some implementations, the WLD circuit 1514 provides the corresponding signal to the odd-numbered or even-numbered word lines of two adjacent memory blocks 1506. For example, as shown in Figures 15 and 16, an odd-numbered WLD circuit 1514 may provide the corresponding signal to the odd-numbered word lines of two adjacent memory blocks 1506, and an even-numbered WLD circuit 1514 may provide the corresponding signal to the even-numbered word lines of two adjacent memory blocks 1506.

[0099] In some implementations, the peripheral structure 1512 may further include a connection circuit 1518. In some implementations, the connection circuit 1518 occupies a third sub-area within the first area. In some implementations, the third sub-area is located next to the first sub-area. In some implementations, the connection circuit 1318 shown in Figure 14 may also be applied to the memory device 1500.

[0100] In some implementations, the peripheral structure 1512 may further include a decoder and control logic 1520. Figure 16 shows a schematic diagram of the decoder and control logic 1520 of the memory device 1500 according to some aspects of this disclosure. In some implementations, the decoder and control logic 1520 may decode the address of the word line in the Y direction. The decoder and control logic 1520 shown in Figure 16 are for illustrative purposes only, and it should be understood that other circuit structures may also be applied to the present applications.

[0101] By using memory devices 600, 1000, 1300, or 1500, the memory array and peripheral circuits of the memory device can be formed on two different wafers and then bonded together. In this way, the WLD circuitry, SA circuitry, connection circuitry, and / or peripheral circuits including decoders and control logic can be hidden beneath the memory array. Thus, the size of the memory devices 600, 1000, 1300, or 1500 can be reduced, and array efficiency can also be improved.

[0102] Figure 18 shows a flowchart of a method 1800 for forming a memory device according to several aspects of the present disclosure. As shown in operation 1802 of Figure 18, the memory array structure is formed on a first substrate, for example, a first wafer. The memory array structure may include at least one memory bank, each memory bank may include multiple memory blocks. In some implementations, the memory array structure may use transistors as switch and select devices. In some implementations, the memory array structure includes an array of DRAM cells. For simplicity of explanation, a DRAM cell array may be used in this disclosure as an example to illustrate a memory cell array. However, it will be understood that a memory cell array is not limited to a DRAM cell array and may include any other suitable type of memory cell array that may use transistors as switch and select devices, such as PCM cell arrays, SRAM cell arrays, FRAM® cell arrays, resistive memory cell arrays, magnetic memory cell arrays, STT memory cell arrays, or any combination thereof.

[0103] In some implementations, each DRAM cell includes a capacitor for storing data bits as positive or negative charge, as well as one or more transistors (also known as pass transistors) that control access to it (e.g., switching and selection). In some implementations, each DRAM cell is a 1-transistor 1-capacitor (1T1C) cell. Since transistors constantly leak small amounts of charge, capacitors slowly discharge, and the stored information is lost. Therefore, to retain data, DRAM cells must be refreshed, for example, by peripheral circuitry.

[0104] As shown in operation 1804 of Figure 18, the peripheral structure having peripheral circuits is formed on a second substrate different from the first substrate, for example, a second wafer. The peripheral structure may include word line driver circuits and sense amplifier circuits. In some implementations, the peripheral circuits (also known as control and sense circuits) may include any suitable digital circuits, analog circuits, and / or mixed-signal circuits used to assist the operation of the memory cell array. For example, the peripheral circuits may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuits, charge pumps, voltage sources or generators, current or voltage references, any part of the functional circuits mentioned above (e.g., subcircuits), or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). According to several implementation configurations, peripheral circuits on the second substrate use CMOS technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0105] As shown in operation 1806 of Figure 18, the memory array structure and peripheral structure are joined to have a word line driver circuit, and the sense amplifier circuit at least partially overlaps with the memory block in the plan view of the memory device.

[0106] In some implementations, the word line driver circuit is formed on a second substrate within a first sub-area, and the sense amplifier circuit is formed on a second substrate within a second sub-area. In some implementations, as shown in Figure 10, the first and second sub-areas are located at diagonal corners of the memory block in a plan view of the memory device.

[0107] In some implementations, the word line driver circuit is formed on the second substrate within the first sub-area, and the sense amplifier circuit is formed on the second substrate within the second and third sub-areas. In some implementations, as shown in Figure 6, the second and third sub-areas are located on two sides of the first sub-area in the plan view of the memory device.

[0108] In some implementations, as shown in Figure 13, the first sub-area is located between adjacent memory blocks in the plan view of the memory device, while the second and third sub-areas are located overlapping with memory blocks in the plan view of the memory device.

[0109] In some implementations, the word line driver circuit is formed on a second board within a first sub-area, the sense amplifier circuit is formed on a second board within a second sub-area, and the decoder circuit is formed on a second board within a third sub-area. In some implementations, as shown in Figure 15, the first sub-area is located between adjacent memory blocks in the plan view of the memory device, and the second and third sub-areas are located overlapping with the memory blocks in the plan view of the memory device.

[0110] Figure 19 shows a block diagram of a system 1900 having a memory device according to several aspects of the present disclosure. System 1900 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage. As shown in Figure 19, system 1900 may include a host 1908 and a memory system 1902 having one or more memory devices 1904 and a memory controller 1906. The host 1908 may be a processor of an electronic device such as a central processing unit (CPU), or a system on a chip (SoC) such as an application processor (AP). The host 1908 may be configured to send data to or receive data from the memory device 1904.

[0111] The memory device 1904 may be any memory device disclosed herein, such as memory device 600, 1000, 1300, or 1500. In some implementations, as described in detail above, the memory device 1904 includes an array of memory cells, each containing a vertical transistor.

[0112] In some implementations, the memory controller 1906 is coupled to the memory device 1904 and the host 1908 and configured to control the memory device 1904. The memory controller 1906 can manage the data stored in the memory device 1904 and communicate with the host 1908. The memory controller 1906 may be configured to control the operation of the memory device 1904, such as read, write, and refresh operations. The memory controller 1906 may also be configured to manage various functions with respect to the data stored or to be stored in the memory device 1904, including, but not limited to, refresh and timing control, command / request translation, buffering and scheduling, and power management. In some implementations, the memory controller 1906 is further configured to determine the maximum memory capacity available to the computer system, the number of memory banks, the type and speed of the memory, the data depth and data width of the memory particles, and other important parameters. Any other appropriate functions may also be performed by the memory controller 1906. The memory controller 1906 can communicate with an external device (for example, the host 1908) according to a specific communication protocol. For example, the memory controller 1906 can communicate with an external device through at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0113] The above description of a particular implementation can be readily modified and / or adapted to various applications. Such adaptations and modifications, based on the teachings and guidance presented herein, should be within the scope of the meaning and equivalents of the disclosed implementations. The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the following claims and their equivalents. [Explanation of Symbols]

[0114] 100 memory devices 101 Memory Devices 102 First Semiconductor Structure 104 Second Semiconductor Structure 106 Bonding boundary 200 memory devices 201 Memory Cell Array 202 Peripheral Circuits 204 Word lines 206-bit line 208 memory cells 210 Vertical Transistors 212 memory units 214 Semiconductor main body 216 Gate Structure 218 Gate Dielectric 220 gate 302 DRAM cells 304 transistors 306 Capacitors 402 PCM cells 404 transistors 406 PCM elements 600 memory devices 602 Memory Array Structure 604 Memory Bank 606 memory blocks 612 Peripheral structure 614 WLD circuit 616 SA Circuit 1000 memory devices 1002 Memory Array Structure 1004 Memory Bank 1006 memory blocks 1012 Peripheral structure 1014 WLD circuit 1016 SA Circuit 1022 SenseAmp 1024 Sense Amp Driver 1026 Decoder and control logic 1300 memory devices 1302 Memory Array Structure 1304 Memory Bank 1306 memory blocks 1312 Surrounding structure 1314 WLD circuit 1316 Sense Amplifier Circuit 1318 Connection Circuit 1322 Data Line Circuit 1324 Switch Circuit 1326 Sense Amp Driver 1500 memory devices 1502 Memory Array Structure 1504 Memory Bank 1506 memory blocks 1512 Surrounding structure 1514 WLD circuit 1516 SA Circuit 1518 Connection Circuit 1520 Decoder and Control Logic 1900 System 1902 Memory System 1904 Memory Device 1906 Memory Controller 1908 Host

Claims

1. A memory device, A memory array structure having vertical transistors and at least one memory bank, wherein each memory bank comprises multiple memory blocks, It includes a peripheral structure comprising a word line driver circuit and a sense amplifier circuit, The first area comprises the word line driver circuit and the sense amplifier circuit, and the second area comprises the memory block. The word line driver circuit and the sense amplifier circuit overlap at least partially with the memory block in the plan view of the memory device. A memory device in which the first area completely overlaps with the second area in the plan view of the memory device.

2. The memory device according to claim 1, wherein the first area comprises a first sub-area having the word line driver circuit and a second sub-area having the sense amplifier circuit, and the first sub-area and the second sub-area are alternately arranged in the first area.

3. The memory device according to claim 2, wherein the first area comprises two first sub-areas and two second sub-areas, the two first sub-areas being located at diagonal corners in the first area and the two second sub-areas being located at diagonal corners in the first area.

4. The memory device according to claim 3, wherein the word line driver circuit in one of the two first sub-areas is coupled to an odd-numbered word line in the memory block, and the word line driver circuit in the other of the two first sub-areas is coupled to an even-numbered word line in the memory block.

5. The memory device according to claim 1, wherein the first area comprises a first sub-area having the word line driver circuit and two second sub-areas each having the sense amplifier circuit, and the two second sub-areas are arranged on two sides of the first sub-area.

6. A memory device, A memory array structure having at least one memory bank, wherein each memory bank has multiple memory blocks, It includes a peripheral structure comprising a word line driver circuit and a sense amplifier circuit, The first area comprising the word line driver circuit and the sense amplifier circuit at least partially overlaps with the second area comprising the memory block in the plan view of the memory device. A memory device wherein the first area comprises a first sub-area having the word line driver circuit, a second sub-area having the sense amplifier circuit, and a third sub-area having the decoder circuit, the first sub-area being arranged between adjacent memory blocks in the plan view of the memory device, and the second and third sub-areas overlapping with the second area of ​​the memory block in the plan view of the memory device.

7. The memory device according to claim 6, wherein the first area further comprises a fourth sub-area comprising a control circuit for the sense amplifier circuit, and the fourth sub-area is disposed between the second sub-area and the third sub-area.

8. The memory device according to claim 7, wherein the second sub-area, the third sub-area, and the fourth sub-area overlap with the second area of ​​the memory block in the plan view of the memory device.

9. A memory device, A memory array structure having at least one memory bank, wherein each memory bank has multiple memory blocks, It includes a peripheral structure comprising a word line driver circuit and a sense amplifier circuit, The first area comprising the word line driver circuit and the sense amplifier circuit at least partially overlaps with the second area comprising the memory block in the plan view of the memory device. The first area comprises a first sub-area comprising the word line driver circuit and two second sub-areas each comprising the sense amplifier circuit, the first sub-area being arranged between adjacent memory blocks in the plan view of the memory device, and the two second sub-areas overlapping with the second area of ​​the memory block in the plan view of the memory device. A memory device wherein the first area further comprises a third sub-area having a control circuit for the sense amplifier circuit, and the third sub-area is disposed between the two second sub-areas.

10. A memory device, A memory array structure disposed on a first substrate having at least one memory bank, wherein each memory bank comprises multiple memory blocks, The system comprises a sense amplifier circuit and a word line driver circuit, and a peripheral structure disposed on a second board different from the first board, the second board having these components. The sense amplifier circuit overlaps with the memory block in the plan view of the memory device. The word line driver circuit is arranged between adjacent memory blocks in the plan view of the memory device. A memory device wherein the peripheral structure further comprises a decoder circuit that overlaps with the memory block in the plan view of the memory device.

11. A method for forming a memory device, A step of forming a memory array structure on a first substrate, wherein the memory array structure has vertical transistors, comprises at least one memory bank, and each memory bank comprises a plurality of memory blocks, A step of forming a peripheral structure on a second substrate different from the first substrate, wherein the peripheral structure comprises a word line driver circuit and a sense amplifier circuit. A method comprising the step of joining the memory array structure and the peripheral structure such that the word line driver circuit and the sense amplifier circuit at least partially overlap with the memory block in a plan view of the memory device.

12. The step of forming the peripheral structure on the second substrate is, The method according to claim 11, comprising the step of forming the word line driver circuit in a first sub-area and the sense amplifier circuit in a second sub-area.

13. The step of forming the peripheral structure on the second substrate is, The method according to claim 11, comprising the step of forming the word line driver circuit in the first sub-area and the sense amplifier circuits in the second and third sub-areas.

14. A method for forming a memory device, A step of forming a memory array structure on a first substrate, wherein the memory array structure comprises at least one memory bank, and each memory bank comprises a plurality of memory blocks. A step of forming a peripheral structure on a second substrate different from the first substrate, wherein the peripheral structure comprises a word line driver circuit and a sense amplifier circuit. The step of joining the memory array structure and the peripheral structure such that the word line driver circuit and the sense amplifier circuit at least partially overlap with the memory block in the plan view of the memory device, The step of forming the peripheral structure on the second substrate is, A method comprising the steps of forming the word line driver circuit in a first sub-area, the sense amplifier circuit in a second sub-area, and the decoder circuit in a third sub-area.

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