Dynamic lane allocation on power-limited dual-port PCIe devices

Abstract

To provide a data storage device that moves a part of a plurality of lanes to a low power state.SOLUTION: In the storage system 100, the data storage device comprises a memory device and a controller coupled to the memory device. The controller requests to move one or more first lanes of a first MAD (MemoryAccessController) from a low power state to a fully operational state, requests to move one or more second lanes of a second MAD separate from the first MAD from the fully operational state to the low power state, and moves the one or more second lanes of the second MAD to the low power state; The one or more first lanes of the first MAC and the one or more second lanes of the second MAC are the same lanes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (Field of the Invention) Embodiments of the present disclosure generally relate to effective utilization of multi-port systems.

[0002] (Cross-Reference to Related Applications) Some nonvolatile memory (NVM) express (NVMe) devices support two peripheral component interconnect (PCI) express (PCIe) ports. Each port has one or more lanes. Each lane consumes a certain amount of power and area (i.e., cost) and provides a given amount of bandwidth. For a 6-lane 2-port device, several configurations are possible.

[0003] One configuration is having a first port with four lanes and a second port with two lanes. The other option is having a first port with two lanes and a second port with four lanes. While the device can support six lanes, the data storage device has only two options.

[0004] A first option is having a total of eight lanes, four for each port, and activating only six lanes at any given time. Such an option wastes area and cost. Another option is having one 4-lane port and one 6-lane port. With that option, the port with six lanes needs to drop the link and reconnect when a new configuration occurs. Such an option wastes bandwidth. Accordingly, multi-port systems have considerable inefficiencies.

[0005] Therefore, in this technical field, there is a need to improve the efficiency of multiport systems. [Overview of the project]

[0006] Rather than having more lanes than the bus can support, the number of lanes can be matched to the number of lanes the bus can support. In the case of a 6-lane, 2-port system, this means that each port has two fixed lanes and two lanes shared with the other port. When changing the configuration from four lanes on the first port to four lanes on the second port, the shared lanes are placed in a low-power phase from the perspective of the first port and moved to a full-operation phase for the second port. Thus, each port can be thought of as having four lanes for the port and a total of eight lanes for the device. However, in reality, there are only six lanes in total for the device, thus saving costs and matching the bandwidth and power limits of the device.

[0007] In one embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, wherein the controller is configured to request that one or more first lanes of a first MAC be moved from a low-power state to a fully operational state, to request that one or more second lanes of a second MAC, which is separate from the first MAC, be moved from a fully operational state to a low-power state, to move one or more second lanes of the second MAC to a low-power state, and to move one or more first lanes of the first MAC, where one or more first lanes and one or more second lanes are the same lane, to a fully operational state.

[0008] In another embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, the controller managing a plurality of lane connections between a plurality of MACs and a plurality of host devices, wherein one or more first lane connections of the plurality of lane connections exist for the first MAC of the plurality of MACs, one or more second lane connections of the plurality of lane connections exist for the second MAC of the plurality of MACs, and one or more third lane connections of the plurality of lane connections are shared by the first MAC and the second MAC, the controller being configured to cause the first MAC to register one or more third lane connections as being in a low-power state, and the second MAC to register one or more third lane connections as being in a fully operational state, while the second MAC registers one or more third lane connections as being in a fully operational state, and the first MAC is configured to register one or more third lane connections as being in a low-power state.

[0009] In another embodiment, the data storage device comprises means for storing data and a controller coupled to the means for storing data, the controller being configured to maintain a PHY having a first plurality of lanes, a first MAC having a second plurality of lanes, wherein the first plurality is greater than the second plurality, a second MAC having a third plurality of lanes, wherein the first plurality is greater than the third plurality, and to switch between a low-power state and a full-operation state for the shared lanes by the first MAC and the second MAC. [Brief explanation of the drawing]

[0010] A more detailed description of the Disclosure, which is concisely summarized above, may be obtained by reference to embodiments, some of which are shown in the accompanying drawings, so that the above-mentioned features of the Disclosure may be understood in detail. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and should not be considered to limit its scope, as the Disclosure may allow for other equally valid embodiments. [Figure 1] This is a schematic block diagram showing a storage system in which, according to a particular embodiment, a data storage device may function as a storage device for a host device. [Figure 2] This is a schematic diagram of a 12-lane system according to one embodiment. [Figure 3] This is a schematic diagram of a 4-lane system according to one embodiment. [Figure 4] This is a schematic diagram of a 6-lane system according to one embodiment. [Figure 5] This flowchart shows the transition from the first 6-lane configuration to the second 6-lane configuration. [Figure 6] This is a schematic diagram of a multiport system according to one embodiment.

[0011] For ease of understanding, the same reference numerals are used to designate identical elements common to the drawings, where possible. Elements disclosed in one embodiment are intended to be usefully utilized in other embodiments without specific description. [Modes for carrying out the invention]

[0012] The following refers to embodiments of the Disclosure. However, it should be understood that the Disclosure is not limited to any specific embodiment described. Instead, any combination of the following features and elements, whether related to a different embodiment or not, is intended to implement and practice the Disclosure. Furthermore, embodiments of the Disclosure may achieve advantages over other possible solutions and / or prior art, but whether a particular advantage is achieved by a given embodiment does not limit the Disclosure. Accordingly, the following aspects, features, embodiments, and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims. Similarly, references to “the Disclosure” shall not be construed as a generalization of the subject matter of any invention disclosed herein and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims.

[0013] Rather than having more lanes than the bus can support, the number of lanes can be matched to the number of lanes the bus can support. In the case of a 6-lane, 2-port system, this means that each port has two fixed lanes and two lanes shared with the other port. When changing the configuration from four lanes on the first port to four lanes on the second port, the shared lanes are placed in a low-power phase from the perspective of the first port and moved to a full-operation phase for the second port. Thus, each port can be thought of as having four lanes for the port and a total of eight lanes for the device. However, in reality, there are only six lanes in total for the device, thus saving costs and matching the bandwidth and power limits of the device.

[0014] Figure 1 is a schematic block diagram showing a storage system 100 having a data storage device 106 which may function as a storage device for a host device 104 according to a particular embodiment. For example, the host device 104 may store and retrieve data using non-volatile memory (NVM) 110 contained in the data storage device 106. The host device 104 includes host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, which may operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID) that collectively function as a high-capacity storage device for the host device 104.

[0015] The host device 104 may store data in and / or retrieve data from one or more storage devices, such as the data storage device 106. As shown in Figure 1, the host device 104 may communicate with the data storage device 106 via the interface 114. The host device 104 may include any of a wide range of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" pad, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other devices capable of sending or receiving data from a data storage device.

[0016] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 allocated to the data storage device 106 for exclusive use by the controller 108. For example, the controller 108 may store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, etc., in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would normally be stored in the controller 108's internal memory, such as volatile memory 112, buffers 116, or static random access memory (SRAM). In an example where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 may use the HMB 150 as the DRAM for the data storage device 106.

[0017] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and an optional DRAM 118. In some examples, the data storage device 106 may include additional components not shown in Figure 1 for clarity. For example, the data storage device 106 may include a printed circuit board (PCB) on which the components of the data storage device 106 are mechanically mounted and which includes conductive traces that electrically interconnect the components such as the data storage device 106. In some examples, the physical dimensions and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., HDD or SSD), 2.5-inch data storage devices, 1.8-inch data storage devices, peripheral component interconnect (PCI), PCI-extended (PCI-X), and PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe MiniCard, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled to the motherboard of the host device 104 (e.g., directly soldered or plugged into a connector).

[0018] Interface 114 may include one or both of the following: a data bus for exchanging data with the host device 104, and a control bus for exchanging commands with the host device 104. Interface 114 may operate according to any preferred protocol. For example, interface 114 may operate according to one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, cache-coherent interface accelerator (CCIX), open channel SSD (OCSSD), etc. Interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108 to provide an electrical connection between the host device 104 and the controller 108, enabling data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of interface 114 may also allow a data storage device 106 to receive power from the host device 104. For example, as shown in Figure 1, a power supply 111 may receive power from the host device 104 via interface 114.

[0019] The NVM110 may include multiple memory devices or memory units. The NVM110 may be configured to store and / or retrieve data. For example, a memory unit of the NVM110 may receive data and messages from controller 108 instructing the memory unit to store the data. Similarly, a memory unit may receive messages from controller 108 instructing the memory unit to retrieve data. In some examples, each of the memory units may be called a die. In some examples, the NVM110 may include multiple dies (i.e., multiple memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0020] In some examples, each memory unit may include any type of non-volatile memory device, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory device.

[0021] The NVM110 may include multiple flash memory devices or memory units. The NVM flash memory devices may include NAND or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, each die containing multiple physical or logical blocks, and the multiple physical or logical blocks may be further divided into multiple pages. Each block of multiple blocks in a particular memory device may contain multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define one of the multiple pages. Each cell in each of the multiple pages may be electrically connected to its respective bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC). The controller 108 may write data to the NVM flash memory device at the page level, read data from the NVM flash memory device, and erase data from the NVM flash memory device at the block level.

[0022] The power source 111 may supply power to one or more components of the data storage device 106. When operating in the standard mode, the power source 111 may use power provided by an external device such as the host device 104 to supply power to one or more components. For example, the power source 111 may use power received from the host device 104 via the interface 114 to supply power to one or more components. In some examples, the power source 111 may include one or more power storage components configured to supply power to one or more components when operating in a shutdown mode, such as when power is no longer received from an external device. In this way, the power source 111 may function as an on-board backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0023] The volatile memory 112 may be used by the controller 108 to store information. The volatile memory 112 may include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 may store cached information in the volatile memory 112 until the cached information is written to the NVM 110. As shown in Figure 1, the volatile memory 112 may consume power received from the power supply 111. Examples of volatile memory 112 include, but are not limited to, random-access memory (RAM), dynamic random-access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, an optional DRAM 118 may be used to store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, etc. In some examples, the data storage device 106 does not include an optional DRAM 118, and is therefore DRAM-less. In other examples, the data storage device 106 includes an optional DRAM 118.

[0024] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage reading of data from the NVM 110 and / or writing of data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate a data storage command for storing data in the NVM 110 and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores data associated with the write command in an internal memory or a write buffer 116 before transmitting the data to the NVM 110. The controller 108 may include a circuit or processor configured to execute a program for operating the data storage device 106.

[0025] The controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be the same as the volatile memory 112. For example, the optional second volatile memory 120 may be SRAM. The controller 108 may allocate a part of the optional second volatile memory to the host device 104 as a controller memory buffer (CMB) 122. The CMB 122 may be directly accessed by the host device 104. For example, instead of maintaining one or more submission queues inside the host device 104, the host device 104 may use the CMB 122 to store one or more submission queues that are normally maintained inside the host device 104. In other words, the host device 104 may generate a command and store the generated command in the CMB 122 with or without associated data, and the controller 108 accesses the CMB 122 to retrieve the stored generated command and / or associated data.

[0026] PCI allows lanes to be turned on and off without rejecting a link. Consider an example with two host devices. Each host device wants to have four ports. Therefore, each host device can support four lanes, but the data storage device only accommodates a total of six lanes. If there are seven or more lanes, the extra lanes serve no purpose and do not improve anything. In fact, extra lanes incur extra costs and consume more power. Therefore, for cost and power reasons, only six lanes are needed.

[0027] To allocate six lanes, four lanes can be allocated to one port and the other two to the other port, but two of the lanes allocated on one port can be switched to the other port. Therefore, each host device sees four lanes, but not simultaneously. Each port can see four lanes, and a data storage device supports six lanes. The controller can dynamically determine which ports require more lanes. This need may be based on bandwidth. A caveat for dynamically adjusting lanes is that any adjustment must be based on a power of two, and note that 1 is a power of two. Therefore, it is not possible to have three or five lanes for a single port. A possible configuration is one port with one lane and another port with four lanes, two lanes, or one lane. Since 5 is not a power of two, a configuration with one lane on one port and five lanes on another is not possible. Six lanes is just an example, and understand that more lanes are intended based on port size and the data storage device capacity. The key point is that the number of lanes can be dynamically increased for each port that requires more bandwidth.

[0028] As mentioned above, some NVMe devices require support for two PCIe ports. This situation can occur in enterprise systems, for example, leading to multiple configurations such as: port A having 4 lanes and port B having 2 lanes; port A having 1 lane and port B having 8 lanes; port A having 4 lanes and port B having 4 lanes, and so on.

[0029] Figure 2 is a schematic diagram of a 12-lane system according to one embodiment. Figure 2 is a high-level diagram of how all of the above examples are supported in a single controller (i.e., port A has 4 lanes and port B has 2 lanes, port A has 1 lane and port B has 8 lanes, port A has 4 lanes and port B has 4 lanes). As shown in Figure 2, there are two hosts, host A and host B, coupled to the controller. The controller is then coupled to a memory device (e.g., NAND). The controller includes a first physical layer (PHY) coupled to host A via a PCIe bus. The first PHY has 4 lanes and is coupled through a pipeline to a 4-lane memory access controller (MAC) (i.e., MAC A). Further components exist for the controller, as indicated by the label "Remaining Controller". The controller also includes a second PHY coupled to host B via a PCIe bus. The second PHY has eight lanes and is connected to an 8-lane MAC (i.e., MAC B) through a pipeline.

[0030] The configuration in Figure 2 allows port A to support all three of the above configurations (i.e., port A has 4 lanes and port B has 2 lanes, port A has 1 lane and port B has 8 lanes, and port A has 4 lanes and port B has 4 lanes), and allows port B to independently support all of the configurations. The configuration in Figure 2 also allows for other configurations, such as any (1, 2, 4 lane) configuration for port A, and separately any (1, 2, 4, 6, or 8 lane) configuration for port B.

[0031] Figure 3 provides a different setup. Figure 3 is a schematic diagram of a 4-lane system according to one embodiment. In the configuration of Figure 3, the PHY supports a total of 4 lanes. In other words, the device supports one port with 4 lanes, or two ports, each with 2 lanes. As shown in Figure 3, there are two hosts, host A and host B, coupled to the controller. The controller is then coupled to a memory device (e.g., NAND). The controller includes a single PHY coupled to hosts A and B via a PCIe bus. The PHY has 4 lanes and is coupled to a pipe mixing module through piping. The pipe mixing module is coupled to a first 4-lane MAC (i.e., MAC A) and a second 4-lane MAC (i.e., MAC B) through a pipeline. Further components exist for the controller, as indicated by the label "Remaining Controller Components".

[0032] For a link (i.e., from the host device to the data storage device MAC) to support four lanes, the link must enumerate four lanes. In Figure 3, the data storage device can operate with either one link of four lanes through either MAC A or MAC B, or with two links of two lanes each for MAC A and MAC B. However, to switch between configurations, the data storage device needs to drop and re-enumerate the link. Starting with PCIe GEN6, each lane can be turned off and on independently without bringing the link down.

[0033] As described above, each lane consumes a specific amount of power, area (e.g., cost), and provides a given amount of bandwidth. Consider the following options: Configuration A: Port A has 4 lanes and Port B has 2 lanes. Configuration B: Port A has 2 lanes and Port B has 4 lanes. A data storage device may be able to support up to 6 lanes (i.e., due to power limitations), but the device has two options. Option 1 is to have 8 lanes (i.e., 4 on each port) and activate only 6 lanes at a given time, but option 1 is a waste of area / cost. Option 2 is to have one 4-lane port and one 6-lane port, and when switching from Configuration A to Configuration B, the data storage device must drop the link and reconnect with the new configuration, but option 2 is a waste of bandwidth. As described herein, embodiments address the problem of dynamically changing the bus width to fit the required bandwidth and power limitations while saving costs.

[0034] Figure 4 focuses on the proposed modifications to the write handler to achieve the desired result. Figure 4 is a schematic diagram of a 6-lane system according to one embodiment. Figure 4 shows a two-host device system in which hosts A and B are coupled to the controller, and the controller is coupled to a memory device (e.g., NAND). The controller has a 6-lane PHY coupled to both hosts A and B via a PCIe bus. The controller also includes a lane management module coupled to the 6-lane PHY via a pipe. The lane management module includes two PHY detaches, one for each host device. The lane management module also includes two MAC detaches, one for each host device. Two MACs also exist, each having four lanes (e.g., MAC A and MAC B) which are respectively coupled to a lane management module via a pipe.

[0035] The basic function of the lane management module is to connect PHY lanes to their respective MACs. For example, in one embodiment, the lane management module connects lanes 0-3 to MAC A and lanes 4 and 5 to MAC B. In another embodiment, the lane management module connects lanes 0 and 1 to MAC A and lanes 2-5 to MAC B. An extended function of the lane management module is to detach lanes from the PIPE interface. For example, the lane management module can be configured to provide two lanes to port A and two lanes to port B (i.e., A2B2, 2 lanes on port A and 2 lanes on port B). Table I below shows the configuration.

[0036] [Table 1]

[0037] In the A2B2 state, each MAC currently uses two active lanes (i.e., fully operational), and each MAC holds two lanes in the L0P state (i.e., low power). However, instead of communicating L0P control to the two PHY lanes, the MAC communicates to two MAC detach logic modules, thereby allowing both MACs to believe that they each hold two PHY lanes. From the MAC side, a total of eight lanes are visible, with four lanes active and four inactive, but in reality, there are only six lanes. On the PHY side, since PHY lanes cannot receive control from two different MACs, the two lanes are kept in L0P by the PHY detach modules.

[0038] A different example is as follows: Port A has 2 lanes and Port B has 4 lanes (A2B4 configuration). Table II shows the configuration.

[0039] [Table 2]

[0040] In the configuration shown in Table II, all PHY lanes are active. MAC B uses all four lanes. MAC A uses two of the four lanes, but the two unused lanes for MAC A are actually communicating with the MAC detach logic.

[0041] When a data storage device decides to switch between an A2B4 configuration and an A4B2 configuration, the data storage device performs the flow described below with respect to Figure 5. The switchover is dynamic.

[0042] Generally speaking, two things happen in parallel. One host device (i.e., host A) wants more bandwidth, and the other host device (i.e., host B) wants less bandwidth. A switchover is performed to accommodate both host A and host B. MAC A wants to move two lanes from low power to full power, and MAC B wants to move two lanes from full power to low power. Figure 5 illustrates how signaling to and from L0 and L0P is performed. Essentially, MAC B detaches these two lanes by moving them to low power. MAC A attaches those same two lanes by moving them to the full operation phase.

[0043] When detaching lanes, operation is still required. MAC A and MAC B are separate. MAC A wants the maximum number of lanes to be active, while MAC B wants only two fewer lanes to be active, with those two lanes in the low-power phase. When detachment occurs, essentially a lie is told to MAC B: the lane is still there, but it is detached. The MAC detach module takes over and informs MAC that the two detached lanes are in the low-power phase and that MAC is unaware that the lanes are actually detached. In this example, MAC B sees the lanes in the low-power phase, but they are actually detached. PHY detach informs the PHY that the two lanes are entering the low-power phase. From MAC A's perspective, the two added lanes were always there, but they were detached. MAC detach relinks the lanes and then moves them into the fully operational phase.

[0044] MAC A's request to move a lane to the fully operational phase cannot be processed until the lane is detached from MAC B. If the lane is still attached to MAC B, there is no power to move the lane to the fully operational phase, so MAC Detach tells MAC A to delay, but the reason there is no power is that the lane is still attached to MAC B, but MAC A is unaware of this. After MAC B releases the two lanes and MAC Detach informs MAC B that those two lanes are in the low-power phase, the lane management module changes the lanes to MAC A.

[0045] In other words, the basic idea in this example is that there are four lanes linked to MAC B and two lanes linked to MAC A, and both MAC A and MAC B want to switch for some reason. So first, MAC B needs to state that MAC B does not need those two lanes, and then the MAC detach module tells MAC B that the lanes are in a low-power phase. Next, using the connection matrix, the lane management module connects these two lanes to MAC A. It should be noted that there may be some time required to release the two lanes, and therefore MAC A may receive notification that the lanes are still in a low-power phase when the lanes have actually detached from MAC A and are still attached to MAC B.

[0046] Figure 5 is a flowchart 500 showing the switch from the first 6-lane configuration to the second 6-lane configuration. Figure 5 illustrates the switch from A2B4 to A4B2. The process begins as block 502, initiating the switch from A2B4 to A4B2. On MAC A, MAC A attempts to change two lanes from L0P to L0 in block 504, and MAC Detach Module A returns L0P in block 506. Simultaneously, MAC B attempts to change two lanes from L0 to L0P in block 514. PHY returns the message "L0P ready" in block 516, and MAC B has two fully operational lanes in block 522. Upon receiving the message, MAC Detach B takes over as block 518, returning the message "L0P ready," and PHY Detach holds two PHY lanes (2, 3) at L0P in block 520. The lane management module connects lanes 2 and 3 to MAC A in block 508, at which point the data storage device is technically in state A4B2 in block 524. Then lanes 2 and 3 synchronize with host A in block 510, and MAC A has four lanes in block 512.

[0047] Three threads run in parallel: MAC A (left), MAC B (right), and the central lane management. First, let's look at MAC B. MAC B requests that two lanes be turned off from L0 to L0P. The PHY returns "L0P ready" to MAC B. MAC B, unaware of this, communicates L0P to the MAC detach logic. Thus, MAC B is in 2-lane mode.

[0048] Next, we look at MAC A. MAC A requests that two lanes be returned from L0P to L0. MAC A receives instructions from MAC detach logic but remains unaware of them, and the PHY state is still L0P. MAC A connects to four PHY lanes, thereby returning that the PHY state is still L0P. PHY lanes 2 and 3, now connected to MAC A, begin to synchronize (CDR lock) themselves. Once complete, MAC A is in the state of four lanes.

[0049] Next, let's look at lane management. The default state of the lane management module (i.e., the state when switching begins) is A2B4, which means that two MAC A lanes are connected to MAC detach logic. The entry point is when PHY lanes 2 and 3 notify MAC-B that they have switched to L0P. Next, MAC B is connected to MAC detach logic. Next, PHY lanes 2 and 3 are connected to PHY detach logic. Next, PHY lanes 2 and 3 are connected to MAC A. The final state is A4B2.

[0050] Figure 6 is a schematic diagram of a multi-port system 600 according to one embodiment. In Figure 6, the endpoint (EP) has five PHY lanes. There are two switches, switch 0 and switch 1, each connected to the EP. There is one host device (RC) which may have two virtual host devices or two separate connections to the EP through the switches. In this example, there are four lanes per virtual host device and per switch. In this example, if one switch fails, the other port still has four lanes. For example, if switch 0 stops working due to failure, instead of being limited to one port, the four ports for switch 1 may be used. Enumeration with four lanes can be done on each port using L0P capability. It is possible to operate with four lanes on switch 0 or four lanes on switch 1, but it is also possible to operate with four lanes + one lane using two ports.

[0051] By adding detach logic, both the PHY and MAC can be tricked into holding onto specific lanes within the L0P, allowing lanes 2 and 3 to move between MAC A and MAC B without disconnecting the link. Then, any two-port configuration can be maintained with only six lanes, totaling six lanes. Thus, the multi-port system exhibits improved efficiency.

[0052] In one embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, wherein the controller is configured to request that one or more first lanes of a first MAC be moved from a low-power state to a fully operational state, request that one or more second lanes of a second MAC, which is separate from the first MAC, be moved from a fully operational state to a low-power state, move one or more second lanes of the second MAC to a low-power state, and move one or more first lanes of the first MAC, where one or more first lanes and one or more second lanes are the same lane, to a fully operational state. The data storage device is configured to be coupled to a plurality of hosts, and the controller comprises a lane management module including a plurality of PHY detaches and a plurality of MAC detaches. The number of PHY detaches among the plurality of PHY detaches is equal to the number of hosts among the plurality of hosts. The number of MAC detaches among the plurality of MAC detaches is equal to the number of hosts among the plurality of hosts. The number of PHY detaches among multiple PHY detaches is equal to the number of MAC detaches among multiple MAC detaches. After a request to move one or more second lanes of the second MAC from a fully operational state to a low-power state, the PHY returns a "L0P ready" message to the second MAC. MAC detaches are configured to communicate "L0P ready" to the MAC to mimic PHY behavior. The first MAC is configured to receive an instruction from the MAC detach logic that the PHY state is still L0P. The controller is configured to connect one or more second lanes to the first MAC. The controller is configured to synchronize one or more second lanes with the host device.

[0053] In another embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, the controller managing a plurality of lane connections between a plurality of MACs and a plurality of host devices, wherein one or more first lane connections of the plurality of lane connections exist for the first MAC of the plurality of MACs, one or more second lane connections of the plurality of lane connections exist for the second MAC of the plurality of MACs, and one or more third lane connections of the plurality of lane connections are shared by the first MAC and the second MAC, the controller is configured to cause the first MAC to register one or more third lane connections as being in a low-power state, and the second MAC to register one or more third lane connections as being in a fully operational state, and simultaneously with the second MAC registering one or more third lane connections as being in a fully operational state, the first MAC registers one or more third lane connections as being in a low-power state. The controller is configured to virtually connect one or more third lane connections to the second MAC. The controller is configured to virtually disconnect one or more third lane connections from the first MAC. The controller is configured to cause a first MAC to register connections to one or more first lane connections and one or more third lane connections, and the first MAC is configured to register one or more first lane connections as fully operational and one or more third lane connections as low-power. The controller is configured to cause a second MAC to register connections to one or more second lane connections and one or more third lane connections, and the second MAC is configured to register one or more second lane connections and one or more third lane connections as fully operational. The first MAC is coupled to a lane management module having corresponding first MAC detach and PHY detach, and the PHY detach is coupled to a multi-lane PHY. The lane management module is configured to detach lanes from a first interface with MAC A and detach lanes from a second interface with MAC B.

[0054] In another embodiment, the data storage device comprises means for storing data and a controller coupled to the means for storing data, the controller maintaining a PHY having a first plurality of lanes, maintaining a first MAC having a second plurality of lanes, wherein the first plurality is greater than the second plurality, and maintaining a second MAC having a third plurality of lanes, wherein the first plurality is greater than the third plurality, and is configured to switch between a low-power state and a full-operation state for the shared lanes by the first MAC and the second MAC. The first plurality is less than the sum of the second plurality and the third plurality. The switching includes switching from the full-operation state for the shared lanes to the low-power state for the first MAC, and the switching includes switching from the low-power state to the full-operation state for the shared lanes to the second MAC.

[0055] While the above applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A data storage device, Memory devices and, The memory device is coupled to a controller, and the controller is The request is to move one or more first lanes of the first MAC from a low-power state to a fully operational state. A second MAC, wherein the second MAC is separate from the first MAC, requires moving one or more second lanes of the second MAC from the fully operational state to the low-power state. Move one or more of the second lanes of the second MAC to the low-power state, A data storage device configured to move one or more first lanes of the first MAC, wherein the one or more first lanes and the one or more second lanes are the same lane, to the fully operational state.

2. The data storage device according to claim 1, wherein the data storage device is configured to be coupled to a plurality of hosts, and the controller comprises a lane management module including a plurality of PHY detaches and a plurality of MAC detaches.

3. The data storage device according to claim 2, wherein the number of PHY detaches among the plurality of PHY detaches is equal to the number of hosts among the plurality of hosts.

4. The data storage device according to claim 2, wherein the number of MAC detaches among the plurality of MAC detaches is equal to the number of hosts among the plurality of hosts.

5. The data storage device according to claim 2, wherein the number of PHY detaches among the plurality of PHY detaches is equal to the number of MAC detaches among the plurality of MAC detaches.

6. The data storage device according to claim 1, wherein after the request to move one or more second lanes of the second MAC from the fully operational state to the low-power state, PHY returns a "L0P ready" message to the second MAC.

7. The data storage device according to claim 6, wherein the MAC detach is configured to communicate "L0P ready" to the MAC in order to mimic PHY behavior.

8. The data storage device according to claim 1, wherein the first MAC is configured to receive an instruction from the MAC detach logic that the PHY state is still L0P.

9. The data storage device according to claim 1, wherein the controller is configured to connect the one or more second lanes to the first MAC.

10. The data storage device according to claim 1, wherein the controller is configured to synchronize the one or more second lanes with a host device.

11. A data storage device, Memory devices and, The memory device is coupled to a controller, and the controller is A plurality of lane connections between a plurality of MACs and a plurality of host devices, wherein one or more first lane connections among the plurality of lane connections exist for the first MAC among the plurality of MACs, one or more second lane connections among the plurality of lane connections exist for the second MAC among the plurality of MACs, and one or more third lane connections among the plurality of lane connections are shared by the first MAC and the second MAC, and the plurality of lane connections are managed. The first MAC is instructed to register the one or more third lane connections as being in a low-power state. A data storage device configured such that the second MAC registers the one or more third lane connections as being in a fully operational state, and simultaneously with the second MAC registering the one or more third lane connections as being in the fully operational state, the first MAC registers the one or more third lane connections as being in the low-power state.

12. The data storage device according to claim 11, wherein the controller is configured to virtually connect the one or more third lane connections to the second MAC.

13. The data storage device according to claim 12, wherein the controller is configured to virtually disconnect the one or more third lane connections from the first MAC.

14. The data storage device according to claim 11, wherein the controller is configured to cause the first MAC to register the connection to the one or more first lane connections and the one or more third lane connections, and the first MAC registers the one or more first lane connections as being in the fully operational state and the one or more third lane connections as being in the low-power state.

15. The data storage device according to claim 12, wherein the controller is configured to cause the second MAC to register the connection to the one or more second lane connections and the one or more third lane connections, and the second MAC is configured to register the one or more second lane connections and the one or more third lane connections as being in the fully operational state.

16. The data storage device according to claim 11, wherein the first MAC is coupled to a lane management module having a corresponding first MAC detach and a PHY detach, and the PHY detach is coupled to a multi-lane PHY.

17. The data storage device according to claim 16, wherein the lane management module is configured to detach lanes from a first interface with MAC A and detach lanes from a second interface with MAC B.

18. A data storage device, Means of storing data, The system comprises a controller coupled to means for storing the aforementioned data, and the controller is Maintain a PHY with multiple lanes, Maintaining a first MAC having a second plurality of lanes, wherein the first plurality is larger than the second plurality, Maintaining a second MAC having a third plurality of lanes, wherein the first plurality is larger than the third plurality, A data storage device configured to switch the power states of the first MAC and the second MAC, respectively, between a low-power state and a fully operational state, such that the respective power states are different from each other, for lanes shared by the first MAC and the second MAC.

19. The data storage device according to claim 18, wherein the first plurality is smaller than the sum of the second plurality and the third plurality.

20. The data storage device according to claim 19, wherein the switching includes switching the shared lane from a fully operational state to a low-power state for the first MAC, and the switching includes switching the shared lane from the low-power state to the fully operational state for the second MAC.

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