Decoder, decoding method, memory controller, and memory system

Abstract

Examples of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system. The decoder includes a cache module and a flip instruction module. The cache module is configured to cache soft data related to a codeword to be decoded. The flip instruction module is configured to retrieve the soft data from the cache module and, when performing hard-decision decoding on the codeword to be decoded, determine, with the help of the soft data, the number of parity checks that are not satisfied by bits in the codeword to be decoded, at least in a first flip iteration.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular, to a decoder, a decoding method, a memory controller, and a memory system.

Background Art

[0002] With the development of storage technology, 3D NAND flash memory has evolved from single-level cells (SLC) capable of storing 1-bit information and double-level cells (DLC) capable of storing 2-bit information, to triple-level cells (TLC) capable of storing 3-bit information, and even to quad-level cells (QLC) capable of storing 4-bit information. The number of stacked layers has also been increasing. For memory devices with more layers and memory bits, low-density parity check (LDPC) is generally adopted for error correction during data reading, in order to improve the reliability of data stored in the memory device. However, the structure of 3D NAND flash is complex, and as the amount of stored data increases, the types of errors contained therein also become increasingly complex. Current error correction methods have the problems of slow error correction speed and inefficiency, which seriously affect the read speed.

Summary of Invention

Problem to be Solved by the Invention

[0003] From this point of view, examples of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system.

[0004] To achieve the above object, the technical solution of the present disclosure is implemented as follows.

Means for Solving the Problem

[0005] In a first embodiment, an example of the present disclosure provides a decoder including a cache module and a flip indication module. The cache module is configured to cache soft data related to the codeword to be decrypted. The flip instruction module is configured to retrieve soft data from the cache module and, when performing hard-decision decoding on the codeword to be decoded, to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, at least in the first flip iteration.

[0006] In the above solution, the flip instruction module is: Determining the initial error bit indicator vector corresponding to the codeword to be decoded, With the help of soft data combined with an initial error bit indicator vector, the number of parity checks that are not filled by bits in the codeword to be decoded is determined. It is further configured to do so.

[0007] In the above solution, the decoder further comprises variable node modules and check node modules connected to form a variable-check connection network according to a pre-constructed check matrix, The variable node module is configured to receive hard-read data, generate a codeword to be decoded according to the hard-read data, send the codeword to be decoded to the check node module, and send the codeword to be decoded and the hard-read data to the flip instruction module. The check node module is configured to receive the codeword to be decoded, determine the checksum vector according to the codeword to be decoded and the check matrix, and send the checksum vector to the flip instruction module. The flip instruction module is further configured to receive the codeword to be decoded and hard read data transmitted by the variable node module, receive the checksum vector transmitted by the check node module, obtain the check matrix and soft data, and determine the initial error bit instruction vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

[0008] In the above solution, the flip instruction module is: Determining the soft data vector corresponding to the soft data, Perform a summation operation on the soft data vector and the initial error bit indicator vector to obtain the target error bit indicator vector, Determine the number of parity checks that are not satisfied by each bit in the codeword to be decoded according to the target error bit instruction vector. It is further configured to do, Each element of the target error bit indicator vector corresponds to the number of parity checks that are not filled by one bit.

[0009] In the above solution, the flip instruction module is: Performing a summation operation on the hard-read data and the codeword to be decoded, and then performing a modulo operation on that sum to obtain a first bit vector, The second bit vector is obtained by multiplying the transpose of the checksum vector by the check matrix, Perform a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector. It is further configured to do so.

[0010] In the above solution, the flip instruction module is: Further configured to generate a flip instruction vector according to the number of unsatisfied parity checks and the flipping criteria, the flip instruction vector contains the determined bits in the codeword to be decoded that need to be flipped. The variable node module is further configured to receive a flip instruction vector and flip the bits in the codeword that need to be flipped according to the flip instruction vector.

[0011] In the above solution, the flipping criterion is: Flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flip bits in the codeword to be decoded if the number of unsatisfied parity checks is greater than or equal to a preset threshold. Includes.

[0012] In the above solution, the decoder further includes a counting module and an termination determination module. The counting module is configured to count the number of iterations of hard decision decoding performed on the codeword to be decoded. The termination determination module is configured to determine whether the number of iterations has reached the maximum number of iterations, whether the checksum vector is a zero vector, and to output a first decryption stop signal when the number of iterations has reached the maximum number of iterations and the checksum vector is a non-zero vector, the first decryption stop signal is configured to indicate that hard-decision decoding of the codeword to be decrypted has failed.

[0013] In the above solution, the decoder further comprises a relocation configuration module, The termination determination module is further configured to output a second decryption stop signal when it is determined that the checksum vector is a zero vector. The reconfiguration module is configured to perform a reconfiguration process on the codeword to be decoded in response to a second decode stop signal, and to output the codeword to be decoded in the correct order.

[0014] In the above solution, the termination determination module is further configured to output a decoding continuation signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, and the decoding continuation signal is configured to instruct the variable node module, the check node module, and the flip instruction module to continue performing hard decision decoding operations on the codeword to be decoded.

[0015] In a second aspect, an example of the present disclosure provides a decoding method, the decoding method comprising: obtaining soft data corresponding to the codeword to be decoded; when performing hard decision decoding on a codeword to be decoded, determining, with the aid of soft data, the number of unsatisfied parity checks by bits in the codeword to be decoded in at least a first flip iteration .

[0016] In the above solution, determining the number of unsatisfied parity checks by bits in the codeword to be decoded with the aid of soft data comprises: determining an initial error bit indication vector corresponding to the codeword to be decoded; determining, with the aid of the soft data combined with the initial error bit indication vector, the number of unsatisfied parity checks by bits in the codeword to be decoded .

[0017] In the above solution, determining the number of unsatisfied parity checks by bits in the codeword to be decoded with the aid of the soft data combined with the initial error bit indication vector comprises: determining a soft data vector corresponding to the soft data; performing a summation operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector determining the number of unsatisfied parity checks for each bit in a codeword to be decoded according to a target error bit indication vector comprising each element of the target error bit indication vector corresponds to the number of parity checks unsatisfied by one bit.

[0018] In the above solution, determining an initial error bit indication vector corresponding to the codeword to be decoded comprises: receiving hard read data and generating the codeword to be decoded according to the hard read data; determining a checksum vector according to the codeword to be decoded and a pre-constructed check matrix; determining an initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix comprising the above steps.

[0019] In the above solution, determining the initial error bit indication vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix comprises: performing a summation operation on the hard read data and the codeword to be decoded, then performing a modulo operation on the summation to obtain a first bit vector; multiplying the transpose of the checksum vector by the check matrix to obtain a second bit vector; performing a summation operation on the first bit vector and the second bit vector to obtain the initial error bit indication vector comprising the above steps.

[0020] In the above solution, the method comprises: generating a flip indication vector according to the number of unsatisfied parity checks and a flipping criterion, wherein the flip indication vector comprises determined bits that need to be flipped in the codeword to be decoded Flip the bits in the codeword that need to be flipped according to the flip instruction vector. It also includes.

[0021] In the above solution, the method is: The process involves generating a flip instruction vector according to the number of unsatisfied parity checks and the flipping criteria, wherein the flip instruction vector includes the determined bits in the codeword to be decoded that need to be flipped. Flip the bits in the codeword that need to be flipped according to the flip instruction vector. It also includes.

[0022] In the above solution, the flipping criterion is: Flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flip bits in the codeword to be decoded if the number of unsatisfied parity checks is greater than or equal to a preset threshold. Includes.

[0023] In the above solution, the method is: Counting the number of iterations of hard decision decoding performed on the codeword to be decoded, This involves determining whether the number of iterations has reached the maximum number of iterations, and whether the checksum vector is a zero vector, Outputting a first decryption stop signal when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, wherein the first decryption stop signal is configured to indicate that hard-decision decoding of the codeword to be decrypted has failed. It also includes.

[0024] In the above solution, the method is: Determine whether the checksum vector is a zero vector, and if it is determined that the checksum vector is a zero vector, output a second decoding stop signal. In response to the second decryption stop signal, a rearrangement and configuration process is performed on the codeword to be decrypted, and the codeword to be decrypted is output in the correct order. It also includes.

[0025] In the above solution, the method is: The system further includes outputting a decryption continuation signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, the decryption continuation signal being configured to instruct a hard-decision decryption operation to be performed on the codeword to be decrypted.

[0026] In a third embodiment, an example of the present disclosure further provides a memory controller comprising a processor and a decoder according to any one of the above embodiments, wherein the processor is configured to read soft data corresponding to a codeword to be decoded from a memory device. The decoder caches soft data and, when performing hard decision decoding on the codeword to be decoded, is configured to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, at least in the first flip iteration.

[0027] In a fourth embodiment, an example of the present disclosure provides a memory system, the memory system is A memory device configured to store data, A memory controller coupled to a memory device, comprising a processor and a decoder, wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device, and Equipped with, The decoder caches soft data and, when performing hard decision decoding on the codeword to be decoded, is configured to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, at least in the first flip iteration.

[0028] In the above solution, the processor is further configured to read hard read data from the memory device and send the hard read data to the decoder. The decoder is further configured to receive hard-read data and generate codewords to be decoded according to the hard-read data.

[0029] In the above solution, the decoder comprises a cache module, a variable node module, a check node module, and a flip instruction module. The cache module is configured to cache soft data read by the processor. The variable node module is configured to receive hard-read data read by the processor, generate a codeword to be decoded according to the hard-read data, and send the codeword to be decoded to the check node module. The check node module is configured to receive the codeword to be decrypted sent by the variable node module, determine the checksum vector according to the codeword to be decrypted and the pre-constructed check matrix, and send the checksum vector to the flip instruction module. The flip instruction module is configured to receive hard read data and the codeword to be decoded transmitted by the variable node module, receive the checksum vector transmitted by the check node module, obtain the check matrix and soft data, determine the initial error bit instruction vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix, and determine the number of parity checks that are not filled by bits in the codeword to be decoded with the help of the soft data combined with the initial error bit instruction vector.

[0030] Examples of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system. The decoder comprises a cache module and a flip indicator module. The cache module is configured to cache soft data relating to a codeword to be decoded. The flip indicator module retrieves the soft data from the cache module and is configured to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, in at least one flip iteration, when performing hard-decision decoding on the codeword to be decoded. The decoder provided by examples of the present disclosure caches soft data relating to the codeword to be decoded through an included buffer module, and the flip indicator module then determines, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, in one or more iterations, when performing hard-decision decoding on the codeword to be decoded. In this way, the soft data is used to assist in the flipping decision of hard-decision decoding, thereby enabling high processing power and low power consumption of hard-decision decoding and significantly improving the error correction capability of hard-decision decoding.

[0031] In drawings that are not necessarily to scale, similar reference numbers may be used to describe similar components in different drawings. The same number with different subscripts may indicate different instances of similar components. Drawings generally use examples to illustrate, without limitation, the various examples described herein. [Brief explanation of the drawing]

[0032] [Figure 1] This is a schematic diagram of an exemplary system having a memory system according to an example of this disclosure. [Figure 2a] This is a schematic diagram of an exemplary memory card having a memory system according to an example of the present disclosure. [Figure 2b]This is a schematic diagram of an exemplary solid-state drive having a memory system according to an example of the present disclosure. [Figure 3] This is a schematic diagram of a memory controller according to an example of the disclosure. [Figure 4] This is a schematic diagram of an exemplary memory device including peripheral circuits, as shown in this disclosure. [Figure 5] This is a schematic cross-sectional view of a memory array including a NAND type memory string according to an example of the present disclosure. [Figure 6] This is a schematic diagram of an exemplary memory device, including a memory array and peripheral circuits, according to an example of the present disclosure. [Figure 7] This is a schematic diagram of a decoder according to an example of the disclosure. [Figure 8] This is an illustrative schematic diagram illustrating how soft data and hard read data are obtained using an example of this disclosure. [Figure 9] This is a schematic diagram of a decoder according to another example of the present disclosure. [Figure 10] This is a schematic diagram of a Tanner graph based on an example of this disclosure. [Figure 11] This is a schematic diagram of a Tanner graph based on an example of this disclosure. [Figure 12] This is a schematic diagram of a decoder according to another example of the present disclosure. [Figure 13] This is a schematic diagram of a decoder according to another example of the present disclosure. [Figure 14] This is a schematic diagram of the decoder workflow as an example of this disclosure. [Figure 15] This is a schematic flowchart of a decryption method according to an example of the disclosure. [Figure 16] This is a schematic diagram of a memory controller according to an example of the disclosure. [Modes for carrying out the invention]

[0033] Various examples of this disclosure are described below in more detail with reference to the accompanying drawings. Other examples, which are variations of any disclosed example, may be formed by differently configuring or arranging the elements and features of the examples of this disclosure. Thus, the examples of this disclosure are not limited to those described herein. Rather, the examples described are provided so that the disclosed examples are comprehensive and complete, and so as to convey the scope of the disclosed examples to those skilled in the art to whom the examples of this disclosure relate. It should be noted that references to “one example,” “another example,” and similar references do not necessarily mean only one example, and different references to such phrases do not necessarily refer to the same example. Terms such as “first,” “second,” and “third” may be used herein to identify various elements, but it should be understood that these elements should not be limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Thus, the first element in one example may be referred to as the second or third element in another example without departing from the spirit and scope of the examples of this disclosure.

[0034] Drawings are not necessarily to scale, and in some cases, they may be exaggerated to clearly illustrate the features of the example. When it is mentioned that one element is connected to or joined to another, it should be understood that the former may be directly connected to or joined to the latter, or electrically connected to or joined to the latter via one or more intervening elements. In addition, when it is mentioned that an element is "between" two elements, it should be understood that the element may be the sole element between the two elements, or that one or more intervening elements may also be present.

[0035] The terms used herein are intended to illustrate specific examples only and are not intended to limit the scope of this disclosure. As used in the original English text of this disclosure, singular nouns are intended to include plural nouns unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context to be singular, at least one of the articles "a" or "an" used in the examples and appended claims of this disclosure in the original English text shall be interpreted as meaning "one or more." It should be further understood that the phrases "comprise," "comprising," "include," and "including" used in the examples of this disclosure specify the presence of the element being described and do not exclude the presence or addition of one or more other elements. The phrase "at least one" used in the examples of this disclosure includes any combination of one or more of the relevant enumerated items. Unless otherwise defined, all terms used in the examples of this disclosure, including technical and scientific terms, have the same meaning as they would be commonly understood by a person skilled in the art in which this disclosure belongs, in light of the examples of this disclosure. Unless explicitly defined by the examples of this disclosure, terms as defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the examples of this disclosure and the art relating to them, and not as being interpreted in an ideal or overly formalized manner.

[0036] In the following description, numerous specific details are given to provide a comprehensive understanding of the disclosure, but the disclosure may be implemented without some or all of these specific details. In other cases, at least one well-known processing structure or process is not described in detail so as not to unnecessarily complicate the disclosure. In some cases, unless otherwise noted, it should be understood that a feature or element described in one example may be used alone or in combination with other features or elements of the other example, as will be obvious to those skilled in the art. Various examples of the disclosure are described below in detail with reference to the accompanying drawings. The following description focuses on details that facilitate understanding of the examples of the disclosure. Well-known technical details may be omitted so as not to complicate the features and aspects of the examples of the disclosure.

[0037] To enable a more detailed understanding of the characteristics and technical content of the examples in this disclosure, these examples are described in detail below in conjunction with the accompanying drawings. The accompanying drawings are provided for reference and illustrative purposes only and are not intended to limit the examples in this application.

[0038] Memory devices are memory devices used to store information in modern information technology. As a typical non-volatile memory device, 3D NAND (Not-And) memory devices have become the mainstream product in the storage market due to their high storage density, controllable production costs, favorable programming and erasing speeds, and retention characteristics. As the number of memory bits and stacks of memory cells increases, the types of errors that occur during the read operation of memory devices become increasingly complex. In this case, when LDPC hard-decision decoding in the decoder is used to decode the codeword to be decoded (data read from the memory device), the decoding time becomes longer, the error correction capability weakens, and the read speed is severely affected.

[0039] Based on one or more of the above problems, an example of the present disclosure provides a decoder that uses soft data to assist in flip determination of hard-decision decoding, thereby achieving the characteristics of high processing power and low power consumption of hard-decision decoding, and thereby significantly improving the error correction capability of hard-decision decoding.

[0040] Examples of this disclosure are described in further detail below, in conjunction with the attached drawings and specific examples.

[0041] Figure 1 is a schematic diagram of an exemplary system having a memory system according to an example of the present disclosure. In Figure 1, system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system in it. As shown in Figure 1, system 100 may comprise a host 108 and a memory system 102. The host 108 may comprise a processor such as a central processing unit (CPU) or a system-on-a-chip (SoC). The SoC may be, for example, an application processor (AP). The host 108 further comprises at least one operating system (OS) that can generally manage and control the functions and operations performed on the host 108. The OS may enable interoperability between the host 108 coupled to the memory system 102 and a user who requires and uses the memory system 102. The OS may support functions and operations that respond to user requests. For example, but not limited to, depending on whether the host 102 is a removable host, the OS may be classified into general-purpose operating systems and mobile operating systems. General-purpose operating systems may be personal operating systems, which may be operating systems used to support general-purpose services including Windows and Chrome, and enterprise operating systems, which may be operating systems specifically designed to ensure and support high performance, including Windows Server, Linux®, Unix, etc. Mobile operating systems may refer to operating systems for mobility services or functions (e.g., power saving functions). Generally, mobile operating systems may be operating systems such as Android, iOS, and Windows Mobile. In some examples, host 108 may contain multiple OSs.In response to this, the host 108 may run multiple operating systems related to the memory system 102. In another example, the host 108 translates a user request into one or more commands, transmits those commands to the memory system 102, and the memory system 102 then performs the operations related to those commands.

[0042] The memory system 102 can operate or perform specific functions or perform various internal operations in response to requests from the host 108. In some examples, the memory system 102 can store data accessed by the host 108. The memory system 102 can function as a primary or secondary memory system to the host 108. The memory system 102 and the host 108 can be electrically coupled and communicate according to corresponding protocols. The memory system 102 can be implemented and packaged in different types of final electronic products, including, but not limited to, solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RSMMCs), microMMCs, secure digital (SD) cards, miniSDs, microSDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash® (CF) cards, smartmedia (SM) cards, and memory sticks.

[0043] In some examples, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured by a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured by a home network, one of various electronic devices configured by a computer network, one of various electronic devices configured by a telematics network, a radio frequency identification (RFID) device, or one of various components configured by a computing system.

[0044] Referring again to Figure 1, the memory system 102 may comprise one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and then control the memory devices 104. For example, the memory controller 106 can read data from the memory device 104 and transmit the read data to the host 108. Furthermore, the memory controller 106 can receive data to be stored from the host 108 and store the data to be stored in the memory device 104. That is, the memory controller 106 can control write (or program) operations, read operations, erase operations, background operations, and similar operations of the memory device 104. Furthermore, the memory system 102 can be implemented and packaged in different types of final electronic products. In one example, as shown in Figure 2a, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include PC cards (PCMCIA, International Personal Computer Memory Card Association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 for connecting the memory card 202 to a host (for example, host 108 in Figure 1). In another example, as shown in Figure 2b, a memory controller 206 and multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 for connecting the SSD 206 to a host (for example, host 108 in Figure 1). In some examples, at least one of the storage capacity or operating speed of the SSD 206 is greater than that of the memory card 202.

[0045] As shown in Figure 3, the memory controller 106 may comprise a host interface (or front-end interface) 301, a memory interface (or back-end interface) 302, a processor 303, and memory 304. The aforementioned components 301, 302, 303, and 304 of the memory controller 106 can share internal transmission signals through an internal bus. In some examples, the host interface 301 can interface the host 108 with the memory system 102 in response to the host 108's protocol, and the host interface 301 exchanges transfer commands and data operations between the host 108 and the memory system 102. The host I / F 301 can process commands and data sent by the host 108 and may include at least one of the following: Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE). In some examples, the host I / F 301 is a component of the memory system 102 used to exchange data with the host 108 and may be implemented by firmware called the Host Interface Layer (HIL).

[0046] The memory interface 302 may also be an interface for commands and data transferred between the memory controller 106 and the memory device 104, enabling the memory controller 106 to control the memory device 104 in response to requests transmitted from the host 108. The memory interface 302 can generate control signals for controlling the memory device 104. In some examples, if the memory device 104 is a NAND flash memory, the memory interface 302 can write data to or read data from the memory device 104 under the control of the processor 303. The memory interface 302 can handle commands and data between the memory controller 106 and the memory device 104, and can, for example, handle the operation of the NAND flash interface, particularly the operation between the memory controller 106 and the memory device 104. In one example, the memory interface 302 may be implemented as a component for exchanging data with the memory device 104 by firmware called the flash interface layer (FIL).

[0047] The processor 303 may be implemented as a microprocessor or a central processing unit (CPU). The memory system 102 may comprise one or more processors 303. The processor 303 can control the overall operation of the memory system 102. For example, but not limited to, the processor 303 can control program operations or read operations of the memory device 104 in response to write or read requests from the host 108. For example, the processor 303 may use or run firmware to control the overall operation of the memory system 102. In this disclosure, firmware may be referred to as a flash conversion layer (FTL). The FTL may act as an interface between the host 108 and the memory device 104. The host 108 can transmit requests related to write and read operations to the memory device 104 through the FTL. For example, the memory controller 106 uses the processor 303 when performing operations requested by the host 108 on the memory device 104. The processor 303 coupled to the memory device 104 can process instructions or commands related to commands from the host 108. The memory controller 106 can perform foreground operations such as command operations corresponding to command input from the host 108, for example, program operations corresponding to write commands, read operations corresponding to read commands, and erase / discard operations corresponding to erase / discard commands, as well as parameter setting operations corresponding to parameter setting commands or feature setting commands with setting commands.

[0048] As another example, the memory controller 106 may perform background operations on the memory device 104 by the processor 303. Background operations may include, but are not limited to, garbage collection (GC) operations, wear leveling (WL) operations, map clearing operations, and bad block management operations that inspect or search for bad blocks. Garbage collection operations may include copying and processing data stored in a particular memory block within the memory device 104 to another memory block. Wear leveling operations may include swapping and processing data stored between memory blocks of the memory device 104. Map clearing operations may include storing map data stored in the memory controller 106 into the memory blocks of the memory device 104. Bad block management operations may include inspecting and processing bad blocks within the memory blocks of the memory device 104. The memory controller 106 may respond to operations that access the memory blocks of the memory device 104. Operations that access memory blocks of memory device 104 may include foreground or background operations performed on memory blocks of memory device 104.

[0049] Memory 304 may also be the working memory of the memory controller 106 and is configured to store data used to drive the memory controller 106. More specifically, when the memory controller 106 controls the memory device 104 in response to a request from the host 108, memory 304 can store firmware driven by the processor 303 and data (e.g., metadata) necessary to drive that firmware. Memory 304 may also be the buffer memory of the memory controller 106 and is configured to temporarily store write data transferred from the host 108 to the memory device 104 and read data transferred from the memory device 104 to the host 108. Memory 304 may include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and map buffer / cache for storing write and read data. Memory 304 may be implemented using volatile memory. Memory 304 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0050] Figure 3 shows that memory 304 is included in memory controller 106, but the disclosure is not limited thereto. In one example, memory 304 may be outside of memory controller 106, and memory controller 106 may input data to memory 304 and output data from memory 304 via another memory interface (not shown).

[0051] The error correction (ECC) module 305 comprises an encoding section 3051 and a decoding section 3052. The encoding section 3051 can perform an encoding operation such as LDPC on data to be programmed into the semiconductor memory device 104 and output data including additional parity check bits. The parity check bits can be stored in the semiconductor memory device 104. The decoding section 3052 can perform error correction decoding on data read from the semiconductor memory device 104, determine whether the error correction decoding was successful, output an instruction signal based on the result of the determination, and correct error bits in the data using the parity check bits generated by the LDPC encoding operation.

[0052] Here, Figure 3 shows that the error correction module 305 is included in the memory controller 106, but the disclosure is not limited thereto. In one example, the error correction module 305 may be located outside the memory controller 106, and the memory controller 106 may communicate with the error correction module 305 via another interface (not shown).

[0053] Referring again to Figure 1, the memory device 104 may include non-volatile memory that retains data stored therein even when power is not supplied. The memory device 104 may further include volatile storage memory. The device 104 can store data provided by the host 108 through write operations. The memory device 104 can also provide stored data to the host 108 through read operations. In the examples of this disclosure, the memory device 104 may include any memory disclosed, for example, volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), or volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM®), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive random-access RAM (RRAM or ReRAM), and flash memory (for example, 3D NAND flash memory).

[0054] Memory devices are illustrated by taking a three-dimensional NAND flash memory as an example. Referring to Figure 4, this shows a schematic circuit diagram of an exemplary memory device 400 including peripheral circuits according to several aspects of the present disclosure. Memory device 400 may be an example of memory device 104 in Figure 1. Memory device 400 may include a memory array 401 and peripheral circuits 402 coupled to the memory array 401. The memory array 401 is illustrated by taking a three-dimensional NAND memory array as an example. Memory cells 406 are provided in the form of an array of NAND memory strings 408, each extending vertically on a substrate (not shown). In some examples, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 406. Each memory cell 406 may be either a floating-gate memory cell including a floating-gate transistor, or a charge-trapped memory cell including a charge-trap transistor.

[0055] In some examples, each memory cell 406 is a single-level cell (SLC) that has two possible memory states and is therefore capable of storing one bit of data. For example, the first memory state "0" can correspond to a first range of voltages, and the second memory state "1" can correspond to a second range of voltages. In some examples, each memory cell 406 is a multi-level cell (MLC) that can store more than one bit of data in more than four memory states. For example, an MLC can store 2 bits per cell, 3 bits per cell (also called a triple-level cell (TLC)), 4 bits per cell (also called a quad-level cell (QLC)), or 5 bits per cell (also called a penta-level cell (PLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores 2 bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal memory value may be used for the erase state.

[0056] As shown in Figure 4, each NAND memory string 408 may have a bottom selective gate (BSG) 410 at its source end and a top selective gate (TSG) 412 at its drain end. The BSG 410 and TSG 412 may be configured to activate a selected NAND memory string 408 during read and program operations. In some examples, the sources of NAND memory strings 408 within the same block 404 are coupled through the same source line (SL) 414, for example, a common SL. In other words, according to some examples, all NAND memory strings 408 within the same block 404 have an array common source (ACS). The TSG 412 of each NAND memory string 408 is coupled, according to some examples, to its respective bit line (BL) 416, from which data may be read or written via an output bus (not shown). In some examples, each NAND memory string 408 is configured to be selected or deselected by at least one of the following: applying a selection voltage (e.g., above the threshold voltage of the transistor having the TSG 412) or a deselection voltage (e.g., 0V) to each TSG 412 through one or more TSG lines 413, or applying a selection voltage (e.g., above the threshold voltage of the transistor having the BSG 410) or a deselection voltage (e.g., 0V) to each BSG 410 through one or more BSG lines 415.

[0057] As shown in Figure 4, a NAND memory string 408 can be organized into multiple blocks 404, each of which may have a common source line 414, for example, connected to ground. In some examples, each block 404 is a basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase the memory cells 406 in a selected block 404, the source line 414 connected to the selected block 404, as well as any unselected blocks 404 in the same plane as the selected block 404, may be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). In some examples, it is understood that the erase operation may be performed at the 1 / 2 block level, the 1 / 4 block level, or at any preferred number of blocks or any preferred portion of a block. Memory cells 406 of adjacent NAND memory strings 408 may be connected through word lines 418 that select which rows of memory cells 406 are affected by read and program operations.

[0058] Figure 5 shows a schematic cross-sectional view of an exemplary memory array 401 including a NAND memory string 408 according to several aspects of the present disclosure. As shown in Figure 5, the NAND memory string 408 may include a stacked structure 510 comprising a plurality of gate layers 511 and a plurality of insulating layers 512 stacked alternately in sequence, and a memory string 408 that penetrates the gate layers 511 and insulating layers 512 perpendicularly. The gate layers 511 and insulating layers 512 may be stacked alternately, and two adjacent gate layers 511 are separated by the insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 can determine the number of memory cells included in the memory array 401.

[0059] The constituent material of the gate layer 511 may include a conductive material. The conductive material may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some examples, each gate layer 511 may include a metallic layer, such as a tungsten layer. In some examples, each gate layer 511 may include a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding the memory cell. A gate layer 511 on top of the stacked structure 510 may extend laterally as a top selective gate line, a gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a bottom selective gate line, and a gate layer 511 extending laterally between the top selective gate line and the bottom selective gate line may be used as a word line layer 503.

[0060] In some examples, the laminated structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0061] In some examples, the NAND memory string 408 includes a channel structure extending vertically through the stacked structure 510. In some examples, the channel structure includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some examples, the semiconductor channel includes silicon, for example, polysilicon. In some examples, the memory film is a composite dielectric layer including a tunnel layer, a storage layer (also referred to as a "charge trap / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a columnar shape). According to some examples, the semiconductor channel, tunnel layer, storage layer, and blocking layer are arranged radially in this order from the center of the column toward the outer surface of the column. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0062] Referring again to Figure 4, the peripheral circuit 402 may be coupled to the memory array 401 through bit lines 416, word lines 418, source lines 414, BSG lines 415, and TSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed-signal circuits to smooth the operation of the memory array 401 by applying and sensing at least one of a voltage signal or current signal from or to each target memory cell 406 through bit lines 416, word lines 418, source lines 414, BSG lines 415, and TSG lines 413. The peripheral circuit 402 may include various types of circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 illustrates several exemplary peripheral circuits, where peripheral circuit 402 comprises a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, registers 614, an interface 616, and a data bus 618. It is understood that in some examples, additional peripheral circuits not shown in Figure 6 may also be included.

[0063] The page buffer / sense amplifier 604 may be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to a control signal from the control logic 612. In one example, the page buffer / sense amplifier 604 may store program data (write data) to be programmed in the memory array 401. In another example, the page buffer / sense amplifier 604 may perform a program verify operation to confirm that data is properly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 may also sense a low-power signal from the bit line 416 representing data bits stored in the memory cell 406 and amplify small voltage amplitudes in the read operation to a recognizable logic level. The column decoder / bit line driver 606 may be controlled by the control logic 612 and configured to select one or more NAND memory strings 408 by applying bit line voltages generated from the voltage generator 610.

[0064] The row decoder / word line driver 608 may be controlled by control logic 612 and configured to select / deselect block 404 of the memory array 401 and select / deselect word line 418 of block 404. The row decoder / word line driver 608 may be further configured to drive word line 418 using word line voltages generated from a voltage generator 610. In some examples, the row decoder / word line driver 608 may also select / deselect and drive BSG line 415 and TSG line 413 as well. The row decoder / word line driver 608 is configured to perform programmed operations on memory cells 406 coupled to the selected word line 418. The voltage generator 610 may be controlled by control logic 612 and configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, channel boost voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0065] The control logic 612 may be coupled to each of the peripherals described above, such as the voltage generator 610 and the row decoder / word line driver 608, and configured to control the operation of each peripheral. Registers 614 may be coupled to the control logic 612 and may include a status register, a command register, and an address register that store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral. Interface 616 may be coupled to the control logic 612 and operate as a control buffer that buffers and relays control commands received to the control logic 612 from a host (not shown) and status information received from the control logic 612 to the host. Interface 616 may also be coupled to the row decoder / bit line driver 606 via the data bus 618 and operate as a data I / O interface and data buffer that buffers and relays data from or to the memory array 401.

[0066] Among 3D NAND memory devices, single-level cells (SLC) hold a certain share of the memory market due to their advantages such as fast read and write speeds, high reliability, and long service life. However, multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC) are the development trends in the memory market due to their high storage density and large storage capacity.

[0067] However, as the number of memory bits in a memory cell increases and the number of stacks increases, the types of errors it contains become increasingly complex. When performing a read operation on a memory device, LDPC hard decision decoding is used to decode the codeword to be decoded, which increases decoding time, weakens error correction capability, and seriously impacts read speed.

[0068] Based on the memory devices and memory systems described above, Figure 7 is referenced to address one or more of the aforementioned problems. Figure 7 is a schematic diagram of a decoder according to an example of the present disclosure.

[0069] In some examples, the decoder 700 includes a cache module 701 and a flip instruction module 702. The cache module 701 is configured to cache soft data related to the codeword to be decrypted. The flip instruction module 702 is configured to retrieve soft data from the cache module 701 and, when performing hard decision decoding on the codeword to be decoded, to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, at least in the first flip iteration.

[0070] It should be noted that the decoder provided by the examples of this disclosure may be applied to the aforementioned memory system, and the decoder 700 may be configured to be set up in the decoding section of the memory controller as shown in Figure 3 and to perform a decoding operation on the codeword to be decoded. The codeword to be decoded here may refer to hard-read data that can be read from the memory device by the memory controller according to the hard-read voltage, or the codeword to be decoded may be a codeword that has been flipped in a particular iteration during decoding. Whether the codeword to be decoded is hard-read data or a codeword that has been flipped in a particular iteration will be described in detail later and will not be repeated here.

[0071] Here, the hard read voltage may be the initial read voltage, which is a default read voltage preset by the memory system, and which may be the same as the reference voltage in the Read Retry Table (RRT), or have a specific offset from the reference voltage, the offset being included in the RRT. Alternatively, the hard read voltage may be the optimal read voltage. Methods for obtaining the optimal read voltage include, but are not limited to, determining the optimal read voltage according to the use of the memory device and the RRT. A particular process may include traversing the RRT, determining the voltage offset in the RRT for the minimum error when reading the memory device in this use case, and then obtaining the optimal read voltage based on the reference voltage and the determined voltage offset.

[0072] Note that the RRT is a table containing multiple voltage offsets, each voltage offset being relative to a reference voltage. These voltage offsets can be implemented by hardware circuitry in memory. For example, these voltage offsets can be set through registers contained in memory. In other words, the required voltage offset for all read voltages is obtained based on the RRT table, then superimposed with the reference voltage (including sign superimposition, i.e., if the voltage offset is negative, the final read voltage is lower than the reference voltage), thereby obtaining the required voltage value, which is then applied to the corresponding word line.

[0073] Regarding RRT, for example, as shown in Table 1, this is the RRT corresponding to the TLC memory cell in the example of this disclosure. Each column in Table 1 represents a set of voltage offsets, i.e., Rd1 to Rd7, that distinguish adjacent programming states with respect to the corresponding reference voltage. Note that since the TLC memory cell has eight data states, they can be distinguished by using seven read voltages, i.e., there are seven columns in Table 1.

[0074] The set of voltage offsets described above may include positive offsets that increase in the direction greater than the reference voltage and negative offsets that decrease in the direction less than the reference voltage. For example, in Rd7, +V1, +V2, +V3, and +V4 are positive offsets, and the values ​​of V1, V2, V3, and V4 increase sequentially, while -V5 through -V11 are negative offsets, and the values ​​of V5 through V11 decrease sequentially.

[0075] [Table 1]

[0076] Referring again to the decoder shown in Figure 7, the soft data used in the decoder may be a kind of probabilistic information used to measure the reliability of specific readout data (such as hard readout data in the examples of this disclosure), and may be represented by the log-likelihood ratio (LLR). Thus, there is readout data that serves as a benchmark for measuring the reliability of the soft data.

[0077] For soft data, please refer to Figure 8. In Figure 8, it is assumed that the hard read data read at the optimal read voltage is 1100, and the data read at the first re-read voltage is 1000, the first re-read voltage is to the left of the optimal read voltage and deviates from the optimal read voltage by a specific offset represented as -Δ, and the data read at the second re-read voltage is 1110, the second re-read voltage is to the right of the optimal read voltage and deviates from the optimal read voltage by a specific offset represented as +Δ. Correspondingly, the soft data may be 0110. In this case, the soft data can be used to determine the confidence level of the hard read data 1100 / 1000 / 1110. In some examples, the soft data is used to determine the confidence level of the hard read data, and a bit of "0" in the soft data indicates that the confidence level of that bit in the hard read data is relatively high. In other words, that bit is determined to be closer to true. A bit of "1" in the soft data indicates that the confidence level of that bit in the hard read data is low. For example, in Figure 8, the confidence level of the hard read data 1100 is determined by using the soft data 0110. The leftmost bit of the hard read data 1100 is "1", and the corresponding number in the soft data is "0". Therefore, the confidence level of that bit is relatively high, i.e., a strong "1". By analogy, the two middle bits of the hard read data 1100 correspond to "1" in the soft data. Therefore, the confidence level of the two middle bits is weak, i.e., a weak "1" or "0", and the rightmost bit of the hard read data 1100 is a strong "0".

[0078] In some examples, the method for obtaining soft data may include directly reading soft data from a NAND memory device, as shown in Figure 8. In some examples, the memory controller can send a command to the memory device to read soft data, and the memory device feeds the soft data back to the memory controller. In some other examples, the soft data may be based on the result of XORing two adjacent hard-read data pre-cached in the memory controller's memory.

[0079] When performing hard-decision decoding on a codeword to be decoded, the decoder provided by the examples of this disclosure obtains soft data relating to the codeword to be decoded, which has been buffered by a buffer module within the decoder, and then, with the help of that soft data, determines the number of parity checks that are not filled by bits in the codeword to be decoded. Hard-decision decoding can be LDPC bit flip decoding. In LDPC bit flip decoding, fast read soft data is used to assist LDPC bit flip decoding in at least a first flip iteration, thereby significantly improving the correction capability of LDPC bit flip decoding. Assisting bit flip determination with soft data in at least a first flip iteration may be done in the first flip iteration only, or in the first and second flip iterations, or in multiple flip iterations, etc.

[0080] Here, an unsatisfied parity check may mean that, after the codeword to be decoded has been checked only once by the check matrix, each non-zero element in the generated checksum vector corresponds to a parity check equation involving a bit in the codeword to be decoded that is not satisfied. The number of unsatisfied parity checks by bits in the codeword to be decoded may refer to the number of non-zero elements in the parity check equation involving bits in the codeword to be decoded.

[0081] For example, assuming the codeword to be decoded is C1C2C3C4C5C6C8C9C10C11C12, the checksum vector satisfied in a single check is:

[0082]

number

[0083] This is the result.

[0084] In this case, the number of parity checks not satisfied by bits in the codeword are C1:2, C2:2, C3:0, C4:1, C5:2, C6:1, C7:1, C8:0, C9:0, C10:1, C11:0, and C12:1, respectively.

[0085] In some examples, the flip instruction module 702 is: Determining the initial error bit indicator vector corresponding to the codeword to be decoded, With the help of soft data combined with an initial error bit indicator vector, the number of parity checks that are not filled by bits in the codeword to be decoded is determined. It can be further configured to do so.

[0086] Note that in some examples, this operation involves using soft data to help determine the number of parity checks that are not filled by the bits in the codeword to be decoded. In some examples, an initial error bit indicator vector for the codeword to be decoded is determined first. The initial error bit indicator vector may indicate the number of parity checks that are not filled by the bits in the codeword to be decoded when only LDPC bit flip decoding is performed without the help of soft data. The number of parity checks that are not filled by the bits in the codeword to be decoded is then determined with the help of soft data in combination with the initial error bit indicator vector.

[0087] In some examples, the flip instruction module 702 is: Determining the soft data vector corresponding to the soft data, Perform a summation operation on the soft data vector and the initial error bit indicator vector to obtain the target error bit indicator vector, Determine the number of parity checks that are not satisfied by each bit in the codeword to be decoded according to the target error bit instruction vector. It is further configured to do, Each element of the target error bit indicator vector corresponds to the number of parity checks that are not filled by one bit.

[0088] It should be noted that the following describes how to determine the number of parity checks that are not filled by bits in the codeword to be decoded, with the help of soft data combined with an initial error bit indicator vector. In some examples, the soft data is first represented in the form of a soft data vector. Then, a summation operation is performed on the soft data vector and the aforementioned initial error bit indicator vector to obtain a target error bit indicator vector, where each element of the target error bit indicator vector corresponds to the number of parity checks that are not filled by 1 bit.

[0089] For example, assuming the initial error bit vector is {0, 1, 1, 0}, the soft data vector corresponding to the soft data is {0, 1, 1, 0}, and the target error bit vector is {0, 2, 2, 0}. Here, the number of parity checks not satisfied by the first bit in the codeword to be decoded is 0, the number of parity checks not satisfied by the second bit in the codeword to be decoded is 2, the number of parity checks not satisfied by the third bit in the codeword to be decoded is 2, and the number of parity checks not satisfied by the fourth bit in the codeword to be decoded is 0.

[0090] According to an example of the present disclosure, as shown in Figure 9, to obtain the initial error bit instruction vector in some examples, the decoder 700 further includes a variable node module 703 and a check node module 704. The node modules and the check node modules are connected to form a variable check connection network according to a pre-constructed check matrix. The variable node module 703 is configured to receive hard read data, generate a codeword to be decoded according to the hard read data, send the codeword to be decoded to the check node module, and send the codeword to be decoded and the hard read data to the flip instruction module. The check node module 704 is configured to receive the codeword to be decoded, determine a checksum vector according to the codeword to be decoded and the check matrix, and transmit the checksum vector to the flip instruction module. The flip instruction module 702 is further configured to receive the codeword to be decoded and hard read data transmitted by the variable node module, receive the checksum vector transmitted by the check node module, obtain the check matrix and soft data, and determine the initial error bit instruction vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

[0091] It should be noted that the decoder shown in Figure 7 discloses only the main structure relating to the inventive concept of the example of this disclosure. In LDPC bit flip decoding, the decoder may further include a variable node module and a check node module. Furthermore, the variable node module may include multiple variable node units, and the check node module may include multiple check node units. The multiple variable node units and the multiple check node units are connected to form a variable check connection network according to a pre-constructed check matrix, where the pre-constructed check matrix refers to the LDPC check matrix, which may also be called the H matrix.

[0092] In practical applications, the variable check connection network formed above may also be referred to as a Tanner graph, as shown in Figure 10. In Figure 10, the Tanner graph includes a check node 1001, a variable node 1002, and an edge 1003 connecting the check node and the variable node. The value transferred from the check node to the variable node after check node processing is referred to as check node information 1004A. The value transferred from the variable node to the check node after variable node processing is referred to as variable node information 1004B.

[0093] As an example, referring to Figure 11, the Tanner graph includes five check nodes 1001 for the parity check expression of the H matrix, ten variable nodes 1002 representing the code symbols, and edges 1003 representing the relationships between the check nodes and the variable nodes. The edges 1003 connect each check node to the variable node corresponding to the code symbol contained in the parity check expression represented by the check node. Figure 11 shows a Tanner graph formed by an H matrix where the number of variable nodes connected to each check node is fixed at 4, and the number of check nodes connected to each variable node is fixed at 2. The initial values ​​of the variable nodes can be hard-read data.

[0094] Under the decoder structure shown in Figure 9, the variable node module can receive hard-read data, generate a codeword to be decoded according to the hard-read data, send the codeword to be decoded to the check node module, and send the codeword to be decoded and the hard-read data to the flip indicator module. The check node module can receive the codeword to be decoded, determine a checksum vector according to the codeword to be decoded and the aforementioned check matrix, and send the checksum vector to the flip indicator module. The flip indicator module can receive the aforementioned codeword to be decoded, hard-read data, and checksum vector, obtain the check matrix, and then obtain an initial error bit indicator vector according to the codeword to be decoded, hard-read data, checksum vector, and check matrix.

[0095] Based on the above description, it should be noted that the decoder may be located within the decoding section of the memory controller. Therefore, the hard read data received by the variable node module may be a read command corresponding to the processor. In this case, the read data fed back by the memory device via the memory I / F is transmitted directly to the variable node module via the bus. Alternatively, the hard read data received by the variable node module may be a read command corresponding to the processor. In this case, the read data fed back by the memory device via the memory I / F is temporarily stored in memory, and the hard read data is retrieved from memory by the processor and transmitted to the variable node module. Any other process that can retrieve the hard read data is also possible. Generally, the decoder is located within the memory controller and coupled to other components such as the processor via the bus. Therefore, the variable node module can receive hard read data from outside the decoder. After the variable node module receives the hard read data, the value of each bit of the hard read data is assigned to the corresponding variable node unit to generate the codeword to be decoded.

[0096] Determining the checksum vector according to the codeword to be decoded and the aforementioned check matrix can be implemented by multiplying the check matrix by the transpose of the codeword to be decoded to obtain the checksum vector.

[0097] In some examples, the flip indicator module 702 obtains an initial error bit indicator vector using the codeword to be decoded, hard read data, checksum vector, and check matrix. Performing a summation operation on the hard-read data and the codeword to be decoded, and then performing a modulo operation on that sum to obtain a first bit vector, The second bit vector is obtained by multiplying the transpose of the checksum vector by the check matrix, Perform a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector. It is further configured to do so.

[0098] It should be noted that what is described here is a specific operation on how to obtain the initial error bit indicator vector using the codeword to be decoded, hard-read data, checksum vector, and check matrix. In some examples, the first bit vector is obtained by performing a sum operation on the hard-read data (the codeword to be decoded in the first iterative flip) and the codeword to be decoded, and then performing a modulo operation on that sum; the second bit vector is obtained by multiplying the check matrix by the transpose of the checksum vector; and then the aforementioned initial error bit indicator vector is obtained by performing a sum operation on the first and second bit vectors. Here, the number of elements in the first and second bit vectors is the same as the number of bits in the codeword to be decoded.

[0099] In some examples, the above calculation process is expressed by the following formula f1=(y+y0) mod2 + s'H It can be described as, f1 is the initial error bit indicator vector, where each element corresponds to a bit in the codeword to be decoded, y is the codeword to be decoded, y0 is the hard read data, s' is the transpose of the checksum vector, and H is the check matrix.

[0100] Note that in the first flip iteration, y=y0. That is, in the first flip iteration, the codeword to be decoded is the hard-read data, and in the remaining flip iterations, the codeword to be decoded is the hard-read data after bit flipping.

[0101] Based on this, in the examples of this disclosure, the target error bit instruction vector is given by the following formula f2=(y+y0) mod2 + s'H + R It can be expressed as, f2 is the target error bit indicator vector, and R is the soft data.

[0102] In some examples, the flip instruction module 702 is: It is further configured to generate a flip instruction vector according to the number of unsatisfied parity checks and the flipping criteria, the flip instruction vector containing the determined bits in the codeword to be decoded that need to be flipped. The variable node module is further configured to receive a flip instruction vector and flip the bits in the codeword that need to be flipped according to the flip instruction vector.

[0103] Here, the flipping criteria are: Flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flip bits in the codeword to be decoded if the number of unsatisfied parity checks is greater than or equal to a preset threshold. It may include.

[0104] Note that after the target error bit instruction vector is obtained, the number of unsatisfied parity checks for each bit in the codeword to be decoded is obtained. The flip instruction module then obtains a flip instruction vector according to the obtained number of unsatisfied parity checks for each bit and the flipping criteria. The variable node module then flips the bits to be flipped in the codeword to be decoded according to the flip instruction vector. Here, the flipping criteria include, but are not limited here, flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, and flipping the bits in the codeword to be decoded whose number of unsatisfied parity checks is greater than or equal to a preset threshold. In the above description, only the bit corresponding to the largest data in f2 is flipped, or alternatively, the bits in f2 whose data is greater than or equal to T (i.e., the preset threshold) are flipped.

[0105] In some examples, as shown in Figure 12, the decoder 700 further includes a counting module 704 and a termination determination module 705. The counting module 704 is configured to count the number of iterations of hard decision decoding performed on the codeword to be decoded. The termination determination module 705 is configured to determine whether the number of iterations has reached the maximum number of iterations, whether the checksum vector is a zero vector, and to output a first decryption stop signal when the number of iterations has reached the maximum number of iterations and the checksum vector is a non-zero vector, the first decryption stop signal is configured to indicate that hard-decision decoding of the codeword to be decrypted has failed.

[0106] Note that in hard-decision decoding, the number of flipping iterations is limited. The number of flipping iterations can be counted by the counting module 704; that is, the number of iterations is counted by the counting module. The termination module 705 then determines whether the counted number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector. When the maximum number of iterations has been reached and the checksum vector is a non-zero vector, a first decryption stop signal is output. The first decryption stop signal is used to indicate that hard-decision decoding of the codeword to be decrypted has failed.

[0107] In some examples, the decoder 700 further comprises a relocation configuration module 706. The termination determination module 705 is further configured to output a second decryption stop signal when it is determined that the checksum vector is a zero vector, and the second decryption stop signal is configured to indicate that hard-decision decoding of the codeword to be decrypted was successful. The reconfiguration module 706 is configured to perform a reconfiguration on the codeword to be decoded in response to a second decode stop signal, and to output the codeword to be decoded in the correct order.

[0108] Note that the termination determination module 705 outputs a second decryption stop signal, and the reconfiguration module, in response to the second decryption stop signal, performs a reconfiguration process on the codewords to be decrypted, outputs the codewords to be decrypted in the correct order, thereby completing the decryption of the hard read data.

[0109] In some examples, the termination determination module 705 is further configured to output a decryption continuation signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, and the decryption continuation signal is configured to instruct the variable node module, the check node module, and the flip instruction module to continue performing hard-decision decryption operations on the codeword to be decrypted.

[0110] Note that these operations may refer here to an termination determination module that outputs a decryption continuation signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations. The decryption continuation signal instructs the aforementioned variable node module, check node module, and flip instruction module to continue performing a hard-decision decryption operation on the codeword to be decrypted, thereby determining whether the decryption of the codeword to be decrypted is successful or unsuccessful.

[0111] Based on the above description, Figure 13 shows a schematic diagram of a decoder according to an example of the present disclosure. Note that in Figure 13, d represents hard-read data, v represents the codeword to be decoded, S represents the checksum vector, I represents the flip instruction vector, and stop represents the decode stop signal, including a first decode stop signal and a second decode stop signal. Here, the first subconnection network and the second subconnection network together form a variable check node connection network.

[0112] Based on the decoder shown in Figure 13, the decoding workflow provided by the examples of this disclosure may be shown in Figure 14. In some examples, the implementable decoding workflow may be as follows:

[0113] S1401: Hard read data y0 and soft data R are obtained, the hard read data is assigned to the codeword y (y=y0) to be decoded, and the soft data is cached. The number of iterations is 0, where y0 is d in Figure 13 and y is v in Figure 13.

[0114] S1402: Generate a checksum vector using the check matrix and the codeword to be decoded, and determine whether the checksum vector is a zero vector (i.e., H*y T =0?), if yes, execute S1403; otherwise, execute S1404.

[0115] S1403: Output the codeword to be decrypted that was successfully decrypted, and terminate the process.

[0116] S1404: Determine if the number of iterations has reached the maximum number of iterations. If yes, execute S1305; otherwise, execute S1406.

[0117] S1405: Outputs a decoding failure instruction signal, for example, a first decoding stop signal.

[0118] S1406: Use the f2 expression to calculate the number of parity checks that are not filled by the bits in the codeword to be decoded.

[0119] S1407: Determine which bits in the codeword to be decoded need to be flipped, according to the number of unsatisfied parity checks and the flipping criteria.

[0120] S1408: Increase the number of iterations by 1 and proceed to the next iteration, continuing to execute S1402 through S1408 sequentially. Terminate the process when the decryption is successful or unsuccessful.

[0121] Note that the methods for obtaining hard-read and soft-read data in operation S1401 are described above. Specifically, hard-read data can be obtained by receiving feedback directly from the memory of a memory device or memory controller. Soft-read data can be cached in the decoder's cache module and then retrieved from the cache module. The operations described above are just one way of implementing the decoding workflow. The execution order of each operation can be adjusted depending on the actual situation. For example, S1404 may be executed before S1402, in which case it is first determined whether the number of iterations has reached the maximum number of iterations. If the maximum number of iterations has not been reached, a checksum vector is generated using the check matrix and the codeword to be decoded; otherwise, a decoding failure signal is output and the process is terminated.

[0122] According to the decoder provided in the examples of this disclosure, soft data is applied to LDPC bit-flipping (i.e., hard-decision) decoding. The strong error correction capability of soft data is utilized to speed up LDPC bit-flipping decoding, thereby reducing the power consumed by LDPC bit-flipping decoding and improving the error correction processing capability of the decoder.

[0123] One example of this disclosure, as shown in Figure 15, also provides a decryption method, which includes the following:

[0124] S1501: Obtain the soft data corresponding to the codeword to be decoded.

[0125] S1502: When performing hard-decision decoding on a codeword to be decoded, the number of parity checks that are not filled by bits in the codeword to be decoded is determined, with the help of soft data, in at least the first flip iteration.

[0126] In some cases, with the help of soft data, determining the number of parity checks that are not filled by the bits in the codeword to be decoded is possible. Determining the initial error bit indicator vector corresponding to the codeword to be decoded, With the help of soft data combined with an initial error bit indicator vector, the number of parity checks that are not filled by bits in the codeword to be decoded is determined. Includes.

[0127] In some cases, determining the number of parity checks that are not filled by bits in the codeword to be decoded, with the help of soft data combined with an initial error bit indicator vector, Determining the soft data vector corresponding to the soft data, Perform a summation operation on the soft data vector and the initial error bit indicator vector to obtain the target error bit indicator vector, Determine the number of parity checks that are not satisfied by each bit in the codeword to be decoded according to the target error bit instruction vector. Includes, Each element of the target error bit indicator vector corresponds to the number of parity checks that are not filled by one bit.

[0128] In some cases, determining the initial error bit indicator vector corresponding to the codeword to be decoded is The process involves receiving hard-read data and generating a codeword to be decoded according to the hard-read data, Determining the checksum vector according to the codeword to be decoded and the pre-reconstructed check matrix, The process involves determining the initial error bit indicator vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector, and the check matrix. Includes.

[0129] In some examples, determining the hard-read data, the codeword to be decoded, the checksum vector, and the initial error bit indicator vector corresponding to the codeword to be decoded according to the check matrix, Performing a summation operation on the hard-read data and the codeword to be decoded, and then performing a modulo operation on that sum to obtain a first bit vector, The second bit vector is obtained by multiplying the transpose of the checksum vector by the check matrix, Perform a summation operation on the first bit vector and the second bit vector to obtain an initial error bit indicator vector. Includes.

[0130] In some examples, the method is The process involves generating a flip instruction vector according to the number of unsatisfied parity checks and the flipping criteria, wherein the flip instruction vector includes the determined bits in the codeword to be decoded that need to be flipped. Flip the bits in the codeword that need to be flipped according to the flip instruction vector. It also includes.

[0131] In some cases, the flipping criterion is: Flipping the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flip bits in the codeword to be decoded if the number of unsatisfied parity checks is greater than or equal to a preset threshold. Includes.

[0132] In some examples, the method is Counting the number of iterations of hard decision decoding performed on the codeword to be decoded, This involves determining whether the number of iterations has reached the maximum number of iterations, and whether the checksum vector is a zero vector, Outputting a first decryption stop signal when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, wherein the first decryption stop signal is configured to indicate that hard-decision decoding of the codeword to be decrypted has failed. It also includes.

[0133] In some examples, the method is Determine whether the checksum vector is a zero vector, and if it is determined that the checksum vector is a zero vector, output a second decoding stop signal. In response to the second decryption stop signal, a rearrangement and configuration process is performed on the codeword to be decrypted, and the codeword to be decrypted is output in the correct order. It also includes.

[0134] In some examples, the method is The system further includes outputting a decryption continuation signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, the decryption continuation signal being configured to instruct a hard-decision decryption operation to be performed on the codeword to be decrypted.

[0135] It should be noted that the decoding methods provided by the examples in this disclosure are in fact the working process of the decoder presented above. The working process of the decoder is described in detail above, and terms and features appearing herein may be referred to above and not repeated here.

[0136] One example of the present disclosure further provides a memory controller 1600, as shown in Figure 16, the memory controller 1600 comprising a processor 1601 and a decoder 700 as described in any one of the above embodiments, wherein the processor 1601 is configured to read soft data corresponding to a codeword to be decoded from a memory device. The decoder caches soft data and, when performing hard decision decoding on the codeword to be decoded, is configured to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, at least in the first flip iteration.

[0137] Note that the memory controller provided by the examples in this disclosure includes the aforementioned decoder, and therefore the terminology and characteristics of the decoder have been described in detail above and will not be repeated here.

[0138] An example of this disclosure further provides a memory system, the memory system is A memory device configured to store data, A memory controller coupled to a memory device, comprising a processor and a decoder, wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device, and Equipped with, The decoder caches soft data and, when performing hard decision decoding on the codeword to be decoded, is configured to determine, with the help of the soft data, the number of parity checks that are not filled by bits in the codeword to be decoded, at least in the first flip iteration.

[0139] In some examples, the processor is further configured to read hard read data from a memory device and send the hard read data to a decoder. The decoder is further configured to receive hard-read data and generate codewords to be decoded according to the hard-read data.

[0140] In some examples, the decoder comprises a cache module, a variable node module, a check node module, and a flip instruction module. The cache module is configured to cache soft data read by the processor. The variable node module is configured to receive hard-read data read by the processor, generate a codeword to be decoded according to the hard-read data, and send the codeword to be decoded to the check node module. The check node module is configured to receive the codeword to be decrypted sent by the variable node module, determine the checksum vector according to the codeword to be decrypted and the pre-constructed check matrix, and send the checksum vector to the flip instruction module. The flip instruction module is configured to receive hard read data and the codeword to be decoded transmitted by the variable node module, receive the checksum vector transmitted by the check node module, obtain the check matrix and soft data, determine the initial error bit instruction vector corresponding to the codeword to be decoded according to the hard read data, the codeword to be decoded, the checksum vector and the check matrix, and determine the number of parity checks that are not filled by bits in the codeword to be decoded with the help of the soft data combined with the initial error bit instruction vector.

[0141] It should be noted that the memory systems provided by the examples in this disclosure comprise the memory controller described above and a decoder included in the memory controller. Therefore, terms and features appearing herein may be described above and will not be repeated here.

[0142] The foregoing description is merely a specific example of the Disclosure, but the scope of protection provided for in this Disclosure is not limited thereto. Those skilled in the art will readily be able to devise modifications or substitutions within the technical scope of the Disclosure, which will fall within the scope of protection provided for in this Disclosure. [Explanation of Symbols]

[0143] 100 Systems 102 memory systems 104 Memory Devices 106 Memory Controller 108 hosts 202 memory card 204 Memory card connector 206 SSD 208 SSD connectors 301 Host I / F (or Front-end Interface) 302 Memory I / F (or backend interface) 303 Processor 304 memory 305 Error Correction (ECC) Module 400 memory devices 401 memory array 402 Peripheral Circuits 404 Block 406 memory cells 408 NAND memory string 410 Bottom Selective Gate (BSG) 412 Top Selective Gate (TSG) 413 TSG Line 414 Source Line (SL) 415 BSG line 416-bit line (BL) 418 Word lines 501 circuit board 510 Laminated structure 511 Gate Layer 512 Insulating layer 604-page buffer / sense amplifier 606-column decoder / bit line driver 608-line decoder / word line driver 610 Voltage Generator 612 Control Logic 614 registers 616 Interface 618 Data Bus 700 decoders 701 Cache Module 702 Flip Indicator Module 703 Variable Node Module 704 Inspection Node Module 704 Counting Module 705 Termination Determination Module 706 Relocation Configuration Module 1001 Inspection Node 1002 Variable Nodes 1003 Edge 1004A Inspection Node Information 1004B Variable Node Information 1600 Memory Controller 1601 Processor 3051 Encoding Section 3052 Decoding Section

Claims

1. It is a cache module, A cache module configured to cache soft data related to the codeword to be decrypted, It is a flip instruction module, The soft data is obtained from the cache module, wherein the soft data is represented as a soft data vector, Performing hard-decision decoding on the codeword to be decoded and It is configured to do so, In order to perform hard decision decoding on the codeword to be decoded, the flip instruction module, Determining the initial error bit indicator vector corresponding to the codeword to be decoded, The process involves performing vector addition on the soft data vector and the initial error bit indicator vector to obtain the target error bit indicator vector, In at least one of one or more flip iterations, determine, with the help of the soft data, the number of parity checks that are not satisfied by each bit in the codeword to be decoded according to the target error bit indicator vector. It is configured to do so, Each element in the target error bit instruction vector corresponds to the number of parity checks that are not filled by one bit, and the flip instruction module and A decoder equipped with the following features.

2. Test node module and It also includes a variable node module, The aforementioned variable node module is Receiving hard read data and generating the codeword to be decoded according to the hard read data, The codeword to be decrypted is transmitted to the inspection node module, The codeword to be decoded and the hard read data are transmitted to the flip instruction module. It is configured to do so, The variable node module and the check node module are connected to form a variable check connection network according to the check matrix. The aforementioned inspection node module is Receiving the codeword to be decoded, Determining a checksum vector according to the codeword to be decoded and the check matrix, The checksum vector is transmitted to the flip instruction module. It is configured to do so, The aforementioned flip instruction module is Receiving the codeword to be decoded and the hard read data transmitted by the variable node module, Receiving the checksum vector transmitted by the inspection node module, To obtain the aforementioned check matrix and the aforementioned soft data, Determining the hard read data, the codeword to be decoded, the checksum vector, and the initial error bit indicator vector corresponding to the codeword to be decoded according to the check matrix. The decoder according to claim 1, further configured to do the following.

3. The aforementioned flip instruction module is The process involves performing vector addition on the hard read data and the codeword to be decoded, and then performing a modulo operation modulo 2 on the result of the vector addition to obtain a first bit vector, The transpose of the checksum vector is multiplied by the check matrix to obtain a second bit vector, The initial error bit indicator vector is obtained by performing vector addition on the first bit vector and the second bit vector. The decoder according to claim 2, further configured to do the following.

4. The aforementioned flip instruction module is Further configured to generate a flip instruction vector according to the number of unsatisfied parity checks and the flipping criterion, wherein the flip instruction vector includes the determined bits in the codeword to be decoded that need to be flipped. The aforementioned variable node module is The decoder according to claim 2, further configured to receive the flip instruction vector and to flip the bits in the codeword that need to be flipped to be decoded according to the flip instruction vector.

5. The aforementioned flipping criteria are: Flip the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flip the bits in the codeword to be decoded such that the number of unsatisfied parity checks is greater than or equal to a preset threshold. The decoder according to claim 4, including the above.

6. A counting module configured to count the number of iterations of the hard decision decoding performed on the codeword to be decoded, This is a termination determination module, The process involves determining whether the number of iterations has reached the maximum number of iterations, and determining whether the checksum vector is a zero vector. The first decryption stop signal is output when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, wherein the first decryption stop signal is configured to indicate that the hard-decision decoding of the codeword to be decrypted has failed. A termination determination module is configured to do the following: The decoder according to claim 2, further comprising:

7. Further equipped with relocation configuration modules, The termination determination module described above is: The system is further configured to output a second decoding stop signal when the checksum vector is determined to be a zero vector. The aforementioned relocation configuration module is In response to the second decoding stop signal, a rearrangement configuration process is performed on the codeword to be decoded, Output the codewords to be decoded in the correct order. The decoder according to claim 6, configured to do the following.

8. A decoding method performed by a decoder, A step of obtaining soft data corresponding to a codeword to be decoded, wherein the soft data is represented as a soft data vector, Determining the initial error bit indicator vector corresponding to the codeword to be decoded, The process involves performing vector addition on the soft data vector and the initial error bit indicator vector to obtain the target error bit indicator vector, In at least one of one or more flip iterations, determine, with the help of the soft data, the number of parity checks that are not satisfied by each bit in the codeword to be decoded according to the target error bit indicator vector. The steps include performing hard-decision decoding on the codeword to be decoded, Includes, A decoding method wherein each element in the target error bit instruction vector corresponds to the number of parity checks that are not filled by one bit.

9. The step of determining the initial error bit indicator vector corresponding to the codeword to be decoded is: The steps include receiving hard read data and generating the codeword to be decoded according to the hard read data, The steps include determining a checksum vector according to the codeword to be decoded and the check matrix, The steps include determining the hard read data, the codeword to be decoded, the checksum vector, and the initial error bit indicator vector corresponding to the codeword to be decoded according to the check matrix. The method according to claim 8, including the method described in claim 8.

10. The step of determining the hard read data, the codeword to be decoded, the checksum vector, and the initial error bit indicator vector corresponding to the codeword to be decoded according to the check matrix, The steps include performing vector addition on the hard read data and the codeword to be decoded, and then performing a modulo operation modulo 2 on the result of the vector addition to obtain a first bit vector, The steps include: obtaining a second bit vector by multiplying the transpose of the checksum vector by the check matrix; The steps include: obtaining the initial error bit indicator vector by performing vector addition on the first bit vector and the second bit vector; The method according to claim 9, including the method described in claim 9.

11. A step of generating a flip instruction vector according to the number of unsatisfied parity checks and a flipping criterion, wherein the flip instruction vector includes a determined bit in the codeword to be decoded that needs to be flipped, A step of flipping the bits in the codeword that need to be flipped, which are to be decoded according to the flip instruction vector. The method according to claim 8, further comprising:

12. The aforementioned flipping criteria are: Flip the bit in the codeword to be decoded that has the largest number of unsatisfied parity checks, or Flip the bits in the codeword to be decoded such that the number of unsatisfied parity checks is greater than or equal to a preset threshold. The method according to claim 11, including the method described in claim 11.

13. A step of counting the number of iterations of the hard decision decoding performed on the codeword to be decoded, The steps include determining whether the number of iterations has reached the maximum number of iterations and determining whether the checksum vector is a zero vector, A step of outputting a first decryption stop signal when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, wherein the first decryption stop signal indicates that the hard decision decoding of the codeword to be decrypted has failed. The method according to claim 9, further comprising:

14. The steps include determining whether the checksum vector is a zero vector, and outputting a second decoding stop signal when it is determined that the checksum vector is a zero vector, The steps include: performing a rearrangement configuration process on the codeword to be decoded in response to the second decryption stop signal; A step of outputting the codewords to be decoded in the correct order. The method according to claim 13, further comprising:

15. The method according to claim 14, further comprising the step of outputting a decryption continuation signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations, wherein the decryption continuation signal is associated with an instruction to perform a hard-decision decryption operation on the codeword to be decrypted.

16. A memory device configured to store data, A memory controller coupled to the aforementioned memory device The memory controller is equipped with, It is a processor, A processor configured to read soft data corresponding to a codeword to be decoded from the memory device, wherein the soft data is represented as a soft data vector, It is a decoder, The aforementioned soft data is cached, Perform hard-decision decoding on the codeword to be decoded. A decoder configured to do the following: In order to perform hard decision decoding on the codeword to be decoded, the decoder, Determining the initial error bit indicator vector corresponding to the codeword to be decoded, The process involves performing vector addition on the soft data vector and the initial error bit indicator vector to obtain the target error bit indicator vector, In at least one of one or more flip iterations, determine, with the help of the soft data, the number of parity checks that are not satisfied by each bit in the codeword to be decoded according to the target error bit indicator vector. It is configured to do so, A memory system in which each element in the target error bit instruction vector corresponds to the number of parity checks that are not filled by one bit.

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