Dielectric-on-dielectric selective deposition using aniline passivation

Abstract

The method includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to create a passivated surface of the conductive material, and, after exposing the conductive material to aniline, forming a second dielectric layer on the first dielectric layer using a deposition process, wherein the deposition process is a waterless, plasmaless deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the manufacture of electronic devices. In particular, embodiments of the present disclosure relate to dielectric-on-dielectric (DoD) selective deposition using aniline passivation. Background Art

[0002] An electronic device manufacturing apparatus may include a plurality of chambers such as a process chamber and a load lock chamber. Such an electronic device manufacturing apparatus may use a robotic apparatus in a transfer chamber configured to transfer substrates between the plurality of chambers. In some cases, a plurality of substrates are transferred together. In electronic device manufacturing apparatuses, a process chamber may be used to perform one or more processes on a substrate, such as a deposition process and an etching process. In many processes, gas is flowed into the process chamber. Summary of the Invention Problem to be Solved by the Invention

[0003] Electronic devices such as semiconductor devices are manufactured by performing a series of operations that may include deposition, oxidation, photolithography, ion implantation, etching, and the like to form a number of patterned layers. In many cases, it is beneficial to align features between layers. Misalignment of features (e.g., due to limitations of photolithography and / or patterning) may in some cases lead to, for example, short circuits and / or capacitive coupling between a via and an underlying metal line. Such short circuits and / or capacitive coupling may impair the function of the manufactured electronic device. Means for Solving the Problem

[0004] According to one embodiment, a method is provided. The method includes the steps of forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to create a passivation surface of the conductive material, and forming a second dielectric layer on the first dielectric layer using a deposition process after the conductive material has been exposed to aniline. The deposition process is a waterless, plasmaless deposition process, and the second dielectric layer is not formed on the passivation surface of the conductive material.

[0005] According to one embodiment, a system is provided. The system includes a passivation chamber for exposing a conductive material to aniline to create a passivation surface of the conductive material. The conductive material is formed on a first dielectric layer disposed on a substrate. The system further includes a deposition chamber for forming a second dielectric layer on the first dielectric layer using a deposition process after the conductive material has been exposed to aniline. The deposition process is a waterless, plasmaless deposition process, and the second dielectric layer is not formed on the passivation surface of the conductive material.

[0006] This disclosure is illustrated, not limited, in the drawings of the accompanying drawings, where similar reference numerals indicate similar elements. Different references to “an” or “one” embodiments in this disclosure do not necessarily refer to the same embodiment, but rather mean at least one. [Brief explanation of the drawing]

[0007] [Figure 1A] This cross-sectional view illustrates an exemplary method for forming a device in which dielectric-on-dielectric (DoD) selective deposition is carried out using aniline passivation, according to some embodiments. [Figure 1B] This cross-sectional view illustrates an exemplary method for forming a device in which dielectric-on-dielectric (DoD) selective deposition is carried out using aniline passivation, according to some embodiments. [Figure 1C]This cross-sectional view illustrates an exemplary method for forming a device in which dielectric-on-dielectric (DoD) selective deposition is carried out using aniline passivation, according to some embodiments. [Figure 1D] This cross-sectional view illustrates an exemplary method for forming a device in which dielectric-on-dielectric (DoD) selective deposition is carried out using aniline passivation, according to some embodiments. [Figure 2A] This is a flowchart illustrating an exemplary method for performing dielectric-on-dielectric (DoD) selective deposition using aniline passivation, according to some embodiments. [Figure 2B] This is a flowchart illustrating an exemplary method for performing dielectric-on-dielectric (DoD) selective deposition using aniline passivation, according to some embodiments. [Figure 3] This is a block diagram of an exemplary electronic device processing system that can be used to perform dielectric-on-dielectric (DoD) selective deposition using aniline passivation, according to some embodiments. [Modes for carrying out the invention]

[0008] Embodiments described herein relate to dielectric-on-dielectric (DoD) selective deposition using aniline passivation. Electronic devices may include dielectric and conductive materials. For example, an electronic device may include a dielectric layer and several conductive wires disposed within the dielectric layer. More specifically, an electronic device may include several metallization levels, each metallization level including its own set of conductive wires, and each pair of metallization levels being separated by its own dielectric layer (e.g., an interlevel dielectric (ILD) layer). Each conductive wire may be formed within its own trench.

[0009] An electronic device may further contain several vias. A via refers to an electrical connection or contact between conductive wires within an electronic device. Each via can function as an interconnection between at least two metallization levels. For example, a through-via is a via that is exposed at both ends of the device (i.e., a through-via is formed by penetrating each metallization level from the top to the bottom of the device). Another example is a buried via, which is not exposed at either end of the device (i.e., a buried via functions as an interconnection between internal metallization levels). Yet another example is a blind via, which is a via that is exposed at one end of the device.

[0010] Electronic device processing techniques may include performing patterning (e.g., photolithography). For example, patterning may include multiple iterative processes of deposition and etching, such as wet etching or dry etching (e.g., plasma etching), using a photomask ("mask") and a resist film. Exemplaryly, conductive wires and vias can be formed using a suitable patterning process. For example, conductive wires and vias can be formed using a single damascene process in which the conductive wires and vias are formed sequentially. As another example, conductive wires and vias can be formed using a dual damascene process in which the conductive wires and vias can be formed simultaneously (e.g., by simultaneously filling both via holes and trenches with conductive material). Conductive wires and vias can be formed from any suitable conductive material (e.g., metal). Examples of suitable conductive materials that can be used to form conductive wires and vias include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), and others.

[0011] As the size of electronic devices decreases (for example, as transistor sizes decrease), process variations can occur during lithography / patterning (e.g., nanoscale patterning). One example of process variation is poor mask alignment between the mask and the patterned substrate. During exposure, poor mask alignment can result in an edge placement error equal to the distance between the target position of the feature edge and the actual position of the feature edge. Edge placement errors can cause detrimental effects that can lead to degraded device performance, such as short circuits, increased resistance, and capacitive coupling.

[0012] For example, mask misalignment can lead to via misalignment during via patterning, resulting in at least one via being patterned misaligned with respect to the wire. For instance, a well-aligned via is one whose edge is substantially correctly positioned on the corresponding wire (e.g., the via is centered relative to the wire). However, mask misalignment during via patterning can result in edge placement errors for the via's edge (e.g., the via's edge may be formed on a portion of the dielectric layer in the region between its corresponding wire and another adjacent wire).

[0013] Via misalignment can lead to short circuits or capacitive coupling between a via and an adjacent wire, which may be a function of the horizontal spacing between the via and the adjacent wire (e.g., the distance between the bottom surface of the via and the top surface of the adjacent wire). The effects of via misalignment can become more pronounced as transistor size decreases (e.g., on a nanometer (nm) scale). Therefore, as transistor size shrinks further, maintaining a minimum amount of spacing becomes crucial to prevent short circuits or capacitive coupling caused by process variations resulting in via misalignment.

[0014] One example of a method that can be used to address via misalignment is the wire recess method. During the wire recess method, after filling trenches in the dielectric layer with a conductive material (e.g., metal) to form wires, an etching process can be used to recess the wires to a specific depth within each trench. In this way, vias can be formed such that the upper surface of each wire is below the upper surface of the dielectric layer. Therefore, if a via formed on a wire is a misaligned via, the edge of the misaligned via may be formed on the dielectric layer and located at a certain distance above the upper surface of the adjacent wire. This allows for a diagonal separation between the misaligned via and the adjacent wire (e.g., the lower surface of the misaligned via and the upper surface of the adjacent wire). The diagonal separation is a function of the horizontal separation mentioned above and the vertical distance between the misaligned via and the adjacent wire. That is, since the diagonal separation is longer than the horizontal separation, it may help prevent short circuits or capacitive coupling. However, the wire recess method has several drawbacks. For example, the conductive wire recess method may exhibit poor uniformity across the entire wafer and across different pitch sizes, resulting in significant surface roughness of the conductive wires and potentially leading to material degradation.

[0015] Another example of a method that can be used to address process variations such as via misalignment is the dielectric-on-dielectric (DoD) method. The DoD method utilizes a selective dielectric material deposition approach that can, for example, increase the spacing between misaligned vias and adjacent conductive wires. More specifically, after forming conductive wires by filling trenches in a first dielectric layer (e.g., a first ILD) with a conductive material (e.g., a metal), a second dielectric layer can be selectively deposited on the exposed surface of the first dielectric layer. The second dielectric layer can be formed to a height similar to the depth achieved during the recess method described above. Similar to the recess method, if a via formed on a conductive wire is a misaligned via, the edge of the misaligned via may be formed on the second dielectric layer and located at a distance above the adjacent conductive wire. Similar to the recess method, the DoD method can separate misaligned vias and adjacent conductive wires by diagonal spacing that is longer than horizontal spacing, thus helping to prevent short circuits or capacitive coupling.

[0016] The first dielectric layer may include any suitable dielectric material. In some embodiments, the first dielectric layer may include an oxide. In some embodiments, the first dielectric layer may include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include silicon dioxide (SiO2), carbon-doped silicon oxide (e.g., SiOC, SiCOH), silicon nitride (Si3N4), and the like. The second dielectric layer may include any suitable dielectric material. In some embodiments, the second dielectric layer may include an oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include hafnium dioxide (HfO2), titanium dioxide (TiO2), aluminum oxide (Al2O3), SiO2, and the like.

[0017] To carry out a dielectric layer formation method, a second dielectric layer can be selectively deposited on a first dielectric layer, with preference over conductive materials (e.g., Cu, W, Co, Mo, or Ru). Selectivity can be defined, for example, as the ratio of the film thickness on the target surface (e.g., the first dielectric layer) (e.g., the thickness of the second dielectric layer) to the film thickness on the non-target surface (e.g., the conductive material). Other definitions of selectivity can be used.

[0018] Some selective deposition processes can utilize atomic layer deposition (ALD) processes. Some ALD processes can use water (H2O) as an oxidizing agent. However, ALD processes using water as an oxidizing agent may not be compatible with embodiments in which the first dielectric layer is made of a porous hydrophobic dielectric material (e.g., SiCOH). Furthermore, some ALD processes use plasma during film deposition (i.e., plasma-enhanced ALD processes). However, similar to water, ALD processes using plasma may not be compatible with embodiments in which the first dielectric layer is made of a porous hydrophobic dielectric material (e.g., SiCOH).

[0019] To address these and other drawbacks, embodiments described herein can enable dielectric-on-dielectric (DoD) selective deposition using aniline passivation. More specifically, embodiments described herein can achieve selective deposition of a dielectric layer on another dielectric layer in preference to a conductive material. For example, the conductive material can form multiple conductive wires within the first dielectric layer (e.g., at the metallization level). The first dielectric layer can include any suitable dielectric material. In some embodiments, the first dielectric layer can include an oxide. In some embodiments, the first dielectric layer can include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include carbon-doped silicon oxide such as SiO2, SiOC, SiCOH, and Si3N4. The conductive material can include any suitable material. In some embodiments, the conductive material includes a transition metal. Examples of suitable conductive materials include Cu, W, Co, Mo, Ru, and the like.

[0020] More specifically, DoD-selective deposition may involve passivating the conductive material (e.g., conductive wire) by exposing the first dielectric layer and the conductive material to aniline (e.g., vapor-phase aniline). Aniline is an aromatic molecule that may contain amine functional groups bonded to a phenyl group (e.g., C6H5NH2). During aniline exposure, aniline may exhibit weak or no adsorption to the first dielectric layer, but strong adsorption to the surface of the conductive material (e.g., transition metal). The passivation layer can prevent (e.g., block) the adsorption of deposition precursors of the later dielectric (e.g., oxide) onto the conductive layer during the subsequent deposition process to form the second dielectric layer (i.e., prevent nucleation of deposition precursors). Therefore, aniline passivation allows for the selective deposition of a second dielectric layer on the first dielectric layer during the subsequent deposition process, with preference over conductive materials (for example, without depositing the second dielectric layer on the passivated metal layer).

[0021] For example, for some conductive materials, aniline may react with the conductive material and cause dissociation. More specifically, this reaction results in deprotonation (i.e., loss of H atoms from the aniline compound), which may form a bond on the surface of the conductive material (e.g., a phenyl-N-metal bond).

[0022] As another example, for some conductive materials (e.g., Ru), aniline can exhibit two preferred adsorption modes without cleavage of bonds within the aniline compound. One adsorption mode is the π-bond configuration in which the entire aniline compound bonds through delocalized π electrons. The other adsorption mode is a donor-bond configuration where aniline forms a bond (e.g., an N-metal bond) with the conductive layer by donating an electron pair from N to the surface of the conductive material.

[0023] Passivation can be performed using any appropriate process parameters. Examples of process parameters for performing passivation include temperature, exposure time, pressure, etc. In some embodiments, aniline exposure is performed at a temperature ranging from about 100°C to about 350°C. In some embodiments, aniline exposure is performed at a temperature ranging from about 250°C to about 350°C. At sufficiently high temperatures (e.g., temperatures exceeding 350°C), degradation of aniline passivation may occur. Therefore, the passivation process can be performed below a threshold temperature (e.g., about 350°C or lower) to maintain the quality of aniline passivation. In some embodiments, the pressure ranges from about 500 millitorr (mTorr) to about 10 torr. In some embodiments, the pressure ranges from about 750 mTorr to about 780 mTorr.

[0024] In some embodiments, the conductive material is exposed to aniline for about 60 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 50 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 40 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 30 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 20 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 10 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 5 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 1 minute or less.

[0025] In some embodiments, a cleaning process can be performed before passivation of the conductive material (i.e., pre-cleaning). The pre-cleaning process is optional and can improve the selectivity of the second dielectric layer on the first dielectric layer and / or decrease the selectivity of the second dielectric layer on the conductive material. The pre-cleaning process may include surface cleaning to remove native oxides from the surface of the conductive material. The pre-cleaning process can further remove contaminants from the surface of the conductive material. The pre-cleaning process can further reduce the growth of defects on the conductive material. For example, the pre-cleaning process may include thermal ethanol (EtOH) treatment, hydrogen radical treatment, etc.

[0026] The pre-cleaning process can be carried out using any appropriate process parameters. Examples of process parameters for pre-cleaning include time, temperature, and pressure. For example, thermal EtOH treatment can be carried out for a time in the range of about 1 minute to about 30 minutes (e.g., about 5 minutes) and a temperature in the range of about 200°C to about 300°C (e.g., about 250°C). In some embodiments, the pressure is in the range of about 100 mTorr to about 10 torr. In some embodiments, the pressure is in the range of about 500 mTorr to about 10 torr. In some embodiments, the pressure is in the range of about 1 torr to about 10 torr.

[0027] After passivation (and optional pre-cleaning before passivation), a deposition process can be used to selectively form a second dielectric layer on the exposed surface of the first dielectric layer. The second dielectric layer may include any suitable dielectric material. In some embodiments, the second dielectric layer may include an oxide. For example, the second dielectric layer may include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include hafnium dioxide (HfO2), titanium dioxide (TiO2), aluminum oxide (Al2O3), SiO2, and the like. In some embodiments, the second dielectric layer may include a nanolaminate to ensure an amorphous structure. The second dielectric layer can be deposited on the first dielectric layer to a target thickness (e.g., by performing an appropriate number of deposition cycles). As described above, the passivation layer formed during aniline passivation can prevent (e.g., block) the deposition precursor from adsorbing onto the conductive material. Thus, aniline passivation can prevent (e.g., inhibit) the formation of the second dielectric layer on the conductive material. Therefore, aniline passivation allows the thickness of the dielectric layer deposited on the conductive material during the deposition process to be negligible (for example, less than about 1 nm thick).

[0028] The deposition process can be a water-free and plasma-free deposition process. For example, water and / or plasma can cause desorption of the adsorbed passivation layer. Therefore, the conductive material can be exposed to aniline once before the deposition process (i.e., it may not be necessary to expose the conductive material to aniline multiple times). Furthermore, since the deposition process does not use water, the first dielectric layer can be formed from a porous hydrophobic dielectric (e.g., SiCOH).

[0029] In some embodiments, the deposition process is a chemical vapor deposition (CVD) process. For example, the CVD process can be a pulsed CVD process. During the pulsed CVD process, a material can be formed by alternately executing deposition precursor pulses and purge gas pulses. The purge gas may be any suitable inert gas. For example, the purge gas may be argon gas (Ar), nitrogen gas (N2), etc.

[0030] The deposition process can utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes the deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide (Hf(OtBu)4) for forming HfO2, titanium isopropoxide (Ti(OiPr)4) for forming TiO2, aluminum isopropoxide (Al(OiPr)3) for forming Al2O3, aluminum tri-sec-butoxide (Al[OCH(CH3)C2H5]3) for forming Al2O3, tetraethoxysilane or tetraethyl orthosilicate (TEOS) (Si(OC2H5)4) for forming SiO2, tetrabutoxysilane or tetrabutyl orthosilicate (TBOS) (Si(OC4H9)4) for forming SiO2, and tetramethoxysilane or tetramethyl orthosilicate (TMOS) (Si(OCH3)4) for forming SiO2. The process parameters of a deposition process (e.g., a CVD process) may depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0031] Examples of process parameters for performing a pulsed CVD process include temperature, number of deposition precursor pulses, pulse length (i.e., duration of each deposition precursor pulse), purge length (i.e., duration of each purge pulse between deposition precursor pulses), pressure (deposition precursor vapor pressure), and purge gas pressure. In some embodiments, the pulsed CVD process can be performed at temperatures ranging from approximately 100°C to approximately 400°C. In some embodiments, the pulsed CVD process can be performed at temperatures ranging from approximately 300°C to approximately 350°C. In some embodiments, the number of deposition precursor pulses ranges from approximately 1 pulse to approximately 1000 pulses. In some embodiments, the number of deposition precursor pulses ranges from approximately 4 pulses to approximately 500 pulses. In some embodiments, the number of deposition precursor pulses ranges from approximately 50 pulses to approximately 250 pulses. In some embodiments, the pulse length ranges from approximately 0.1 seconds to approximately 4 seconds. In some embodiments, the purge length ranges from approximately 0.1 seconds to approximately 10 seconds.

[0032] Next, further details regarding the formation of a device for performing DoD-selective deposition using aniline passivation are described below with reference to Figures 1A to 1D.

[0033] Figures 1A to 1D are cross-sectional views illustrating exemplary methods for forming a device 100 that performs dielectric-on-dielectric selective deposition using aniline passivation, according to some embodiments. As shown in Figure 1A, a dielectric layer 110-1 may be provided, and a plurality of conductive wires, including conductive wires 120-1 and 120-2, may be formed within the dielectric layer 110-1. More specifically, the dielectric layer 110-1 may be an interlevel dielectric (ILD) layer, and the conductive wires 120-1 and 120-2 may correspond to a first metallization level within the device 100. Forming a plurality of conductive wires may include forming a plurality of trenches within the dielectric layer 110-1 using an etching process, and forming a conductive material within the plurality of trenches to form the plurality of conductive wires. More specifically, each trench corresponds to a respective conductive wire. The dielectric layer 110-1 and the conductive wires 120-1 and 120-2 may, in embodiments, be incorporated within a base structure on a substrate such as a semiconductor wafer.

[0034] Although not shown, the base structure may include one or more additional layers such that the dielectric layer 110-1 and multiple conductive wires are arranged on this one or more additional layer. For example, device 100 may further include at least a substrate layer (e.g., a silicon (Si) substrate) (not shown) as an initial layer of the device.

[0035] The dielectric layer 110-1 may include any suitable dielectric material. In some embodiments, the dielectric layer 110-1 may include an oxide (e.g., a metal oxide). In some embodiments, the dielectric layer 110-1 may include a nitride (e.g., a metal nitride). Examples of suitable dielectric materials include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. Conductive wires 120-1 and 120-2 can be formed from any suitable conductive material (e.g., a metal). In some embodiments, conductive wires 120-1 and 120-2 are formed from conductive materials containing transition metals. Examples of suitable conductive materials that can be used to form conductive wires 120-1 and 120-2 include Cu, W, Co, Mo, Ru, etc.

[0036] As shown in Figure 1B, the dielectric layer 130 is selectively deposited on the dielectric layer 110-1. The deposition can be carried out, for example, using a CVD process. Other deposition processes can also be used to produce the dielectric layer 130. The dielectric layer 130 can contain any suitable dielectric material. In some embodiments, the dielectric layer 130 can contain an oxide. For example, the dielectric layer 130 can contain a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include HfO2, TiO2, Al2O3, and SiO2.

[0037] More specifically, selectively depositing the dielectric layer 130 involves performing a passivation process by exposing the dielectric layer 110-1 and the conductive wires 120-1 and 120-2 to aniline (e.g., vapor-phase aniline). By exposing the conductive wires 120-1 and 120-2 to aniline, passivation surfaces can be created on the surfaces of the conductive wires 120-1 and 120-2.

[0038] More specifically, aniline reacts with conductive wires 120-1 and 120-2 to form a passivation layer adsorbed onto the surfaces of conductive wires 120-1 and 120-2. The passivation layer may contain by-products of the aniline reaction adsorbed onto the surfaces of conductive wires 120-1 and 120-2. The passivation layer can prevent (e.g., block) the growth of the dielectric layer 130 on conductive wires 120-1 and 120-2 by preventing (e.g., blocking) the adsorption of deposition precursors during the deposition of the dielectric layer 130. In some embodiments, the passivation layer has a single-layer thickness.

[0039] The passivation process can be carried out using any appropriate process parameters. For example, the passivation process can be thermal aniline exposure. In some embodiments, the passivation process is carried out once to form a single passivation layer. Examples of process parameters for carrying out the passivation process include temperature, exposure time, and pressure. In some embodiments, the aniline exposure is carried out at temperatures in the range of about 100°C to about 400°C. In some embodiments, the aniline exposure is carried out at temperatures in the range of about 250°C to about 350°C. In some embodiments, the pressure is in the range of about 500 mTorr to about 10 torr. In some embodiments, the pressure is in the range of about 750 mTorr to about 780 mTorr.

[0040] In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 60 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 50 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 40 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 30 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 20 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 10 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 5 minutes or less. In some embodiments, conductive wires 120-1 and 120-2 are exposed to aniline for a time of about 1 minute or less.

[0041] In some embodiments, a pre-cleaning process can be performed before passivation of the conductive wires 120-1 and 120-2. The pre-cleaning process can improve the selectivity of the dielectric layer 130 on the dielectric layer 110-1 and / or reduce the selectivity of the dielectric layer 130 on the conductive wires 120-1 and 120-2. The pre-cleaning process may include surface cleaning to remove native oxides from the surfaces of the conductive wires 120-1 and 120-2. The pre-cleaning process may further remove contaminants from the surfaces of the conductive wires 120-1 and 120-2. The pre-cleaning process may further reduce the growth of defects on the conductive wires 120-1 and 120-2. For example, the pre-cleaning process may include thermal EtOH treatment, hydrogen radical treatment, etc. Exemplary, the pre-cleaning process may include a continuous EtOH administration at a temperature in the range of about 200°C to about 300°C (e.g., about 250°C) for a time in the range of about 4 minutes to about 6 minutes (e.g., about 5 minutes) before passivation. In some embodiments, the pressure is in the range of approximately 100 mTorr to approximately 10 torr. In some embodiments, the pressure is in the range of approximately 500 mTorr to approximately 10 torr. In some embodiments, the pressure is in the range of approximately 1 torr to approximately 10 torr.

[0042] After passivation (and optional pre-cleaning before passivation), a dielectric layer 130 can be formed using a deposition process. More specifically, the dielectric layer 130 can be selectively deposited on the exposed surface of the dielectric layer 110. The deposition process can be a waterless deposition process or a plasmaless deposition process. In some embodiments, the deposition process is a CVD process. For example, the CVD process can be a pulsed CVD process. Other deposition processes can also be used. Aniline passivation allows the thickness of the dielectric layer deposited on the conductive material during the deposition process to be negligible (e.g., less than about 1 nm thick). This thin dielectric layer may be removed during further processing (e.g., during a subsequent metal deposition process and / or cleaning process).

[0043] The deposition process can utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide for forming HfO2, titanium isopropoxide for forming TiO2, aluminum isopropoxide for forming Al2O3, aluminum tri-sec-butoxide for forming Al2O3, TEOS for forming SiO2, TBOS for forming SiO2, and TMOS for forming SiO2. The process parameters of the deposition process (e.g., a CVD process) may depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0044] Examples of process parameters for executing a pulsed CVD process include temperature, number of pulses, pulse length (i.e., the length of time the deposition precursor is pulsed), purge length (i.e., the length of time the purge gas (e.g., Ar or N2) is introduced between pulses), deposition precursor vapor pressure, and purge gas pressure. For example, the pulsed CVD process can be performed at temperatures ranging from approximately 100°C to approximately 400°C. As another example, the pulse length can range from approximately 0.1 seconds to approximately 4 seconds. As yet another example, the purge length can range from approximately 0.1 seconds to approximately 10 seconds. Further details regarding the deposition process are described below with reference to Figures 2A and 2B.

[0045] After forming the dielectric layer 130, an optional post-cleaning process can be performed. Performing a post-cleaning process may include removing the passivation layer and / or a thin dielectric layer from the surface of the conductive material. For example, performing a post-cleaning process may include heating the device to a temperature of 350°C or higher. Heating the device to a temperature of 350°C or higher can cause the passivation layer to delaminate. As another example, performing a post-cleaning process may further include removing defects (e.g., portions of dielectric material that may have formed on the conductive material during the deposition process). As yet another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process.

[0046] As shown in Figure 1C, after selectively depositing a dielectric layer 130 on a dielectric layer 110-1, a plurality of conductive wires and a dielectric layer 110-2 can be formed on the dielectric layer 130. More specifically, the dielectric layer 110-2 can be a second ILD layer. The dielectric layer 110-2 can contain any suitable dielectric material. In some embodiments, the dielectric layer 110-2 can contain an oxide. In some embodiments, the dielectric layer 110-2 can contain a nitride. Examples of suitable dielectric materials include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. In some embodiments, the dielectric layer 110-2 contains the same dielectric material as the dielectric layer 110-1. In some embodiments, the dielectric layer 110-2 contains a different dielectric material than the dielectric layer 110-1.

[0047] As shown in Figure 1D, at least one via 140 is formed. More specifically, the via 140 can be formed in contact with at least one conductive wire 120-2. Further as shown in this exemplary example, at least one conductive wire 150 is formed. More specifically, the conductive wire 150 can correspond to a second metallization level different from the first metallization level (i.e., at least one metallization level higher than the first metallization level).

[0048] Forming the vias 140 and conductive wires 150 may include forming trenches within the dielectric layer 110-2, forming via holes within the dielectric layer 110-2, and forming conductive material within the trenches and via holes. In some embodiments, the vias 140 and conductive wires 150 are formed simultaneously (e.g., using a dual damascene process). In some embodiments, the vias 140 and conductive wires 150 are formed sequentially (e.g., using a single damascene process).

[0049] The vias 140 and conductive wires 150 may include any suitable conductive material (e.g., metal). In some embodiments, the vias 140 and conductive wires 150 are formed from a conductive material including a transition metal. Examples of suitable conductive materials that can be used to form the vias 140 and conductive wires 150 include Cu, W, Co, Mo, Ru, and the like. In some embodiments, the vias 140 and conductive wires 150 may include the same material as conductive wires 120-1 and 120-2. In some embodiments, the vias 140 and conductive wires 150 may include a different material from conductive wires 120-1 and 120-2.

[0050] As shown in Figure 1D, via 140 in this example is an offset via whose edge is located on the dielectric layer 130 between conductive wires 120-1 and 120-2. The distance between via 140 and conductive wire 120-1 is indicated by the diagonal line "D" in Figure 1D. Diagonal line D is longer than the horizontal line that would indicate the separation between via 140 and conductive wire 120-1 in the absence of the dielectric layer 130. Therefore, the formation of the dielectric layer 130 can improve the performance of device 100 by reducing short circuits or capacitive coupling between via 140 and conductive wire 120-1. Further details regarding the formation of device 100 are described below with reference to Figures 2A and 2B.

[0051] Figure 2A shows an exemplary method 200 for performing DoD-selective deposition using aniline passivation, according to some embodiments. Method 200 can be performed within an electronic device processing system. More specifically, Method 200 can be performed within one or more process chambers of an electronic device processing system. Further details regarding the electronic device processing system are described below with reference to Figure 3.

[0052] In step 210, the first conductive material is formed on the first dielectric layer. For example, the first dielectric layer may be provided, and the first conductive material may be formed on the first dielectric layer. In some embodiments, forming the first conductive material includes forming a plurality of conductive wires within the first dielectric layer. More specifically, the first dielectric layer may be an ILD layer, and the plurality of conductive wires may correspond to a first metallization level in the device. Forming the plurality of conductive wires may include forming a plurality of trenches within the first dielectric layer using an etching process, and forming the conductive material within the plurality of trenches to form the plurality of conductive wires. More specifically, each trench corresponds to a respective conductive wire.

[0053] The first dielectric layer and conductive material (e.g., multiple conductive wires) can be included within the base structure. The base structure may include one or more additional layers on which the first dielectric layer and conductive material are arranged. For example, the device may further include at least a substrate layer (e.g., a silicon (Si) substrate) as an initial layer of the device.

[0054] The first dielectric layer may include any suitable dielectric material. In some embodiments, the first dielectric layer may include an oxide. In some embodiments, the first dielectric layer may include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. The conductive material may include any suitable conductive material (e.g., a metal). In some embodiments, the conductive material may include a transition metal. Examples of suitable conductive materials include Cu, W, Co, Mo, Ru, etc.

[0055] In step 220, a second dielectric layer is selectively deposited on the first dielectric layer using a deposition process. The second dielectric layer may include any suitable dielectric material. In some embodiments, the second dielectric layer may include an oxide. For example, the second dielectric layer may include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include HfO2, TiO2, Al2O3, SiO2, etc. More specifically, selectively depositing the second dielectric layer may include passivating a conductive material (e.g., multiple conductive wires) with aniline. Further details regarding the selective deposition of the second dielectric layer are described below with reference to Figure 2B.

[0056] Figure 2B shows an exemplary method 220, according to some embodiments, for selectively depositing a second dielectric layer on a first dielectric layer using aniline passivation. Method 220 can be performed within an electronic device processing system. More specifically, Method 220 can be performed within one or more process chambers of an electronic device processing system.

[0057] In step 222, a pre-cleaning process is optionally performed. More specifically, a base structure including a conductive material formed on a first dielectric layer (e.g., multiple conductive wires arranged within the first dielectric layer) can be cleaned. The pre-cleaning process can improve the selectivity of the second dielectric layer formed on the first dielectric layer and / or reduce the selectivity of the second dielectric layer formed on the conductive material. The pre-cleaning process may include surface cleaning to remove native oxides from the surface of the conductive material. The pre-cleaning process may further remove contaminants from the surface of the conductive material. The pre-cleaning process may further reduce the growth of defects on the conductive material. For example, pre-cleaning may include thermal EtOH treatment, hydrogen radical treatment, etc. Exemplary, the pre-cleaning process may include a continuous EtOH administration at a temperature in the range of about 200°C to about 300°C (e.g., about 250°C) for a time in the range of about 4 minutes to about 6 minutes (e.g., about 5 minutes) prior to passivation. In some embodiments, the pressure is in the range of about 100 mTorr to about 10 torr. In some embodiments, the pressure ranges from approximately 500 mTorr to approximately 10 torr. In some embodiments, the pressure ranges from approximately 1 torr to approximately 10 torr.

[0058] In step 224, the first conductive material is exposed to aniline. In some embodiments, the aniline includes vapor-phase aniline. More specifically, the first conductive material (and the first dielectric layer) can be exposed to aniline to create a passivation surface of the conductive material. The aniline can react strongly with the first conductive material to adsorb onto the surface of the conductive material and form a passivation layer that prevents (e.g., blocks) the growth of the second dielectric layer on the conductive material. More specifically, the passivation layer can prevent (e.g., block) the adsorption of a deposition precursor used in a subsequent deposition process to form the second dielectric layer onto the surface of the first conductive material. In some embodiments, the first conductive material is exposed to aniline during a single passivation process to form a single passivation layer. In some embodiments, the passivation layer has a single-layer thickness. However, the passivation layer can have any suitable thickness according to the embodiments described herein.

[0059] Aniline exposure can be carried out at an appropriate temperature. For example, aniline exposure can be carried out at a temperature in the range of about 100°C to about 400°C. Aniline exposure can be carried out for any appropriate time. In some embodiments, conductive materials are exposed to aniline for a time in the range of about 30 minutes to about 60 minutes. For example, conductive materials can be exposed to aniline for about 40 minutes.

[0060] In step 226, a second dielectric layer is formed using a deposition process. More specifically, the second dielectric layer can be selectively deposited on the exposed surface of the first dielectric layer. As described above, the passivation layer formed on the conductive material to form the second dielectric layer prevents (e.g., blocks) the adsorption of the deposition precursor used during the deposition process. The deposition process can be a waterless deposition process or a plasmaless deposition process. In some embodiments, the deposition process is a CVD process. For example, the CVD process can be a pulsed CVD process. Aniline passivation allows the thickness of the dielectric layer deposited on the conductive material during the deposition process to be negligible (e.g., less than about 1 nm thick).

[0061] The deposition process can utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide for forming HfO2, titanium isopropoxide for forming TiO2, aluminum isopropoxide for forming Al2O3, aluminum tri-sec-butoxide for forming Al2O3, TEOS for forming SiO2, TBOS for forming SiO2, and TMOS for forming SiO2. The process parameters of the deposition process (e.g., a CVD process) may depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0062] Examples of process parameters for performing a pulsed CVD process include temperature, number of deposition precursor pulses, pulse length (i.e., duration of each deposition precursor pulse), purge length (i.e., duration of each purge pulse between deposition precursor pulses), pressure (deposition precursor vapor pressure), and purge gas pressure. In some embodiments, the pulsed CVD process can be performed at temperatures ranging from approximately 100°C to approximately 400°C. In some embodiments, the pulsed CVD process can be performed at temperatures ranging from approximately 300°C to approximately 350°C. In some embodiments, the number of deposition precursor pulses ranges from approximately 1 pulse to approximately 1000 pulses. In some embodiments, the number of deposition precursor pulses ranges from approximately 4 pulses to approximately 500 pulses. In some embodiments, the number of deposition precursor pulses ranges from approximately 50 pulses to approximately 250 pulses. In some embodiments, the pulse length ranges from approximately 0.1 seconds to approximately 4 seconds. In some embodiments, the purge length ranges from approximately 0.1 seconds to approximately 10 seconds.

[0063] As an exemplary example, assume that the first dielectric layer contains SiO2 and the conductive material is passivated by aniline exposure as described above. Furthermore, assume that the second dielectric layer contains HfO2. HfO2 can be deposited on SiO2 using a pulsed CVD process with a hafnium tert-butoxide precursor at temperatures in the range of approximately 250°C to approximately 350°C (e.g., approximately 300°C). The vapor pressure of the hafnium tert-butoxide precursor can be approximately 0.1 mTorr to approximately 0.5 mTorr (e.g., approximately 0.3 mTorr). A time interval of approximately 60 seconds can exist between each pulse of the hafnium tert-butoxide precursor. A purge gas (e.g., Ar or N2) with a pressure of approximately 120 mTorr can be used during each purge pulse between the hafnium tert-butoxide precursor pulses. Pulsing a hafnium tert-butoxide precursor approximately 60 times allows for the deposition of HfO2 with a thickness of approximately 5 nm onto SiO2.

[0064] As another exemplary example, suppose the first dielectric layer contains SiO2 and the conductive material is passivated by aniline exposure as described above. Furthermore, suppose the second dielectric layer contains Al2O3. Al2O3 can be deposited on SiO2 using a pulsed CVD process with an aluminum tri-sec-butoxide precursor at temperatures in the range of about 300°C to about 375°C (e.g., about 330°C). The vapor pressure of the aluminum tri-sec-butoxide precursor can be about 0.1 mTorr to about 0.5 mTorr (e.g., about 0.3 mTorr). A time interval of about 60 seconds can exist between each pulse of the aluminum tri-sec-butoxide precursor. A purge gas (e.g., Ar or N2) with a pressure of about 120 mTorr can be used during each purge pulse between the aluminum tri-sec-butoxide precursor pulses. Pulsing an aluminum tri-sec-butoxide precursor approximately 200 times allows for the deposition of Al2O3 particles of about 5 nm on SiO2.

[0065] In step 228, an optional post-cleaning process may be performed. More specifically, the post-cleaning process may be performed after the formation of the second dielectric layer. Performing the post-cleaning process may include removing the passivation layer from the surface of the conductive material. For example, performing the post-cleaning process may include heating the device to a temperature of 350°C or higher. As another example, performing the post-cleaning process may further include removing defects (e.g., portions of dielectric material that may have formed on the conductive material during the deposition process). As yet another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process.

[0066] Referring again to Figure 2A, in step 230, a third dielectric layer is formed on the second dielectric layer and the conductive material. For example, the third dielectric layer can be the second ILD layer. The third dielectric layer can contain any suitable dielectric material. In some embodiments, the third dielectric layer can contain an oxide. In some embodiments, the third dielectric layer can contain a nitride. Examples of suitable dielectric materials that can be used to form the third dielectric layer include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. In some embodiments, the third dielectric layer contains the same dielectric material as the first dielectric layer (i.e., the first ILD layer). In some embodiments, the third dielectric layer contains a different dielectric material than the first dielectric layer.

[0067] In step 240, a second conductive material is formed on the third dielectric layer. In some embodiments, forming the second conductive material includes forming vias within the third dielectric layer. For example, the first end of a via can be in contact with at least a portion of the first conductive wires among a plurality of conductive wires. In some embodiments, forming the second conductive material further includes forming a second conductive wire. More specifically, the second conductive wire can be located at the second end of a via. The second conductive wire can correspond to a second metallization level different from the first metallization level (i.e., a metallization level at least one higher than the first metallization level).

[0068] Forming vias and second conductive wires may include forming trenches in a third dielectric layer, forming via holes in the third dielectric layer, and forming conductive material in the trenches and via holes. In some embodiments, vias and second conductive wires may be formed simultaneously (e.g., using a dual damascene process). In some embodiments, vias and second conductive wires may be formed sequentially (e.g., using a single damascene process).

[0069] The second conductive material may include any suitable conductive material (e.g., a metal). Examples of conductive materials suitable for the second conductive material include Cu, W, Co, Mo, Ru, etc. In some embodiments, the first conductive material includes the same material as the second conductive material. In some embodiments, the first conductive material includes a different material from the second conductive material. Further details regarding steps 210 to 240 are described above with reference to Figures 1A to 1D.

[0070] Figure 3 is a block diagram of an exemplary electronic device processing system ("System") 300 that can be used to form a device that performs DoD selective deposition using CVD, according to some embodiments. For example, System 300 can be used to form the device 100 described above with reference to Figures 1A to 1D, and can be used to carry out the method 200 described above with reference to Figures 2A to 2B.

[0071] As illustrated, system 300 includes a passivation chamber 310, a transfer chamber 320, and a deposition chamber 330. Interface 340-1 may be located between the passivation chamber 310 and the transfer chamber 320, and interface 340-2 may be located between the transfer chamber and the deposition chamber 330. In some embodiments, interfaces 340-1 and 340-2 are gate valves, respectively. The transfer chamber 320 may include a transfer robot (not shown). The transfer chamber 320, the passivation chamber 310, and the deposition chamber 330 may each be maintained under vacuum under controlled conditions (e.g., little to no humidity). Although not illustrated, system 300 may further include at least one load lock chamber and at least one factory interface to allow the transfer of substrates from the atmosphere to the transfer chamber 320. Thus, substrates can be transferred between chambers without breaking the vacuum and therefore without exposing the substrates to air and / or moisture.

[0072] The passivation chamber 310 can receive a substrate containing a first dielectric layer and a conductive material, and can passivate the conductive material by exposing the conductive material to aniline. For example, the aniline may include vapor-phase aniline. The passivation chamber 310 can be operably coupled to at least one passivation gas storage unit 312. For example, at least one passivation gas storage unit 312 may include an aniline storage unit. At least one passivation gas storage unit 312 may further include a purge gas storage unit. The purge gas storage unit may include any suitable inert gas (e.g., Ar or N2) for purging the passivation chamber 312 during the passivation process. The passivation process can be carried out using any suitable passivation process parameters. Further details regarding the passivation of conductive materials with aniline are described above with reference to Figures 1A to 2B.

[0073] After passivating the conductive material, the transfer robot can transfer the substrate to the deposition chamber 330. Upon receiving the substrate, the deposition chamber 330 can perform a deposition process to selectively form a second dielectric layer on the first dielectric layer. More specifically, the deposition process can be a waterless and plasmaless deposition process. In some embodiments, the deposition process is a CVD process. For example, the deposition process can be a pulsed CVD process.

[0074] The deposition chamber 330 can be operably coupled to a deposition precursor storage unit 332 and a purge gas storage unit 334. The deposition precursor storage unit 332 may contain any suitable deposition precursor for forming a second dielectric layer. The purge gas storage unit 334 may contain any suitable inert gas (e.g., Ar or N2) for purging the deposition chamber 330 during the deposition process. The deposition process can be carried out using any suitable deposition process parameters. Further details regarding carrying out the deposition process are described above with reference to Figures 1A to 2B.

[0075] In some embodiments, the deposition process is performed in a passivation chamber 310 (i.e., the passivation chamber 310 is a process chamber configured to perform both the passivation and deposition processes). In these embodiments, the deposition precursor storage unit 332 and the purge gas storage unit 334 can be operably coupled to the passivation chamber 310. In some embodiments, the passivation process is performed in a deposition chamber 330 (i.e., the deposition chamber 330 is a process chamber configured to perform both the passivation and deposition processes). In these embodiments, at least one passivation gas storage unit 312 can be operably coupled to the deposition chamber 330.

[0076] In some embodiments, the system 300 may optionally include a cleaning chamber 350 for performing an optional cleaning process before passivation (i.e., a pre-cleaning process) and / or an optional cleaning process after the formation of a second dielectric layer (i.e., a post-cleaning process). Interface 340-3 may be located between the cleaning chamber 350 and the transfer chamber 320. In some embodiments, the cleaning chamber 350 is an in-situ cleaning chamber and interface 340-3 is a gate valve. In some embodiments, the cleaning chamber 350 is an ex-situ cleaning chamber and interface 340-3 is a load lock chamber.

[0077] For example, the pre-cleaning process can be thermal EtOH treatment. Alternatively, the pre-cleaning process can be hydrogen radical treatment. The pre-cleaning and / or post-cleaning processes can be performed using any appropriate pre-cleaning process parameters.

[0078] For example, performing a post-cleaning process may include heating the device to a temperature of 350°C or higher. As another example, performing a post-cleaning process may further include removing defects (e.g., portions of dielectric material that may have formed on the conductive material during the deposition process). As yet another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process. The post-cleaning process can be performed using any appropriate post-cleaning process parameters.

[0079] The cleaning chamber 350 can be operably coupled to at least one cleaning gas storage unit 352. The at least one cleaning gas storage unit 352 may contain a suitable cleaning chemical. For example, the at least one cleaning gas storage unit 352 may contain an ethanol storage unit for performing thermal EtOH cleaning. The at least one passivation gas storage unit 312 may further contain a purge gas storage unit. The purge gas storage unit may contain any suitable inert gas (e.g., Ar or N2) for purging the cleaning chamber 352.

[0080] In some embodiments, the pre-cleaning process can be performed in the same chamber as the passivation (e.g., the passivation chamber 310 or the deposition chamber 330). In these embodiments, at least one clean gas storage unit 352 can be operably coupled to the passivation chamber 310 and / or the deposition chamber 330. In some embodiments, the post-cleaning process can be performed in the passivation chamber 310 and / or the deposition chamber 330. In these embodiments, at least one clean gas storage unit 352 can be operably coupled to the passivation chamber 310 and / or the deposition chamber 330. Further details regarding the execution of the cleaning processes (e.g., the pre-cleaning process and / or post-cleaning process) are described above with reference to Figures 1A to 2B.

[0081] The foregoing description includes numerous specific details, such as examples of particular systems, components, and methods, in order to provide a good understanding of some embodiments of the Disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the Disclosure can be implemented without these specific details. In other cases, well-known components or methods are not described in detail or are presented in simple block diagram form in order to avoid unnecessarily obscuring the Disclosure. Thus, the specific details described are merely illustrative. Certain embodiments may differ from these exemplary details and are still intended to be within the scope of the Disclosure.

[0082] Throughout this specification, any reference to “one embodiment” or “a particular embodiment” means that a specific feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment. Therefore, occurrences of the phrase “in one embodiment” or “a particular embodiment” in various places throughout this specification do not necessarily all refer to the same embodiment. In addition, the term “or” is intended to mean inclusive “or” rather than exclusive “or.” Where the terms “about” or “approximately” are used herein, this is intended to mean that the presented nominal values ​​are accurate within ±10%.

[0083] Although the operations of the methods described herein are shown and described in a specific order, the order of operations of each method may be modified so that certain operations can be performed in reverse order, or so that certain operations can be performed at least partially concurrently with other operations. In another embodiment, instructions or suboperations of separate operations may be performed intermittently and / or alternately.

[0084] It should be understood that the above description is illustrative and not limiting. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the above description. Therefore, the scope of this disclosure should be determined by reference to the appended claims, together with the entire scope of equivalents to which such claims are granted.

Claims

1. The steps include forming a conductive material in at least one trench formed in the first dielectric layer, A step of exposing the conductive material to aniline at a temperature of 350°C or lower for 60 minutes or less to generate a passivation surface of the conductive material, A step of forming a second dielectric layer on the first dielectric layer by exposing the conductive material to aniline and then performing a pulsed chemical vapor deposition (CVD) process using a set of process parameters, wherein the pulsed CVD process is a deposition process that does not use water or plasma, the second dielectric layer is not formed on the passivation surface of the conductive material, and the set of process parameters is Temperatures below 350°C, The number of deposition precursor pulses in the range of 50 pulses to 250 pulses, A deposition precursor pulse length in the range of 0.1 seconds to 4 seconds, Steps including, Methods that include...

2. The method according to claim 1, further comprising the step of performing a pre-cleaning process to reduce native oxides on the surface of the conductive material before exposing the conductive material to aniline.

3. The method according to claim 1, wherein the conductive material includes conductive wires associated with the metallization level of the device, and the first dielectric layer is an interlevel dielectric (ILD) layer of the device.

4. The method according to claim 1, wherein the first dielectric layer comprises at least one of silicon dioxide, carbon-doped silicon oxide, or silicon nitride.

5. The method according to claim 1, wherein the conductive material includes a transition metal.

6. The method according to claim 1, wherein the second dielectric layer contains a metal oxide.

7. The steps include forming a third dielectric layer on the second dielectric layer and the conductive material, The steps include forming a second conductive material on the third dielectric layer, The method according to claim 1, further comprising:

8. The method according to claim 7, wherein the second conductive material includes vias and the first dielectric layer is an interlevel dielectric (ILD) layer.

9. A system comprising at least one chamber, wherein the at least one chamber is The conductive material in at least one trench formed in the first dielectric layer is exposed to aniline at a temperature of 350°C or less for 60 minutes or less to generate a passivation surface of the conductive material. The conductive material is exposed to aniline, and then a second dielectric layer is formed on the first dielectric layer by performing a pulsed chemical vapor deposition (CVD) process using a set of process parameters, wherein the pulsed CVD process is a waterless and plasmaless deposition process, the second dielectric layer is not formed on the passivation surface of the conductive material, and the set of process parameters is Temperatures below 350°C, The number of deposition precursor pulses in the range of 50 pulses to 250 pulses, A deposition precursor pulse length in the range of 0.1 seconds to 4 seconds, including, system.

10. The system according to claim 9, wherein the at least one chamber is further configured to perform a pre-cleaning process to reduce native oxides on the surface of the conductive material before exposing the conductive material to aniline.

11. The system according to claim 9, further comprising a deposition precursor storage unit and a purge gas storage unit, each operably coupled to at least one of the chambers.

12. The system according to claim 11, wherein the deposition precursor storage unit maintains a deposition precursor selected from the group consisting of hafnium tert-butoxide, titanium isopropoxide, aluminum isopropoxide, aluminum tri-sec-butoxide, tetraethyl orthosilicate (TEOS), tetrabutyl orthosilicate (TBOS), or tetramethyl orthosilicate (TMOS).

13. The system according to claim 9, wherein the first dielectric layer comprises at least one of silicon dioxide, carbon-doped silicon oxide, or silicon nitride.

14. The system according to claim 9, wherein the conductive material includes a transition metal.

15. The system according to claim 9, wherein the second dielectric layer includes a metal oxide.

16. The at least one chamber is A third dielectric layer is formed on the second dielectric layer and the conductive material. A second conductive material is formed on the third dielectric layer. The system according to claim 9, further configured as follows.

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