Dynamic memory, electronic device, and method for manufacturing dynamic memory

Abstract

According to the embodiments of the present disclosure, a semiconductor memory device, a manufacturing method thereof, a read / write method, an electronic device, and a memory circuit are provided. [Solution] A transistor is provided for each memory cell in a semiconductor memory device, a gate and an auxiliary electrode are provided for the transistor, and the auxiliary electrode is electrically connected to the drain. During a write operation, a first voltage is applied to the gate via a word line, and then an electrical signal is applied to the source via a bit line based on external input data. During a read operation, a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0") is applied to the auxiliary electrode via the word line by utilizing the effect of the voltage on the auxiliary electrode on the threshold voltage of the transistor, and then the magnitude of the output current of the field effect transistor is detected to read data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular, relates to a dynamic memory, an electronic apparatus, and a method for manufacturing the dynamic memory.

BACKGROUND ART

[0002] This application claims the priority of Chinese Patent Application No. 202210351841.1 filed with the National Intellectual Property Administration on April 2, 2022, the entire contents of which are incorporated herein by reference.

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device, and compared with static memory memories, it has the advantages of simple structure, low manufacturing cost and high capacity density, and with the development of technology, the applications of DRAM memory are becoming more and more extensive. However, the conventional DRAM memory has the disadvantages of complex structure and low integration level, which limits the applications of DRAM memory .

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] An objective of the present disclosure is to reduce leakage current that may occur in read and write states while ensuring high integration of the device, Dynamic memory make the structure compact, and improve the storage performance Dynamic memory, electronic device, and method for manufacturing dynamic memory .

MEANS FOR SOLVING THE PROBLEMS

[0005] According to the several embodiments of the present disclosure, A dynamic memory is provided, comprising a substrate and a plurality of memory cells provided on the substrate, wherein the memory cells include a transistor, a bit line and a word line, and the transistor includes a drain provided above the substrate, a main gate provided on the side of the drain far from the substrate, insulated from the drain and electrically connected to the word line, a back gate provided on the side of the drain far from the substrate, surrounding the main gate, insulated from the main gate and electrically connected to the drain, an active layer surrounding the main gate, insulated from the main gate and the back gate respectively and electrically connected to the drain, and a source electrically connected to the active layer and the bit line respectively and insulated from the main gate and the back gate respectively. In some embodiments, the orthographic projection of the back gate onto the substrate and the orthographic projection of the main gate onto the substrate do not overlap. In some embodiments, the back gate is located between the source and the drain. In some embodiments, the orthographic projection of the back gate onto the substrate overlaps with the orthographic projection of the drain onto the substrate. In some embodiments, the orthographic projection of the back gate onto the substrate aligns with the orthographic projection of the drain onto the substrate. In some embodiments, the active layer is provided between the main gate and the back gate. In some embodiments, the back gate is further provided with a connector, which is electrically connected to the drain. In some embodiments, the connection surrounds the back gate. In some embodiments, the active layer comprises a single-crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor, wherein the metal oxide semiconductor comprises IGZO, ITO, or IWO.

[0006] According to some embodiments of the present disclosure, a dynamic memory is provided, comprising a substrate and a plurality of memory cells provided on the substrate, wherein the memory cell comprises a transistor, a bit line and a word line, and the transistor comprises a main gate located above the substrate and connected to the word line, an active layer surrounding the main gate and insulated from the main gate, sources connected to the active layer and the bit line, respectively, a drain connected to the active layer and spaced apart from the sources, and a back gate located between the sources and the drain and insulated from the active layer, wherein the back gate is connected to the drain, and the orthographic projection of the back gate onto the substrate is located at the orthographic projection of the drain onto the substrate. In some embodiments, the back gate surrounds the main gate, and the active layer is provided between the main gate and the back gate. In some embodiments, the orthographic projection of the source onto the substrate and the orthographic projection of the active layer onto the substrate are located at the orthographic projection of the drain onto the substrate, respectively. In some embodiments, the orthographic projection of the main gate onto the substrate aligns with the orthographic projection of the drain onto the substrate. In some embodiments, there is a node capacity between the back gate and the drain, and the node capacity constitutes the storage capacity. In some embodiments, a second gate insulating layer is further provided, wherein the back gate is insulated from the active layer, the source, and the drain by the second gate insulating layer. In some embodiments, the back gate is further provided with a connecting portion surrounding it, and the back gate is electrically connected to the drain via the connecting portion. In some embodiments, the drain includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface between the bottom surface and the top surface, and the connection portion is in contact with the side surface.

[0007] Another embodiment of the present disclosure provides an electronic device having the dynamic memory.

[0008] According to some embodiments of the present disclosure, a method for manufacturing a dynamic memory is provided, comprising: preparing a substrate; forming a drain on the substrate by patterning; forming a sacrificial layer covering the drain on the side of the drain furthest from the substrate; forming a source by patterning on the side of the sacrificial layer furthest from the substrate; forming a first dielectric layer covering the source on the source; forming a through-hole through which the drain is exposed at the bottom and the source is exposed at the wall of the hole, the through-hole penetrating the first dielectric layer, the source and the sacrificial layer; forming an active layer, a first gate insulating layer and a main gate in order within the through-hole, electrically connected to the source and the drain, respectively; and forming a back gate and a connection portion electrically connected to the back gate and the drain, respectively, on the side of the drain furthest from the substrate.

[0009] In some embodiments, forming a back gate and a connection portion on the side of the drain furthest from the substrate includes removing a portion of the first dielectric layer and the sacrificial layer by patterning to expose the drain; removing the remaining sacrificial layer to form a housing space to expose the drain, the source, and the active layer; depositing and forming a second gate insulating layer to cover the exposed active layer, the source, and the drain; depositing and forming the back gate on the second gate insulating layer to fill the housing space; and depositing and forming the connection portion to connect the drain and the back gate, respectively.

[0010] of the present disclosure several According to the embodiment of, the Dynamic memory provides a read-write method, wherein in a write state, a first voltage is applied to the gate through a word line to turn on the transistor, a data signal is applied to the source through a bit line, and the data signal passes through the turned-on transistor to the drain and the Back gate is stored in a storage capacitor connected thereto, and in a read state, a second voltage is applied to the gate through the word line, and the current at the source is measured through the bit line to read the data signal.

[0011] According to the present disclosure Dynamic memory achieves the following beneficial effects.

[0012] In the present disclosure Dynamic memory , each memory cell is provided with one transistor, and the transistor has a gate and Back gateA system was established, Back gate The gate and drain are electrically connected. When performing a write operation, a first voltage is applied to the gate via the word line, and then, based on the external input data, an electrical signal is applied to the source via the bit line, the source transmits the electrical signal to the drain, and the drain transmits the electrical signal Back gate To communicate, Back gate By using the node capacitor between the drain and the memory cell as the memory capacitor, data writing is achieved, and when reading operations are performed, Back gate By utilizing the effect of the above voltage on the transistor's threshold voltage, via the word line Back gate A second voltage (the magnitude of which lies between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0") is applied, and then the magnitude of the transistor's output current is detected to read the data. Therefore, data reading and writing can be achieved by installing only one transistor in the memory cell, eliminating the need to install separate transistors and capacitor elements, and significantly simplifying the structure of the memory cell. Dynamic memory This is advantageous for improving the integration density and memory density. [Brief explanation of the drawing]

[0013] The above and / or additional aspects and advantages of this disclosure will become clearer and easier to understand by describing the embodiments with reference to the following drawings. [Figure 1] This is a schematic diagram of the cross-sectional structure of a memory cell of a dynamic memory according to some embodiments of the present disclosure, perpendicular to the substrate. [Figure 2] This is a schematic diagram of the planar structure of a memory cell of a dynamic memory according to an embodiment of the present disclosure. [Figure 3] This is a schematic diagram of the cross-sectional structure of a dynamic memory according to an embodiment of the present disclosure, in the direction perpendicular to the substrate. [Figure 4] This is a schematic diagram of the structure of a memory circuit according to an embodiment of the present disclosure. [Figure 5] This is a schematic diagram of the circuit structure of a dynamic memory according to an embodiment of the present disclosure. [Figure 6] This graph shows the transfer characteristics of a dynamic memory transistor when writing different types of data. [Figure 7] This is a schematic flowchart of the method for manufacturing a dynamic memory according to the embodiments of this disclosure. [Figure 8a] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8b] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8c] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8d] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8e] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8f] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8g] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8h] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8i] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8j] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8k] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8l] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8m] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8n] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8o] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8p] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8q] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8r] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 8s] This is a schematic diagram of the structure of different processes for manufacturing dynamic memory according to embodiments of the present disclosure. [Figure 9] This is a flowchart of the method for reading and writing to dynamic memory according to the embodiments of this disclosure. [Modes for carrying out the invention]

[0014] The present disclosure will be described in detail below, and examples of embodiments of the present disclosure will be shown in the drawings, where the same or similar reference numerals indicate the same or similar components or components having the same or similar functions. Furthermore, detailed explanations of the prior art regarding the exemplary features of the present invention will be omitted where such explanations are unnecessary. The embodiments described below with reference to the drawings are illustrative and are for illustrative purposes only, and do not limit the present disclosure.

[0015] Those skilled in the art will understand that, unless otherwise specified, the singular forms “1,” “one,” “the said,” and “the said” as used herein may also include the plural form. It should be further understood that the expression “including” as used in this disclosure means that features, integers, steps, actions, elements, and / or components exist, but does not exclude the existence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof. Where an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or an intermediate element may exist. Furthermore, “connected” or “coupled” as used herein may include wireless connection or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more related enumerated items.

[0016] According to the present invention Dynamic memory, electronic device, and method for manufacturing dynamic memory The aim is to reduce leakage current while ensuring a high degree of integration.

[0017] The present invention is electrically connected to a drain, located on one side of a channel, with an insulating layer between it and the channel, and a gate located on the other side of the channel. Back gate Add the following. Back gate It functions simultaneously as both a back gate and a storage electrode, controlling the transistor's small off-current and playing a role in storing charge. This allows for relatively low-frequency refresh without the need for additional capacitors, while adding additional capacitors can ensure greater charge storage capability.

[0018] The following describes various embodiments of the present invention with reference to the drawings. Dynamic memory, electronic device, and method for manufacturing dynamic memory I will explain this in detail.

[0019] Figure 1 shows the present disclosure several Examples relating to Dynamic memory 10 memory cells In the direction perpendicular to the substrate This is a cross-sectional view. In Figure 1, Dynamic memoryFigure 10 shows only one memory cell among multiple memory cells arranged in an array. Figure 2 is a plan view of a portion of a portion of the components of the storage unit shown in Figure 1.

[0020] As shown in Figure 1, Dynamic memory 10 includes a substrate 110 and a plurality of memory cells 101 provided on the substrate 110, and each memory cell 101 includes a transistor 11, a bit line 32, and a word line 31. Transistor 11 has a drain 112, Main gate 115, back gate 116, active layer It has 114 and source 113.

[0021] The substrate 110 may be a silicon substrate, a glass substrate, a flexible substrate, or the like, but is not limited to these. The substrate 110 may have an upper surface and a lower surface that face each other.

[0022] Main Gate 115 This is connected to word line 31 and controls the on / off state of transistor 11. main It is a gate, Back gate 116 is, Main Gate 115 In contrast, Main gate 115 is the active layer Located on the surface of the channel, Back gate 116 active layer It is located on the back side of the channel. Main Gate 115 and Back gate All 116s are used to control transistor current, and all of them function as gates, Back gate The role of 116 is not to control the on / off state of the transistor, but to control the transistor to reduce leakage current. Main Gate 115 This controls the on / off state of the transistor through the action of the word line voltage.

[0023] In some embodiments, Main Gate 115 It is provided on the substrate 110, extends in a first direction perpendicular to the upper surface of the substrate 110, and may have a columnar shape. Main Gate 115 It may be electrically connected to the word line 31.

[0024] An interlayer insulating layer 111 may be provided on the upper surface of the substrate 110, and a drain 112 may be provided on the interlayer insulating layer 111.

[0025] active layer 114 may be provided on the interlayer insulating layer 111. active layer At least part of 114, Main Gate 115 The side walls may be enclosed.

[0026] active layer 114 may be formed from a single-crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor. The metal oxide semiconductor may also contain at least one of In, Ga, Zn, Sn, and W.

[0027] Source 113 is, active layer It is provided so as to surround the outer wall of 114, active layer Source 113 may be electrically connected to bit line 32.

[0028] Drain 112 is active layer 114 Side closer to substrate 110 to, active layer It may be provided to be electrically connected to 114. Also, the drain 112 is spaced apart from the source 113 in the first direction.

[0029] 1 gate The insulating layer 117a is Main Gate 115 and active layer Between 114 and, Main Gate 115 It may be provided between the drain 112 and the drain 112.

[0030] Back gate 116 is between source 113 and drain 112 in the first direction active layer It may be provided so as to surround the outer wall of 114.

[0031] The second gate insulating layer 117b is Back gate 116 active layer To be isolated from both 114 and source 113, Back gate 116 and active layer Between 114 and, Back gate It may be provided between 116 and source 113. Also, Back gate 116 may be electrically connected to drain 112.

[0032] in particular, Back gate 116 may extend in a first direction from source 113 toward drain 112. several In the embodiment, a plane parallel to the upper surface of the substrate 110 Back gate The orthographic projection of 116 and the orthographic projection of drain 112 onto a plane parallel to the upper surface of substrate 110 may overlap.

[0033] several In the embodiment, a plane parallel to the upper surface of the substrate 110 Back gate The orthographic projection of the outer wall of 116 may be located outside the orthographic projection of the source 113 onto the plane, or within the orthographic projection of the drain 112 onto the plane.

[0034] As shown in Figure 1, active layer 114 is, Main Gate 115 The side walls and Main Gate 115 The lower surface can be enclosed in a U-shape. First gate insulating layer 117a too, active layer 114 and Main Gate 115 To insulate them, active layer 114 and Main Gate 115 It can be formed in a U-shape between them.

[0035] As shown in Figure 1, the drain 112 is connected to the substrate 110 and active layer Provided between 114, active layer It is in contact with the underside of 114.

[0036] In Figure 1, the substrate 110 and active layer Although it is shown that a drain 112 is provided between 114 and 114, unlike in Figure 1, the drain 112 is, active layer It surrounds the lower part of the outer wall of 114, active layer It may be provided in contact with the lower part of the outer wall of 114.

[0037] Specifically, as shown in Figure 1, the drain 112 is connected to the substrate 110 and active layer It may also include a first portion located between 114 and a second portion extending outward from the first portion in a second direction parallel to the upper surface of the substrate 110. Orthographic projection onto substrate 110 teeth, Orthographic projection of back gate 116 onto substrate 110 It may overlap with at least some of the other.

[0038] several In this embodiment, although not shown, the second portion of the drain 112 is Back gate It may be made to contact 116 directly.

[0039] In another embodiment, as shown in Figure 1, Back gate 116 in the first direction Second gate insulating layer 117b The second part of the drain 112 may be separated via this, Back gate 116 is, Connection part 119 It may be electrically connected to the second part of drain 112 via this.

[0040] in particular, Back gate 116 may be electrically connected to the end of the second portion of the drain 112 via a conductive connector 119.

[0041] Although not shown in the diagram, Connection part 119 teeth, active layer It may extend downward in the first direction so as to enclose the outer wall of 116 in a ring shape and connect to the second part of the drain 112 (for example, Second gate insulating layer 117b (It may extend through the substrate.) Also, a plane parallel to the upper surface of the substrate 110 Connection part 119 The orthographic projection of is onto the plane. Back gate It is located within the orthographic projection of 116.

[0042] In other embodiments, Connection part 119 teeth, Back gate A portion of the outer wall of 116 may be electrically connected to the end of the second portion of drain 112. In this case, as shown in Figure 2, to a plane parallel to the upper surface of substrate 110 Connection part 119 The orthographic projection of is onto the plane. Back gate It may be located outside the orthographic projection of 116.

[0043] Word line 31 and bit line 32 are both Main Gate 115 of The side furthest from circuit board 110 They are located in different layers and are insulated from each other.

[0044] As shown in Figure 1, the orthographic projection of the source 113 onto a plane parallel to the upper surface of the substrate 110 is onto that plane. Back gate It may overlap with the orthographic projection of 116.

[0045] Also, Dynamic memory 10 in the first direction Back gate An additional electrode (not shown) that at least partially overlaps with 116 may be provided. The orthographic projection of this additional electrode onto the substrate 110 and the orthographic projection of the back gate 116 onto the substrate 110 overlap at least partially. The additional electrode is, Back gate Together with 116, they may form two opposing electrodes of the capacitor.

[0046] As shown in Figure 1, on a plane parallel to the upper surface of the substrate 110 Main Gate 115 The orthographic projection of the drain 112 coincides with the orthographic projection of the drain 112 onto a plane parallel to the upper surface of the substrate 110. Main Gate 115 It may be insulated from drain 112.

[0047] However, in other embodiments, the substrate 110 Main Gate 115 The orthographic projection of the image and the orthographic projection of the image 112 onto the substrate 110 do not overlap.

[0048] As shown in Figure 1, Back gate 116 may be provided on the upper surface of the drain 112, away from the substrate 110. Back gate The orthographic projection of 116 may overlap with the orthographic projection of the drain 112 onto the substrate 110. Back gate 116 is, Main Gate 115 It may be insulated from the substrate 110. Back gate The orthographic projection of 116 is onto substrate 110. Main Gate 115 It does not need to overlap with the orthographic projection.

[0049] active layer 114 is, Main Gate 115It may be surrounded. As shown in Figure 1, to the substrate 110 active layer The orthographic projection of 114 overlaps with the orthographic projection of drain 112 onto substrate 110. active layer 114 is, Main Gate 115 and Back gate Each is isolated from 116, active layer 114 is electrically connected to drain 112.

[0050] Source 113 is, active layer Source 113 may be electrically connected to 114 and bit line 32, respectively. Main Gate 115 and Back gate It is acceptable to isolate it from 116.

[0051] Specifically, as shown in Figures 1-5, the substrate 110 may contain silicon or glass, and the multiple memory cells 101 located on the substrate 110 are arranged in an array.

[0052] The drain 112 can be formed by a patterning process. On the upper surface of the drain 112, away from the substrate 110, active layer 114, Main Gate 115 , First gate insulating layer 117a, second gate insulating layer 117b, back gate 116 and source 113 are provided.

[0053] Source 113 is, Back gate 116 may be located on a surface away from the substrate 110, i.e., drain 112, Back gate 116 and source 113 are arranged in a stacked manner along the first direction in Figure 1. Main Gate 115 and Back gate 116 extends upward along the first direction on the substrate 110. That is, Main Gate 115 and Back gate In Figure 1, the length of 116 in the first direction is longer than the lengths in the other directions.

[0054] Main gate 115 and active layer Between 114, source 113 and drain 112 First gate insulating layer 117a Insulated by, Back gate 116 and active layer 114, Between source 113 and drain 112 Second gate insulating layer 117bInsulated by, source 113 and drain 112 respectively active layer Electrically connected to 114. Source 113, drain 112, Main gate 115, back gate 116 and active layer 114 are stacked to form a three-dimensional transistor 11. active layer 114, Main gate 115 and back gate (All of the 116s extend along a direction perpendicular to the substrate 110), Back gate 116 is electrically connected to drain 112. Memory cell 101 is Main Gate 115 The system further includes a word line 31 electrically connected to the source 113 and a bit line 32 electrically connected to the source 113.

[0055] Dynamic memory When 10 is in write operation mode, via word line 31 Main Gate 115 A first voltage is applied to the source 113, which is the on-voltage (e.g., +5V), and at this time the transistor channel is conducting, and the source voltage is approximately equal to the drain voltage. Simultaneously, a voltage input data signal is applied to the source 113 via the bit line 32, and the voltage at the drain 112 is equal to the voltage of the source input data signal. Back gate Since 116 is electrically connected, at this time the magnitude of the voltage at source 113 and drain 112 and Back gate The magnitude of the voltage at 116 is the same (drain 112 and Back gate (The potentials of 116 are the same.) Back gate The node capacitor between 116 and drain 112 constitutes the storage capacitor 103 of the memory cell 101. Back gate The voltage level at 116 determines the amount of charge in the storage capacitor and, further, determines whether the binary value of the data signal stored in the memory cell 101 is 0 or 1. When a high voltage (e.g., 5 V) is applied to the source 113 via the bit line 32, the data "1" is written to the memory cell 101, and when a low voltage (e.g., 0 V) ​​is applied to the source 113 via the bit line 32, the data "0" is written to the memory cell 101.

[0056] In the above embodiment, the node capacitor is the Back gateThe potential difference between 116 and infinity, or the aforementioned Back gate This could also be the voltage difference between 116 and peripheral electrodes such as the source and gate.

[0057] Dynamic memory When 10 is in read operation mode, Main Gate 115 A voltage difference exists between the source 113 and via the word line 31. Main Gate 115 Apply a second voltage to turn on the transistor. Back gate The charge accumulated in 116 is sensed by the detection bit line 32, and the magnitude of the current in the bit line 32 (i.e., the output current of transistor 11) is detected, enabling data reading. In some embodiments, the detection bit line 32 may be the bit line described above, in which case the input signal line and the data read line are the same line.

[0058] Specifically, if the data stored before memory cell 101 is "1", Back gate 116 and drain 112 have a high potential (e.g., +5V), and due to the combined action of the first gate voltage and the second gate voltage, transistor 11 is in the ON state, so a significant current can be measured via bit line 32. If a significant current is measured, the read data is determined to be "1". If the data stored before memory unit 101 was "0", Back gate The potential above 116 and drain 112 is low. Main Gate 115 After applying the second voltage, transistor 11 remains off, so the current measured via bit line 32 is very weak, and at this time, the data read is determined to be "0".

[0059] The magnitude of the threshold voltage of transistor 11 is, Back gate This relates to the control of 116. If only a gate is present, Vth is related to factors such as material and device structure. Back gate When controlling the semiconductor channel of a transistor, a negative bias is generated in the transistor's Vth.

[0060] Regarding N-type field-effect transistors (where the carriers are electrons when the transistor is turned on), Back gate The higher the potentials on 116 and drain 112 (for example, +5V), the smaller the on-voltage of the transistor gate becomes (i.e., the threshold voltage is negative), i.e., Main Gate 115 When the pressure difference between and source 113 is small, transistor 11 is also turned on. Back gate The lower the potential on 116 and drain 112, the Back gate by active layer The channel control is weak, and the threshold voltage is Back gate It is not affected by it. Therefore, Main Gate 115 When the same second voltage is applied, refer to Figure 6, where the horizontal axis is Main Gate 115 This is the voltage applied to (i.e., the second voltage), and the vertical axis represents the output current of transistor 11. Main Gate 115 If the voltage applied to it is a specific value (at the position of the dashed line in Figure 6), Back gate The voltage difference between 116 and drain 112 (i.e., whether the data written to transistor 11 is "1" or "0") significantly affects the magnitude of the output current of transistor 11 (i.e., the current measured via bit line 32). By detecting the current on bit line 32, data can be read from memory cell 101. When transistor 11 writes data "1", the output current of transistor 11 is large, so the data read out is also "1". When the data written by transistor 11 is "0", the output current of transistor 11 is extremely weak, so the data read out is also "0".

[0061] in this case, Back gate By increasing the control of the semiconductor channel, the transistor can obtain a large current with a small on-voltage and become less likely to turn off when it is turned on. When the transistor is turned off, it requires a large voltage and becomes less likely to turn on. In this way, dark current during on or off is reduced, the device's ability to accumulate and retain charge is improved, and in some embodiments, the refresh frequency can be reduced.

[0062] The value of the second voltage depends on the transistor parameters and the write operation. Back gate It may be determined according to the magnitude of the voltage applied to 116 and drain 112. Note that the value of the second voltage must be appropriate (it must be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"), and if the value of the second voltage is not appropriate, data "1" will be stored (i.e., drain 112 and Back gate The output current of transistor 11 and the data "0" are stored when the potential above 116 is high (i.e., drain 112 and Back gate Because the magnitude of the output current of transistor 11 is very similar when the potential on the gate is low, it is difficult to determine whether the read data is "0" or "1" when performing a read operation, and this is Dynamic memory This affects the performance of 10. The optimal value of the second voltage can be determined by experimental or simulation methods so that the difference in output current is maximized when transistor 11 performs read operations under different conditions, in order to improve read performance.

[0063] Disclosure Dynamic memory In 10, one transistor 11 is provided for each memory cell 101, and the transistor 11 Main gate 115 and back gate 116 and are provided, Back gate 116 and drain 112 are electrically connected. Main Gate 115 After applying a first voltage via word line 31, an electrical signal is applied to source 113 via bit line 32 according to external input data, source 113 transmits the electrical signal to drain 112, and drain 112 transmits the electrical signal Back gate Transmit to 116, Back gate The node capacitor between 116 and drain 112 constitutes the memory capacitor of the memory cell 101, thereby enabling data writing (writing of "1" or "0"). When performing a read operation, Back gate The voltage at 116 has a favorable effect on the threshold voltage of transistor 11, via word line 31. Main Gate 115A second voltage (the magnitude of the second voltage lies between the threshold voltage when transistor 11 stores "1" and the threshold voltage when transistor 11 stores "0") is applied, and data is read by detecting the magnitude of the output current of the field-effect transistor. Therefore, the memory cell 101 in the embodiment of this disclosure can achieve data reading and writing by providing only one transistor 11, eliminating the need for other transistors and capacitive elements, significantly simplifying the structure of the memory cell 101, which is advantageous for improving the integration density and storage density of the semiconductor memory element 10. Furthermore, stacking the memory cells 101 creates a multilayer structure. Dynamic memory It becomes easier to form 10, Dynamic memory The 10 formation process is simplified.

[0064] In the embodiments of this disclosure, Main gate 115, back gate 116, active layer Both 114 and source 113 are provided on the side of drain 112 that is farther from substrate 110. Main gate 115, back gate 116, active layer The specific positions of 114 and source 113 can be adjusted according to the actual situation. In the embodiments, as shown in Figures 1 and 2, Main gate 115, back gate 116, Source 113 and active layer Since the orthographic projections of 114 on substrate 110 all fall within the orthographic projection of drain 112 on substrate 110, the area occupied by transistor 11 can be reduced. Dynamic memory The 10 structural layouts are more compact and offer advantages in terms of device integration.

[0065] As shown in Figures 1 and 2, in the embodiment, Back gate 116 is Main Gate 115 Surrounding, The active layer 114 is connected to the main gate 115 and the back gate It is provided between 116. Back gate 116 is the main gate 115 By surrounding it, Main gate 115, back gate 116 and active layer The area of ​​the overlapping region between 114 can be maximized, thereby, Back gate The influence of transistor 11 on the threshold voltage can be greatly increased, that is, Back gateWhen the voltages at 116 are different, applying the same threshold voltage can cause a large difference in the output current of the transistor. Therefore, it is advantageous for distinguishing data read during a read operation, and improves the accuracy of the read data. Note that in the first direction in FIG. 1 Main Gate 115 layer and the Back gate thickness of the 116 layer may be determined according to actual situations, and is not limited herein.

[0066] In this embodiment, active layer the material of 114 includes a metal oxide semiconductor material. Due to the inherent properties of metal oxide semiconductors (factors such as low electron mobility), active layer when a metal oxide is adopted as the material of 114, the leakage current of the transistor 11 can be reduced, and the speed of charge flow in the storage capacitor can be reduced, so that Dynamic memory the data retention time of 10 can be extended, Dynamic memory which is advantageous for reducing the refresh frequency and power consumption of 10.

[0067] The metal oxide material may be Indium Gallium Zinc Oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 11 is small (the leakage current is 10 -15 A or less), whereby Dynamic memory the operating performance of can be ensured. Note that the metal oxide material may also be ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x Iny Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a , Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z , Al x Zn y Sn z O a , Ga x Zn y Sn z O a , Zr x Zn y Sn z O a The material may be InGaSiO or other materials, as long as the transistor's leakage current is guaranteed to meet the requirements, and the specifics will be adjusted according to the actual circumstances.

[0068] In addition, Back gate The specific method for achieving the electrical connection between 116 and drain 112 can be determined according to the actual situation. In the embodiment, as shown in Figures 1 and 2, transistor 11 is Connection part 119 It further includes, Connection part 119 It is provided on the side of the drain 112 that is far from the substrate 110. Back gate 116 is, Connection part 119 It is electrically connected to drain 112 via this. Dynamic memory In the formation process of 10, drain 112 and Back gateAfter forming 116, the conductive connecting member 119 can be formed by depositing a metallic material on the drain 112, which is an easy process. The material of the conductive connecting member 119 can be a material with good conductive properties such as copper or aluminum, and is not limited thereto. The size and position of the conductive connecting member 119 can be adjusted according to the actual situation. In the embodiment, as shown in Figures 1 and 2, Connection part 119 teeth Back gate To surround 116, Connection part 119 and back gate The contact area with 116 and drain 112 can be maximized. Back gate This is advantageous for improving the electrical connection performance between 116 and drain 112.

[0069] In the embodiments, as shown in Figures 1-5, in the embodiments of this disclosure, Dynamic memory 10 includes a plurality of array modules 102 arranged in a stack, and each array module 102 includes a plurality of storage units 101 arranged in an array. Specifically, the word lines 31 (not shown in Figure 3) of the plurality of memory cells 101 are connected to each other, and the bit lines 32 (not shown in Figure 3) are connected to each other, forming a single array module 102. The multi-array module 102 has a three-dimensional structure. Dynamic memory By being arranged in layers to form 10, Dynamic memory In addition to improving memory capacity, Dynamic memory This reduces the area occupied by 10, which is advantageous for device integration.

[0070] Based on the same inventive concept, embodiments of the present disclosure further provide a memory circuit, as shown in Figure 4, Main gate 115, back gate Including line 116, source 113, drain 112, word line 31 and bit line 32, Main Gate 115 The word line 31 is electrically connected, the source 113 is electrically connected to the bit line 32, and the drain 112 is Back gate Electrically connected to 116, Main gate 115 and back gate 116 is isolated from each other. Main Gate 115 These are isolated from source 113 and drain 112, respectively. Back Main Gate 115These are isolated from source 113 and drain 112, respectively. Back gate The node capacitor between 116 and drain 112 constitutes the memory capacitor 103.

[0071] Based on the same inventive concept, the embodiments of this disclosure are as described above according to the embodiments of this disclosure. Dynamic memory Further, the present disclosure provides an electronic device including 10, or an electronic device including the memory circuit according to an embodiment of the present disclosure. Dynamic memory Because it includes 10, Dynamic memory Since it has the same beneficial effects as item 10, we will omit the explanation here.

[0072] Specifically, the electronic devices according to the embodiments of this disclosure include, but are not limited to, memory devices, smartphones, computers, tablet computers, artificial intelligence devices, wearable devices, or mobile power supplies.

[0073] Based on the same inventive concept, embodiments of this disclosure are: Dynamic memory Further, 10 manufacturing methods are provided. In S101, a substrate is provided. In S102, a drain is formed on one side of the substrate by the patterning process. In S103, the source is on the side furthest from the drain substrate. active layer and gates are formed in sequence. In S104, on the side of the drain furthest from the substrate Back gate And a conductive connecting member is formed.

[0074] In a formation method according to one embodiment of the present disclosure, one transistor 11 is provided in each memory cell 101, so that the transistor 11 Main gate 115 and back gate 116 was established, Back gate 116 and drain 112 are electrically connected. When performing a write operation, the word line 31 is used. Main Gate 115A first voltage is applied to the source 113, and then, based on the external input data, an electrical signal is applied to the source 113 via the bit line 32, the source 113 transmits the electrical signal to the drain 112, and the drain 112 receives the electrical signal Back gate Transmit to 116, Back gate The node capacity between 116 and drain 112 constitutes the storage capacity of memory cell 101, thereby enabling data writing and, when performing read operations, via word line 31 Main Gate 115 A second voltage (the magnitude of which lies between the threshold voltage at which transistor 11 stores "1" and the threshold voltage at which transistor 11 stores "0") is applied, and then the magnitude of the output current of the field-effect transistor is detected to realize data reading. Therefore, data reading and writing can be achieved by installing only one transistor 11 in the memory cell 101, eliminating the need to install separate transistors 11 and capacitor elements, and significantly simplifying the structure of the memory cell 101. Dynamic memory This is advantageous for improving integration density and memory density.

[0075] In one embodiment, the source 113 is located on the side of the drain 112 that is farther from the substrate 110. active layer 114 and Main Gate 115 The steps for forming them in order are: A sacrificial layer is formed on the side of the drain furthest from the substrate, and the sacrificial layer covers the drain. The patterning process forms a source on the side of the sacrificial layer furthest from the substrate, and the orthographic projection of the source onto the substrate lies within the orthographic projection of the drain onto the substrate. A first medium layer is formed on the side of the source furthest from the substrate, and the first medium layer covers the source and drain. Through holes are provided that sequentially penetrate the first medium layer, the source, and the sacrificial layer, with the drain exposed at the bottom of the through hole and the source exposed at the wall of the through hole. Inside the through hole, active layer Then, the first insulating layer and the gate are formed in sequence. active layer This includes being electrically connected to the source and drain, respectively.

[0076] In one embodiment, on the side of the drain 112 that is farther from the substrate 110 Back gate The step of forming 116 and the conductive connecting member 119 is: The patterning process removes part of the first medium layer and the sacrificial layer, exposing the drain. Remove the remaining sacrificial layer, drain, source and active layer To form a containment space that exposes, The second insulating layer was deposited and formed, and then exposed. active layer The source 113 and drain are covered by the second insulating layer, On the surface of the second insulating layer Back gate Forms deposits back gate To fill the containment space with it, Conductive connecting members are deposited on both ends of the exposed drain, and the conductive connecting members are connected to the drain and the drain, respectively. Back gate This includes connecting to it.

[0077] In the embodiments of this disclosure, the drain 112 is on the side furthest from the substrate 110. Back gate 116 and Connection part 119 After forming, The process involves forming word lines through a patterning process and electrically connecting the word lines to the gates. This includes forming a bit line by a patterning process and electrically connecting the bit line to a source.

[0078] The following describes embodiments of this disclosure. Dynamic memory The 10 manufacturing steps will be described in detail with reference to the drawings. Specifically, the patterning steps in the embodiments of this disclosure include some or all of the processes of coating, exposing, developing, etching, and removing the photoresist. As shown in Figure 8a, first, a substrate 110 is provided. The material of the substrate 110 includes silicon or glass. As shown in Figure 8b, an interlayer insulating layer 111 is then formed on one side of the substrate 110. As shown in Figure 8c, a drain 112 is then formed on the side of the interlayer insulating layer 111 that is far from the substrate 110 by a patterning process. As shown in Figure 8d, a sacrificial layer 100 is then formed on the side of the drain 112 furthest from the substrate 110, the sacrificial layer 100 covers the drain 112, and the material of the sacrificial layer 100 includes an organic material or an inorganic material. As shown in Figure 8e, next, a patterning process forms a source 113 on the side of the sacrificial layer 100 that is farther from the substrate 110, and the orthographic projection of the source 113 on the substrate 110 is positioned within the orthographic projection of the drain 112 on the substrate 110. As shown in Figure 8f, a first medium layer 118a is then formed on the side of the source 113 furthest from the substrate 110, so that the first medium layer 118a covers the source 113. The material of the first medium layer 118a includes an inorganic material such as silicon oxide or silicon nitride. As shown in Figure 8g, next, a portion of the first medium layer 118a is shielded by the mask 23, and a through hole 20 is made in the first medium layer 118a that is not shielded by the mask 23. The through hole 20 penetrates the first medium layer 118a, the source 113, and the sacrificial layer 100 in sequence, with the drain 112 exposed at the bottom of the through hole 20 and the source 113 exposed at the wall of the through hole 20. As shown in Figure 8h, the via hole 20 is then subjected to processes such as atomic deposition, chemical vapor deposition, and physical vapor deposition. active layer 114, First gate insulating layer 117a and Main Gate 115 Form them in order, active layer Connect 114 electrically to source 113 and drain 112, respectively. active layer 114 materials include metal oxides such as IGZO, First gate insulating layer 117a The materials include materials with good insulating properties, such as aluminum oxide. Main Gate 115 The materials include titanium nitride, tungsten, and other materials with good conductivity. Subsequently, by a chemical mechanical polishing process... Active layer 114, first gate insulating layer 117a and main gate 115 The surface away from the substrate 110 is polished. Active layer 114, first gate insulating layer 117a, main gate 115 And the first medium layer 118a is made flush with the surface. As shown in Figure 8i, next, a patterning process removes part of the first medium layer 118a and the sacrificial layer 100, exposing the drain 112. Specifically, using a mask 23 active layer 114, First gate insulating layer 117aand Main Gate 115 The corresponding region is shielded, and the portions located at both ends of the first medium layer 118a and the sacrificial layer 100 are etched. As shown in Figure 8j, the remaining sacrificial layer 100 is then removed by the etching process, drain 112, source 113 and active layer The accommodation space 22 is formed so as to expose 114. As shown in Figure 8k, the next step is the deposition process into the containment space 22 Second gate insulating layer 117b Forming, Second gate insulating layer 117b However, exposed active layer Covers 114, source 113, and drain 112. As shown in Figure 8, next, Second gate insulating layer 117b on the surface Back gate 116 formed by deposition, Back gate 116 is filled into the containment space 22. Next, by the etching process Back gate Etching the side of 116 to create adjacent memory cells Back gate Ensure that units 116 are isolated from each other. As shown in Figure 8m, next, at both ends of the drain 112 exposed by the deposition process Connection part 119 It deposits and forms Connection part 119 drain 112 and Back gate Connect them to terminals 116 to complete the manufacturing of transistor 11. As shown in Figure 8n, a second medium layer 118b is then formed on one side of the substrate 110 by a deposition process, so that the second medium layer 118b covers the transistor 11. As shown in Figure 8o, a through passage 21 is then created in the second medium layer 118b at a position corresponding to the source 113. As shown in Figure 8p, next, a patterning process forms bit lines 32 on the side of the second medium layer 118b that is farther from the substrate 110, and the bit lines 32 are electrically connected to the source 113 via through vias 21. As shown in Figure 8q, the third medium layer 118c is then deposited on the second medium layer 118b. As shown in Figure 8r, next, in the third medium layer 118c Main Gate 115 A through passage 21 is provided at the corresponding location. As shown in Figure 8s, next, a word line 31 is formed on the side of the third medium layer 118c furthest from the substrate 110 by a patterning process, and the word line 31 is passed through the through passage 21. Main Gate 115 Connect it electrically. Based on the same inventive concept, embodiments of this disclosure are: Dynamic memory We will provide 10 more reading and writing methods. In S201, when writing is in progress, a first voltage is applied to the gate via the word line. In S202, based on the external input data, an electrical signal is applied to the source via the bit line, and the data is processed. Dynamic memory When writing to or reading from the device, a second voltage is applied to the gate via the word line. In S203, the current in the source is measured by the bit line and the data Dynamic memory Read from there.

[0079] Specifically, as shown in Figures 1 and 2 (word lines and bit lines are not shown in Figure 2), Dynamic memory When 10 is in write operation mode, via word line 31 Main Gate 115 By applying a first voltage (e.g., 5V), the transistor 11 is turned on, and the magnitude of the first voltage depends on the structure of the transistor 11 and the position of the transistor 11. active layer In relation to factors such as material 114, specifically, it can be adjusted according to the actual situation. When transistor 11 is turned on, a voltage is applied to source 113 via bit line 32 according to the external input data, and source 113 and drain 112 active layer Conduction occurs via 114, and drain 112 and Back gate Since 116 is electrically connected, the magnitude of the voltage at source 113 and drain 112 and Back gate The voltage magnitude will be the same as at 116. Back gate The node capacity between 116 and drain 112 constitutes the storage capacity of memory cell 101. Back gateThe gate voltage of 116 determines the amount of charge in the storage capacitance and also determines whether the binary value of the data signal stored in the memory cell 101 is 0 or 1. When a high voltage (e.g., 5 V) is applied to the source 113 via the bit line 32, the data "1" is written to the memory cell 101, and when a low voltage (e.g., 0 V) ​​is applied to the source 113 via the bit line 32, the data "0" is written to the memory cell 101.

[0080] Dynamic memory When 10 is in read operation mode, Main Gate 115 A voltage difference exists between the source 113 and via the word line 31. Main Gate 115 A second voltage is applied, and the magnitude of the current flowing through the bit line 32 (i.e., the output current of transistor 11) is detected to enable data reading. Specifically, if the data stored before memory cell 101 is "1", Back gate 116 and drain 112 have a high potential, and due to the combined action of the first voltage and the second voltage, transistor 11 is in the ON state, so a significant current can be measured via bit line 32. If a significant current is measured, the read data is determined to be "1". If the data stored before memory unit 101 was "0", Back gate The voltage at 116 and drain 112 is low. Main Gate 115 After applying the second voltage, the field-effect transistor remains in the off state, so the current measured via bit line 32 is very weak, and at this time, the data read is determined to be "0".

[0081] The magnitude of the threshold voltage of transistor 11 is, Back gate In relation to the magnitude of the voltage at 116 and drain 112, the N-type field-effect transistor (i.e., transistor 11) active layer Regarding the adoption of N-type semiconductor materials in 114, Back gate The higher the potential at 116 and drain 112, the lower the threshold voltage becomes, i.e., Main Gate 115When the differential pressure between the transistor and source 113 is small, transistor 11 can have a large output current. Back gate The lower the potential at 116 and drain 112, the higher the threshold voltage becomes. Main Gate 115 When a similar second voltage is applied, as shown in Figures 1, 4, and 6, Back gate The voltage level at 116 and drain 112 (i.e., whether the data written by transistor 11 is "1" or "0") causes a significant difference in the magnitude of the output current of transistor 11 (i.e., the current measured by bit line 32). By detecting the current at bit line 32, it is possible to read data from memory cell 101. When transistor 11 writes the data "1", the output current of transistor 11 is "1".

[0082] Note that the value of the second voltage is a parameter of the field-effect transistor and is used when performing a writing operation. Back gate This can be determined based on the magnitude of the voltage applied to 116 and drain 112. Note that the value of the second voltage must be appropriate (it must be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"), and if the value of the second voltage is not appropriate, data "1" will be stored (i.e., drain 112 and Back gate The output current of transistor 11 and the data "0" are stored when the potential above 116 is high (i.e., drain 112 and Back gate Because the magnitude of the output current of transistor 11 is very similar when the potential on the gate is low, it is difficult to determine whether the read data is "0" or "1" when performing a read operation, and this is Dynamic memory This affects performance. In actual applications, the optimal value of the second voltage can be determined by experimental or simulation methods to maximize the difference in output current when transistor 11 performs readout operations under different conditions, thereby improving readout performance.

[0083] By applying the embodiments of this disclosure, at least the following beneficial effects can be achieved. 1. By this disclosure Dynamic memory In 10, one transistor 11 is provided for each memory cell 101, and the transistor 11 Main gate 115 and back gate 116 and are provided, Back gate 116 and drain 112 are electrically connected. When performing a write operation, via word line 31 Main Gate 115 A first voltage is applied to the source 113, and then, based on the external input data, an electrical signal is applied to the source 113 via the bit line 32, the source 113 transmits the electrical signal to the drain 112, and the drain 112 receives the electrical signal Back gate Transmit to 116, Back gate The node capacity between 116 and drain 112 constitutes the storage capacity of memory cell 101, thereby enabling data writing and read operations. Back gate By utilizing the effect of the voltage on 116 on the threshold voltage of transistor 11, via word line 31 Main Gate 115 A second voltage (the magnitude of which lies between the threshold voltage at which transistor 11 stores "1" and the threshold voltage at which the transistor stores "0") is applied, and then the magnitude of the output current of the field-effect transistor is detected to realize data reading. Therefore, data reading and writing can be achieved by installing only one transistor 11 in the memory cell 101, eliminating the need to install separate transistors 11 and capacitor elements, and significantly simplifying the structure of the memory cell 101. Dynamic memory This is advantageous for improving integration density and memory density. 2. In the embodiments of this disclosure, Main Gate 115 , to substrate 110 Back gate 116, Source 113 and active layer By ensuring that the orthographic projections of 114 all fall within the orthographic projection of the drain 112 onto the substrate 110, the area occupied by the transistor 11 is reduced. Dynamic memory The 10 structural layouts are more compact and offer advantages in terms of device integration. 3. In the embodiments of this disclosure, Back gate 116 is the main gate 115 By surrounding it, Main gate 115, back gate 116 and active layer The area of ​​the overlapping region between 114 can be maximized, thereby, Back gate The influence of transistor 11 on the threshold voltage can be greatly increased, that is, Back gate When the voltage at 116 differs, applying the same threshold voltage can create a significant difference in the output current of the field-effect transistor. Therefore, it is advantageous for distinguishing the data read during the reading operation and improves the accuracy of the read data. 4. active layer When metal oxide is used as the material for 114, the leakage current of transistor 11 can be reduced (if the metal oxide is IGZO, the leakage current is 10 -15 (It is less than or equal to A), so the rate of charge loss in the storage capacity can be reduced, Dynamic memory The data storage time can be extended by 10. Dynamic memory It is advantageous for reducing refresh rates and power consumption. 5. In the embodiments of this disclosure, a plurality of memory cells 101 are arranged in an array to form an array module 102, and then the multilayer array modules 102 are stacked and installed to form a three-dimensional structure. Dynamic memory In order to form 10, Dynamic memory In addition to improving memory capacity, Dynamic memory This reduces the area occupied by 10, which is advantageous for integrating devices.

[0084] In the description of this disclosure, the orientations or positional relationships indicated by terms such as “center,” “top,” “bottom,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside” are based on the orientations or positional relationships shown in the drawings and are merely for the convenience and simplification of the description of this disclosure. They do not indicate or imply that the specified device or element has a specific orientation or must be configured and operated in a specific orientation, and should not be understood as limiting this disclosure.

[0085] The terms “First” and “Second” are for descriptive purposes only and should not be understood as indicating or implying relative importance or the number of technical features described. Thus, features limited to “First” and “Second” may explicitly or implicitly include one or more such features. In this disclosure, unless otherwise specified, “multiple” means two or more.

[0086] In this specification, specific features, structures, materials, or characteristics can be combined in any way appropriate in any one or more embodiments or examples.

[0087] The foregoing describes only some embodiments of the present disclosure, and those skilled in the art can make several improvements and modifications without departing from the principles of the present disclosure, and these improvements and modifications should also be considered within the scope of the present disclosure.

Claims

1. A dynamic memory comprising a substrate and a plurality of memory cells provided on the substrate, The memory cell includes a transistor, bit lines and word lines, The aforementioned transistor is A drain provided above the substrate, A main gate is provided on the side of the drain furthest from the substrate, is insulated from the drain, and is electrically connected to the word line. A back gate is provided on the side of the drain furthest from the substrate, surrounds the main gate, is insulated from the main gate, and is electrically connected to the drain. An active layer surrounds the main gate, is insulated from the main gate and the back gate, and is electrically connected to the drain. A dynamic memory comprising a source electrically connected to the active layer and the bit line, respectively, and isolated from the main gate and the back gate, respectively.

2. The dynamic memory according to claim 1, wherein the orthographic projection of the back gate onto the substrate and the orthographic projection of the main gate onto the substrate do not overlap.

3. The dynamic memory according to claim 1, wherein the back gate is located between the source and the drain.

4. The dynamic memory according to claim 1, wherein the orthographic projection of the back gate onto the substrate and the orthographic projection of the drain onto the substrate overlap.

5. The dynamic memory according to claim 4, wherein the orthographic projection of the back gate onto the substrate is located at the orthographic projection of the drain onto the substrate.

6. The dynamic memory according to claim 1, wherein the active layer is provided between the main gate and the back gate.

7. The dynamic memory according to claim 1, further comprising a connection portion, wherein the back gate is electrically connected to the drain via the connection portion.

8. The dynamic memory according to claim 7, wherein the connection portion surrounds the back gate.

9. The active layer comprises a single-crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor. The dynamic memory according to claim 1, wherein the metal oxide semiconductor includes IGZO, ITO, or IWO.

10. A dynamic memory comprising a substrate and a plurality of memory cells provided on the substrate, The memory cell includes a transistor, bit lines and word lines, The aforementioned transistor is A main gate located above the aforementioned substrate and connected to the word line, An active layer surrounding the main gate and insulated from the main gate, Sources connected to the active layer and the bit lines, A drain connected to the active layer and spaced apart from the source, A back gate located between the source and the drain and isolated from the active layer, A dynamic memory wherein the back gate is connected to the drain, and the orthographic projection of the back gate onto the substrate is located at the orthographic projection of the drain onto the substrate.

11. The dynamic memory according to claim 10, wherein the back gate surrounds the main gate, and the active layer is provided between the main gate and the back gate.

12. The dynamic memory according to claim 10, wherein the orthographic projection of the source onto the substrate and the orthographic projection of the active layer onto the substrate are each located at the orthographic projection of the drain onto the substrate.

13. The dynamic memory according to claim 10, wherein the orthographic projection of the main gate onto the substrate is located at the orthographic projection of the drain onto the substrate.

14. The dynamic memory according to claim 10, wherein the back gate and the drain both form one electrode of the node capacity, and the node capacity constitutes the storage capacity.

15. The dynamic memory according to claim 10, further comprising a second gate insulating layer, wherein the second gate insulating layer is provided between the back gate and the active layer, between the back gate and the source, and between the back gate and the drain.

16. The dynamic memory according to claim 10, further comprising a connecting portion surrounding the back gate, wherein the back gate is electrically connected to the drain via the connecting portion.

17. The dynamic memory according to claim 16, wherein the drain includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface between the bottom surface and the top surface, and the connection portion is in contact with the side surface.

18. An electronic device having a dynamic memory as described in claim 1.

19. Prepare the circuit board, A drain is formed above the aforementioned substrate by patterning, A sacrificial layer covering the drain is formed on the side of the drain furthest from the substrate, A source is formed on the side of the sacrificial layer furthest from the substrate by patterning, A first dielectric layer covering the source is formed on the source, A through-hole in which the drain is exposed at the bottom and the source is exposed on the wall of the hole, and the through-hole is formed to penetrate the first dielectric layer, the source and the sacrificial layer, Within the through-hole, an active layer, a first gate insulating layer, and a main gate are formed in order, electrically connected to the source and the drain, respectively. The drain is provided with a back gate and a connection portion that is electrically connected to the back gate and the drain, respectively, on the side of the drain furthest from the substrate. A method for manufacturing dynamic memory.

20. A back gate and a connection portion are formed on the side of the drain furthest from the substrate. To expose the drain, a portion of the first dielectric layer and the sacrificial layer is removed by patterning, The remaining sacrificial layer is removed to form a containment space that exposes the drain, the source, and the active layer. A second gate insulating layer is deposited and formed to cover the exposed active layer, the source, and the drain. The back gate is formed by depositing it on the second gate insulating layer so as to fill the housing space, A method for manufacturing a dynamic memory according to claim 19, comprising forming the connection portion by deposition so as to connect to the drain and the back gate, respectively.

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