Gaming machine

Abstract

To provide a game machine that can suppress the adverse effects on the progress of a game due to the occurrence of troubles related to LCD control as much as possible.SOLUTION: A game machine includes reservation storage means for reserving and storing random number information acquired when a symbol start condition is satisfied until it is subjected to symbol variation by symbol display means, and profit state generating means for generating a profit state when a stop symbol after variation of the symbol display means becomes in a specific mode. The game machine can display a reservation notification image on liquid crystal display means, and outputs odd image data and even image data to the liquid crystal display means via wiring paths different from each other. For the reservation notification image, dynamic display with a change in a vertical direction is executed. Therefore, even if either the odd image data or the even image data is missing, dynamic display of the reservation notification image can be identified easily.SELECTED DRAWING: Figure 81

Description

[Technical Field]

[0001] This invention relates to amusement machines such as pachinko machines and slot machines. [Background technology]

[0002] In amusement machines such as pachinko machines, those equipped with liquid crystal display means for displaying visual effects and other images are the mainstream. This liquid crystal display means is controlled based on image data signals and other control signals output from a VDP (Video Display Processor) circuit mounted on a control board (Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-093632 [Overview of the project] [Problems that the invention aims to solve]

[0004] In conventional gaming machines, if even a small portion of the control signals related to LCD control were lost due to some kind of malfunction, the LCD display might show an image that the player could not recognize, potentially preventing the player from continuing to play normally. This invention has been made in view of the above circumstances, and aims to provide a gaming machine that can minimize the adverse effects on gameplay caused by problems related to LCD control. [Means for solving the problem]

[0005] The present invention relates to a gaming machine comprising: a symbol display means capable of displaying a changing symbol based on random number information acquired when a symbol activation condition is met; a holding storage means that holds and stores the random number information up to a predetermined upper limit until it is used for symbol variation by the symbol display means; a profit state generation means that generates a profit state when the stopped symbol after variation by the symbol display means becomes a specific form; and a display control means that controls the display of a liquid crystal display means, wherein the liquid crystal display means can display a number of holding notification images corresponding to the number of random number information stored in the holding storage means, and the display control means includes odd image data corresponding to odd pixels and the odd pixels The system is configured to output even image data corresponding to horizontally adjacent even pixels to the liquid crystal display means via different wiring paths, and comprises: a first substrate on which the display control means is mounted and a first signal line is formed for transmitting the odd image data and the even image data to the liquid crystal display means; a second substrate on which a second signal line is formed for transmitting the odd image data and the even image data, and an output connector is mounted for outputting the odd image data and the even image data to the liquid crystal display means; and a connection connector connecting the first signal line of the first substrate and the second signal line of the second substrate. The second signal line is composed of multiple wiring paths, and each of the multiple wiring paths is Connect the protection circuit and / or test point, In order to equalize the wiring lengths upstream of the protection circuit and / or the test point in the plurality of wiring paths, adjustment sections of different lengths are provided in the plurality of wiring paths. By performing a dynamic display with vertical changes on the pending notification image, the system is configured to make the dynamic display of the pending notification image easily identifiable even if either the odd-numbered image data or the even-numbered image data is missing. [Effects of the Invention]

[0006] According to the present invention, it is possible to minimize the adverse effects on gameplay caused by problems related to liquid crystal control. [Brief explanation of the drawing]

[0007] [Figure 1] This is an overall front view of a pachinko machine according to the first embodiment of the present invention. [Figure 2] This is a disassembled perspective view of the same pachinko machine. [Figure 3] This is an exploded perspective view of the glass door of the same pachinko machine. [Figure 4] This is a plan view of the essential parts showing the operation performance means, cross operation button, volume adjustment button, light quantity adjustment button, etc. of the same pachinko machine. [Figure 5] This is a front view of the game board of the same pachinko machine. [Figure 6] This is a front view of the game information display means of the same pachinko machine. [Figure 7] This is a rear view of the same pachinko machine. [Figure 8] This is an exploded perspective view of the performance board case and the performance control unit of the same pachinko machine. [Figure 9] This is a plan sectional view of the performance board case and the performance control unit of the same pachinko machine. [Figure 10] This is a block diagram showing the overall circuit configuration of the same pachinko machine. [Figure 11] This is an explanatory diagram relating to the specifications of the liquid crystal display means in the same pachinko machine. [Figure 12] This is an explanatory diagram relating to the specifications of the liquid crystal control signal in the same pachinko machine. [Figure 13] This is a block diagram showing the configuration of the liquid crystal display means in the same pachinko machine. [Figure 14] This is a block diagram showing the overall configuration of the composite chip in the same pachinko machine. [Figure 15] This is a block diagram showing the main configuration of the composite chip in the same pachinko machine. [Figure 16] This is an explanatory diagram relating to the index space, index table, virtual drawing space, and drawing area in the same pachinko machine. [Figure 17] This is a block diagram describing the internal configuration of the data transfer circuit in the same pachinko machine together with the related circuit configuration. [Figure 18] This is a block diagram describing the internal configuration of the display circuit in the same pachinko machine together with the related circuit configuration. [Figure 19] This is an explanatory diagram of the data valid signal ENAB in the same pachinko machine. [Figure 20]This is a diagram showing the first wiring layer on the liquid crystal control board of the same pachinko machine. [Figure 21] This is a diagram showing the second wiring layer on the same liquid crystal control board. [Figure 22] This is a diagram showing the third wiring layer on the same liquid crystal control board. [Figure 23] This is a diagram showing the fourth wiring layer on the same liquid crystal control board. [Figure 24] This is a diagram showing the fifth wiring layer on the same liquid crystal control board. [Figure 25] This is a diagram showing the sixth wiring layer on the same liquid crystal control board. [Figure 26] This is a diagram showing terminal information of the composite chip arranged on the same liquid crystal control board. [Figure 27] This is a diagram showing terminal information of the control ROM arranged on the same liquid crystal control board. [Figure 28] This is a diagram in which wiring paths P1 to P71 are extracted from the first wiring layer of the same liquid crystal control board. [Figure 29] This is a diagram in which wiring paths P1 to P71 are extracted from the second wiring layer of the same liquid crystal control board. [Figure 30] This is a diagram in which wiring paths P1 to P71 are extracted from the third wiring layer of the same liquid crystal control board. [Figure 31] This is a diagram in which wiring paths P1 to P71 are extracted from the fourth wiring layer of the same liquid crystal control board. [Figure 32] This is a diagram in which wiring paths P1 to P71 are extracted from the fifth wiring layer of the same liquid crystal control board. [Figure 33] This is a diagram in which wiring paths P1 to P71 are extracted from the sixth wiring layer of the same liquid crystal control board. [Figure 34] This is an enlarged view of region E1a in Figure 28. [Figure 35] This is an enlarged view of region E1b in Figure 28. [Figure 36] This is an enlarged view of region E1c in Figure 28. [Figure 37] This is an enlarged view of region E3a in Figure 30. [Figure 38] This is an enlarged view of region E3b in Figure 30. [Figure 39] This is a magnified view of region E3c in Figure 30. [Figure 40] This is an enlarged view of region E4 in Figure 31. [Figure 41] This is a magnified view of region E6a in Figure 33. [Figure 42] This is a magnified view of region E6b in Figure 33. [Figure 43] This is a magnified view of region E6c in Figure 33. [Figure 44] This is a magnified view of region E6d in Figure 33. [Figure 45] This diagram schematically shows the wiring paths of wiring lines P1 to P8 in the liquid crystal control board of a pachinko machine according to the first embodiment of the present invention. [Figure 46] This diagram schematically shows the wiring paths P9 to P17 in the LCD control board. [Figure 47] This diagram schematically shows the wiring paths P18 to P26 in the LCD control board. [Figure 48] This diagram schematically shows the wiring paths P27 to P34 in the LCD control board. [Figure 49] This diagram schematically shows the wiring paths P35 to P42 in the LCD control board. [Figure 50] This diagram schematically shows the wiring paths P43 to P47 in the LCD control board. [Figure 51] This diagram schematically shows the wiring paths P48 to P51 on the LCD control board. [Figure 52] This diagram schematically shows the wiring paths P52 to P61 in the LCD control board. [Figure 53] This diagram schematically shows the wiring paths P62 to P71 in the LCD control board. [Figure 54] This is a circuit diagram of the decoding circuit in the LCD control board. [Figure 55] This is a circuit diagram of the reset circuit in the LCD control board. [Figure 56] This figure shows the silk screen printing pattern on the first wiring layer side of the liquid crystal control board. [Figure 57]This figure shows the first wiring layer in the liquid crystal interface substrate of the pachinko machine. [Figure 58] This figure shows the second and fifth wiring layers in the liquid crystal interface substrate. [Figure 59] This diagram shows the third wiring layer in the liquid crystal interface substrate. [Figure 60] This diagram shows the fourth wiring layer in the liquid crystal interface substrate. [Figure 61] This diagram shows the sixth wiring layer in the LCD interface substrate. [Figure 62] This diagram shows only the wiring paths P101 to P124 extracted from the first wiring layer of the LCD interface substrate. [Figure 63] This diagram shows the wiring paths P101 to P124 extracted from the second and fifth wiring layers of the LCD interface substrate. [Figure 64] This diagram shows the wiring paths P101 to P124 extracted from the third wiring layer of the LCD interface substrate. [Figure 65] This diagram shows the wiring paths P101 to P124 extracted from the fourth wiring layer of the LCD interface substrate. [Figure 66] This diagram shows the wiring paths P101 to P124 extracted from the 6th wiring layer of the LCD interface board. [Figure 67] This is a magnified view of region E11a in Figure 62. [Figure 68] This is a magnified view of region E11b in Figure 62. [Figure 69] This is a magnified view of region E11c in Figure 62. [Figure 70] This is a magnified view of region E16a in Figure 66. [Figure 71] This is a magnified view of region E16b in Figure 66. [Figure 72] This is a magnified view of region E16c in Figure 66. [Figure 73] This figure schematically shows the wiring paths P101 to P110 in the liquid crystal interface board of a pachinko machine according to the first embodiment of the present invention. [Figure 74] This diagram schematically shows the wiring paths P111 to P120 on the LCD interface board. [Figure 75] This diagram schematically shows the wiring paths P121 to P124 on the LCD interface board. [Figure 76] This is a circuit diagram of the area near the third LCD IF connector on the LCD interface board. [Figure 77] This is a circuit diagram of the area near the second LCD IF connector on the LCD interface board. [Figure 78] This is a circuit diagram of the main components of the LCD interface board for the pachinko machine. [Figure 79] This is a block diagram illustrating the schematic configuration of the performance control unit of the pachinko machine. [Figure 80] This figure shows the types of hold notification images and the probability of winning a jackpot in the same pachinko machine. [Figure 81] This diagram illustrates the dynamic display of the hold notification image in the pachinko machine at the start, during, and end of its display. [Figure 82] This is an explanatory diagram showing the display state of the hold notification image when either odd-numbered or even-numbered image data is missing in the pachinko machine. [Figure 83] This diagram shows the distribution of color information at the pixel level when either odd-numbered or even-numbered image data is missing in the pachinko machine. (a) shows the case where multiple types of color information are distributed vertically, and (b) shows the case where they are distributed horizontally. [Figure 84] This is an explanatory diagram for the dynamic display of the reserve notification image during shifts in the pachinko machine. [Figure 85] This diagram shows the color distribution of decorative patterns in the pachinko machine. [Figure 86] This diagram shows the dynamic display of decorative symbols in the pachinko machine. [Figure 87] This is a diagram showing the operating instructions for the pachinko machine. [Figure 88] This figure shows an example of a rainbow background image used in the full-screen rainbow image effect of the pachinko machine. [Figure 89] This figure shows the time-dependent changes in the rainbow background image of the same pachinko machine. [Figure 90] This diagram shows a specific example of the win / loss branching button effect NB1 of the same pachinko machine. [Figure 91] This figure shows the time-dependent changes in the banner-like visual effects in the same pachinko machine. [Figure 92] This diagram shows the types of operation guidance images used in the pachinko machine. [Figure 93] This figure shows the time change near the boundary of the operation validity period notification image in the pachinko machine (when it moves 2 dots per frame), with (a) showing the case where there is no loss of image data, and (b) showing the case where either odd-numbered or even-numbered image data is lost. [Figure 94] This diagram shows the time change when the boundary of the operation validity period notification image moves by one pixel per frame. (a) shows the case where there is no loss of image data, and (b) shows the case where either odd-numbered or even-numbered image data is missing. [Figure 95] This diagram shows the case where color information changes vertically in the partial rainbow image effect of the same pachinko machine. [Figure 96] This diagram shows the case where color information changes in the left-right direction during the partial rainbow image effect of the same pachinko machine. [Figure 97] This diagram shows the selection table for the setting indication effects of the pachinko machine. [Figure 98] This figure shows an example of a screen display for the setting indication feature of the pachinko machine. [Figure 99] This diagram illustrates the pixel-level color distribution in the normal and odd / even pixel-by-odd pixel loss scenarios when the rainbow effect of the pachinko machine moves by a predetermined number of dots per frame, relative to the machine's position and time. [Figure 100] This figure shows the time change of the band effect image in a pachinko machine according to a second embodiment of the present invention. [Figure 101](a) is a diagram showing an example where the star shape displayed during the reach animation is a rainbow image, and (b) is a diagram showing an example where the reach title text is a rainbow image. [Best Mode for Carrying Out the Invention]

[0008] The embodiments of the invention will be described in detail below with reference to the drawings. Figures 1 to 99 illustrate a first embodiment in which the present invention is applied to a pachinko machine. In Figures 1 and 2, the gaming machine body 1 comprises an outer frame 2 and a front frame 3 positioned in front of the outer frame 2. The front frame 3 is pivotally attached to the outer frame 2 so as to be able to open and close and to be detached via a first hinge 4 in the vertical direction, which is located on one end in the left-right direction, for example on the left end. The front frame 3 can be locked in the closed position relative to the outer frame 2 by a locking means 5 provided on the opposite side of the first hinge 4 in the left-right direction, for example on the right end.

[0009] The front frame 3 comprises an inner frame 6 and a front door 7 positioned in front of the inner frame 6. The front door 7 is pivotally attached to the inner frame 6 via a second hinge 8 in the vertical direction, positioned at one end in the left-right direction, for example, on the left end, so as to be able to open, close, and detachably attached, and can be locked in the closed position relative to the inner frame 6 by a locking means 5.

[0010] As shown in Figure 2, the outer frame 2 is formed in a rectangular shape by a pair of left and right vertical frame members 2a, 2b and a pair of upper and lower horizontal frame members 2c, 2d. A front cover member 9, for example made of synthetic resin, is attached to the lower front of the outer frame 2, connecting the lower front of the left and right vertical frame members 2a, 2b along the front edge of the lower horizontal frame member 2d. The front cover member 9 protrudes forward from the left and right vertical frame members 2a, 2b, and the inner frame 6 is positioned above it. The outer frame 2 also has an upper outer frame hinge fitting 11, which constitutes the first hinge 4, positioned for example on the upper left, and a lower outer frame hinge fitting 12, which is positioned above the front cover member 9 on the lower left.

[0011] The inner frame 6 is made of synthetic resin and integrally comprises, for example, a rectangular frame portion 13 that can substantially abut against the front edge of the outer frame 2 above the front cover member 9, a game board mounting portion 14 provided on the upper side of the frame portion 13, and a lower mounting portion 15 provided on the lower side of the frame portion 13. The game board 16 is attached to the game board mounting portion 14, for example, detachably from the front, and the launching means 17, lower speaker 18, etc. are arranged on the front side of the lower mounting portion 15. The inner frame 6 also has, for example, an upper main frame hinge fitting 19 that constitutes the first hinge 4 and an upper main frame hinge fitting 20 that constitutes the second hinge 8, located, for example, on the upper left, and a lower main frame hinge fitting 21 that constitutes the first, second hinges 4, and 8, located, for example, on the lower left.

[0012] The front door 7 is equipped with a rectangular resin door base 22 that corresponds to the front side of the inner frame 6. A window opening 24a for a glass window 24 is formed in this door base 22, corresponding to the front side of the game area 23 formed in the game board 16, and various performance means such as a plurality (four in this case) of upper speakers 25, a first movable performance means 26 for the frame, a second movable performance means 27 for the frame, and a blower means 28 are arranged around the window opening 24a.

[0013] A side unit 30 is attached to the upper front side of the door base 22, at least a portion of the outer circumference of the window opening 24a, for example, the inverted L-shaped portion in a front view corresponding to the upper to right side of the window opening 24a (Figures 1 and 3). As shown in Figures 2 and 3, the side unit 30 can be easily attached and detached with the front frame 3 open, without the use of special tools, by operating the fixing screws 30a and fixing lever 30b on the back side of the front frame 3. On the front side of the side unit 30, as shown in Figure 1, a first movable frame display means 26 having a first movable frame body 26a, a second movable frame display means 27 having a second movable frame body 27a, and a blower means 28 are mounted.

[0014] The first movable frame body 26a of the first movable display means 26 is formed into an arbitrary three-dimensional shape (here, a shape based on a butterfly), and can slide in a substantially forward and backward direction by being driven by a drive means (not shown). The second movable frame body 27a of the second movable display means 27 can slide in a substantially forward and backward direction by being driven by a drive means (not shown), and can also vibrate by a vibration means (not shown) located inside the gripping part 27b, and the player can push in the gripping part 27b. The blowing means 28 can blow air towards the player's hand at the moment the player grips the gripping part 27b. In addition, on the front side of the front door 7, including the side unit 30, a frame lamp 304 consisting of numerous LEDs 301a to 301d is arranged so as to substantially surround the glass window (display window) 24.

[0015] The lower front side of the door base 22 is equipped with an upper tray 33 for storing game balls dispensed from the dispensing means 32 located at the rear of the inner frame 6 and supplying them to the launching means 17, a lower tray 34 for storing excess balls when the upper tray 33 is full, and a launching handle 35 for operating the launching means 17. Furthermore, a lower decorative cover 36 is attached that substantially covers the upper tray 33, lower tray 34, etc. from the front. The lower decorative cover 36 is formed, for example, in a forward-facing bulge, and various operating means such as an operation and performance means 37, a cross-shaped operation button 38, a volume adjustment button 39, and a light intensity adjustment button 40 are provided on its upper side (Figure 4). The operation and performance means 37 is used for announcement effects during symbol changes and other effects, and is equipped with an up-and-down moving effect button 41 that can be pressed by the player.

[0016] As shown in Figure 2, a glass unit 50 that substantially covers the window opening 24a from the rear is detachably attached to the rear side of the door base 22. In addition, a vertical hinge end reinforcing plate 51a is positioned along the edges on the first and second hinges 4 and 8 sides, a vertical opening / closing end reinforcing plate 51b is positioned along the edge on the opening / closing end side, and a horizontal lower reinforcing plate 51c is positioned below the window opening 24a, which are detachably fixed by screws or the like. Furthermore, the upper glass door hinge fitting 52a, which constitutes the second hinge 8, is positioned, for example, in the upper left, and the lower glass door hinge fitting 52b is positioned, for example, in the lower left.

[0017] Furthermore, for example, a ball feeding unit 53a, a lower tray guide unit 53b, etc., are mounted on the rear side of the lower reinforcing plate 51c. The ball feeding unit 53a is for supplying game balls from the upper tray 33 to the launching means 17, and is positioned in front of the launching means 17 which is located on the inner frame 6 side. By operating the ball feeding solenoid 53c in synchronization with the launching operation of the launching means 17, the balls from the upper tray 33 are supplied one by one onto the launching rail 17a of the launching means 17.

[0018] The launching mechanism 17 includes a launching rail 17a arranged in an upward sloping manner when viewed from the front, a launching ball stopper 17b that supports the game balls supplied onto the launching rail 17a by the ball feeding unit 53a in a launching standby position, a striking hammer 17c positioned on the launching rail 17a corresponding to the launching standby position and capable of swinging around a drive axis in the front-rear direction, and a launching drive mechanism 17d such as a rotary solenoid that swings the striking hammer 17c. When the launching handle 35 is rotated, the launching drive mechanism 17d continuously drives the striking hammer 17c in the striking direction (clockwise) with a launching intensity corresponding to the amount of rotation.

[0019] The lower tray guide unit 53b is for guiding excess balls when the upper tray 33 is full, and foul balls that have been launched by the launching means 17 but have returned without reaching the game area 23, to the lower tray 34. For example, it is located adjacent to the ball feeding unit 53a, on the side of its first and second hinges 4 and 8.

[0020] As shown in Figure 5, the game board 16 includes a base plate 55 made of plywood, polycarbonate, or the like. Guide rails 56 are arranged in a ring shape on the front side of the base plate 55 to guide the game balls launched from the launching means 17. In the game area 23 inside the guide rails 56, unit components such as a central display frame unit 57, a starting prize unit 58, and a normal prize unit 59 are arranged, as well as numerous game pins (not shown). Additionally, for example, a game information display means 60 is arranged on the lower outside of the game area 23.

[0021] As shown in Figure 6, the game information display means 60 is equipped with four LED groups, each consisting of eight LEDs 70. A predetermined number of these 32 LEDs 70 are assigned to the normal symbol display means 61, the normal reserve count display means 62, the first special symbol display means 63, the second special symbol display means 64, the first special reserve count display means 65, the second special reserve count display means 66, the variation shortening notification means 67, the right-hand shooting notification means 68, and the round number notification means 69. Specifically, the eight LEDs 70 belonging to the first and second LED groups 60a and 60b each constitute the first and second special symbol display means 63 and 64, respectively; the eight LEDs 70 belonging to the third LED group 60c are divided into pairs to constitute the first special reserved number display means 65, the second special reserved number display means 66, the normal reserved number display means 62, and the variation shortening notification means 67, respectively; and the eight LEDs 70 belonging to the fourth LED group 60d consist of two normal symbol display means 61, two right-hand shooting notification means 68, and the remaining four round number notification means 69.

[0022] Multiple unit components 57-59 of the game board 16 are provided with a normal symbol starting means 71, a first special symbol starting means 72, a second special symbol starting means 73, a big prize winning means 74, multiple normal prize winning means 75, etc. Also, on the rear side of the base plate 55, in addition to a liquid crystal display means (image display means) 76, a movable display means 77 equipped with a movable mechanism 77a that can move in front of the liquid crystal display means 76 is arranged.

[0023] The movable component 77a is formed in the shape of a horizontally elongated rectangular box, and both its left and right ends are supported so as to be able to move up and down on the outside of the side edges of the liquid crystal display means 76. Driven by a drive means (not shown), it can move up and down between the upper origin position of the liquid crystal display means 76 (see Figure 5) and the front operating position of the liquid crystal display means 76. In addition, a movable component lamp 314 consisting of multiple LEDs 311 is arranged on the front side of the movable component 77a.

[0024] The central display frame unit 57 constitutes the display frame for the liquid crystal display means 76 and the movable mechanism 77a. An opening window 80 corresponding to the rear liquid crystal display means 76 is formed approximately in the center, and it is detachably attached from the front to a mounting hole (not shown) formed in the base plate 55 that penetrates in the front-to-back direction. As shown in Figure 5, the central display frame unit 57 comprises a front mounting plate 81 positioned outside the mounting hole along the front surface of the base plate 55 and through which game balls can pass; a decorative frame 82 positioned in a roughly gate shape in front of the liquid crystal display means 76, extending from both the left and right sides to the upper side, and projecting forward from the inner circumference of the front mounting plate 81; and a stage 83 positioned between the left and right lower ends of the decorative frame 82. The game balls, launched by the launching means 17 and entering the upper part of the game area 23, are divided to the left and right at the top of the decorative frame 82 and flow down either the left-flow path 84a on the left side of the central display frame unit 57 or the right-flow path 84b on the right side.

[0025] The central display frame unit 57 is provided with a warp inlet 85 into which game balls can flow, on at least one side of the left-flow path 84a and the right-flow path 84b, for example, on the left-flow path 84a side. Game balls that flow down the left-flow path 84a and enter the warp inlet 85 roll freely in the left-right direction on the stage 83, and then fall forward from either the central drop section 86, which is provided corresponding to the left-right center of the game area 23, or the other parts.

[0026] Furthermore, a panel lamp 324 consisting of numerous LEDs 321a to 321c is arranged on the front side of the central display frame unit 57, corresponding to at least a portion of the outer periphery of the liquid crystal display means 76, for example, both the left and right sides and the top side. Note that some of the panel lamps 324 may also be arranged in the starting prize unit 58, the normal prize unit 59, etc.

[0027] As shown in Figure 5, the starting prize unit 58 is positioned below the central display frame unit 57 along the guide rail 56 and is detachably attached to the base plate 55 from the front. As shown in Figure 5, the normal prize unit 59 is positioned below the central display frame unit 57 to the left of the starting prize unit 58 along the guide rail 56 and is detachably attached to the base plate 55 from the front.

[0028] The normal symbol starting means 71 is for initiating the display of the normal symbols by the normal symbol display means 61, and is composed of a passage gate or the like through which the game ball can pass, and is equipped with a game ball detection switch (not shown) for detecting the passage of the game ball. As shown in Figure 5, this normal symbol starting means 71 is provided, for example, on the front side of the front mounting plate 81 on the right side of the central display frame unit 57, and is accessible to game balls flowing down the rightward flow path 84b.

[0029] The normal symbol display means 61 is for displaying a normal symbol in a variable manner. As shown in Figure 6, it consists of a predetermined number (two in this case) of LEDs 70 in the game information display means 60. Based on the normal symbol start means 71 detecting a game ball, the two LEDs 70 constituting the normal symbol light up in a normal variable light pattern. Then, if the random value for winning judgment included in the normal random number information acquired when the normal symbol start means 71 detects the game ball matches a predetermined winning judgment value, the variable stops in a winning state; otherwise, it stops in a losing state. The two LEDs 70 constituting the normal symbol can display one or more winning states and one or more losing states by combining their light patterns (e.g., on / off). The light pattern during normal variation is configured to switch between, for example, a specific set of multiple types (two in this case) of light patterns at predetermined intervals (e.g., 128ms).

[0030] Furthermore, if the normal symbol activation means 71 detects a game ball during the normal symbol display means 61's symbol variation and normal profit state, the acquired normal random number information is stored in a predetermined upper limit, for example, 4 units, and one unit is consumed each time the normal symbol variation ends, causing the normal symbols to change. The number of stored normal random number information units (normal reserve units) is notified to the player by the normal reserve unit display means 62, etc. As shown in Figure 6, the normal reserve unit display means 62 is composed of a predetermined number (2 units in this case) of LEDs 70 in the game information display means 60, and by combining the respective light emission modes (e.g., on / flashing / off) of these two LEDs 70, it is possible to display 5 different normal reserve units from 0 to 4 units.

[0031] The first special symbol starting means 72 is for initiating the symbol change by the first special symbol display means 63, and is composed of a non-opening type prize entry means that does not have an opening / closing mechanism, and is equipped with a game ball detection switch (not shown) for detecting the game ball that has entered the prize. As shown in Figure 5, this first special symbol starting means 72 is provided, for example, in the starting prize entry unit 58, and is positioned with an upward opening below the central drop section 86 of the stage 83, corresponding to the central drop section 86 of the stage 83, and there is a route from the warp entrance 85 on the left flow path 84a side through the stage 83 to enter the prize, so that game balls that have flowed down the left flow path 84a have a higher probability of entering the prize than game balls that have flowed down the right flow path 84b. When a game ball enters this first special symbol starting means 72, a predetermined number of game balls are paid out as prize balls for each prize.

[0032] The second special symbol starting means 73 is for initiating the symbol change by the second special symbol display means 64. It is composed of an open / close type prize-winning means that can change between an open state in which a game ball can be won and a closed state in which a game ball cannot be won (or is more difficult to win than in the open state) by the operation of the opening / closing part 88. It includes a game ball detection switch (not shown) for detecting a game ball that has been won, and an opening / closing drive means such as an electromagnetic solenoid for opening and closing the opening / closing part 88. When the stopped symbol after the change of the normal symbol display means 61 becomes a winning pattern and a normal profit state occurs, the opening / closing part 88 changes from the closed state to the open state for a predetermined time.

[0033] As shown in Figure 5, the second special symbol starting means 73 is positioned, for example, on the front mounting plate 81 on the right side of the central display frame unit 57 and downstream of the normal symbol starting means 71, allowing game balls that have flowed down the rightward flow path 84b to enter. The opening / closing part 88 can swing around a left-right rotation axis provided on the lower side, for example. In the closed state, it is almost flush with the front mounting plate 81, allowing game balls to pass in front of it. In the open state, it is inclined downwards towards the rear in front of the front mounting plate 81, allowing game balls to enter backwards. When a game ball enters the second special symbol starting means 73, a predetermined number of game balls are dispensed as prize balls for each entry.

[0034] As shown in Figure 6, the first special symbol display means (symbol display means) 63 is composed of a predetermined number (in this case, 8) of LEDs 70 in the game information display means 60. When the first special symbol starting means 72 detects a game ball, the 8 LEDs 70 constituting the first special symbol light up in a special variation light pattern. Then, if the jackpot judgment random number value included in the first special random number information acquired when the first special symbol starting means 72 detects a game ball (when the symbol starting condition is met) matches a predetermined jackpot judgment value (when a jackpot is determined by random number drawing), the variation stops in a jackpot mode. Similarly, if it matches a minor win judgment value (when a minor win is determined by random number drawing), the variation stops in a minor win mode. Otherwise, the variation stops in a losing mode. When the stopped symbol of the first special symbol display means 63 after variation is in a jackpot mode, a jackpot game is executed; when it is in a minor win mode, a minor win game is executed (profit state generation means).

[0035] As shown in Figure 6, the second special symbol display means (symbol display means) 64 is composed of a predetermined number (in this case, 8) of LEDs 70 in the game information display means 60. When the second special symbol starting means 73 detects a game ball, the 8 LEDs 70 constituting the second special symbol light up in a special variation light pattern. Then, if the jackpot judgment random number value included in the second special random number information acquired when the second special symbol starting means 73 detects a game ball (when the symbol starting condition is met) matches a predetermined jackpot judgment value (when a jackpot is determined by random number drawing), the variation stops in a jackpot mode. Similarly, if it matches a minor win judgment value (when a minor win is determined by random number drawing), the variation stops in a minor win mode. Otherwise, the variation stops in a losing mode. If the stopped symbol after variation of the second special symbol display means 64 is in a jackpot mode, a jackpot game is executed; if it is in a minor win mode, a minor win game is executed (profit state generation means).

[0036] The first and second special symbol display means 63 and 64 can display one or more jackpot patterns, one or more minor jackpot patterns, and one or more losing patterns by combining the light emission patterns (e.g., on / off) of the eight LEDs 70 each. In addition, the light emission pattern during special variations is configured to switch between a specific set of multiple light emission patterns (two in this case) at predetermined intervals (e.g., 128ms).

[0037] Furthermore, if the first and second special symbol starting means 72 and 73 detect a game ball during the special reserve period, including the symbol change of the first special symbol display means 63, the symbol change of the second special symbol display means 64, and during a jackpot game, the first and second special random number information acquired thereby is stored in the reserve storage means, each up to a predetermined upper limit of four reserved values. When the special reserve period ends, if there is one or more reserved values ​​for the second special symbol, one reserved value for the second special symbol is consumed and the second special symbol changes. If only the reserved value for the first special symbol is one or more, one reserved value for the first special symbol is consumed and the first special symbol changes. Thus, in this embodiment, the first and second special symbols are never both changing at the same time, and if there are reserved values ​​for both the first and second special symbols, the second special symbol changes are prioritized.

[0038] In this embodiment, during normal gameplay, except during the special game state described later, the player aims to the first special symbol starting means 72 and shoots to the left, and during the special game state, the player aims to the normal symbol starting means 71 and the second special symbol starting means 73 and shoots to the right. Therefore, during normal gameplay, the first special symbol mainly changes, and during the special game state, the second special symbol mainly changes.

[0039] The number of first and second special random number information items (first and second special reserved numbers) stored in the reserved storage means is notified to the player by the first and second special reserved number display means 65, 66, liquid crystal display means 76, etc. Here, as shown in Figure 6, the first and second special reserved number display means 65, 66 are composed of a predetermined number (two each) of LEDs 70 in the game information display means 60, and by combining their light emission modes (e.g., on / flashing / off), it is possible to display five types of first and second special reserved numbers, from 0 to 4.

[0040] Furthermore, the probability of winning a jackpot (jackpot probability) in the jackpot determination (random number drawing) performed based on the detection of game balls by the first and second special symbol starting means 72 and 73 has two types: low probability and high probability. During the probability variation state, one of the special game states described later, the probability is set to high, and at all other times, it is set to low probability. In this embodiment, the setting value can be set to any of several levels (6 levels in this case), and the jackpot probability (low probability and high probability) changes according to the setting value (settings 1 to 6). For example, the jackpot probability is higher as the setting value increases.

[0041] Furthermore, if the jackpot determination result is a miss, one or more types of misses are selected; if the jackpot determination result is a minor win, one or more types of minor wins are selected; and if the jackpot determination result is a jackpot, one or more types of jackpots (for example, two types: a probability-increasing jackpot and a non-probability-increasing jackpot) are selected. Here, a probability-increasing jackpot is a jackpot that generates a probability-increasing state (first special game state) as a special game state after the jackpot game ends, and a non-probability-increasing jackpot is a jackpot that generates a special game state, for example, a time-saving state (second special game state), as a special game state after the jackpot game ends. The distribution of these is based on the random values ​​of the jackpot symbols, etc.

[0042] During the time-saving state, for example, the fluctuation time of the first and second special symbol display means 63 and 64 for the first and second special symbols is switched to a shortened fluctuation time, which is shorter than the normal fluctuation time. For the regular symbols, the probability of winning is switched from the normal probability to the high probability, the fluctuation time is switched from the normal fluctuation time to the shortened fluctuation time, and the opening and closing pattern of the second special symbol starting means 73 in the normal profit state is switched from the normal opening and closing pattern (e.g., 0.2 seconds x 1 opening) to the special opening and closing pattern (e.g., 2 seconds x 3 openings). The time-saving state starts when a jackpot game ends and ends when, for example, the first and second special symbols have fluctuated a predetermined number of times (e.g., 50 times), or when the next jackpot game occurs before that. During the probability variation state, in addition to the same switching as in the time-saving state, for example, the probability of winning a jackpot is switched from the low probability to the high probability. The probability variation state starts when a jackpot game ends and ends when, for example, the next jackpot game occurs.

[0043] The grand prize winning mechanism 74 is an open / close type prize winning mechanism equipped with an open / close plate 89 that can be switched between an open state in which a game ball can enter and a closed state in which it cannot enter. As shown in Figure 5, it is provided, for example, on the central display frame unit 57 and is equipped with a game ball detection switch (not shown) for detecting a game ball that has entered a prize, and an open / close drive means such as an electromagnetic solenoid for opening and closing the open / close plate 89. Because it is positioned downstream of the second special symbol starting mechanism 73 and upstream of the first special symbol starting mechanism 72, game balls that have flowed down the rightward flow path 84b have a higher probability of entering a prize than game balls that have flowed down the leftward flow path 84a. This big prize mechanism 74 opens in a predetermined big win opening pattern (big win game) if the first and second special symbols of the first and second special symbol display means 63 and 64 stop in a big win pattern (specific pattern) after changing, and opens in a predetermined small win opening pattern (small win game) if they stop in a small win pattern. When a game ball enters this big prize mechanism 74, a predetermined number of game balls are paid out as prize balls for each entry.

[0044] Furthermore, the liquid crystal display means 76 is capable of displaying decorative patterns 90 in parallel with the display of the first and second special patterns by the first and second special pattern display means 63 and 64, and can also display various images such as the first and second reserved notification images X1~X4, Y1~Y4 indicating the number of first and second special reserved items, and the reserved item notification image Z during variation.

[0045] Here, the decorative pattern 90 has multiple rows of patterns (three in the left-right direction in the example of Figure 5) which are composed of a number pattern and other multiple patterns. Each pattern that makes up one of these rows of patterns is composed of a pattern body 90a consisting of numbers such as 1 to 8 and other patterns, and a character or other decorative part 90b attached to this pattern body 90a, as shown in Figure 5. The decorative pattern 90 can be arbitrarily changed in its display manner, such as by enlarging or reducing it, changing its display position, or erasing the decorative part 90b.

[0046] The decorative symbols 90 begin to move vertically, horizontally, or otherwise according to a predetermined movement pattern for each row of symbols, approximately simultaneously with the start of movement of the first and second special symbols, and come to a final stop approximately simultaneously with the stop of movement of the first and second special symbols, so that the stopping symbols on a predetermined active line are in a predetermined state. In the case of the decorative symbols 90, for example, if all the stopping symbols on an active line are the same, it is a jackpot presentation, and otherwise it is a minor win presentation or a losing presentation. If the first and second special symbols are in a jackpot presentation, the decorative symbols 90 will be in a jackpot presentation; if the first and second special symbols are in a minor win presentation, the decorative symbols 90 will be in a minor win presentation; and if the first and second special symbols are in a losing presentation, the decorative symbols 90 will be in a losing presentation.

[0047] Furthermore, with respect to the first and second reserved notification images X1~X4, Y1~Y4 and the variable reserved notification image Z, when the number of first and second special reserved balls increases based on the detection of game balls by the first and second special symbol starting means 72, 73, one additional first and second reserved notification image X1~, Y1~ is displayed on the liquid crystal display means 76. Also, when the number of first and second special reserved balls decreases based on the start of a new variation of the first and second special symbols by the first and second special symbol display means 63, 64, for example, the variable reserved notification image Z is erased, the first and second reserved notification images X1~, Y1~ are shifted one by one toward the front of the queue (for example, the right side of the screen), and the leading first and second reserved notification images X1, Y1 that have been pushed out are moved to a predetermined position, for example, and changed into a new variable reserved notification image Z.

[0048] Furthermore, as shown in Figure 7, a back case 91 is attached to the back of the game board 16 to support the liquid crystal display means 76 at the rear of the game board 16. On the back side of this back case 91, a main board case 94 housing the main control board 93 which constitutes the main control unit 92, and a performance board case 100 housing the performance interface board 96, liquid crystal interface board 97, liquid crystal control board 98 and ROM board 99 which constitute the performance control unit 95 are detachably attached.

[0049] Here, the details of how the performance interface board 96, liquid crystal interface board 97, liquid crystal control board 98, and ROM board 99 are stored in the performance board case 100 will be explained with reference to Figures 8 and 9.

[0050] The performance interface board 96 and the liquid crystal interface board 97 are positioned close to each other on the left and right sides, with their respective surfaces 96a and 97a facing backward. The performance interface board 96 and the liquid crystal interface board 97 are integrated by directly connecting the first and second performance IF connectors CN11 and CN12, which are positioned along the edge of the performance interface board 96 on the liquid crystal interface board 97 side, and the first and second liquid crystal IF connectors CN21 and CN22, which are positioned along the edge of the liquid crystal interface board 97 on the performance interface board 96 side, in the left-right direction. Various electronic components are arranged on both the front and back surfaces of the performance interface board 96, but various ICs such as the audio processor 101 and digital amplifier 102, various connectors such as the first to third liquid crystal IF connectors CN21 to CN23, and the audio ROM 103 are located on the front surface 96a side. Furthermore, while various electronic components are arranged on both the front and back surfaces of the liquid crystal interface board 97, various connectors such as the first to third liquid crystal interface connectors CN21 to CN23, as well as the first and second liquid crystal connection connectors CN24 and CN25 for connecting the liquid crystal display means 76, are located on the front surface 97a.

[0051] Furthermore, the liquid crystal control board 98 is positioned behind the performance interface board 96 and the liquid crystal interface board 97, with its front surface 98a facing backward and its back surface 98b facing the front surfaces 96a and 97a of the performance interface board 96 and the liquid crystal interface board 97. The liquid crystal control board 98 is integrated with the performance interface board 96 and the liquid crystal interface board 97 by directly connecting the first liquid crystal control connector CN31 on its back surface 98b to the third performance IF connector CN13 on the performance interface board 96, and the second liquid crystal control connector CN32, also on its back surface 98b, to the third liquid crystal IF connector CN23 on the liquid crystal interface board 97. Various electronic components are arranged on both the front and back surfaces of the liquid crystal control board 98. The front surface 98a has a composite chip 104, a control ROM 105, a DRAM 106, and the third liquid crystal control connector CN33, etc., while the back surface 98b has the first and second liquid crystal control connectors CN31 and CN32, etc.

[0052] Furthermore, the ROM board 99 is positioned adjacent to the liquid crystal control board 98, for example, on its underside, with its front surface 99a facing backward and its back surface 99b facing the front surface 97a of, for example, the liquid crystal interface board 97, one of the two display interface boards 96 and liquid crystal interface boards 97. The ROM board 99 is integrated with the liquid crystal control board 98 by directly connecting the ROM first connector CN41, located on the upper edge of its front surface 99a, to the liquid crystal control third connector CN33, located on the lower edge of the liquid crystal control board 98. Various electronic components are arranged on both the front and back surfaces of the ROM board 99, but the CGROM 107, ROM first connector CN41, etc., are located on the front surface 99a side.

[0053] As explained above, the circuit boards 96 to 99 are connected and integrated by directly connecting their connectors to each other, so that the front surfaces 96a and 97a of the performance interface board 96 and the liquid crystal interface board 97 are connected to the back surfaces 98b and 99b of the liquid crystal control board 98 and the ROM board 99, with a predetermined gap between them. Therefore, when the circuit boards 96 to 99 are connected to each other, the back surface 98b of the liquid crystal control board 98 is hidden by the performance interface board 96 and the liquid crystal interface board 97 and cannot be seen.

[0054] The performance board case 100 is made of transparent synthetic resin and is formed in a roughly box shape with a base body 111 that covers the back side of the circuit boards 96-99 and a cover body 112 that covers the front side of the circuit boards 96-99. When storing the circuit boards 96-99 in the performance board case 100, the liquid crystal control board 98 and the ROM board 99 are first connected to each other by direct connection of connectors and then fixed to a predetermined position inside the cover body 112 with screws. At this time, the surfaces 98a and 99a of the liquid crystal control board 98 and the ROM board 99 face each other on the inner side of the back wall 113 of the cover body 112 with a predetermined gap in between.

[0055] Next, with the performance interface board 96 and the liquid crystal interface board 97 connected to each other by direct connection of connectors, they are fitted into predetermined positions inside the cover body 112 from the back side of the liquid crystal control board 98 and the ROM board 99. At this time, the performance IF third connector CN13 on the performance interface board 96 is connected to the liquid crystal control first connector CN31 on the liquid crystal control board 98, and the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 is connected to the liquid crystal control second connector CN32 on the liquid crystal control board 98.

[0056] Next, the base body 111 is fitted onto the cover body 112 from the back surfaces 96b and 97b of the performance interface board 96 and the liquid crystal interface board 97. Then, the boards 96-99 are fixed in their predetermined positions inside the performance board case 100 by screwing them to the screw base 115 on the cover body 112 through the through holes 114 in the performance interface board 96 and the liquid crystal interface board 97 from the outside of the base body 111. The performance board case 100, which houses the boards 96-99, is detachably attached to the back side of the back case 91 with the base body 111 facing forward and the cover body 112 facing backward.

[0057] Furthermore, as shown in Figure 7, a rear cover 121 is detachably attached to the back of the front frame 3, which opens and closes to cover the back of the game board 16. Above it are a game ball tank 122 and a tank rail 123, and on one side are a dispensing means 32 and a dispensing passage 124. When a game ball enters a prize-winning opening such as the big prize means 74, or when a ball dispensing command is received from an automatic ball dispensing machine (not shown), the game balls in the game ball tank 122 are dispensed via the tank rail 123 by the dispensing means 32, and the game balls are guided to the upper tray 33 via the dispensing passage 124. The rear cover 121 is positioned to cover almost the entire performance board case 100 and a portion of the upper side of the main board case 94 from the rear.

[0058] Furthermore, a circuit board mounting base 125 is detachably attached to the lower back of the front frame 3, and a power supply board case 127 housing a power supply board 126 and a dispensing / launching board case 129 housing a dispensing / launching control board 128 are detachably attached to the back of this circuit board mounting base 125.

[0059] Figure 10 is a block diagram showing the overall configuration of the control system of this pachinko machine. As shown in Figure 10, the overall circuit configuration of this pachinko machine consists of a board-side member 131 mounted on the game board 16 side and a frame-side member 132 mounted on the front frame 3 side.

[0060] First, let's describe the overview of the control panel side member 131. The control panel side member 131 consists of the main control board 93 which constitutes the main control unit 92, the performance interface board 96 which constitutes the performance control unit 95, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99, as well as the game board relay board 133, LED connection board 134, main control relay board 135, power supply relay board 136, frame LED relay board 137, etc.

[0061] The main control board 93 comprehensively controls the game, and is connected to game ball detection switches provided in the normal symbol starting means 71 and the big prize means 74, opening and closing drive means provided in the big prize means 74, various sensors such as magnetic, radio wave, and vibration sensors located in various parts of the game board 16, and game information display means 60, either via relay boards such as the game board relay board 133 or directly without going through relay boards. The main control board 93 is also connected to the performance interface board 96 via the performance control harness 138, and is capable of transmitting control commands CMD and strobe signals STB.

[0062] The main control relay board 135, the power supply relay board 136, and the frame LED relay board 137 are for connecting the panel-side member 131 to the frame-side member 132. The main control board 93 is connected to the payout launch control board 128 via the main control relay board 135, and the performance interface board 96 is connected to the power supply board 126 via the power supply relay board 136 and to the frame lower LED connection board 139 via the frame LED relay board 137. On the game board 16 side, the main control relay board 135, power relay board 136, and frame LED relay board 137 are arranged so that the first to third connectors CN1a to CN3a on the game board side correspond to the rear side of the game board 16, and the first to third connectors CN1b to CN3b on the frame side are arranged so that they correspond to the first to third connectors CN1a to CN3a on the game board mounting section 14 (Figure 2) on the inner frame 6 side, and when the game board 16 is mounted on the game board mounting section 14 of the inner frame 6 from the front, the first to third connectors CN1a to CN3a on the game board side are connected to the first to third connectors CN1b to CN3b on the frame side, respectively. The frame-side first connector CN1b is provided on one end of the payout / launch control relay harness 141 connected to the payout / launch control board 128, the frame-side second connector CN2b is provided on one end of the performance control power harness 142 connected to the power supply board 126, and the frame-side third connector CN3b is provided on one end of the lower frame LED connection harness 143 connected to the lower frame LED connection board 139.

[0063] As previously explained, the performance interface board 96, liquid crystal interface board 97, liquid crystal control board 98, and ROM board 99 that constitute the performance control unit 95 are integrated with each other by directly connecting their connectors without the need for a harness.

[0064] Furthermore, the liquid crystal display means 76 is connected to the liquid crystal interface board 97 via the first and second liquid crystal connection harnesses 144 and 145 from the first and second liquid crystal connection connectors CN24 and CN25. In addition, the LED connection board 134 is connected to the performance interface board 96 via the LED connection harness 146. The LED connection board 134 is connected to various LED boards such as the LED board 312 that constitutes the movable prop lamp 314 and the LED boards 322a to 322c that constitute the panel lamp 324, as well as movable body driving means such as motors and solenoids used for driving control of the movable prop 77a, and position detection switches.

[0065] Here, the specifications of the liquid crystal display means 76 will be explained based on Figure 11, etc. The liquid crystal display means 76 is a liquid crystal color display with 1280 pixels horizontally and 1024 pixels vertically. Control signals (ODD signal, EVEN signal) corresponding to adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) in the left-right direction are received by the receiving unit RV (RVa + RVb) via separate LVDS (Low Voltage Differential Signaling) transmission lines. In this embodiment, in accordance with these specifications, the ODD signal (first signal) is transmitted via the first transmission line LVDS1 using the liquid crystal connection first connector CN24, the liquid crystal connection first harness 144, etc., and the EVEN signal (second signal) is transmitted via the second transmission line LVDS2 (lower left of Figure 10).

[0066] Furthermore, in this liquid crystal display means 76, the operating clock CK that defines the internal operation is specified to have a frequency in the range of 40MHz to 70MHz (typical value is 54MHz). This operating clock CK corresponds to the dot clock DCK, but for convenience, in the following explanation, the frequency of the operating clock CK will be assumed to be the typical value of 54MHz. We will now describe a configuration in which the update time (frame rate) required to update one frame of image is approximately 1 / 60th of a second with this 54MHz operating clock CK.

[0067] The liquid crystal display means 76 is configured to process two adjacent pixels in the left-right direction of the display screen simultaneously with a single operating clock CK, based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. As a result, the pixel data for 1280 pixels corresponding to one horizontal line is updated in an operating time of 640 / 54MHz = 11.85μS, and this operation is repeated for 1024 lines in the vertical direction, thereby updating the image display of 1280 × 1024 pixels for one frame. The image is updated line by line in a non-interlaced manner, such as 1st line → 2nd line → ... → 1024th line.

[0068] However, as shown in Figure 11, the specifications of the liquid crystal display means 76 stipulate that a typical waiting time (blank period) WTh be provided horizontally for 204 clock cycles, and a typical waiting time (blank period) WTv be provided vertically for 42 lines. Therefore, considering these waiting times WTh and WTv, the actual screen update cycle, calculated based on the typical values ​​described above, is (204 + 640) × (42 + 1024) / 54 MHz ≈ 16.66 ms, resulting in a frame rate of approximately 60 Hz.

[0069] Note that the horizontal standby time WTh and vertical standby time WTv each have specified tolerance ranges relative to their typical values, and in practice, it is possible to select values ​​different from the typical values ​​mentioned above. However, in order to achieve a frame rate of 1 / 60th of a second, the horizontal and vertical standby times WTh and WTv must be set precisely so that (WTh + 640) × (WTv + 1024) / 54MHz = 1 / 60th of a second.

[0070] Furthermore, while the liquid crystal display means 76 does not require the horizontal synchronization signal HS and the vertical synchronization signal VS, it does require the transmission of a data valid signal ENAB at an H level when transmitting the ODD signal and the EVEN signal. In other words, when a significant signal (ODD / EVEN signal) is being transmitted to the first and second transmission lines LVDS1 and LVDS2, the data valid signal ENAB needs to be at an active level (H level).

[0071] Therefore, in this embodiment, based on the specifications of the liquid crystal display means 76 described above, the liquid crystal control board (display control means) 98 and the liquid crystal display means 76 are connected via LVDS using a dual-link transmission line with a dot clock (pixel clock) DCK of 54 MHz (Figures 13 and 18). In addition, the VDP circuit 172 mounted on the liquid crystal control board 98 (Figure 14, etc.) is provided with a horizontal standby time WTh and a vertical standby time WTv that satisfy the specifications of the liquid crystal display means 76, and when outputting image data (ODD / EVEN signals), the data validity signal ENAB is set to an active level (H level).

[0072] In other words, as shown in Figure 12(b), the data valid signal ENAB is configured such that only the horizontal display period THd of the horizontal synchronization period TH is at an H level. Therefore, the data valid signal ENAB is always at an L level except for the vertical display period TVd of the vertical synchronization period TV (Figure 12(c)). Note that the horizontal standby time WTh and the vertical standby time WTv are set to values ​​different from their typical values ​​(WTh is 204, WTv is 42), but the specific design values ​​will be described later based on Figure 19.

[0073] In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operating cycle of the dot clock DCK via the differential signal lines RA2 and RB2, as shown in Figure 12(a). The data valid signal ENAB shown in Figures 12(b) and (c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous sequence of discrete DE signals on the time axis. In addition, as shown in Figure 12(a), the vertical synchronization signal VS and the horizontal synchronization signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB) via the differential signal lines RA2 and RB2, but the liquid crystal display means 76 of this embodiment does not utilize the synchronization signals VS and HS, and no internal operations related to these synchronization signals HS and VS are performed.

[0074] In other words, the horizontal line break timing of the display lines in the liquid crystal display means 76 of this embodiment is determined to be the optimal timing for the internal circuit of the liquid crystal display means 76, based on the falling edge timing of the data valid signal ENAB and the number of operation clocks CK (corresponding to the dot clock DCK) after the rising edge timing of the data valid signal ENAB (640 in this embodiment), regardless of the received horizontal synchronization signal HS (downward arrow in Figure 12(b)).

[0075] This also applies to the vertical line break timing after displaying one frame of image. Based on the number of consecutive data valid signals ENAB with a predetermined pulse width (1024 in this embodiment), the timing is determined to be optimal for the internal circuitry of the liquid crystal display means 76 (downward arrow in Figure 12(c)), and is not affected by the received vertical synchronization signal VS. Thus, in this embodiment, there is no need to transmit the horizontal synchronization signal HS or the vertical synchronization signal VS to the liquid crystal display means 76. Therefore, there is no need to optimally set the pulse widths PWh, PWv of the synchronization signals HS and VS, the front porch FPh, FPv, the back porch BPh, BPv, etc., and the control burden on the VDP circuit 172, etc., is greatly reduced.

[0076] Furthermore, the internal operation of the liquid crystal display means 76 is such that horizontal and vertical line breaks are performed at optimal timings based on its own internal configuration, thus eliminating the risk of unnatural display operation. Incidentally, in the case of display means that operate based on horizontal synchronization signals HS and vertical synchronization signals VS received from an external source, if the pulse width of the synchronization signals HS and VS, or the front porch and back porch periods before and after the synchronization signals HS and VS are inappropriate, normal display operation may be impaired.

[0077] By the way, in Figure 12(a), the first transmission line LVDS1, which uses differential signal lines RA0~RA3 and RACLK, transmits the signal corresponding to the odd-numbered pixels (A-side ODD signal), and the second transmission line LVDS2, which uses differential signal lines RB0~RB3 and RBCLK, transmits the signal corresponding to the even-numbered pixels (B-side EVEN signal). In this embodiment, by transmitting the ODD signal and the EVEN signal via a dual-link transmission line, the frequency of the dot clock DCK can be reduced to virtually half, thereby improving noise immunity and increasing the transmission distance.

[0078] On the other hand, the liquid crystal display means 76 has a built-in receiver RV that receives the ODD signal and EVEN signal transmitted via a dual-link transmission line, and reconstructs the RGB signal from the two LVDS signals (ODD signal and EVEN signal) to display one frame (1280 x 1024 pixels) of image. Since each RGB signal is composed of 8 bits, the liquid crystal display means 76 has 2 gradation levels. 8 ×2 8 ×2 8 A full-color image will be displayed.

[0079] Figure 13 is a block diagram illustrating the internal configuration of the liquid crystal display means 76, along with the related parts of the VDP circuit 172. As shown in the figure, the ODD signal is transmitted to the LVDS-to-parallel converter RVa via the first transmission line LVDS1 (A side), and the EVEN signal is transmitted to the LVDS-to-parallel converter RVb via the second transmission line LVDS2 (B side). The first transmission line LVDS1 is equipped with five differential signal lines RA0~RA3 and RACLK, and the second transmission line LVDS2 is equipped with five differential signal lines RB0~RB3 and RBCLK.

[0080] From the differential signal lines RA0 / RB0, image data R0~R5 and G0 of the 8-bit RGB data are output; from the differential signal lines RA1 / RB1, image data G1~G5, B0, and B1 are output; from the differential signal lines RA2 / RB2, image data B2~B5, the DE signal (i.e., the data validity signal ENAB), the VS signal, and the HS signal are output; and from the differential signal lines RA3 / RB3, image data G6, G7, B6, B7, R6, and R7 are output. As mentioned above, the outputted VS and HS signals are not used.

[0081] Furthermore, the dot clock DCK of the differential signal lines RACLK / RBCLK is supplied to the PLL circuit, generating an operating clock CK with the same frequency as the dot clock DCK, at 54MHz. This operating clock CK defines the internal operation of the liquid crystal controller LCD_CTL, which processes image data corresponding to two adjacent RGB pixels (8 bits x 3 x 2) in the left-right direction on the liquid crystal panel LCD, synchronized with a single operating clock CK.

[0082] Therefore, processing 1280 (=640×2) pixels horizontally is completed in 11.85μS (=640 / 54MHz), which is the processing time for 640 operating clocks CK. Note that the image data corresponding to one pixel is 1 byte in length for each of RGB (2 gradation levels). 8 ×2 8 ×2 8 Therefore, the image data of all pixels (1280 dots) that make up one line will be 3 × 1280 bytes in length in total.

[0083] As shown in Figure 13, the LCD_CTL liquid crystal controller has 1280 source signal lines, each connected in pairs. 8The source driver SDV, which is driven by a drive signal for 256 grayscale levels, and the gate driver GDV, which controls the ON / OFF state of 1024 gate signal lines, are controlled as appropriate. Specifically, the liquid crystal controller LCD_CTL operates each part appropriately based on the DE signal (data valid signal ENAB) output from the LVDS transmission line and the operating clock CK, thereby achieving a frame rate of 60Hz for image updating.

[0084] Each pixel of the liquid crystal panel (LCD) is composed of basic pixels of the three RGB colors. Since there are 3 × 1280 basic pixels corresponding to all pixels (1280 dots) in one line, the source driver SDV is configured with 10 driver elements, each having 384 output terminals. These 10 driver elements are sequentially supplied with image data DAT from the liquid crystal controller LCD_CTL, which is then transferred as needed based on the start signal SP and the transfer clock DCLK. Synchronized with the latch signal LT, the analog-converted drive signal is supplied to 3840 source signal lines. As explained earlier, the time required to update all pixels (1280 dots) in one line of the liquid crystal panel (LCD) is 11.85 μS (= 640 / 54 MHz).

[0085] Meanwhile, the liquid crystal controller LCD_CTL updates the gate signal line to be driven by supplying the gate start signal GS and the gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is composed of four driver elements, each having 256 output terminals.

[0086] The update timing of the gate signal line is determined based on the falling edge timing of the DE signal and the operating clock CK. The horizontal rewind period of the gate signal line is counted by the operating clock CK and is typically calculated to be 640 + 204 clocks (see Figure 11). Also, based on the number of DE signals (1024), the gate signal line to be driven is reset to its initial state, the gate start signal GS is output at the optimal timing, and the output of the gate clock signal GCLK is resumed. The vertical rewind period of the gate signal line is counted by the operating clock CK and is typically calculated to be 42 + 1024 clocks (see Figure 11). However, as explained earlier, in this embodiment the liquid crystal display means 76 is operated with a design different from the typical value (see Figure 19).

[0087] Next, returning to Figure 10, we will explain the outline of the frame-side member 132. The frame-side member 132 is mainly composed of a power supply board 126 and a payout / launch control board 128. The power supply board 126 receives AC24V and outputs various DC voltages, outputting DC5V, DC12V, and DC35V to the payout / launch control board 128, DC12V to the frame-bottom LED connection board 139, and also outputting DC5V, DC12V, and DC35V to the performance interface board 96 via the power relay board 136. A backup board 147 is connected to the payout / launch control board 128, and from the payout / launch control board 128 to the main control board 93, in addition to the DC5V, DC12V, and DC35V received from the power supply board 126, backup power, power abnormality signals, etc. are output via the main control relay board 135.

[0088] Furthermore, the payout launch control board 128 is connected to the launch drive means 17d that constitute the launch means 17, the external terminal board 148 for outputting various information to an external host computer, etc., the dispensing device connection terminal board 149 for connecting an external game ball dispensing device, as well as the frame relay board 150, the tray relay board 151, and the like.

[0089] The frame relay board 150 relays the connection between the payout motor 32a, payout counting switch 32b, front door / inner frame opening switch 152, etc., located on the inner frame 6 side, and the payout launch control board 128. The tray relay board 151 relays the connection between the launch connection board 153, ball jam detection board 154, frequency display board 155, etc., on the front door 7 side and the payout launch control board 128. The launch connection board 153 is connected to the variable resistor 35a, launch stop switch 35b, touch sensor 35c, which constitute the launch handle 35, as well as the ball feed solenoid 53c provided on the ball feed unit 53a.

[0090] In addition, the lower frame LED connection board 139 is connected to the lower speaker 18 on the inner frame 6 side, as well as the lower left frame LED connection board 156 on the front door 7 side. The lower left frame LED connection board 156 is connected to the LED boards 302a to 302d that make up the frame lamp 304, the handle LED board 158 that is placed on the firing handle 35, the performance button LED connection board 159 to which the performance button 41 and its internal LED boards are connected, the volume / brightness button board 160 to which the volume / brightness adjustment buttons 39, 40 etc. are connected, the upper speaker 25, the side unit relay board 161 that is connected to the side unit 30, etc.

[0091] Next, the circuit configurations of the performance interface board 96, liquid crystal interface board 97, liquid crystal control board 98, and ROM board 99, which constitute the performance control unit 95, will be explained in detail with reference to Figures 10, 14, etc.

[0092] As shown in Figure 10, the performance interface board 96 includes various input / output buffers, an audio processor 101 that reproduces audio signals based on instructions received from the CPU circuit 171 (Figure 14) mounted on the composite chip 104 of the liquid crystal control board 98, an audio ROM 103 that stores compressed audio data, which is the source data of the audio signals to be reproduced, and a digital amplifier 102 that receives the audio signals output from the audio processor 101. The audio processor 101 incorporates a WDT circuit that automatically resets the settings of the internal circuit to their default values ​​in the event of an abnormal operation of the internal circuit, and an audio control register SRG. The audio control register SRG accesses the audio ROM 103 based on the operating parameters received from the CPU circuit 171 of the composite chip 104, reproduces the necessary audio signals, and outputs them to the digital amplifier 102.

[0093] The various input / output buffers mounted on the performance interface board 96 include an input buffer for receiving control commands CMD and strobe signals STB from the main control board 93 and transferring them to the composite chip 104 of the LCD control board 98; an input buffer for receiving switch signals such as performance buttons 41 via the frame LED relay board 137 and transferring them to the composite chip 104 of the LCD control board 98; an output buffer for transferring serial signals received from the LCD control board 98 to driver ICs such as LED boards via the frame LED relay board 137; an input buffer for receiving switch signals such as movable body position detection switches via the LED connection board 134 and transferring them to the composite chip 104 of the LCD control board 98; and an output buffer for transferring serial signals received from the LCD control board 98 to driver ICs such as LED boards via the LED connection board 134.

[0094] The LCD control board 98 also includes a composite chip (chip) 104 that incorporates a CPU circuit 171, a VDP circuit 172, etc., a control ROM (ROM connected to the chip) 105 that stores the control program for the CPU circuit 171, and a DRAM (Dynamic Random Access Memory) 106 that allows high-speed access to large amounts of data. The ROM board 99 connected to the LCD control board 98 is equipped with a CGROM 107 that stores a large amount of CG data necessary for controlling the performance.

[0095] The control ROM 105 is located in address space CS0, which is selected by the chip select signal CS0. The DRAM 106 is located in address space CS5, which is selected by the chip select signal CS5.

[0096] Figure 14 is a circuit block diagram illustrating the composite chip 104 mounted on the liquid crystal control board 98, including related circuit elements. As shown in the figure, the composite chip 104 incorporates a CPU circuit 171 that issues a display list DL at predetermined intervals, and a VDP circuit 172 that generates image data based on the issued display list DL and drives the liquid crystal display means 76. The CPU circuit 171 and the VDP circuit 172 are connected via a CPUIF circuit 173 that relays the transmitted and received data between them.

[0097] The CPU circuit 171 takes the oscillation output (e.g., 100 / 3MHz) from the oscillator OSC1 received at the HCLKI terminal of the composite chip 104 and multiplies its frequency (e.g., by 8) to obtain a CPU operating clock of approximately 266.7MHz. Here, the oscillator OSC1 is configured to output a spread spectrum wave, thus providing EMI (Electromagnetic Interference) protection against radio interference / electromagnetic interference.

[0098] On the other hand, the VDP circuit 172 uses the oscillation output (e.g., 40MHz) from the oscillator OSC2, which is received at the PLLREF terminal of the composite chip 104, after frequency multiplying as needed, as the system clock for the VDP circuit 172, the display clock for the display device (dot clock, etc.), and the DDR clock for the external DRAM 106. In other words, the output of the oscillator OSC2 functions as the reference clock for the entire VDP circuit 172.

[0099] Therefore, considering the importance of this reference clock, the oscillator OSC2 is operated at the same power supply voltage of 3.3V as the VDP circuit 172, and the reference clock is output under the condition that the output enable terminal OE is at a high level (=3.3V). If the power supply voltage of 3.3V drops below a predetermined level, an unmaskable interrupt (NMI) is generated.

[0100] The composite chip 104 is also provided with an HBTSL terminal, and based on the logic level of this HBTSL terminal, it identifies the ROM that stores the boot program (initial setup program) to be executed after power-on (CPU reset). As shown in the figure, in this embodiment, HBTSL is set to L, and address zero of the address space CS0 of the CPU circuit 171 is assigned to the control ROM 105.

[0101] The CPUIF circuit 173 is connected to a control ROM 105 that non-volatilely stores control programs and necessary control data, and a work memory (RAM) 174 with a storage capacity of approximately 2 MB, both of which are accessible from the CPU circuit 171 and the VDP circuit 172, respectively.

[0102] The control ROM 105 is located in address space CS0, which is selected by the chip select signal CS0, and the work memory 174 is located in address space CS6, which is selected by the chip select signal CS6. The work memory 174 has a DL buffer BUF which temporarily stores a display list DL containing a series of instruction commands that identify a frame of the liquid crystal display means 76.

[0103] The CPU circuit 171 is a circuit with performance equivalent to that of a general-purpose single-chip microcontroller, and includes an image processing control CPU 181 that comprehensively controls image processing based on the control program in the control ROM 105, an internal RAM 182 with a memory capacity of about 16kbytes used as the CPU's working area, a DMAC (Direct Memory Access Controller) 183 for enabling data transfer without going through the image processing control CPU 181, a serial input / output port (SIO) 184 with multiple input ports Si and output port So, a parallel input / output port (PIO) 185 with multiple input ports Pi and output port Po, and a control register (REG) 186 where setting values ​​are set to control the operation of each of these parts.

[0104] The parallel input / output port 185 is connected to an external device (performance interface board 96) via the input / output circuit 187, etc., and the performance control CPU 181 receives switch signals such as performance buttons 41, control commands CMD, interrupt signals STB, etc., via the input / output circuit 187.

[0105] Next, the VDP circuit 172 will be described. The VDP circuit 172 is connected to a CGROM 107 that stores compressed data which is a component of still images and videos used in image effects, an external DRAM 106 with a storage capacity of about 4 Gbit, and a liquid crystal display means 76. In this embodiment, the DRAM 106 is composed of DDR3 (Double-Data-Rate3 SDRAM), and the CGROM 107 is composed of a flash SSD (solid state drive) made of NAND flash memory.

[0106] As shown in Figure 14, the VDP circuit 172 includes a group of control registers 201 that allow the performance control CPU 181 to set various operating parameters that define the operation of the VDP (Video Display Processor), a built-in VRAM (video RAM) 202 of about 48 MB used when generating image data to be displayed on the liquid crystal display means 76, a data transfer circuit 203 that performs data transmission and reception between parts inside the chip and data transmission and reception with the outside of the chip, an index table IDXTBL that can identify source and destination address information for the built-in VRAM 202, a preloader 204 that can perform a preload operation that performs a READ access to the CGROM 107 prior to the drawing operation, a graphics decoder (GDEC) 205 that decodes (decodes and decompresses / unpacks) the compressed data read from the CGROM 107, a drawing circuit 206 that generates image data for one frame of the liquid crystal display means 76 by appropriately combining the decoded (unpacked) still image data and video data, and a geometry engine 207 that generates a 3D image by appropriate coordinate transformation as part of the operation of the drawing circuit 206. The system includes a display circuit 208A to 208C with multiple systems, for example, three systems (A / B / C), that can read image data from the frame buffer FBa generated by the drawing circuit 206 and perform appropriate image processing in parallel; an output selection unit 209 that appropriately selects the output of the three systems (A / B / C) of display circuits 208A to 208C; an LVDS unit 210 that converts the image data output by the output selection unit 209 into an LVDS signal; an SMC unit 211 that can send and receive serial data; a CPUIF unit 212 that relays data transmission and reception with the CPUIF circuit 173; a CG bus IF unit 213 that relays data reception from the CGROM 107; a DRAMIF unit 214 that relays data transmission and reception with the external DRAM 106; a VRAMIF unit 215 that relays data transmission and reception with the built-in VRAM 202; and an audio circuit SND.

[0107] Figure 15 illustrates the relationship between the CPUIF unit 212, CG bus IF unit 213, DRAMIF unit 214, and VRAMIF unit 215, and the control register group 201, CGROM 107, DRAM 106, and built-in VRAM 202. As shown in the figure, CG data acquired from CGROM 107 is transferred, for example, as preload data to the preload area of ​​the external DRAM 106 via the data transfer circuit 203 and DRAMIF unit 214. Note that this preload operation is not mandatory, and the data transfer destination is not limited to the external DRAM 106, but may also be the built-in VRAM 202. For example, if the preload operation is not performed, the CG data is transferred to the built-in VRAM 202 via the data transfer circuit 203 and VRAMIF unit 215.

[0108] Incidentally, the built-in VRAM 202 requires an area for decompressing compressed data read from CGROM 107, a frame buffer area for storing image data that identifies each ARGB information (32 bits = 8 × 4) for the W × H display pixels of the display device, and a Z buffer area for storing depth information for each display pixel. In ARGB information, A represents 8-bit alpha plane data, and RGB represents 8-bit data for the three primary colors.

[0109] Here, the aforementioned areas of the built-in VRAM 202 are accessed indirectly by the performance control CPU 181 based on various instruction commands (textures, sprites, etc.) described in the display list DL. However, it would be cumbersome to specify the destination address and source address of the built-in VRAM 202 each time for READ / WRITE access. Therefore, in this embodiment, during the initial processing after a CPU reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as the index space) necessary for drawing operations is secured, and an index number is assigned to each index space, thereby enabling access based on the index number.

[0110] Specifically, after a CPU reset, the built-in VRAM 202 is divided into three main memory areas, and the necessary number of index spaces are allocated in each memory area. Then, an index table IDXTBL (see Figure 16(a)) is constructed that stores the index spaces and index numbers in association, thereby enabling subsequent operations based on the index numbers.

[0111] This index space needs to be (1) added to after initial processing, and conversely, (2) released. Therefore, a flag area FG is provided in the index table IDXTBL that can determine whether it is possible to perform the addition / release process when the CPU 181 controls the addition / release process, and whether the addition / release process has actually been completed. The built-in VRAM 202 is broadly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an arbitrary area (c), and the index table IDXTBL is divided into three sections corresponding to these three types of memory areas (a1, a2), (b), and (c) (Figure 16(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are allocated as the AAC area (a), but it is not limited to this, and either one alone may be used. In the following explanation, the first and second AAC regions (a1, a2) may be collectively referred to as AAC region (a).

[0112] In this embodiment, the built-in VRAM 202 is configured to be divided into (a) an AAC area in which an index space and its index number are automatically assigned by internal processing and which has a memory cache function, (b) a page area in which an index space can be allocated in a range of integer multiples thereof, with a two-dimensional space of, for example, 4096 bits × 128 lines as the unit space, and (c) an arbitrary area in which the starting address (space starting address) STx and horizontal size Hx can be arbitrarily set (see Figure 16(b)). However, in order to facilitate the internal operation of the VDP circuit 172, the space starting address STx of the index space arbitrarily set in the arbitrary area (c) must have its lower 11 bits set to 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

[0113] After the CPU reset, the maximum required address space for each region and the starting address of the region (lower 11 bits = 0) are defined, and the AAC region (a1), the second AAC region (a2), and the page region (b) are allocated, with the remaining memory region becoming the arbitrary region (c). To facilitate the internal operation of the VDP circuit 172, the maximum value of the address space for the AAC region is defined in units of 2048 bits, and the maximum value of the address space for the page region is set to an integer multiple of the aforementioned 4096-bit × 128-line unit space.

[0114] Next, the required number of index spaces are set in each of the allocated regions (a1, a2), (b), and (c). Note that when using the arbitrary region (c), in order to facilitate the internal operation of the VDP circuit 172, the horizontal size Hx of the index space handling two-dimensional data can be arbitrarily set as a multiple of 256 bits, while its vertical size is fixed (e.g., 2048 lines).

[0115] In any case, the first and second AAC regions (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 172. For example, if the decoding destination is specified as the AAC region (a) using the SETINDEX command of the texture setting commands, then the TXLOAD (texture load) command, which reads CG data from the CGROM 107, only needs to specify the source address of the CGROM 107 and the horizontal and vertical sizes after decompression (decoding). Therefore, in this embodiment, the decoding destination for still images (textures) of characters and other elements that appear temporarily during preview sequences, etc., is set to the AAC region (a).

[0116] Since each of these AAC areas (a) is equipped with a memory cache function, for example, when the same texture from CGROM107 is read into the AAC area (a) multiple times, the decoded data cached in the AAC area (a) can be used from the second time onward, suppressing unnecessary READ access and decoding processes. However, when the AAC area (a) is exhausted, the old data is automatically destroyed, so in this embodiment, when using the AAC area (a), the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are acquired in the second AAC area (a2).

[0117] Examples of textures that are used repeatedly include characters that appear repeatedly during a specific preview sequence, or background images when constructing a background screen using still images. In such cases, the SETINDEX command of the texture setting commands is used to set the decoding destination to the second AAC area (a2), and after decoding textures such as characters and background images into the second AAC area (a2) using the TXLOAD command, the decoding result is protected by not using the second AAC area (a2).

[0118] Then, by specifying the decoding destination as the second AAC area (a2) using the SETINDEX command and executing the same TXLOAD command to reacquire the already acquired texture, the acquired texture will be cache-hit, thus eliminating the time required for READ access to CGROM107 and decoding. This cache-hit function is also effective for preloaded data that has been pre-fetched into the preload area, but the significance lies in the fact that the preloaded data that is cache-hit in the preload area is compressed data before decoding, whereas the cache-hit in the AAC area is decompressed data after decoding.

[0119] Incidentally, while texture generally refers to the feel or texture of an object's surface, in this embodiment, it is used as a concept that includes not only sprite image data that makes up a still image, image data that makes up a single frame of a video, and image data that is applied to drawing primitives such as triangles and rectangles, but also decoded image data. When copying image data within the built-in VRAM202 (hereinafter referred to as "moving" for convenience), the source image data is set as a texture using the SETINDEX command of the texture setting system, and then the SPRITE command is executed.

[0120] When the SPRITE command is executed, the source image data is formally drawn to the virtual rendering space shown in Figure 16(c). However, if the correspondence between the rendering area in the virtual rendering space that is actually drawn to the display device and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then, for example, when the SPRITE command is used to draw to the virtual rendering space, the source image data will be drawn to the predetermined index space (frame buffer) (see Figure 16(c)).

[0121] In any case, in this embodiment, the built-in VRAM 202 is broadly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be allocated to each, and each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte in length, and for the page area (b) and the arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuit), the performance control CPU 181 can freely assign index numbers in the range of 0 to 255.

[0122] Therefore, in this embodiment, as shown in Figure 16(a), a pair of frame buffers FBa are secured in an arbitrary region (c) for the liquid crystal display means 76, and index numbers 255 and 254 are assigned to both sides of the double buffer structure. That is, index spaces 255 and 254 are secured as frame buffers FBa for the liquid crystal display means 76, which are used by toggling them. Although not particularly limited, these index spaces 255 and 254 have a horizontal size of 1280, corresponding to the number of horizontal pixels of the liquid crystal display means 76. Since each pixel is identified by 32 bits of ARGB information, a horizontal size of 1280 means 32 × 1280 = 40960 bits (a multiple of 256 bits).

[0123] The reason for allocating the frame buffer FBa in the arbitrary area (c) is that the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (=256 bits = 8 pixels), and by matching it to the number of horizontal pixels of the liquid crystal display means 76 as described above, no wasted space is created in the allocated area. On the other hand, the page area (b) can only be set to horizontal / vertical sizes that are integer multiples of a unit space of 128 pixels × 128 lines. However, the vertical size of the two-dimensional index space allocated in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area with a horizontal size of 1280 × a vertical size of 1024 becomes the effective data area for the liquid crystal display means 76.

[0124] Furthermore, in this embodiment, when an additional index space (memory area) is allocated in the arbitrary area (c) where the frame buffer FBa is allocated, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, an index space (0) is allocated in the arbitrary area (c) as a work area for a preview effect that makes a performance image composed of characters or other still images appear on a part of the display screen in an appropriate rotational position as needed.

[0125] However, the use of the work area is not mandatory, and instead of the arbitrary area (c), an index space may be allocated in the page area (b) to serve as the work area. Using the page area (b) allows for the allocation of an index space with dimensions that are multiples of a square unit space with a horizontal size of 128 (=4096 bits) x a vertical size of 128, making it suitable for handling small animation images.

[0126] In this embodiment, image effects, including background images, are implemented almost entirely using video. In particular, during variable effect animations, a large number of videos (usually 10 or more) are rendered simultaneously. These videos are all stored in the CGROM 107 in a compressed state as a series of video frames, but they are divided into I-stream videos, which consist only of I-frames, and IP-stream videos, which consist of I-frames and P-frames. Here, an I-frame (Intra coded frame) refers to a frame that compresses the input image as is, independently of other screens. On the other hand, a P-frame (Predictive coded frame) refers to a frame that performs forward predictive coding, and requires an I-frame or P-frame located in the past in time.

[0127] Therefore, in this embodiment, IP stream video is expanded into the page area (b) rather than the AAC area (a), where there is a concern about the corruption of old data. That is, a number of index spaces (IDX0 to IDXN) are secured in the page area (b), which is capable of securing an index space with dimensions that are multiples of horizontal size 128 × vertical size 128, and a series of video frames are decoded using the same index space IDXi corresponding to each video MVi. In other words, video MV1 is expanded into index space IDX1, video MV2 is expanded into index space IDX2, and so on, with video MVi being expanded into index space IDXi.

[0128] To explain video MVi in more detail, the SETINDEX command pre-specifies that "the decoding destination for IP stream video MVi is the index space (i) of index number i in the page area (b)," and then the TXLOAD command is executed to obtain one frame of the IP stream video MVi.

[0129] Then, the video frame (any of a series of video frames) on CGROM107 identified by the TXLOAD command is first acquired in the AAC area (a), and then the acquired video frame is decoded and expanded in the index space (i) of the page area (b) by the graphics decoder (GDEC) 205, which is automatically activated.

[0130] On the other hand, in this embodiment, I-stream videos are treated the same as still images, and the SETINDEX command is used to specify that "the decoding destination for I-stream video MVj is the first AAC area (a1)," and the TXLOAD command is executed. As a result, the video frames are acquired in the first AAC area (a1), and then the graphics decoder 205, which is automatically started, expands the decoded data into the first AAC area (a1). As explained earlier, the index space of the AAC area (a) is automatically generated, so it is not necessary to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal and vertical sizes of the decoded texture (video frame), is determined by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b).

[0131] Incidentally, IP stream video MVi and I stream video MVj generally consist of N video frames (I-frames and P-frames). Therefore, the TXLOAD command specifies, for example, the Source address of CGROM107 where the k-th (1≦k≦N) video frame is stored, and the horizontal and vertical sizes after expansion. Although not limited in any way, in this embodiment where still images are hardly used, most of the 48MB address space of the built-in VRAM202 (about 30MB) is allocated to the page area (b). Furthermore, in this embodiment where still images are hardly used, only the first AAC area (a1) is reserved as the AAC area, the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

[0132] Furthermore, to speed up the decoding process of compressed video data, it is conceivable to provide a dedicated GDEC (graphics decoder) circuit. If the dedicated GDEC circuit is built into the VDP circuit 172, then in the decoding process of compressed video data consisting of N compressed video frames, it will be sufficient to instruct the GDEC circuit with the starting address of the compressed video data, eliminating the need to specify the starting address for each of the N compressed video frames.

[0133] However, incorporating multiple dedicated GDEC circuits for each compression algorithm would further complicate the internal configuration of the VDP circuit 172. Therefore, in this embodiment, software GDEC is used, and decoding of IP stream video, I stream video, still images, and other data such as alpha values ​​is achieved through software processing corresponding to each compression algorithm. The difference in processing time between hardware processing and software processing is not a significant issue; the processing time that matters is primarily the access (READ) time from CGROM 107.

[0134] Let's return to Figure 14 and continue the explanation. The data transfer circuit 203 is a circuit that performs DMA (Direct Memory Access) data transfer operations between the resources (storage medium) inside the VDP circuit and the external storage medium, using the source port and destination port as the transfer source port and destination port, respectively. Figure 17 is a block diagram showing the internal configuration of this data transfer circuit 203 along with the related circuit configurations.

[0135] As shown in Figure 17, the data transfer circuit 203 is configured to send and receive data to and from the CGROM 107, DRAM 106, and built-in VRAM 202 via the integrated connection bus ICM, which has router functionality. The CGROM 107 and DRAM 106 are accessed via the CG bus IF section 213 and the DMAMIF section 214.

[0136] Meanwhile, the CPU circuit 171 issues a display list DL to the drawing circuit 206 and the preloader 204 via the transfer port register TR_PORT built into the data transfer circuit 203. Although the CPU circuit 171 and the data transfer circuit 203 are connected bidirectionally, when issuing the display list DL, the transfer port register TR_PORT functions as a data writing port that accepts one unit of data that constitutes the display list DL. The write unit (data length of one unit) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 203d.

[0137] As shown in the diagram, the performance control CPU 181 can access the transfer port register TR_PORT via the CPUIF unit 212, while when the DMAC circuit 183 is used, the DMAC circuit 183 directly accesses the transfer port register TR_PORT. The series of instruction commands written to the transfer port register TR_PORT (i.e., the sequence of instruction commands that make up the display list DL) are configured to be automatically stored in 32-bit units in the CPU bus control unit 203d, which has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

[0138] Furthermore, this data transfer circuit 203 performs data transmission and reception operations on a 3-channel ChA to ChC transmission path, and has a ChA control circuit 203a (N=130 stages) with a FIFO buffer (64 bits × N stages), a ChB control circuit 203b (N=1026 stages), and a ChC control circuit 203c (N=130 stages).

[0139] The instruction command sequence (display list DL) stored in the CPU bus control unit 203d is then transferred to the drawing circuit 206 or preloader 204 based on the setting value in the data transfer register RGij (a type of various control register 201) by the performance control CPU 181. As indicated by the arrows, the display list DL is configured to be transferred from the CPU bus control unit 203d to the drawing circuit 206 via the FIFO buffer of the ChB control circuit 203b, and then to the preloader 204 via the FIFO buffer of the ChC control circuit 203c.

[0140] In this embodiment, the ChB control circuit 203b and the ChC control circuit 203c are specialized for the transfer operation of the display list DL. The data stored in the FIFO buffer of the CPU bus control unit 203d is transferred as part of the display list DL to the drawing circuit 206 or the display list analyzer of the preloader 204 via the FIFO buffer of either the ChB control circuit 203b or the ChC control circuit 203c.

[0141] Then, the drawing circuit 206 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 204 performs the necessary preload operations based on the transferred display list DL. Through the preload operations, the CG data from the CGROM 107 is pre-read into the preload area allocated in the DRAM 106, and a display list DL with the texture source address changed (hereinafter referred to as the rewritten list DL') with respect to the TXLOAD command, etc., is saved in the DL buffer area BUF' allocated in the DRAM 106.

[0142] On the other hand, the ChA control circuit 203a and the connection bus access arbitration circuit 203e function for data transfer between storage media such as CGROM107, DRAM106, and built-in VRAM202. In addition, the IDXTBL access arbitration circuit 203f functions when accessing the built-in VRAM202, which requires address information from the index table IDXTBL. Specifically, the ChA control circuit 203a functions, for example, when (a) transferring compressed data from CGROM107 to the built-in VRAM202, (b) preloading (reading ahead) compressed data from CGROM107 and transferring it to the external DRAM106, or (c) transferring pre-read data from the preloaded area to the built-in VRAM202.

[0143] Here, the ChA control circuit 203a is configured to operate in parallel with the ChB control circuit 203b and the ChC control circuit 203c, and the operations (a) to (c) described above can be executed in parallel with the issuance of the display list DL and the transfer of the rewrite list DL'. Furthermore, the ChB control circuit 203b and the ChC control circuit 203c can also be executed simultaneously. However, since there is only one transfer port register TR_PORT, when either one (203b / 203c) is using the transfer port register TR_PORT, the other (203c / 203b) cannot access the transfer port register TR_PORT.

[0144] When the ChA control circuit 203a is operating, the connection bus access arbitration circuit 203e arbitrates data transmission with each memory element (CGROM 107, DRAM 106) via the integrated connection bus ICM. Meanwhile, the IDXTBL access arbitration circuit 203f arbitrates data communication with the built-in VRAM 202 by controlling the ChA control circuit 203a based on the index table IDXTBL. In this embodiment, where the preloader 204 is functioning, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 106 is transferred to the drawing circuit 206 via the connection bus access arbitration circuit 203e and the ChB control circuit 203b.

[0145] As described above, the data transfer circuit 203 of this embodiment achieves high-speed data transfer between a data source arbitrarily selected from various memory resources and a data destination arbitrarily selected from various memory resources. The memory resources on which the data transfer circuit 203 functions include not only the built-in VRAM 202 but also external devices accessed via the CPUIF unit 212, CG bus IF unit 213, and DRAMIF unit 214.

[0146] Furthermore, the amount of data to be acquired from CGROM107 in one go (memory sequential READ) is enormous when the ChA control circuit 203a is operating with an external device, compared to the case of display list DL when the ChB control circuit 203b or ChC control circuit 203c is operating, and the amount of data to be acquired differs greatly from that of the other.

[0147] Here, it is conceivable to configure the unit data amount and total data transfer amount for these various data transfers to be finely configurable, but this would complicate the control operations within the VDP and hinder smooth transfer operation. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total data transfer amount is limited to an integer multiple of the minimum data amount DTmin, thereby achieving high-speed and smooth data transfer operation. Although not particularly limited, in the data transfer circuit 203 of this embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total data transfer amount is limited to an integer multiple of this.

[0148] Therefore, the instruction command sequence of the display list DL, which is accumulated in the FIFO buffer of the CPU bus control unit 203d every 32 bits, is transferred to the ChB control circuit 203b and the ChC control circuit 203b when its total amount reaches the minimum data amount Dmin, and is accumulated in their respective FIFO buffers.

[0149] The display list DL consists of a series of instruction commands, but in this embodiment, corresponding to the write unit (32 bits) of the transfer port register TR_PORT, the display list DL consists only of instruction commands with a command length that is a multiple of a 32-bit integer N (N>0). Therefore, the drawing circuit 206 and preloader 204, which receive the instruction commands of the display list DL via the data transfer circuit 203, can quickly and smoothly start command analysis processing (DL analyze). Note that the command length of a multiple of a 32-bit integer N does not necessarily mean that all of them are significant bits; it means that the command length is a multiple of a 32-bit integer including unimportant bits (Don't care bits).

[0150] Next, the preloader 204 will be explained. The preloader 204 is a circuit that interprets the display list DL transferred from the data transfer circuit 203 (ChC control circuit 203b) and transfers the CG data on the CGROM 107 referenced by the TXLOAD command to the preload area of ​​the DRAM 106 in advance. The preloader 204 also stores a rewrite list DL' in the DL buffer BUF' of the DRAM 106, in which the reference destination of the CG data for this TXLOAD command has been rewritten to the address after the transfer. Note that the DL buffer BUF' and the preload area are allocated in advance during the initial processing after the CPU reset.

[0151] The rewrite list DL' is then transferred to the display list analyzer (DL Analyzer) of the drawing circuit 206 via the connection bus access arbitration circuit 203e and ChB control circuit 203b of the data transfer circuit 203 when the drawing operation of the drawing circuit 206 begins. The drawing circuit 206 then performs the drawing operation based on the rewrite list DL'. Therefore, CG data that should originally be obtained from the CGROM 107 based on a TCLOAD command, etc., is obtained from the preload area of ​​the DRAM 106 as preloaded data that has been pre-read into the preload area. In this case, the preloaded data can be reused repeatedly unless it is overwritten and erased, and preloaded data that has been cached in the preload area is reused repeatedly.

[0152] In this embodiment, since the preload area is set in the external DRAM 106 which has sufficient memory capacity, the cache hit function described above functions effectively. Furthermore, because the external DRAM 106 has a large memory capacity, it is possible to perform multiple preloads, for example, by preloading CG data for multiple frames at once. That is, regarding the operation period of the preloader 204, multiple preloads are realized by appropriately setting the operation period of a series of preload operations, including the pre-reading operation of CG data, within the range of an integer multiple of the operation period δ during the intermittent operation of the VDP circuit 172.

[0153] However, for convenience, the following description will explain a configuration without multiple preloads, so the preloader 204 in this embodiment will complete the preload operation for one frame during one operating cycle (δ). In this embodiment, the operating cycle δ of the VDP circuit 172 during intermittent operation is 1 / 30 second, which is twice the period of the vertical synchronization signal of the liquid crystal display means 76.

[0154] Next, the drawing circuit 206 sequentially analyzes the instruction command sequences of the display list DL and rewrite list DL' transferred via the data transfer circuit 203, and works in cooperation with the graphics decoder 205, geometry engine 207, etc., to draw an image for one frame of the liquid crystal display means 76 onto the frame buffer formed in the VRAM 202.

[0155] As described above, when the preloader 204 is activated, the CG data referenced in the rewrite list DL' is located in the preload area set in DRAM 106, not CGROM 107. Therefore, sequential access to CG data that occurs during drawing by the drawing circuit 206 can be performed quickly, and even high-resolution videos with rapid movement can be drawn without problems. In other words, according to this embodiment, complex and advanced image effects can be performed while utilizing an inexpensive SATA module as CGROM 107.

[0156] Incidentally, regardless of whether the preloader 204 is activated or not, even if data corruption occurs during the transfer of the display list DL or the rewrite list DL', the drawing circuit 206 cannot detect it. Also, due to the influence of noise or other factors, the drawing circuit 206 may freeze, and the READ / WRITE access to the built-in VRAM 202 may abnormally stop. Therefore, in this embodiment, the drawing circuit 206 is configured to generate a drawing abnormal interrupt if it detects an unreasonable instruction command (a bit sequence that cannot be analyzed) or if there has been no READ / WRITE access to the built-in VRAM 202 for a certain period of time (drawing abnormal interrupt is enabled).

[0157] Next, as explained with respect to Figure 16, the frame buffer FB allocated in the arbitrary area (c) of the VRAM 202 is a double buffer divided into a drawing area and a reading area, and the two areas are used alternately, switching their purpose. In this embodiment, since one liquid crystal display means 76 is connected, one frame buffer FBa is allocated as shown in Figure 16. Therefore, the drawing circuit 206 draws image data for one frame into the drawing area (writing area) of the frame buffer FBa for the liquid crystal display means 76.

[0158] Display circuits 208A to 208C read image data from frame buffers FBa to FBc, perform final image processing, and then output the image (see Figure 18). Final image processing includes, for example, scaling processing by a scaler to enlarge / reduce the image, subtle color correction processing, and dithering processing to minimize the quantization error of the entire image. The digital RGB signal (24 bits in total) that has undergone these image processing steps is then output along with the horizontal sync signal HS and the vertical sync signal VS, etc.

[0159] As shown in Figure 18, in this embodiment, three display circuits A / B / C are provided to perform the above operations in parallel. Each display circuit 208A to 208C reads image data from its corresponding frame buffers FBa / FBb / FBc and performs the final image processing described above. However, in this embodiment, there is only one display device, so frame buffers FBb and FBc are not allocated, and display circuits 208B and 208C do not function.

[0160] Here, examining the specifications of the liquid crystal display means 76, it is necessary for the liquid crystal display means 76 to receive adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) in the left-right direction through separate LVDS (Low Voltage Differential Signaling) transmission paths at the receiving unit RV (RVa, RVb). Furthermore, the frequency of the dot clock DCK of the liquid crystal display means 76 needs to be around 40-70MHz (typical value is 54MHz), and the horizontal / vertical waiting times WTh / WTv need to be set so that (WTh+640)×(WTv+1024) / 54MHz ≈ 1 / 60 seconds. In addition, at the timing of outputting image data (ODD / EVEN signals) to the liquid crystal display means 76, it is necessary to output an active-level data validity signal ENAB.

[0161] Therefore, the display circuit 208A needs to output a signal that satisfies all of the above specifications. Figures 19(a) to 19(e) illustrate the various signals output from the display circuit 208A. First, it is necessary to determine the frequency of the dot clock DCK. In this embodiment, the liquid crystal display means 76 is operated with an operating clock CK of a typical value of 54 MHz, so correspondingly, the design dot clock DCK in the VDP circuit 172 is set to 108 MHz (= 54 × 2).

[0162] This is because, in an LCD display panel with 1280 horizontal dots and 1024 vertical lines (see Figure 19(f)), two adjacent pixels are processed simultaneously in synchronization with the 54MHz operating clock CK, which is essentially equivalent to operating with a 108MHz dot clock DCK.

[0163] Then, various operation parameters that define the operation of the display circuit 208A are defined based on the dot clock DCK with a frequency of 108 MHz. First, it is necessary to set the horizontal / vertical waiting times WTh / WTv such that (WTh+640)×(WTv+1024) / 54 MHz ≈ 1 / 60 seconds, and the operation parameters WTh / WTv for the display circuit 208A need to satisfy (WTh+1280)×(WTv+1024) / 108 MHz ≈ 1 / 60 seconds.

[0164] Further, regarding the horizontal / vertical waiting times WTh / WTv, it is also necessary to consider the allowable range in the specifications of the liquid crystal display means 76. Therefore, in the present embodiment, the horizontal waiting time WTh is set to 382 clocks when counted with the 108 MHz dot clock DCK, and the vertical waiting time WTv is set to 59 lines. Accordingly, the time required for image update of one frame is (382+1280)×(59+1024) / 108 MHz = 16.666 mS, and the frame rate is 1 / 60 seconds.

[0165] Corresponding to this setting, the data valid signal ENAB is at L level during the waiting time WTh (=382 / 108 MHz) corresponding to 382 clocks in the image update operation of each line, and thereafter, goes to active (H) level during the active interval (=1280 / 108 MHz) corresponding to 1280 clocks (Figure 19(c)). As shown in Figures 19(d) and (e), in the active interval of the data valid signal ENAB, image data is output such that the image update operation is completed for pixels of 1280 dots per line within a predetermined time (11.85 μS = 1280 / 108 MHz). That is, 1280 pieces of pixel data (Pixel Data) are output in synchronization with 1280 dot clocks DCK. The liquid crystal display means 76 has a gradation level of 2 8 ×2 8 ×2 8 full-color image displayed, so the pixel data for one pixel has a length of 3×8 bits.

[0166] In this embodiment, although not required by the liquid crystal display means 76, it outputs a vertical synchronization signal VS and a horizontal synchronization signal HS. The vertical synchronization signal VS is output within the vertical standby time WTv, and the horizontal synchronization signal HS is output within the horizontal standby time WTh. For ease of understanding, Figures 19(a) and (b) show the respective operating cycles. In Figure 19(f), circles are shown at the top left and bottom right corners of a rectangular frame specified by TH×TV (=1083×1662 clock), labeled "Start of display operation" and "End of display operation," respectively. These circles represent the "V-blank start," which begins every 1 / 60 second. Since the 1083×1662 clock that defines the display operation coincides with 1 / 60 second, the elapsed time from "Start of display operation" to "End of display operation" is 1 / 60 second.

[0167] Returning to Figure 18 and continuing the explanation, the output selection unit 209 in this embodiment divides the output signal of the display circuit 208A into dual links that divide the 108MHz dot clock DCK by two, and transmits them to the LVDS units 210a and 210b respectively (see Figures 18 and 13). Then, each LVDS unit 210a and 210b converts the image data (a total of 24 bits of digital RGB signals) into first and second LVDS signals, adds a pair that transmits a clock signal (54MHz = 108 / 2) to these, and outputs a total of five pairs of differential signals LVDS1 and LVDS2 to the liquid crystal display means 76 via two paths (see Figures 18 and 12).

[0168] As explained earlier, in the liquid crystal display means 76, the ODD signal for one pixel and the EVEN signal for an adjacent pixel are processed at the same timing, so the effective frequency of the dot clock DCK matches the 108MHz dot clock DCK output by the display circuit 208A.

[0169] In this embodiment, the display circuits 208A to 208C are provided with underrun counters URCNTa to URCNTc, which count underrun anomalies where the generation of display data did not keep up with the display timing (see Figure 18). The counter values ​​of these underrun counters URCNTa to URCNTc are configured to be automatically incremented for each VBLANK when an underrun anomaly occurs.

[0170] Next, the SMC (Serial Management Controller) unit 211 is a composite controller that incorporates both an LED controller and a motor controller. It outputs LED drive signals and motor drive signals to an LED / Motor driver (a driver IC with a built-in shift register) mounted on an external board, synchronized with the clock signal, while also being configured to output latch pulses at appropriate timings.

[0171] Regarding the internal circuitry and operation of the VDP circuit 172 described above, the operations that the internal circuitry should perform are defined by the operation parameters (setting values) that the performance control CPU 181 sets in the control register group 201, and the execution state of the VDP circuit 172 can be determined by reading the operation status value of the control register group 201. The control register group 201 refers to a number of VDP registers RGij mapped to an address space of about 1 MB (0 to FFFFFH) on the memory map of the performance control CPU 181, and the performance control CPU 181 of the CPU circuit 171 performs WRITE (setting) operations of operation parameters and READ operations of operation status values ​​via the CPUIF unit 212 (see Figure 15).

[0172] The control register group 201 (VDP register RGij) includes, as shown in Figure 15, a "system control register" where initial settings related to system operations such as interrupt operation are written; an "index table register" for determining the AAC area (a) and page area (b) in the built-in VRAM 202 and constructing or modifying the index table IDXTBL; a "data transfer register" where settings related to data transfer processing by the data transfer circuit 203 between the performance control CPU 181 and the internal circuit of the VDP circuit 172 are written; and the execution status of the graphics decoder 205. It includes a "GDEC register" to identify the device, a "drawing register" where instruction commands and settings related to the drawing circuit 206 are written, a "preloader register" where settings related to the operation of the preloader 204 are written, a "display register" where settings related to the operation of the display circuit 208 are written, an "LED control register" where settings related to the LED controller (SMC unit 211) are written, a "motor control register" where settings related to the motor controller (SMC unit 211) are written, and a "voice control register SRG" where settings related to the voice circuit SND are written. However, in this embodiment, the voice circuit SND is not utilized.

[0173] In any case, the performance control CPU 181 controls the internal operation of the VDP circuit 172 by writing appropriate setting values ​​to a predetermined VDP register RGij. Specifically, the performance control CPU 181 realizes predetermined image effects based on the display list DL, which is updated at appropriate time intervals, and the setting values ​​to the predetermined VDP register RGij. In this embodiment, the performance control CPU 181 is also responsible for lamp effects and motor effects, so the VDP register RGij also includes the LED control register and the motor control register.

[0174] Next, we will explain the details of the LCD control board 98 and the LCD interface board 97, which constitute the performance control unit 95, including their wiring patterns. First, we will explain the LCD control board 98.

[0175] The liquid crystal control board 98 has a total of six wiring layers, specifically a first wiring layer La1 on the front (first surface) 98a side, a sixth wiring layer La6 on the back (second surface) 98b side, and second to fifth wiring layers La2 to La5 arranged between them, totaling six first to sixth wiring layers La1 to La6 (Figures 20 to 25). The second wiring layer La2 (Figure 21) is a solid wiring layer connected to ground, and the fifth wiring layer La5 (Figure 24) is a solid wiring layer connected to the power supply. In addition, the liquid crystal control board 98 has a large number of vias (interlayer conductive portions) provided in the thickness direction of the board, and the multiple wiring layers La1 to La6 are electrically connected to each other through these vias (interlayer conductive portions). The vias used in this embodiment are through-hole type vias with plating applied to the through-holes, and they penetrate from the front surface (first surface) 98a to the back surface (second surface) 98b of the substrate body 190.

[0176] In the following explanation, the in-plane direction and orientation of each wiring layer La1 to La6 will be as shown in the coordinate system in Figures 20 to 25. In these figures, the left-right direction will be the X direction, and the up-down direction will be the Y direction. Rightward / leftward directions will be expressed as +X / -X directions (sides), and upward / downward directions will be expressed as +Y / -Y directions (sides), respectively. Diagonal directions will also be expressed as diagonal +XY directions and diagonal -XY directions. As is clear from Figures 7 and 8, when the liquid crystal control board 98 is attached to the gaming machine body 1, the +X direction of the liquid crystal control board 98 is upward, and the +Y direction is to the right toward the gaming machine body 1 (leftward when viewed from the rear).

[0177] As shown in Figure 20, the first wiring layer (Wave A wiring layer) La1 on the surface 98a side is provided with a composite chip placement area (first placement area) 191 where the composite chip (first electronic component) 104 is placed, and a control ROM placement area (second placement area) 192 where the control ROM (second electronic component, specific electronic component) 105 is placed. The composite chip placement area 191 is approximately square in shape corresponding to the shape of the composite chip 104 and is located near the center of the surface 98a of the liquid crystal control substrate 98. Within the composite chip placement area 191, dot-shaped terminal connection parts corresponding to each terminal of the composite chip 104 are arranged in a matrix at approximately equal intervals. The composite chip 104 has a total of 1020 terminals arranged in 32 rows and 32 columns (except for the four at the four corners) on its bottom side, and each of these terminals is connected to the corresponding terminal connection part before being mounted in the composite chip placement area 191.

[0178] The control ROM placement area 192 is a roughly rectangular shape that is elongated in the Y direction, corresponding to the shape of the ROM socket 193 (see Figure 8) in which the control ROM 105 is mounted, and the length of its longest side is approximately the same as the length of one side of the composite chip placement area 191. The control ROM placement area 192 is located near the composite chip placement area 191 on the +X side, and the first edge 192a of the first and second edges 192a and 192b, which are the longest sides on the -X and +X sides of the control ROM placement area 192, faces the first edge 191a of the first to fourth edges 191a to 191d on the +X, -Y, -X, and +Y sides of the composite chip placement area 191, at a predetermined distance with an offset in the -Y direction.

[0179] The control ROM placement area 192 has multiple terminal connection points (ROM terminal connection points) arranged along both of its long sides, i.e., the first and second edges 192a and 192b, respectively (35 on each side). A ROM socket 193 is fixed to the control ROM placement area 192, which detachably supports the control ROM 105, and the control ROM 105 is detachably mounted in the ROM socket 193 (Figure 8). The control ROM 105 has multiple terminals arranged along both ends (35 on each side), and each of these terminals is connected to the respective terminal connection points in the control ROM placement area 192 via the ROM socket 193.

[0180] As shown in Figure 8, the ROM socket 193 comprises a roughly rectangular bottom wall 193a corresponding to the control ROM placement area 192, and a pair of ROM holding parts 193b that detachably hold both edges of the control ROM 105 mounted on the bottom wall 193a. The bottom wall 193a is fixed to the surface 98a of the liquid crystal control substrate 98 so as to cover substantially the entire control ROM placement area 192. Therefore, the wiring patterns (vias, etc.) within the control ROM placement area 192 in the first wiring layer La1 are shielded by the bottom wall (shielding wall) 193a of the ROM socket 193, even when the control ROM 105 is removed from the ROM socket 193, and cannot be seen from the outside. This makes it possible to enhance the preventative effect against cheating, such as illegally modifying the wiring patterns connecting the composite chip 104 and the control ROM 105. In addition, by drawing the wiring patterns within the control ROM placement area 192, it is possible to secure wiring space in other areas.

[0181] As shown in Figure 25, the sixth wiring layer (second wiring layer) La6 on the back surface 98b is provided with a first connector placement area 194 where the first liquid crystal control connector CN31 is located, and a second connector placement area 195 where the second liquid crystal control connector CN32 is located. The first connector placement area 194 is a roughly rectangular shape that is long in the X direction and is located near the +Y side edge of the back surface 98b of the liquid crystal control substrate 98. Within the first connector placement area 194, multiple terminal connection parts corresponding to each terminal of the first liquid crystal control connector CN31 are arranged along each of the two long sides (70 in this case). The second connector placement area 195 is a roughly rectangular shape that is long in the X direction and is located near the -Y side edge of the back surface 98b of the liquid crystal control substrate 98. Within the second connector placement area 195, multiple terminal connection parts corresponding to each terminal of the second liquid crystal control connector CN32 are arranged along each of the two long sides (50 in this case).

[0182] Of all the terminals of the composite chip 104, those connected to the control ROM 105 are concentrated near the first edge 191a on the control ROM 105 side of the composite chip placement area 191. Figure 26 shows the type (terminal information) of some of the terminals near the first edge 191a and the second edge 192b of the composite chip 104. Note that the arrangement of each terminal in Figure 26 matches the arrangement of the terminal connections in the composite chip placement area 191 in Figure 20.

[0183] In Figure 26(a), HAD0 to HAD25 are address output terminals for outputting address information, HDT0 to HDT15 are data input / output terminals for inputting and outputting data information, HCS0 is a chip select output terminal for outputting a chip select signal, HRD is a read strobe output terminal for outputting a read strobe signal, and HRESET is a system reset terminal for inputting a system reset signal.

[0184] Furthermore, in Figure 26(b), RA0+ and RA0- are data output terminals corresponding to differential signal line RA0 on the first transmission line LVDS1, RA1+ and RA1- are data output terminals corresponding to differential signal line RA1 on the first transmission line LVDS1, RA2+ and RA2- are data output terminals corresponding to differential signal line RA2 on the first transmission line LVDS1, RA3+ and RA3- are data output terminals corresponding to differential signal line RA3 on the first transmission line LVDS1, and RACLK+ and RACLK- are clocks corresponding to differential signal line RACLK on the first transmission line LVDS1. The output terminals RB0+ and RB0- are data output terminals corresponding to the differential signal line RB0 on ​​the second transmission line LVDS2 side; RB1+ and RB1- are data output terminals corresponding to the differential signal line RB1 on the second transmission line LVDS2 side; RB2+ and RB2- are data output terminals corresponding to the differential signal line RB2 on the second transmission line LVDS2 side; RB3+ and RB3- are data output terminals corresponding to the differential signal line RB3 on the second transmission line LVDS2 side; and RBCLK+ and RBCLK- are clock output terminals corresponding to the differential signal line RBCLK on the second transmission line LVDS2 side.

[0185] In the following explanation, the terminal symbols HAD0~HAD25, HDT0~HDT15, RA1+, RA1-, RBCLK+, RBCLK-, etc. of the corresponding composite chip 104 will be used as is for the terminal connection parts within the composite chip placement area 191. For example, terminal connection part HRD indicates the terminal connection part corresponding to the lead strobe output terminal HRD.

[0186] Figure 27 shows the type (terminal information) of each terminal of the control ROM 105. Of the terminals shown in Figure 27, A0 to A24 are address input terminals for inputting address information, and Q0 to Q15 are data input / output terminals for inputting and outputting data information, and are connected to the address output terminal and data input / output terminal of the composite chip 104, respectively. CE# is a chip select input terminal for inputting the chip select signal and is connected to the chip select output terminal of the composite chip 104. WE# is a writable input terminal and, by connecting it to the power supply and keeping it at a constant high level, it is possible to switch modes according to the value (H / L) of the OE# terminal. OE# is an outputable input terminal and is connected to the lead strobe output terminal of the composite chip 104.

[0187] RESET# is a reset terminal, connected to the power supply voltage monitoring integrated circuit (reset IC) along with the system reset input terminal HRESET of the composite chip 104. WP# / ACC is a write-protect / program input terminal, which can be connected to ground (L level) or power supply (H level) to switch between write protection / allowance and program execution protection / allowance. In this embodiment, the WP# / ACC terminal is connected to the power supply and set to H level. BYTE# is an 8 / 16-bit mode selection terminal, which can be connected to ground (L level) or power supply (H level) to select between 8-bit communication mode and 16-bit communication mode.

[0188] In the following explanation, the terminal connections corresponding to the control ROM layout area 192 will also use the same symbols as the terminals of the corresponding control ROM 105, such as A0-A24, Q0-Q15, CE#. For example, the terminal connection RESET# indicates the terminal connection corresponding to the reset terminal RESET#.

[0189] The following describes, with reference to the drawings, the details of several types of wiring paths P1 to P71, which connect the composite chip 104, the control ROM 105, the first LCD control connector CN31, the second LCD control connector CN32, etc., among the many wiring paths provided on the liquid crystal control board 98. Figures 28 to 33 show only the portions that constitute wiring paths P1 to P71, extracted from the wiring patterns of the first to sixth wiring layers La1 to La6 shown in Figures 20 to 25, and Figures 34 to 44 are enlarged views of these portions. Figures 45 to 53 schematically show the wiring paths of wiring paths P1 to P71. In Figures 45 to 50, vias shown in gray (for example, via v86 in wiring path P1 in Figure 45) indicate vias (specific interlayer conductive parts) located within the control ROM placement area 192, and wiring paths shown in thick lines (for example, wiring path cp13 in wiring path P2 in Figure 45) indicate wiring paths connected from the inside of the control ROM placement area 192 to the terminal connection part on the control ROM 105 side.

[0190] First, let's describe the wiring paths P1 to P26 connected to the address output terminals HAD0 to HAD25 of the composite chip 104. In this embodiment, of the address output terminals HAD0 to HAD25, HAD1 to HAD25 are connected to the address input terminals A0 to A24 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31. On the other hand, the address output terminal HAD0 is connected to the liquid crystal control first connector CN31, but is not connected to any terminals on the control ROM 105 side.

[0191] Furthermore, comparing the arrangement of the address output terminals HAD1 to HAD25 of the composite chip 104 (Figure 26(a)) with the corresponding arrangement of the address input terminals A0 to A24 of the control ROM 105 (Figure 27), the two are clearly different. Specifically, the address output terminals HAD1 to HAD25 of the composite chip 104 are arranged in six rows as shown in Figure 26(a), with the number of columns differing in each row but the order being consistent. In contrast, the address input terminals A0 to A24 of the control ROM 105 are arranged in two columns as shown in Figure 27, and there is no consistent order in the order of the terminals in each column. Moreover, the placement of the composite chip 104 and the control ROM 105, along with the large number of wiring patterns, results in a very complex wiring layout. Therefore, optimizing the wiring layout connecting the composite chip 104 and the control ROM 105 is extremely important, as it allows for shorter wiring lengths, leading to noise reduction and a slimmer overall board design. Furthermore, these points apply not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and various connectors and other electronic components. In particular, for wiring patterns that connect to multiple electronic components such as the composite chip 104 (HAD1-HAD25, HDT1-HDT25, etc.), the control ROM 105, and various connectors, the aforementioned challenges are significant, and therefore the benefits of optimization are substantial.

[0192] Of the wiring paths P1 to P26, in wiring path P1 (Figure 45), as shown in Figure 34, terminal connection HAD0 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp0 to via v0, which is located nearby in the diagonal XY direction. Via v0 is located approximately in the center of the four terminal connection points (including terminal connection HAD0) arranged around it. As shown in Figure 37, via v0 is connected to via v41 by wiring path cp1 provided in the third wiring layer La3. Via v41 is located between the composite chip placement area 191 and the control ROM placement area 192. Via v41 is then connected to via v86, which is located within the control ROM placement area 192, by wiring path cp2 provided in the fourth wiring layer La4, as shown in Figure 40. Thus, the wiring path drawn out from the terminal connection HAD0 in the first wiring layer La1 is connected to via v86 in the control ROM placement area 192 via two wiring layers La3 and La4.

[0193] The wiring path from terminal connection HAD0 to via v86 branches into two at via v86. As shown in Figures 37 and 38, the first branch is connected to via v146 in the first connector placement area 194 via via v205, which constitutes test point TP28, through wiring path cp3 provided in the third wiring layer La3, as shown in Figure 42. Furthermore, as shown in Figure 42, it is connected to terminal connection HAD0 from the inside of the first connector placement area 194 via wiring path cp4 provided in the sixth wiring layer La6. The second branch is connected to termination resistor RA16 via wiring path cp5 provided in the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA16 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0194] In the wiring path P2 (Figure 45), as shown in Figure 34, terminal connection HAD1, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp11 to via v5, which is located nearby in the diagonal XY direction. Via v5 is located approximately in the center of the four terminal connection sections (including terminal connection HAD1) arranged around it. As shown in Figure 40, via v5 is connected by wiring path cp12, located in the fourth wiring layer La4, to via v85, which is located in the control ROM placement area 192. Thus, unlike the wiring path drawn from terminal connection HAD0, the wiring path drawn from terminal connection HAD1 does not pass through the third wiring layer La3, but instead passes through the fourth wiring layer La4 to connect to via v85 in the control ROM placement area 192.

[0195] The wiring path from terminal connection HAD1 to via v85 branches into four at via v85. The first branch is connected from via v85 to terminal connection A0 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp13 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v85 to termination resistor RA16 via wiring path cp14 provided in the sixth wiring layer La6, as shown in Figure 41.

[0196] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v85 to via v145 in the first connector placement area 194 via wiring path cp15 provided in the third wiring layer La3, and further connected to terminal connection section had1 from the inside of the first connector placement area 194 via wiring path cp16 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v85 to via v182 via wiring path cp17 provided in the third wiring layer La3, and further connected to decoder IC 12 which constitutes the decoding circuit via wiring path cp18 provided in the sixth wiring layer La6, as shown in Figure 43.

[0197] Although some details are omitted in the wiring diagrams such as Figure 43, the decoding circuit including decoder ICs 12 to 14 is configured as shown in Figure 54. As shown in Figure 54, decoder ICs 13 and 14 are connected to the liquid crystal display means 76 via the liquid crystal IF third connector CN23, etc., and when the power is turned on, data information is input from the data input / output terminals HDT0 to HDT15 of the composite chip 104. Decoder ICs 13 and 14 then output data information to the liquid crystal display means 76, etc., based on a clock synchronized with the CPU input from decoder IC 12, so the CPU does not need to send fixed data information each time. As a result, the CPU does not need to output the same data information at predetermined intervals, and the CPU only needs to send new data information when the content of the data information is changed, thus simplifying the control program.

[0198] In wiring path P3 (Figure 45), as shown in Figure 34, terminal connection HAD2, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp21 to via v4, which is located nearby in the diagonal +XY direction. Via v4 is located approximately in the center of the four terminal connection parts (including terminal connection HAD2) arranged around it. As shown in Figure 40, via v4 is connected by wiring path cp22, provided in the fourth wiring layer La4, to via v84, which is located in the control ROM placement area 192.

[0199] The wiring path from terminal connection HAD2 to via v84 branches into four at via v84. The first branch is connected from via v84 to terminal connection A1 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp23 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v84 to termination resistor RA16 via wiring path cp24 provided in the sixth wiring layer La6, as shown in Figure 41.

[0200] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v84 to via v144 in the first connector placement area 194 via wiring path cp25 provided in the third wiring layer La3, and further connected to the terminal connection part had2 from the inside of the first connector placement area 194 via wiring path cp26 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v84 to via v184 via wiring path cp27 provided in the third wiring layer La3, and further connected to the decoder IC 12 that constitutes the decoding circuit via wiring path cp28 provided in the sixth wiring layer La6, as shown in Figure 43.

[0201] In wiring path P4 (Figure 45), as shown in Figure 34, terminal connection HAD3, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp31 to via v13, which is located nearby in the diagonal +XY direction. Via v13 is located approximately in the center of the four terminal connection parts (including terminal connection HAD3) arranged around it. As shown in Figure 40, via v13 is connected by wiring path cp32, located in the control ROM placement area 192, to via v83, which is located in the fourth wiring layer La4.

[0202] The wiring path from terminal connection HAD3 to via v83 branches into four at via v83. The first branch is connected from via v83 to terminal connection A2 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp33 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v83 to termination resistor RA16 via wiring path cp34 provided in the sixth wiring layer La6, as shown in Figure 41.

[0203] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v83 to via v143 in the first connector placement area 194 via wiring path cp35 provided in the third wiring layer La3, and further connected to terminal connection section had3 from the inside of the first connector placement area 194 via wiring path cp36 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v83 to via v181 via wiring path cp37 provided in the third wiring layer La3, and further connected to decoder IC 12 which constitutes the decoding circuit via wiring path cp38 provided in the sixth wiring layer La6, as shown in Figure 43.

[0204] In wiring path P5 (Figure 45), as shown in Figure 34, terminal connection HAD4, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp41 to via v20, which is located nearby in the diagonal +XY direction. Via v20 is located approximately in the center of the four terminal connection parts (including terminal connection HAD4) arranged around it. As shown in Figure 40, via v20 is connected by wiring path cp42, provided in the fourth wiring layer La4, to via v82, which is located in the control ROM placement area 192.

[0205] The wiring path from terminal connection HAD4 to via v82 branches into three at via v82. The first branch, as shown in Figure 35, is connected from via v82 to terminal connection A3 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp43 provided on the first wiring layer La1. The second branch, as shown in Figure 41, is connected from via v82 to termination resistor RA15 via wiring path cp44 provided on the sixth wiring layer La6. The other end of this termination resistor RA15 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0206] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v82 to via v142 in the first connector placement area 194 via wiring path cp45 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to the terminal connection part had4 from the inside of the first connector placement area 194 via wiring path cp46 provided in the sixth wiring layer La6.

[0207] In the wiring path P6 (Figure 45), as shown in Figure 34, the terminal connection part HAD5 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp51 to via v34 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HAD5 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v34 is connected by the wiring path cp52 provided in the fourth wiring layer La4 to via v81 located within the control ROM placement area 192.

[0208] The wiring path from terminal connection HAD5 to via v81 branches into three at via v81. The first branch is connected from via v81 to terminal connection A4 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp53 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v81 to termination resistor RA15 via wiring path cp54 provided in the sixth wiring layer La6, as shown in Figure 41.

[0209] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v81 to via v141 in the first connector placement area 194 via wiring path cp55 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to terminal connection part had5 from the inside of the first connector placement area 194 via wiring path cp56 provided in the sixth wiring layer La6.

[0210] In the wiring path P7 (Figure 45), as shown in Figure 34, the terminal connection HAD6 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp61 to via v39 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection HAD6 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v39 is connected by the wiring path cp62 provided in the fourth wiring layer La4 to via v80 located within the control ROM placement area 192.

[0211] The wiring path from terminal connection HAD6 to via v80 branches into three at via v80. The first branch is connected from via v80 to terminal connection A5 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp63 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v80 to termination resistor RA15 via wiring path cp64 provided on the sixth wiring layer La6, as shown in Figure 41.

[0212] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v80 to via v140 in the first connector placement area 194 via wiring path cp65 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to the terminal connection part had6 from the inside of the first connector placement area 194 via wiring path cp66 provided in the sixth wiring layer La6.

[0213] In wiring path P8 (Figure 45), as shown in Figure 34, terminal connection HAD7, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp71 to via v3, which is located nearby in the diagonal +XY direction. Via v3 is located approximately in the center of the four terminal connection parts (including terminal connection HAD7) arranged around it. As shown in Figure 40, via v3 is connected by wiring path cp72, located in the control ROM placement area 192, to via v79, which is located within the control ROM placement area 192, in the fourth wiring layer La4.

[0214] The wiring path from terminal connection HAD7 to via v79 branches into three at via v79. The first branch path, as shown in Figure 35, is connected from via v79 to terminal connection A6 of the control ROM 105 from inside the control ROM placement area 192 via wiring path cp73 provided on the first wiring layer La1. The second branch path, as shown in Figure 41, is connected from via v79 to termination resistor RA15 via wiring path cp74 provided on the sixth wiring layer La6.

[0215] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v79 to via v139 in the first connector placement area 194 via wiring path cp75 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to terminal connection portion had7 from the inside of the first connector placement area 194 via wiring path cp76 provided in the sixth wiring layer La6.

[0216] In wiring path P9 (Figure 46), as shown in Figure 34, terminal connection HAD8, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp81 to via v12, which is located nearby in the diagonal +XY direction. Via v12 is located approximately in the center of the four terminal connection parts (including terminal connection HAD8) arranged around it. As shown in Figure 40, via v12 is connected by wiring path cp82, located in the control ROM placement area 192, to via v78, which is located within the control ROM placement area 192.

[0217] The wiring path from terminal connection HAD8 to via v78 branches into three at via v78. The first branch is connected from via v78 to terminal connection A7 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp83 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v78 to termination resistor RA13 via wiring path cp84 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA13 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0218] Further, as shown in FIG. 37 and FIG. 38, the third branch path is connected from the via v78 to the via v138 in the first connector arrangement region 194 by the wiring path cp85 provided in the third wiring layer La3, and as further shown in FIG. 42, is connected to the terminal connection portion had8 from the inside of the first connector arrangement region 194 by the wiring path cp86 provided in the sixth wiring layer La6.

[0219] In the wiring path P10 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD9 provided in the composite chip arrangement region 191 of the first wiring layer La1 is connected by the wiring path cp91 to the via v33 arranged outside the composite chip arrangement region 191, specifically between the composite chip arrangement region 191 and the control ROM arrangement region 192. The terminal connection portion HAD9 is arranged in the second row from the outer peripheral side of the composite chip arrangement region 191. As shown in FIG. 40, the via v33 is connected to the via v77 arranged in the control ROM arrangement region 192 by the wiring path cp92 provided in the fourth wiring layer La4.

[0220] The wiring path extending from the terminal connection portion HAD9 to the via v77 branches into three paths at this via v77. As shown in FIG. 35, the first branch path is connected from the via v77 to the terminal connection portion A8 of the control ROM 105 from the inside of the control ROM arrangement region 192 by the wiring path cp93 provided in the first wiring layer La1. Further, as shown in FIG. 41, the second branch path is connected from the via v77 to the termination resistor RA13 by the wiring path cp94 provided in the sixth wiring layer La6.

[0221] Further, as shown in FIG. 37 and FIG. 38, the third branch path is connected from the via v77 to the via v137 in the first connector arrangement region 194 by the wiring path cp95 provided in the third wiring layer La3, and as further shown in FIG. 42, is connected to the terminal connection portion had9 from the inside of the first connector arrangement region 194 by the wiring path cp96 provided in the sixth wiring layer La6.

[0222] In the wiring path P11 (Figure 46), as shown in Figure 34, the terminal connection portion HAD10 provided in the composite chip arrangement region 191 of the first wiring layer La1 is connected by the wiring path cp101 to the via v38 arranged outside the composite chip arrangement region 191, specifically between the composite chip arrangement region 191 and the control ROM arrangement region 192. The terminal connection portion HAD10 is arranged on the outermost peripheral side of the composite chip arrangement region 191. As shown in Figure 40, the via v38 is connected by the wiring path cp102 provided in the fourth wiring layer La4 to the via v76 arranged in the control ROM arrangement region 192.

[0223] The wiring path that reaches the via v76 from the terminal connection portion HAD10 branches into three at this via v76. As shown in Figure 35, the first branch path is connected from the inside of the control ROM arrangement region 192 to the terminal connection portion A9 of the control ROM 105 from the via v76 by the wiring path cp103 provided in the first wiring layer La1. As shown in Figure 41, the second branch path is connected from the via v76 to the terminating resistor RA13 by the wiring path cp104 provided in the sixth wiring layer La6.

[0224] As shown in Figure 37 and Figure 38, the third branch path is connected from the via v76 to the via v136 in the first connector arrangement region 194 by the wiring path cp105 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected from the inside of the first connector arrangement region 194 to the terminal connection portion had10 by the wiring path cp106 provided in the sixth wiring layer La6.

[0225] In the wiring path P12 (Figure 46), as shown in Figure 34, the terminal connection portion HAD11 provided in the composite chip arrangement region 191 of the first wiring layer La1 is connected by the wiring path cp111 to the via v2 arranged in the vicinity in the oblique -X+Y direction. The via v2 is arranged substantially at the center of the four terminal connection portions (including the terminal connection portion HAD11) arranged around it. As shown in Figure 40, this via v2 is connected by the wiring path cp112 provided in the fourth wiring layer La4 to the via v75 arranged in the control ROM arrangement region 192.

[0226] The wiring path from terminal connection HAD11 to via v75 branches into three at via v75. The first branch is connected from via v75 to terminal connection A10 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp113 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v75 to termination resistor RA13 via wiring path cp114 provided in the sixth wiring layer La6, as shown in Figure 41.

[0227] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v75 to via v135 in the first connector placement area 194 via wiring path cp115 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to the terminal connection part had11 from the inside of the first connector placement area 194 via wiring path cp116 provided in the sixth wiring layer La6.

[0228] In wiring path P13 (Figure 46), as shown in Figure 34, terminal connector HAD12, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp121 to via v19, which is located nearby in the diagonal +XY direction. Via v19 is located approximately in the center of the four terminal connectors (including terminal connector HAD12) arranged around it. As shown in Figure 40, via v19 is connected by wiring path cp122, located in the control ROM placement area 192, to via v74, which is located in the fourth wiring layer La4.

[0229] The wiring path from terminal connection HAD12 to via v74 branches into three at via v74. The first branch, as shown in Figure 35, is connected from via v74 to terminal connection A11 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp123 provided on the first wiring layer La1. The second branch, as shown in Figure 41, is connected from via v74 to termination resistor RA11 via wiring path cp124 provided on the sixth wiring layer La6. The other end of this termination resistor RA11 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0230] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v74 to via v134 in the first connector placement area 194 via wiring path cp125 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to the terminal connection part had12 from the inside of the first connector placement area 194 via wiring path cp126 provided in the sixth wiring layer La6.

[0231] In the wiring path P14 (Figure 46), as shown in Figure 34, the terminal connection part HAD13 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp131 to via v49 located outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection part HAD13 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v49 is connected by the wiring path cp132 provided in the fourth wiring layer La4 to via v73 located within the control ROM placement area 192.

[0232] The wiring path from terminal connection HAD13 to via v73 branches into two at via v73. As shown in Figure 41, the first branch is connected from via v73 to termination resistor RA11 via wiring path cp133 provided in the sixth wiring layer La6.

[0233] Furthermore, as shown in Figure 37, the second branch is connected from via v73 to via v107 located in the control ROM placement area 192 via wiring path cp134 provided in the third wiring layer La3, and further branches into two here. The first of these, the 2a branch, is connected from via v107 to terminal connection A12 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp135 provided in the first wiring layer La1, as shown in Figure 35. The second of these, the 2b branch, is connected from via v107 to via v133 in the first connector placement area 194 via wiring path cp136 provided in the third wiring layer La3, as shown in Figures 37 and 38, and further connected to terminal connection had13 from the inside of the first connector placement area 194 via wiring path cp137 provided in the sixth wiring layer La6, as shown in Figure 42.

[0234] In the wiring path P15 (Figure 46), as shown in Figure 34, the terminal connection part HAD14 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp141 to via v50 located outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection part HAD14 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v50 is connected by the wiring path cp142 provided in the fourth wiring layer La4 to via v72 located within the control ROM placement area 192.

[0235] The wiring path from terminal connection HAD14 to via v72 branches into two at via v72. As shown in Figure 41, the first branch is connected from via v72 to termination resistor RA11 by wiring path cp143 provided in the sixth wiring layer La6.

[0236] Furthermore, as shown in Figure 37, the second branch is connected from via v72 to via v106 located in the control ROM placement area 192 via wiring path cp144 provided in the third wiring layer La3, and here it further branches into two. The first of these, the 2a branch, is connected from via v106 to terminal connection A13 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp145 provided in the first wiring layer La1, as shown in Figure 35. The second of these, the 2b branch, is connected from via v106 to via v132 in the first connector placement area 194 via wiring path cp146 provided in the third wiring layer La3, as shown in Figures 37 and 38, and further connected to terminal connection had14 from the inside of the first connector placement area 194 via wiring path cp147 provided in the sixth wiring layer La6, as shown in Figure 42.

[0237] In wiring path P16 (Figure 46), as shown in Figure 34, terminal connection HAD15, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp151 to via v11, which is located nearby in the diagonal +XY direction. Via v11 is located approximately in the center of the four terminal connection parts (including terminal connection HAD15) arranged around it. As shown in Figure 40, via v11 is connected by wiring path cp152, located in the control ROM placement area 192, to via v71, which is located in the fourth wiring layer La4.

[0238] The wiring path from terminal connection HAD15 to via v71 branches into two at via v71. As shown in Figure 41, the first branch is connected from via v71 to termination resistor RA11 by wiring path cp153 provided in the sixth wiring layer La6.

[0239] Furthermore, as shown in Figure 37, the second branch is connected from via v71 to via v105 located in the control ROM placement area 192 via wiring path cp154 provided in the third wiring layer La3, and then branches into two further. The first of these, the 2a branch, is connected from via v105 to terminal connection A14 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp155 provided in the first wiring layer La1, as shown in Figure 35. The second of these, the 2b branch, is connected from via v105 to via v131 in the first connector placement area 194 via wiring path cp156 provided in the third wiring layer La3, as shown in Figures 37 and 38, and further connected to terminal connection had15 from the inside of the first connector placement area 194 via wiring path cp157 provided in the sixth wiring layer La6, as shown in Figure 42.

[0240] In the wiring path P17 (Figure 46), as shown in Figure 34, terminal connection HAD16, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp161 to via v18, which is located nearby in the diagonal +XY direction. Via v18 is located approximately in the center of the four terminal connection parts (including terminal connection HAD16) arranged around it. As shown in Figure 40, via v18 is connected by wiring path cp162, provided in the fourth wiring layer La4, to via v70, which is located in the control ROM placement area 192.

[0241] The wiring path from terminal connection HAD16 to via v70 branches into two at via v70. The first branch is connected to termination resistor RA10 via wiring path cp163, which is provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA10 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0242] Further, as shown in FIG. 37, the second branch path is connected from the via v70 to the via v104 arranged in the control ROM arrangement region 192 by the wiring path cp164 provided in the third wiring layer La3, and is further branched into two here. As shown in FIG. 35, the first 2a-th branch path is connected from the via v104 to the terminal connection portion A15 of the control ROM 105 from the outside of the control ROM arrangement region 192 by the wiring path cp165 provided in the first wiring layer La1. As shown in FIGS. 37 and 38, the second 2b-th branch path is connected from the via v104 to the via v130 in the first connector arrangement region 194 by the wiring path cp166 provided in the third wiring layer La3, and as further shown in FIG. 42, is connected to the terminal connection portion had16 from the inside of the first connector arrangement region 194 by the wiring path cp167 provided in the sixth wiring layer La6.

[0243] In the wiring path P18 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD17 provided in the composite chip arrangement region 191 of the first wiring layer La1 is connected by the wiring path cp171 to the via v51 arranged outside the composite chip arrangement region 191, specifically on the +Y side of the control ROM arrangement region 192. The terminal connection portion HAD17 is arranged in the second row from the outer peripheral side of the composite chip arrangement region 191. As shown in FIG. 40, the via v51 is connected to the via v69 arranged in the control ROM arrangement region 192 by the wiring path cp172 provided in the fourth wiring layer La4.

[0244] The wiring path that has reached the via v69 from the terminal connection portion HAD17 is branched into two at this via v69. As shown in FIG. 41, the first branch path is connected from the via v69 to the termination resistor RA10 by the wiring path cp173 provided in the sixth wiring layer La6.

[0245] Furthermore, as shown in Figure 37, the second branch is connected from via v69 to via v103 located within the control ROM placement area 192 via wiring path cp174 provided in the third wiring layer La3, and here it further branches into two. The first of these, the 2a branch, is connected from via v103 to terminal connection A16 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp175 provided in the first wiring layer La1, as shown in Figure 35. The second of these, the 2b branch, is connected from via v103 to via v129 in the first connector placement area 194 via wiring path cp176 provided in the third wiring layer La3, as shown in Figures 37 and 38, and further connected to terminal connection had17 from inside the first connector placement area 194 via wiring path cp177 provided in the sixth wiring layer La6, as shown in Figure 42.

[0246] In the wiring path P19 (Figure 47), as shown in Figure 34, the terminal connection part HAD18 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp181 to via v52 located outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. Note that the terminal connection part HAD18 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v52 is connected by the wiring path cp182 provided in the fourth wiring layer La4 to via v68 located within the control ROM placement area 192.

[0247] The wiring path from terminal connection HAD18 to via v68 branches into three at via v68. The first branch, as shown in Figure 35, is connected from via v68 to terminal connection A17 of the control ROM 105 from inside the control ROM placement area 192 via wiring path cp183 provided in the first wiring layer La1. The second branch, as shown in Figure 41, is connected from via v68 to termination resistor RA10 via wiring path cp184 provided in the sixth wiring layer La6.

[0248] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v68 to via v128 in the first connector placement area 194 via wiring path cp185 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to terminal connection portion had18 from the inside of the first connector placement area 194 via wiring path cp186 provided in the sixth wiring layer La6.

[0249] In the wiring path P20 (Figure 47), as shown in Figure 34, terminal connection HAD19, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp191 to via v1, which is located nearby in the diagonal +XY direction. Via v1 is located approximately in the center of the four terminal connection parts (including terminal connection HAD19) arranged around it. As shown in Figure 40, via v1 is connected by wiring path cp192, provided in the fourth wiring layer La4, to via v67, which is located in the control ROM placement area 192.

[0250] The wiring path from terminal connection HAD19 to via v67 branches into three at via v67. The first branch, as shown in Figure 35, is connected from via v67 to terminal connection A18 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp193 provided in the first wiring layer La1. The second branch, as shown in Figure 41, is connected from via v67 to termination resistor RA10 via wiring path cp194 provided in the sixth wiring layer La6.

[0251] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v67 to via v127 in the first connector placement area 194 via wiring path cp195 provided in the third wiring layer La3, and further connected to terminal connection portion had19 from the inside of the first connector placement area 194 via wiring path cp196 provided in the sixth wiring layer La6, as shown in Figure 42.

[0252] In the wiring path P21 (Figure 47), as shown in Figure 34, terminal connection HAD20, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp201 to via v10, which is located nearby in the diagonal +XY direction. Via v10 is located approximately in the center of the four terminal connection parts (including terminal connection HAD20) arranged around it. As shown in Figure 40, via v10 is connected by wiring path cp202, provided in the fourth wiring layer La4, to via v66, which is located in the control ROM placement area 192.

[0253] The wiring path from terminal connection HAD20 to via v66 branches into three at via v66. The first branch is connected from via v66 to terminal connection A19 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp203 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v66 to termination resistor RA9 via wiring path cp204 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA9 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0254] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v66 to via v126 in the first connector placement area 194 via wiring path cp205 provided in the third wiring layer La3, and further connected to terminal connection section had20 from the inside of the first connector placement area 194 via wiring path cp206 provided in the sixth wiring layer La6, as shown in Figure 42.

[0255] In the wiring path P22 (Figure 47), as shown in Figures 34 and 35, the terminal connection part HAD21 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp211 to via v54 located outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection part HAD21 is located on the outermost periphery of the composite chip placement area 191. As shown in Figure 40, via v54 is connected by the wiring path cp212 provided in the fourth wiring layer La4 to via v65 located within the control ROM placement area 192.

[0256] The wiring path from terminal connection HAD21 to via v65 branches into three at via v65. The first branch is connected from via v65 to terminal connection A20 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp213 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v65 to termination resistor RA9 via wiring path cp214 provided in the sixth wiring layer La6, as shown in Figure 41.

[0257] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v65 to via v125 in the first connector placement area 194 via wiring path cp215 provided in the third wiring layer La3, and further connected to terminal connection portion had21 from the inside of the first connector placement area 194 via wiring path cp216 provided in the sixth wiring layer La6, as shown in Figure 42.

[0258] In the wiring path P23 (Figure 47), as shown in Figures 34 and 35, the terminal connection part HAD22 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp221 to via v53 located outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection part HAD22 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v53 is connected by the wiring path cp222 provided in the fourth wiring layer La4 to via v64 located within the control ROM placement area 192.

[0259] The wiring path from terminal connection HAD22 to via v64 branches into three at via v64. The first branch is connected from via v64 to terminal connection A21 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp223 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v64 to termination resistor RA9 via wiring path cp224 provided in the sixth wiring layer La6, as shown in Figure 41.

[0260] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v64 to via v124 in the first connector placement area 194 via wiring path cp225 provided in the third wiring layer La3, and further connected to terminal connection section had22 from the inside of the first connector placement area 194 via wiring path cp226 provided in the sixth wiring layer La6, as shown in Figure 42.

[0261] In the wiring path P24 (Figure 47), as shown in Figure 34, terminal connection HAD23 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp231 to via v21 located nearby in the diagonal +X+Y direction. Via v21 is located approximately in the center of the four terminal connection areas (including terminal connection HAD23) arranged around it. As shown in Figure 40, via v21 is connected by wiring path cp232 provided in the fourth wiring layer La4 to via v36 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. Furthermore, as shown in Figures 34 and 35, it is connected by wiring path cp233 provided in the first wiring layer La1 to via v63 located within the control ROM placement area 192.

[0262] The wiring path from terminal connection HAD23 to via v63 branches into three at via v63. The first branch is connected from via v63 to terminal connection A22 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp234 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v63 to termination resistor RA9 via wiring path cp235 provided on the sixth wiring layer La6, as shown in Figure 41.

[0263] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v63 to via v123 in the first connector placement area 194 via wiring path cp236 provided in the third wiring layer La3, and further connected to terminal connection portion had23 from the inside of the first connector placement area 194 via wiring path cp237 provided in the sixth wiring layer La6, as shown in Figure 42.

[0264] In the wiring path P25 (Figure 47), as shown in Figure 34, terminal connector HAD24 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp241 to via v14 located nearby in the diagonal +X+Y direction. Via v14 is located approximately in the center of the four terminal connectors (including terminal connector HAD24) arranged around it. As shown in Figure 40, via v14 is connected by wiring path cp242 provided in the fourth wiring layer La4 to via v35 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. Furthermore, as shown in Figures 34 and 35, it is connected by wiring path cp243 provided in the first wiring layer La1 to via v62 located within the control ROM placement area 192.

[0265] The wiring path from terminal connection HAD24 to via v62 branches into four at via v62. The first branch is connected from via v62 to terminal connection A23 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp244 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v62 to termination resistor R45 via wiring path cp245 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor R45 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0266] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v62 to via v122 in the first connector placement area 194 via wiring path cp246 provided in the third wiring layer La3, and further connected to terminal connection section had24 from the inside of the first connector placement area 194 via wiring path cp247 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v62 to via v183 via wiring path cp248 provided in the third wiring layer La3, and further connected to decoder IC12 which constitutes the decoding circuit via wiring path cp249 provided in the sixth wiring layer La6, as shown in Figure 43.

[0267] In the wiring path P26 (Figure 47), as shown in Figure 34, terminal connector HAD25 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp251 to via v6 located nearby in the diagonal +X+Y direction. Via v6 is located approximately in the center of the four terminal connectors (including terminal connector HAD25) arranged around it. As shown in Figure 40, via v6 is connected by wiring path cp252 provided in the fourth wiring layer La4 to via v40 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. Furthermore, as shown in Figures 34 and 35, it is connected by wiring path cp253 provided in the first wiring layer La1 to via v61 located within the control ROM placement area 192.

[0268] The wiring path from terminal connection HAD25 to via v61 branches into three at via v61. The first branch is connected from via v61 to terminal connection A24 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp254 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v61 to termination resistor R44 via wiring path cp255 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor R44 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0269] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v61 to via v121 in the first connector placement area 194 via wiring path cp256 provided in the third wiring layer La3, and as shown in Figure 42, it is connected to terminal connection portion had25 from the inside of the first connector placement area 194 via wiring path cp257 provided in the sixth wiring layer La6.

[0270] Next, we will explain the wiring paths P27 to P42 connected to the data input / output terminals HDT0 to HDT15 of the composite chip 104. The data input / output terminals HDT0 to HDT15 are connected to the data input / output terminals Q0 to Q15 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31.

[0271] Furthermore, comparing the arrangement of the data input / output terminals HDT0 to HDT15 of the composite chip 104 (Figure 26(a)) with the corresponding arrangement of the data input / output terminals Q0 to Q15 of the control ROM 105 (Figure 27), the two are clearly different. Specifically, the data input / output terminals HDT0 to HDT15 of the composite chip 104 are arranged in four rows as shown in Figure 26(a), with a different number of columns per row but a consistent order. In contrast, the data input / output terminals Q0 to Q15 of the control ROM 105 are arranged in two columns as shown in Figure 27, with no consistent order in each column. Moreover, the placement of the composite chip 104 and the control ROM 105, along with the large number of wiring patterns, results in a very complex wiring pattern routing. Therefore, optimizing the routing of the wiring patterns connecting the composite chip 104 and the control ROM 105 is extremely important, as this allows for shorter wiring pattern lengths, leading to noise reduction and a slimmer overall board design. Furthermore, these points apply not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and various connectors and other electronic components. In particular, for wiring patterns that connect to multiple electronic components such as the composite chip 104 (HAD1-HAD25, HDT1-HDT25, etc.), the control ROM 105, and various connectors, the aforementioned challenges are significant, and therefore the benefits of optimization are substantial.

[0272] Of the wiring paths P27 to P42, in wiring path P27 (Figure 48), as shown in Figure 34, the terminal connection part HDT0 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp301 to via v32 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. Note that the terminal connection part HDT0 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v32 is connected by wiring path cp302 provided in the fourth wiring layer La4 to via v102 located within the control ROM placement area 192.

[0273] The wiring path from terminal connection HDT0 to via v102 branches into four at via v102. The first branch is connected from via v102 to terminal connection Q0 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp303 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v102 to termination resistor RA34 via wiring path cp304 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA34 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0274] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v102 to via v162 in the first connector placement area 194 via wiring path cp305 provided in the third wiring layer La3, and further connected to the terminal connection part hdt0 from the inside of the first connector placement area 194 via wiring path cp306 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v102 to via v197 via wiring path cp307 provided in the third wiring layer La3, and further connected to the decoder IC 13 constituting the decoding circuit via wiring path cp308 provided in the sixth wiring layer La6, as shown in Figure 43.

[0275] In the wiring path P28 (Figure 48), as shown in Figure 34, the terminal connection part HDT1 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp311 to via v31 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT1 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v31 is connected by wiring path cp312 provided in the fourth wiring layer La4 to via v101 located within the control ROM placement area 192.

[0276] The wiring path from terminal connection HDT1 to via v101 branches into four at via v101. As shown in Figure 35, the first branch is connected from via v101 to terminal connection Q1 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp313 provided in the first wiring layer La1. The second branch is connected from via v101 to termination resistor RA34 via wiring path cp314 provided in the sixth wiring layer La6, as shown in Figure 41.

[0277] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v101 to via v161 in the first connector placement area 194 via wiring path cp315 provided in the third wiring layer La3, and further connected to the terminal connection part hdt1 from the inside of the first connector placement area 194 via wiring path cp316 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v101 to via v198 via wiring path cp317 provided in the third wiring layer La3, and further connected to the decoder IC 13 which constitutes the decoding circuit via wiring path cp318 provided in the sixth wiring layer La6, as shown in Figure 43.

[0278] In wiring path P29 (Figure 48), as shown in Figure 34, terminal connection HDT2, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp321 to via v24, which is located nearby in the diagonal +X+Y direction. Via v24 is located approximately in the center of the four terminal connection parts (including terminal connection HDT2) arranged around it. As shown in Figure 40, via v24 is connected by wiring path cp322, provided in the fourth wiring layer La4, to via v100, which is located in the control ROM placement area 192.

[0279] The wiring path from terminal connection HDT2 to via v100 branches into four at via v100. The first branch is connected from via v100 to terminal connection Q2 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp323 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v100 to termination resistor RA34 via wiring path cp324 provided on the sixth wiring layer La6, as shown in Figure 41.

[0280] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v100 to via v160 in the first connector placement area 194 via wiring path cp325 provided in the third wiring layer La3, and further connected to the terminal connection part hdt2 from the inside of the first connector placement area 194 via wiring path cp326 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v100 to via v199 via wiring path cp327 provided in the third wiring layer La3, and further connected to the decoder IC 13 which constitutes the decoding circuit via wiring path cp328 provided in the sixth wiring layer La6, as shown in Figure 43.

[0281] In wiring path P30 (Figure 48), as shown in Figure 34, terminal connection HDT3, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp331 to via v8, which is located nearby in the diagonal XY direction. Via v8 is located approximately in the center of the four terminal connection parts (including terminal connection HDT3) arranged around it. As shown in Figure 40, via v8 is connected by wiring path cp332, provided in the fourth wiring layer La4, to via v99, which is located in the control ROM placement area 192.

[0282] The wiring path from terminal connection HDT3 to via v99 branches into four at via v99. The first branch is connected from via v99 to terminal connection Q3 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp333 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v99 to termination resistor RA34 via wiring path cp334 provided on the sixth wiring layer La6, as shown in Figure 41.

[0283] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v99 to via v159 in the first connector placement area 194 via wiring path cp335 provided in the third wiring layer La3, and further connected to the terminal connection part hdt3 from the inside of the first connector placement area 194 via wiring path cp336 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v99 to via v200 via wiring path cp337 provided in the third wiring layer La3, and further connected to the decoder IC 13 which constitutes the decoding circuit via wiring path cp338 provided in the sixth wiring layer La6, as shown in Figure 43.

[0284] In the wiring path P31 (Figure 48), as shown in Figure 34, the terminal connection part HDT4 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp341 to via v37 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT4 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v37 is connected by wiring path cp342 provided in the fourth wiring layer La4 to via v98 located within the control ROM placement area 192.

[0285] The wiring path from terminal connection HDT4 to via v98 branches into four at via v98. The first branch is connected from via v98 to terminal connection Q4 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp343 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v98 to termination resistor RA32 via wiring path cp344 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA32 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0286] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v98 to via v158 in the first connector placement area 194 via wiring path cp345 provided in the third wiring layer La3, and further connected to the terminal connection part hdt4 from the inside of the first connector placement area 194 via wiring path cp346 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v98 to via v189 via wiring path cp347 provided in the third wiring layer La3, and further connected to the decoder IC 13 constituting the decoding circuit via wiring path cp348 provided in the sixth wiring layer La6, as shown in Figure 43.

[0287] In the wiring path P32 (Figure 48), as shown in Figure 34, the terminal connection part HDT5 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp351 to via v46 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT5 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v46 is connected by wiring path cp352 provided in the fourth wiring layer La4 to via v97 located within the control ROM placement area 192.

[0288] The wiring path from terminal connection HDT5 to via v97 branches into four at via v97. The first branch is connected from via v97 to terminal connection Q5 of the control ROM 105 from outside the control ROM arrangement area 192 via wiring path cp353 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v97 to termination resistor RA32 via wiring path cp354 provided on the sixth wiring layer La6, as shown in Figure 41.

[0289] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v97 to via v157 in the first connector placement area 194 via wiring path cp355 provided in the third wiring layer La3, and further connected to the terminal connection part hdt5 from the inside of the first connector placement area 194 via wiring path cp356 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v97 to via v190 via wiring path cp357 provided in the third wiring layer La3, and further connected to the decoder IC 13 which constitutes the decoding circuit via wiring path cp358 provided in the sixth wiring layer La6, as shown in Figure 43.

[0290] In the wiring path P33 (Figure 48), as shown in Figure 34, the terminal connection part HDT6 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp361 to via v17, which is located nearby in the diagonal +X+Y direction. Via v17 is located approximately in the center of the four terminal connection parts (including terminal connection part HDT6) arranged around it. As shown in Figure 40, via v17 is connected by wiring path cp362 provided in the fourth wiring layer La4 to via v96, which is located in the control ROM placement area 192.

[0291] The wiring path from terminal connection HDT6 to via v96 branches into four at via v96. The first branch is connected from via v96 to terminal connection Q6 of the control ROM 105 from outside the control ROM arrangement area 192 via wiring path cp363 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v96 to termination resistor RA32 via wiring path cp364 provided on the sixth wiring layer La6, as shown in Figure 41.

[0292] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v96 to via v156 in the first connector placement area 194 via wiring path cp365 provided in the third wiring layer La3, and further connected to the terminal connection part hdt6 from the inside of the first connector placement area 194 via wiring path cp366 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v96 to via v195 via wiring path cp367 provided in the third wiring layer La3, and further connected to the decoder IC 13 that constitutes the decoding circuit via wiring path cp368 provided in the sixth wiring layer La6, as shown in Figure 43.

[0293] In the wiring path P34 (Figure 48), as shown in Figure 34, the terminal connection part HDT7 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp371 to via v45 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT7 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v45 is connected by wiring path cp372 provided in the fourth wiring layer La4 to via v95 located within the control ROM placement area 192.

[0294] The wiring path from terminal connection HDT7 to via v95 branches into four at via v95. The first branch is connected from via v95 to terminal connection Q7 of the control ROM 105 from outside the control ROM placement area 192 via wiring path cp373, which is provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v95 to termination resistor RA32 via wiring path cp374, which is provided on the sixth wiring layer La6, as shown in Figure 41.

[0295] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v95 to via v155 in the first connector placement area 194 via wiring path cp375 provided in the third wiring layer La3, and further connected to the terminal connection part hdt7 from the inside of the first connector placement area 194 via wiring path cp376 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v95 to via v196 via wiring path cp377 provided in the third wiring layer La3, and further connected to the decoder IC 13 that constitutes the decoding circuit via wiring path cp378 provided in the sixth wiring layer La6, as shown in Figure 43.

[0296] In the wiring path P35 (Figure 49), as shown in Figure 34, the terminal connection part HDT8 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp381 to via v44 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT8 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v44 is connected by wiring path cp382 provided in the fourth wiring layer La4 to via v94 located within the control ROM placement area 192.

[0297] The wiring path from terminal connection HDT8 to via v94 branches into four at via v94. The first branch is connected from via v94 to terminal connection Q8 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp383 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v94 to termination resistor RA30 via wiring path cp384 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA30 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0298] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v94 to via v154 in the first connector placement area 194 via wiring path cp385 provided in the third wiring layer La3, and further connected to the terminal connection part hdt8 from the inside of the first connector placement area 194 via wiring path cp386 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v94 to via v191 via wiring path cp387 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp388 provided in the sixth wiring layer La6, as shown in Figure 43.

[0299] In wiring path P36 (Figure 49), as shown in Figure 34, terminal connection HDT9, provided in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp391 to via v23, which is located nearby in the diagonal +X+Y direction. Via v23 is located approximately in the center of the four terminal connection parts (including terminal connection HDT9) arranged around it. As shown in Figure 40, via v23 is connected by wiring path cp392, provided in the fourth wiring layer La4, to via v93, which is located within the control ROM placement area 192.

[0300] The wiring path from terminal connection HDT9 to via v93 branches into four at via v93. The first branch is connected from via v93 to terminal connection Q9 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp393 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v93 to termination resistor RA30 via wiring path cp394 provided on the sixth wiring layer La6, as shown in Figure 41.

[0301] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v93 to via v153 in the first connector placement area 194 via wiring path cp395 provided in the third wiring layer La3, and further connected to the terminal connection part hdt9 from the inside of the first connector placement area 194 via wiring path cp396 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v93 to via v192 via wiring path cp397 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp398 provided in the sixth wiring layer La6, as shown in Figure 43.

[0302] In wiring path P37 (Figure 49), as shown in Figure 34, terminal connection HDT10, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp401 to via v16, which is located nearby in the diagonal +X+Y direction. Via v16 is located approximately in the center of the four terminal connection parts (including terminal connection HDT10) arranged around it. As shown in Figure 40, via v16 is connected by wiring path cp402, located in the control ROM placement area 192, to via v92, which is located in the fourth wiring layer La4.

[0303] The wiring path from terminal connection HDT10 to via v92 branches into four at via v92. The first branch is connected from via v92 to terminal connection Q10 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp403 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v92 to termination resistor RA30 via wiring path cp404 provided on the sixth wiring layer La6, as shown in Figure 41.

[0304] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v92 to via v152 in the first connector placement area 194 via wiring path cp405 provided in the third wiring layer La3, and further connected to the terminal connection part hdt10 from the inside of the first connector placement area 194 via wiring path cp406 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v92 to via v193 via wiring path cp407 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp408 provided in the sixth wiring layer La6, as shown in Figure 43.

[0305] In wiring path P38 (Figure 49), as shown in Figure 34, terminal connection HDT11, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp411 to via v7, which is located nearby in the diagonal +X+Y direction. Via v7 is located approximately in the center of the four terminal connection parts (including terminal connection HDT11) arranged around it. As shown in Figure 40, via v7 is connected by wiring path cp412, located in the control ROM placement area 192, to via v91, which is located in the fourth wiring layer La4.

[0306] The wiring path from terminal connection HDT11 to via v91 branches into four at via v91. As shown in Figure 35, the first branch is connected from via v91 to terminal connection Q11 of the control ROM 105 from inside the control ROM arrangement area 192 via wiring path cp413 provided in the first wiring layer La1. The second branch is connected from via v91 to termination resistor RA30 via wiring path cp414 provided in the sixth wiring layer La6, as shown in Figure 41.

[0307] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v91 to via v151 in the first connector placement area 194 via wiring path cp415 provided in the third wiring layer La3, and further connected to the terminal connection part hdt11 from the inside of the first connector placement area 194 via wiring path cp416 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v91 to via v194 via wiring path cp417 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp418 provided in the sixth wiring layer La6, as shown in Figure 43.

[0308] In the wiring path P39 (Figure 49), as shown in Figure 34, the terminal connection part HDT12 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp421 to via v43 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT12 is located on the outermost edge of the composite chip placement area 191. As shown in Figure 40, via v43 is connected by wiring path cp422 provided in the fourth wiring layer La4 to via v90 located within the control ROM placement area 192.

[0309] The wiring path from terminal connection HDT12 to via v90 branches into four at via v90. The first branch is connected from via v90 to terminal connection Q12 of the control ROM 105 from the inside of the control ROM placement area 192 via wiring path cp423 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v90 to termination resistor RA17 via wiring path cp424 provided on the sixth wiring layer La6, as shown in Figure 41. The other end of this termination resistor RA17 is connected to the ground plane (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

[0310] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v90 to via v150 in the first connector placement area 194 via wiring path cp425 provided in the third wiring layer La3, and further connected to the terminal connection part hdt12 from the inside of the first connector placement area 194 via wiring path cp426 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v90 to via v185 via wiring path cp427 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp428 provided in the sixth wiring layer La6, as shown in Figure 43.

[0311] In the wiring path P40 (Figure 49), as shown in Figure 34, the terminal connection part HDT13 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp431 to via v42 located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT13 is located in the second row from the outer edge of the composite chip placement area 191. As shown in Figure 40, via v42 is connected by the wiring path cp432 provided in the fourth wiring layer La4 to via v89 located within the control ROM placement area 192.

[0312] The wiring path from terminal connection HDT13 to via v89 branches into four at via v89. The first branch is connected from via v89 to terminal connection Q13 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp433 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v89 to termination resistor RA17 via wiring path cp434 provided on the sixth wiring layer La6, as shown in Figure 41.

[0313] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v89 to via v149 in the first connector placement area 194 via wiring path cp435 provided in the third wiring layer La3, and further connected to the terminal connection part hdt13 from the inside of the first connector placement area 194 via wiring path cp436 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v89 to via v186 via wiring path cp437 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp438 provided in the sixth wiring layer La6, as shown in Figure 43.

[0314] In the wiring path P41 (Figure 49), as shown in Figure 34, the terminal connection part HDT14 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp441 to via v22, which is located nearby in the diagonal +X+Y direction. Via v22 is located approximately in the center of the four terminal connection parts (including terminal connection part HDT14) arranged around it. As shown in Figure 40, via v22 is connected by wiring path cp442 provided in the fourth wiring layer La4 to via v88, which is located in the control ROM placement area 192.

[0315] The wiring path from terminal connection HDT14 to via v88 branches into four at via v88. The first branch is connected from via v88 to terminal connection Q14 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp443 provided in the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v88 to termination resistor RA17 via wiring path cp444 provided in the sixth wiring layer La6, as shown in Figure 41.

[0316] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v88 to via v148 in the first connector placement area 194 via wiring path cp445 provided in the third wiring layer La3, and further connected to the terminal connection part hdt14 from the inside of the first connector placement area 194 via wiring path cp446 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v88 to via v187 via wiring path cp447 provided in the third wiring layer La3, and further connected to the decoder IC 14 that constitutes the decoding circuit via wiring path cp448 provided in the sixth wiring layer La6, as shown in Figure 43.

[0317] In the wiring path P42 (Figure 49), as shown in Figure 34, the terminal connection part HDT15 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp451 to via v15, which is located nearby in the diagonal +X+Y direction. Via v15 is located approximately in the center of the four terminal connection parts (including terminal connection part HDT15) arranged around it. As shown in Figure 40, via v15 is connected by wiring path cp452 provided in the fourth wiring layer La4 to via v87, which is located in the control ROM placement area 192.

[0318] The wiring path from terminal connection HDT15 to via v87 branches into four at via v87. The first branch is connected from via v87 to terminal connection Q15 / A-1 of the control ROM 105 from the inside of the control ROM arrangement area 192 via wiring path cp453 provided on the first wiring layer La1, as shown in Figure 35. The second branch is connected from via v87 to termination resistor RA17 via wiring path cp454 provided on the sixth wiring layer La6, as shown in Figure 41.

[0319] Furthermore, as shown in Figures 37 and 38, the third branch is connected from via v87 to via v147 in the first connector placement area 194 via wiring path cp455 provided in the third wiring layer La3, and further connected to the terminal connection part hdt15 from the inside of the first connector placement area 194 via wiring path cp456 provided in the sixth wiring layer La6, as shown in Figure 42. Furthermore, as shown in Figures 37 and 39, the fourth branch is connected from via v87 to via v188 via wiring path cp457 provided in the third wiring layer La3, and further connected to the decoder IC 14 via wiring path cp458 provided in the sixth wiring layer La6, as shown in Figure 43.

[0320] Next, we will explain the wiring paths P43 to P45 connected to the chip select output terminal HCS0, the lead strobe output terminal HRD, and the system reset terminal HRESET of the composite chip 104, respectively.

[0321] In wiring path P43 (Figure 50), as shown in Figure 34, terminal connection HCS0, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp501 to via v9, which is located nearby in the diagonal -X+Y direction, and here it branches into two. Via v9 is located approximately in the center of the four terminal connection parts (including terminal connection HCS0) arranged around it. The first branch path at via v9 is connected by wiring path cp502, located in the sixth wiring layer La6, to via v60, which is located in the control ROM placement area 192, as shown in Figure 33, and further connected from the inside of the control ROM placement area 192 to terminal connection CE#, as shown in Figure 35, by wiring path cp503, located in the first wiring layer La1.

[0322] Furthermore, the second branch in via v9 is connected to via v173 by wiring path cp504 located in the fourth wiring layer La4, as shown in Figure 31, and then branches into two further. The second a branch in via v173 is connected to via v201 by wiring path cp505 located in the sixth wiring layer La6, as shown in Figure 33. This via v201 constitutes test point TP33. The second b branch in via v173 is connected to DC3.3V (fifth wiring layer La5) via resistor RA12 through wiring path cp506 located in the first wiring layer La1, as shown in Figure 28.

[0323] In wiring path P44 (Figure 50), as shown in Figure 28, terminal connection HRD, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp511 to via v25, which is located nearby in the diagonal +XY direction, and here it branches into two. Via v25 is located approximately in the center of the four terminal connection areas (including terminal connection HRD) arranged around it. The first branch path at via v25 is connected by wiring path cp512, located in the sixth wiring layer La6, to via v47, located outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192, as shown in Figure 33. Furthermore, as shown in Figure 35, it is connected from outside the control ROM placement area 192 to terminal connection OE# by wiring path cp513, located in the first wiring layer La1.

[0324] Furthermore, as shown in Figure 30, the second branch in via v25 is connected to via v172 by wiring path cp514 provided in the third wiring layer La3, where it further branches into two. The seconda branch in via v172 is connected to via v171, located near the outside of the first connector placement area 194, by wiring path cp515 provided in the third wiring layer La3, as shown in Figure 30, and further connected to the terminal connection part hrd from the outside of the first connector placement area 194 by wiring path cp516 provided in the sixth wiring layer La6, as shown in Figure 33. The secondb branch in via v172 is connected to DC3.3V (fifth wiring layer La5) via resistor RA8 by wiring path cp517 provided in the first wiring layer La1, as shown in Figure 28.

[0325] In wiring path P45 (Figure 50), as shown in Figure 28, the terminal connection HRESET provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp521 to via v26 located on the outside (+X side) of the composite chip placement area 191. Note that the terminal connection HRESET is located on the outermost periphery of the composite chip placement area 191. As shown in Figure 31, via v26 is connected to via v202 by wiring path cp522 provided in the fourth wiring layer La4, and further connected to via v174 by wiring path cp523 provided in the sixth wiring layer La6, as shown in Figure 33, where it branches into two.

[0326] As shown in Figure 33, the first branch path in via v174 is connected to via v108, located near the outside (+X side) of the control ROM placement area 192, via wiring path cp524 provided in the sixth wiring layer La6. Furthermore, as shown in Figure 35, it is connected to the terminal connection RESET# from the inside of the control ROM placement area 192 via wiring path cp525 provided in the first wiring layer La1. As shown in Figure 33, wiring path cp524 of the sixth wiring layer La6 is connected to DC 3.3V (fifth wiring layer La5) via resistor R40, and is also connected to ground (second wiring layer La2) via capacitor C151.

[0327] Furthermore, the second branch in via v174 is connected to via v204 by wiring path cp526 provided on the first wiring layer La1, as shown in Figure 28. This via v204 constitutes test point TP17. Via v204 is then connected to the reset circuit on the sixth wiring layer La6 side. That is, as shown in Figure 33, via v204 is connected to resistor-integrated transistor T1 by wiring path cp527 provided on the sixth wiring layer La6, further connected to logic integrated circuit IC7 by wiring path cp528, and further connected to WDT-integrated reset integrated circuit (reset IC) IC10 via wiring path cp529 through via v203 which constitutes test point TP23. Wiring path cp528 is connected to DC3.3V (fifth wiring layer La5) via resistor R19, and wiring path cp529 is connected to ground (second wiring layer La2) via capacitor C40 and to DC3.3V (fifth wiring layer La5) via resistor R26.

[0328] The reset circuit on the sixth wiring layer La6 is configured as shown in Figure 55. The logic integrated circuit IC7 can receive a system reset signal via the liquid crystal control first connector CN31, and a reset signal from the WDT-integrated reset integrated circuit (reset IC) IC10. When either of these reset signals is input, a reset signal is transmitted to the composite chip 104 and the control ROM 105 via the resistor-integrated transistor T1 for noise suppression. The WDT-integrated reset integrated circuit (reset IC) IC10 is connected, for example, to the LED data output terminal ASIBLDTB of the composite chip 104 for WDT reset.

[0329] Here, test point TP23 is used to check when the reset integrated circuit IC10 is activated. As shown in Figure 33, it is located on the wiring path cp421 on the sixth wiring layer La6 side and near the reset integrated circuit IC10. Therefore, the identification information "TP23" indicating test point TP23 is usually printed on the sixth wiring layer La6 side where the wiring path cp421 is located, i.e., on the back side 98b. On the other hand, the check operation using test point TP23 needs to be performed when the circuit board is assembled (see Figures 8 and 9) or when the circuit board is installed in the gaming machine body. However, in that state, the back side 98b of the liquid crystal control board 98 is obscured by the opposing performance interface board 96 and liquid crystal interface board 97, making it impossible to apply a tester. Therefore, in this embodiment, as shown in Figure 56, the identification information "TP23" indicating test point TP23 is placed on the front side 98a, not on the wiring path cp421 side where test point TP23 is located, i.e., on the back side 98b. Furthermore, since test point TP23 is formed by via v203 that penetrates the main board body 190, it is possible to apply the tester from the surface 98a side of the main board body 190.

[0330] Furthermore, test point TP17 is located in via v204, which connects the wiring path cp418 on the first wiring layer La1 side and the wiring path cp419 on the sixth wiring layer La6 side. The "TP17" marking, which is the identification information for test point TP17, is also located on the surface 98a side, just like test point TP23.

[0331] The same applies to the other test points TP28 and TP33 mentioned above. Specifically, test point TP28 is located on the wiring path cp3 of the third wiring layer La3, but the identification information "TP28" for this test point TP28 is located on the surface 98a side. Similarly, test point TP33 is located on the wiring path cp505 of the sixth wiring layer La6, but the identification information "TP33" for this test point TP33 is located on the surface 98a side.

[0332] Next, we will explain the wiring paths P46 and P47 connected to the 8 / 16-bit mode selection terminal BYTE#, the writable input terminal WE#, and the write-protected / program input terminal WP# / ACC of the control ROM 105, respectively. Note that these wiring paths P46 and P47 are not connected to the composite chip 104.

[0333] In the wiring path P46 (Figure 50), as shown in Figure 35, terminal connection BYTE#, located in the control ROM placement area 192 of the first wiring layer La1, is connected to via v48 by wiring path cp531. This via v48 is located near terminal connection BYTE# on the outside (-X side) of the control ROM placement area 192 and is connected to DC 3.3V via the fifth wiring layer La5, as shown in Figure 32. Thus, in this embodiment, the 16-bit communication mode is selected because the 8 / 16-bit mode selection terminal BYTE# of the control ROM 105 is connected to the power supply (H level).

[0334] In the wiring path P47 (Figure 50), as shown in Figure 35, the terminal connection part WE# (first predetermined terminal) provided in the control ROM placement area 192 of the first wiring layer La1 is connected to via v111 by the wiring path cp541. This via v111 (first predetermined interlayer conduction part) is located near the terminal connection part WE# on the outside (+X side) of the control ROM placement area 192, and as shown in Figure 32, it is connected to DC 3.3V via the fifth wiring layer La5. Thus, in this embodiment, since the writable input terminal WE# of the control ROM 105 is connected to the power supply (H level), it is possible to switch modes according to the value (H / L) of the output-enabled input terminal OE#, such as being in a non-output mode when the level is H (not reading) and in output mode when the level is L (reading). Note that the output-enabled input terminal OE# is connected to the lead strobe output terminal HRD of the composite chip 104 as described above.

[0335] Furthermore, in wiring path P47, as shown in Figure 35, the terminal connection part WP# / ACC (second predetermined terminal) provided in the control ROM placement area 192 of the first wiring layer La1 is connected to via v112 by wiring path cp542. This via v112 is located near the terminal connection part WP# / ACC on the outside (+X side) of the control ROM placement area 192. Also, as shown in Figure 33, via v112 (second predetermined interlayer conduction part) is connected to via v111 via resistor R43 by wiring path cp543 provided in the sixth wiring layer La6. This via v111 is connected to DC 3.3V via the fifth wiring layer La5 as described above. Thus, in this embodiment, the write-protect / program input terminal WP# / ACC of the control ROM (specific electronic component) 105 is connected to the power supply (H level), thereby enabling writing and program execution. In addition, by connecting to the power supply via resistor R43, inputs exceeding the H level are excluded, ensuring a stable H level.

[0336] For example, if, depending on the type of control ROM, a mode setting different from write-prohibition / allowance or program execution-prohibition / allowance is performed when an input exceeding the H level is received, configuring it to stably reach the H level via a resistor in this way prevents the control ROM from switching to a mode different from write-prohibition / allowance or program execution-prohibition / allowance even when an input exceeding the H level is received due to noise or other factors.

[0337] Next, we will explain the wiring paths P48 to P51 for transmitting the power control signals PS1 and PS2, the backlight ON / OFF control signal XSTABY1, and the backlight dimming PWM signal VBR1, respectively, by connecting the decoder IC 13 and the LCD control second connector CN32. The connection between the data input / output terminals HDT0 to HDT7 of the composite chip 104 and the decoder IC 13 has already been explained as wiring paths P27 to P34 (Figure 48). In addition, the LCD control second connector CN32 has a large number of terminals arranged in two rows along the longitudinal direction (X direction), and the connector terminals ps1, ps2, xstaby1, and vbr1 are arranged along the second edge 195b on the -Y side of the second connector arrangement area 195.

[0338] The wiring path P48 (Figure 51) transmits the power control signal PS1. As shown in Figure 43, wiring path cp551 is drawn out from the decoder IC 13 on the sixth wiring layer La6 to the -Y side and connected to via v211. As shown in Figure 30, via v211 is connected to via v212 via wiring path cp552 located on the third wiring layer La3. Then, as shown in Figure 44, via v212 is connected to the terminal connection part ps1 of the liquid crystal control second connector CN32 from the outside (-Y side) of the second connector arrangement area 195 via wiring path cp553 located on the sixth wiring layer La6.

[0339] The wiring path P49 (Figure 51) transmits the power control signal PS2. As shown in Figure 43, wiring path cp561 is drawn out from the decoder IC 13 on the sixth wiring layer La6 to the -Y side and connected to via v221. As shown in Figure 30, via v221 is connected to via v222 via wiring path cp562 located on the third wiring layer La3. Then, as shown in Figure 44, via v222 is connected to the terminal connection part ps2 of the liquid crystal control second connector CN32 from the outside (-Y side) of the second connector arrangement area 195 via wiring path cp563 located on the sixth wiring layer La6.

[0340] The wiring path (B wiring path) P50 (Figure 51) transmits the backlight ON / OFF control signal XSTABY1. As shown in Figure 43, wiring path cp571 is drawn out from decoder IC 13 on the 6th wiring layer La6 to the -Y side and connected to via v231. As shown in Figure 30, via v231 is connected to via v232 via wiring path cp572 located on the 3rd wiring layer La3. Then, as shown in Figure 44, via v232 is connected to the terminal connection part xstaby1 of the liquid crystal control 2nd connector CN32 from the outside (-Y side) of the 2nd connector arrangement area 195 via wiring path cp573 located on the 6th wiring layer La6.

[0341] The wiring path (B wiring path) P51 (Figure 51) transmits the PWM signal VBR1 for backlight dimming. As shown in Figure 43, wiring path cp581 is drawn out from decoder IC 13 on the sixth wiring layer La6 to the -Y side and connected to via v241. As shown in Figure 30, via v241 is connected to via v242 via wiring path cp582 located on the third wiring layer La3. Then, as shown in Figure 44, via v242 is connected to the terminal connection part vbr1 of the liquid crystal control second connector CN32 from the outside (-Y side) of the second connector arrangement area 195 via wiring path cp583 located on the sixth wiring layer La6.

[0342] Next, we will explain the wiring (first wiring, wiring A) P52~P61 that connects the data output terminals RA0+, RA0-, RA1+, RA1-, RA2+, RA2-, RA3+, RA3-, RACLK+, RACLK- (hereinafter referred to as the ODD-side data output terminal group) of the composite chip 104 to the LCD control second connector CN32, and the wiring (second wiring, wiring A) P62~P71 that connects the data output terminals RB0+, RB0-, RB1+, RB1-, RB2+, RB2-, RB3+, RB3-, RBCLK+, RBCLK- (hereinafter referred to as the EVEN-side data output terminal group) to the LCD control second connector CN32. Note that wiring P52~P61 constitutes the first transmission line LVDS1 for transmitting the ODD signal, and wiring P62~P71 constitutes the second transmission line LVDS2 for transmitting the EVEN signal.

[0343] The ODD-side data output terminals (first chip terminals) of the composite chip 104 are arranged in two rows along the second edge 191b of the composite chip placement area 191, as shown in Figures 26(b) and 36. Specifically, the data output terminals RA0-, RA1-, RA2-, RACLK-, and RA3- are arranged in the -X direction in that order on the outermost periphery of the composite chip placement area 191, and further inside these, the data output terminals RA0+, RA1+, RA2+, RACLK+, and RA3+ are arranged in the -X direction in that order.

[0344] Furthermore, the EVEN-side data output terminal group (second chip terminals) of the composite chip 104 are arranged in two rows inside the composite chip placement area 191 relative to the ODD-side data output terminal group, as shown in Figures 26(b) and 36. Specifically, inside the ODD-side data output terminal group, with the GND terminal row in between, the data output terminals RB0-, RB1-, RB2-, RBCLK-, and RB3- are arranged in that order in the -X direction, and further inside these, the data output terminals RB0+, RB1+, RB2+, RBCLK+, and RB3+ are arranged in that order in the -X direction.

[0345] Furthermore, the second connector placement area 195, where the liquid crystal control second connector CN32 is located, is arranged in an elongated shape parallel to the second edge 191b of the composite chip placement area 191, as shown in Figures 33, 36, etc. In the liquid crystal control second connector CN32, numerous terminals are arranged in two rows along the longitudinal direction (X direction). As shown in Figure 44, the connector terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ corresponding to the ODD side data output terminal group are arranged in the -X direction along the first edge 195a on the -Y side of the second connector arrangement area 195, and the connector terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ corresponding to the EVEN side data output terminal group are arranged in the -X direction along the second edge 195b on the +Y side of the second connector arrangement area 195.

[0346] First, let's explain the wiring paths (first wiring paths) P52 to P61 (Figure 52) that constitute the first transmission path LVDS1. In wiring path P52 (Figure 52), as shown in Figure 36, the terminal connection part RA0- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp601 to a via (specific interlayer conduction part) v251 located within the second connector placement area 195 (near the connector). As shown in Figure 44, via v251 is connected to the terminal connection part ra0- from the inside of the second connector placement area 195 by wiring path cp602 of the sixth wiring layer La6.

[0347] In wiring path P53 (Figure 52), as shown in Figure 36, terminal connection RA0+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp603 to via (specific interlayer conductive portion) v252 located within the second connector placement area 195 (near the connector). Note that wiring path cp603 is led out to the outside of the composite chip placement area 191 via terminal connection RA0- and the adjacent terminal connection RA1-. That is, the two wiring paths cp601 and cp603 that constitute the operating signal line RA0 are arranged adjacent to each other and in parallel. As shown in Figure 44, via v252 is connected to terminal connection ra0+ from the inside of the second connector placement area 195 by wiring path cp604 of the sixth wiring layer La6.

[0348] In the wiring path P54 (Figure 52), as shown in Figure 36, the terminal connection portion RA1- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp605 to a via (specific interlayer conductive portion) v253 located within the second connector placement area 195 (near the connector). As shown in Figure 44, via v253 is connected to the terminal connection portion ra1- from the inside of the second connector placement area 195 by the wiring path cp606 of the sixth wiring layer La6.

[0349] In wiring path P55 (Figure 52), as shown in Figure 36, terminal connection RA1+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp607 to via (specific interlayer conductive portion) v254 located within the second connector placement area 195 (near the connector). Note that wiring path cp607 is led out to the outside of the composite chip placement area 191 via terminal connection RA1- and the adjacent terminal connection RA2-. That is, the two wiring paths cp605 and cp607 that constitute the operating signal line RA1 are arranged adjacent to each other and in parallel. As shown in Figure 44, via v254 is connected to terminal connection ra1+ from the inside of the second connector placement area 195 by wiring path cp608 of the sixth wiring layer La6.

[0350] In the wiring path P56 (Figure 52), as shown in Figure 36, the terminal connection portion RA2- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp609 to a via (specific interlayer conductive portion) v255 located within the second connector placement area 195 (near the connector). As shown in Figure 44, via v255 is connected to the terminal connection portion ra2- from the inside of the second connector placement area 195 by the wiring path cp610 of the sixth wiring layer La6.

[0351] In wiring path P57 (Figure 52), as shown in Figure 36, terminal connection RA2+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp611 to via (specific interlayer conductive portion) v256 located within the second connector placement area 195 (near the connector). Note that wiring path cp611 is led out to the outside of the composite chip placement area 191 via terminal connection RA2- and the adjacent terminal connection RACLK-. That is, the two wiring paths cp609 and cp611 that constitute the operating signal line RA2 are arranged adjacent to each other and in parallel. As shown in Figure 44, via v256 is connected to terminal connection ra2+ from the inside of the second connector placement area 195 by wiring path cp612 of the sixth wiring layer La6.

[0352] In wiring path P58 (Figure 52), as shown in Figure 36, the terminal connection RACLK- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp613 to a via (specific interlayer conductive portion) v257 located within the second connector placement area 195 (near the connector). As shown in Figure 44, via v257 is connected to the terminal connection raclk- from the inside of the second connector placement area 195 by wiring path cp614 of the sixth wiring layer La6.

[0353] In wiring path P59 (Figure 52), as shown in Figure 36, the terminal connection RACLK+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp615 to via (specific interlayer conductive portion) v258 located within the second connector placement area 195 (near the connector). Note that wiring path cp615 is led out to the outside of the composite chip placement area 191 via the space between terminal connection RACLK- and the adjacent terminal connection RA3-. That is, the two wiring paths cp613 and cp615 that constitute the operating signal line RACLK are arranged adjacent to each other and in parallel. As shown in Figure 44, via v258 is connected to terminal connection raclk+ from the inside of the second connector placement area 195 by wiring path cp616 of the sixth wiring layer La6.

[0354] In the wiring path P60 (Figure 52), as shown in Figure 36, the terminal connection portion RA3- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp617 to a via (specific interlayer conductive portion) v259 located within the second connector placement area 195 (near the connector). As shown in Figure 44, via v259 is connected to the terminal connection portion ra3- from the inside of the second connector placement area 195 by the wiring path cp618 of the sixth wiring layer La6.

[0355] In the wiring path P61 (Figure 52), as shown in Figure 36, the terminal connection part RA3+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp619 to the via (specific interlayer conductive part) v260 located within the second connector placement area 195 (near the connector). The wiring path cp619 is led out to the outside of the composite chip placement area 191 via the -X side of the terminal connection part RA3-. In other words, the two wiring paths cp617 and cp619 that constitute the operating signal line RA3 are arranged adjacent to each other and in parallel. The via v260 is then connected to the terminal connection part ra3+ from the inside of the second connector placement area 195 by the wiring path cp620 of the sixth wiring layer La6, as shown in Figure 44.

[0356] Furthermore, as shown in Figure 36, in the first wiring layer La1, ground wiring paths gp1 to gp4 are arranged between the wiring paths cp601 and cp603 that constitute the activation signal line RA0 and the wiring paths cp605 and cp607 that constitute the activation signal line RA1; between the wiring paths cp605 and cp607 that constitute the activation signal line RA1 and the wiring paths cp609 and cp611 that constitute the activation signal line RA2; between the wiring paths cp609 and cp611 that constitute the activation signal line RA2 and the wiring paths cp613 and cp615 that constitute the activation signal line RACLK; and between the wiring paths cp613 and cp615 that constitute the activation signal line RACLK and the wiring paths cp617 and cp619 that constitute the activation signal line RA3. The ground wiring paths gp1 to gp4 are formed in an elongated shape with a substantially constant width.

[0357] Next, the wiring paths (second wiring paths) P62 to P71 (Figure 53) that constitute the second transmission path LVDS2 will be described. In wiring path P62 (Figure 53), as shown in Figure 36, the terminal connection part RB0- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp621 to via v261 which is located nearby in the diagonal +XY direction. Via v261 is located approximately in the center of the four terminal connection parts (including terminal connection part RB0-) arranged around it. As shown in Figure 44, via v261 is connected to the terminal connection part rb0- from the outside of the second connector placement area 195 by wiring path cp622 of the sixth wiring layer La6.

[0358] In wiring path P63 (Figure 53), as shown in Figure 36, the terminal connection RB0+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp623 to via v262, which is located nearby in the diagonal +XY direction. Via v262 is located approximately in the center of the four terminal connection parts (including terminal connection part RB0+) arranged around it. As shown in Figure 44, via v262 is connected to the terminal connection rb0+ from outside the second connector placement area 195 by wiring path cp624 of the sixth wiring layer La6. Note that wiring path cp624 is led out to the outside of the composite chip placement area 191 via the +X side of via v261. In other words, the two wiring paths cp622 and cp624 that constitute the operation signal line RB0 are arranged adjacent to each other and in parallel.

[0359] In the wiring path P64 (Figure 53), as shown in Figure 36, the terminal connection portion RB1- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp625 to via v263, which is located nearby in the diagonal +XY direction. Via v263 is located approximately in the center of the four terminal connection portions (including terminal connection portion RB1-) arranged around it. As shown in Figure 44, via v263 is connected to the terminal connection portion rb1- from outside the second connector placement area 195 by the wiring path cp626 of the sixth wiring layer La6.

[0360] In wiring path P65 (Figure 53), as shown in Figure 36, terminal connection RB1+, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp627 to via v264, which is located nearby in the diagonal +XY direction. Via v264 is located approximately in the center of the four terminal connection parts (including terminal connection RB1+) arranged around it. As shown in Figure 44, via v264 is connected to terminal connection rb1+ from outside the second connector placement area 195 by wiring path cp628 of the sixth wiring layer La6. Note that wiring path cp628 is led out to the outside of the composite chip placement area 191 via via v263 and the adjacent via v261. In other words, the two wiring paths cp626 and cp628 that constitute the operation signal line RB1 are arranged adjacent to each other and in parallel.

[0361] In the wiring path P66 (Figure 53), as shown in Figure 36, the terminal connection part RB2- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by the wiring path cp629 to via v265, which is located nearby in the diagonal +XY direction. Via v265 is located approximately in the center of the four terminal connection parts (including terminal connection part RB2-) arranged around it. As shown in Figure 44, via v265 is connected to the terminal connection part rb2- from the outside of the second connector placement area 195 by the wiring path cp630 of the sixth wiring layer La6.

[0362] In wiring path P67 (Figure 53), as shown in Figure 36, terminal connection RB2+, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp631 to via v266, which is located nearby in the diagonal +XY direction. Via v266 is located approximately in the center of the four terminal connection parts (including terminal connection RB2+) arranged around it. As shown in Figure 44, via v266 is connected to terminal connection rb2+ from outside the second connector placement area 195 by wiring path cp632 of the sixth wiring layer La6. Note that wiring path cp632 is led out to the outside of the composite chip placement area 191 via via v265 and the adjacent via v263. In other words, the two wiring paths cp630 and cp632 that constitute the operation signal line RB2 are arranged adjacent to each other and in parallel.

[0363] In wiring path P68 (Figure 53), as shown in Figure 36, the terminal connection RBCLK- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp633 to via v267, which is located nearby in the diagonal +XY direction. Via v267 is located approximately in the center of the four terminal connection parts (including terminal connection RBCLK-) arranged around it. As shown in Figure 44, via v267 is connected to the terminal connection rbclk- from outside the second connector placement area 195 by wiring path cp634 of the sixth wiring layer La6.

[0364] In wiring path P69 (Figure 53), as shown in Figure 36, the terminal connection RBCLK+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp635 to via v268, which is located nearby in the diagonal +XY direction. Via v268 is located approximately in the center of the four terminal connections (including terminal connection RBCLK+) arranged around it. As shown in Figure 44, via v268 is connected to the terminal connection rbCLK+ from outside the second connector placement area 195 by wiring path cp636 of the sixth wiring layer La6. Note that wiring path cp636 is led out to the outside of the composite chip placement area 191 via via v267 and the adjacent via v265. In other words, the two wiring paths cp634 and cp636 that constitute the operating signal line RBCLK are arranged adjacent to each other and in parallel.

[0365] In wiring path P70 (Figure 53), as shown in Figure 36, terminal connection portion RB3- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by wiring path cp637 to via v269, which is located nearby in the diagonal +XY direction. Via v269 is located approximately in the center of the four terminal connection portions (including terminal connection portion RB3-) arranged around it. As shown in Figure 44, via v269 is connected to terminal connection portion rb3- from the outside of the second connector placement area 195 by wiring path cp638 of the sixth wiring layer La6.

[0366] In wiring path P71 (Figure 53), as shown in Figure 36, terminal connection RB3+, located in the composite chip placement area 191 of the first wiring layer La1, is connected by wiring path cp639 to via v270, which is located nearby in the diagonal +XY direction. Via v270 is located approximately in the center of the four terminal connection parts (including terminal connection RB3+) arranged around it. As shown in Figure 44, via v270 is connected to terminal connection rb3+ from outside the second connector placement area 195 by wiring path cp640 of the sixth wiring layer La6. Note that wiring path cp640 is led out to the outside of the composite chip placement area 191 via via v269 and the adjacent via v267. In other words, the two wiring paths cp638 and cp640 that constitute the operation signal line RB3 are arranged adjacent to each other and in parallel.

[0367] Furthermore, as shown in Figure 44, in the sixth wiring layer La6, ground wiring paths gp11 to gp14 are arranged between the wiring paths cp622 and cp624 that constitute the activation signal line RB0 and the wiring paths cp626 and cp628 that constitute the activation signal line RB1; between the wiring paths cp626 and cp628 that constitute the activation signal line RB1 and the wiring paths cp630 and cp632 that constitute the activation signal line RB2; between the wiring paths cp630 and cp632 that constitute the activation signal line RB2 and the wiring paths cp634 and cp636 that constitute the activation signal line RBCLK; and between the wiring paths cp634 and cp636 that constitute the activation signal line RBCLK and the wiring paths cp638 and cp640 that constitute the activation signal line RB3.

[0368] As described above, in the wiring patterns shown in Figures 36 and 44, ground wiring paths gp1~gp4 and gp11~gp14 are placed between multiple sets (5 sets each) of wiring path pairs that constitute the operating signal line. This is to reduce noise to the surrounding wiring paths cp601, cp622, etc., from these ground wiring paths gp1~gp4 and gp11~gp14. Furthermore, it is desirable that these ground wiring paths gp1~gp4 and gp11~gp14 be wider than the surrounding wiring paths cp601, cp622, etc., as shown in Figures 36 and 44. This is because the surrounding wiring paths cp601, cp622, etc., are wiring paths for transmitting image data, and a more noise-resistant design is necessary to prevent the images on the screen from becoming difficult to see due to noise.

[0369] Furthermore, the ground wiring paths gp1 to gp4 on the first wiring layer La1 side and the ground wiring paths gp11 to gp14 on the sixth wiring layer La6 side are connected to each other via multiple through-holes (vias), as shown in Figures 36 and 44, thereby enabling further noise reduction.

[0370] Furthermore, as shown in Figures 36 and 44, the ground wiring paths gp1 to gp4 on the first wiring layer La1 side and the ground wiring paths gp11 to gp14 on the sixth wiring layer La6 side have different shapes depending on the surrounding wiring pattern, but they are configured to pass through partially corresponding locations (regions) of each other, and are connected via through-holes (vias) at these corresponding locations (multiple locations in this case). This makes it possible to adopt a shape that corresponds to the surrounding wiring pattern while creating a wiring pattern that is more resistant to noise and more efficient.

[0371] To summarize the configuration of the wiring paths P1 to P71 described above, of the wiring paths P2 to P45 that connect the composite chip 104 and the control ROM 105, wiring paths P2 to P43 and P45 (specific wiring paths) are connected to the terminal connection parts on the control ROM 105 side via vias v60 to v108 (specific interlayer conduction parts; vias shown in gray in Figures 45 to 50) located within the control ROM placement area (second placement area) 192, as shown in Figures 35, 45 to 50. Furthermore, among these, wiring paths P2 to P16, P19 to P23, P35 to P43 and P45 (first specific wiring paths) are connected from the inside of the control ROM placement area 192 to the terminal connection parts A0 to A14, A17 to A21, Q8 to Q15, CE#, and RESET# on the control ROM 105 side (wiring paths shown in thick lines in Figures 45 to 50). In this way, by arranging the wiring path connecting the composite chip 104 and the control ROM 105 to pass through the relatively spacious control ROM placement area 192, and by connecting to the terminals of the control ROM 105 from as far inside the control ROM placement area 192 as possible, the wiring pattern on the board can be arranged more efficiently, making better use of the limited space.

[0372] Furthermore, the wiring paths connecting vias v60~v108 (specific interlayer conductive parts) located within the control ROM placement area (second placement area) 192 to the terminal connection parts on the control ROM 105 side from outside the control ROM placement area 192, specifically wiring paths cp165, cp175, cp234, cp244, cp254, cp343, cp353, cp363, cp373, cp303, cp313, cp323, and cp333, are arranged to cross the long sides 192a and 192b of the control ROM placement area 192 outside each terminal connection part, as shown in Figure 35. By configuring it in this way, the wiring length can be shortened compared to wiring while avoiding the control ROM placement area 192, thereby increasing wiring efficiency and reducing noise. Furthermore, in the area indicated by the control ROM placement area 192, the control ROM 105 is actually located there, so the wiring pattern cannot be visually inspected, and thus it is possible to prevent unauthorized access to the wiring pattern.

[0373] Furthermore, the wiring paths connected to vias v60~v108 (specific interlayer conduction sections) located within the control ROM arrangement area (second arrangement area) 192, specifically wiring paths cp233, cp243, and cp253, via the first wiring layer La1, are also arranged so as shown in Figure 35 that they cross the long side 192a of the control ROM arrangement area 192 outside each terminal connection section. By implementing this configuration in multiple locations in conjunction with the configuration described above, the effects described above become even more effective.

[0374] Furthermore, a ROM socket 193 (Figure 8) is fixed to the control ROM placement area 192, and the bottom wall (shielding wall corresponding to the specific interlayer conductive portion) 193a of the ROM socket 193 shields the control ROM placement area 192. Therefore, even when the control ROM 105 is removed from the ROM socket 193, the wiring pattern within the control ROM placement area 192, including vias v60~v108 (specific interlayer conductive portions), cannot be seen from the outside, nor can it be accessed.

[0375] The vias v60 to v108 (specific interlayer conductive sections) within the control ROM placement area 192 penetrate from the front surface (first surface) 98a to the back surface (second surface) 98b of the main board body 190 to enhance heat dissipation. Furthermore, the vias v60 to v108 (specific interlayer conductive sections) within the control ROM placement area 192 are connected to predetermined electronic components such as ICs, resistors, capacitors, and connectors on the back surface 98b side, i.e., the sixth wiring layer La6 side.

[0376] Furthermore, the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105 branch off from a first wiring section connecting the composite chip 104 to a predetermined via (a predetermined interlayer conductive section), to a second wiring section connecting the predetermined via to the control ROM 105, and to a third wiring section connecting the predetermined via to other electronic components such as the liquid crystal control first connector CN31. The second wiring section is located on a first predetermined wiring layer such as the first wiring layer La1, and the third wiring section is located on a second predetermined wiring layer such as the third wiring layer La3, sixth wiring layer La6, etc., which are different from the first predetermined wiring layer.

[0377] Furthermore, of the wiring paths P2 to P45, the wiring paths P2 to P42 that transmit address / data information have predetermined vias (predetermined interlayer conduction sections) at branching points that are specific interlayer conduction sections (vias shown in gray in Figures 45 to 50) located within the control ROM placement area (second placement area) 192. Moreover, the second wiring section is provided on the first wiring layer La1, at least a part of the first wiring section is provided on the fourth wiring layer La4 (an example of a predetermined wiring layer other than the first wiring layer), and the third wiring section is provided on the first wiring layer La1 (first predetermined wiring layer). This makes it possible to enhance the preventability against cheating, such as illegally modifying the wiring patterns and vias that transmit address / data information. In addition, by drawing the wiring patterns within the control ROM placement area 192, it becomes possible to secure wiring space in other areas. Furthermore, particularly at branching points, wiring patterns tend to be densely packed across multiple layers of the circuit board. Therefore, sufficient wiring space is required in the areas where branching points are located. From this perspective, it is effective to place branching points within the control ROM placement area 192, which has ample wiring space.

[0378] Furthermore, among the vias v60 to v107 (specific interlayer conduction sections) in the control ROM arrangement area 192, vias v61 to v85 and v103 to v107 (first specific interlayer conduction section) which constitute part of the wiring path P2 to P26 (address wiring) for transmitting address information, and vias v87 to v102 (second specific interlayer conduction section) which constitute part of the wiring path P27 to P42 (data wiring) for transmitting data information, are arranged in the Y direction (first direction), which is the direction of terminal arrangement in the control ROM 105.

[0379] Furthermore, the address output terminals HAD1~HAD25 and data input / output terminals HDT0~HDT15 (first terminals) on the composite chip 104 side have a different arrangement from the corresponding address input terminals A0~A24 and data input / output terminals Q0~Q15 (second terminals) on the control ROM 105 side. The wiring paths P2~P42 connecting them have vias v60~v85 and v87~v107 (specific interlayer conduction sections) in the control ROM arrangement area 192, and the arrangement of these vias v60~v85 and v87~v107 (specific interlayer conduction sections) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals (specific second terminals) on the control ROM 105 side. This makes it possible to organize the wiring patterns connecting the specific interlayer conduction section and the terminals of the control ROM. For example, it is not necessary to route the patterns in such a way that the relative positions of multiple wiring patterns change (twist), making the connection method easier and allowing for more effective use of the space within the control ROM placement area 192. Thus, when the terminal arrangement of the composite chip 104 and the terminal arrangement of the control ROM 105 are different, it is more efficient in terms of wiring efficiency to approximate the arrangement of the specific interlayer conduction section to the terminal arrangement of the control ROM 105 by optimizing the routing of the wiring patterns with a relatively long wiring distance from the composite chip 104 to the specific interlayer conduction section, rather than optimizing the routing of the wiring patterns with a relatively short wiring distance from the specific interlayer conduction section within the placement area of ​​the control ROM 105 to the terminals of the control ROM 105.

[0380] Specifically, as shown in Figure 35, for example, address input terminals A0 to A6 and their corresponding vias v85 to v79, address input terminals A17 to A20 and their corresponding vias v68 to v64, and data input / output terminals Q12 to Q15 and their corresponding vias v90 to v87 are arranged in approximately the same order in the Y direction, while address input terminals A23, A22, A24, A16, A15 and their corresponding vias v62, v63, v61, v103, v104, data input / output terminals Q0 to Q3 and their corresponding vias v102 to v99, data input / output terminals Q8 to Q11 and their corresponding vias v94 to v91, and data input / output terminals Q4 to Q7 and their corresponding vias v98 to v95 are arranged in approximately the reverse order in the Y direction. Thus, instead of devising the arrangement of specific interlayer conductive sections by considering only the terminal arrangement of the control ROM 105, the terminal arrangement of the specific interlayer conductive sections may also be considered by considering the terminal arrangement of the composite chip 104 and the terminal arrangement of the LCD control first connector CN31, which are also connected. As a result, although the connection relationship with the control ROM 105 becomes partially more complex, the connection relationship with the composite chip 104 and the terminals of the LCD control first connector CN31, which are located further away from the terminals of the control ROM 105, is simplified using the specific interlayer conductive sections as a reference, thereby improving the overall wiring efficiency of the board. In other words, the overall wiring efficiency of the board can be improved by devising the arrangement of specific interlayer conductive sections as needed within the control ROM placement area 192. Furthermore, the overall wiring efficiency of the board can also be improved by devising the arrangement of vias that serve as branching points, not limited to the control ROM placement area 192, as described above.

[0381] Furthermore, the address output terminals HAD1~HAD25 and data input / output terminals HDT0~HDT15 (first terminals) on the composite chip 104 side have different arrangements not only with the corresponding address input terminals A0~A24 and data input / output terminals Q0~Q15 (second terminals) on the control ROM 105 side, but also with the terminals had1~had25 and hdt0~hdt15 (third terminals) of the liquid crystal control first connector CN31. The arrangement of vias v61~v85 and v87~v102 (specific interlayer conduction sections) is made to match (approximate) the arrangement of the terminals had1~had25 and hdt0~hdt15 (third terminals) of the liquid crystal control first connector CN31. In other words, as shown in Figures 37, 38, and 42, the Y-direction arrangement of vias v61~v85, v87~v102 (specific interlayer conductive sections) matches the X-direction arrangement of terminals had1~had25, hdt0~hdt15 of the liquid crystal control first connector CN31, allowing the wiring group connecting them (third wiring group) to be arranged in parallel without twisting. As a result, the wiring group connecting vias v61~v85, v87~v102 (specific interlayer conductive sections) and the address input terminals A0~A24 and data input / output terminals Q0~Q15 (second terminals) on the control ROM 105 side (second wiring group) will have a complex wiring pattern including twisting, but this can be easily realized by arranging it within the control ROM placement area 192, which has relatively ample space.

[0382] Of the wiring paths P2 to P42 used for transmitting address / data information, wiring paths P2 to P13 and P19 to P42 branch off to the control ROM 105 side and the liquid crystal control first connector CN31 side at vias v61 to v68, v74 to v85, v87 to v102 (specific interlayer conduction section) within the control ROM arrangement area 192. However, wiring paths P14 to P18 do not branch off to the control ROM 105 side at vias v69 to v73 within the control ROM arrangement area 192. Instead, vias v103 to v107 are provided separately within the control ROM arrangement area 192 on the wiring path connecting vias v69 to v73 and the liquid crystal control first connector CN31, and the wiring branches off to the control ROM 105 side from vias v103 to v107. By configuring it in this way, the wiring to the LCD control connector CN31 can be arranged in parallel without twisting, in harmony with other wiring paths, while the wiring to the control ROM 105 can also be efficiently arranged while avoiding interference with other wiring paths.

[0383] Furthermore, multiple one-end wiring paths P2~P9, P19, P20, P22, P23, P27~P30, P35~P38 connect specific one-end terminals A0~A7, A17, A18, A20, A21, Q0~Q3, Q8~Q11 included in the one-end terminals located on one end of the control ROM (second electronic component) 105 to the corresponding first specific terminals HAD0~HAD7, HAD17, HAD18, HAD20, HAD21, HDT0~HDT3, HDT8~HDT11 on the composite chip (first electronic component) 104 via vias v65~v68, v78~v85, v91~v94, v99~v102 (first interlayer conduction section), and specific other-end terminals included in the other-end terminals located on the other end of the control ROM (second electronic component) 105. The device comprises multiple other-end wiring paths P10~P18, P21, P24~P26, P31~P34, P39~P42, which connect side terminals A8~A16, A19, A22~A24, Q4~Q7, Q12~Q15 and the corresponding second specific terminals HAD8~HAD16, HAD19, HAD22~HAD24, HDT4~HDT7, HDT12~HDT15 on the composite chip (first electronic component) 104 side via vias v61~v63, v66, v74~v77, v87~v90, v95~v98 (second inter-layer conductive sections). The first inter-layer conductive sections and the second inter-layer conductive sections are arranged in a different arrangement from the first specific terminals and the second specific terminals, respectively, and are located close to each other so as to correspond to specific one-end terminals and specific other-end terminals.

[0384] Furthermore, for multiple ROM terminal connection sections arranged in a row, internal connection wiring sections connected from the inside of the control ROM arrangement area 192 and external connection wiring sections connected from the outside are arranged alternately. That is, as shown in Figure 35, the external connection wiring sections cp303, cp313, cp323, cp333 and the internal connection wiring sections cp383, cp393, cp403, cp413 are alternately connected to the terminal connection sections Q0, Q8, Q1, Q9, Q2, Q10, Q3, Q11 of the control ROM arrangement area 192. Moreover, the vias v102 to v99 on the other end of these external connection wiring sections cp303, cp313, cp323, cp333 are located close to each other, and the vias v94 to v91 on the other end of the internal connection wiring sections cp383, cp393, cp403, cp413 are also located close to each other. Similarly, the internal connection wiring sections cp453, cp443, cp433, cp423 and the external connection wiring sections cp373, cp363, cp353, cp343 are alternately connected to the terminal connection sections Q15 / A-1, Q7, Q14, Q6, Q13, Q5, Q12, and Q4 of the control ROM arrangement area 192. Furthermore, vias v87 to v90 on the other ends of these internal connection wiring sections cp453, cp443, cp433, cp423 are located close to each other, and vias v95 to v98 on the other ends of the external connection wiring sections cp373, cp363, cp353, cp343 are also located close to each other. In this way, by grouping the internal and external connection wiring sections in close proximity to each other, rather than by the terminal arrangement of the control ROM 105, the routing of the wiring pattern can be simplified and wiring efficiency can be improved.

[0385] Furthermore, the first wiring paths P2-P42, which transmit address information or data information, and the second wiring path P43, which transmits chip select information, are connected to different wiring layers. Specifically, the first wiring layers P2-P42 are connected to the fourth wiring layer La4, and the second wiring path P43 is connected to the sixth wiring layer La6, connecting from the composite chip 104 side to vias v61-v85, v87-v101, v60 (specific interlayer conduction sections) in the control ROM placement area 192. By routing the chip select signal, which is important for data transmission, using a different wiring layer than the wiring pattern that transmits address information or data information, transmission noise from the wiring pattern that transmits address information or data information is less likely to be transmitted to the chip select signal, making it possible to create a noise-resistant configuration. In addition, by making the pattern of the chip select signal wiring path different from other wiring paths, it becomes relatively easy to identify the wiring of the chip select signal, and it becomes relatively easy to check for tampering such as short-circuiting the wiring pattern and to perform power-on checks.

[0386] Furthermore, in the wiring path P45 that constitutes the reset circuit, there are wiring paths cp418~cp421 (first reset wiring path) connecting the reset integrated circuit (reset IC) IC10 and via v174 (predetermined interlayer conduction part), wiring paths cp413~cp415 (second reset wiring path) connecting via v174 (predetermined interlayer conduction part) and the reset terminal HRESET of the composite chip 104, and wiring paths cp416,cp417 (third reset wiring path) connecting via v174 (predetermined interlayer conduction part) and the reset terminal RESET# of the control ROM 105. The LCD control board 98 is equipped with the following: Test points TP17 (first test point) and TP23 (second test point) are placed on the wiring paths cp418~cp421 (first reset wiring path), penetrating the LCD control board 98 in the thickness direction. Identification information "TP17" and "TP23" indicating these test points TP17 and TP23 are displayed on the front side, i.e., the surface (first surface) 98a opposite to the other display interface boards 96 and 97, when the LCD control board 98 is assembled together with other display interface boards 96 and LCD interface boards 97. The reset integrated circuit (reset IC) IC10 is placed on the back side (second surface) 98b. As a result, even though the wiring paths where test points TP17 and TP23 are located are not visible when the board is assembled (see Figures 8 and 9) or when the board is installed in the gaming machine body, it is possible to easily perform checks using test points TP17 and TP23 based on the identification information displayed on the visible surface 98a.

[0387] Furthermore, the wiring paths cp418~cp421 (first reset wiring path) consist of wiring path cp418 (first wiring path) located on the front (first surface) 98a side, wiring paths cp420 and cp421 (second wiring paths) located on the back (second surface) 98b side, and via v204 (first reset interlayer conduction section) connecting them. Test point TP17 (first test point) is located on via v204, and test point TP23 (second test point) is located on wiring path cp421 (second wiring path).

[0388] Furthermore, the control ROM (specific electronic component) 105 operates in an operating mode corresponding to the voltage level of the write-protected / program input terminal WP# / ACC (second predetermined terminal), the writeable input terminal WE# (first predetermined terminal) is connected to the power supply wiring of the fifth wiring layer La5 via via v111 (first predetermined interlayer conduction section), and the write-protected / program input terminal WP# / ACC (second predetermined terminal) is connected to via v111 (first predetermined interlayer conduction section) via resistor R43. In addition, the control ROM (specific electronic component) 105 is located on the front surface (first surface) 98a of the liquid crystal control board 98, and the resistor R43 is located on the back surface (second surface) 98b, with the write-protected / program input terminal WP# / ACC (second predetermined terminal) and resistor R43 connected via via v112 (second predetermined interlayer conduction section). In this way, by using the via that connects WP# / ACC (second predetermined terminal) to the power supply wiring circuit via resistor R43 as a common via for connecting WE# (first predetermined terminal) to the power supply wiring circuit, the number of vias can be reduced compared to connecting them individually via vias.

[0389] Furthermore, multiple terminals are arranged in a matrix on the bottom side of the composite chip 104. Of these multiple terminals, the outer terminals located near the outer edge of the composite chip placement area (first placement area) 191, such as terminals HDT0, HDT1, HDT4, HDT5, etc., located on the outermost edge and the second row inside it, are connected to the control ROM 105 by first wiring paths P27, P28, P31, P32, etc., while the inner terminals located inside the outer terminals, such as terminals HDT2, HDT3, HDT6, etc., are connected to second wiring paths P29, P30, P33, etc. These are connected to the control ROM 105. The first wiring paths P27, P28, P31, P32, etc. connect vias v32, v31, v37, v46, etc. (first interlayer conduction section) located outside the composite chip placement area 191 to the outer terminals HDT0, HDT1, HDT4, HDT5, etc. via the first wiring layer La1. The second wiring paths P29, P30, P33, etc. connect vias v24, v8, v17, etc. (second interlayer conduction section) located inside the composite chip placement area 191 to the inner terminals HDT2, HDT3, HDT6, etc. via the first wiring layer La1. Furthermore, the distance from the inner terminals HDT2, HDT3, HDT6, etc. to vias v24, v8, v17, etc. (inter-layer conduction section) is shorter than the distance from the outer terminals HDT0, HDT1, HDT4, HDT5, etc. to vias v32, v31, v37, v46, etc. (inter-layer conduction section).

[0390] Thus, in a composite chip 104 with multiple terminals arranged in a matrix, the outer terminals located near the outer edge of the composite chip 104's placement area are connected to vias located on the outside of the composite chip 104. This creates wiring space near the outer edge of the composite chip 104, making it easier to route the wiring patterns of the inner terminals of the composite chip 104 outwards, thereby improving wiring efficiency. Furthermore, regarding the aforementioned wiring space, since wiring space is created near the outer edge of the composite chip in multiple wiring layers of the substrate, it goes without saying that it becomes easier to route wiring patterns to the outside of the composite chip regardless of which of the multiple wiring layers is used.

[0391] Furthermore, the wiring paths (first wiring paths) P52-P61 that transmit the ODD signal (first signal) corresponding to odd-numbered pixels are arranged such that the wiring ratio to the first wiring layer (layout A) La1 is the highest among the multiple wiring layers La1-La6, and the wiring paths (second signal) that transmit the EVEN signal (second signal) corresponding to even-numbered pixels are arranged such that the wiring ratio to the sixth wiring layer (layout B) La6 is the highest among the multiple wiring layers La1-La6.

[0392] In other words, the ODD-side data output terminal group (first chip terminals) to which the wiring path (first wiring path) P52~P61 is connected is located on the outer edge of the composite chip 104 than the EVEN-side data output terminal group (second chip terminals) to which the wiring path (second wiring path) P62~P71 is connected, and the liquid crystal control second connector CN32 is located on the Lb6 side of the sixth wiring layer (second wiring layer) opposite to the composite chip 104. Furthermore, the wiring paths (first wiring paths) P52~P61 connected to the ODD-side data output terminal group (first chip terminals) are connected to the second LCD control connector CN32 via vias (specific interlayer conductive parts) v251~v260 located near the LCD control second connector CN32, and the EVEN-side data output terminal group (second chip terminals) connected to the EVEN-side data output terminal group (second chip terminals) are connected to the second LCD control connector CN32 via vias (non-specific interlayer conductive parts) v261~v270 located near the EVEN-side data output terminal group. With this configuration, it is possible to reduce the possibility of simultaneous disconnections or noise-related malfunctions occurring in the wiring paths (first wiring paths) P52~P61 that transmit the ODD signal (first signal) and the wiring paths (second wiring paths) P62~P7 that transmit the EVEN signal (second signal), thereby distributing the risk.

[0393] Furthermore, the liquid crystal control second connector CN32 is located on the second edge (first side) 191b side of the composite chip 104. Wiring paths (Type A wiring paths) P52 to P71, which can transmit image data signals to the liquid crystal display means 76, are drawn out from the second edge (first side) 191b side of the composite chip 104 and connected to the first connector terminal of the liquid crystal control second connector CN32. Wiring paths (Type B wiring paths) P50 and P51, which can transmit control signals related to the backlight, are drawn out from the first edge (second side) 191a side of the composite chip 104 and connected to the second connector terminal of the liquid crystal control second connector CN32. This allows for efficient wiring by shortening the wiring length of wiring paths (Type A wiring paths) P52 to P71 and separating wiring paths (Type B wiring paths) P50 and P51.

[0394] Next, the details of the wiring pattern and other aspects of the liquid crystal interface substrate 97 will be explained. The liquid crystal interface substrate 97 has a total of six wiring layers, consisting of a first wiring layer Lb1 on the surface (first side) 97a side, a sixth wiring layer Lb6 on the back side (second side) 97b side, and second to fifth wiring layers Lb2 to Lb5 arranged between them, totaling six layers of first to sixth wiring layers Lb1 to Lb6 (Figures 57 to 61). The second and fifth wiring layers Lb2 and Lb5 (Figure 58) are solid wiring layers connected to ground, and the fourth wiring layer Lb4 (Figure 60) is a solid wiring layer connected to the power supply. In addition, the substrate body 220 of the liquid crystal interface substrate 97 is provided with many through-hole type vias (interlayer conductive parts), and the multiple wiring layers Lb1 to Lb6 are electrically connected to each other through these vias (interlayer conductive parts).

[0395] In the following explanation, the in-plane direction and orientation of each wiring layer Lb1 to Lb6 are based on the same XY coordinate system as the liquid crystal control substrate 98 (see Figure 8). In Figures 57 to 61, the up-down direction is the X direction, and the left-right direction is the Y direction. Upward / downward directions are the +X / -X directions (sides), and leftward / rightward directions are the +Y / -Y directions (sides), respectively.

[0396] As shown in Figure 57, the first wiring layer Lb1 of the liquid crystal interface substrate 97 is provided with liquid crystal IF first to third connector placement areas 221 to 223 where liquid crystal IF first to third connectors CN21 to CN23 are arranged, and liquid crystal connection first and second connector placement areas 224 and 225 where liquid crystal connection first and second connectors CN24 and CN25 are arranged.

[0397] The liquid crystal interface (LCD) first connector placement area 221 is elongated in the X direction and is located on the +X side near the +Y edge of the first wiring layer Lb1. The liquid crystal interface (LCD) second connector placement area 222 is elongated in the X direction and is located on the -X side near the +Y edge of the first wiring layer Lb1. The liquid crystal interface (LCD) third connector placement area 223 is elongated in the X direction and is located slightly to the +X and -Y side of the center of the first wiring layer Lb1. The liquid crystal connection first and second connectors CN24 and CN25 are both elongated in the Y direction and are located adjacent to each other near the -Y side of the first wiring layer Lb1, closer to the -Y side, with the -Y side becoming the liquid crystal connection second connector CN25.

[0398] The following describes, with reference to the drawings, the details of several types of wiring paths P101 to P124, which are connected to the liquid crystal display means 76 via the first and second liquid crystal connection connectors CN24 and CN25, from among the numerous wiring paths provided on the liquid crystal interface board 97. Figures 62 to 66 show only the portions that constitute wiring paths P101 to P124, extracted from the wiring patterns of the first to sixth wiring layers Lb1 to Lb6 shown in Figures 57 to 61, and Figures 67 to 72 are enlarged views of these portions. Figures 73 to 75 schematically show the wiring paths of wiring paths P101 to P124, and Figures 76 to 78 show circuit diagrams corresponding to wiring paths P101 to P124.

[0399] First, we will explain the wiring paths P101 to P110 that constitute the first transmission path LVDS1 for transmitting the ODD signal. Wiring paths P101 to P110 are arranged to connect the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ on the LCD IF third connector CN23 to the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ on the LCD connection first connector CN24.

[0400] As shown in Figure 62, the LCD IF third connector CN23 is arranged in an elongated shape in the X direction, with numerous terminals arranged along its pair of long sides. As shown in Figure 67, the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ are arranged in the X direction along the long side of the Y side in that order. Note that terminals ra0- and ra0+, ra1- and ra1+, ra2- and ra2+, raclk- and raclk+, and ra3- and ra3+ are each placed next to each other, and a predetermined number of GND terminals (one in this case) are placed between each of these five pairs (omitted in Figure 67).

[0401] Furthermore, the first LCD connector CN24 is elongated in the Y direction, as shown in Figure 62, and is positioned on the -X side relative to the third LCD IF connector CN23. Numerous terminals are arranged along its long side on the +X side, and as shown in Figure 69, the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ are arranged in the +Y direction in that order.

[0402] In wiring paths P101 to P110 (Figure 73), as shown in Figure 67, in the first wiring layer Lb1, wiring paths cp701 to cp710 are drawn out in the -Y direction from terminal connection points ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ on the liquid crystal IF third connector placement area 223 side, respectively. Then, these wiring paths cp701 to cp710 change direction toward the liquid crystal connection first connector CN24 side (-X side), and as shown in Figures 68 and 69, they are connected to terminal connection points ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ on the liquid crystal connection first connector CN24 side via test points TP101 to TP110.

[0403] Thus, in wiring paths P101 to P110, the terminal arrangement on the LCD IF third connector CN23 side and the terminal arrangement on the LCD connection first connector CN24 side are aligned facing each other, making it possible to arrange the wiring without twisting using only the first wiring layer Lb1 without switching wiring layers.

[0404] The wiring paths cp701 and cp702, cp703 and cp704, cp705 and cp706, cp707 and cp708, and cp709 and cp710 are parallel to each other, maintaining approximately constant intervals, and ground patterns are placed between each of these five sets of wiring paths. Furthermore, these five sets of wiring paths are equipped with meandering sections of varying lengths to equalize the wiring length. Test points TP101 to TP110 have a diameter larger than the minimum interval between each wiring path, so they are positioned with their axes offset from each of the wiring paths cp701 to cp710, widening the spacing between them. In addition, five sets of adjacent test points are positioned alternately in the X direction, offset from each other, to avoid interference.

[0405] Furthermore, wiring paths P101 to P110 branch off from wiring paths cp701 to cp710 at test points TP101 to TP110 and are connected to ground (second wiring layer Lb2) via protection diodes located on the sixth wiring layer Lb6 side. Specifically, wiring paths P101 and P102 are connected to protection diode D103, wiring paths P103 and P104 are connected to protection diode D105, wiring paths P105 and P106 are connected to protection diode D102, wiring paths P107 and P108 are connected to protection diode D104, and wiring paths P109 and P110 are connected to protection diode D101.

[0406] Next, we will explain the wiring paths P111 to P120 that constitute the second transmission path LVDS2 for transmitting the EVEN signal. Note that wiring paths P111 to P120 are arranged to connect the EVEN side terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ on the LCD IF third connector CN23 to the EVEN side terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ on the LCD connection first connector CN24.

[0407] The arrangement of the EVEN-side terminals in the LCD IF third connector CN23 is reversed in terms of + / - compared to the arrangement of the ODD-side terminals. That is, as shown in Figure 67, the EVEN-side terminals in the LCD IF third connector CN23 are arranged in the -X direction along the long side of the +Y side in the order of rb0+, rb0-, rb1+, rb1-, rb2+, rb2-, rbclk+, rbclk-, rb3+, rb3-. Note that terminals rb0+ and rb0-, rb1+ and rb1-, rb2+ and rb2-, rbclk+ and rbclk-, and rb3+ and rb3- are each placed next to each other, but a predetermined number of GND terminals (one in this case) are placed between each of these five pairs (omitted in Figure 67).

[0408] On the other hand, the arrangement of the EVEN side terminals in the LCD connection connector CN24 is the same as the arrangement of the ODD side terminals. That is, as shown in Figure 69, the EVEN side terminals in the LCD IF third connector CN23 are arranged in the +Y direction in the order of rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ on the +Y side of the ODD side terminals.

[0409] Comparing the EVEN terminal on the LCD IF third connector CN23 (Figure 67) and the EVEN terminal on the LCD connection first connector CN24 (Figure 69) side-by-side, we find that the arrangement of the five sets of terminal pairs, rb0, rb1, rb2, rbclk, and rb3, is reversed. Therefore, the wiring paths connecting them will be twisted, and unlike the wiring paths on the ODD side, the wiring must span multiple wiring layers.

[0410] In wiring paths P111~P120 (Figure 74), as shown in Figure 67, in the first wiring layer Lb1, wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 are drawn out in the +Y direction from terminal connection parts rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, and rb3+ on the liquid crystal IF third connector placement area 223 side. Then, these wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 change direction toward the liquid crystal connection first connector CN24 side (-X side) and are connected to vias v301~v310.

[0411] The wiring paths cp711 and cp714, cp717 and cp720, cp723 and cp726, cp729 and cp732, and cp735 and cp738 run parallel to each other at approximately constant intervals, and ground patterns are provided between each of these five sets of wiring paths.

[0412] Here, v301 to v310 correspond to five sets of terminal pairs, rb0, rb1, rb2, rbclk, and rb3, and are arranged in pairs adjacent to each other in the X direction. Furthermore, the five pairs of vias are arranged with a staggered position in the X direction such that vias v301 and v302, which correspond to the +Y-side wiring paths cp711 and cp714, are on the -X side, and vias v309 and v310, which correspond to the -Y-side wiring paths cp735 and cp738, are on the +Y side.

[0413] Furthermore, for vias v303 to v310 corresponding to wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738, vias v303 to v310 on the -signal side are positioned to be on the -X side relative to vias v304, v306, v308, and v310 on the +signal side, and wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 are connected from the -Y side, while for vias v301 and v302 corresponding to wiring paths cp711 and cp714, via v301 on the -signal side is positioned to be on the +X side relative to via v302 on the +signal side, and wiring paths cp711 and cp714 are connected from the +Y side.

[0414] Furthermore, v301 to v310 are connected to the wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 on the Lb6 side of the sixth wiring layer, as shown in Figure 70. These wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 are then reoriented toward the LCD connection first connector CN24 side (-X side) so that the wiring paths cp712 and cp715, corresponding to the vias v301 and v302 on the furthest -X side, are on the furthest -Y side, and the wiring paths cp736 and cp739, corresponding to the vias v309 and v310 on the furthest +X side, are on the furthest +Y side, before being connected to the test points TP111 to TP120. As a result, the order of the wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, cp739 on the sixth wiring layer Lb6 side is changed from the order of the wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, cp738 on the first wiring layer Lb1 side, and matches the arrangement of the EVEN side terminals in the LCD connection first connector CN24.

[0415] Note that cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 are led out in the +Y direction to vias v303 to v310, while cp712 and cp715 are led out in the -Y direction to vias v301 and v302. Therefore, there is no change in the arrangement of + / - wiring paths between the first wiring layer Lb1 side and the sixth wiring layer Lb6 side.

[0416] Test points TP111 to TP120 have a diameter larger than the minimum spacing between each wiring path. Therefore, similar to test points TP101 to TP110, they are positioned with their axes offset from each wiring path cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739, and with wider spacing between them. Furthermore, five pairs of adjacent test points are positioned alternately in the X direction to avoid interference with each other.

[0417] Furthermore, as shown in Figure 69, test points TP111 to TP120 are connected to terminal connections rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ on the liquid crystal connection first connector CN24 side via wiring paths cp713, cp716, cp719, cp722, cp725, cp728, cp731, cp734, cp737, and cp740 on the first wiring layer Lb1 side.

[0418] Furthermore, the wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 on the sixth wiring layer Lb6 side are connected to ground (second wiring layer Lb2) via protection diodes D110, D111, D112, D108, and D109 from test points TP111 to TP120, respectively. That is, as shown in Figure 70, wiring paths cp712 and cp715 are connected to protection diode D110, wiring paths cp718 and cp721 are connected to protection diode D111, wiring paths cp724 and cp727 are connected to protection diode D112, wiring paths cp730 and cp733 are connected to protection diode D108, and wiring paths cp736 and cp739 are connected t...

Claims

[Claim 1] A symbol display means capable of displaying symbols in a variable manner based on random number information obtained when the symbol activation conditions are met, A holding storage means that holds and stores the aforementioned random number information up to a predetermined upper limit until it is used for pattern variation by the pattern display means, A profit state generating means that generates a profit state when the stopped symbols after the change in the symbol display means become a specific pattern, It comprises a display control means for controlling the display of a liquid crystal display means, The liquid crystal display means is capable of displaying a number of reserved notification images corresponding to the number of random number information stored in the reserved storage means. In gaming machines, The display control means is configured to output odd-numbered image data corresponding to odd-numbered pixels and even-numbered image data corresponding to even-numbered pixels horizontally adjacent to the odd-numbered pixels to the liquid crystal display means via different wiring paths. A first substrate on which the display control means is mounted and on which a first signal line for transmitting the odd-numbered image data and the even-numbered image data to the liquid crystal display means is formed, A second circuit board is provided on which a second signal line for transmitting the odd-numbered image data and the even-numbered image data is formed, and an output connector for outputting the odd-numbered image data and the even-numbered image data to the liquid crystal display means is mounted. The system includes a connection connector that connects the first signal line of the first board and the second signal line of the second board, The second signal line is composed of multiple wiring paths. Each of the aforementioned multiple wiring paths is connected to a protection circuit and / or a test point. In order to equalize the wiring lengths upstream of the protection circuit and / or test point in the plurality of wiring paths, adjustment sections of different lengths are provided in the plurality of wiring paths. By performing a dynamic display with vertical changes on the pending notification image, the system is configured to make the dynamic display of the pending notification image easily identifiable even if either the odd-numbered image data or the even-numbered image data is missing. A gaming machine characterized by the following features.

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