Photoelectric converter, photoelectric conversion system

Abstract

To provide a photoelectric conversion device with better characteristics.SOLUTION: A photoelectric conversion device includes a first substrate having a photoelectric conversion portion and a transfer transistor in a first semiconductor layer, a second substrate having a pixel circuit in a second semiconductor layer, and a third substrate with a logic circuit in a third semiconductor layer. The first substrate and the second substrate are electrically connected by a through wiring that penetrates the second semiconductor layer. The plane orientation of the first semiconductor layer and the plane orientation of the second semiconductor layer are the same.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] In order to realize further higher density of pixels included in a photoelectric conversion device, Patent Document 1 describes an example in which a photoelectric conversion portion is provided in a first semiconductor layer and a pixel circuit is provided in a second semiconductor layer. Patent Document 1 describes that the first semiconductor layer and the second semiconductor layer are stacked face-to-back to form a stacked body. Further, Patent Document 1 describes that a third semiconductor layer having a logic circuit is stacked on the stacked body.

Related Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] However, Patent Document 1 does not discuss how to configure the plane orientation of the silicon substrates constituting the first to third semiconductor layers.

[0005] Accordingly, the present invention has an object to provide a photoelectric conversion device with further improved characteristics compared to the configuration of Patent Document 1.

Means for Solving the Problem

[0006] The photoelectric conversion device according to the present invention comprises: a first substrate having a photoelectric conversion element and a transfer transistor for transferring charge generated in the photoelectric conversion element on a first semiconductor layer; a second substrate having a pixel circuit for outputting a signal based on the charge transferred from the transfer transistor on a second semiconductor layer; and a third substrate having a logic circuit for processing the signal on a third semiconductor layer. The first substrate, the second substrate, and the third substrate are stacked such that the second substrate is provided between the first substrate and the third substrate, the first substrate and the second substrate are electrically connected by through-wiring that penetrates the second semiconductor layer, and the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are the same. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a photoelectric conversion device with improved characteristics compared to the configuration of Patent Document 1. [Brief explanation of the drawing]

[0008] [Figure 1] Equivalent circuit diagram of a pixel according to the first embodiment [Figure 2] Pixel cross-sectional view according to the first embodiment [Figure 3] Plan view of the pixel circuit board according to the first embodiment [Figure 4] Equivalent circuit diagram of another pixel according to the first embodiment [Figure 5] Another pixel cross-sectional view according to the first embodiment [Figure 6] Plan view of another pixel circuit board according to the first embodiment [Figure 7] Cross-sectional view and explanatory diagram of the photoelectric converter according to the first embodiment. [Figure 8] Plan view of the photoelectric conversion unit substrate and pixel circuit board according to the first embodiment [Figure 9] Plan view of the photoelectric conversion unit substrate, pixel circuit board, and logic board according to the first embodiment [Figure 10] Plan view of the photoelectric conversion unit substrate and pixel circuit board according to the second embodiment [Figure 11]Cross-sectional view and explanatory diagram of the photoelectric converter according to the second embodiment. [Figure 12] According to the third embodiment [Figure 13] Cross-sectional view and explanatory diagram of the photoelectric converter according to the third embodiment. [Figure 14] Diagram showing the configuration of the equipment according to the fourth embodiment. [Modes for carrying out the invention]

[0009] The embodiments shown below are intended to embody the technical concept of the present invention and do not limit it. The size and positional relationships of the components shown in each drawing may be exaggerated for clarity of explanation. In the following description, identical components may be given the same number and their explanation may be omitted. Furthermore, the components described in each embodiment can be substituted or combined with the components described in other embodiments, unless there are technical problems.

[0010] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "up," "down," "right," "left," and other terms including these terms) will be used as needed. The use of these terms is to facilitate understanding of the invention with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention. In other words, even a configuration inverted vertically falls within the technical scope of the present invention.

[0011] In the following explanation, we will use type N as the first conductivity type and type P as the second conductivity type, but this relationship can also be reversed.

[0012] (First Embodiment) Figure 1 shows an equivalent circuit diagram of the photoelectric conversion unit and pixel circuit according to this embodiment. That is, it is an equivalent circuit diagram of one pixel. Here, an example of one pixel is shown, but the photoelectric conversion device has a pixel region in which multiple pixels are arranged in a matrix.

[0013] The photoelectric conversion unit (photodiode) 101 and the transfer transistor 111 are provided on the first substrate 100.

[0014] The photoelectric conversion unit 101 generates electric charges upon incidence of light. The transfer transistor 111 is a transistor that transfers the electric charges generated in the photoelectric conversion unit 101.

[0015] The cathode of the photoelectric conversion unit 101 is electrically connected to the source of the transfer transistor 111, and the anode of the photoelectric conversion unit 101 is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor 111 is electrically connected to the floating diffusion 121, and the gate of the transfer transistor 111 is electrically connected to a pixel drive line (not shown).

[0016] The electric charges output from the photoelectric conversion unit 101 via the transfer transistor 111 are temporarily held in the floating diffusion 121.

[0017] The pixel circuit 211 includes, for example, a reset transistor 131, a selection transistor 151, and an amplification transistor 141. The pixel circuit 211 is provided on the second substrate 200.

[0018] The gate of the reset transistor 131 is electrically connected to a pixel drive line (not shown). The source of the amplification transistor 141 is electrically connected to the drain of the selection transistor 151, and the gate of the amplification transistor 141 is electrically connected to the source of the reset transistor 131. The source of the selection transistor 151 (the output terminal of the pixel circuit 211) is electrically connected to the output line 161, and the gate of the selection transistor 151 is electrically connected to a pixel drive line (not shown).

[0019] When the transfer transistor 111 is turned ON, it transfers the charge from the photodiode 101 to the floating diffusion 121. The gate (transfer gate) of the transfer transistor 111 is positioned on the surface of the semiconductor layer, as explained in Figure 2. Alternatively, it may extend from the surface of the semiconductor layer to a depth that reaches the photoelectric conversion unit 101. In other words, it may be in the form of a vertical transfer gate.

[0020] The reset transistor 131 resets the potential of the floating diffusion 121 to a predetermined potential. When the reset transistor 131 is turned on, it resets the potential of the floating diffusion 121 to the potential of the power line VDD.

[0021] The selection transistor 151 controls the output timing of the pixel signal from the pixel circuit 211. The selection transistor 151 may be omitted if necessary. The source of the reset transistor 131 (the input terminal of the pixel circuit 211) is electrically connected to the floating diffusion 121, and the drain of the reset transistor 131 is electrically connected to the power line VDD and the drain of the amplification transistor 141.

[0022] The amplification transistor 141 generates a pixel signal with a voltage corresponding to the level of charge held in the floating diffusion 121. The amplification transistor 141 constitutes a source follower type amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated in the photoelectric conversion unit 101. When the selection transistor 151 is turned ON, the amplification transistor 141 amplifies the potential of the floating diffusion 121 and outputs a voltage corresponding to that potential to the column circuit (not shown) via the output line 161.

[0023] A selection transistor 151 may be provided between the power line VDD and the amplification transistor 141. In this case, the drain of the reset transistor 131 is electrically connected to the power line VDD and the drain of the selection transistor 151. The source of the selection transistor 151 is electrically connected to the drain of the amplification transistor 141, and the gate of the selection transistor 151 is electrically connected to the pixel drive line (not shown). The source of the amplification transistor 141 is electrically connected to the output line 161, and the gate of the amplification transistor 141 is electrically connected to the source of the reset transistor 131. A transistor FDG may be provided between the source of the reset transistor 131 and the gate of the amplification transistor 141. The transistor FDG is used to switch the conversion efficiency. Generally, the pixel signal is small when shooting in dark places. When performing charge-to-voltage conversion based on Q=CV, if the capacitance of the floating diffusion 121 (FD capacitance C) is large, the V when converted to voltage by the amplification transistor 121 will be small. On the other hand, in bright conditions, the pixel signal becomes larger, so if the FD capacitance C is not large enough, the floating diffusion 121 cannot handle the charge from the photoelectric conversion unit 101. Furthermore, the FD capacitance C needs to be large so that the V obtained when the signal is converted to voltage by the amplification transistor 141 does not become too large (in other words, to keep it small). Considering these factors, when transistor FDG is turned on, the gate capacitance of transistor FDG increases, so the overall FD capacitance C becomes larger. Conversely, when transistor FDG is turned off, the overall FD capacitance C becomes smaller. In this way, by switching transistor FDG on and off, the FD capacitance C can be varied, and the conversion efficiency can be switched.

[0024] Figure 2 is a cross-sectional view of a pixel according to this embodiment. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. In other words, it is a photoelectric converter in which the second substrate is stacked between the first substrate 100 and the third substrate 300.

[0025] The first substrate 100 has a first semiconductor layer 100a, a first wiring layer 100b, and a component 100c. The second substrate 200 has a pixel circuit provided on the surface side (third substrate 300 side) of the second semiconductor layer 200a. The second substrate 200 is bonded to the first substrate 100 with the back side of the second semiconductor layer 200a facing the surface side of the first semiconductor layer 100a. In other words, the second substrate 200 is bonded to the first substrate 100 face to face.

[0026] The second substrate 200 has a second semiconductor layer 200a and a second wiring layer 200b. The second wiring layer 200b has multiple insulating layers 165 and a conductive layer 166 provided between the multiple insulating layers 165. In Figure 2, reference numeral 166 is used to indicate a portion of the conductive layer in the wiring layer of M2 (second layer), but a conductive layer is also provided in the wiring layer of M1 (first layer).

[0027] The third substrate 300 has a third semiconductor layer 300a and a third wiring layer 300b. Similarly, the third wiring layer 300b is provided with multiple insulating layers and multiple conductive layers. The top layer of the second wiring layer 200b (bottom layer in Figure 2) and the top layer of the third wiring layer 300b (top layer in Figure 2) are provided with an insulating film 165 and a conductive layer 167, respectively. The conductive layer provided on the top layer is also called a pad layer or pad electrode. Electrical conductivity between the second wiring layer 200b and the third wiring layer 300b is ensured by bonding these insulating films to each other and conductive layers to each other. In other words, the second substrate 200 and the third substrate 300 are bonded face to face by hybrid bonding.

[0028] Each semiconductor layer is made of, for example, single-crystal silicon. The insulating layer is made of, for example, SiO (silicon oxide). The insulating layer may also have layers of SiC (silicon carbide) or SiN (silicon nitride) to suppress metal diffusion from the conductive layer. The conductive layer is made of a metal such as Cu (copper) or Al (aluminum). In particular, the top conductive layer in the hybrid junction is made of Cu (copper).

[0029] A barrier layer with diffusion-preventing properties is appropriately provided around these metals.

[0030] (First substrate: Photoelectric conversion unit substrate) The first substrate 100 has a photoelectric conversion unit 101 on the first semiconductor layer 11. More precisely, the first semiconductor region of the first conductivity type, which is part of the photodiode that is the photoelectric conversion unit 101, is indicated by reference numeral 101. The first semiconductor region is, for example, an N-type semiconductor region and functions as the cathode of the photodiode that is the photoelectric conversion unit 101. Around the first semiconductor region are a second semiconductor region 211 of the second conductivity type (for example, a P-type semiconductor region) and a third semiconductor region 221 of the second conductivity type (for example, a P-type semiconductor region). The second semiconductor region 211 of the second conductivity type (for example, a P-type semiconductor region) is a region provided to separate each pixel. A reference potential (for example, ground) is supplied to the second semiconductor region 211 and it functions as the anode of the photodiode that is the photoelectric conversion unit 101. Although not shown in Figure 2, the second semiconductor region 211 is electrically connected by through wiring and is configured to supply the reference potential.

[0031] (Second board: Pixel circuit board) A pixel isolation portion 211 is provided in the second semiconductor region 211 of the second substrate 200. The pixel isolation portion 211 is a DTI (Deep Trench Isolation) provided so as to penetrate the first semiconductor layer 100a. The DTI is formed by filling the opening that penetrates the first semiconductor layer 100a with an insulating film, metal, or the like.

[0032] The component 100c includes a pinning layer 231, a planarization film 241, and a microlens 251. Specifically, the pinning layer 231 is provided on the back side of the first semiconductor layer 100a. The pinning layer 231 is, for example, a negative fixed charge film, specifically hafnium oxide, zircon oxide, aluminum oxide, titanium oxide, or tantalum oxide. The negative fixed charge film excites holes on the back side of the first semiconductor layer 100a, and even if dark electrons are generated, the holes and electrons can be recombined, eliminating electrons that contribute to noise signals. It is also possible to provide a color filter (not shown) between the pinning layer 231 and the microlens 251.

[0033] A through-wiring (not shown) is electrically connected to the gate 112 of the transfer transistor 111, and a predetermined voltage is applied. This transfers the charge accumulated in the first semiconductor region to the floating diffusion 121. A through-wiring 260 is connected to the floating diffusion 121. The through-wiring 260 is electrically connected to the gate 142 of the amplification transistor 141. More specifically, the through-wiring 260 is a contact electrode configured to penetrate the interlayer insulating film constituting the first wiring layer 100b, the insulator 250 of the second semiconductor layer 200a, and the interlayer insulating film of the second wiring layer 200b. The insulator 250 is constructed by forming an opening in a part of the second semiconductor layer 200a and filling it with an insulating film. For example, the insulator 250 is an STI (Shallow Trench Isolation). In Figure 2, the through-wiring 260 is electrically connected to the gate 142 of the amplification transistor 141 via contact electrodes and the second wiring layer M1. The through-wiring 260 is provided for each pixel.

[0034] (Third board: Logic board) A transistor 261 of the logic circuit is provided on the third semiconductor layer 300a of the third substrate 300. The transistor 261 of the logic circuit constitutes part of a circuit that processes the output signal from the pixel circuit 211 provided on the second substrate 200. The logic circuit includes, for example, a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, and a system control circuit. The logic circuit (specifically the horizontal drive circuit) outputs an output voltage Vout for each pixel to the outside. In the logic circuit, for example, a low-resistance region made of silicide may be formed on the surface of the impurity diffusion region in contact with the source and drain. Specifically, the silicide is formed using a salicide (Self-Aligned Silicide) process such as CoSi or NiSi.

[0035] The vertical drive circuit, for example, sequentially selects multiple pixels row by row. The column signal processing circuit, for example, applies correlated double sampling (CDS) to the pixel signals output from each pixel in the row selected by the vertical drive circuit. The column signal processing circuit, for example, extracts the signal level of the pixel signals by applying CDS processing and holds pixel data corresponding to the amount of light received by each pixel. The horizontal drive circuit, for example, sequentially outputs the pixel data held by the column signal processing circuit to the outside. The system control circuit, for example, controls the driving of each block in the logic circuit (vertical drive circuit, column signal processing circuit, and horizontal drive circuit).

[0036] Figure 3(A) is a plan view showing the first semiconductor layer 100a and the first wiring layer 100b. Such a plan view is sometimes called a plan view. Figure 3(B) is a plan view showing a portion of the second semiconductor layer 200a and the second wiring layer 200b.

[0037] A through-wiring 260 is provided on the floating diffusion 121 shown in Figure 3(A). As shown in Figure 3(B), the through-wiring 260 is configured to penetrate the insulator 250 of the second semiconductor layer 200a. Although not shown in Figure 3(B), the through-wiring 260 has a wiring structure that electrically connects to the gate of the amplifying transistor 141.

[0038] (Pixel sharing) Figure 4 shows an equivalent circuit diagram for four pixels. It illustrates an example where the floating diffusion 121s of multiple photoelectric conversion units 101 are electrically connected to each other and also electrically connected to the input terminal of a common pixel circuit 211. In Figure 4, subscripts a through d are assigned to each code to distinguish the photoelectric conversion unit 101 etc. corresponding to each pixel. By providing one pixel circuit 211 for multiple photoelectric conversion units 101 in this way, there is an advantage in that the area occupied by the pixel circuit 211 in the entire photoelectric conversion device can be reduced.

[0039] Figure 5 is a pixel cross-sectional view corresponding to the equivalent circuit diagram shown in Figure 4. In Figure 5, the cross-sectional view of two of the four pixels is shown.

[0040] A through-wiring 260 is connected to the floating diffusion 121 of the first pixel 410 and the floating diffusion 121 of the second pixel. These two through-wirings 260 are electrically connected to the gate 142 of the amplification transistor 141 via a conductive layer provided in M1 (the first layer) of the second wiring layer 200b.

[0041] Figure 6 is a plan view corresponding to the equivalent circuit diagram shown in Figure 4. Figure 6(A) is a plan view showing the first semiconductor layer 100a and the first wiring layer 100b. Figure 6(B) is a plan view showing a portion of the second semiconductor layer 200a and the second wiring layer 200b. As shown in Figure 6(A), the floating diffusions 221 of the four pixels are arranged to converge in the center, and a through-wiring 260 is connected to each floating diffusion 221. Also, as shown in Figure 6(B), four through-wirings 260 are provided so as to penetrate the insulator 250. Although not shown, the four through-wirings 260 are electrically connected to the amplification transistor 141.

[0042] (Semiconductor substrate surface orientation) Figure 7 shows cross-sectional views of the first substrate 100, the second substrate 200, and the third substrate 300. In this embodiment, the silicon crystal orientations of the first semiconductor layer 100a, the second semiconductor layer 200a, and the third semiconductor layer 300a are the same.

[0043] For example, if the plane orientation of silicon wafer 301 (corresponding to the first semiconductor layer 100a) is (100), then the plane orientation of silicon wafer 311 (corresponding to the second semiconductor layer 200a) is also (100). Here, a plane orientation of (100) for a silicon wafer means that the planes parallel to the plane index (100) of the Miller index of the silicon crystal are the main planes (front and back) of the silicon wafer. In this case, the plane orientation of silicon wafer 321 (corresponding to the third semiconductor layer 300a) is also (100).

[0044] Similarly, if the plane orientation of silicon wafer 301 is (110), then the plane orientation of silicon wafer 311 is (110), and the plane orientation of silicon wafer 321 is (110).

[0045] In this way, by making the crystal orientation of the silicon crystals of the first semiconductor layer 100a and the second semiconductor layer 200a the same, the generation of stress that occurs during bonding can be suppressed. In particular, the second semiconductor layer 200a is provided with an insulator 250 in order to provide through wiring 260, and stress tends to occur near the insulator 250, which is beneficial. If stress occurs during bonding, the first substrate 100 including the first semiconductor layer 100a will be distorted, which can narrow the band gap and potentially increase the dark current. By adopting the above configuration, the generation of stress during bonding can be suppressed, and the generation of dark current can be suppressed.

[0046] Furthermore, since the third semiconductor layer 300 is the thickest of the three semiconductor layers (first semiconductor layer 100, second semiconductor layer 200, and third semiconductor layer 300), the stress generated in the first semiconductor layer 100 and second semiconductor layer 200 is caused by the difference in expansion and contraction between them and the third semiconductor layer 300. Therefore, by making the surface orientation of the third semiconductor layer 300 the same as that of the first semiconductor layer 100 and second semiconductor layer 200, the generation of stress in the third semiconductor layer 300 and the first semiconductor layer 100 and second semiconductor layer 200 can be suppressed.

[0047] Furthermore, by aligning the notches on silicon wafers 301, 311, and 321, distortion during bonding can be suppressed, and dark current can be reduced.

[0048] Figure 8 shows the orientation of the silicon wafers 301 and 311, and the orientation of the semiconductor elements on the first substrate 100 and the second substrate 200. Specifically, it shows the orientation of the photoelectric conversion unit 101 (first semiconductor region), the transfer transistor 111, the floating diffusion 121, and the orientation of each transistor constituting the pixel circuit 211.

[0049] The arrows on wafers 301 and 311 in Figures 8(A) and (B) indicate the crystal direction. That is, they show the crystal direction which is perpendicular to the crystal plane. For example, in the case of a (100) substrate with a (100) plane orientation, as shown in Figure 8(C), the first crystal direction is: <100> The direction is the second crystal direction, <100> This is the direction. Here, the crystal direction indicates the direction perpendicular to a specific crystal plane. Also, in the case of a (110) substrate with a plane orientation of (110), as shown in Figure 8(D), the first crystal direction is <110> The direction is the second crystal direction, <100> It is the direction.

[0050] Furthermore, Figures 8(A) and (B) show the orientation of the semiconductor elements. In this orientation, the two wafers are bonded together so that the first crystal directions of wafer 301 and wafer 311 overlap with each other, and the second crystal directions of wafer 301 and wafer 311 overlap with each other. This not only aligns the surface orientation of the wafers but also aligns the crystal directions, thereby suppressing stress generation during bonding.

[0051] In the above, the direction in which the source and drain of the transfer transistor 111 provided in the first semiconductor layer 100a are aligned is referred to as the second crystal direction, but this direction may also be referred to as the first crystal direction. Furthermore, the angle between the direction in which the source and drain of the transfer transistor 111 are aligned and the first or second crystal direction may be 0 degrees or more and 15 degrees or less. Here, if the angle between the two directions is neither 0 degrees nor 90 degrees, it may be an acute angle or an obtuse angle, but in this specification, we will always focus on the acute angle. That is, the angle between the two directions is defined in the range of 0 degrees or more and 90 degrees or less. Also, angles do not have negative values ​​and are always positive. 0 degrees or more and 15 degrees or less typically means 0 degrees or more and 10 degrees or less. More typically, it is 0°.

[0052] Similarly, the direction in which the source and drain of the transistor constituting the pixel circuit provided in the second semiconductor layer 200a are aligned is defined as the second crystal direction, but this direction may also be defined as the first crystal direction. Furthermore, the angle between the direction in which the source and drain of the transistor constituting the pixel circuit are aligned and the first or second crystal direction may be 0 degrees or more and 15 degrees or less. Typically, it is 0 degrees or more and 10 degrees or less, and more typically, it is 0°.

[0053] Figure 9 shows the orientations of silicon wafers 301, 311, and 321, and the orientations of semiconductor elements on the first substrate 100, the second substrate 200, and the third substrate 300. The difference from Figure 8 is that, as shown in Figure 9(C), an example of the arrangement of logic circuit transistors 261 has been added. In the arrangement example shown in Figure 9, the two wafers are bonded together so that the first crystal directions of wafers 301, 311, and 321 overlap with each other, and the second crystal directions overlap with each other. This not only aligns the surface orientation of the wafers but also aligns the crystal directions, thereby suppressing stress generation during bonding.

[0054] (Second Embodiment) The photoelectric conversion device according to this embodiment will be described with reference to Figures 10 and 11.

[0055] Figure 10 shows wafer 331 used for the first semiconductor layer 100b and wafer 341 used for the second semiconductor layer 200b.

[0056] In this embodiment, as in the first embodiment, the surface orientations of wafer 331 and wafer 341 are aligned. For example, if the surface orientation of wafer 331 is (100), then the surface orientation of wafer 341 is also (100). Also, for example, if the surface orientation of wafer 331 is (110), then the surface orientation of wafer 341 is also (110).

[0057] On the other hand, this embodiment differs from the first embodiment in that when wafer 331 and wafer 341 are bonded together, wafer 341 is rotated relative to wafer 331 to change the orientation of its crystal direction. For example, as shown in Figure 10, wafer 341 is tilted 45 degrees to the right with respect to the wafer 331, and then bonded together.

[0058] Figure 11 shows the orientation of the silicon wafers 331 and 341, and the orientation of the semiconductor elements on the first substrate 100 and the second substrate 200. Specifically, it shows the orientation of the photoelectric conversion unit 101 (first semiconductor region), the transfer transistor 111, the floating diffusion 121, and the orientation of each transistor constituting the pixel circuit 211.

[0059] Similar to Figure 8, the direction of the arrows on wafers 331 and 341 in Figures 11(A) and (B) indicates the crystal direction. For example, in the case of a (100) substrate with a (100) plane orientation, as shown in Figure 11(C), the first crystal direction is: <100> The direction is the second crystal direction, <100> This is the direction. Also, in the case of a (110) substrate with a (110) plane orientation, as shown in Figure 11(D), the first crystal direction is <110> The direction is the second crystal direction, <100> It is the direction.

[0060] Here, in wafer 341 of Figure 11(B), unlike in Figure 8(B), the third crystal direction is shown. To explain the first to third crystal directions, Figures 11(C) and (D) are used. In the case of the (100) substrate shown in Figure 11(C), the third crystal direction is: <110> In addition, in the case of the (110) substrate shown in Figure 11(D), the third crystal direction is <111> That is the case.

[0061] In the orientation of the semiconductor elements shown in Figures 11(A) and (B), the two semiconductor element wafers are bonded together so that the second crystal direction of wafer 331 and the third crystal direction of wafer 341 overlap. That is, wafer 341 is rotated 45 degrees to the left with respect to wafer 331, using the wafer center as the axis, before bonding.

[0062] In the second semiconductor layer 200a (wafer 341) on which the pixel circuit is provided, there is a suitable crystal orientation of the silicon crystal for high-speed operation of the transistors constituting the pixel circuit. Therefore, considering the characteristics of the transistors for the pixel circuit, the source or drain of the transistor is positioned in the third crystal orientation, as shown in Figure 11(B). For this reason, as shown in the above configuration, wafer 341 is rotated and bonded to wafer 331.

[0063] In the above example, we described a configuration where the angle between the first crystal direction and the direction in which the source and drain of the transistor are aligned is 45 degrees for the second semiconductor layer 200a. However, it is also possible to configure this angle to be greater than 30 degrees and less than 60 degrees. Furthermore, it is also possible to configure this angle to be greater than 40 degrees and less than 50 degrees.

[0064] Furthermore, the transfer transistor 111 provided in the first semiconductor layer 100a can have the same configuration as in the first embodiment.

[0065] According to this embodiment, by making the crystal orientation of the silicon crystals of the first semiconductor layer 100a and the second semiconductor layer 200a the same, the generation of stress that occurs during bonding can be suppressed. Furthermore, it is also possible to improve the characteristics of the transistors of the pixel circuit provided in the second semiconductor layer 200a.

[0066] (Third embodiment) The photoelectric conversion device according to this embodiment will be described with reference to Figures 12 and 13.

[0067] Figure 12 shows cross-sectional views of the first substrate 100, the second substrate 200, and the third substrate 300. In this embodiment, the silicon crystal orientations of the first semiconductor layer 100a, the second semiconductor layer 200a, and the third semiconductor layer 300a are the same. Wafer 331 is used for the first semiconductor layer 100a, wafer 341 is used for the second semiconductor layer 200a, and wafer 351 is used for the third semiconductor layer 300a.

[0068] As shown in Figure 12, wafers 331 and 341 are bonded together with the same crystal orientation, but wafer 351 is bonded together with a different crystal orientation than wafers 331 and 341.

[0069] In the second embodiment, the crystal orientation of the second semiconductor layer 200a and the crystal orientation of the first semiconductor layer 100a were different, taking into consideration the characteristics of the transistors constituting the pixel circuit, and then they were bonded together. In contrast, in this embodiment, the crystal orientation of the third semiconductor layer 300a and the crystal orientation of the first semiconductor layer 100a were different, taking into consideration the characteristics of the transistors of the logic circuit provided on the third semiconductor layer 300a, and then they were bonded together.

[0070] Specifically, as shown in Figure 13(C), the direction in which the sources and drains of the transistors in the logic circuit provided on the third semiconductor layer 300a are aligned is the third crystal direction. That is, the angle between the first crystal direction of the wafer 351 and the direction in which the sources and drains of the transistors in the logic circuit are aligned is 45 degrees.

[0071] Furthermore, regarding the third semiconductor layer 300a, an example was described in which the angle between the first crystal direction and the direction in which the source and drain of the transistor are aligned is 45 degrees. However, it is also possible to configure this angle to be greater than 30 degrees and less than 60 degrees. It is also possible to configure this angle to be greater than 40 degrees and less than 50 degrees.

[0072] According to this embodiment, by making the crystal orientations of the silicon crystals of the first semiconductor layer 100a, the second semiconductor layer 200a, and the third semiconductor layer 300a the same, the generation of stress that occurs during bonding can be suppressed. Furthermore, it is also possible to improve the characteristics of the transistors of the logic circuit provided on the third semiconductor layer 300a.

[0073] In this embodiment, the angle between the direction in which the sources and drains of the logic circuit transistors are aligned and the first crystal direction of the wafer is greater than 30 degrees and less than 60 degrees. In addition, the angle between the direction in which the sources and drains of the pixel circuit transistors are aligned and the first crystal direction of the wafer may be greater than 30 degrees and less than 60 degrees. With this configuration, it is also possible to improve the characteristics of the transistors of the pixel circuit provided on the second semiconductor layer 200a.

[0074] (Fourth Embodiment) Figure 14 is a diagram relating to a device according to the fourth embodiment. This embodiment is applicable to any of the above embodiments. Figure 14(a) is a schematic diagram illustrating a device 9191 equipped with the semiconductor device 930 of this embodiment. The photoelectric converters of each of the above embodiments can be used as the semiconductor device 930. The device 9191 equipped with the semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 may include a semiconductor device 910 having a semiconductor layer 10, as well as a package 920 that houses the semiconductor device 910. The package 920 may include a substrate to which the semiconductor device 910 is fixed, and a lid such as glass facing the semiconductor device 910. The package 920 may further include bonding members such as bonding wires and bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0075] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device (signal processing unit) 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, or mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0076] The processing unit 960 processes the signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0077] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0078] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0079] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) through its imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, office equipment such as a copier, or industrial equipment such as a robot.

[0080] According to the embodiments described above, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. Increasing value here means at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0081] Therefore, by using the semiconductor device 930 according to this embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device according to this embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device to assist in driving and / or perform automated driving.

[0082] Furthermore, the photoelectric conversion system and mobile body of this embodiment will be explained using Figures 14(b) and (c).

[0083] Figure 14(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device (imaging device) as described in any of the embodiments above. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0084] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to the control ECU 820, which is a control device (control unit) that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to the warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment result of the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0085] In this embodiment, the photoelectric conversion system 8 images the area around the vehicle, for example, the front or rear. Figure 14(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0086] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0087] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0088] For example, examples in which some configurations of one embodiment are added to other embodiments, or in which some configurations of other embodiments are replaced, are also included as embodiments of the present invention.

[0089] Furthermore, the equipment (photoelectric conversion system) shown in the above embodiment is merely an example of a photoelectric conversion system to which the photoelectric conversion device can be applied, and the photoelectric conversion system to which the photoelectric conversion device of the present invention can be applied is not limited to the configuration shown in Figure 14.

[0090] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention. The disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto.

[0091] Furthermore, the disclosure of this embodiment includes the following configurations and methods.

[0092] (Composition 1) A first substrate having a photoelectric conversion unit and a transfer transistor for transferring the charge generated by the photoelectric conversion unit, A second substrate having a pixel circuit that outputs a signal based on the charge transferred from the transfer transistor in the second semiconductor layer, The third semiconductor layer comprises a third substrate having a logic circuit for processing the signal, The first substrate, the second substrate, and the third substrate are stacked such that the second substrate is placed between the first substrate and the third substrate. The first substrate and the second substrate are electrically connected by through-wiring that penetrates the insulator of the second semiconductor layer. A photoelectric conversion device characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are the same.

[0093] (Configuration 2) The photoelectric conversion apparatus according to configuration 1, characterized in that the first substrate and the second substrate are stacked such that the first crystal direction of the first semiconductor layer and the first crystal direction of the second semiconductor layer are in the same direction.

[0094] (Composition 3) The photoelectric conversion apparatus according to configuration 1, characterized in that the first substrate and the second substrate are stacked such that the first crystal direction of the first semiconductor layer and the first crystal direction of the second semiconductor layer are in different directions.

[0095] (Composition 4) The photoelectric conversion device according to configuration 1 or 3, characterized in that the angle between the first crystal orientation of the second semiconductor layer and the direction in which the source and drain of the transistor constituting the pixel circuit are aligned is greater than 30 degrees and less than 60 degrees.

[0096] (Composition 5) The photoelectric conversion apparatus according to any one of claims 1 to 4, characterized in that the surface orientation of the third semiconductor layer and the surface orientation of the second semiconductor layer are the same.

[0097] (Composition 6) The photoelectric conversion apparatus according to configuration 5, characterized in that the second substrate and the third substrate are stacked such that the first crystal direction of the second semiconductor layer and the first crystal direction of the third semiconductor layer are in the same direction.

[0098] (Composition 7) The photoelectric conversion apparatus according to configuration 5, characterized in that the second substrate and the third substrate are stacked such that the first crystal direction of the second semiconductor layer and the first crystal direction of the third semiconductor layer are in different directions.

[0099] (Composition 8) The photoelectric conversion device according to configuration 7, characterized in that the angle between the first crystal orientation of the third semiconductor layer and the direction in which the source and drain of the transistor constituting the logic circuit are aligned is greater than 30 degrees and less than 60 degrees.

[0100] (Composition 9) The photoelectric conversion device according to any one of configurations 1 to 8, characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (100).

[0101] (Composition 10) The photoelectric conversion device according to any one of configurations 1 to 8, characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (110).

[0102] (Composition 11) The surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (100), and the first crystal direction is <100> A photoelectric conversion device according to any one of the configurations 2 to 4, characterized in that it is the same as described above.

[0103] (Composition 12) The surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (110), and the first crystal direction is <110> A photoelectric conversion device according to any one of the configurations 2 to 4, characterized in that it is the same as described above.

[0104] (Composition 13) A first wiring layer is provided between the first semiconductor layer and the second semiconductor layer. A second wiring layer is provided between the second semiconductor layer and the third semiconductor layer. A third wiring layer is provided between the second wiring layer and the third semiconductor layer. The first wiring layer has an interlayer insulating film The photoelectric conversion device according to any one of the configurations 1 to 12, characterized in that the through-wiring penetrates the interlayer insulating film.

[0105] (Composition 14) A photoelectric conversion device according to any configuration 1 to 13, A photoelectric conversion system characterized by having a signal processing unit that generates an image using the signal output by the aforementioned photoelectric conversion device.

[0106] (Composition 15) A mobile body comprising a photoelectric converter according to any configuration of claim 1 to 13, The photoelectric converter has a control unit that controls the movement of the mobile body using the signal output by the photoelectric converter. A mobile body characterized by the following features. [Explanation of Symbols]

[0107] 100 First board 200 Second board 300 Third board 331, 341, 351 wafers

Claims

1. A first semiconductor layer comprises a first substrate having a photoelectric conversion unit and a transfer transistor that transfers the charge generated in the photoelectric conversion unit, A second substrate having a pixel circuit that outputs a signal based on the charge transferred from the transfer transistor in the second semiconductor layer, The third semiconductor layer comprises a third substrate having a logic circuit for processing the signal, The first substrate, the second substrate, and the third substrate are stacked such that the second substrate is placed between the first substrate and the third substrate. The first substrate and the second substrate are electrically connected by through-wiring that penetrates the insulator of the second semiconductor layer. The surface orientation of the first semiconductor layer, the surface orientation of the second semiconductor layer, and the surface orientation of the third semiconductor layer are the same. The photoelectric conversion device is characterized in that the third semiconductor layer is thicker than the first semiconductor layer and the second semiconductor layer.

2. The first substrate, the second substrate, and the third substrate are stacked such that the first crystal direction of the first semiconductor layer, the first crystal direction of the second semiconductor layer, and the first crystal direction of the third semiconductor layer are in the same direction. The photoelectric conversion apparatus according to claim 1, characterized in that the first crystal direction is the crystal direction within the main plane of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

3. The first substrate and the second substrate are stacked such that the first crystal direction of the first semiconductor layer and the first crystal direction of the second semiconductor layer are in different directions. The photoelectric conversion apparatus according to claim 1, characterized in that the first crystal direction is the crystal direction within the main planes of the first semiconductor layer and the second semiconductor layer, respectively.

4. The photoelectric conversion device according to claim 3, characterized in that the angle between the first crystal orientation of the second semiconductor layer and the direction in which the source and drain of the transistor constituting the pixel circuit are aligned is greater than 30 degrees and less than 60 degrees.

5. The second substrate and the third substrate are stacked such that the first crystal direction of the second semiconductor layer and the first crystal direction of the third semiconductor layer are in different directions. The photoelectric conversion apparatus according to claim 1, characterized in that the first crystal orientation is the crystal orientation within the main planes of the second semiconductor layer and the third semiconductor layer, respectively.

6. The photoelectric conversion device according to claim 5, characterized in that the angle between the first crystal orientation of the third semiconductor layer and the direction in which the source and drain of the transistor constituting the logic circuit are aligned is greater than 30 degrees and less than 60 degrees.

7. The photoelectric conversion apparatus according to any one of claims 1 to 4, characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (100).

8. The photoelectric conversion apparatus according to any one of claims 1 to 4, characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (110).

9. The photoelectric conversion apparatus according to claim 2 or 3, characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (100), and the first crystal direction is <100>.

10. The photoelectric conversion apparatus according to claim 2 or 3, characterized in that the surface orientation of the first semiconductor layer and the surface orientation of the second semiconductor layer are (110), and the first crystal direction is <110>.

11. A first wiring layer is provided between the first semiconductor layer and the second semiconductor layer. A second wiring layer is provided between the second semiconductor layer and the third semiconductor layer. A third wiring layer is provided between the second wiring layer and the third semiconductor layer. The first wiring layer has an interlayer insulating film, The photoelectric conversion device according to claim 1, characterized in that the through-wiring penetrates the interlayer insulating film.

12. The photoelectric conversion device according to claim 1, A photoelectric conversion system characterized by having a signal processing unit that generates an image using the signal output by the aforementioned photoelectric conversion device.

13. A mobile body comprising the photoelectric conversion device described in claim 1, A mobile body characterized by having a control unit that controls the movement of the mobile body using a signal output by the photoelectric converter.

Images