Manufacturing method for stacked devices

Abstract

To provide a technology that enables significant simplification of a manufacturing process for a lamination device in which multiple chips are stacked.SOLUTION: In a manufacturing method of a lamination device, in a state in which a first joining object is held by a first support, before cutting is performed to separate the multiple base regions, in a separation step, in a state in which a second joining object having multiple chip regions is held by a second support, a cutting process is performed on the second joining object using plasma or laser light to form a separation portion that separates adjacent chip regions by a predetermined width, and in a joining step, in a state in which the first joining object is held by the first support, the second support is moved relative to the first support to join the second joining object to the first joining object such that, for each base region, at least one chip region corresponding to that base region is stacked in a predetermined positional relationship.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a manufacturing technology for a stacked device in which a plurality of chips are stacked.

Background Art

[0002] In the field of semiconductor technology, various methods such as the COW (Chip on Wafer) method and the WOW (Wafer on Wafer) method have been proposed as stacking technologies for three-dimensionally stacking chips such as LSI (Large Scale Integration).

[0003] In the COW method (see, for example, Patent Documents 1 and 3), first, a semiconductor wafer is subjected to a cutting process to singulate the semiconductor wafer into a plurality of chips, and then the plurality of chips are stacked one by one on a base wafer. After the chips are stacked until a desired number of stacked layers is reached, the base wafer is subjected to a cutting process to singulate the base wafer into a plurality of bases (portions that serve as the foundation of the stacked device), thereby completing a stacked device in which a plurality of chips are stacked on the base.

[0004] In the WOW method (see, for example, Patent Documents 2 and 3), first, semiconductor wafers are stacked on a base wafer. After the semiconductor wafers are stacked until a desired number of stacked layers is reached, the wafer stack is subjected to a cutting process to singulate the wafer stack into a plurality of stacked devices.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of Invention

[0006] However, conventional COW and WOW methods had the problem of complicated manufacturing processes, as described below.

[0007] Consider a case where a base wafer has N base regions that serve as the base for stacked devices. In the COW (Chip-on-Wave) method, it is necessary to stack one chip at a time in each of these N base regions. Therefore, stacking the first layer of chips on the base wafer requires N stacking operations. And to stack chips up to the Mth layer on the base wafer, N × M stacking operations are required.

[0008] Furthermore, in the WOW method, when it is necessary to stack thinned semiconductor wafers on a base wafer, the handling of the thinned semiconductor wafers becomes technically difficult when attempting to stack them on the base wafer. Therefore, conventionally, the semiconductor wafers were bonded (stacked) onto the base wafer before thinning, and then thinned by polishing. On the other hand, during polishing, shear stress is generated at the bonding surface between wafers, and if the bonding strength is weak, there is a risk that the bonding (stack) between wafers will break. For this reason, it was necessary to apply heat treatment to the entire stack before polishing in order to increase the bonding strength. Consequently, when stacking thinned semiconductor wafers on a base wafer until the desired number of layers is reached, it was necessary to perform heat treatment to increase the bonding strength before polishing each layer of semiconductor wafer that was stacked.

[0009] Therefore, the objective of the present invention is to achieve a significant simplification of the manufacturing process in the manufacturing technology of stacked devices in which multiple chips are stacked. [Means for solving the problem]

[0010] In the method for manufacturing a stacked device according to the present invention, a first bonding target having multiple base regions is held by a first support and subjected to a cutting process to separate each of the multiple base regions into individual pieces, before performing a separation step and a bonding step. In the separation step, a second bonding target having multiple chip regions is held by a second support and subjected to a cutting process using plasma or laser light to form a separation portion that separates adjacent chip regions by a predetermined width, thereby separating each of the multiple chip regions into individual pieces. In the bonding step, the second bonding target is bonded to the first bonding target by moving the second support relative to the first support while the first bonding target is held by the first support, so that at least one chip region corresponding to each base region is stacked in a predetermined positional relationship.

[0011] In the above manufacturing method, similar to the conventional COW method, it is necessary to join (stack) individual chip regions onto multiple base regions, and then to separate each of the multiple base regions into individual pieces by cutting the first bonding target (not limited to cutting using plasma or laser light). For this reason, in such a manufacturing method, it is necessary to create an appropriate gap (a gap that enables cutting of the first bonding target) between adjacent chip regions on the first bonding target so that cutting of the first bonding target is possible after joining (stacking) the individual chip regions.

[0012] Therefore, in the conventional COW method, the size of the chip region was designed to be smaller than the size of the base region even before the chip region was separated into individual pieces by cutting. Then, the separated chip regions were either taken out one by one and joined (stacked) onto the base region, or, in order to join them together to multiple base regions, the chip regions were taken out one by one and rearranged on a support (such as a holding sheet) so that they were in a positional relationship with the base region. Consequently, in such conventional COW methods, it was necessary to take out the separated chip regions one by one when joining (stacking) onto the base region.

[0013] On the other hand, attempting to remove individual chip regions one by one risked contact with adjacent chip regions. Furthermore, if plasma or laser light was used for cutting the chip regions in the conventional COW method, the cutting lines would be extremely thin (e.g., 10 μm or less), making it easy to contact adjacent chip regions when attempting to remove them one by one in their cut state. Therefore, to avoid such contact, it was necessary to increase the distance between adjacent chip regions by either stretching the support (such as a holding sheet) used when separating the chip regions if the support was a stretchable sheet, or by stretching the stretchable sheet after transfer if the support was not stretchable. However, stretching the stretchable sheet to increase the distance between chip regions resulted in variations in the distance between adjacent chip regions, requiring re-measurement of their positions in order to determine their positions on the stretchable sheet.

[0014] According to the above manufacturing method, by appropriately adjusting the width (predetermined width) of the separation section in the separation step, a suitable gap can be created between adjacent chip regions, enabling cutting of the first joining target. Therefore, in the joining step, by simply joining the chip regions separated in the separation step directly to the first joining target, a suitable gap (a gap that enables cutting of the first joining target) can be created between adjacent chip regions on the first joining target as well. Thus, a suitable gap can be formed between adjacent chip regions on the first joining target without having to remove each chip region one by one as in the conventional method. Consequently, processes such as stretching the stretchable sheet and measuring the position of each chip region after stretching become unnecessary. Furthermore, even after being separated into individual chips, the chip regions can be handled in the same positional relationship as before separation (i.e., before the separation step), and as a result, handling of the separated chip regions becomes easier.

[0015] Furthermore, by forming the chip region in the second bonding target in a positional relationship corresponding to the base region, in the bonding step, the chip regions separated in the separation step can be grouped together and bonded to the multiple base regions provided on the first bonding target while positioning them so that their respective positional relationships with the multiple base regions are predetermined. In other words, in the bonding step, the multiple chip regions separated from the second bonding target in the separation step can be grouped together and bonded (stacked) to the multiple base regions provided on the first bonding target in a single bonding operation.

[0016] This significantly simplifies the manufacturing process compared to the method of bonding (stacking) individual chip regions from the second bonding target to multiple base regions provided in the first bonding target one by one. Specifically, when the first bonding target has N base regions and the second bonding target has N chip regions, bonding (stacking) the chip regions one by one to the N base regions requires N bonding (stacking) steps, whereas the above manufacturing method only requires one bonding step, thus significantly simplifying the manufacturing process.

[0017] Furthermore, by using plasma or laser cutting, high-precision cutting of the second bonding target becomes possible, and processing can be performed with almost no lateral force (force in the direction along the holding surface of the second support) applied to the second bonding target. As a result, in the chip regions separated by the formation of the separation section, the variation in the positional relationship between the circuit within each chip region and the edge (outer edge) of that chip region can be reduced. In addition, the bending strength of the cut surface can be increased, and a clean edge without defects can be formed. [Effects of the Invention]

[0018] According to the present invention, a significant simplification of the manufacturing process is achieved in the manufacturing technology of stacked devices in which multiple chips are stacked. [Brief explanation of the drawing]

[0019] [Figure 1] This is a conceptual perspective view showing a stacked device obtained by the manufacturing method according to the embodiment. [Figure 2] (A) is a plan view showing the base material (first to be joined) and (B) is a plan view showing the chip material (second to be joined). [Figure 3] This is a conceptual diagram showing the state before and after the base material (first bonding target) is held by the first support. [Figure 4] This is an enlarged perspective view of the Ya region shown in the upper left of Figure 3. [Figure 5] This is a conceptual diagram showing the separation step. [Figure 6] This is an enlarged perspective view of the portion in the Yb region shown in the upper left diagram of Figure 5. [Figure 7] (A) A plan view conceptually showing the state of the second bonding target G2 after execution of the separation step, and (B) a vertical cross-sectional view taken along the Za-Za line shown in Figure 7(A) (the same line as the Za-Za line shown in the lower left diagram of Figure 5). [Figure 8] This is a conceptual diagram showing the method for forming the separation portion executed in the separation step in the embodiment. [Figure 9] (A) A conceptual diagram showing the bonding step, and (B) a vertical cross-sectional view taken along the Zb-Zb line shown in the upper left diagram of Figure 9(A). [Figure 10] (A) A conceptual diagram showing the bonding step executed in the repeated process, and (B) a vertical cross-sectional view taken along the Zc-Zc line shown in Figure 10(A). [Figure 11] (A) A conceptual diagram showing the state when the chip base material (second bonding target) is bonded (laminated) up to the 7th layer on the base base material (first bonding target), and (B) a vertical cross-sectional view taken along the Zd-Zd line shown in Figure 11(A). [Figure 12] This is a vertical cross-sectional view exemplifying the state when the chip base material (second bonding target) is bonded (laminated) up to the 2nd layer on the base base material (first bonding target) in the fourth modified example. [Figure 13] This is a conceptual diagram showing a process that can be executed in place of the thinning step and the separation step. [Mode for Carrying Out the Invention]

[0020] [1] Embodiment [1-1] Configuration of laminated device Figure 1 is a conceptual perspective view of a stacked device 10 obtained by the manufacturing method according to the embodiment. As shown in Figure 1, the stacked device 10 comprises a base 11 and a chip stack 12. Here, the base 11 is the foundation of the stacked device 10, and external terminals and wiring are formed on the base 11. The chip stack 12 is a part composed of multiple chips Mc stacked three-dimensionally on the base 11. In the example in Figure 1, the case in which chips Mc are stacked three-dimensionally from the 1st to the 7th layer on the base 11 is shown. The chips Mc are not particularly limited, but for example, they are semiconductor chips such as LSIs. Note that the number of stacked chips Mc can be changed as appropriate to a number other than 7 layers (including 1 layer).

[0021] Furthermore, the base 11 may have the same or different circuits as the chip Mc, not limited to terminals and wiring. Also, the chip Mc constituting the chip stack 12 may include chips with the same circuit, or chips with different circuits.

[0022] In this embodiment, all chips Mc are identical in shape (including squares) and size. The base 11 is rectangular (including squares) in shape and larger in size than the chips Mc. However, the shape and size are not limited to these and can be changed as appropriate. The shapes of the base 11 and chips Mc may be changed to, for example, circular. Furthermore, as shown in the fourth modification described later (see Figure 12), chips Mc of different sizes may be stacked on the base 11, or as shown in the fifth modification described later, chips Mc may be arranged three-dimensionally at multiple locations on the base 11.

[0023] [1-2] Method for manufacturing stacked devices In the manufacturing method of this embodiment, a base material Gb and a chip material Gc are used as the base materials for manufacturing the stacked device 10. These base materials are not particularly limited, but for example, a semiconductor wafer.

[0024] Figures 2(A) and 2(B) are plan views showing the base material Gb and the tip material Gc, respectively. As shown by the dashed line in Figure 2(A), the base material Gb has multiple regions that will become the base 11 (base region Rb). Similarly, as shown by the dashed line in Figure 2(B), the tip material Gc has multiple regions that will become the tip Mc (tip region Rc).

[0025] In this embodiment, the base material Gb and the chip material Gc are provided with an equal number of base regions Rb and chip regions Rc. These regions are formed such that one chip region Rc corresponds to each base region Rb, and when the positional relationship of any one pair of corresponding base regions Rb and chip regions Rc is adjusted to a predetermined positional relationship, the positional relationship of the base regions Rb and chip regions Rc in any other pair is also formed to be predetermined. Here, the predetermined positional relationship is a positional relationship (a positional relationship that takes into account the connection positions between circuits, etc.) that allows the circuits provided in the base regions Rb and chip regions Rc to function normally in the stacked device 10.

[0026] In this embodiment, as will be described in detail later, before performing a cutting process on the base material Gb to separate each of the multiple base regions Rb into individual pieces, the chip regions Rc (chip Mc) that have been separated by cutting the chip material Gc are joined (stacked) three-dimensionally on the multiple base regions Rb until the desired number of stacks is reached. Therefore, in the manufacturing method of this embodiment, similar to the conventional COW method, it is necessary to separate each of the multiple base regions Rb by cutting the base material Gb (not limited to cutting using plasma or laser light) after joining (stacking) the separated chip regions Rc (chip Mc). For this reason, in such a manufacturing method, it is necessary to create an appropriate gap (a gap that enables cutting of the base material Gb) between adjacent chip regions Rc (chip Mc) on the base material Gb so that cutting of the base material Gb is possible after joining (stacking) the separated chip regions Rc (chip Mc).

[0027] Therefore, in the conventional COW method, even before the chip region Rc is separated into individual pieces by cutting the chip base material Gc, the size of the chip region Rc is designed to be smaller than the size of the base region Rb. Then, the separated chip region Rc is taken out one by one and joined (stacked) onto the base region Rb, or, in order to join them together to multiple base regions Rb, the chip region Rc is taken out one by one and rearranged on a support (holding sheet, etc.) so that it is in a positional relationship with the base region Rb. Consequently, in such conventional COW methods, it was necessary to take out the separated chip region Rc one by one when joining (stacking) onto the base region Rb.

[0028] On the other hand, when attempting to remove individual chip regions Rc one by one, there was a risk of contact with adjacent chip regions Rc. Furthermore, if plasma or laser light was used for cutting to individualize the chip regions Rc in the conventional COW method, the cutting line would be extremely thin (e.g., 10 μm or less), making it easy to contact adjacent chip regions Rc when attempting to remove them one by one in the state after cutting. Therefore, to avoid such contact, if the support (holding sheet, etc.) used when individualizing the chip regions Rc was a stretchable sheet, it was necessary to stretch the support, or if not, to stretch the stretchable sheet after transfer, thereby increasing the distance between adjacent chip regions Rc. However, when the distance between chip regions Rc is increased by stretching the stretchable sheet, variations in the distance between adjacent chip regions Rc occur, so in order to determine the position of the chip regions Rc on the stretchable sheet, their positions must be measured again.

[0029] Therefore, in this embodiment, the manufacturing process for producing the stacked device 10 facilitates the handling of the individual chip regions Rc, thereby significantly simplifying the manufacturing process. To achieve this, the following steps are performed: a thinning step, a separation step, a bonding step, and a cutting step. The flow of the manufacturing process and the details of each step will be described in detail below. These steps can be implemented using various well-known devices. Furthermore, the manufacturing method described below can also be applied when manufacturing a stacked device 10 with a number of chip Mc layers other than 7 (including 1 layer).

[0030] First, one base material Gb and one tip material Gc are prepared, and the thinning step, separation step, and bonding step are performed on these two base materials. Here, the base material Gb and tip material Gc are referred to as "G1, the first bonding target" and "G2, the second bonding target," respectively.

[0031] The first bonding target G1 (base material Gb) is held by the first support 21 (see upper left and right figures in Figure 3). In this embodiment, the first support 21 is a holding sheet mainly composed of a resin (such as polyolefin or silicone) or rubber (such as fluorinated rubber) that has at least some adhesive force, and the first bonding target G1 can be held by the adhesive force of this main component. The first support 21 further has the following configuration. The second bonding target G2 (chip material Gc) is held by the second support 22 in the separation step described later (see upper left and right figures in Figure 5).

[0032] Figure 4 is an enlarged perspective view of the Ya region portion of the first support 21 (holding sheet) shown in the upper left of Figure 3. As shown in this figure, the first support 21 is provided with a plurality of protrusions 21b on the holding surface 21a that holds the first object to be joined G1. The protrusions 21b are made of the same components as the main components that constitute the first support 21 and are formed integrally with the first support 21. The first object to be joined G1 is held by the first support 21 by the suction force of the protrusions 21b when it makes surface contact with the plurality of protrusions 21b.

[0033] On the other hand, when the first object to be joined G1 is held by the holding surface 21a, the first object to be joined G1 will only be in surface contact with the portion of the holding surface 21a where the protrusion 21b is provided. In the example in Figure 4, the protrusion 21b is formed such that the contact surface 21c with the first object to be joined G1 is rectangular (including square). Note that the shape of the contact surface 21c of the protrusion 21b is not limited to a rectangle, but may be changed to various shapes including polygons and circles, as long as it can hold the first object to be joined G1.

[0034] With such a first support 21, the contact area with the first bonding target G1 can be adjusted by adjusting the number of protrusions 21b and the area of ​​the contact surface 21c. As a result, the holding force of the first support 21 with respect to the first bonding target G1 (i.e., the sum of the suction forces of the protrusions 21b) can be adjusted. By adjusting the holding force of the first support 21, the necessary holding force can be maintained during the manufacturing process, and after the laminated device 10 is completed in the cutting step described later, the pickup of the laminated device 10, which involves peeling it off the first support 21, can be made easier. Specifically, the holding force of the first support 21 can be adjusted to an appropriate size so as not to damage the bonding portion within the laminated device 10 when it is peeled off the first support 21 by pickup. Therefore, by holding the first bond target G1 using such a first support 21, the first bond target G1 can be firmly held, and when it becomes necessary to peel the laminated device 10 from the first support 21, it becomes possible to easily peel it without adversely affecting (such as damaging) the bonded portion within the laminated device 10.

[0035] Furthermore, the first support 21 may be appropriately replaced with a substrate (such as a wafer or glass substrate) on which the above-mentioned retaining sheet is formed. For example, a retaining sheet having protrusions 21b can be formed on the surface of the substrate by applying a resin or rubber with adhesive properties to the surface of the substrate and then molding it by pressing or the like. Alternatively, the first support 21 may be appropriately replaced with a substrate (such as a wafer or glass substrate) that holds the first bonding target G1 with an adhesive or the like, as long as it can peel off the laminated device 10.

[0036] <Thinning step> In the thinning step, the second bonding target G2 (chip base material Gc) is thinned by polishing. As an example, the second bonding target G2 is thinned to a thickness of 150 μm or less. In this embodiment, the thinning of the second bonding target G2 is performed before the separation step (i.e., before the bonding step) described later.

[0037] Furthermore, in this thinning step, not only is the second target G2 to be joined thinned, but the first target G1 (base material Gb) may also be thinned to a desired thickness (which may be different from the thickness of the second target G2). When the first target G1 to be joined is thinned, the holding of the first target G1 by the first support 21 may be performed after the thinning of the first target G1. As described above, the first support 21 firmly holds the first target G1 to be joined, and when peeling becomes necessary, peeling can be easily performed without adversely affecting the joint (such as breaking) the joint. Therefore, by holding the first target G1 to be joined using such a first support 21, even the thinned first target G1 to be joined becomes easier to handle.

[0038] In this embodiment, the thinning of both the base material Gb and the tip material Gc is performed before joining (lamination) in the joining step described later. If the base material Gb or tip material Gc is to be thinned after joining (lamination) as in the conventional method, shear stress will be generated at the joining surface between the base materials during polishing, and if the joining strength is weak, the joining (lamination) between the base materials may break. For this reason, in order to thin using the conventional method, it is necessary to increase the joining strength by applying heat treatment to the entire laminate before polishing. Furthermore, when joining (laminating) two or more tip material Gc onto the base material Gb, two or more joining (lamination) steps are required, and it is necessary to perform heat treatment to increase the joining strength before polishing each time joining is performed. On the other hand, by performing the thinning step before joining (lamination) as in this embodiment, it is not necessary to perform heat treatment each time joining is performed, and the manufacturing process is simplified.

[0039] <Separation Step> Figure 5 is a conceptual diagram showing the separation step. In the separation step, the second bonding target G2 (chip base material Gc), which has been thinned in the thinning step, is held by the second support 22 (upper left and right diagrams of Figure 5). In this embodiment, the second support 22, like the first support 21, is a holding sheet mainly composed of a resin (such as polyolefin or silicone) or rubber (such as fluorinated rubber) that has at least some adhesive force, and the second bonding target G2 can be held by the adhesive force of the main component. Furthermore, the second support 22 has the following configuration.

[0040] Figure 6 is an enlarged perspective view of the Yb region of the second support 22 (holding sheet) shown in the upper left of Figure 5. As shown in this figure, the second support 22 is provided with a plurality of protrusions 22b on the holding surface 22a that holds the second bond target G2. The protrusions 22b are made of the same components as the main components that constitute the second support 22 and are integrally formed with the second support 22. The second bond target G2 is held by the second support 22 by the suction force of the protrusions 22b when it makes surface contact with the plurality of protrusions 22b.

[0041] On the other hand, when the second object to be joined G2 is held by the holding surface 22a, the second object to be joined G2 will only be in surface contact with the portion of the holding surface 22a where the protrusion 22b is provided. In the example in Figure 6, the protrusion 22b is formed such that the contact surface 22c with the second object to be joined G2 is rectangular (including square). Note that the shape of the contact surface 22c of the protrusion 22b is not limited to a rectangle, but may be changed to various shapes including polygons and circles, as long as it can hold the second object to be joined G2.

[0042] With such a second support 22, the contact area with the second bonding target G2 can be adjusted by adjusting the number of protrusions 22b and the area of ​​the contact surface 22c. As a result, the holding force of the second support 22 with respect to the second bonding target G2 (i.e., the sum of the adsorption forces of the protrusions 22b) can be adjusted. By adjusting the holding force of the second support 22, the necessary holding force can be maintained during the manufacturing process, and after the second bonding target G2 is bonded (laminated) to the first bonding target G1 in the bonding step described later, the second support 22 can be easily peeled off the second bonding target G2. Specifically, the holding force of the second support 22 can be adjusted to an appropriate size so as not to damage the bonded portion when peeling the second support 22 off the second bonding target G2. Therefore, by holding the second target G2 using such a second support 22, the second target G2 can be firmly held, and when it becomes necessary to peel the second support 22 from the second target G2, this peeling can be easily performed without adversely affecting (such as damaging) the joint between the base materials. Thus, even a thinned second target G2 becomes easier to handle.

[0043] Furthermore, the second support 22 may be appropriately replaced with a substrate (such as a wafer or glass substrate) on which the above-mentioned retaining sheet is formed. For example, a retaining sheet with protrusions 22b can be formed on the surface of the substrate by applying a resin or rubber with adhesive properties to the surface of the substrate and then molding it by pressing or the like. Alternatively, the second support 22 may be appropriately replaced with a substrate (such as a wafer or glass substrate) that holds the second bonding target G2 with an adhesive or the like, as long as it can be peeled off from the second bonding target G2.

[0044] Furthermore, in this embodiment, the first support 21 and the second support 22 (see Figures 4 and 6) have protrusions 21b and 22b formed on their holding surfaces 21a and 22a such that the contact area when the second support 22 holds the second bonding target G2 is smaller than the contact area when the first support 21 holds the first bonding target G1. With this configuration, by creating a difference in the size of the contact area, a difference in holding force can be created, and as a result, a difference in peel strength can also be created (specifically, the smaller the contact area, the easier it is to peel). Therefore, if it is desired to peel off only the second support 22 after bonding (laminating) the second bonding target G2 to the first bonding target G1 in the bonding step described later, the difference in holding force (in this case, the difference in peel strength) can be used to easily peel off only the second support 22.

[0045] In the separation step, after the second bonding target G2 is held by the second support 22, a cutting process using plasma or laser light is performed on the second bonding target G2 in that state to form a separation section Ed that separates adjacent chip regions Rc by a predetermined width Wt, thereby separating multiple chip regions Rc into individual pieces (see the lower left diagram of Figure 5, Figure 7(A), and Figure 7(B)). The method for forming the separation section Ed will be described in detail below.

[0046] Figures 8(A) to 8(C) are conceptual diagrams showing the method for forming the separation portion Ed in this embodiment. Here, Figure 8(A) is a conceptual diagram of the second joint target G2 viewed from the plan, similar to Figure 7(A), and Figure 8(B) is a partially enlarged view showing an enlarged portion of the longitudinal cross-section along the Za-Za line shown in Figure 8(A) (the same line as the Za-Za line shown in the lower left diagram of Figure 5). Furthermore, Figure 8(C) is a conceptual diagram showing the completed state of the separation portion Ed, for the same portion as in Figure 8(B).

[0047] In this embodiment, first, as shown in Figures 8(A) and 8(B), two parallel cutting lines Ld are formed on the second bonding target G2 by cutting using plasma or laser light. Specifically, the cutting lines Ld are formed by etching the cutting area (the area where the cutting lines Ld are formed) using plasma (plasma etching). At this time, the area of ​​the surface of the second bonding target G2 other than the cutting area is protected from the plasma by a resist. Alternatively, instead of plasma etching, the cutting lines Ld may be formed by causing ablation at the cutting area using laser light (laser ablation).

[0048] Subsequently, as shown in Figure 8(C), the separation section Ed is completed by removing the unnecessary portion between the two cutting lines Ld. For example, by inverting the second support 22, only the unnecessary portion between the two cutting lines Ld can be dropped and removed. As another example, in a cleaning process to remove the resist used in plasma etching, the unnecessary portion between the two cutting lines Ld can be washed away and removed together with the resist.

[0049] With this method of forming the separation portion Ed, it is only necessary to perform a cutting process using plasma or laser light (specifically, plasma etching or laser ablation) on the area where the cutting line Ld, which forms the edge of the separation portion Ed, is to be formed. Therefore, it is possible to form the separation portion Ed in a shorter time compared to when plasma etching or laser ablation is performed on the entire area where the separation portion Ed is formed.

[0050] Furthermore, by adjusting the width of the two cutting lines Ld, the width of the formed separation section Ed (a predetermined width Wt) can be appropriately adjusted. By appropriately adjusting the width of the separation section Ed, a suitable gap can be created between adjacent chip regions Rc, enabling cutting of the first joining target G1.

[0051] Furthermore, by using plasma or laser cutting, high-precision cutting of the second bonding target G2 becomes possible, and processing can be performed with almost no lateral force (force in the direction along the holding surface 22a of the second support 22) applied to the second bonding target G2. As a result, in the chip regions Rc separated by the formation of the separation portion Ed, the variation in the positional relationship between the circuit within each chip region Rc and its edge (outer edge) can be reduced for each chip region Rc. In addition, the bending strength of the cut surface can be increased, and a clean edge without defects can be formed.

[0052] <Joining Steps> The bonding step is performed after the separation step and after the first bonding target G1 is held by the first support 21. Figure 9(A) is a conceptual diagram showing the bonding step, and 9(B) is a longitudinal cross-sectional view along the Zb-Zb line shown in the upper left of Figure 9(A). In the bonding step, as shown in Figure 9(A), the second bonding target G2 is bonded to the first bonding target G1 by moving the second support 22 relative to the first support 21. Specifically, as shown in Figure 9(B), the second bonding target G2 is bonded to the first bonding target G1 such that, for each base region Rb, the chip region Rc corresponding to that base region Rb is stacked in a predetermined positional relationship. Here, the predetermined positional relationship is a positional relationship (a positional relationship that takes into account the connection positions between circuits, etc.) that allows the circuits provided in the base region Rb and the chip region Rc to function normally in the stacked device 10.

[0053] In this embodiment, as described above, the base region Rb and the chip region Rc are formed such that one chip region Rc corresponds to each base region Rb, and when the positional relationship of any one pair of corresponding base region Rb and chip region Rc is adjusted to a predetermined positional relationship, the positional relationship of the base region Rb and chip region Rc in any other pair is also formed to be predetermined. Therefore, in the bonding step, the chip region Rc, which was separated into individual pieces in the separation step, can be collectively positioned so that the positional relationship of each chip region Rc with the multiple base region Rb provided on the first bonding target G1 is predetermined. In this embodiment, positioning marks Pt (see Figure 9(A)) provided on the first bonding target G1 and the second bonding target G2 are used as means for such positioning. The combination of the shape of the positioning mark Pt on the first bonding target G1 side and the shape of the positioning mark Pt on the second bonding target G2 side may be a combination of two cross shapes as shown in Figure 9(A), or it may be a combination of different shapes such as a cross shape and a square shape.

[0054] Furthermore, in the separation step described above, by appropriately adjusting the width of the separation section Ed, a suitable gap can be created between adjacent chip regions Rc that allows for cutting of the first bonding target G1. Therefore, in the bonding step, by simply bonding the chip regions Rc that have been separated in the separation step directly to the first bonding target G1, a suitable gap (a gap that allows for cutting of the first bonding target G1) can be created on the first bonding target G1 as well. Thus, a suitable gap can be formed between adjacent chip regions Rc on the first bonding target G1 without having to remove each chip region Rc one by one as in the conventional method. Consequently, processes such as stretching the stretchable sheet and measuring the position of each chip region Rc after stretching become unnecessary. In addition, even after being separated, the chip regions Rc can be handled in the same positional relationship as before separation (i.e., before the separation step), and as a result, handling of the separated chip regions Rc becomes easier.

[0055] Therefore, in the bonding step, the chip regions Rc separated in the separation step can be combined and positioned so that their respective positional relationships with the multiple base regions Rb provided on the first bonding target G1 are predetermined, and then bonded to the multiple base regions Rb. In other words, in the bonding step, the multiple chip regions Rc separated from the second bonding target G2 in the separation step can be combined and bonded (stacked) to the multiple base regions Rb provided on the first bonding target G1 in a single bonding operation.

[0056] This significantly simplifies the manufacturing process compared to the method of bonding (stacking) individual chip regions Rc from the second bonding target G2 to multiple base regions Rb provided on the first bonding target G1 one by one. Specifically, when the first bonding target G1 has N base regions Rb and the second bonding target G2 has N chip regions Rc, bonding (stacking) one chip region Rc to each of the N base regions Rb would require N bonding (stacking) steps, whereas the above manufacturing method only requires one bonding step, thus significantly simplifying the manufacturing process.

[0057] Furthermore, by using plasma or laser cutting in the separation step, high-precision cutting is possible, and in the chip regions Rc separated by the formation of the separation portion Ed, the positional relationship between the circuit within each chip region Rc and its edge (outer edge) can be reduced. Therefore, when joining (stacking) the base region Rb and the chip regions Rc in the joining step, the edge of the chip region Rc may be used as the positioning reference for the second joining target G2 side instead of the positioning mark Pt.

[0058] <Repeating the thinning step and joining step> In this embodiment, when the stacked device 10 to be manufactured is a stack of two or more chip Mcs on a base 11 (see Figure 1), it is necessary to bond two or more chip base materials Gc to the base material Gb. In this case, before proceeding to the cutting step described later, the thinning step, separation step, and bonding step described above are repeatedly executed according to the number of chip base materials Gc to be bonded to the base material Gb. That is, in this embodiment, before performing cutting processing to separate each of the multiple base regions Rb into individual pieces (before executing the cutting step described later) on the base material Gb (first bonding target G1) which has multiple base regions Rb, the thinning step, separation step, and bonding step described above are repeatedly executed to stack chip Mcs (chip regions Rc) on each base region Rb provided on the base material Gb. The process of repeating the thinning step to bonding step will be described in detail below.

[0059] After the bonding step described above, the second support 22 is peeled off the second bonding target G2 (see the upper left diagram in Figure 10(A)). In this embodiment, as described above, the holding force of the second support 22 is adjusted to a size that does not damage the bonded portion between the first bonding target G1 and the second bonding target G2 when the sheet is peeled off. Therefore, there is almost no damage to the bonded portion due to the peeling off of the second support 22. Furthermore, in the first support 21 and the second support 22, protrusions 21b and 22b are formed on their holding surfaces 21a and 22a such that the contact area when the second support 22 holds the second bonding target G2 is smaller than the contact area when the first support 21 holds the first bonding target G1. Therefore, there is a difference in the holding force of the first support 21 and the second support 22 with respect to the bonding target, and as a result there is a difference in peel strength (specifically, the second support 22, which has a smaller contact area, is easier to peel off). Therefore, in this embodiment, it is possible to easily peel off only the second support 22 by utilizing such a difference in holding force (in this case, a difference in peel strength).

[0060] Subsequently, another chip base material Gc is further bonded to the second bond target G2. Specifically, the first bond target G1 to which the second bond target G2 has been bonded in the bonding step described above (see Figures 9(A) and 9(B)) is made into a new first bond target G1, and the other chip base material Gc is made into a new second bond target G2. The thinning of the second bond target G2, as well as the separation step described above (see Figures 5, 7(A), and 7(B)) and bonding step (see Figures 10(A) and 10(B)) are further performed.

[0061] Then, depending on the number of chip base material Gc to be joined, the peeling of the second support 22, thinning of the second joining target G2, separation step (see Figure 5), and joining step (see Figure 10(A)) are repeatedly performed. In this embodiment, since it is necessary to join seven chip base material Gc, after the first joining step (see Figure 9(A)), the above repetition is performed six times in order to further join the second to seventh layers of chip base material Gc. Figure 11(A) is a conceptual diagram showing the state when seven layers of chip base material Gc are joined (laminated) on the base material Gb, and Figure 11(B) is a longitudinal cross-sectional view along the Zd-Zd line shown in Figure 11(A).

[0062] Furthermore, in the bonding steps performed in this iterative process, instead of positioning marks Pt, the edges of the chip regions Rc included in the new first bonding target G1 and the edges of the chip regions Rc of the new second bonding target G2 that are stacked on top of those chip regions Rc can be used as the reference for positioning the new second bonding target G2 relative to the new first bonding target G1.

[0063] With this iterative process, even when multiple chip base materials Gc are bonded (stacked) to the first bonding target G1 (base base material Gb) as the second bonding target G2, all chip regions Rc provided on each chip base material Gc can be bonded (stacked) together in a single bonding operation. Specifically, when the first bonding target G1 (base base material Gb) has N base regions Rb and the second bonding target G2 (chip base material Gc) has N chip regions Rc, stacking one chip region Rc on each of the N base regions Rb three-dimensionally M times would require N × M stacking operations. However, with the above iterative process, only M bonding operations are required, thus significantly simplifying the manufacturing process of the stacked device 10.

[0064] Then, by performing this repeated process, as shown in Figure 11(B), chip regions Rc (chip Mc) are stacked three-dimensionally from the 1st to the 7th layer on each base region Rb provided in the base material Gb, thereby forming a chip stack 12. In addition, a suitable gap (i.e., a gap that allows cutting of the base material Gb) is formed between adjacent chip stacks 12, created by the separation portion Ed.

[0065] <Cutting Step> In the cutting process, the gaps formed between the chip stacks 12 are used to cut the base material Gb (in the example in Figure 11(B), the base material Gb is cut at the position indicated by the dashed line), thereby separating multiple base regions Rb into individual pieces. This completes the stacked device 10 (see Figure 1).

[0066] [2] Variant [2-1] First variation In the manufacturing method of the stacked device 10 described above, in the separation step, two cutting lines Ld may be formed such that the PCM (Process Control Monitor) is located between the two cutting lines Ld. Alternatively, the PCM may be formed so that it is located between the two cutting lines Ld formed in the separation step.

[0067] According to the configuration of the first modified example, when the unnecessary portion between the two cutting lines Ld is removed, the PCM (specifically, the circuit elements that make up the PCM) can also be removed together. Therefore, there is no need to provide a separate process for removing the PCM in advance (such as removal by irradiation with laser light), and the manufacturing process of the stacked device 10 can be simplified.

[0068] [2-2] Second variation In the manufacturing method of the stacked device 10 described above, in the separation step, plasma etching may be performed over the entire formation region of the separation portion Ed to form an etched region of a predetermined width Wt etched by plasma as the separation portion Ed.

[0069] [2-3] Third variation In the manufacturing method of the stacked device 10 described above, an inspection step and a replacement step may be further performed. Here, the inspection step and the replacement step are performed after the separation step and before the bonding step. In the inspection step, each chip region Rc separated in the separation step is inspected to see whether or not that chip region Rc is defective. If a defective product is detected in the inspection step, the defective product is replaced with a good product in the replacement step.

[0070] As described in the above embodiment, in the separation step, multiple chip regions Rc provided in the chip base material Gc are separated into individual chips with an appropriate gap between adjacent chip regions Rc. Therefore, from the multiple chip regions Rc separated in the separation step, one chip region Rc can be easily removed in its original state (i.e., without widening the distance between adjacent chip regions Rc using an expandable sheet or the like) without contacting the adjacent chip region Rc. Thus, in the configuration of the third modified example, this is utilized to replace defective products with good products, thereby increasing the yield (good product rate) of the stacked device 10.

[0071] [2-4] Fourth variation In the manufacturing method of the stacked device 10 described above, the stacked device 10 to be manufactured may be appropriately modified to one in which chips Mc of different sizes are stacked on a base 11. In this case, when joining (stacking) the second and subsequent chip base materials Gc (second bonding target G2) in the repeated process, the width of the separation portion Ed (predetermined width Wt) formed on the chip base material Gc in the separation step can be appropriately changed for each layer, thereby making the sizes of the stacked chips Mc different.

[0072] Figure 12 is a conceptual longitudinal cross-sectional view illustrating the state when a chip base material Gc (second bonding target G2) is bonded (laminated) up to the second layer on a base material Gb (first bonding target G1) in the fourth modified example. In the example in Figure 12, the width of the separation portion Ed formed in the second layer of chip base material Gc (predetermined width Wt=Wt2) is made larger than the width of the separation portion Ed formed in the first layer of chip base material Gc (predetermined width Wt=Wt1), so that the size of the chip Mc (fragmented chip region Rc) obtained from the second layer of chip base material Gc is smaller than the size of the chip Mc (fragmented chip region Rc) obtained from the first layer of chip base material Gc.

[0073] [2-5] Fifth variation In the manufacturing method of the stacked device 10 described above, the stacked device 10 to be manufactured is not limited to one in which chip Mc is stacked three-dimensionally at only one location on the base 11 (see Figure 1), but may be appropriately modified to one in which chip Mc is stacked three-dimensionally at multiple locations on the base 11. In this case, the base region Rb provided on the base material Gb (first bonding target G1) and the chip region Rc provided on the chip material Gc (second bonding target G2) are formed such that multiple chip regions Rc correspond to the base region Rb in a predetermined positional relationship.

[0074] [2-6] Sixth variation In the manufacturing method of the stacked device 10 described above, in the separation step, the second bonding target G2 (chip base material Gc) thinned in the thinning step may be held on some substrate (such as a wafer or glass substrate), and in that state, a separation portion Ed may be formed using plasma or laser light. After the formation of the separation portion Ed, before proceeding to the next bonding step, the chip region Rc separated by the formation of the separation portion Ed may be transferred directly from the substrate to the second support 22.

[0075] [2-7] Seventh variation In the manufacturing method of the stacked device 10 described above, the thinning of the second bonding target G2 (chip base material Gc) and the formation of the separated portion Ed may be achieved by the following process instead of the thinning step and separation step described above.

[0076] Figures 13(A) to 13(C) are conceptual diagrams showing alternative processes that can be performed instead of the thinning and separation steps described above. As shown in Figure 13(A), before thinning the second bonding target G2 (chip base material Gc), the second bonding target G2 is subjected to a cutting process using plasma or laser light to form grooves Qd that will become two cutting lines Ld for forming the separation section Ed to the depth that will be exposed by thinning. Next, as shown in Figure 13(B), the second bonding target G2 is transferred to some substrate or holding sheet, and then the second bonding target G2 is thinned from the side opposite to the side on which the grooves Qd were formed. Then, as shown in Figure 13(C), the grooves Qd are exposed on the opposite side, thereby transforming the grooves Qd into cutting lines Ld. After that, the separation section Ed is completed by removing the unnecessary portion between the two cutting lines Ld thus formed (see Figure 8(C)). Furthermore, in the step of forming groove Qd by cutting using plasma or laser light (see Figure 13(A)), instead of forming groove Qd which will become the two cutting lines Ld, grooves which will become the etching regions as described in the second modified example may be formed.

[0077] [2-8] Other variations In the manufacturing method of the stacked device 10 described above, dicing tape may be used as appropriate for the first support 21 and the second support 22.

[0078] The above-described embodiments and modifications should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims, rather than by the above-described embodiments and modifications. Furthermore, the scope of the present invention is intended to include all modifications within the meaning and scope equivalent to the claims.

[0079] Furthermore, from the above-described embodiments and modifications, several steps constituting the manufacturing method of the stacked device 10 may be partially extracted as the subject of the invention, or each step may be extracted individually. [Explanation of Symbols]

[0080] 10 Stacked Devices 11 Bass 12-chip stack 21 First support 22 Second support 21a, 22a holding surface 21b, 22b protrusions 21c, 22c contact surface Ed separation part G1 First Joining Target G2 Second Joining Target Gb base material Gc chip base material Ld cutting line Mc Chip Pt positioning mark Qd groove Rb base region Rc chip area Wt Specified width

Claims

1. With respect to a first joining target having multiple base regions, while holding it with a first support, before performing a cutting process to separate each of the multiple base regions into individual pieces, A separation step is performed to separate adjacent chip regions by a predetermined width, while holding a second bonding target having multiple chip regions with a second support, and applying a cutting process using plasma or laser light to the second bonding target, thereby separating each of the multiple chip regions into individual pieces. After the separation step is performed, an inspection step is performed to check whether each of the chip regions separated in the separation step is a defective product. A replacement step is performed in which, if a defective product is detected in the inspection step, the defective product is replaced with a good product. After the substitution step is performed, the second bonding target is bonded to the first bonding target by moving the second support relative to the first support while the first bonding target is held by the first support, so that at least one chip region corresponding to each base region is stacked in a predetermined positional relationship for each base region. A method for manufacturing stacked devices.

2. With respect to a first joining target having multiple base regions, while holding it with a first support, before performing a cutting process to separate each of the multiple base regions into individual pieces, A separation step is performed to separate adjacent chip regions by a predetermined width, while holding a second bonding target having multiple chip regions with a second support, and applying a cutting process using plasma or laser light to the second bonding target, thereby separating each of the multiple chip regions into individual pieces. A bonding step in which the second bonding target is bonded to the first bonding target by moving the second support relative to the first support while the first bonding target is held by the first support, so that at least one of the chip regions corresponding to each base region is stacked in a predetermined positional relationship for each base region, Execute, A method for manufacturing a laminated device, wherein both the first support and the second support include a holding sheet mainly composed of a resin or rubber having at least adhesive force, and the holding sheet is provided with a plurality of protrusions on the holding surface that holds the first and second bonding targets, respectively.

3. The method for manufacturing a laminated device according to claim 2, wherein the holding surface has the protrusions formed such that the contact area between the second support and the second object to be joined when the second object to be joined is held by the second support is smaller than the contact area between the first object to be joined and the first support.

4. A method for manufacturing a stacked device according to any one of claims 1 to 3, wherein after the bonding step, the second support is peeled off from the second bonding target, and another bonding target having a plurality of chip regions is further bonded to the second bonding target, A method for manufacturing a stacked device, comprising: further performing the separation step and the joining step, wherein the first object to be joined in the joining step is made a new first object to be joined, and the other object to be joined is made a new second object to be joined.

5. A thinning step is performed before the separation step to thin the second object to be joined. A method for manufacturing a stacked device according to any one of claims 1 to 3, further comprising the method described above.

6. A method for manufacturing a stacked device according to any one of claims 1 to 3, wherein in the separation step, two parallel cutting lines are formed, and the portion between the two cutting lines is removed to form the separated portion.

7. The method for manufacturing a stacked device according to claim 6, wherein in the separation step, the two cutting lines are formed such that a PCM (Process Control Monitor) is located between the two cutting lines.

8. A method for manufacturing a stacked device according to any one of claims 1 to 3, wherein in the separation step, an etching region of a predetermined width etched with plasma is formed as the separation portion.

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