memory devices

Abstract

To provide a memory device that increases the storage capacity or expands the read margin.SOLUTION: A memory device of an embodiment includes a first memory cell and a sequencer. The first memory cell is configured to store a plurality of bit data at k threshold voltage levels (k is an integer equal to or greater than 2). The sequencer is configured to execute a writing operation with a loop processing, including a programming operation and a verifying operation. The programming operation includes a first programming process and a second programming process. The sequencer stores data in the first memory cell by either of the first programming process and the second programming process according to the data to be written to the first memory cell during the writing operation.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments relate to a memory device.

Background Art

[0002] A NAND flash memory capable of nonvolatilely storing data is known.

Prior Art Literature

Patent Documents

[0003]

Patent Document 1

Summary of Invention

Problems to be Solved by the Invention

[0004] To increase the storage capacity or expand the read margin of a memory device.

Means for Solving the Problems

[0005] A memory device of an embodiment includes a first memory cell and a sequencer. The first memory cell is configured to store multi-bit data with k threshold voltage levels, where k is an integer of 2 or more. The sequencer is configured to execute a write operation including loop processing that contains a program operation and a verify operation. The program operation includes a first program process and a second program process. In the write operation, the sequencer causes the first memory cell to store data by one of the first program process and the second program process in accordance with data to be written to the first memory cell.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing an example of the configuration of the memory device according to the first embodiment. [Figure 2]A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 3] A circuit diagram showing an example of the circuit configuration of a low decoder module included in a memory device according to the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of a sense amplifier module included in a memory device according to the first embodiment. [Figure 5] A plan view showing an example of a planar layout of a memory cell array included in a memory device according to the first embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory cell array provided in a memory device according to the first embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar in a memory device according to the first embodiment. [Figure 8] A schematic diagram showing an example of the data storage area of ​​a NAND string provided in a memory device according to the first embodiment. [Figure 9] A distribution diagram showing an example of the threshold voltage distribution of memory cell transistors in a memory device according to the first embodiment. [Figure 10] A table showing an example of data allocation used in a memory device according to the first embodiment. [Figure 11] A time chart showing an overview of the writing operation of the memory device according to the first embodiment. [Figure 12] A flowchart showing an example of the writing operation of a memory device according to the first embodiment. [Figure 13] A schematic diagram showing a specific example of the “ACE” program for a memory device according to the first embodiment. [Figure 14] A schematic diagram showing a specific example of the “BDFG” program for a memory device according to the first embodiment. [Figure 15] A timing chart showing an example of lower page readout of a memory device according to the first embodiment. [Figure 16]A timing chart showing an example of middle page reading of the memory device according to the first embodiment. [Figure 17] A timing chart showing an example of upper page reading of the memory device according to the first embodiment. [Figure 18] A graph showing an example of IV characteristics of a memory cell transistor in a memory device according to a comparative example. [Figure 19] A graph showing an example of IV characteristics of a memory cell transistor in the memory device according to the first embodiment. [Figure 20] A table showing an example of data allocation in a modification of the first embodiment. [Figure 21] A timing chart showing an example of lower page reading in a modification of the first embodiment. [Figure 22] A timing chart showing an example of middle page reading in a modification of the first embodiment. [Figure 23] A timing chart showing an example of upper page reading in a modification of the first embodiment. [Figure 24] A distribution diagram showing an example of threshold voltage distribution of memory cell transistors included in the memory device according to the second embodiment. [Figure 25] A flowchart showing an example of a write operation of the memory device according to the second embodiment. [Figure 26] A graph showing an example of IV characteristics of a memory cell transistor in the memory device according to the second embodiment. [Figure 27] A cross-sectional view showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the third embodiment. [Figure 28] A cross-sectional view taken along line XXVIII-XXVIII of Figure 27, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the third embodiment. [Figure 29] A cross-sectional view taken along line XXIX-XXIX of Figure 27, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the third embodiment. [Figure 30]Schematic diagram showing an example of a data storage area of a NAND string included in the memory device according to the third embodiment. [Figure 31] Graph showing an example of IV characteristics of a memory cell transistor included in the memory device according to the third embodiment. [Figure 32] Flowchart showing an example of a write operation of the memory device according to the third embodiment. [Figure 33] Schematic diagram showing a specific example of HE programming for a selected string in the memory device according to the third embodiment. [Figure 34] Schematic diagram showing a specific example of HE programming for an unselected string in the memory device according to the third embodiment. [Figure 35] Schematic diagram showing a specific example of FN programming for a selected string in the memory device according to the third embodiment. [Figure 36] Schematic diagram showing a specific example of FN programming for an unselected string in the memory device according to the third embodiment. [Figure 37] Flowchart showing an example of a manufacturing method of the memory device according to the third embodiment. [Figure 38] Cross-sectional view showing an example of a cross-sectional structure in the middle of manufacturing the memory device according to the third embodiment. [Figure 39] Cross-sectional view taken along line XXXIX-XXXIX of FIG. 38, showing an example of a cross-sectional structure in the middle of manufacturing the memory device according to the third embodiment. [Figure 40] Cross-sectional view showing an example of a cross-sectional structure in the middle of manufacturing the memory device according to the third embodiment. [Figure 41] Cross-sectional view taken along line XXXXI-XXXXI of FIG. 40, showing an example of a cross-sectional structure in the middle of manufacturing the memory device according to the third embodiment. [Figure 42] Cross-sectional view showing an example of a cross-sectional structure in the middle of manufacturing the memory device according to the third embodiment. [Figure 43] Cross-sectional view taken along line XXXXIII-XXXXIII of FIG. 42, showing an example of a cross-sectional structure in the middle of manufacturing the memory device according to the third embodiment. [Figure 44] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 45] A cross-sectional view along the line XXXXV-XXXXV in Figure 44, showing an example of a cross-sectional structure of a memory device during manufacturing according to the third embodiment. [Figure 46] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 47] A cross-sectional view along the line XXXXVII-XXXXVII in Figure 46, showing an example of a cross-sectional structure of a memory device during manufacturing according to the third embodiment. [Figure 48] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 49] A cross-sectional view along the line XXXXIX-XXXXIX in Figure 48, showing an example of a cross-sectional structure of a memory device during manufacturing according to the third embodiment. [Figure 50] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 51] A cross-sectional view along the LI-LI line in Figure 50, showing an example of a cross-sectional structure of a memory device during manufacturing according to the third embodiment. [Figure 52] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 53] A cross-sectional view along the line LIII-LIII in Figure 52, showing an example of a cross-sectional structure of a memory device during manufacturing according to the third embodiment. [Figure 54] A cross-sectional view along the LIV-LIV line in Figure 52, showing an example of a cross-sectional structure of a memory device during manufacturing according to the third embodiment. [Figure 55] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the fourth embodiment. [Figure 56] A plan view showing an example of a planar layout of a memory cell array included in a memory device according to the fourth embodiment. [Figure 57] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array provided in a memory device according to the fourth embodiment. [Figure 58] A cross-sectional view showing an example of the cross-sectional structure of a memory pillar in a memory device according to the fourth embodiment. [Figure 59] A cross-sectional view along the LIX-LIX line in Figure 58, showing an example of the cross-sectional structure of a memory pillar in the memory device according to the fourth embodiment. [Figure 60] A schematic diagram showing a specific example of an HE program for a selected memory group in a memory device according to the fourth embodiment. [Figure 61] A schematic diagram showing a specific example of an HE program for a non-selected memory group in a memory device according to the fourth embodiment. [Figure 62] A schematic diagram showing a specific example of an FN program for a selected memory group in a memory device according to the fourth embodiment. [Figure 63] A schematic diagram showing a specific example of an FN program for a non-selected memory group in a memory device according to the fourth embodiment. [Figure 64] A flowchart showing an example of a method for manufacturing a memory device according to the fourth embodiment. [Figure 65] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 66] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 67] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 68] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 69] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 70] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 71] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 72]A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and proportions in each drawing are not necessarily the same as those in reality. The illustration of the components is omitted where appropriate. Hatching added to the plan views is not necessarily related to the material or properties of the components. In this specification, components having substantially the same function and configuration are assigned the same reference numeral. Numbers and letters added to reference numerals are used to distinguish between elements that are referred to by the same reference numeral and are similar to each other.

[0008] <1> First Embodiment The memory device 1 according to the first embodiment performs a write operation that can write the S-factor state of the memory cell in two different ways. The memory device 1 according to the first embodiment reads multiple bits of data from the memory cell using two different sense times. The details of the memory device 1 according to the first embodiment are described below.

[0009] <1-1> Composition First, the configuration of the memory device 1 according to the first embodiment will be described.

[0010] <1-1-1> Configuration of Memory Device 1 Figure 1 is a block diagram showing an example of the configuration of a memory device 1 according to the first embodiment. As shown in Figure 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of storing data non-volatilely. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where "n" is an integer of 1 or more). A block BLK is a collection of multiple memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes multiple pages. A page corresponds to a unit in which data is read or written. Although not shown in the diagram, the memory cell array 10 is provided with multiple bit lines BL0 to BLm (where "m" is an integer of 1 or more) and multiple word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL. Each block BLK is assigned a block address. Each bit line BL is assigned a column address. Each word line WL is assigned a page address.

[0012] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals to and from the memory controller 2. These input / output signals include, for example, data, status information, address information, and commands. The input / output circuit 11 can input and output data to and from the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13, respectively.

[0013] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on the control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal it has received is a command or address information. The logic controller 12 commands the input / output circuit 11 to input or output the input / output signal.

[0014] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes block addresses, page addresses, column addresses, etc. The commands include instructions for various operations of the memory device 1.

[0015] The sequencer 14 controls the overall operation of the memory device 1. Based on the commands and address information stored in the register circuit 13, the sequencer 14 performs read operations, write operations, erase operations, etc.

[0016] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the raw decoder module 16, sense amplifier module 17, and other components.

[0017] The row decoder module 16 is a circuit used for selecting the block BLK to operate on and for transferring voltage to wiring such as word lines WL. The row decoder module 16 includes multiple row decoders RD0 to RDn. Each row decoder RD0 to RDn is associated with a block BLK0 to BLKn.

[0018] The sense amplifier module 17 is a circuit used for transferring voltage to each bit line BL and reading data. The sense amplifier module 17 includes multiple sense amplifier units SAU0 to SAUm. Each of the sense amplifier units SAU0 to SAUm is associated with multiple bit lines BL0 to BLm.

[0019] The combination of memory device 1 and memory controller 2 may constitute a single semiconductor device. For example, an SD card is one such semiconductor device. TM Examples include memory cards and SSDs (solid state drives).

[0020] <1-1-2> Circuit configuration of memory device 1 Next, the circuit configuration of the memory device 1 according to the first embodiment will be described.

[0021] (Circuit configuration of memory cell array 10) Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array 10 provided in a memory device 1 according to the first embodiment. Figure 2 shows one of several block BLKs included in the memory cell array 10. As shown in Figure 2, the block BLK includes, for example, five string units SU0 to SU4. Selection gate lines SGD0 to SGD4 and SGS and word lines WL0 to WL7 are provided for each block BLK. Bit lines BL0 to BLm and source line SL are shared, for example, by multiple block BLKs.

[0022] Each string unit SU includes a plurality of NAND strings NS. Each of the plurality of NAND strings NS is associated with a bit line BL0 to BLm. Each NAND string NS is connected between the associated bit line BL and the source line SL. Each NAND string NS includes, for example, memory cell transistors MC0 to MC7 and selection transistors ST1 and ST2. Each memory cell transistor MC is a transistor having a control gate and a charge storage layer, which holds (stores) data nonvolatilically. The memory cell transistor MC in the first embodiment is a charge trap type memory cell. Selection transistors ST1 and ST2 are used for selecting the string unit SU, respectively.

[0023] In each NAND string NS, the selection transistor ST1, memory cell transistors MC7 to MC0, and selection transistor ST2 are connected in series. Specifically, the drain and source terminals of selection transistor ST1 are connected to the associated bit line BL and the drain terminal of memory cell transistor MC7, respectively. The drain and source terminals of selection transistor ST2 are connected to the source terminal of memory cell transistor MC0 and the source line SL, respectively. Memory cell transistors MC0 to MC7 are connected in series between selection transistors ST1 and ST2.

[0024] The selection gate lines SGD0 to SGD4 are associated with string units SU0 to SU4, respectively. Each selection gate line SGD is connected to the gate terminal of each of the multiple selection transistors ST1 contained in the associated string unit SU. The selection gate line SGS is connected to the gate terminal of each of the multiple selection transistors ST2 contained in the associated block BLK. The word lines WL0 to WL7 are connected to the control gate terminals of each of the memory cell transistors MC0 to MC7 of each NAND string NS contained in the associated block BLK, respectively.

[0025] A collection of multiple memory cell transistors MC connected to a common word line WL within the same string unit SU is called, for example, a “cell unit CU”. For example, the storage capacity of a cell unit CU when each memory cell transistor MC stores 1 bit of data is defined as “1 page of data”. A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by each memory cell transistor MC.

[0026] The circuit configuration of the memory cell array 10 provided in the memory device 1 according to the first embodiment may be any other configuration. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MC and selection transistors ST1 and ST2 included in each NAND string NS can be designed to any number.

[0027] (Circuit configuration of the low decoder module 16) Figure 3 is a circuit diagram showing an example of the circuit configuration of a row decoder module 16 provided in the memory device 1 according to the first embodiment. Figure 3 shows the connection relationships between the row decoder module 16 and the driver circuit 15 and the memory cell array 10, respectively, and the detailed circuit configuration of the row decoder RD0. As shown in Figure 3, each row decoder RD is connected to the driver circuit 15 via, for example, signal lines CG0~CG7, SGDD0~SGDD4, SGSD, USGD, and USGS. Each row decoder RD is connected to its associated block BLK via, for example, word lines WL0~WL7 and selection gate lines SGS and SGD0~SGD4.

[0028] The following describes the connection relationships between each element of the row decoder RD, the driver circuit 15, and the block BLK0, focusing on the row decoder RD0. Note that the configuration of other row decoders RD is the same as row decoder RD0, except that the associated block BLK is different. Row decoder RD0 includes, for example, transistors TR0 to TR19, transfer gate lines TG and bTG, and block decoder BD.

[0029] Each of the transistors TR0 to TR19 is a high-voltage N-type MOS transistor (hereinafter also referred to as a "high-voltage transistor"). In this specification, the threshold voltage of the high-voltage transistors is designed to be 10V or higher. The drain and source terminals of transistor TR0 are connected to the signal line SGSD and the select gate line SGS, respectively. The drain terminals of each of the transistors TR1 to TR8 are connected to the signal lines CG0 to CG7, respectively. The source terminals of each of the transistors TR1 to TR8 are connected to the word lines WL0 to WL7, respectively. The drain terminals of each of the transistors TR9 to TR13 are connected to the signal lines SGDD0 to SGDD4, respectively. The source terminals of each of the transistors TR9 to TR13 are connected to the select gate lines SGD0 to SGD4, respectively. The drain and source terminals of transistor TR14 are connected to the signal line USGS and the select gate line SGS, respectively. The drain terminals of each of the transistors TR15 to TR19 are connected to the signal line USGD. The source terminals of transistors TR15 to TR19 are connected to the select gate lines SGD0 to SGD4, respectively. The gate terminals of transistors TR0 to TR13 are connected to the transfer gate line TG. The gate terminals of transistors TR14 to TR19 are connected to the transfer gate line bTG. The inverted signal of the signal input to transfer gate line TG is input to transfer gate line bTG.

[0030] The block decoder BD is a circuit that has the function of decoding a block address. Based on the decoding result of the block address, the block decoder BD applies predetermined voltages to the transfer gate lines TG and bTG, respectively. Specifically, the block decoder BD corresponding to the selected block BLK applies "H" level and "L" level voltages to the transfer gate lines TG and bTG, respectively. The block decoder BD corresponding to the unselected block BLK applies "L" level and "H" level voltages to the transfer gate lines TG and bTG, respectively. As a result, the voltages of signal lines CG0 to CG7 are transferred to the word lines WL0 to WL7 of the selected block BLK, respectively; the voltages of signal lines SGDD0 to SGDD4 and SGSD are transferred to the selected gate lines SGD0 to SGD4 and SGS of the selected block BLK, respectively; and the voltages of signal lines USGD and USGS are transferred to the selected gate lines SGD and SGS of the unselected block BLK, respectively.

[0031] The raw decoder module 16 may have other circuit configurations. For example, the number of transistors TR included in the raw decoder module 16 can be changed according to the number of wires provided in each block BLK. The signal line CG may be called a "global word line" because it is shared among multiple block BLKs. The word line WL may be called a "local word line" because it is provided for each block. The signal lines SGDD and SGSD may each be called "global transfer gate lines" because they are shared among multiple block BLKs. The selection gate lines SGD and SGS may each be called "local transfer gate lines" because they are provided for each block BLK.

[0032] (Circuit configuration of sense amplifier module 17) Figure 4 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module 17 included in the memory device 1 according to the first embodiment. Figure 4 shows an extracted circuit configuration of one sense amplifier unit SAU. As shown in Figure 4, the sense amplifier unit SAU includes, for example, a sense amplifier section SA, a bit line connection section BLHU, latch circuits SDL, ADL, BDL, CDL and XDL, and a bus LBUS. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL and XDL are configured to transmit and receive data via, for example, the bus LBUS.

[0033] The sense amplifier section SA is a circuit used for determining data based on the voltage of the bit line BL and for applying voltage to the bit line BL. When the control signal STB is asserted during a read operation, the sense amplifier section SA determines whether the data read from the selected memory cell transistor MC is "0" or "1" based on the voltage of the associated bit line BL. The latch circuits SDL, ADL, BDL, CDL, and XDL are circuits capable of temporarily holding data. The latch circuit XDL is used for input and output of data DAT between the sense amplifier unit SAU and the input / output circuit 11. The latch circuit XDL can also be used as a cache memory. The latch circuit XDL may be configured to be shareable by multiple sense amplifier units SAU.

[0034] The sense amplifier section SA includes transistors T0 to T7, capacitor CP, and nodes ND, SEN, and SRC. The bit line connection section BLHU is a switch circuit to prevent the high voltage applied to the channel of the NAND string NS during the erase operation from being applied to the sense amplifier section SA. The bit line connection section BLHU includes transistor T8. The latch circuit SDL includes inverters IV0 and IV1, transistors T10 and T11, and nodes SINV and SLAT. Transistor T0 is a P-type MOS transistor. Transistors T1 to T8, T10, and T11 are N-type MOS transistors, respectively. Transistor T8 is an N-type high-voltage transistor.

[0035] The gate terminal of transistor T0 is connected to node SINV. The source terminal of transistor T0 is connected to the power line. The drain terminal of transistor T0 is connected to the source terminal of transistor T1. The source terminal of transistor T1 is connected to node ND. The drain terminal of transistor T2 is connected to the power line. The source terminal of transistor T2 is connected to node SEN. Node SEN is connected to the drain terminal of transistor T3, the gate terminal of transistor T6, and one electrode of capacitor CP, respectively. The source terminal of transistor T3 is connected to node ND. Node ND is connected to the drain terminals of transistors T4 and T5, respectively. The source terminal of transistor T4 is connected to the drain terminal of transistor T8. The source terminal of transistor T8 is electrically connected to the associated bit line BL. The source terminal of transistor T5 is connected to node SRC. The gate terminal of transistor T5 is connected to node SINV. The source terminal of transistor T6 is connected to the ground node. The drain and source terminals of transistor T7 are connected to the bus LBUS and the drain terminal of transistor T6, respectively.

[0036] For example, the power supply voltage VDD is applied to the source terminal of transistor T0. For example, the ground voltage VSS is applied to node SRC. Control signals BLX, PRE, XXL, BLC, and STB are input to the gate terminals of transistors T1, T2, T3, T4, and T7, respectively. The control signal BLS is input to the gate terminal of transistor T8. The clock signal CLK is input to the other electrode of capacitor CP.

[0037] The input and output nodes of inverter IV0 are connected to nodes SLAT and SINV, respectively. The input and output nodes of inverter IV1 are connected to nodes SINV and SLAT, respectively. One end and the other end of transistor T10 are connected to node SINV and bus LBUS, respectively. The control signal STINV is input to the gate terminal of transistor T10. One end and the other end of transistor T11 are connected to node SLAT and bus LBUS, respectively. The control signal STLAT is input to the gate terminal of transistor T11. The latch circuit SDL holds data in node SLAT and holds the inverted data of the data held in node SLAT in node SINV.

[0038] The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are similar to those of latch circuit SDL. For example, latch circuit ADL holds data at node ALAT and its inverted data at node AINV. The control signal ATINV is input to the gate terminal of transistor T10 of latch circuit ADL, and the control signal ATLAT is input to the gate terminal of transistor T11 of latch circuit ADL. Latch circuit BDL holds data at node BLAT and its inverted data at node BINV. The control signal BTINV is input to the gate terminal of transistor T10 of latch circuit BDL, and the control signal BTLAT is input to the gate terminal of transistor T11 of latch circuit BDL. The same applies to latch circuits CDL and XDL, so their explanation is omitted.

[0039] The control signals BLX, PRE, XXL, BLC, STB, BLS, STINV, and STLAT are each generated, for example, by the sequencer 14. The sense amplifier module 17 may have other circuit configurations. For example, the number of latch circuits in each sense amplifier unit SAU may be changed according to the number of bits stored in the memory cell transistor MC. The sense amplifier unit SAU may have an arithmetic circuit capable of performing simple logic operations. The sense amplifier module 17 can determine (determine) the data stored in the memory cell transistor MC by appropriately performing arithmetic processing using the latch circuit during the read operation of each page.

[0040] <1-1-3> Structure of memory device 1 Next, the structure of the memory device 1 according to the first embodiment will be described. In the drawings referenced below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the perpendicular direction with respect to the surface of the reference substrate.

[0041] (Planar layout of memory cell array 10) Figure 5 is a plan view showing an example of a planar layout of a memory cell array 10 provided in a memory device 1 according to the first embodiment. Figure 5 shows a region containing one block BLK (string units SU0 to SU4). As shown in Figure 5, the memory cell array 10 includes a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of contacts CT, and a plurality of bit lines BL. Each slit SLT includes a contact LIC and a spacer SP.

[0042] Each slit SLT has a portion that extends along the X direction. Multiple slit SLTs are aligned in the Y direction. Each slit SLT has a structure in which, for example, an insulator or a plate-shaped contact is embedded. Each slit SLT separates adjacent wiring (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. In the memory cell array 10, each region separated by a slit SLT corresponds to one block BLK.

[0043] Each slit SHE has a portion that extends along the X direction. Multiple slit SHEs are arranged in the Y direction. In this example, four slit SHEs are positioned between each of two adjacent slits SLT in the Y direction. Each slit SHE has a structure, for example, an insulator embedded in it. Each slit SHE separates adjacent wiring (at least selected gate lines SGD) through it. In the memory cell array 10, each region separated by slits SLT and SHE corresponds to one string unit SU.

[0044] Each memory pillar MP functions as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 24 rows, in the region between two adjacent slits SLT. For example, counting from the top of the paper, one slit SHE is placed overlapping the 5th, 10th, 15th, and 20th memory pillar MPs.

[0045] Each bit line BL is a conductor having a portion extending in the Y direction. Multiple bit lines are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are positioned overlapping on one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CT. Note that the contact CT between the memory pillar MP and the bit line BL that are in contact with two different selection gate lines SGD may be omitted.

[0046] The contact LIC is a conductor having a portion extending in the X direction. The spacer SP is an insulator provided on the side surface of the contact LIC. In the illustrated region, the contact LIC is sandwiched in the Y direction by the spacer SP. The contact LIC and the conductors adjacent to it in the Y direction (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) are separated and insulated by the spacer SP. The spacer SP is, for example, an oxide film.

[0047] The planar layout of the memory cell array 10 may be any other layout. For example, the number and arrangement of memory pillars MP and slits SHE placed between two adjacent slits SLT can be changed as appropriate. The number of string units SU in each block BLK can be changed based on the number of slits SHE between two adjacent slits SLT. The number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0048] (Cross-sectional structure of memory cell array 10) Figure 6 is a cross-sectional view along line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory cell array 10 provided in a memory device 1 according to the first embodiment. As shown in Figure 6, the memory cell array 10 includes, for example, a semiconductor substrate 20, conductive layers 21-24, and insulating layers 30-34. In the following description, the direction away from the front surface of the semiconductor substrate 20 is considered the positive direction (upward). The front surface of the substrate corresponds to the side on which elements such as transistors (CMOS circuits) are formed. The back surface of the substrate corresponds to the side opposite to the front surface.

[0049] The semiconductor substrate 20 is, for example, a P-type silicon substrate. An insulating layer 30 is provided on the semiconductor substrate 20. A conductive layer 21 is provided on the insulating layer 30. Insulating layers 31 and conductive layers 22 are alternately stacked on the conductive layer 21. An insulating layer 32 is provided on the uppermost conductive layer 22. A conductive layer 23 is provided on the insulating layer 32. An insulating layer 33 is provided on the conductive layer 23. A conductive layer 24 is provided on the insulating layer 33. An insulating layer 34 is provided on the conductive layer 24. Wiring and contacts for connecting the memory cell array 10, the low decoder module 16, and the sense amplifier module 17 are provided on the wiring layer on which the insulating layer 34 is formed, although these are not shown in the figure.

[0050] Each of the conductive layers 21, 22, and 23 has a portion formed in a plate shape extending along the XY plane. Conductive layer 24 has a portion formed in a line shape extending along the Y direction. Conductive layer 21 is used as the selection gate line SGS. The multiple conductive layers 22 are used in order from bottom to top as word lines WL0 to WL7, respectively. Conductive layer 23 is used as the selection gate line SGD. Conductive layer 24 is used as the bit line BL. Each of the conductive layers 21, 22, and 23 contains, for example, tungsten. Conductive layer 24 contains, for example, copper.

[0051] Each memory pillar MP is provided extending along the Z direction. Each memory pillar MP penetrates the insulating layers 30-32 and the conductive layers 21-23. The bottom of the memory pillar MP reaches the semiconductor substrate 20. The portion where the memory pillar MP intersects with the conductive layer 21 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with one conductive layer 22 functions as a memory cell transistor MC. The portion where the memory pillar MP intersects with the conductive layer 23 functions as a selection transistor ST1.

[0052] Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is provided stretched along the Z direction. The semiconductor layer 41 covers the periphery of the core member 40. The bottom of the semiconductor layer 41 is in contact with the semiconductor substrate 20. The laminated film 42 covers the sides and bottom of the semiconductor layer 41, except for the portion where the semiconductor layer 41 and the semiconductor substrate 20 are in contact. The core member 40 includes an insulator such as silicon oxide. The semiconductor layer 41 includes, for example, silicon.

[0053] The contact CTs are arranged in a columnar shape extending along the Z direction. Each contact CT is provided on the semiconductor layer 41 of the corresponding memory pillar MP. One conductive layer 24 is in contact with each contact CT. Each conductive layer 24 is electrically connected to, for example, a memory pillar MP provided between adjacent slits SLT and SHE, and a memory pillar MP provided between two adjacent slits SHE.

[0054] The slit SLT has, for example, a portion provided along the XZ plane, separating the conductive layers 21-23 and the insulating layers 30-32. The contact LIC within the slit SLT is provided along the slit SLT. The upper end of the contact LIC is located at the height between the upper end of the memory pillar MP and the conductive layer 24. The lower end of the contact LIC is in contact with the semiconductor substrate 20. The semiconductor substrate 20 has an impurity diffusion region in the portion in contact with the contact LIC. The contact LIC is used, for example, as part of the source line SL. The spacer SP insulates the contact LIC from the conductive layers 21-23.

[0055] The slit SHE has, for example, a portion provided along the XZ plane and divides the conductive layer 23. The upper end of the slit SHE is located at the height between the upper end of the memory pillar MP and the conductive layer 24. The lower end of the slit SHE is located at the height of the insulating layer 32. The slit SHE contains an insulator such as silicon oxide.

[0056] Contacts are connected to each of the conductive layers 21-23 in areas not shown in the diagram. These contacts electrically connect each of the conductive layers 21-23 to the row decoder module 16. This allows the row decoder module 16 to apply voltage to the conductive layers 21-23 (selection gate lines SGS and SGD and word line WL) provided on the memory cell array 10.

[0057] (Cross-sectional structure of memory pillar MP) Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar MP provided in the memory device 1 according to the first embodiment. Figure 7 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the surface of the semiconductor substrate 20 and including a conductive layer 22. As shown in Figure 7, the laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45.

[0058] The core member 40 is located in the center of the memory pillar MP. The semiconductor layer 41 surrounds the sides of the core member 40. The tunnel insulating film 43 surrounds the sides of the semiconductor layer 41. The insulating film 44 surrounds the sides of the tunnel insulating film 43. The block insulating film 45 surrounds the sides of the insulating film 44. The conductive layer 22 surrounds the sides of the block insulating film 45. The tunnel insulating film 43 and the block insulating film 45 each contain, for example, silicon oxide. The insulating film 44 contains, for example, silicon nitride.

[0059] In the memory pillar MP, the semiconductor layer 41 is used as the channel (current path) for the memory cell transistors MC0 to MC7 and the selection transistors ST1 and ST2. The insulating film 44 is used as the charge storage layer for the charge trap type memory cell transistor MC. By turning on the memory cell transistors MC0 to MC7 and the selection transistors ST1 and ST2, the memory device 1 can pass current through the memory pillar MP between the bit line BL and the contact LIC (source line SL).

[0060] <1-1-4>Data storage method Next, the configuration related to the data storage method of the memory device 1 according to the first embodiment will be described. In the following description, it will be assumed that the data writing order in each NAND string NS starts from the memory cell transistor MC on the bit line BL side. Furthermore, the case in which the memory cell transistor MC stores 3 bits of data will be described as an example.

[0061] (Data storage area) Figure 8 is a schematic diagram showing an example of the data storage area of ​​the NAND string NS provided in the memory device 1 according to the first embodiment. Figure 8 extracts the portion of the NAND string NS corresponding to the memory cell transistors MC(k-2) to MC(k+2) and shows five word lines WL(k-2) to WL(k+2) (five conductive layers 22), an insulating film 44 (charge storage layer), and a semiconductor layer 41. In this example, "k" is an integer between 2 and 5. Note that the upper limit of "k" in the first embodiment may change depending on the design of the memory cell array 10.

[0062] A memory cell transistor MC is a charge-trap type memory cell, and the charge storage layer (insulating film 44) of the NAND string NS is provided continuously. The insulating film 44 has memory sections P1 and P2 for each memory cell transistor MC. Memory section P1 corresponds to the portion of the insulating film 44 provided between the conductive layer 22 and the semiconductor layer 41. The memory section P1 of memory cell transistor MC(k) faces the conductive layer 22 corresponding to the word line WL(k). The memory section P2 corresponds to the portion of the insulating film 44 provided between two adjacent conductive layers 22 and the semiconductor layer 41. In other words, the memory section P2 corresponds to the portion of the insulating film 44 that does not face the conductive layer 22. The memory section P2 of memory cell transistor MC(k) faces the portion between the word lines WL(k) and WL(k-1) and is adjacent to the memory section P1 of memory cell transistor MC(k).

[0063] Figure 8(A) corresponds to the case where the memory cell transistor MC(k) in the first embodiment is in the erase state. As shown in Figure 8(A), the memory units P1 and P2 of the memory cell transistor MC(k) in the erase state are in a state where electrons are not trapped.

[0064] Figure 8(B) corresponds to the case in the first embodiment where the memory cell transistor MC(k) stores data associated with the first S-factor. As shown in Figure 8(B), the storage unit P1 of the memory cell transistor MC(k) having the first S-factor is in a state where it is trapping an amount of electrons corresponding to the data. On the other hand, the storage unit P2 of the memory cell transistor MC(k) having the first S-factor is in a state where it is not trapping electrons, or where electron trapping is suppressed.

[0065] Figure 8(C) corresponds to the case in the first embodiment where the memory cell transistor MC(k) stores data associated with a second S-factor that is lower than the first S-factor. As shown in Figure 8(C), the storage portion P1 of the memory cell transistor MC(k) having the second S-factor is in a state where it is trapping an amount of electrons corresponding to the data. Furthermore, the storage portion P2 of the memory cell transistor MC(k) having the second S-factor is in a state where it is trapping more electrons than the storage portion P2 of the memory cell transistor MC(k) having the first S-factor.

[0066] (Threshold voltage distribution of memory cell transistor MC) When a memory cell transistor (MC) stores 3 bits of data, it is programmed to one of eight threshold voltage levels depending on the data. Therefore, when a single cell unit (CU) stores 3 pages of data, eight different states can be formed in the threshold voltage distribution of the memory cell transistor (MC). In this specification, these eight states are referred to as "Z," "A," "B," "C," "D," "E," "F," and "G" states, in order from lowest to highest threshold voltage. In this example, three different 3 bits of data are assigned to each of the "Z," "A," "B," "C," "D," "E," "F," and "G" states. The "Z" state is formed corresponding to the threshold voltage of the memory cell transistor (MC) in the erase state. The "A," "B," "C," "D," "E," "F," and "G" states are formed corresponding to the memory cell transistor (MC) whose threshold voltage has risen above the erase state due to a write operation.

[0067] In the memory device 1 according to the first embodiment, a memory cell transistor MC on which data corresponding to any of the “A”, “C”, and “E” states is written has a first S-factor. A memory cell transistor MC on which data corresponding to any of the “B”, “D”, and “F” states is written has a second S-factor. The S-factor of a memory cell transistor MC on which data corresponding to the “G” state is written has, for example, the first S-factor. However, it is not limited to this, and the S-factor of a memory cell transistor MC on which data corresponding to the “G” state is written may be either the first S-factor or the second S-factor. In the first embodiment, in a plurality of states distributed between the lowest state (e.g., the “Z” state) and the highest state (e.g., the “G” state), it is sufficient that two adjacent states have different S-factors.

[0068] In this specification, the read voltages associated with states "A", "B", "C", "D", "E", "F", and "G" are referred to as read voltages AR, BR, CR, DR, ER, FR, and GR, respectively. Read voltages AR, BR, CR, DR, ER, FR, and GR are set to voltage levels that allow for the distinction between a memory cell transistor MC storing data corresponding to states "A", "B", "C", "D", "E", "F", and "G", and a memory cell transistor MC storing data corresponding to the state below it.

[0069] Furthermore, in this specification, the verify voltages associated with states "A", "B", "C", "D", "E", "F", and "G" are referred to as verify voltages AV, BV, CV, DV, EV, FV, and GV, respectively. The verify voltages AV, BV, CV, DV, EV, FV, and GV are used as reference levels when writing data corresponding to states "A", "B", "C", "D", "E", "F", and "G", respectively. Hereafter, a read operation using the verify voltage performed in a write operation will be referred to as a "verified read".

[0070] Figure 9 is a distribution diagram showing an example of the threshold voltage distribution of memory cell transistors MC in the memory device 1 according to the first embodiment. In the graph shown in Figure 9, the horizontal axis represents the threshold voltage Vth of the memory cell transistors MC, and the vertical axis represents the number of memory cell transistors NMCs. As shown in Figure 9, in the memory device 1 according to the first embodiment, the threshold voltage distribution of memory cell transistors MC is formed in correspondence with two sense times TS1 and TS2, respectively. Each of the sense times TS1 and TS2 corresponds to the time from when the discharge of the node SEN charged in the sense amplifier unit SAU starts and stops, with the read voltage or verify voltage applied to the selected word line WLsel during the read operation. Sense time TS2 is longer than sense time TS1.

[0071] Figure 9(1) corresponds to the threshold voltage distribution of the memory cell transistor MC during readout using sense time TS1. As shown in Figure 9(1), in the threshold voltage distribution of the memory cell transistor MC when sense time TS1, the "A" state and the "B" state are distributed in an overlapping manner, the "C" state and the "D" state are distributed in an overlapping manner, and the "E" state and the "F" state are distributed in an overlapping manner. Furthermore, the "Z" state and the pair of "A" and "B" states are distributed separately, the pair of "A" and "B" states and the pair of "C" and "D" states are distributed separately, the pair of "C" and "D" states and the pair of "E" and "F" states are distributed separately, and the pair of "E" and "F" states and the "G" state are distributed separately.

[0072] In the first embodiment, the read voltages AR, CR, ER, and GR are associated with the sense time TS1. Specifically, the read voltage AR is set to the voltage level between the "Z" state and the pair of "A" and "B" states at the sense time TS1. The read voltage CR is set to the voltage level between the pair of "A" and "B" states and the pair of "C" and "D" states at the sense time TS1. The read voltage ER is set to the voltage level between the pair of "C" and "D" states and the pair of "E" and "F" states at the sense time TS1. The read voltage GR is set to the voltage level between the pair of "E" and "F" states and the "G" state at the sense time TS1.

[0073] Furthermore, in the first embodiment, verify voltages AV and BV are integrated and used as verify voltage ABV. In the write operation, verify voltage ABV is used for verify readout using sense time TS1 and is used as a reference level when writing data corresponding to either "A" or "B" state. Similarly, verify voltages CV and DV are integrated and used as verify voltage CDV. In the write operation, verify voltage CDV is used for verify readout using sense time TS1 and is used as a reference level when writing data corresponding to either "C" or "D" state. Similarly, verify voltages EV and FV are integrated and used as verify voltage EFV. In the write operation, verify voltage EFV is used for verify readout using sense time TS1 and is used as a reference level when writing data corresponding to either "E" or "F" state.

[0074] Figure 9(2) corresponds to the threshold voltage distribution of the memory cell transistor MC during readout using sense time TS2. As shown in Figure 9(2), the voltage levels distributed for each state in the threshold voltage distribution of the memory cell transistor MC when sense time TS2 is longer than when sense time TS1 are lower than when sense time TS1 is longer. As a result, in the threshold voltage distribution of the memory cell transistor MC when sense time TS2 is longer, states "A" and "B" are distributed separately from the state at sense time TS1, states "C" and "D" are distributed separately, and states "E" and "F" are distributed separately.

[0075] In the first embodiment, the read voltages BR, DR, and FR are associated with the sense time TS2. Specifically, the read voltage BR is set to the voltage level between state "A" and state "B" when the sense time TS2 is reached. The read voltage DR is set to the voltage level between state "C" and state "D" when the sense time TS2 is reached. The read voltage FR is set to the voltage level between state "E" and state "F" when the sense time TS2 is reached. In the first embodiment, the read voltage GR may also be associated with the sense time TS2. In this case, the read voltage GR is set to the voltage level between state "F" and state "G" when the sense time TS2 is reached.

[0076] (Data allocation) Figure 10 is a table showing an example of data allocation used in the memory device 1 according to the first embodiment. The data allocation in the first embodiment will be described below with reference to Figure 10.

[0077] In this example, each memory cell transistor MC is configured to store 3-bit data consisting of an upper bit, a middle bit, and a lower bit. Hereafter, the data composed of the upper bits will be referred to as "upper page data." The data composed of the middle bits will be referred to as "middle page data." The data composed of the lower bits will be referred to as "lower page data." Furthermore, a read operation targeting lower page data will be referred to as "lower page read." A read operation targeting middle page data will be referred to as "middle page read." A read operation targeting upper page data will be referred to as "upper page read." Note that the names "upper," "middle," and "lower" used in the explanation of data allocation are merely examples and may be interchanged or changed.

[0078] The assignment of 3-bit data to each of the “Z”, “A”, “B”, “C”, “D”, “E”, “F”, and “G” states in the first embodiment is as follows:

[0079] (Example) State name: “Higher bit / Middle bit / Lower bit” data "Z" State: "111" Data "A" State: "110" Data "B" State: "100" Data "C" State: "000" Data "D" State: "010" Data "E" State: "011" Data "F" State: "001" Data “G” State: “101” Data

[0080] In the first embodiment, upper page reading involves determining the upper page data stored in the target cell unit CU by performing two readings using reading voltages CR and GR, respectively. In the first embodiment, middle page reading involves determining the middle page data stored in the target cell unit CU by performing three readings using reading voltages BR, DR, and FR, respectively. In the first embodiment, lower page reading involves determining the lower page data stored in the target cell unit CU by performing two readings using reading voltages AR and ER, respectively.

[0081] In the first embodiment, the multiple page data stored in a single cell unit CU is classified into a group of memory cell transistors MC written with a first S-factor and a group of memory cell transistors MC written with a second S-factor. In the above data allocation, lower page readout and upper page readout each correspond to read operations targeting the group of memory cell transistors MC written with the first S-factor. On the other hand, middle page readout corresponds to read operations targeting the group of memory cell transistors MC written with the second S-factor.

[0082] <1-2> Operation Next, the operation of the memory device 1 according to the first embodiment will be described. In the following description, a memory cell transistor MC included in a cell unit CU that is the target of a write or read operation will be referred to as a "selected memory cell transistor MCsel". A word line WL connected to a selected memory cell transistor MCsel will be referred to as a "selected word line WLsel". A bit line BL connected to a program-target selected memory cell transistor MCsel will be referred to as a "program bit line BLprog". A bit line BL connected to a program-inhibit selected memory cell transistor MCsel will be referred to as a "program-inhibit bit line BLinh". A NAND string NS connected to the program bit line BLprog will be referred to as a "selected string". A NAND string NS connected to the program-inhibit bit line BLinh will be referred to as a "non-selected string".

[0083] <1-2-1> Writing operation First, the writing operation of the memory device 1 according to the first embodiment will be described.

[0084] (Overview of the writing operation) Figure 11 is a time chart showing an overview of the write operation of the memory device 1 according to the first embodiment. Figure 11 shows the voltage changes of the selection word line WLsel, the program bit line BLprog, and the program disable bit line BLinn during the write operation. As shown in Figure 11, the memory device 1 performs a loop process (program loop process) that includes program operation and verification operation during the write operation. Although Figure 11 shows three loop processes (1st Loop, 2nd Loop, 3rd Loop), the number of loop processes may vary depending on the settings of the write operation, etc.

[0085] The program operation is an operation that can raise the threshold voltage of the selected memory cell transistor MCsel. The sequencer 14 sets each selected memory cell transistor MCsel to be programmable or program-unprogrammable and executes the program operation. A selected memory cell transistor MCsel to be programmable is a selected memory cell transistor MCsel that has not reached the threshold voltage of the state corresponding to the data to be written (hereinafter referred to as the "target state"). A selected memory cell transistor MCsel that has reached the threshold voltage of the target state is a selected memory cell transistor MCsel that has reached the threshold voltage of the target state.

[0086] For example, when the sense amplifier unit SAU holds data in a state other than the erase state, the sequencer 14 treats the select memory cell transistor MCsel connected to the sense amplifier unit SAU as the select memory cell transistor MCsel to be programmed. Also, when the sense amplifier unit SAU holds data in the erase state ("Z" state), the sequencer 14 treats the select memory cell transistor MCsel connected to the sense amplifier unit SAU as a select memory cell transistor MCsel that is not programmed. As the write operation progresses, the sequencer 14 can set the select memory cell transistor MCsel connected to the sense amplifier unit SAU to be not programmed by making the data held in the sense amplifier unit SAU the same as the data assigned to the erase state.

[0087] Furthermore, the program operation of the memory device 1 according to the first embodiment includes a first program process (1st Program) and a second program process (2nd Program). The first program process is an operation that can increase the threshold voltage of the selected memory cell transistor MCsel so that it has a first S-factor. The second program process is an operation that can increase the threshold voltage of the selected memory cell transistor MCsel so that it has a second S-factor. The sequencer 14 sets the selected memory cell transistor MCsel, which is the target of the program in the first program process, to be unprogrammable in the second program process. The sequencer 14 also sets the selected memory cell transistor MCsel, which is the target of the program in the second program process, to be unprogrammable in the first program process.

[0088] In both the first and second program processing, the sequencer 14 controls the driver circuit 15, the low decoder module 16, and the sense amplifier module 17, respectively, so that the threshold voltage of the selection memory cell transistor MCsel connected to the program bit line BLprog increases, and the increase in the threshold voltage of the selection memory cell transistor MCsel connected to the program disable bit line BLinn is suppressed. Specifically, the sequencer 14 applies VPGM, VSS, and Vinh to the selection word line WLsel, the program bit line BLprog, and the program disable bit line BLinn, respectively. VPGM is a high voltage capable of increasing the threshold voltage of the selection memory cell transistor MCsel. VSS is the ground voltage of the memory device 1. Vinh is a voltage higher than VSS and lower than VPGM.

[0089] Then, in both the first and second program processing, electrons are injected into the charge storage layer of the select memory cell transistor MCsel connected to the program bit line BLprog based on the voltage difference between the select word line WLsel and the channel, causing the threshold voltage to rise. On the other hand, in the select memory cell transistor MCsel connected to the program disable bit line BLinn, the channel potential is boosted by the cutoff of the select transistor ST1, suppressing the rise in the threshold voltage. The voltage value of VPGM is stepped up according to the iteration of the loop processing. In Figure 11, the voltage difference corresponding to the step-up width of VPGM for each loop processing is shown as DVPGM. In each program operation, the VPGM used in the first program processing and the VPGM used in the second program processing are, for example, at the same voltage level. The specific method for writing the first S-factor and the second S-factor separately in each of the first and second program processing will be described later.

[0090] When the program execution is complete, the sequencer 14 performs a verify operation. The verify operation checks whether the threshold voltage of the selected memory cell transistor MCsel has reached the threshold voltage of the target state. The verify operation includes at least one verify readout. In other words, the sequencer 14 performs a verify readout using the verify voltage Vvfy in each loop process. The verify voltage Vvfy is one of the verify voltages AV, BV, CV, DV, EV, FV, and GV. Multiple types of verify readouts may be performed in each loop process. If multiple types of verify readouts are performed in each loop process, multiple types of verify voltages Vvfy with different voltage levels are applied sequentially to the selected word line WLsel.

[0091] The verify read operation is performed on a select memory cell transistor MCsel that is programmed within the same loop and whose state, associated with the verify voltage Vvfy, is the target state. For example, in the verify read operation, the sequencer 14 applies VBL and VSS to the program bit line BLprog and the program disable bit line BLinn, respectively. VBL is a higher voltage than VSS. In addition, in the verify read operation, if the verify voltage Vvfy used targets a state different from the target state of the select memory cell transistor MCsel connected to it, VSS may be applied to the program bit line BLprog.

[0092] During the verify readout, each sense amplifier unit (SAU) determines, based on the voltage of its own node (SEN), whether the threshold voltage of the associated selected memory cell transistor (MCsel) exceeds the verify voltage (Vvfy) applied to the selected word line (WLsel). Selected memory cell transistors (MCsel) whose threshold voltage exceeds the verify voltage, i.e., those that have reached the target state threshold voltage, are determined to be "verify pass". On the other hand, selected memory cell transistors (MCsel) whose threshold voltage is less than or equal to the verify voltage (Vvfy), i.e., those that have not reached the target state threshold voltage, are determined to be "verify fail". Each sense amplifier unit (SAU) stores the result of the target state verify readout in one of its internal latch circuits.

[0093] Once the verification operation is complete, the sequencer 14 sets the selected memory cell transistor MCsel whose threshold voltage has reached the target state to program-disabled, based on the verification readout results in the current loop processing. For example, the sequencer 14 sets the data held in the sense amplifier unit SAU associated with the selected memory cell transistor MCsel in the verify path to the same data as the data assigned to the erase state. The sequencer 14 then starts the next loop processing.

[0094] Furthermore, the memory device 1 may perform a detection operation after each loop process. In the detection operation, the number of selected memory cell transistors MTsel that have passed the verify pass is counted for each state. The sequencer 14 then determines for each state whether or not the write operation is complete. Completion of the write operation is determined, for example, based on the number of selected memory cell transistors MCsel that have failed the verify fall below a predetermined number. In the repetition of the loop process, the sequencer 14 terminates the write operation when it detects that the write operation for each of the states "A" to "G" has been completed.

[0095] (Writing process flow) The following describes the flow of the write operation of the memory device 1 according to the first embodiment, with reference to Figure 12 as appropriate. Figure 12 is a flowchart showing an example of the write operation of the memory device 1 according to the first embodiment. The dashed lines in Figure 12 show the processing flow path when the associated process is omitted.

[0096] When memory device 1 receives a command from memory controller 2 to instruct it to perform a write operation, the address of the cell unit CU to which the data will be written, and the data to be written, sequencer 14 starts the write operation (start).

[0097] First, the sequencer 14 executes the "ACE" program (S101). The "ACE" program is the first program processing targeting the select memory cell transistor MCsel whose target state is one of the "A", "C", or "E" states. The "ACE" program raises the threshold voltage of the select memory cell transistor MCsel whose target state is one of the "A", "C", or "E" states. In the process of S101, the select memory cell transistor MCsel whose target state is one of the "B", "D", "F", or "G" states is set to write-protected. The process of S101 is omitted if writing to the "A", "C", and "E" states has been completed.

[0098] Next, the sequencer 14 executes the “BDFG” program (S102). The “BDFG” program is a second program process targeting a select memory cell transistor MCsel whose target state is one of the “B”, “D”, “F”, and “G”. The “BDFG” program raises the threshold voltage of the select memory cell transistor MCsel whose target state is one of the “B”, “D”, “F”, and “G”. In the process of S102, the select memory cell transistor MCsel whose target state is one of the “A”, “C”, and “E”, is set to write-protected. The process of S102 is omitted if writing to each of the “B”, “D”, “F”, and “G” states has been completed.

[0099] Next, the sequencer 14 performs a "G" verify (S103). The "G" verify is a verify read targeting the selected memory cell transistor MCsel whose target state is the "G" state. In the "G" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "G" verification has exceeded the verify voltage GV. The process in S103 may be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "G" state.

[0100] Next, the sequencer 14 performs an "EF" verify (S104). The "EF" verify is a verify read targeting a selected memory cell transistor MCsel whose target state is either the "E" state or the "F" state. In the "EF" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for the "EF" verify exceeds the verify voltage EFV. The process in S104 is omitted if the writing of the respective "E" and "F" states has been completed. The process in S104 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "E" or "F" state.

[0101] Next, the sequencer 14 performs a "CD" verify (S105). The "CD" verify is a verify read targeting a selected memory cell transistor MCsel whose target state is either the "C" state or the "D" state. In the "CD" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for the "CD" verify has exceeded the verify voltage CDV. The process in S105 is omitted if the writing of the respective "C" and "D" states has been completed. The process in S105 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "C" or "D" state.

[0102] Next, the sequencer 14 performs an "AB" verify (S106). The "AB" verify is a verify read targeting a selected memory cell transistor MCsel whose target state is either state "A" or state "B". In the "AB" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for the "AB" verify exceeds the verify voltage ABV. The process in S106 is omitted if the writing of states "A" and "B" has been completed.

[0103] Next, the sequencer 14 checks whether the writing of all states has been completed (S107). That is, the sequencer 14 determines whether the writing of each of the “A”, “B”, “C”, “D”, “E”, “F”, and “G” states has been completed based on the results of the processes in S103 to S106.

[0104] If, during the S107 process, the writing of all states is not complete (S107:NO), the PLC 14 steps up the VPGM (S108). Once the S108 process is complete, the PLC 14 proceeds to the S101 process. In other words, if the writing of all states is not complete during the S107 process, the PLC 14 uses the stepped-up VPGM to execute the next loop process.

[0105] In the process of S107, if the writing of all states is complete (S107:YES), the sequencer 14 terminates the series of processes shown in Figure 12 (termination). That is, the sequencer 14 terminates the writing operation and notifies the memory controller 2 of the termination of the writing operation.

[0106] (Examples of the "ACE" program) Figure 13 is a schematic diagram showing a specific example of the “ACE” program (first program processing) of the memory device 1 according to the first embodiment. Figure 13 shows the voltage applied to the word lines WL(k-2) to WL(k+2) and the injection of electrons into the charge storage layer (insulating film 44) of the selected memory cell transistor MCsel when the word line WL(k) is selected as the word line WLsel in the “ACE” program. In this example, the memory cell transistors MC connected to the word lines WL(k-1), WL(k-2), etc. are in an erased state, and the memory cell transistors MC connected to any of the word lines WL(k+1), WL(k+2), etc. are in a state where they have a threshold voltage corresponding to the data.

[0107] As shown in Figure 13, in the “ACE” program, the sequencer 14 applies VPASS, VPASSH, VPGM, VPASSD, and VPASS to the word lines WL(k-2), WL(k-1), WL(k), WL(k+1), and WL(k+2), respectively. VPASS is a voltage higher than the threshold voltage of the memory cell transistor MC distributed in the highest state, for example, 10V. VPASSD is a voltage greater than or equal to VPASS and lower than VPGM. VPASSH is a voltage higher than the threshold voltage of the memory cell transistor MC distributed in the highest state and lower than VPGM. In addition, when VPGM is applied to the word line WL(k), the sequencer 14 applies, for example, VDD to the selection gate lines SGD and SGS, respectively (not shown). VDD is a voltage that can turn on the selection transistors ST1 and ST2, for example, 3V.

[0108] Then, the selection transistors ST1 and ST2 are turned ON, and the channel potential of the NAND string NS becomes, for example, VSS, based on the voltage of the program bit line BLprog. Then, based on the potential difference between the channel (semiconductor layer 41) and the word line WL(k), electrons are injected into the insulating film 44 near the memory cell transistor MC(k). The injected electrons are then trapped in the memory section P1 of the memory cell transistor MC(k), and further trapped in the memory section P2 of the memory cell transistor MC(k) based on the potential difference between the channel (semiconductor layer 41) and the word line WL(k-1). In this way, the electrons trapped in the charge storage layer by the "ACE" program are distributed to the memory sections P1 and P2 of the selection memory cell transistor MCsel, respectively.

[0109] In the "ACE" program, VPASSH is set to a voltage level that allows electrons to be trapped in the memory unit P2 of the selective memory cell transistor MCsel. In the "ACE" program, the sequencer 14 may apply VPASS to the word line WL(k+1) when VPGM is applied to the word line WL(k). Furthermore, writing to the memory unit P2 of the selective memory cell transistor MCsel may be achieved by changing the length of the program pulse corresponding to VPGM.

[0110] (A concrete example of the "BDFG" program) Figure 14 is a schematic diagram showing a specific example of the “BDFG” program (second program processing) of the memory device 1 according to the first embodiment. Figure 14 shows the voltage applied to the word lines WL(k-2) to WL(k+2) and the injection of electrons into the charge storage layer (insulating film 44) of the selected memory cell transistor MCsel when the word line WL(k) is selected as the word line WLsel in the “BDFG” program. In this example, the memory cell transistors MC connected to the word lines WL(k-1), WL(k-2), etc. are in an erased state, and the memory cell transistors MC connected to any of the word lines WL(k+1), WL(k+2), etc. have a threshold voltage corresponding to the data.

[0111] As shown in Figure 14, in the “BDFG” program, the sequencer 14 applies VPASS, VPASSL, VPGM, VPASSD, and VPASS to the word lines WL(k-2), WL(k-1), WL(k), WL(k+1), and WL(k+2), respectively. VPASSL is a voltage that is higher than the threshold voltage of the memory cell transistor MC distributed in the highest state, and lower than VPASSH. In addition, when VPGM is applied to the word line WL(k), the sequencer 14 applies, for example, VDD to the selected gate lines SGD and SGS, respectively (not shown).

[0112] Then, based on the voltage of the program bit line BLprog, the channel potential becomes, for example, VSS. Based on the potential difference between the channel (semiconductor layer 41) and the word line WL(k), electrons are injected into the insulating film 44 near the memory cell transistor MC(k). The injected electrons are then trapped in the memory unit P1 of the memory cell transistor MC(k). In this way, the electrons trapped in the charge storage layer by the "BDFG" program are distributed in the memory unit P1 of the selected memory cell transistor MCsel.

[0113] In the “BDFG” program, it is preferable that the voltage applied to the word line WL(k-1) suppresses the trapping of electrons in the memory unit P2 of the selected memory cell transistor MCsel. In the “BDFG” program, when the sequencer 14 applies VPGM to the word line WL(k), it may also apply VPASS to the word lines WL(k-1) and WL(k+1), respectively.

[0114] <1-2-2> Read operation Next, the read operation of the memory device 1 according to the first embodiment will be described. In the drawings referenced below, the voltages of the selection word line WLsel, node SEN, and bit line BL before the start of the read operation are, for example, VSS. Also, the control signals BLX, BLC, PRE, XXL, and STB are, for example, at the "L" level.

[0115] (Specific example of reading lower-level pages) Figure 15 is a timing chart showing an example of lower page readout of memory device 1 according to the first embodiment. Figure 15 shows the voltage changes of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL and STB, and node SEN during lower page readout. As shown in Figure 15, in lower page readout of the first embodiment, the sequencer 14 sequentially executes the processes from time t0 to t6.

[0116] At time t0 of lower page readout, the PLC 14 applies the read voltage ER to the selection word line WLsel. The PLC 14 also sets the control signals BLX, BLC, and PRE to the "H" level. As a result, the voltage at node SEN rises to VSEN, and the voltage at bit line BL rises to VPCH. When the voltage at selection word line WLsel reaches the read voltage ER, the selection memory cell transistor MCsel turns on or off depending on the threshold voltage. If the selection memory cell transistor MCsel is in the off state (MCsel(OFF)), the voltage at bit line BL remains at VPCH. If the selection memory cell transistor MCsel is in the on state (MCsel(ON)), the voltage at bit line BL drops to a level lower than VPCH. Then, after the voltage at node SEN rises to VSEN, the PLC 14 sets the control signal PRE to the "L" level.

[0117] At time t1 of lower page readout, the sequencer 14 sets the control signal XXL to the "H" level. This forms a current path between node SEN and bit line BL, and the voltage of node SEN becomes corresponding to the voltage of bit line BL. Specifically, when the select memory cell transistor MCsel is in the off state (MCsel(OFF)), the voltage of node SEN remains at VSEN. When the select memory cell transistor MCsel is in the on state (MCsel(ON)), the voltage of node SEN decreases from VSEN. Then, after sense time TS1 has elapsed from time t1, the sequencer 14 sets the control signal XXL to the "L" level. This blocks the current path between node SEN and bit line BL, and the decrease in node SEN voltage stops. In other words, the voltage of node SEN is fixed at a level corresponding to the threshold voltage of the select memory cell transistor MCsel and sense time TS1.

[0118] At time t2 of lower page readout, the sequencer 14 asserts the control signal STB. That is, the sequencer 14 temporarily sets the control signal STB to the "H" level. Then, transistor T6 turns on or off based on the voltage of node SEN, and the readout result is reflected in the voltage of bus LBUS. The sense amplifier unit SAU then stores the data based on the bus LBUS voltage in one of its internal latch circuits. That is, at sense time TS1, it is determined whether the threshold voltage of the selection memory cell transistor MCsel exceeds the readout voltage ER, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU. The processing at times t0 to t2 of lower page readout corresponds to readout using the readout voltage ER.

[0119] At time t3 of lower page readout, the PLC 14 applies the read voltage AR to the selection word line WLsel. The PLC 14 also sets the control signal PRE to the "H" level and maintains the control signals BLX and BLC at the "H" level. As a result, the voltage at node SEN rises to VSEN and the voltage at bit line BL rises to VPCH. When the voltage at selection word line WLsel reaches the read voltage AR, the selection memory cell transistor MCsel becomes either ON or OFF. If the selection memory cell transistor MCsel is OFF, the voltage at bit line BL remains at VPCH. If the selection memory cell transistor MCsel is ON, the voltage at bit line BL drops to a voltage level lower than VPCH, based on the amount of current flowing through the selection memory cell transistor MCsel. Then, after the voltage at node SEN rises to VSEN, the PLC 14 sets the control signal PRE to the "L" level.

[0120] At time t4, when reading a lower page, the sequencer 14 sets the control signal XXL to the "H" level, just as at time t1. Then, the voltage of node SEN becomes corresponding to the voltage of bit line BL. After the sense time TS1 has elapsed from time t4, the sequencer 14 sets the control signal XXL to the "L" level, stopping the voltage of node SEN from decreasing.

[0121] At time t5 of lower page readout, the sequencer 14 asserts the control signal STB, similar to time t2. This determines whether the threshold voltage of the selection memory cell transistor MCsel exceeds the readout voltage AR at sense time TS1, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU. The processing at times t3 to t5 of lower page readout corresponds to readout using the readout voltage AR.

[0122] At time t6 of lower page readout, the sequencer 14 controls the state of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL, and STB, and node SEN to the same state as before the start of lower page readout. In addition, each sense amplifier unit SAU confirms the lower bit data stored in the selection memory cell transistor MCsel based on the determination results of the readout voltages ER and AR. Subsequently, the memory device 1 transmits the confirmed set of lower bit data as middle page data to the memory controller 2, and the lower page readout is completed.

[0123] (Specific example of reading mid-pages) Figure 16 is a timing chart showing an example of a middle page read operation of the memory device 1 according to the first embodiment. Figure 16 shows the voltage changes of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL and STB, and node SEN during a middle page read operation. As shown in Figure 16, in a middle page read operation of the first embodiment, the sequencer 14 sequentially executes the processes from time t0 to t9.

[0124] The processing for mid-page readouts at times t0 to t2 corresponds to readouts using the read voltage FR. The processing for mid-page readouts at times t0 to t2 is the same as the processing for low-page readouts at times t0 to t2, but with the read voltage ER replaced by the read voltage FR and the sense time TS1 replaced by the sense time TS2. As a result, it is determined whether the threshold voltage of the selection memory cell transistor MCsel exceeds the read voltage FR when the sense time is TS2, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU.

[0125] The processing at times t3 to t5 for middle page readout corresponds to readout using read voltage DR. The processing at times t3 to t5 for middle page readout is the same as the processing at times t3 to t5 for lower page readout, but with the read voltage AR replaced by read voltage DR and sense time TS1 replaced by sense time TS2. As a result, it is determined whether the threshold voltage of the selection memory cell transistor MCsel exceeds the read voltage DR when sense time TS2 is reached, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU.

[0126] The processing at times t6 to t8 for mid-page readout corresponds to readout using read voltage BR. The processing at times t6 to t8 for mid-page readout is the same as the processing at times t3 to t5 for mid-page readout, but with read voltage DR replaced by read voltage BR. This allows it to be determined whether the threshold voltage of the selection memory cell transistor MCsel exceeds the read voltage BR at sense time TS2, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU.

[0127] At time t9 of the middle page readout, the sequencer 14 controls the state of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL, and STB, and node SEN to the same state as before the start of the middle page readout. In addition, each sense amplifier unit SAU determines the middle bit data stored in the selection memory cell transistor MCsel based on the determination results of the readout voltages FR, DR, and BR. Subsequently, the memory device 1 transmits the set of determined middle bit data as middle page data to the memory controller 2, and the middle page readout is completed.

[0128] (Specific example of loading a higher-level page) Figure 17 is a timing chart showing an example of upper page readout of memory device 1 according to the first embodiment. Figure 17 shows the voltage changes of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL and STB, and node SEN during upper page readout. As shown in Figure 17, in upper page readout of the first embodiment, the sequencer 14 sequentially executes the processes from time t0 to t9.

[0129] The processing for upper page readouts at times t0 to t2 corresponds to readouts using the read voltage GR. The processing for upper page readouts at times t0 to t2 is the same as the processing for lower page readouts at times t0 to t2, but with the read voltage ER replaced by the read voltage GR. This allows it to be determined whether the threshold voltage of the selection memory cell transistor MCsel exceeds the read voltage GR at sense time TS1, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU.

[0130] The processing at times t3 to t5 for upper page readout corresponds to readout using read voltage CR. The processing at times t3 to t5 for upper page readout is the same as the processing at times t3 to t5 for lower page readout, but with read voltage AR replaced by read voltage CR. This allows it to be determined whether the threshold voltage of the selection memory cell transistor MCsel exceeds the read voltage CR at sense time TS1, and the determination result is stored in one of the latch circuits of the sense amplifier unit SAU.

[0131] At time t6 of the upper page readout, the sequencer 14 controls the state of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL, and STB, and node SEN to the same state as before the start of the upper page readout. In addition, each sense amplifier unit SAU determines the upper bit data stored in the selection memory cell transistor MCsel based on the determination results of the readout voltages GR and CR. Subsequently, the memory device 1 transmits the determined set of upper bit data as upper page data to the memory controller 2, and the upper page readout is completed.

[0132] <1-3> Effects of the First Embodiment The memory device 1 according to the first embodiment described above can increase the storage capacity of the memory device or expand the read margin. The effects (advantages) of the first embodiment are described in detail below.

[0133] One known method for increasing the storage capacity of memory devices is to store multiple bits of data in a single memory cell. For example, a memory cell can store multiple bits of data by having threshold voltage levels corresponding to the data. In this method, if the number of bits of data to be stored in the memory cell increases, it is necessary to increase the number of threshold voltage levels in proportion to the number of bits. However, expanding the range of threshold voltages that a memory cell can take is difficult due to the effects of disturbances, etc. Therefore, as the number of threshold voltage levels increases, the read margin and data retention margin per level decrease. When the read margin and data retention margin decrease, the number of error bits during reading increases, which may reduce the reliability of the data stored in the memory cell.

[0134] Therefore, the memory device 1 according to the first embodiment stores multiple bit data in the memory cell transistor MC by utilizing a combination of threshold voltage level and S-factor. Specifically, in a write operation, the memory device 1 executes a first program process that raises the threshold voltage of the memory cell transistor MC to have a first S-factor, and a second program process that raises the threshold voltage of the memory cell transistor MC to have a second S-factor that is greater than the first S-factor, according to the data to be written.

[0135] Specifically, between the first and second program processing, the memory device 1 changes the voltage applied to the selected word line WLsel and the adjacent word line WL while applying the program voltage to the selected word line WLsel. This allows the memory device 1 to adjust the number of electrons written between adjacent memory cell transistors MC (storage section P2). When electrons are trapped in storage section P2, a back bias is applied to the read operation, increasing the S-factor of the memory cell transistors MC. Furthermore, in the verify operation, the memory device 1 performs a verify read using the same sense time TS1 for both the first and second program processing. The memory device 1 then uses the first sense time TS1 for reads using the read voltage associated with the threshold voltage level written in the first program processing, and the second sense time TS2 for reads using the read voltage associated with the threshold voltage level written in the second program processing.

[0136] Figures 18 and 19 are graphs showing examples of the IV characteristics of the memory cell transistor MC in the comparative example and the memory device 1 according to the first embodiment, respectively. In Figures 18 and 19, the horizontal axis corresponds to the gate-source voltage Vgs of the memory cell transistor MC, and the vertical axis corresponds to the current Icell flowing through the memory cell transistor MC. The comparative example corresponds to the case in which 3 bits of data are stored in the memory cell transistor MC at 8 threshold voltage levels and the same S-factor.

[0137] In the comparative example, S-factor differentiation is not performed. Therefore, as shown in Figure 18, the IV characteristics of the memory cell transistor MC at each threshold voltage level have, for example, similar slopes. Also, in the comparative example, the sense current IS1 is used for verification and read operations. The sense current IS1 corresponds to the cell current flowing through the selected memory cell transistor MCsel when the control signal STB is asserted during readout using the sense time TS1. In this way, when the threshold voltage distribution is formed with the same sense current IS1, the spacing between adjacent states becomes narrower as the number of states increases.

[0138] On the other hand, in the first embodiment, two types of S-factors are written differently. In this case, as shown in Figure 19, for example, two types of slopes can be formed in the IV characteristics of the memory cell transistor MC at each threshold voltage level. Specifically, the slopes of the IV characteristics of the memory cell transistor MC in states "A", "C", and "E" that have a first S-factor are similar. Also, the slopes of the IV characteristics of the memory cell transistor MC in states "B", "D", and "F" that have a second S-factor that is larger than the first S-factor are similar. And, since the second S-factor is larger than the first S-factor, the slopes of the IV characteristics of the memory cell transistor MC in states "B", "D", and "F" are larger than those of states "A", "C", and "E", respectively.

[0139] Furthermore, the memory device 1 according to the first embodiment uses the sense current IS1 to write states "A" to "F", and the same verify voltage is used for each of the following pairs: "A" and "B", "C" and "D", and "E" and "F". Therefore, in a read operation using the sense current IS1, the pairs of "A" and "B", "C" and "D", and "E" and "F" are distributed in an overlapping manner. The memory device 1 is also configured to perform a read operation using the sense current IS2. The sense current IS2 corresponds to the cell current flowing through the selection memory cell transistor MCsel when the control signal STB is asserted in a read operation using the sense time TS2. In a read operation using the sense current IS2, since the sense time TS2 is longer than the sense time TS1, adjacent states can be separated according to the difference between the first S-factor and the second S-factor.

[0140] As a result, the memory device 1 can distinguish between two overlapping states during a read operation using the sense current IS1 by setting a read voltage between separated adjacent states. Furthermore, when a threshold voltage distribution is formed by the sense current IS1, the memory device 1 can widen the spacing between adjacent states compared to the comparative example. In other words, the memory device 1 according to the first embodiment can widen the spacing between two adjacent states by using a first sense time and a second sense time. Consequently, the memory device 1 can expand the read margin and improve the reliability of the memory device 1.

[0141] Furthermore, the memory device 1 according to the first embodiment can utilize even more threshold voltage levels by increasing the read margin. In this case, the memory device 1 can increase the number of bits stored in a single memory cell transistor MC, thereby increasing the storage capacity of the memory device 1.

[0142] Furthermore, in the memory device 1 according to the first embodiment, in each loop process, after the first program processing and the second program processing, the verify read of adjacent states is performed all at once. For example, in the comparative example, the number of verifications is 7, whereas in the first embodiment, the number of verifications is 4. Therefore, the memory device 1 according to the first embodiment can shorten the write operation time compared to the comparative example.

[0143] <1-4> Modified form of the first embodiment The data allocation applied to the memory device 1 may be any other type of allocation. An example of an alternative data allocation is described below as a modification of the first embodiment. The threshold voltage distribution setting of the memory cell transistor MC in the modification of the first embodiment is the same as in the first embodiment. In the modification of the first embodiment, the memory cell transistor MC on which data corresponding to any of the "A", "C", and "E" states is written has a first S-factor, as in the first embodiment. The memory cell transistor MC on which data corresponding to any of the "B", "D", and "F" states is written has a second S-factor, as in the first embodiment. In the modification of the first embodiment, the S-factor of the memory cell transistor MC on which data corresponding to the "G" state is written may be either the first S-factor or the second S-factor.

[0144] (Data allocation) Figure 20 is a table showing an example of data allocation in a modified version of the first embodiment. The data allocation in a modified version of the first embodiment will be described below with reference to Figure 20.

[0145] The assignment of 3-bit data to each of the “Z”, “A”, “B”, “C”, “D”, “E”, “F”, and “G” states in the modified version of the first embodiment is as follows:

[0146] (Example) State name: “Higher bit / Middle bit / Lower bit” data "Z" State: "111" Data "A" State: "101" Data "B" State: "001" Data "C" State: "011" Data "D" State: "010" Data "E" State: "110" Data "F" State: "100" Data “G” State: “000” Data

[0147] In the modified version of the first embodiment, upper page reading is performed by determining the upper page data stored in the cell unit CU to be read by performing three readings using reading voltages BR, ER, and GR, respectively. In the modified version of the first embodiment, middle page reading is performed by determining the middle page data stored in the cell unit CU to be read by performing three readings using reading voltages AR, CR, and FR, respectively. In the modified version of the first embodiment, lower page reading is performed by determining the lower page data stored in the cell unit CU to be read by performing one reading using reading voltage DR.

[0148] Thus, in the modified version of the first embodiment, the number of read operations for both upper page readout and middle page readout is three. On the other hand, lower page readout is set so that the data is determined in a single read operation. Furthermore, in the modified version of the first embodiment, both upper page readout and middle page readout each include readouts targeting a group of memory cell transistors MC written with a first S-factor and readouts targeting a group of memory cell transistors MC written with a second S-factor, in equal proportions. Additionally, lower page readout includes readouts targeting a group of memory cell transistors MC written with a second S-factor.

[0149] (Specific example of reading lower-level pages) Figure 21 is a timing chart showing an example of lower page readout in a modified version of the first embodiment. Figure 21 shows the voltage changes of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL and STB, and node SEN in lower page readout in a modified version of the first embodiment. As shown in Figure 21, in lower page readout in a modified version of the first embodiment, the sequencer 14 sequentially executes the processing from time t0 to t3.

[0150] In the lower page readout of the modified version of the first embodiment, the processing at times t0 to t2 corresponds to readout using the readout voltage DR. The details of readout using the readout voltage DR are the same as in the first embodiment. As a result, the determination result of whether or not the threshold voltage of the selection memory cell transistor MCsel exceeds the readout voltage DR at sense time TS2 is stored in one of the latch circuits of the sense amplifier unit SAU. This determination result corresponds to the upper bit data stored in the selection memory cell transistor MCsel.

[0151] At time t3 of lower page readout in the modified version of the first embodiment, the sequencer 14 controls the state of the selected word line WLsel, the bit line BL, the control signals BLX, BLC, PRE, XXL, and STB, and the node SEN to the same state as before the start of lower page readout. Subsequently, the memory device 1 transmits the set of lower bit data as lower page data to the memory controller 2, thereby ending the lower page readout.

[0152] (Specific example of reading mid-pages) Figure 22 is a timing chart showing an example of a mid-page readout in a modified version of the first embodiment. Figure 22 shows the voltage changes of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL and STB, and node SEN in a mid-page readout in a modified version of the first embodiment. As shown in Figure 22, in a mid-page readout in a modified version of the first embodiment, the sequencer 14 sequentially executes the processes from time t0 to t9.

[0153] In the intermediate page readout of the modified version of the first embodiment, the processing at times t0 to t2 corresponds to readout using readout voltage FR, the processing at times t3 to t5 corresponds to readout using readout voltage CR, and the processing at times t6 to t8 corresponds to readout using readout voltage AR. The details of readout using readout voltage FR, readout using readout voltage CR, and readout using readout voltage AR are the same as in the first embodiment. As a result, the determination result of whether the threshold voltage of the selection memory cell transistor MCsel exceeds the readout voltage FR when the sense time is TS2, the determination result of whether the threshold voltage of the selection memory cell transistor MCsel exceeds the readout voltage CR when the sense time is TS1, and the determination result of whether the threshold voltage of the selection memory cell transistor MCsel exceeds the readout voltage AR when the sense time is TS1 are each stored in the latch circuit of one of the sense amplifier units SAU.

[0154] At time t9 of the intermediate page readout in the modified version of the first embodiment, the sequencer 14 controls the state of the selection word line WLsel, the bit line BL, the control signals BLX, BLC, PRE, XXL, and STB, and the node SEN to the same state as before the start of the intermediate page readout. In addition, each sense amplifier unit SAU determines the intermediate bit data stored in the selection memory cell transistor MCsel based on the determination results of the readout voltages FR, CR, and AR. Subsequently, the memory device 1 transmits the set of determined intermediate bit data as intermediate page data to the memory controller 2, and the intermediate page readout is completed.

[0155] (Specific example of loading a higher-level page) Figure 23 is a timing chart showing an example of upper page readout in a modified version of the first embodiment. Figure 23 shows the voltage changes of the selection word line WLsel, bit line BL, control signals BLX, BLC, PRE, XXL and STB, and node SEN in upper page readout in a modified version of the first embodiment. As shown in Figure 23, in upper page readout in a modified version of the first embodiment, the sequencer 14 sequentially executes the processing from time t0 to t9.

[0156] In the upper page readout of the modified version of the first embodiment, the processing at times t0 to t2 corresponds to readout using readout voltage GR, the processing at times t3 to t5 corresponds to readout using readout voltage ER, and the processing at times t6 to t8 corresponds to readout using readout voltage BR. The details of readout using readout voltage GR, readout using readout voltage ER, and readout using readout voltage BR are the same as in the first embodiment. As a result, the determination result of whether the threshold voltage of the selected memory cell transistor MCsel exceeds the readout voltage GR at sense time TS1, the determination result of whether the threshold voltage of the selected memory cell transistor MCsel exceeds the readout voltage ER at sense time TS1, and the determination result of whether the threshold voltage of the selected memory cell transistor MCsel exceeds the readout voltage BR at sense time TS2 are each stored in the latch circuit of one of the sense amplifier units SAU.

[0157] At time t9 of the upper page readout in the modified version of the first embodiment, the sequencer 14 controls the state of the selection word line WLsel, the bit line BL, the control signals BLX, BLC, PRE, XXL, and STB, and the node SEN to the same state as before the start of the upper page readout. In addition, each sense amplifier unit SAU determines the upper bit data stored in the selection memory cell transistor MCsel based on the determination results of the readout voltages GR, ER, and BR. Subsequently, the memory device 1 transmits the determined set of upper bit data as upper page data to the memory controller 2, and the upper page readout is completed.

[0158] (Effects of modified version of the first embodiment) In the read operation of the first embodiment, three read operations are performed during the reading of a mid-page, utilizing a sense time TS2 that is longer than the sense time TS1. Therefore, in the first embodiment, the read time for reading a mid-page is longer than the read time for reading other pages.

[0159] In contrast, in the modified version of the first embodiment, read operations using sense time TS2 are assigned to each page. As a result, in the modified version of the first embodiment, the read times for intermediate pages and upper pages can be made the same. Furthermore, in the modified version of the first embodiment, since lower page data is determined in a single read operation, the read time for lower pages can be made shorter than for other pages. Lower page read operations in the modified version of the first embodiment are suitable for storing data that requires low latency.

[0160] As described above, the method for writing S-factors as described in the first embodiment may be applied to other data assignments. The concept of the first embodiment can be applied regardless of data assignment.

[0161] <2> Second Embodiment The memory device 1 according to the second embodiment performs a write operation that differentiates the S-factor state of the memory cell, and a read operation that utilizes two types of sense times, similar to the first embodiment. In the second embodiment, each state is arranged so that the read margin for each read voltage is widened. The following describes the differences between the memory device 1 according to the second embodiment and the first embodiment.

[0162] <2-1> Composition First, the configuration of the memory device 1 according to the second embodiment will be described. The hardware configuration of the memory device 1 according to the second embodiment is the same as that of the memory device 1 according to the first embodiment. In the memory device 1 according to the second embodiment, the arrangement of each state in the threshold voltage distribution of the memory cell transistor MC is different from that of the first embodiment. Below, the threshold voltage distribution of the memory cell transistor MC in the memory device 1 according to the second embodiment will be described using the case where each memory cell transistor MC stores 3 bits of data as an example.

[0163] Figure 24 is a distribution diagram showing an example of the threshold voltage distribution of memory cell transistors MC in the memory device 1 according to the second embodiment. In the graph shown in Figure 24, the horizontal axis represents the threshold voltage Vth of the memory cell transistors MC, and the vertical axis represents the number of memory cell transistors NMCs. As shown in Figure 24, in the memory device 1 according to the second embodiment, the threshold voltage distribution of memory cell transistors MC is formed in correspondence with each of the two sense times TS1 and TS2, similar to the first embodiment.

[0164] Figure 24(1) corresponds to the threshold voltage distribution of the memory cell transistor MC during readout using sense time TS1. As shown in Figure 24(1), in the threshold voltage distribution of the memory cell transistor MC when sense time TS1, states "Z", "A", "B", "C", "D", "E", "F", and "G" are distributed far apart. The intervals between states "Z" and "A", between states "B" and "C", and between states "D" and "E" are set to be wide, while the intervals between states "A" and "B", between states "C" and "D", and between states "E" and "F" are set to be narrow.

[0165] In other words, in the threshold voltage distribution of the memory cell transistor MC for a sense time TS1, the interval between the L-th state (where "L" is an odd number) and the (L+1)th state, starting from the lowest threshold voltage, is set to be wider than the interval between the (L+1)th state and the (L+2)th state. Note that in the threshold voltage distribution of the memory cell transistor MC for a sense time TS1, a portion of the (L+1)th state and a portion of the (L+2)th state may overlap.

[0166] In the second embodiment, the setting of the read voltages associated with the sense time TS1 is the same as in the first embodiment. That is, in the second embodiment, the read voltages AR, CR, ER, and GR are associated with the sense time TS1. Also, in the second embodiment, for example, the verify voltage of each state is associated with the sense time TS1. In other words, in the second embodiment, the verify voltages AV, BV, CV, DV, EV, FV, and GV can each be set in association with the sense time TS1 so that the threshold voltage distribution shown in Figure 24(1) is formed.

[0167] Figure 24(2) corresponds to the threshold voltage distribution of the memory cell transistor MC during readout using sense time TS2. As shown in Figure 24(2), the voltage levels distributed for each state in the threshold voltage distribution of the memory cell transistor MC when sense time TS2 is longer than when sense time TS1 are lower. As a result, in the threshold voltage distribution of the memory cell transistor MC when sense time TS2 is longer, the intervals between the "Z" state and the "A" state, the intervals between the "B" state and the "C" state, and the intervals between the "D" state and the "E" state are set to be narrower than in the state at sense time TS1, while the intervals between the "A" state and the "B" state, the intervals between the "C" state and the "D" state, and the intervals between the "E" state and the "F" state are set to be wider.

[0168] In other words, in the threshold voltage distribution of the memory cell transistor MC for a sense time TS2, the interval between the (L+1)th state and the (L+2)th state, starting from the lowest threshold voltage, is set to be wider than the interval between the Lth state and the (L+1)th state. Note that in the threshold voltage distribution of the memory cell transistor MC for a sense time TS2, a portion of the Lth state and a portion of the (L+1)th state, starting from the lowest threshold voltage, may overlap.

[0169] In the second embodiment, the setting of the readout voltages associated with the sense time TS2 is the same as in the first embodiment. That is, in the second embodiment, the readout voltages BR, DR, and FR are associated with the sense time TS2. In the second embodiment, some of the verify voltages may also be associated with the sense time TS2. For example, the verify voltages BV', DV', and FV' may be set in association with the sense time TS2 so that states "B", "D", and "F" are formed in the threshold voltage distribution shown in Figure 24 (2).

[0170] <2-2> Operation Next, the operation of the memory device 1 according to the second embodiment will be described. The memory device 1 according to the second embodiment performs a different writing operation than that of the first embodiment.

[0171] The following describes the flow of the write operation of the memory device 1 according to the second embodiment, with reference to Figure 25. Figure 25 is a flowchart showing an example of the write operation of the memory device 1 according to the second embodiment. The dashed lines in Figure 25 show the processing flow path when the associated process is omitted.

[0172] When memory device 1 receives a command from memory controller 2 to instruct it to perform a write operation, the address of the cell unit CU to which the data will be written, and the data to be written, sequencer 14 starts the write operation (start).

[0173] First, the sequencer 14 executes the "ACE" program (S101), similar to the first embodiment. The process in S101 is omitted if the writing of states "A", "C", and "E" has been completed.

[0174] Next, the sequencer 14 executes the "BDFG" program, as in the first embodiment (S102). The process in S102 is omitted if the writing of the "B", "D", "F", and "G" states has been completed.

[0175] Next, the sequencer 14 performs a "G" verification, similar to the first embodiment (S103). The process in S103 may be omitted in loop processing where it is presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has clearly not reached the "G" state.

[0176] Next, the sequencer 14 performs an "F" verify (S201). The "F" verify is a verify read targeting a selected memory cell transistor MCsel whose target state is "F". In the "F" verify, the sequencer 14 uses sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "F" verification has exceeded the verify voltage FV, or uses sense time TS2 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "F" verification has exceeded the verify voltage FV'. The process in S201 is omitted if the writing of the "F" state is complete. The process in S201 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "F" state.

[0177] Next, the sequencer 14 performs an "E" verify (S202). The "E" verify is a verify read targeting the selected memory cell transistor MCsel whose target state is the "E" state. In the "E" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "E" verification exceeds the verify voltage EV. The process in S202 is omitted if the writing of the "E" state is complete. The process in S202 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "E" state.

[0178] Next, the sequencer 14 performs a "D" verify (S203). The "D" verify is a verify read targeting the selected memory cell transistor MCsel whose target state is "D". In the "D" verify, the sequencer 14 uses sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "D" verification has exceeded the verify voltage DV, or uses sense time TS2 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "D" verification has exceeded the verify voltage DV'. The process in S203 is omitted if the writing of the "D" state is complete. The process in S203 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "D" state.

[0179] Next, the sequencer 14 performs a "C" verify (S204). The "C" verify is a verify read targeting the selected memory cell transistor MCsel whose target state is "C". In the "C" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "C" verification exceeds the verify voltage CV. The process in S204 is omitted if the writing of the "C" state is complete. The process in S204 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "C" state.

[0180] Next, the sequencer 14 performs a "B" verify (S205). The "B" verify is a verify read targeting the selected memory cell transistor MCsel whose target state is "B". In the "B" verify, the sequencer 14 uses sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "B" verification has exceeded the verify voltage BV, or uses sense time TS2 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "B" verification has exceeded the verify voltage BV'. The process in S205 is omitted if the writing of the "B" state is complete. The process in S205 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "B" state.

[0181] Next, the sequencer 14 performs an "A" verify (S206). The "A" verify is a verify read targeting the selected memory cell transistor MCsel whose target state is "A". In the "A" verify, the sequencer 14 uses the sense time TS1 to determine whether the threshold voltage of the selected memory cell transistor MCsel targeted for "A" verification exceeds the verify voltage AV. The process in S206 is omitted if the writing of the "A" state is complete.

[0182] Next, the sequencer 14 checks whether all states have been written, similar to the first embodiment (S107).

[0183] If, during the S107 process, the writing of all states is not complete (S107:NO), the PLC 14 steps up the VPGM (S108). Once the S108 process is complete, the PLC 14 proceeds to the S101 process. In other words, if the writing of all states is not complete during the S107 process, the PLC 14 uses the stepped-up VPGM to execute the next loop process.

[0184] In the process of S107, if the writing of all states is complete (S107:YES), the sequencer 14 terminates the series of processes shown in Figure 25 (termination). That is, the sequencer 14 terminates the writing operation and notifies the memory controller 2 of the termination of the writing operation.

[0185] Other operations of the memory device 1 according to the second embodiment are the same as those of the first embodiment.

[0186] <2-3> Effects of the second embodiment The memory device 1 according to the second embodiment performs S-factor differentiation during writing operations, similar to the first embodiment, and also performs a verify operation for each state. Figure 26 is a graph showing an example of the IV characteristics of a memory cell in the memory device 1 according to the second embodiment. In Figure 26, the horizontal axis corresponds to the gate-source voltage Vgs of the memory cell transistor MC, and the vertical axis corresponds to the current Icell flowing through the memory cell transistor MC. As shown in Figure 26, the memory device 1 can finely control the state arrangement in the threshold voltage distribution of the memory cell transistor MC for sense time TS1 and the threshold voltage distribution of the memory cell transistor MC for sense time TS2, respectively, by performing a verify operation for each state.

[0187] As a result, the memory device 1 according to the second embodiment can widen both the read margin when using the first sense current IS1 and the read margin when using the second sense current IS2. Therefore, the memory device 1 according to the second embodiment can widen the read margin, similar to the first embodiment, and improve the reliability of the memory device 1.

[0188] <3> Third Embodiment The memory device 1 according to the third embodiment is a NAND flash memory that utilizes memory cells equipped with a floating gate, and implements the same data storage method as the first embodiment. The details of the memory device 1 according to the third embodiment, and the differences from the first embodiment, will be described below.

[0189] <3-1> Composition First, the configuration of the memory device 1 according to the third embodiment will be described. The memory device 1 according to the third embodiment has a configuration that differs from the memory device 1 according to the first embodiment in the structure of the memory pillar MP and the allocation of the data storage area. Hereinafter, the memory pillar MP in the third embodiment will be referred to as "memory pillar MPa". <3-1-1> Structure of Memory Pillar MP Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of a memory pillar MPa provided in the memory device 1 according to the third embodiment. Figure 27 shows an extracted portion where two adjacent word lines WL intersect with the memory pillar MPa. As shown in Figure 27, the memory pillar MPa differs from the memory pillar MP in the first embodiment in that it has a recess RP and in its configuration related to the memory cell transistor MC.

[0190] The recess RP corresponds to a portion that extends along the Z direction of the memory pillar MPa and protrudes in the Y direction. The recess RP is in contact with the conductive layers 21, 22, and 23, respectively. Therefore, the outer diameter of the cross-section of the memory pillar MPa along the XY plane is larger in the portion including the recess RP than in the portion excluding the recess RP.

[0191] The memory pillar MPa includes a core member 40, a semiconductor layer 41, insulating layers 50 and 51, a semiconductor layer 52, insulating layers 53, 54 and 55, and semiconductor layers 56U and 56L. The core member 40 is provided stretched along the Z direction. The semiconductor layer 41 covers the periphery of the core member 40. The bottom of the semiconductor layer 41 is in contact with the semiconductor substrate 20 (not shown). The insulating layer 50 covers the side surface of the semiconductor layer 41. The insulating layer 51 is provided along the outer periphery of the memory pillar MP. The insulating layer 51 is in contact with the conductive layer 22 in the recess RP, for example, and with the insulating layer 31 and the semiconductor layer 41 outside the recess RP.

[0192] The semiconductor layer 52 is provided in the center of the recess RP. The semiconductor layer 52 is surrounded by a pair of insulating layers 53 and 54. The insulating layer 53 has a portion provided between the insulating layer 50 and the semiconductor layer 52. The insulating layer 54 is in contact with the semiconductor layer 52 and the insulating layer 55, and has a portion provided between the semiconductor layer 52 and the conductive layer 22, and a portion provided between the semiconductor layer 52 and the insulating layer 31. The insulating layer 55 is in contact with the insulating layers 54 and 51, and has a portion provided between the insulating layer 54 and the conductive layer 22, and a portion provided between the insulating layer 54 and the insulating layer 31.

[0193] The semiconductor layer 56U is provided above the semiconductor layer 56L. The semiconductor layers 56U and 56L are separated and insulated from each other. Each of the semiconductor layers 56L and 56U is covered by, for example, a set of insulating layers 50, 51, 53, 54, and 55. Each of the semiconductor layers 56L and 56U has a portion provided between the conductive layer 22 and the semiconductor layer 41. The semiconductor layer 56 only needs to be separated and insulated from at least the semiconductor layers 41 and 52 and the conductive layer 22. In the recess RP, the volume occupied by the semiconductor layer 52 is larger than that of the semiconductor layer 56.

[0194] Each of the semiconductor layers 41, 52, 56L, and 56U contains, for example, silicon. Each of the insulating layers 51, 53, and 54 is, for example, a silicon oxide film (SiO). The insulating layer 55 is, for example, a silicon oxide film containing hafnium (HfSiO). In the memory pillar MPa, semiconductor layer 52 corresponds to the first floating gate, and semiconductor layers 56L and 56U correspond to the second floating gate. In the third embodiment, the memory cell transistor MC stores data nonvolatilously by the combination of the first floating gate and the second floating gate. The functions of the first floating gate and the second floating gate correspond to the storage units P1 and P2 of the first embodiment, respectively. Hereinafter, semiconductor layer 52 will be referred to as the "floating gate section FG1," and semiconductor layers 56L and 56U will be referred to as the "floating gate section FG2."

[0195] Figure 28 is a cross-sectional view along the line XXVIII-XXVIII in Figure 27. Figure 28 shows an example of a cross-section of a memory pillar MPa that includes a semiconductor layer 52 (floating gate portion FG1) and is aligned with the XY plane. As shown in Figure 28, in the memory pillar MPa, the core member 40, semiconductor layer 41, insulator layers 50 and 53, semiconductor layer 52 (floating gate portion FG1), and insulator layers 54, 55 and 51 are arranged concentrically and in this order toward the outer circumference. In the third embodiment, the floating gate portion FG1 is arranged in an annular shape in a cross-section along the XY plane.

[0196] Figure 29 is a cross-sectional view along the line XXIX-XXIX in Figure 27. Figure 29 shows an example of a cross-section of a memory pillar MPa that includes a semiconductor layer 56L (floating gate portion FG2) and is aligned with the XY plane. As shown in Figure 29, in the memory pillar MPa, the core member 40, semiconductor layer 41, insulator layer 50, semiconductor layer 56L (floating gate portion FG1), and insulator layers 55 and 51 are arranged concentrically and in this order toward the outer circumference. In the third embodiment, the floating gate portion FG2 is provided in an annular shape in a cross-section along the XY plane. Although not shown, the semiconductor layer 56U is provided in an annular shape in a cross-section along the XY plane, similar to the semiconductor layer 56L.

[0197] <3-1-2> Data storage area Figure 30 is a schematic diagram showing an example of the data storage area of ​​the NAND string NS provided in the memory device 1 according to the third embodiment. Figure 30 extracts the portion of the NAND string NS corresponding to the memory cell transistors MC(k-1) to MC(k+1), showing three word lines WL(k-1) to WL(k+1) (three conductive layers 22), semiconductor layers 52, 56L, and 56U (charge storage layers), and semiconductor layer 41. In this example, "k" is an integer between 1 and 6. Note that the upper limit of "k" in the third embodiment may change depending on the design of the memory cell array 10.

[0198] The memory cell transistor MC is a floating-gate type memory cell, and the charge storage layer of the NAND string NS is provided separately for each memory cell transistor MC. Each memory cell transistor MC has a semiconductor layer 52 (floating gate portion FG1) and semiconductor layers 56L and 56U (floating gate portion FG2) as its charge storage layer. The semiconductor layers 52, 56L and 56U of the memory cell transistor MC(k) are provided between the conductive layer 22 and the semiconductor layer 41 corresponding to the word line WL(k).

[0199] Figure 30(A) corresponds to the case where the memory cell transistor MC(k) is in the erase state in the third embodiment. As shown in Figure 30(A), the floating gate portions FG1 and FG2 of the memory cell transistor MC(k) in the erase state are in a state where no electrons are stored.

[0200] Figure 30(B) corresponds to the case in the third embodiment where the memory cell transistor MC(k) has a first S-factor. As shown in Figure 30(B), the floating gate portion FG1 of the memory cell transistor MC(k) having a first S-factor is in a state where it is accumulating an amount of electrons corresponding to the data. On the other hand, the floating gate portion FG2 of the memory cell transistor MC(k) having a first S-factor is in a state where it is not accumulating electrons, or where electron accumulation is suppressed. In other words, in the memory cell transistor MC(k) having a first S-factor, electrons are injected into the floating gate portion FG1.

[0201] Figure 30(C) corresponds to the case in the third embodiment where the memory cell transistor MC(k) has a second S-factor lower than the first S-factor. As shown in Figure 30(C), the floating gate portion FG1 of the memory cell transistor MC(k) having the second S-factor is in a state where it has accumulated an amount of electrons corresponding to the data. Furthermore, the floating gate portion FG2 of the memory cell transistor MC(k) having the second S-factor has accumulated more electrons than the floating gate portion FG2 of the memory cell transistor MC(k) having the first S-factor. In other words, in the memory cell transistor MC(k) having the second S-factor, electrons are injected into both the floating gate portions FG1 and FG2.

[0202] (IV characteristics of memory cell transistor MC) Figure 31 is a graph showing an example of the IV (current-voltage) characteristics of a memory cell transistor MC in the memory device 1 according to the third embodiment. In the graph shown in Figure 31, the horizontal axis corresponds to the gate-source voltage Vgs of the memory cell transistor MC, and the vertical axis represents the current Icell flowing through the memory cell transistor MC. The solid line corresponds to the IV characteristics of the portion corresponding to the floating gate portion FG1, and the dashed line corresponds to the IV characteristics of the portion corresponding to the floating gate portion FG2.

[0203] As shown in Figure 31, each memory cell transistor MC can form eight types of IV characteristics corresponding to one of the following states: "Z", "A", "B", "C", "D", "E", "F", and "G", based on the amount of electrons accumulated in the floating gate portion FG1. In addition, each memory cell transistor MC can form two types of IV characteristics based on the amount of electrons accumulated in the floating gate portion FG2. For example, the erased state of the floating gate portion FG2 corresponds to "1" data, and the state in which electrons have been injected into the floating gate portion FG2 corresponds to "0" data. The threshold voltage distribution of the cell unit CU in the third embodiment is formed based on the sum of the IV characteristics corresponding to the floating gate portion FG1 and the IV characteristics corresponding to the floating gate portion FG2.

[0204] The saturation current value in the IV characteristics corresponding to the floating gate section FG1 is higher than the saturation current value in the IV characteristics corresponding to the floating gate section FG2. Specifically, the saturation current value in the IV characteristics corresponding to the floating gate section FG1 is higher than the sense current IS1. The saturation current value in the IV characteristics corresponding to the floating gate section FG2 is lower than the sense current IS1 and higher than the sense current IS2. The sense current IS1 is used to read data written to the floating gate section FG1. The sense current IS2 is used to read data written to the floating gate section FG2. In the third embodiment, the memory cell transistor MC stores 8 values ​​(i.e., 3-bit data) in the floating gate section FG1 and 2 values ​​(i.e., 1-bit data) in the floating gate section FG2. Therefore, the memory cell transistor MC in the third embodiment can store 4-bit data.

[0205] In the memory device 1 according to the third embodiment, a memory cell transistor MC with its floating gate portion FG2 in an erased state has the first S-factor described in the first embodiment. A memory cell transistor MC with electrons injected into its floating gate portion FG2 has the second S-factor described in the first embodiment. Therefore, the memory device 1 according to the third embodiment can store data as in the first embodiment by using a write operation that allows for two different S-factor states of the memory cell transistor MC, and by using sense times TS1 and TS2 appropriately.

[0206] <3-2> Operation Next, the operation of the memory device 1 according to the third embodiment will be described. The memory device 1 according to the third embodiment forms the threshold voltage distribution of the memory cell transistor MC described in the first or second embodiment by a writing operation adapted to the memory cell transistor MC having floating gate portions FG1 and FG2. In the following, the writing operation of the memory device 1 according to the third embodiment will be described using the case in which the threshold voltage distribution of the memory cell transistor MC described in the first embodiment is formed as an example.

[0207] (Writing process flow) The following describes the flow of the write operation of the memory device 1 according to the third embodiment, with reference to Figure 32. Figure 32 is a flowchart showing an example of the write operation of the memory device 1 according to the third embodiment. The dashed lines in Figure 32 show the processing flow path when the associated process is omitted.

[0208] When memory device 1 receives a command from memory controller 2 to instruct it to perform a write operation, the address of the cell unit CU to which the data will be written, and the data to be written, sequencer 14 starts the write operation (start).

[0209] First, the sequencer 14 executes the HE program (S301). The HE program is a program that targets the selected memory cell transistor MCsel whose state set as the second S-factor is the target state. In the HE program, electrons are injected into the floating gate portion FG2 of the selected memory cell transistor MCsel that is being programmed using hot electrons. As a result, the S-factor of the selected memory cell transistor MCsel that is being programmed becomes the second S-factor. In the HE program, electrons may or may not be injected into the floating gate portion FG1 of the selected memory cell transistor MCsel. This is because even if the threshold voltage of the selected memory cell transistor MCsel changes, the threshold voltage of the selected memory cell transistor MCsel will increase due to the subsequent loop processing, and a verification operation will be performed.

[0210] Next, the sequencer 14 performs HE verification (S302). In HE verification, a verification voltage corresponding to the "0" data of the sense current IS1 is applied to the selected word line WLsel, and a read operation using the sense current IS1 is performed. Then, it is checked whether the threshold voltage of the memory cell transistor MCcel to be programmed has been written to the level of "0" data in the sense current IS1.

[0211] Next, the sequencer 14 checks whether the HE verification has passed (S303: HE verification pass?). For example, in process S303, the sequencer 14 checks whether the number of selected memory cell transistors MCsel that have not passed the HE verification has fallen below a predetermined number.

[0212] If it is confirmed in the S303 process that the HE verification has not passed (S303: NO), the PLC 14 steps up the VPGM (S304). Once the S304 process is complete, the PLC 14 proceeds to the S301 process. In other words, if the HE verification does not pass in the S303 process, the PLC 14 uses the stepped-up VPGM to execute the HE program and HE verification again in sequence.

[0213] If the HE verification is confirmed to have passed in the S303 process (S303: YES), the sequencer 14 then executes the FN program (S305). The FN program is a program process targeting a selected memory cell transistor MCsel whose threshold voltage has not reached the target state. The FN program uses an FN (Fowler-Nordheim) tunnel current to inject electrons into the floating gate portion FG1 of the selected memory cell transistor MCsel being programmed. This causes the threshold voltage of the selected memory cell transistor MCsel to rise. When transitioning from the S303 process to the S305 process, the sequencer 14 resets various setting voltages, such as VPGM, to the initial voltages for the FN program.

[0214] Next, the sequencer 14 performs a "G" verify (S306). In the "G" verify of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel to be verified exceeds the verify voltage GV. The process in S306 may be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "G" state.

[0215] Next, the sequencer 14 performs an "F" verify (S307). In the "F" verify of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel to be verified exceeds the verify voltage FV. The process in S307 is omitted if the program for the "F" state is completed. The process in S307 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "F" state.

[0216] Next, the sequencer 14 performs an "E" verify (S308). In the "E" verify of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel to be verified exceeds the verify voltage EV. The process in S308 is omitted if the writing of the "E" state is complete. The process in S308 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "E" state.

[0217] Next, the sequencer 14 performs a "D" verify (S309). In the "D" verify of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel to be verified exceeds the verify voltage DV. The process in S309 is omitted if the writing of the "D" state is complete. The process in S309 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "D" state.

[0218] Next, the sequencer 14 performs a "C" verify (S310). In the "C" verify of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel to be verified exceeds the verify voltage CV. The process in S310 is omitted if the writing of the "C" state is complete. The process in S310 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "C" state.

[0219] Next, the sequencer 14 performs a "B" verify (S311). In the "B" verify of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel to be verified exceeds the verify voltage BV. The process in S311 is omitted if the writing of the "B" state is complete. The process in S311 may also be omitted in loop processing where it is clearly presumed that the threshold voltage of the selected memory cell transistor MCsel to be programmed has not reached the "B" state.

[0220] Next, the sequencer 14 performs an "A" verification (S312). In the "A" verification of the third embodiment, the sense current IS1 is used to determine whether the threshold voltage of the selected memory cell transistor MCsel, which is the target of the "A" verification, exceeds the verification voltage AV. The process in S312 is omitted if the writing of the "A" state is complete.

[0221] Next, the sequencer 14 checks whether all states have been written (S313).

[0222] In the process of S313, if writing of all states is not completed (S313: NO), the sequencer 14 steps up VPGM (S314). When the process of S314 is completed, the sequencer 14 proceeds to the process of S305. That is, if writing of all states is not completed in the process of S313, the sequencer 14 executes the next loop process using the stepped-up VPGM.

[0223] In the process of S313, if writing of all states is completed (S313: YES), the sequencer 14 ends the series of processes in FIG. 32 (End). That is, the sequencer 14 ends the write operation and notifies the memory controller 2 of the end of the write operation.

[0224] As described above, in the write operation of the third embodiment, after the loop process including the HE program (S301) is executed, the loop process including the FN program (S305) is executed.

[0225] (Specific Example of HE Program) FIG. 33 is a schematic diagram showing a specific example of the HE program for a selected string in the memory device 1 according to the third embodiment. FIG. 33 shows voltages applied to each of the word lines WL(k-1), WL(k) and WL(k+1), and the select gate lines SGD and SGS of the selected string, when the word line WL(k) is set as the selected word line WLsel in the HE program.

[0226] As shown in FIG. 33, in the HE program, the sequencer 14 applies VPASS, VHEP, VPASS, VDD, and VDDH to the word lines WL(k-1), WL(k) and WL(k+1), and the select gate lines SGS and SGD of the selected string, respectively. VHEP is a high voltage capable of injecting hot electrons into the floating gate portion FG2 of the selected memory cell transistor MCsel, and is, for example, a voltage higher than VPASS. VDDH is a voltage higher than VDD and lower than VPASS.

[0227] Then, the select transistors ST1 and ST2 are turned on, and electrons are supplied to the channel of the NAND string NS based on the voltage difference between the source line SL and the program bit line BLprog. Then, electrons (hot electrons) are injected into the floating gate portion FG2 of the memory cell transistor MC(k) based on the voltage of the word line WL(k) and the channel current.

[0228] FIG. 34 is a schematic diagram illustrating a specific example of the HE program for unselected strings in the memory device 1 according to the third embodiment. FIG. 33 shows the voltages applied to each of the word lines WL(k-1), WL(k), and WL(k+1), and the select gate lines SGD and SGS of the unselected strings when the word line WL(k) is set as the selected word line WLsel in the HE program.

[0229] As shown in FIG. 34, the voltages applied to the word lines WL(k-1), WL(k), and WL(k+1) are the same as in the case of FIG. 33. In the HE program, the sequencer 14 applies VSS to each of the select gate lines SGS and SGD of the unselected strings. As a result, the select transistors ST1 and ST2 are turned off, and the current path between the source line SL and the program bit line BLprog is cut off. Therefore, even if VHEP is applied to the word line WL(k), the injection of electrons into the floating gate portion FG2 of the selected memory cell transistor MCsel is suppressed.

[0230] (Specific Example of FN Program) FIG. 35 is a schematic diagram illustrating a specific example of the FN program for selected strings in the memory device 1 according to the third embodiment. FIG. 35 shows the voltages applied to each of the word lines WL(k-1), WL(k), and WL(k+1), and the select gate lines SGD and SGS of the selected strings when the word line WL(k) is set as the selected word line WLsel in the FN program.

[0231] As shown in Figure 35, in the FN program, the sequencer 14 applies VPASS, VPGM, VPASS, VDD, and VDD to the word lines WL(k-1), WL(k), and WL(k+1), and to the selection gate lines SGS and SGD of the selection string, respectively. Then, the selection transistors ST1 and ST2 are turned on, and the channel potential becomes VSS based on the voltage applied to the program bit line BLprog. Then, based on the potential difference between the word line WL(k) and the channel, electrons are injected into the floating gate portion FG1 of the memory cell transistor MC(k).

[0232] Figure 36 is a schematic diagram showing a specific example of an FN program for an unselected string in the memory device 1 according to the third embodiment. Figure 36 shows the voltages applied to the word lines WL(k-1), WL(k), and WL(k+1) and the selected gate lines SGD and SGS of the unselected string, respectively, when the word line WL(k) is set to the selected word line WLsel in the FN program.

[0233] As shown in Figure 36, the voltages applied to the word lines WL(k-1), WL(k), and WL(k+1) are the same as in Figure 35. In the FN program, the sequencer 14 applies VSS to the selection gate lines SGS and SGD of the unselected string, respectively. This turns off the selection transistors ST1 and ST2, interrupting the current path between the source line SL and the program bit line BLprog. As a result, VPASS is applied to the unselected word line WL, boosting the channel potential. Consequently, even if VPGM is applied to the word line WL(k), electron injection into the floating gate portion FG1 of the selection memory cell transistor MCsel is suppressed.

[0234] Other operations of the memory device 1 according to the third embodiment are the same as those of the first embodiment.

[0235] <3-3> Manufacturing method Next, an example of a method for manufacturing the memory device 1 according to the third embodiment will be described with reference to Figure 37 as appropriate. Figure 37 is a flowchart showing an example of a method for manufacturing the memory device 1 according to the third embodiment. Figures 38 to 54, which are referenced below, are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory device according to the third embodiment. Figures 38, 40, 42, 44, 46, 48, 50, and 52 each show the region where the memory pillar MP shown in Figure 27 is formed. Figure 39 shows a cross-section along the line XXXIX-XXXIX in Figure 38. Figure 41 shows a cross-section along the line XXXXI-XXXXI in Figure 40. Figure 43 shows a cross-section along the line XXXXIII-XXXXIII in Figure 42. Figure 45 shows a cross-section along the line XXXXV-XXXXV in Figure 44. Figure 47 shows a cross-section along the line XXXXVII-XXXXVII in Figure 46. Figure 49 shows a cross-section along the line XXXXIX-XXXXIX in Figure 48. Figure 51 shows a cross-section along the LI-LI line in Figure 50. Figure 53 shows a cross-section along the LIII-LIII line in Figure 52. Figure 54 shows a cross-section along the LIV-LIV line in Figure 52.

[0236] First, the lamination process of the sacrificial layer 60 and the insulating layer 31 is performed (S311). This forms a structure on the semiconductor substrate 20 in which the insulating layer 31 and the sacrificial layer 60 are alternately laminated (not shown). The sacrificial layer 60 is, for example, silicon nitride (SiN).

[0237] Next, memory holes MH are formed (S312). The process in S312 includes, for example, photolithography and RIE (Reactive Ion Etching). As shown in Figure 38, the memory holes MH are provided penetrating the stacked sacrificial layer 60 and insulating layer 31. The cross-sectional shape of the memory holes MH along the XY plane is circular, as shown in Figure 39.

[0238] Next, a recessing process of the sacrificial layer 60 is performed (S313). The process in S313 includes a wet etching process with a high selectivity for the sacrificial layer 60. As shown in Figure 40, the process in S313 removes a portion of the sacrificial layer 60 that is exposed on the side surface of the memory hole MH. As a result, in the memory hole MH, the inner diameter W2 at the height including the sacrificial layer 60 becomes larger than the inner diameter W1 at the height including the insulating layer 31. In other words, a space corresponding to the recess RP of the memory pillar MP is formed on the side surface of the memory hole MH. As shown in Figure 41, the recess RP is provided in a shape that spreads concentrically from the shape of the opening of the memory hole MH in a cross-section along the XY plane.

[0239] Next, as shown in Figure 42, insulating layers 51, 55, and 54 and a semiconductor layer 52 are formed (S314). The insulating layers 51, 55, and 54 are formed sequentially along the sides of the memory hole MH and the recess RP. The semiconductor layer 52 is formed to fill the space corresponding to the recess RP, as shown in Figure 43, without filling the memory hole MH.

[0240] Next, a recessing process is performed on the semiconductor layer 52 (S315). The process in S315 includes a wet etching process with a high selectivity for the semiconductor layer 52. As shown in Figure 44, the semiconductor layer 52 provided on the side portion of the memory hole MH is removed by the process in S315. As a result, in the memory hole MH, the inner diameter W4 at the height including the sacrificial layer 60 becomes smaller than the inner diameter W3 at the height including the insulator layer 31. As shown in Figure 45, the semiconductor layer 52 is provided in a ring shape in a cross-section along the XY plane. The semiconductor layer 52 functions as a floating gate portion FG1.

[0241] Next, recess processing of the insulating layers 54 and 55 is performed (S316). Processing S316 includes a wet etching process with a high selectivity ratio for insulating layers 54 and 55. Processing S316 removes portions of the insulating layers 54 and 55 that are exposed on the side of the memory hole MH so as to penetrate the recess RP, as shown in Figure 46. As a result, in the memory hole MH, the inner diameter W5 in the portion that includes the sacrificial layer 60 and is along the recess RP becomes larger than the inner diameter W4 in the portion that includes the semiconductor layer 52. As shown in Figure 47, the insulating layer 55 is provided in a ring shape in a cross-section along the XY plane and is adjacent to the sacrificial layer 60 via the insulating layer 51.

[0242] Next, the semiconductor layer 52 is oxidized (S317). As a result, as shown in Figure 48, the surface portion of the semiconductor layer 52 that was exposed in the memory hole MH is oxidized, and an insulating layer 53 is formed. At this time, the semiconductor layer 52 is surrounded by insulating layers 53 and 54. As shown in Figure 49, the semiconductor layer 52 is provided between insulating layers 53 and 54 in a cross-section along the XY plane.

[0243] Next, a semiconductor layer 56 is formed (S318). Specifically, first, the semiconductor layer 56 is provided on the side portion of the memory hole MH. Then, the space provided in the recess portion RP is filled by the semiconductor layer 56. After that, the semiconductor layer 56 provided on the side portion of the memory hole MH is removed by wet etching or the like. As a result, the semiconductor layer 56 is separated on the upper and lower sides of each insulator layer 53, and as shown in Figure 50, the structures corresponding to the semiconductor layers 56U and 56L remain in the recess portion RP of the memory hole MH. As shown in Figure 51, the semiconductor layer 56L is provided in a ring shape in a cross-section along the XY plane and is adjacent to the sacrificial layer 60 via the insulator layers 55 and 51. The cross-sectional structure of the semiconductor layer 56U along the XY plane is the same as that of the semiconductor layer 56L. Each of the semiconductor layers 56U and 56L functions as a floating gate portion FG2.

[0244] Next, the insulating layer 50, the semiconductor layer 41, and the core member 40 are formed (S319). The insulating layer 55 and the semiconductor layer 41 are formed sequentially along the side surface of the memory hole MH. The core member 40 is formed so as to fill the memory hole MH, as shown in Figure 52. As a result, a structure is formed in which the semiconductor layers 52 and 41 are adjacent to each other via the insulating layers 50 and 53, as shown in Figure 53. Also, as shown in Figure 54, a structure is formed in which the semiconductor layers 56L and 41 are adjacent to each other via the insulating layer 50. Although not shown, the semiconductor layers 56L and 41, and the semiconductor layer 56U, are adjacent to each other via the insulating layer 50.

[0245] Next, a replacement process is performed (S320). Specifically, first, a slit SLT is formed. Then, the stacked sacrificial layer 60 is selectively removed through the slit SLT by wet etching with thermal phosphoric acid or the like. After that, a conductor is embedded through the slit SLT into the space where the sacrificial layer 60 was removed. For example, CVD (Chemical Vapor Deposition) is used to form the conductor in this process. Subsequently, the conductor formed on the side of the slit SLT is removed by an etch-back process, and the conductor formed on the adjacent wiring layer is separated. This forms a stacked wiring including multiple conductor layers 22 that function as word lines WL.

[0246] <3-4> Effects of the third embodiment The memory cell transistor MC of the memory device 1 according to the third embodiment has a floating gate portion that is separated, and has floating gate portions FG1 and FG2. In the writing operation, electrons are injected into the floating gate portion FG1 by FN tunneling current, and electrons are injected into the floating gate portion FG2 by writing with hot electrons. In other words, the two types of floating gate portions FG1 and FG2 of the memory cell transistor MC have different writing principles.

[0247] When electrons are injected into the floating gate portion FG2, the memory cell transistor MC has a high resistance at the floating gate portion FG2, but can be turned on due to the short channel effect. Thereby, in the third embodiment, memory cell transistors MC with different S-factors can be formed in accordance with the presence or absence of electrons in the floating gate portion FG2, similarly to the first embodiment. Then, the memory device 1 according to the third embodiment can inject electrons into the floating gate portion FG2 of the memory cell transistor MC associated with the second S-factor by HE programming. Further, the memory device 1 according to the third embodiment can inject electrons into the floating gate portion FG1 of each memory cell transistor MC by FN programming, thereby raising the threshold voltage of each memory cell transistor MC to a desired level.

[0248] As a result, the memory device 1 according to the third embodiment can form a threshold voltage distribution similar to that of the first embodiment. In addition, the memory device 1 according to the third embodiment can distinguish adjacent states with different S-factors by executing a read operation using two types of sense times TS1 and TS2. Therefore, the memory device 1 according to the third embodiment can expand the read margin and improve the reliability of the memory device 1.

[0249] <4>Fourth Embodiment The memory device 1 according to the fourth embodiment implements the same data storage scheme as that of the first embodiment in a NAND flash memory that uses memory cells each including a floating gate and has two NAND strings NS to which each memory pillar MP is connected in parallel. Hereinafter, regarding details of the memory device 1 according to the fourth embodiment, differences from the first to third embodiments will be described.

[0250] <4-1>Configuration First, the configuration of the memory device 1 according to the fourth embodiment will be described. Compared to the memory device 1 according to the third embodiment, the memory cell array 10 is replaced by a memory cell array 10a, and the row decoder module 16 has a configuration that allows it to apply voltage according to the wiring configuration of the memory cell array 10a. In the following, the case in which the memory cell array 10a includes a plurality of block BLKs and each block BLK has five string units SUs will be described.

[0251] <4-1-1> Circuit configuration of the memory cell array 10a Figure 55 is a circuit diagram showing an example of the circuit configuration of a memory cell array 10a provided in the memory device 1 according to the fourth embodiment. Figure 55 shows two string units SU0 and SU1 included in a block BLK. As shown in Figure 55, the memory cell array 10a includes selection gate lines SGDa0~SGDa4, SGDb0~SGDb4, SGSa and SGSb, word lines WLa0~WLa7 and WLb0~WLb7, bit lines BL0~BLm and source line SL. Each of the selection gate lines SGDa0~SGDa4, SGDb0~SGDb4, SGSa and SGSb, and the word lines WLa0~WLa7 and WLb0~WLb7 are provided for each block BLK. The bit lines BL0~BLm and source line SL are shared, for example, by multiple block BLKs. The row decoder module 16 of the fourth embodiment is configured to allow voltage to be applied independently to each of the selected gate lines SGDa0~SGDa4, SGDb0~SGDb4, SGSa and SGSb, and the word lines WLa0~WLa7 and WLb0~WLb7.

[0252] Each string unit SU of the memory cell array 10a includes multiple memory groups MG. Each of the multiple memory groups MG is associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each memory group MG includes two NAND strings NSa and NSb. NAND string NSa includes memory cell transistors MCa0 to MCa7 and selection transistors STa1 and STa2. NAND string NSb includes memory cell transistors MCb0 to MCb7 and selection transistors STb1 and STb2. Each of the selection transistors STa1, STb1, STa2, and STb2 is used to select string unit SU and NAND string NS. Each of the memory cell transistors MCa and MCb is a transistor having a control gate and a charge storage layer, which holds data non-volatilely. Memory cell transistors MCa and MCb are floating-gate type memory cells.

[0253] The drain terminals of selection transistors STa1 and STb1 are connected to their respective associated bit lines BL. The source terminal of selection transistor STa1 is connected to one end of the series-connected memory cell transistors MCa0 to MCa7, i.e., the drain terminal of memory cell transistor MCa7. The other end of the series-connected memory cell transistors MCa0 to MCa7, i.e., the source terminal of memory cell transistor MCa0, is connected to the drain terminal of selection transistor STa2. The source terminal of selection transistor STb1 is connected to one end of the series-connected memory cell transistors MCb0 to MCb7, i.e., the drain terminal of memory cell transistor MCb7. The other end of the series-connected memory cell transistors MCb0 to MCb7, i.e., the source terminal of memory cell transistor MCb0, is connected to the drain terminal of selection transistor STb2. The source terminals of selection transistors STa2 and STb2 are connected to the source line SL.

[0254] Each gate terminal of multiple selection transistors STa1 contained in the same block BLK is connected to a common selection gate line SGDa for each string unit SU. Each gate terminal of multiple selection transistors STb1 contained in the same block BLK is connected to a common selection gate line SGDb for each string unit SU. Specifically, multiple selection transistors STa1 contained in string unit SU0 are connected to selection gate line SGDa0. Multiple selection transistors STb1 contained in string unit SU0 are connected to selection gate line SGDb0. Multiple selection transistors STa1 contained in string unit SU1 are connected to selection gate line SGDa1. Multiple selection transistors STb1 contained in string unit SU1 are connected to selection gate line SGDb1. Similarly, multiple selection transistors STa1 contained in string units SU2 to SU5 are connected to selection gate lines SGDa2 to SGDa5, respectively. Multiple selection transistors STb1 contained in string units SU2 to SU5 are connected to selection gate lines SGDb2 to SGDb5, respectively.

[0255] The control gate terminals of each of the multiple memory cell transistors MCa0 to MCa7 contained within the same block BLK are connected to word lines WLa0 to WLa7, respectively. The control gate terminals of each of the memory cell transistors MCb0 to MCb7 contained within the same block BLK are connected to word lines WLb0 to WLb7, respectively.

[0256] The gate terminals of each of the multiple selection transistors STa2 contained within the same block BLK are connected to the selection gate line SGSa. The gate terminals of each of the multiple selection transistors STb2 contained within the same block BLK are connected to the selection gate line SGSb.

[0257] <4-1-2> Structure of memory cell array 10a (Planar layout of memory cell array 10a) Figure 56 is a plan view showing an example of the planar layout of a memory cell array 10a provided in the memory device 1 according to the fourth embodiment. Figure 56 shows an extracted region corresponding to three consecutive blocks BLK0 to BLK2. As shown in Figure 56, the region of the memory cell array 10a includes a cell region CA and replacement regions RA1 and RA2. Each of the cell region CA and replacement regions RA1 and RA2 is a region that extends in the Y direction. The cell region CA is sandwiched in the X direction by the replacement regions RA1 and RA2. The memory cell array 10a also includes a plurality of memory trenches MT, a plurality of memory pillars MPb, and a plurality of replacement holes STH.

[0258] Each of the selection gate lines SGDa and SGDb has a portion that extends along the X direction and crosses the cell region CA and the replacement regions RA1 and RA2. The selection gate lines SGDa and SGDb are arranged alternately in the Y direction. Although not shown in the illustration, each of the word line WLa and selection gate line SGSa is arranged overlapping with selection gate line SGDa in the Z direction, and each of the word line WLb and selection gate line SGSb is arranged overlapping with selection gate line SGDb in the Z direction.

[0259] Each memory trench MT is positioned between adjacent selection gate lines SGDa and SGDb. The memory trench MT has a portion extending along the X direction. The memory trench MT separates adjacent wiring layers in the Y direction. An insulator, for example, is embedded in the memory trench MT. The memory trench MT may have portions separated by memory pillars MPb or replacement holes STH.

[0260] Each memory pillar MPb functions as one memory group MG. Each memory pillar MP is positioned to divide the memory trench MT and to be in contact with the respective selection gate lines SGDa and SGDb. Although not shown in the diagram, each memory pillar MP is in contact with the respective word lines WLa and WLb and the respective selection gate lines SGSa and SGSb. The portion of memory pillar MPb facing the selection gate line SGDa functions as selection transistor STa1. The portion of memory pillar MPb facing the selection gate line SGDb functions as selection transistor STb1. The portion of memory pillar MPb facing the word line WLa functions as memory cell transistor MCa. The portion of memory pillar MPb facing the word line WLb functions as memory cell transistor MCb. The portion of memory pillar MPb facing the selection gate line SGSa functions as selection transistor STa2. The portion of memory pillar MPb facing the selection gate line SGSb functions as selection transistor STb2.

[0261] Each memory pillar MP is provided with at least one overlapping bit line BL, and one bit line BL is electrically connected. In the region corresponding to each block BLK, multiple memory pillars MPb are arranged, for example, in a staggered pattern of four rows. Memory trenches MT, which are not separated by memory pillars MP, are placed at the boundaries of adjacent block BLKs. The memory cell array 10b is divided into block BLK units by being separated by memory trenches MT that are not separated by memory pillars MPb.

[0262] Each replacement hole STH is used during the formation of a multilayer wiring. For example, a group of replacement holes STH includes replacement holes STH that overlap even-numbered memory trenches MT in replacement region RA1, and replacement holes STH that overlap odd-numbered memory trenches MT in replacement region RA2. Each replacement hole STH divides a memory trench MT and is in contact with the selected gate lines SGDa and SGDb, respectively. An insulator is embedded in the replacement hole STH, for example.

[0263] (Cross-sectional structure of memory cell array 10a) Figure 57 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 10a provided in the memory device 1 according to the fourth embodiment. Figure 57 shows an extracted cross-section including two adjacent memory trenches MT and a memory pillar MPb disposed between the two adjacent memory trenches MT. As shown in Figure 57, the memory cell array 10a includes, for example, a semiconductor substrate 70, conductive layers 21a, 21b, 22a, 22b, 23a, 23b, 24 and 72, insulating layers 30 to 34 and 71, and contact CTs.

[0264] The semiconductor substrate 70 is, for example, a P-type silicon substrate. An insulating layer 71 is provided on the semiconductor substrate 70. The insulating layer 71 includes configurations, wiring, and contacts corresponding to the elements provided on the semiconductor substrate 70. For example, the insulating layer 71 is provided with circuits such as a low decoder module 16. A conductive layer 72 is provided on the insulating layer 71. The conductive layer 72 is, for example, formed in the shape of a plate extending along the XY plane and used as a source wire SL. The conductive layer 72 includes, for example, phosphorus-doped silicon. The conductive layer 72 may include multiple types of semiconductor layers or may include a metal layer.

[0265] An insulating layer 30 is provided on the conductive layer 72. A conductive layer 21 is provided on the insulating layer 30. In the fourth embodiment, the conductive layer 21 is divided into conductive layers 21a and 21b by the memory trench MT and memory pillar MPb. Insulating layers 31 and conductive layers 22 are alternately stacked on the conductive layer 21. In the fourth embodiment, the conductive layer 22 is divided into conductive layers 22a and 22b by the memory trench MT and memory pillar MPb. An insulating layer 32 is provided on the uppermost conductive layer 22. A conductive layer 23 is provided on the insulating layer 32. In the fourth embodiment, the conductive layer 23 is divided into conductive layers 23a and 23b by the memory trench MT and memory pillar MPb. An insulating layer 33 is provided on the conductive layer 23. A conductive layer 24 is provided on the insulating layer 33. An insulating layer 34 is provided on the conductive layer 24. Wiring and contacts for connecting the memory cell array 10a with the low decoder module 16 and the sense amplifier module 17 are provided on the wiring layer on which the insulating layer 34 is formed.

[0266] Each of the conductive layers 21a, 21b, 22a, 22b, 23a, and 23b has a portion formed in a line shape extending along the X direction. Conductive layers 21a and 21b are used as selection gate lines SGSa and SGSb, respectively. Multiple conductive layers 22a are used, from bottom to top, as word lines WLa0 to WLa7, respectively. Multiple conductive layers 22b are used, from bottom to top, as word lines WLb0 to WLb7, respectively. Conductive layers 23a and 23b are used as selection gate lines SGDa and SGDb, respectively. Conductive layer 24 is used as bit line BL. Each of the conductive layers 21a, 21b, 22a, 22b, 23a, and 23b contains, for example, tungsten.

[0267] The memory pillar MPb is provided extending along the Z direction. The memory pillar MPb has recesses RPa and RPb. Each of the recesses RPa and RPb corresponds to a portion of the memory pillar MPb that extends along the Z direction and protrudes in the direction along the Y direction. Recess RPa is in contact with each of the conductive layers 21a, 22a, and 23a. Recess RPb is in contact with each of the conductive layers 21b, 22b, and 23b. The memory pillar MPb includes a core member 40 and a semiconductor layer 41. It is provided extending along the Z direction. The semiconductor layer 41 of the memory pillar MPb covers the periphery of the core member 40. The lower part of the semiconductor layer 41 is in contact with the conductive layer 72. The upper part of the semiconductor layer 41 is connected to the conductive layer 24 via a contact CT. The memory pillar MPb is provided on the side surface of the semiconductor layer 41 and includes a stacked portion containing floating gate portions FG1 and FG2. Details of this stacked portion will be described later.

[0268] The memory trench MT separates the conductive layers 21-23 and the insulating layers 30-32. An insulator is embedded within the memory trench MT. The upper end of the memory trench MT is in contact with the insulating layer 33. The lower end of the memory trench MT is in contact with the conductive layer 72. Multiple types of materials may be embedded in the memory trench MT. The memory trench MT only needs to be able to insulate at least adjacent conductive layers.

[0269] Furthermore, multiple conductive layers 22a (word lines WLa) provided at the same height are electrically connected to each block BLK in a region not shown. Multiple conductive layers 22b (word lines WLb) provided at the same height are electrically connected to each block BLK in a region not shown. Multiple conductive layers 21a (selection gate lines SGSa) provided at the same height are electrically connected to each block BLK in a region not shown. Multiple conductive layers 21b (selection gate lines SGSb) provided at the same height are electrically connected to each block BLK in a region not shown.

[0270] (Cross-sectional structure of memory pillar MPa) Figure 58 is a cross-sectional view showing an example of the cross-sectional structure of a memory pillar MPa provided in a memory device 1 according to the fourth embodiment. Figure 58 includes memory cell transistors MCa and MCb and shows a cross-section along the XY plane. As shown in Figure 58, the memory pillar MPb includes, for example, insulator layers 50 and 51, semiconductor layers 52a and 52b, insulator layers 53a and 53b, insulator layers 54a, 54b, 55a and 55b, and semiconductor layers 56a and 56b. Each of the semiconductor layer 52a and the insulator layers 53a, 54a and 55a is provided corresponding to the recess RPa. Each of the semiconductor layer 52b and the insulator layers 53b, 54b and 55b is provided corresponding to the recess RPa.

[0271] The core member 40 of the memory pillar MPb is located in the center of the memory pillar MPb. The semiconductor layer 41 of the memory pillar MPb covers the sides of the core member 40. The insulating layer 50 covers the sides of the semiconductor layer 41. The insulating layer 51 is located along the outer periphery of the memory pillar MP. The insulating layer 51 is in contact with the conductive layer 22a in the recess RPa and in contact with the conductive layer 22b in the recess RPb. The insulating layer 51 is also located between the memory trench MT and the semiconductor layer 41.

[0272] The semiconductor layer 52a is provided in the central part of the recess RPa. The periphery of the semiconductor layer 52a is covered by a set of insulating layers 53a and 54a. The insulating layer 53a has a portion provided between the insulating layer 50 and the semiconductor layer 52a. The insulating layer 54a is in contact with the semiconductor layer 52a and the insulating layer 55a, and has a portion provided between the semiconductor layer 52a and the conductive layer 22a, and a portion provided between the semiconductor layer 52a and the memory trench MT. The insulating layer 55a is in contact with the insulating layers 54a and 51, and has a portion provided between the insulating layer 54a and the conductive layer 22a, and a portion provided between the insulating layer 54a and the memory trench MT. The semiconductor layer 56a is covered by, for example, a set of insulating layers 50, 51, 53a, 54a and 55a. The semiconductor layer 56a has a portion provided between the conductive layer 22a and the semiconductor layer 41. The semiconductor layer 56a only needs to be separated and insulated from at least the semiconductor layers 41 and 52a and the conductive layer 22a. In the recess RPa, the volume occupied by the semiconductor layer 52a is larger than that of the semiconductor layer 56a.

[0273] The semiconductor layer 52b is provided in the central part of the recess RPb. The semiconductor layer 52b is surrounded by a set of insulating layers 53b and 54b. The insulating layer 53b has a portion provided between the insulating layer 50 and the semiconductor layer 52b. The insulating layer 54b is in contact with the semiconductor layer 52b and the insulating layer 55b, and has a portion provided between the semiconductor layer 52b and the conductive layer 22b, and a portion provided between the semiconductor layer 52b and the memory trench MT. The insulating layer 55b is in contact with the insulating layers 54b and 51, and has a portion provided between the insulating layer 54b and the conductive layer 22b, and a portion provided between the insulating layer 54b and the memory trench MT. The semiconductor layer 56b is covered by, for example, a set of insulating layers 50, 51, 53b, 54ba, and 55b. The semiconductor layer 56b has a portion provided between the conductive layer 22b and the semiconductor layer 41. The semiconductor layer 56b only needs to be separated and insulated from at least the semiconductor layers 41 and 52b and the conductive layer 22b. In the recess RPb, the volume occupied by the semiconductor layer 52b is greater than that of the semiconductor layer 56b.

[0274] Semiconductor layer 52a corresponds to the floating gate portion FG1 of the memory cell transistor MCa provided in recess portion RPa. Semiconductor layer 52b corresponds to the floating gate portion FG1 of the memory cell transistor MCb provided in recess portion RPa. Semiconductor layer 56a corresponds to the floating gate portion FG2 of the memory cell transistor MCa provided in recess portion RPa. Semiconductor layer 56b corresponds to the floating gate portion FG2 of the memory cell transistor MCb provided in recess portion RPb. Insulator layers 50, 53a and 53b correspond to tunnel insulating films. Insulator layers 51, 54a, 54b, 55a and 55b correspond to block insulating films. Semiconductor layer 41 includes, for example, silicon. Insulator layer 51 is, for example, silicon oxide (SiO). Semiconductor layers 52a and 52b include, for example, silicon. Insulator layers 53a and 53b are, for example, silicon oxide (SiO). The insulating layer 54 is, for example, a silicon oxide film (SiO). The insulating layer 55 is, for example, a silicon oxide film containing hafnium (HfSiO). The semiconductor layers 56a and 56b contain, for example, silicon. In the memory pillar MPb, the semiconductor layer 41 may be divided in accordance with the recesses RPa and RPb.

[0275] Figure 59 is a cross-section along the LIX-LIX line in Figure 58, showing cross-sections along the XZ plane of the floating gate portions FG1 and FG2 included in the same memory cell transistor MC. As shown in Figure 59, in the memory cell transistor MCb, the semiconductor layer 56b is provided in a ring shape. An insulating layer 53b is provided between the semiconductor layers 56b and 52b. Similarly, although not shown, in the memory cell transistor MCa, the semiconductor layer 56a is provided in a ring shape. An insulating layer 53b is provided between the semiconductor layers 56a and 52ab.

[0276] <4-2>Operation Next, the operation of the memory device 1 according to the fourth embodiment will be described. In the following description, the memory group MG connected to the program bit line BLprog will be referred to as the "selected memory group". The memory group connected to the program disable bit line BLinn will be referred to as the "non-selected memory group".

[0277] (Specific example of an HE program) Figure 60 is a schematic diagram showing a specific example of the HE program for a selected memory group in the memory device 1 according to the fourth embodiment. Figure 60 shows the voltages applied to the word lines WLa(k-1), WLa(k), and WLa(k+1), the word lines WLb(k-1), WLb(k), and WLb(k+1), and the selected gate lines SGDa, SGSa, SGDb, and SGSb of the selected memory group, respectively, when the word line WLa(k) is selected as the selected word line WLsel in the HE program.

[0278] As shown in Figure 60, in the HE program, the sequencer 14 applies VHEP to the word line WLa(k), VPASS to the word lines WLa(k-1), WLa(k+1), WLb(k-1), WLb(k), and WLb(k+1), respectively, and VDDH, VDD, VSS, and VSS to the selected gate lines SGDa, SGSa, SGDb, and SGSb of the selected memory group, respectively.

[0279] Then, the selection transistors STa1 and STa2 turn ON, and electrons are supplied to the channel of the NAND string NSa based on the voltage difference between the source line SL and the program bit line BLprog. On the other hand, the selection transistors STb1 and STb2 turn OFF, and the current path between the source line SL and the program bit line BLprog is interrupted. Then, electrons are injected into the floating gate portion FG2 of the memory cell transistor MCa(k) based on the voltage of the word line WLa(k) and the channel current. Meanwhile, in the NAND string NSb, the current path between the source line SL and the program bit line BLprog is interrupted. For this reason, even if VHEP is applied to the word line WL(k), the injection of electrons into the floating gate portion FG2 of the memory cell transistor MCb(k) is suppressed.

[0280] Furthermore, in the HE program, electrons may be injected into the floating gate portion FG1 of the selected memory cell transistor MCsel. This is because even if the threshold voltage of the selected memory cell transistor MCsel changes, the subsequent loop processing will raise the threshold voltage of the selected memory cell transistor MCsel until it reaches the target state.

[0281] Figure 61 is a schematic diagram showing a specific example of an HE program for a non-selected memory group in the memory device 1 according to the fourth embodiment. Figure 61 shows the voltages applied to the word lines WLa(k-1), WLa(k), and WLa(k+1), the word lines WLb(k-1), WLb(k), and WLb(k+1), and the selected gate lines SGDa, SGSa, SGDb, and SGSb of the selected memory group, respectively, when the word line WL(k) is set to the selected word line WLsel in the HE program.

[0282] As shown in Figure 61, in the HE program, the sequencer 14 applies VHEP to the word line WLa(k), VPASS to the word lines WLa(k-1), WLa(k+1), WLb(k-1), WLb(k), and WLb(k+1), and VSS to the selection gate lines SGDa, SGSa, SGDb, and SGSb of the non-selected memory group. As a result, the selection transistors STa1, STa2, STb1, and STb2 are turned off, and the current path between the source line SL and the program bit line BLprog in the NAND strings NSa and NSb is interrupted. Therefore, even if VHEP is applied to the word line WLa(k), electron injection into the floating gate portion FG2 of the memory cell transistor MCa(k) is suppressed.

[0283] (Specific example of an FN program) Figure 62 is a schematic diagram showing a specific example of the FN program for a selected memory group in the memory device 1 according to the fourth embodiment. Figure 62 shows the voltages applied to the word lines WLa(k-1), WLa(k), and WLa(k+1), the word lines WLb(k-1), WLb(k), and WLb(k+1), and the selected gate lines SGDa, SGSa, SGDb, and SGSb of the selected memory group, respectively, when the word line WLa(k) is selected as the selected word line WLsel in the HE program.

[0284] As shown in Figure 62, in the FN program, the sequencer 14 applies VPGM to the word line WLa(k), VPASS to the word lines WLa(k-1), WLa(k+1), WLb(k-1), WLb(k), and WLb(k+1), respectively, and VDD, VDD, VSS, and VSS to the selected gate lines SGDa, SGSa, SGDb, and SGSb of the selected memory group, respectively.

[0285] Then, the selection transistors STa1 and STa2 are turned ON, and the channel potential of the NAND string NSa becomes VSS based on the voltage applied to the program bit line BLprog. Then, electrons are injected into the floating gate portion FG1 of the memory cell transistor MCa(k) based on the potential difference between the word line WLa(k) and the channel. On the other hand, the selection transistors STb1 and STb2 are turned OFF, and the channel potential of the NAND string NSa is boosted based on VPASS. As a result, electron injection into the floating gate portion FG2 of each memory cell transistor MCb(k) is suppressed in the NAND string NSb.

[0286] Figure 63 is a schematic diagram showing a specific example of an FN program for a non-selected memory group in the memory device 1 according to the fourth embodiment. Figure 63 shows the voltages applied to the word lines WLa(k-1), WLa(k), and WLa(k+1), the word lines WLb(k-1), WLb(k), and WLb(k+1), and the selected gate lines SGDa, SGSa, SGDb, and SGSb of the selected memory group, respectively, when the word line WLa(k) is selected as the selected word line WLsel in the FN program.

[0287] As shown in Figure 63, in the FN program, the sequencer 14 applies VPGM to the word line WLa(k), VPASS to each of the word lines WLa(k-1), WLa(k+1), WLb(k-1), WLb(k), and WLb(k+1), and VSS to each of the selection gate lines SGDa, SGSa, SGDb, and SGSb of the selection memory group. As a result, the selection transistors STa1, STa2, STb1, and STb2 are turned off, and the current path between the source line SL and the program bit line BLprog in each of the NAND strings NSa and NSb is interrupted. Therefore, the channel potentials of each of the NAND strings NSa and NSb are boosted based on VPASS. Consequently, in each of the NAND strings NSa and NSb of the non-selected memory group, electron injection into the floating gate portion FG1 of each memory cell transistor MCa and the floating gate portion FG1 of each memory cell transistor MCb is suppressed.

[0288] Other operations of the memory device 1 according to the fourth embodiment are the same as those of the third embodiment.

[0289] <4-3> Manufacturing method Next, an example of a method for manufacturing the memory device 1 according to the fourth embodiment will be described with reference to Figure 64 as appropriate. Figure 64 is a flowchart showing an example of a method for manufacturing the memory device 1 according to the fourth embodiment. Figures 65 to 72, which are referenced below, are cross-sectional views showing an example of a cross-sectional structure of the memory device 1 during the manufacturing process according to the fourth embodiment. Figures 65 to 72 each show the region where the memory pillar MP shown in Figure 58 is formed.

[0290] First, similar to the third embodiment, the lamination process of the sacrificial layer 60 and the insulating layer 31 is performed (S311). This forms, for example, a structure in which the insulating layer 31 and the sacrificial layer 60 are alternately laminated on the semiconductor substrate 20.

[0291] Next, a memory trench MT is formed (S401). Specifically, the memory trench MT is first formed by photolithography and etching. The memory trench MT is provided by separating the stacked sacrificial layer 60 and insulating layer 31. The formed memory trench MT is then embedded with the insulating layer. Hereinafter, the portion of the sacrificial layer 60 separated by the memory trench MT that is adjacent on one side of the memory trench MT will be called "sacrificial layer 60a", and the portion adjacent on the other side of the memory trench MT will be called "sacrificial layer 60b".

[0292] Next, as shown in Figure 65, a memory hole MH is formed (S402). In the fourth embodiment, the memory hole MH divides the memory trench MT. In the memory hole MH, a portion of the sacrificial layers 60a and 60b is exposed.

[0293] Next, the sacrificial layer 60 is recessed (S403). As shown in Figure 66, the S403 process removes portions of the sacrificial layers 60a and 60b that are exposed on the sides of the memory hole MH. This creates spaces on the sides of the memory hole MH that correspond to the recesses RPa and RPb of the memory pillar MP.

[0294] Next, as shown in Figure 67, insulating layers 51, 55, and 54 and a semiconductor layer 52 are formed (S404). The insulating layers 51, 55, and 54 are formed sequentially along the sides of the memory holes MH and recesses RP. The semiconductor layer 52 is formed to fill the spaces corresponding to the recesses RPa and RPb, and without filling the memory holes MH.

[0295] Next, a recess process is performed on the semiconductor layer 52 (S405). As shown in Figure 68, the semiconductor layer 52 provided on the side of the memory hole MH is removed by the process in S405, and a part of the insulating layer 54 is exposed within the memory hole MH. As a result, the semiconductor layer 52 is separated into a portion provided in the recess RPa (semiconductor layer 52a) and a portion provided in the recess RPb (semiconductor layer 52b).

[0296] Next, the insulator layers 54 and 55 are recessed (S406). As shown in Figure 69, the process in S406 removes portions of the insulator layers 54 and 55 that are exposed on the side surfaces of the memory holes MH so that they fit into recesses RPa and RPb, respectively. In addition, this process separates the insulator layer 54 into a portion provided in recess RPa (insulator layer 54a) and a portion provided in recess RPb (insulator layer 54b). Similarly, the insulator layer 55 is separated into a portion provided in recess RPa (insulator layer 55a) and a portion provided in recess RPb (insulator layer 55b).

[0297] Next, the semiconductor layers 52a and 52b are subjected to oxidation (S407). As a result, as shown in Figure 70, the surface portions of the semiconductor layers 52a and 52b that were exposed within the memory hole MH are oxidized, forming the insulating layers 53a and 54b. At this time, the semiconductor layer 52a is surrounded by the insulating layers 53a and 54a. The semiconductor layer 52b is surrounded by the insulating layers 53b and 54b.

[0298] Next, as shown in Figure 71, semiconductor layers 56a and 56b are formed (S408). Specifically, first, the semiconductor layer 56 is provided on the side surface of the memory hole MH. Then, the spaces provided in recesses RPa and RPb are filled with the semiconductor layer 56. After that, the semiconductor layer 56 provided on the side surface of the memory hole MH is removed by wet etching or the like. As a result, the semiconductor layer 56 is separated into a portion provided in recess RPa (semiconductor layer 56a) and a portion provided in recess RPb (semiconductor layer 56b).

[0299] Next, as shown in Figure 72, an insulating layer 50, a semiconductor layer 41, and a core member 40 are formed (S409). The insulating layer 55 and the semiconductor layer 41 are formed sequentially along the side surface of the memory hole MH. The core member 40 is formed so as to fill the memory hole MH. This creates a structure in which semiconductor layers 52a and 41 are adjacent via insulating layers 50 and 53a. Similarly, a structure is created in which semiconductor layers 52b and 41 are adjacent via insulating layers 50 and 53b.

[0300] Next, a replacement process is performed (S410). Specifically, first, a replacement hole STH is formed. Then, the stacked sacrificial layers 60a and 60b are selectively removed through the replacement hole STH by wet etching with thermal phosphoric acid or the like. After that, a conductor is embedded through the replacement hole STH into the space where the sacrificial layers 60a and 60b were removed. For example, CVD is used to form the conductor in this process. Subsequently, the conductor formed on the side of the replacement hole STH is removed by an etch-back process, and the conductor formed on the adjacent wiring layer is separated. As a result, a stacked wiring is formed that includes a plurality of conductor layers 22a that function as word lines WLa and a plurality of conductor layers 22b that function as word lines WLb.

[0301] <4-4> Effects of the fourth embodiment The memory device 1 according to the fourth embodiment can achieve the same effects as the third embodiment. Furthermore, since the memory device 1 according to the fourth embodiment has a structure in which the memory pillar MPb has two NAND strings NSa and NSb, the storage capacity can be increased compared to the third embodiment.

[0302] <5> others In the third embodiment, the case in which the threshold voltage distribution of the memory cell transistor MC described in the first embodiment is formed has been described, but the embodiment is not limited thereto. The third embodiment can also form the threshold voltage distribution of the memory cell transistor MC described in the second embodiment. In this case, the memory device 1 according to the third embodiment performs a write operation in which the processes S104 to S106 in the flowchart shown in Figure 32 are replaced by the processes S201 to S206 shown in Figure 25. Similarly, the memory device 1 according to the fourth embodiment may form the threshold voltage distribution of the memory cell transistor MC of either the first or second embodiment.

[0303] In the above embodiment, the example given is that the data writing order in each NAND string NS starts from the memory cell transistor MC on the bit line BL side, but it is not limited to this. The data writing order in each NAND string NS may start from the memory cell transistor MC on the source line SL side. In this case, the storage portion P2 of the memory cell transistor MC(k) is associated with the portion that faces the portion between the word lines WL(k) and WL(k+1) and is adjacent to the storage portion P1 of the memory cell transistor MC(k). Then, in each program operation (for example, the "ACE" program, the "BDFG" program, the HE program, the FN program), when the selected word line WLsel is the word line WL(k), the voltage applied to the word line WL(k+1) and the voltage applied to the word line WL(k-1) are swapped.

[0304] The above embodiments illustrate the case where the memory cell transistor MC stores 3 bits of data, but are not limited to this. The memory cell transistor MC may be configured to store 2 bits or 4 bits or more of data. In other words, in the above embodiments, the memory cell transistor MC only needs to be configured to store multiple bits of data at two or more threshold voltage levels. The technical ideas described in the first to fourth embodiments can be applied regardless of the number of bits stored in the memory cell transistor MC.

[0305] In the above embodiment, an example was given in which the sequencer 14 applies the read voltages to the selected word line WLsel in order from the highest to the lowest in a read operation using multiple read voltages, but the system is not limited to this. The sequencer 14 may also apply the read voltages to the selected word line WLsel in order from the lowest to the highest. Furthermore, in the above embodiment, an example was given in which each of the judgment results of multiple read operations is stored in the latch circuit of the sense amplifier unit SAU, but the system is not limited to this. The calculation processing for determining the data may be executed sequentially as the read operation progresses.

[0306] In the above embodiment, the memory cell array 10 may have dummy wiring. For example, the memory cell array 10 may have one or more dummy word lines between the uppermost word line WL and the selection gate line SGD. Similarly, the memory cell array 10 may have one or more dummy word lines between the lowermost word line WL and the selection gate line SGS. The intersection of the dummy word lines and the memory pillar MP corresponds to a memory cell transistor MC that is not used for data storage. By utilizing the dummy word lines, the memory device 1 can perform the write operation described in the above embodiment on the memory cell transistor MC located at the end of the NAND string NS. Similarly, the memory cell array 10a may have dummy wiring.

[0307] The timing chart used to describe the write operation in the above embodiment is merely an example. For example, the timing at which the voltages of the signals and wiring are controlled at each time point may be different. Also, some of the processes in each flowchart can be rearranged as much as possible. For example, the order in which the verify operation is performed in the loop process can be changed as appropriate. Furthermore, in the above embodiment, the voltages applied to the various wirings in the memory cell array 10 may be estimated based on the voltages of signal lines CG, SGDD, SGDS, USGD, and USGS. For example, the voltage applied to the selection word line WLsel can be estimated based on the voltage of the signal line CG.

[0308] In this specification, “connection” means that there is an electrical connection, and does not exclude the presence of another element in between. The off state of a transistor does not exclude the flow of a small current, such as leakage current. The “H” level is the voltage level at which an N-type MOS transistor to which the voltage is applied to the gate turns on, and a P-type MOS transistor to which the voltage is applied to the gate turns off. The “L” level is the voltage level at which an N-type MOS transistor to which the voltage is applied to the gate turns off, and a P-type MOS transistor to which the voltage is applied to the gate turns on. Insulators embedded in slits SLT, slits SHE, memory trenches MT, and replacement holes STH may be called insulating members. VPGM and VHEP may each be called program voltages. “Columnar” indicates a structure provided within a hole formed in the manufacturing process of memory device 1. “Diameter (inner diameter)” refers to the diameter of a hole, etc., in a cross-section parallel to the surface of the substrate. “Outer diameter” refers to the diameter of a memory pillar MP, etc., in a cross-section parallel to the surface of the substrate. "Width" refers to, for example, the size of a component in the X or Y direction. Dimensional comparisons are preferably performed in the vicinity of the memory cell transistor (MC) of interest. The "semiconductor layer" may also be called a "conductive layer." The first to fourth embodiments illustrate, but are not limited to, the case of 3 bits / cell. The first to fourth embodiments may be applied to memories storing multiple thresholds, such as 4 bits / cell and 2 bits / cell.

[0309] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0310] 1...Memory device, 2...Memory controller, 10, 10a, 10b...Memory cell array, 11...Input / output circuit, 12...Logic controller, 13...Register circuit, 14...Programmable logic controller, 15...Driver circuit, 16...Raw decoder module, 17...Sense amplifier module, 20...Semiconductor substrate, 21-24...Conductive layer, 30-34...Insulating layer, 35...Semiconductor layer, 40...Core component, 41...Semiconductor layer, 42...Laminated film, 43...Tunnel insulating film, 44...Insulating film, 45...Block insulating film, 50, 51...Insulating layer, 52...Semiconductor layer, 53 ~55...Insulator layer, 56...Semiconductor layer, 70...Semiconductor substrate, 71...Insulator layer, 72...Conductive layer, BLK...Block, SU...String unit, MG...Memory group, BL...Bit line, WL...Word line, SGD, SGS...Selection gate line, MC...Memory cell transistor, ST1, ST2...Selection transistor, FG1, FG2...Floating gate section, P1, P2...Storage section, RA1, RA2...Replacement area, RD...Raw decoder, SAU...Sense amplifier unit, TS1, TS2...Sense time, IS1, IS2...Sense current

Claims

1. A memory pillar comprising a semiconductor layer stretched in a first direction and a laminated film covering at least the side surface of the semiconductor layer, A plurality of conductive layers are stacked in the first direction, each extending in a second direction intersecting the first direction, and facing the memory pillar, A plurality of memory cells are provided at the intersections of the memory pillar and the plurality of conductive layers, each configured to store multiple bit data at a threshold voltage level of k (where k is an integer of 2 or more), A sequencer configured to perform a write operation having a loop process including program operation and verification operation, The aforementioned program operation includes a first program process and a second program process, The plurality of conductive layers include a first conductive layer and a second conductive layer and a third conductive layer provided adjacent to the first conductive layer. The plurality of memory cells include a first memory cell corresponding to the first conductive layer, a second memory cell corresponding to the second conductive layer, and a third memory cell corresponding to the third conductive layer. In the write operation, the sequencer causes the data to be stored in the first memory cell by either the first program processing or the second program processing, depending on the data to be written to the first memory cell. The first memory cell has a first S-factor when storing data written by the first program processing, and has a second S-factor different from the first S-factor when storing data written by the second program processing. The aforementioned sequencer, In the first program processing targeting the first memory cell, a program voltage is applied to the first conductive layer, a first voltage is applied to the second conductive layer, and a third voltage is applied to the third conductive layer. In the second program processing targeting the first memory cell, the program voltage is applied to the first conductive layer, a fourth voltage lower than the first voltage is applied to the second conductive layer, and the third voltage is applied to the third conductive layer. Memory device.

2. A memory pillar comprising a semiconductor layer stretched in a first direction and a laminated film covering at least the side surface of the semiconductor layer, A plurality of conductive layers are stacked in the first direction, each extending in a second direction intersecting the first direction, and facing the memory pillar, A plurality of memory cells are provided at the intersections of the memory pillar and the plurality of conductive layers, each configured to store multiple bit data at a threshold voltage level of k (where k is an integer of 2 or more), A sequencer configured to perform a write operation having a loop process including program operation and verification operation, The aforementioned program operation includes a first program process and a second program process, The plurality of conductive layers include a first conductive layer and a second conductive layer and a third conductive layer provided adjacent to the first conductive layer. The plurality of memory cells include a first memory cell corresponding to the first conductive layer, a second memory cell corresponding to the second conductive layer, and a third memory cell corresponding to the third conductive layer. In the write operation, the sequencer causes the data to be stored in the first memory cell by either the first program processing or the second program processing, depending on the data to be written to the first memory cell. When reading data written to the first memory cell by the first program processing, a first sense time is used, and when reading data written to the first memory cell by the second program processing, a second sense time different from the first sense time is used. In the first program processing targeting the first memory cell, a program voltage is applied to the first conductive layer, a first voltage is applied to the second conductive layer, and a third voltage is applied to the third conductive layer. In the second program processing targeting the first memory cell, the program voltage is applied to the first conductive layer, a fourth voltage lower than the first voltage is applied to the second conductive layer, and the third voltage is applied to the third conductive layer. Memory device.

3. The laminated film has a charge storage layer, The charge storage layer is The first storage section is the portion facing the first conductive layer, It has a second storage portion which is a portion not facing the first conductive layer, The second storage unit faces the portion between the first conductive layer and the second conductive layer, and is adjacent to the first storage unit. The memory device according to claim 1 or claim 2.

4. The threshold voltage level of the k value consists of the first to the k threshold voltage levels. In the aforementioned write operation, the sequencer, When data is stored in the first memory cell by the first program processing described above, the first memory cell is written to the nth threshold voltage level (where n is an even number and an integer between 2 and k). When data is stored in the first memory cell by the second program processing described above, the first memory cell is written to the mth threshold voltage level (where m is an odd number and an integer between 3 and k). In the program operation described above, the second program process is executed after the first program process. The memory device according to claim 1 or claim 2.

5. The verification operation includes a first verify read associated with writing data corresponding to the n threshold voltage level, and a second verify read associated with writing data corresponding to the (n+1) threshold voltage level. The sequencer performs the first verify readout and the second verify readout simultaneously using the same verify voltage. The memory device according to claim 4.

6. The sequencer, in the verification operation, performs a verify read using a first sense time in each case: when the first memory cell is the target of the first program processing, and when the first memory cell is the target of the second program processing. The memory device according to claim 1 or claim 2.

7. In the verification operation, the sequencer performs a verify readout using a first sense time if the first memory cell is the target of the first program processing, and performs a verify readout using a second sense time if the first memory cell is the target of the second program processing. The memory device according to claim 1 or claim 2.

8. The system further comprises a sense amplifier connected to the first memory cell and having a sense node, The first sense time and the second sense time are each associated with the time from when the sense node and the first memory cell are electrically connected while a read voltage is applied to the first memory cell until the connection between the sense node and the first memory cell is electrically disconnected, and the first sense time is different from the second sense time. The memory device according to claim 7.

9. A bit line and Source line and, A first memory string comprising: a plurality of memory cells connected in series, each configured to store multiple bit data at a threshold voltage level of value k (where k is an integer of 2 or greater); a first selection transistor connected between the plurality of memory cells and the bit line; and a second selection transistor connected between the plurality of memory cells and the source line; Multiple word lines connected to the gates of the multiple memory cells, A first selection gate line connected to the gate of the first selection transistor, A second selection gate line connected to the gate of the second selection transistor, A sequencer configured to perform a write operation having a first program operation and a loop processing including a second program operation and a verify operation, The plurality of word lines include a first word line and a second word line provided adjacent to the first word line. The plurality of memory cells include a first memory cell corresponding to the first word line and a second memory cell corresponding to the second word line. Each of the plurality of memory cells has a first floating gate portion and a second floating gate portion. The aforementioned sequencer, In the first program operation in which the first memory cell is the target of the program, while the first program voltage is applied to the first word line, a first voltage lower than the first program voltage is applied to the first select gate line, a second voltage lower than the first voltage is applied to the second select gate line, and a third voltage lower than the first program voltage is applied to the second word line. In the second program operation in which the first memory cell is the target of the program, while the second program voltage is applied to the first word line, a fourth voltage lower than the first voltage is applied to the first selection gate line, the second voltage is applied to the second selection gate line, and the third voltage is applied to the second word line. In the write operation, the first memory cell is set to be writeable or write-protected according to the data to be written to the first memory cell, the first program operation is executed, and the data is stored in the first memory cell by the loop process. Memory device.

10. The first memory cell has a first S-factor when storing data written by the first program operation, and has a second S-factor different from the first S-factor when storing data written by the second program operation. The memory device according to claim 9.

11. The first program operation is a program operation targeting the second floating gate section, and the second program operation is a program operation targeting the first floating gate section. The memory device according to claim 9.

12. In the first program operation described above, hot electrons are used to inject electrons into the second floating gate portion. In the second program operation described above, an FN (Fowler-Nordheim) tunnel current is used to inject electrons into the first floating gate portion. The memory device according to claim 11.

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