Semiconductor equipment

Abstract

To provide a semiconductor device whose surge current tolerance is improved.SOLUTION: A semiconductor device in an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first part in contact with a first surface, a plurality of p-type second silicon carbide regions, an n-type third silicon carbide region, a plurality of p-type fourth silicon carbide regions connecting between the second silicon carbide regions, a first electrode, a second electrode, and a gate electrode. The diode region includes an n-type first silicon carbide region having a second part in contact with the first surface, p-type fifth silicon carbide regions, a plurality of p-type sixth silicon carbide regions connecting between the fifth silicon carbide regions, a first electrode, and a second electrode. In addition, a seventh silicon carbide region connecting the third silicon carbide region and the fifth silicon carbide region is included.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device.

Background Art

[0002] Silicon carbide is one of the materials for semiconductor devices. Silicon carbide has excellent physical properties, with a band gap about 3 times, a breakdown electric field strength about 10 times, and a thermal conductivity about 3 times that of silicon. By utilizing these characteristics, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with high breakdown voltage, low loss, and capable of high-temperature operation can be realized.

[0003] A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, it is possible to pass a reflux current by using the built-in diode.

[0004] However, when a reflux current is passed using the body diode, there is a problem that stacking faults grow in the silicon carbide layer due to carrier recombination energy, increasing the on-resistance of the MOSFET. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET. For example, by providing a Schottky Barrier Diode (SBD) that operates in a unipolar manner as a built-in diode in the MOSFET, growth of stacking faults in the silicon carbide layer can be suppressed. Providing the SBD as a built-in diode in the MOSFET improves the reliability of the MOSFET.

[0005] A large surge current that momentarily exceeds the steady state may flow through the MOSFET. When a large surge current flows, a large surge voltage is applied to generate heat, and the MOSFET is destroyed. The maximum allowable peak current value (I FSMThis is called surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2023-77119 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The problem that this invention aims to solve is to provide a semiconductor device with improved surge current withstand capability. [Means for solving the problem]

[0008] The semiconductor device of the embodiment comprises a plurality of transistor regions and a plurality of diode regions arranged alternately in a first direction, wherein the transistor region is a silicon carbide layer having a first surface and a second surface opposite to the first surface, and comprises an n-type first silicon carbide region having a plurality of first portions that are in contact with the first surface, extend in a second direction perpendicular to the first direction and arranged in the first direction, and a plurality of p-type second silicon carbide regions provided between the first silicon carbide region and the first surface, extend in a second direction and arranged in the first direction A silicon carbide layer comprising: a silicon carbide region; an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a plurality of p-type fourth silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction and connecting two adjacent second silicon carbide regions; a first electrode in contact with the first portion, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region; a second electrode in contact with the second surface; and a second electrode facing the second silicon carbide region. The diode region includes a plurality of gate electrodes extending in the second direction and arranged in the first direction, and a gate insulating layer provided between the gate electrodes and the second silicon carbide region, wherein the diode region includes an n-type first silicon carbide region having a plurality of second portions touching the first surface and extending in the second direction, a plurality of p-type fifth silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction, and provided between the first silicon carbide region and the first surface A silicon carbide layer comprising: a plurality of p-type sixth silicon carbide regions arranged in a second direction and connecting two adjacent fifth silicon carbide regions; a first electrode in contact with the second portion, the fifth silicon carbide regions, and the sixth silicon carbide regions; and a second electrode, wherein the silicon carbide layer further comprises a plurality of p-type seventh silicon carbide regions provided between the first silicon carbide region and the first surface and arranged in the second direction, connecting adjacent second silicon carbide regions and the fifth silicon carbide regions. [Brief explanation of the drawing]

[0009] [Figure 1]A schematic top view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 3] A schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 4] An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 5] An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 6] A schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 7] A schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 8] An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 9] An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 10] A schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 11] A schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 12] An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 13] An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 14] A schematic top view of the semiconductor device according to the first embodiment. [Figure 15] A schematic top view of the semiconductor device of the first comparative example. [Figure 16] A schematic cross-sectional view of the semiconductor device of the first comparative example. [Figure 17] Equivalent circuit diagram of the semiconductor device of the first comparative example. [Figure 18] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 19] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 20] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 21] A schematic top view of the semiconductor device of the third comparative example. [Figure 22] Diagram illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 23] Diagram illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 24] Schematic cross-sectional view of a semiconductor device according to the first modification of the first embodiment. [Figure 25] Schematic cross-sectional view of a semiconductor device according to the first modification of the first embodiment. [Figure 26] Schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 27] Schematic top view of a part of the semiconductor device according to the second embodiment. [Figure 28] Schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 29] Schematic top view of a part of the semiconductor device according to the second embodiment. [Figure 30] Schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 31] Schematic top view of a part of the semiconductor device according to the second embodiment. [Modes for Carrying Out the Invention]

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members and the like are denoted by the same reference numerals, and descriptions of members and the like that have been once described may be omitted as appropriate.

[0011] Further, in the following description, n + , n, n - , and p + , p, p - notations represent relative levels of impurity concentration in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + has a relatively higher p-type impurity concentration than p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. In addition, n + type, n- Simply refer to the type as n type, p + type, p - Sometimes the type is simply written as type p.

[0012] Impurity concentrations can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative levels of impurity concentrations can be determined, for example, from the carrier concentrations obtained by SCM (Scanning Capacitance Microscopy). Additionally, distances such as the depth and thickness of impurity regions can be determined, for example, from images obtained by SEM (Scanning Electron Microscope) or by SIMS.

[0013] In this specification, unless otherwise specified, the impurity concentration in the semiconductor region refers to the maximum impurity concentration in that semiconductor region.

[0014] (First Embodiment) The semiconductor device of the first embodiment comprises a plurality of transistor regions and a plurality of diode regions arranged alternately in a first direction. The transistor region is a silicon carbide layer having a first surface and a second surface opposite to the first surface, and includes a plurality of n-type first silicon carbide regions having a plurality of first portions that are in contact with the first surface, extend in a second direction perpendicular to the first direction, and are arranged in the first direction; a plurality of p-type second silicon carbide regions provided between the first silicon carbide region and the first surface, extend in a second direction, and are arranged in the first direction; a third n-type silicon carbide region provided between the second silicon carbide region and the first surface; and the first silicon carbide region and the first A silicon carbide layer including a plurality of p-type fourth silicon carbide regions provided between the surface and arranged in a second direction, connecting two adjacent second silicon carbide regions; a first electrode in contact with the first portion, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region; a second electrode in contact with the second surface; a plurality of gate electrodes facing the second silicon carbide region, extending in a second direction and arranged in a first direction; and a gate insulating layer provided between the gate electrodes and the second silicon carbide region. The diode region includes a silicon carbide layer comprising: an n-type first silicon carbide region having a plurality of second portions in contact with a first surface and extending in a second direction; a plurality of p-type fifth silicon carbide regions provided between the first silicon carbide region and the first surface, extending in a second direction and arranged in the first direction; and a plurality of p-type sixth silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in a second direction, and connecting two adjacent fifth silicon carbide regions; a first electrode in contact with the second portions, the fifth silicon carbide regions, and the sixth silicon carbide regions; and a second electrode. The silicon carbide layer further comprises a plurality of p-type seventh silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in a second direction, and connecting adjacent second silicon carbide regions and fifth silicon carbide regions.

[0015] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the body region and source region are formed by ion implantation, for example. The semiconductor device of the first embodiment also includes an SBD (Shottky Barrier Diode) as an internal diode. The MOSFET 100 is a vertical n-channel type MOSFET that uses electrons as carriers.

[0016] Figures 1(a) and 1(b) are schematic top views of a semiconductor device according to the first embodiment. Figure 1(a) is a diagram showing the arrangement of each region of the MOSFET 100. Figure 1(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 100.

[0017] Figures 2(a) and 2(b) are schematic cross-sectional views of a part of the semiconductor device of the first embodiment. Figure 3 is a schematic top view of a part of the semiconductor device of the first embodiment. Figures 4 and 5 are enlarged schematic cross-sectional views of a part of the semiconductor device of the first embodiment.

[0018] Figure 2(a) is a section AA' of Figure 3. Figure 2(b) is a section BB' of Figure 3. Figure 4 is an enlarged schematic cross-sectional view of a portion of Figure 2(a). Figure 5 is an enlarged schematic cross-sectional view of a portion of Figure 2(b).

[0019] Figures 6(a) and 6(b) are schematic cross-sectional views of a part of the semiconductor device of the first embodiment. Figure 7 is a schematic top view of a part of the semiconductor device of the first embodiment. Figures 8 and 9 are enlarged schematic cross-sectional views of a part of the semiconductor device of the first embodiment.

[0020] Figure 6(a) is a cross-section of CC' in Figure 7. Figure 6(b) is a cross-section of DD' in Figure 7. Figure 8 is an enlarged schematic cross-sectional view of a portion of Figure 6(a). Figure 9 is an enlarged schematic cross-sectional view of a portion of Figure 6(b).

[0021] Figures 10(a) and 10(b) are schematic cross-sectional views of a part of the semiconductor device of the first embodiment. Figure 11 is a schematic top view of a part of the semiconductor device of the first embodiment. Figures 12 and 13 are enlarged schematic cross-sectional views of a part of the semiconductor device of the first embodiment.

[0022] Figure 10(a) is a section of EE' in Figure 11. Figure 10(b) is a section of FF' in Figure 11. Figure 12 is an enlarged schematic cross-sectional view of a portion of Figure 10(a). Figure 13 is an enlarged schematic cross-sectional view of a portion of Figure 10(b).

[0023] As shown in Figure 1(a), the MOSFET 100 comprises a plurality of transistor regions 101, a plurality of diode regions 102, and a termination region 103.

[0024] Multiple transistor regions 101 and multiple diode regions 102 are arranged alternately in a first direction parallel to the first plane P1. In the first direction, a transistor region 101 is sandwiched between, for example, two diode regions 102. In the first direction, a diode region 102 is sandwiched between, for example, two transistor regions 101.

[0025] The width of the transistor region 101 in the first direction (w1 in Figure 1(a)) is, for example, greater than the width of the diode region 102 in the first direction (w2 in Figure 1(a)).

[0026] Figure 1(a) illustrates a case where two transistor regions 101 and three diode regions 102 are arranged in the first direction. However, the number of transistor regions 101 and diode regions 102 is not limited to this number.

[0027] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0028] The termination region 103 surrounds the transistor region 101 and the diode region 102. The termination region 103 is provided with a structure to improve the breakdown voltage of the MOSFET 100. This structure to improve the breakdown voltage of the MOSFET 100 is, for example, a resurf or a guard ring.

[0029] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and gate wiring 24.

[0030] Within the silicon carbide layer 10, n + Drain region 26 of type n - Type drift region 28 (first silicon carbide region), p-type body region 30 (second silicon carbide region), n + The p-type includes a source region 32 (third silicon carbide region), a p-type anode region 34 (fifth silicon carbide region), a p-type first bridging region 36 (fourth silicon carbide region), a p-type second bridging region 38 (sixth silicon carbide region), and a p-type third bridging region 40 (seventh silicon carbide region).

[0031] The drift region 28 includes a plurality of first parts 28a and a plurality of second parts 28b.

[0032] Figures 2(a), 2(b), 3, 4, and 5 show the transistor region 101.

[0033] As shown in Figures 2(a), 2(b), 3, 4, and 5, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. Within the silicon carbide layer 10 of the transistor region 101, n + Drain region 26 of type n - A drift region 28 of type p (first silicon carbide region), multiple p-type body regions 30 (second silicon carbide region), multiple n +It includes a source region 32 of type p (third silicon carbide region) and multiple first bridging regions 36 of type p (fourth silicon carbide region).

[0034] Note that Figure 3 shows only the patterns of the drift region 28, the body region 30, the first bridging region 36, and the gate electrode 18.

[0035] In the transistor region 101, the source electrode 12, the first portion 28a of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. In addition, the source electrode 12, the body region 30, the drift region 28, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

[0036] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

[0037] The silicon carbide layer 10 comprises a first surface ("P1" in Figures 2(a) and 2(b)) and a second surface ("P2" in Figures 2(a) and 2(b)). The first surface P1 and the second surface P2 face each other. Hereinafter, the first surface may be referred to as the front surface and the second surface as the back surface. Hereinafter, "depth" refers to the depth relative to the first surface.

[0038] The first surface P1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0039] n + The drain region 26 is provided on the back side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 26 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm-3 The following applies:

[0040] n - A drift region 28 of this type is provided between the drain region 26 and the first surface P1. A drift region 28 is provided between the source electrode 12 and the drain electrode 14. A drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0041] The drift region 28 is located on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 28 is lower than the n-type impurity concentration in the drain region 26. The n-type impurity concentration in the drift region 28 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 17 cm -3 The following applies: The thickness of the drift region 28 is, for example, between 5 μm and 150 μm.

[0042] The drift region 28 includes a plurality of first portions 28a. The first portions 28a are tangent to the first surface P1.

[0043] The first portion 28a extends in a second direction perpendicular to the first direction. The first portion 28a is repeatedly arranged in the first direction. The first portion 28a is sandwiched between two adjacent body regions 30 in the first direction.

[0044] The first portion 28a functions as the n-type semiconductor region of the SBD.

[0045] The p-shaped body region 30 is provided between the drift region 28 and the first surface P1. The body region 30 extends in a second direction. The body region 30 is repeatedly arranged in the first direction.

[0046] A portion of the body region 30 functions as the channel region of the MOSFET 100. The body region 30 functions as the p-type semiconductor region of the pn junction diode.

[0047] The body region 30 includes, for example, a low-concentration portion and a high-concentration portion. The high-concentration portion is provided between the low-concentration portion and the first surface P1. The p-type impurity concentration in the high-concentration portion is higher than that in the low-concentration portion.

[0048] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the body region 30 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm -3 The following applies. Note that the p-type impurity concentration in the body region 30 is defined as the p-type impurity concentration at half the depth of the body region 30.

[0049] The depth of the body region 30 is, for example, 0.3 μm or more and 1.0 μm or less.

[0050] The body region 30 is fixed at the potential of the source electrode 12.

[0051] n + The source region 32 of the mold is provided between the body region 30 and the first surface P1. The source region 32 extends, for example, in a second direction.

[0052] Source region 32 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 32 is higher than the concentration of n-type impurities in drift region 28.

[0053] The n-type impurity concentration in source region 32 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies: The depth of the source region 32 is shallower than the depth of the body region 30. For example, the depth of the source region 32 is between 0.1 μm and 0.3 μm.

[0054] The first p-shaped bridging region 36 is provided between the drift region 28 and the first surface P1. The first bridging region 36 is repeatedly arranged in the second direction.

[0055] The first bridging region 36 connects two adjacent body regions 30 in a first direction. The first bridging region 36 extends, for example, in a first direction. The first bridging region 36 intersects, for example, with a body region 30. The first bridging region 36 overlaps, for example, with a body region 30.

[0056] The first bridging region 36 divides the first portion 28a that extends in the second direction. The first bridging region 36 connects two adjacent body regions 30, separated by an n-type first portion 28a, with a p-type silicon carbide region.

[0057] The distance (dx in Figure 3) between two adjacent first bridging regions 36 in the second direction is, for example, smaller than the width of the transistor region 101 in the first direction (w1 in Figure 1(a)). The distance (dx) between two adjacent first bridging regions 36 in the second direction is, for example, between 10 μm and 200 μm.

[0058] The width of the first bridged region 36 in the second direction (wx in Figure 3) is, for example, smaller than the first distance in the first direction between two adjacent first portions 28a (d1 in Figures 2(a) and 3). The width of the first bridged region 36 in the second direction (wx in Figure 3) is, for example, less than or equal to half the first distance in the first direction between two adjacent first portions 28a (d1 in Figures 2(a) and 3).

[0059] The first distance d1 in the first direction between two adjacent first portions 28a is, for example, 3 μm or more and 30 μm or less. The width wx in the second direction of the first crosslinking region 36 is, for example, 1 μm or more and 10 μm or less.

[0060] The first crosslinking region 36 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first crosslinking region 36 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0061] The p-type impurity concentration in the first crosslinking region 36 is substantially the same as, for example, the p-type impurity concentration in the body region 30. The p-type impurity concentration in the first crosslinking region 36 is defined as the p-type impurity concentration at half the depth of the first crosslinking region 36.

[0062] The depth of the first crosslinking region 36 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the first crosslinking region 36 is, for example, substantially the same as the depth of the body region 30.

[0063] The potential of the first bridging region 36 is fixed to the potential of the source electrode 12.

[0064] Although Figure 3 illustrates a case where two first bridging regions 36 are arranged in the second direction, there may be three or more first bridging regions 36.

[0065] The gate electrode 18 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate electrode 18 extends in a second direction parallel to the first surface P1 and perpendicular to the first direction. Multiple gate electrode 18s are arranged parallel to each other in the first direction. The gate electrode 18 has a so-called stripe shape.

[0066] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0067] The gate electrode 18 faces, for example, the portion of the body region 30 that is in contact with the first surface P1. The gate electrode 18 also faces, for example, the portion of the drift region 28 that is in contact with the first surface P1.

[0068] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 30. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region 28.

[0069] The gate insulating layer 16 is, for example, silicon oxide. For the gate insulating layer 16, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0070] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0071] The source electrode 12 is provided on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface P1.

[0072] The source electrode 12 is in contact with the first portion 28a of the drift region 28, the body region 30, the source region 32, and the first bridging region 36.

[0073] The source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a layered structure of titanium (Ti) and aluminum (Al).

[0074] The body region 30, the source region 32, and the portion of the source electrode 12 in contact with the first bridging region 36 are, for example, made of metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. The portion of the source electrode 12 in contact with the first portion 28a of the drift region 28 is, for example, not provided with metal silicide.

[0075] The junction between the body region 30, the source region 32, and the first bridging region 36 and the source electrode 12 is, for example, an ohmic junction. The junction between the first portion 28a of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0076] The drain electrode 14 is provided on the side of the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface P2. The drain electrode 14 is in contact with the drain region 26.

[0077] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0078] The junction between the drain region 26 and the drain electrode 14 is, for example, an ohmic junction.

[0079] Figures 6(a), 6(b), 7, 8, and 9 show the diode region 102.

[0080] As shown in Figures 6(a), 6(b), 7, 8, and 9, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). Within the silicon carbide layer 10 of the diode region 102, n + Drain region 26 of type n - It includes a type drift region 28 (first silicon carbide region), multiple p-type anode regions 34 (fifth silicon carbide region), and a second p-type bridging region 38 (sixth silicon carbide region).

[0081] Note that Figure 7 shows only the patterns of the drift region 28, the anode region 34, and the second bridging region 38.

[0082] In the diode region 102, the source electrode 12, the second portion 28b of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. In addition, the source electrode 12, the anode region 34, the drift region 28, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

[0083] The drift region 28 includes a plurality of second portions 28b. The second portions 28b are tangent to the first surface P1.

[0084] The second portion 28b extends in a second direction. The second portion 28b is repeatedly arranged in the first direction. The second portion 28b is sandwiched between two adjacent anode regions 34 in the first direction.

[0085] The second portion 28b functions as the n-type semiconductor region of the SBD.

[0086] The p-type anode region 34 is provided between the drift region 28 and the first surface P1. The anode region 34 functions as the p-type semiconductor region of the pn junction diode.

[0087] The anode region 34 includes, for example, a low-concentration portion and a high-concentration portion. The high-concentration portion is located between the low-concentration portion and the first surface P1. The p-type impurity concentration in the high-concentration portion is higher than that in the low-concentration portion.

[0088] The anode region 34 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the anode region 34 is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 21 cm -3 The following applies. Note that the p-type impurity concentration in the anode region 34 is defined as the p-type impurity concentration at half the depth of the anode region 34.

[0089] The width of the anode region 34 in the first direction (wb in Figure 7) is, for example, greater than the width of the body region 30 in the first direction.

[0090] The depth of the anode region 34 is, for example, substantially the same as the depth of the body region 30. The depth of the anode region 34 is, for example, between 0.3 μm and 1.0 μm.

[0091] The anode region 34 is fixed at the potential of the source electrode 12.

[0092] The p-shaped second bridging region 38 is provided between the drift region 28 and the first surface P1. The second bridging region 38 is repeatedly arranged in the second direction.

[0093] The second bridging region 38 connects two adjacent anode regions 34 in the first direction. The second bridging region 38 extends, for example, in the first direction. The second bridging region 38 intersects, for example, with the anode region 34. The second bridging region 38 overlaps, for example, with the anode region 34.

[0094] The second bridging region 38 divides the second portion 28b that extends in the second direction. The second bridging region 38 connects two adjacent anode regions 34, separated by an n-type second portion 28b, with a p-type silicon carbide region.

[0095] The distance between two adjacent second bridging regions 38 in the second direction (dy in Figure 7) is, for example, smaller than the width of the transistor region 101 in the first direction (w1 in Figure 1(a)). The distance between two adjacent second bridging regions 38 in the second direction (dy) is, for example, between 10 μm and 200 μm.

[0096] The width of the second bridging region 38 in the second direction (wy in Figure 7) is, for example, smaller than the width of the anode region 34 in the first direction (wb in Figure 7). The width of the second bridging region 38 in the second direction (wy in Figure 7) is, for example, less than or equal to half the width of the anode region 34 in the first direction (wb in Figure 7).

[0097] Furthermore, the width of the second bridge region 38 in the second direction (wy in Figure 7) is smaller than, for example, the second distance in the first direction between two adjacent second portions 28b (d2 in Figures 6(a) and 7). The width of the second bridge region 38 in the second direction (wy in Figure 7) is, for example, less than or equal to half the second distance in the first direction between two adjacent second portions 28b (d2 in Figure 6(a)).

[0098] The second distance d2 in the first direction between two adjacent second portions 28b is, for example, 3 μm or more and 30 μm or less. The width wy in the second direction of the second crosslinking region 38 is, for example, 1 μm or more and 10 μm or less.

[0099] The second distance in the first direction between two adjacent second portions 28b (d2 in Figures 6(a) and 7) is substantially equal to, for example, the first distance in the first direction between two adjacent first portions 28a (d1 in Figure 2(a)).

[0100] The second crosslinking region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the second crosslinking region 38 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0101] The p-type impurity concentration in the second cross-linking region 38 is substantially the same as, for example, the p-type impurity concentration in the anode region 34. The p-type impurity concentration in the second cross-linking region 38 is substantially the same as, for example, the p-type impurity concentration in the first cross-linking region 36. The p-type impurity concentration in the second cross-linking region 38 is defined as the p-type impurity concentration at half the depth of the second cross-linking region 38.

[0102] The depth of the second crosslinking region 38 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the second crosslinking region 38 is, for example, substantially the same as the depth of the anode region 34. The depth of the second crosslinking region 38 is, for example, substantially the same as the depth of the first crosslinking region 36.

[0103] The potential of the second bridging region 38 is fixed to the potential of the source electrode 12.

[0104] Although Figure 7 illustrates a case where two second bridging regions 38 are arranged in the second direction, there may be three or more second bridging regions 38.

[0105] The source electrode 12 is provided on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface P1.

[0106] The source electrode 12 is in contact with the second portion 28b of the drift region 28, the anode region 34, and the second bridging region 38.

[0107] The body region 30, the anode region 34, and the portion of the source electrode 12 in contact with the second bridging region 38 are, for example, made of metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. The portion of the source electrode 12 in contact with the second portion 28b of the drift region 28 is, for example, not provided with metal silicide.

[0108] The junction between the anode region 34 and the second bridging region 38 and the source electrode 12 is, for example, an ohmic junction. The junction between the second portion 28b of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0109] Figures 10(a), 10(b), 11, 12, and 13 show the boundary between the transistor region 101 and the diode region 102.

[0110] As shown in Figures 10(b), 11, and 13, the silicon carbide layer 10 at the boundary between the transistor region 101 and the diode region 102 includes a p-type third bridging region 40 (seventh silicon carbide region).

[0111] The p-shaped third bridging region 40 is provided between the drift region 28 and the first surface P1. The third bridging region 40 is repeatedly arranged in the second direction.

[0112] The third bridging region 40 connects the adjacent body region 30 and anode region 34 in the first direction.

[0113] The third bridging region 40 divides the drift region 28 that extends in the second direction on the first surface. The third bridging region 40 connects adjacent body regions 30 and anode region 34, which are separated by an n-type drift region 28, with a p-type silicon carbide region.

[0114] The third bridging region 40 is in contact with, for example, the first bridging region 36 and the second bridging region 38. The first bridging region 36, the second bridging region 38, and the third bridging region 40 are continuous in, for example, a first direction.

[0115] The distance between two adjacent third bridging regions 40 in the second direction (dz in Figure 11) is, for example, smaller than the width of the transistor region 101 in the first direction (w1 in Figure 1(a)). The distance between two adjacent third bridging regions 40 in the second direction (dz) is, for example, between 10 μm and 200 μm.

[0116] The width of the third crosslinking region 40 in the second direction (wz in Figure 11) is, for example, smaller than the second distance in the first direction between two adjacent second portions 28b (d2 in Figure 11). The second distance d2 in the first direction between two adjacent second portions 28b is, for example, 3 μm or more and 30 μm or less. The width of the third crosslinking region 40 in the second direction (wz) is, for example, 1 μm or more and 10 μm or less.

[0117] The third crosslinking region 40 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the third crosslinking region 40 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0118] The p-type impurity concentration in the third crosslinking region 40 is substantially the same as, for example, the p-type impurity concentration in the body region 30 and the anode region 34. The p-type impurity concentration in the third crosslinking region 40 is substantially the same as, for example, the p-type impurity concentration in the first crosslinking region 36. The p-type impurity concentration in the third crosslinking region 40 is substantially the same as, for example, the p-type impurity concentration in the second crosslinking region 38. Note that the p-type impurity concentration in the third crosslinking region 40 is defined as the p-type impurity concentration at half the depth of the third crosslinking region 40.

[0119] The depth of the third crosslinking region 40 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the third crosslinking region 40 is, for example, substantially the same as the depth of the body region 30 and the anode region 34. The depth of the third crosslinking region 40 is, for example, substantially the same as the depth of the first crosslinking region 36. The depth of the third crosslinking region 40 is, for example, substantially the same as the depth of the second crosslinking region 38.

[0120] The potential of the third bridging region 40 is fixed to the potential of the source electrode 12.

[0121] Although Figure 11 illustrates the case where two third bridging regions 40 are arranged in the second direction, there may be three or more third bridging regions 40.

[0122] The source electrode 12 is provided on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface P1.

[0123] The source electrode 12 is in contact with the third bridging region 40.

[0124] The portion of the source electrode 12 in contact with the third bridging region 40 is, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

[0125] The junction between the third bridging region 40 and the source electrode 12 is, for example, an ohmic junction.

[0126] Figure 14 is a schematic top view of a semiconductor device according to the first embodiment. Figure 14 shows the pattern of the body region 30 projected onto the first surface P1 and the pattern of the anode region 34 projected onto the first surface P1. The patterns of the body region 30 and the anode region 34 in Figure 14 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

[0127] In Figure 14, the region where the first bridging region 36 intersects with the body region 30 is also recognized as the body region 30. Similarly, the region where the second bridging region 38 intersects with the anode region 34 is also recognized as the anode region 34.

[0128] The occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. In other words, in a region of a predetermined size, the occupancy rate of the anode region 34 projected onto the first surface P1 is greater than the occupancy rate of the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0129] The occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times or less of the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1.

[0130] The above unit area is not particularly limited, as long as it is a size that allows for a comparison of the average occupancy rate of the body region 30 of the transistor region 101 and the average occupancy rate of the anode region 34 of the diode region 102. For example, the above unit area could be 30 μm × 30 μm = 900 μm. 2 That is the case.

[0131] Furthermore, the contact area per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. In other words, the contact resistance per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0132] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0133] Figures 15(a) and 15(b) are schematic top views of the semiconductor device of the first comparative example. Figure 15(a) is a diagram showing the arrangement of each region of the MOSFET of the first comparative example. Figure 15(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET of the first comparative example. Figures 15(a) and 15(b) correspond to Figures 1(a) and 1(b) of the first embodiment.

[0134] Figure 16 is a schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 16 is a cross-sectional view of the transistor region 101 in Figure 15(a). Figure 16 corresponds to Figure 2(a) of the first embodiment.

[0135] The MOSFET of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not have a diode region 102.

[0136] In the transistor region 101 of the MOSFET of the first comparative example, a MOSFET and an SBD are provided, similar to the MOSFET 100 of the first embodiment.

[0137] Figure 17 is an equivalent circuit diagram of the semiconductor device of the first comparative example. Between the source electrode 12 and the drain electrode 14, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes.

[0138] For example, consider a case where a MOSFET is used as a switching element connected to an inductive load. When the MOSFET is off, a load current caused by the inductive load may apply a voltage that makes the source electrode 12 positive relative to the drain electrode 14. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0139] The forward voltage (Vf) at which forward current begins to flow through an SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, forward current flows through the SBD first.

[0140] The forward voltage (Vf) of an SBD is, for example, 1.0V. The forward voltage (Vf) of a pn junction diode is, for example, 2.5V.

[0141] The SBD operates unipolar. Therefore, even when a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy.

[0142] Figures 18(a) and 18(b) are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 18(a) and 18(b) are schematic cross-sectional views of the first comparative example. Figures 18(a) and 18(b) correspond to Figure 16.

[0143] Figures 18(a) and 18(b) show the current flowing through the built-in diode of the MOSFET in the first comparative example. Figure 18(a) shows the state where forward current flows only through the SBD, and Figure 18(b) shows the state where forward current flows through both the SBD and the pn junction diode.

[0144] Specifically, Figure 18(a) shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 18(b) shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0145] In Figures 18(a) and 18(b), the dotted arrows indicate the current flowing through the SBD. In Figure 18(b), the solid arrows indicate the current flowing through the pn junction diode.

[0146] As shown in Figure 18(a), the current flowing through the SBD wraps around to the bottom of the body region 30. As a result, electrostatic potential wraps around to the drift region 28 opposite the bottom of the body region 30. This electrostatic potential wraps around to the drift region 28, which is the opposite of the bottom of the body region 30, and reduces the voltage applied between the body region 30 and the drift region 28.

[0147] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the body region 30. In other words, the forward voltage (Vf) of the pn junction diode of the MOSFET in the first comparative example can be made higher compared to the case where an SBD is not provided. As a result, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0148] The forward voltage (Vf) of the pn junction diode of the MOSFET in the first comparative example depends on the distance between two adjacent SBDs in the first direction. By reducing the distance between two adjacent SBDs in the first direction, the forward voltage (Vf) of the pn junction diode of the MOSFET in the first comparative example can be increased.

[0149] In some cases, a large surge current exceeding the steady state may be applied to the MOSFET instantaneously. The surge current flows from the source electrode 12 towards the drain electrode 14.

[0150] When a large surge current flows, a large surge voltage is applied, causing heat generation and damaging the MOSFET. The maximum allowable peak current value (I) of the surge current that can be allowed in a MOSFET. FSM This is called surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability.

[0151] When a large surge voltage is applied to the MOSFET of the first comparative example, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

[0152] When the voltage applied across the pn junction of a pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 18(b).

[0153] Figure 19 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 19 is a schematic cross-sectional view of the second comparative example. Figure 19 corresponds to Figure 16 of the first comparative example.

[0154] The MOSFET in the second comparative example differs from the MOSFET in the first comparative example in that its transistor region does not contain an SBD. The built-in diode in the MOSFET of the second comparative example is only a pn junction diode.

[0155] Figure 20 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 20 is a diagram showing the voltage-current characteristics of the built-in diodes of the MOSFET of the first comparative example and the MOSFET of the second comparative example.

[0156] As shown in Figure 20, in the second comparative example MOSFET, current flows through the pn junction diode when a voltage of Vf2 or higher is applied to the pn junction diode. On the other hand, in the first comparative example MOSFET, current flows through the SBD until the forward voltage Vf1 of the pn junction diode is applied. In the first comparative example MOSFET, current flows through the pn junction diode when a voltage of Vf1 or higher is applied to the pn junction diode.

[0157] The MOSFET in the first comparative example operates unipolar up to the forward voltage Vf1, so the slope of the current increase is smaller compared to the MOSFET in the second comparative example. Therefore, the maximum allowable peak current value I of the MOSFET in the second comparative example is FSM Compared to 2, the maximum allowable peak current value I of the MOSFET in the first comparative example FSM 1 becomes smaller. In other words, the surge current withstand capability of the MOSFET in the first comparative example becomes smaller than the surge current withstand capability of the MOSFET in the second comparative example.

[0158] Figure 21 is a schematic top view of the semiconductor device of the third comparative example. Figure 21 corresponds to Figure 11 of the first embodiment.

[0159] The MOSFET of the third comparative example differs from the MOSFET 100 of the first embodiment in that the silicon carbide layer 10 does not include the first p-type bridging region 36 (fourth silicon carbide region), the second p-type bridging region 38 (sixth silicon carbide region), and the third p-type bridging region 40 (seventh silicon carbide region).

[0160] The MOSFET of the third comparative example, like the MOSFET 100 of the first embodiment, includes diode regions 102 arranged alternately with transistor regions 101. The surge current withstand capability of the MOSFET of the third comparative example is improved by including the diode regions 102. This will be described in detail below.

[0161] Figures 22(a) and 22(b) are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 22(a) and 22(b) are schematic cross-sectional views of the MOSFET of the third comparative example. Figures 22(a) and 22(b) correspond to Figure 10(a) of the first embodiment. The MOSFET of the third comparative example has a structure similar to that shown in Figure 10(a) of the first embodiment.

[0162] Figures 22(a) and 22(b) show the current flowing through the built-in diode of the MOSFET of the third comparative example. Figure 22(a) shows the state where forward current flows only through the SBD, and Figure 22(b) shows the state where forward current flows through both the SBD and the pn junction diode.

[0163] Specifically, Figure 22(a) shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 22(b) shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0164] In Figures 22(a) and 22(b), the dotted arrows indicate the current flowing through the SBD. In Figure 22(b), the solid arrows indicate the current flowing through the pn junction diode.

[0165] In the diode region 102, the second distance d2 in the first direction between two adjacent second portions 28b with the anode region 34 in between is substantially equal to the first distance d1 in the first direction between two adjacent first portions 28a with the body region 30 in between in the transistor region 101. In other words, the diode region 102 has second portions 28b at the same spacing as the first portions 28a in the transistor region 101. To put it another way, the diode region 102 has SBD regions at the same spacing as the transistor region 101.

[0166] Therefore, as shown in Figure 22(a), in the diode region 102, the current flowing through the SBD flows around to the bottom of the anode region 34. As a result, it becomes less likely for the forward voltage (Vf) of the pn junction diode to be exceeded at the bottom of the anode region 34. The forward voltage (Vf) of the pn junction diode in the diode region 102 is increased by the presence of the SBD region.

[0167] When the voltage applied across the pn junction of a pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 22(b).

[0168] In the MOSFET of the third comparative example, for example, the occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0169] Furthermore, for example, the contact area per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. In other words, the contact resistance per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0170] Therefore, the current flowing through the pn junction diode in diode region 102 is greater than the current flowing through the pn junction diode in transistor region 101.

[0171] Furthermore, the large current flowing through the pn junction diode in diode region 102 causes carrier propagation and heat propagation to the adjacent transistor region 101. Consequently, conductivity modulation in the transistor region 101 adjacent to diode region 102 is promoted. Therefore, the current flowing through the pn junction diode in the transistor region 101 adjacent to diode region 102 becomes larger.

[0172] Figure 23 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 23 is a diagram showing the voltage-current characteristics of the built-in diodes of the MOSFET of the first comparative example, the MOSFET of the second comparative example, and the MOSFET of the third comparative example.

[0173] As shown in Figure 23, in the third comparative example MOSFET, current flows through the SBD until the forward voltage Vf3 of the pn junction diode is applied. In the third comparative example MOSFET, when a voltage equal to or greater than the forward voltage Vf3 of the pn junction diode is applied, current flows through the pn junction diode.

[0174] In the third comparative example, an SBD region is provided in the diode region 102 of the MOSFET at the same interval as in the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode of the MOSFET in the third comparative example is equivalent to the forward voltage Vf1 of the pn junction diode of the MOSFET in the first comparative example.

[0175] On the other hand, in the MOSFET of the third comparative example, the current after the forward voltage Vf3 of the pn junction diode is exceeded is greater than the current after the forward voltage Vf1 of the pn junction diode is exceeded in the MOSFET of the first comparative example. This is because the current flowing through the pn junction diode in diode region 102 and the pn junction diode in transistor region 101 adjacent to diode region 102 is greater than in the MOSFET of the first comparative example.

[0176] The current increases after the forward voltage Vf3 of the pn junction diode, which affects the maximum allowable peak current value I of the MOSFET in the third comparative example. FSM 3 is the maximum allowable peak current value I of the MOSFET in the first comparative example. FSM It becomes larger compared to 1. In other words, the surge current withstand capability of the MOSFET in the third comparative example is greater than that of the MOSFET in the first comparative example.

[0177] As described above, the MOSFET of the third comparative example has improved surge current withstand capability by including a diode region 102 provided between the transistor regions 101.

[0178] In the MOSFET 100 of the first embodiment, the silicon carbide layer 10 includes a first p-type bridging region 36 (fourth silicon carbide region), a second p-type bridging region 38 (sixth silicon carbide region), and a third p-type bridging region 40 (seventh silicon carbide region), thereby further improving the surge current withstand capability compared to the MOSFET of the third comparative example. This will be described in detail below.

[0179] For example, in the MOSFET of the third comparative example, there is a risk that the surge current flowing through the MOSFET will vary within the chip. This variation in surge current within the chip is thought to be due to variations in the start of operation and the rise of the forward current after the start of operation of the pn junction diodes provided in the diode region 102 and transistor region 101.

[0180] If surge currents vary within the chip, for example, the amount of heat generated locally can increase. Consequently, MOSFETs may be destroyed locally, resulting in a decrease in their surge current withstand capability.

[0181] In the MOSFET 100 of the first embodiment, a p-type first bridging region 36 (fourth silicon carbide region), a p-type second bridging region 38 (sixth silicon carbide region), and a p-type third bridging region 40 (seventh silicon carbide region) are provided, so that a plurality of p-type body regions 30 and a plurality of p-type anode regions 34 extending in the second direction are connected by p-type regions in the first direction. The first bridging region 36, the second bridging region 38, and the third bridging region 40 connecting the body regions 30 and anode regions 34 promote the movement of holes in the first direction, thereby making it possible to equalize the start of operation and the rise of the forward current after the start of operation of the pn junction diodes provided in the diode region 102 and transistor region 101 within the chip.

[0182] According to the MOSFET 100 of the first embodiment, variations in surge current flowing through the MOSFET within the chip can be suppressed. Therefore, according to the MOSFET 100 of the first embodiment, the surge current withstand capability is improved.

[0183] The distance between two adjacent first bridging regions 36 in the second direction (dx in Figure 3) is preferably smaller than the width of the transistor region 101 in the first direction (w1 in Figure 1(a)). By making the distance dx in the second direction smaller than the width w1 of the transistor region 101 in the first direction, the start of operation of the pn junction diode provided in the transistor region 101 and the rise of the forward current after the start of operation can be made even more uniform within the chip.

[0184] The width of the first bridging region 36 in the second direction (wx in Figure 3) is preferably smaller than the first distance in the first direction between two adjacent first portions 28a (d1 in Figures 2(a) and 3). By making the width wx of the first bridging region 36 in the second direction smaller than the first distance d1 between two adjacent first portions 28a, the decrease in the forward voltage (Vf) of the pn junction diode of the transistor region 101 can be suppressed.

[0185] The width of the second bridging region 38 in the second direction (wy in Figure 7) is preferably smaller than, for example, the width of the anode region 34 in the first direction (wb in Figure 7). By making the width of the second bridging region 38 in the second direction (wy in Figure 7) smaller than, for example, the width of the anode region 34 in the first direction (wb in Figure 7), the decrease in the forward voltage (Vf) of the pn junction diode in the diode region 102 can be suppressed.

[0186] From the viewpoint of suppressing a decrease in the forward voltage (Vf) of the pn junction diode in the diode region 102, it is preferable that the width of the second bridging region 38 in the second direction (wy in Figure 7) is half or less of the width of the anode region 34 in the first direction (wb in Figure 7). From the viewpoint of suppressing a decrease in the forward voltage (Vf) of the pn junction diode in the diode region 102, it is preferable that the width of the second bridging region 38 in the second direction (wy in Figure 7) is 10 μm or less.

[0187] The width of the second bridging region 38 in the second direction (wy in Figure 7) is preferably smaller than the second distance in the first direction between two adjacent second portions 28b (d2 in Figures 6(a) and 7). By making the width wy of the second bridging region 38 in the second direction smaller than the second distance d2 between two adjacent second portions 28b in the first direction, the decrease in the forward voltage (Vf) of the pn junction diode in the diode region 102 can be suppressed.

[0188] From the viewpoint of increasing the on-current of MOSFET 100, it is preferable that the width of the transistor region 101 in the first direction (w1 in Figure 1(a)) is larger than the width of the diode region 102 in the first direction (w2 in Figure 1(a)).

[0189] (First variation) The semiconductor device of the first modified example differs from the semiconductor device of the first embodiment in that the depth of the fourth silicon carbide region is deeper than the depth of the second silicon carbide region, and the depth of the sixth silicon carbide region is deeper than the depth of the fifth silicon carbide region.

[0190] Figures 24(a), 24(b), 25(a), and 25(b) are schematic cross-sectional views of a semiconductor device of a first modified example of the first embodiment. Figures 24(a) and 24(b) correspond to Figures 2(a) and 2(b) of the first embodiment. Figures 25(a) and 25(b) correspond to Figures 6(a) and 6(b) of the first embodiment.

[0191] As shown in Figures 24(a) and 24(b), in the first modified MOSFET, the depth of the first p-type bridging region 36 (fourth silicon carbide region) is greater than the depth of the p-type body region 30 (second silicon carbide region). Also, as shown in Figures 25(a) and 25(b), the depth of the second p-type bridging region 38 (sixth silicon carbide region) is greater than the depth of the p-type anode region 34 (fifth silicon carbide region).

[0192] The increased depth of the first p-type bridging region 36 and the second p-type bridging region 38 further promotes the movement of holes in the first direction. Therefore, according to the first modified MOSFET, the surge current withstand capability is further improved.

[0193] (Second variation) The semiconductor device of the second modified example differs from the semiconductor device of the first embodiment in that the p-type impurity concentration in the fourth silicon carbide region is higher than that in the second silicon carbide region, and the p-type impurity concentration in the sixth silicon carbide region is higher than that in the fifth silicon carbide region.

[0194] In the second modified MOSFET, the p-type impurity concentration in the first p-type bridging region 36 (fourth silicon carbide region) is higher than the p-type impurity concentration in the p-type body region 30 (second silicon carbide region). Also, the p-type impurity concentration in the second p-type bridging region 38 (sixth silicon carbide region) is higher than the p-type impurity concentration in the p-type anode region 34 (fifth silicon carbide region).

[0195] The high p-type impurity concentration in the first p-type bridging region 36 and the second p-type bridging region 38 further promotes hole movement in the first direction. Therefore, the surge current withstand capability is further improved according to the second modified MOSFET.

[0196] As described above, according to the first embodiment and its modifications, a semiconductor device with improved surge current withstand capability can be provided.

[0197] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the fourth silicon carbide region does not intersect with the second silicon carbide region, and the sixth silicon carbide region does not intersect with the fifth silicon carbide region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0198] The semiconductor device of the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide, similar to the semiconductor device of the first embodiment.

[0199] Figures 26(a) and 26(b) are schematic cross-sectional views of a part of the semiconductor device of the second embodiment. Figure 27 is a schematic top view of a part of the semiconductor device of the second embodiment. Figure 26(a) is the AA' cross-section of Figure 27. Figure 26(b) is the BB' cross-section of Figure 27.

[0200] Figures 28(a) and 28(b) are schematic cross-sectional views of a part of the semiconductor device of the second embodiment. Figure 29 is a schematic top view of a part of the semiconductor device of the second embodiment. Figure 28(a) is the CC' section of Figure 29. Figure 28(b) is the DD' section of Figure 29.

[0201] Figures 30(a) and 30(b) are schematic cross-sectional views of a part of the semiconductor device of the second embodiment. Figure 31 is a schematic top view of a part of the semiconductor device of the second embodiment. Figure 30(a) is the EE' section of Figure 31. Figure 30(b) is the FF' section of Figure 31.

[0202] The MOSFET200 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and gate wiring 24.

[0203] Within the silicon carbide layer 10, n + Drain region 26 of type n - Type drift region 28 (first silicon carbide region), p-type body region 30 (second silicon carbide region), n + The p-type includes a source region 32 (third silicon carbide region), a p-type anode region 34 (fifth silicon carbide region), a p-type first bridging region 36 (fourth silicon carbide region), a p-type second bridging region 38 (sixth silicon carbide region), and a p-type third bridging region 40 (seventh silicon carbide region).

[0204] The drift region 28 includes a plurality of first parts 28a and a plurality of second parts 28b.

[0205] Figures 26(a), 26(b), and 27 show the transistor region 101.

[0206] As shown in Figures 26(a), 26(b), and 27, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. Within the silicon carbide layer 10 of the transistor region 101, n + Drain region 26 of type n - A drift region 28 of type p (first silicon carbide region), multiple p-type body regions 30 (second silicon carbide region), multiple n +It includes a source region 32 of type p (third silicon carbide region) and multiple first bridging regions 36 of type p (fourth silicon carbide region).

[0207] Note that Figure 27 shows only the patterns of the drift region 28, the body region 30, the first bridging region 36, and the gate electrode 18.

[0208] The first p-shaped bridging region 36 is provided between the drift region 28 and the first surface P1. The first bridging region 36 is repeatedly arranged in the second direction.

[0209] The first bridging region 36 connects two adjacent body regions 30 in the first direction. The first bridging regions 36 are, for example, repeatedly arranged in the first direction. Two adjacent first bridging regions 36 in the first direction have a body region 30 in between them.

[0210] The first bridging region 36 divides the first portion 28a that extends in the second direction. The first bridging region 36 connects two adjacent body regions 30, separated by an n-type first portion 28a, with a p-type silicon carbide region.

[0211] The distance between two adjacent first bridging regions 36 in the second direction is, for example, smaller than the width of the transistor region 101 in the first direction. The distance between two adjacent first bridging regions 36 in the second direction is, for example, between 10 μm and 200 μm.

[0212] The width of the first crosslinking region 36 in the second direction is, for example, smaller than the distance between two adjacent first portions 28a. The distance between two adjacent first portions 28a is, for example, 3 μm or more and 30 μm or less. The width of the first crosslinking region 36 in the second direction is, for example, 1 μm or more and 10 μm or less.

[0213] The first crosslinking region 36 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first crosslinking region 36 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm-3 The following applies: The p-type impurity concentration in the first crosslinking region 36 is substantially the same as, for example, the p-type impurity concentration in the body region 30.

[0214] The depth of the first crosslinking region 36 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the first crosslinking region 36 is, for example, substantially the same as the depth of the body region 30.

[0215] Although Figure 27 illustrates a case where two first bridging regions 36 are arranged in the second direction, there may be three or more first bridging regions 36.

[0216] Figures 28(a), 28(b), and 29 show the diode region 102.

[0217] As shown in Figures 28(a), 28(b), and 29, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). Within the silicon carbide layer 10 of the diode region 102, n + Drain region 26 of type n - It includes a type drift region 28 (first silicon carbide region), multiple p-type anode regions 34 (fifth silicon carbide region), and a second p-type bridging region 38 (sixth silicon carbide region).

[0218] Note that Figure 29 shows only the patterns of the drift region 28, the anode region 34, and the second bridging region 38.

[0219] The drift region 28 includes a plurality of second portions 28b. The second portions 28b are tangent to the first surface P1.

[0220] The p-shaped second bridging region 38 is provided between the drift region 28 and the first surface P1. The second bridging region 38 is repeatedly arranged in the second direction.

[0221] The second bridging region 38 connects two adjacent anode regions 34 in the first direction. The second bridging regions 38 are, for example, repeatedly arranged in the first direction. Two adjacent second bridging regions 38 in the first direction have an anode region 34 in between them.

[0222] The second bridging region 38 divides the second portion 28b that extends in the second direction. The second bridging region 38 connects two adjacent anode regions 34, separated by an n-type second portion 28b, with a p-type silicon carbide region.

[0223] The distance between two adjacent second bridging regions 38 in the second direction is, for example, smaller than the width of the transistor region 101 in the first direction. The distance between two adjacent second bridging regions 38 in the second direction is, for example, 10 μm or more and 200 μm or less.

[0224] The width of the second crosslinking region 38 in the second direction is, for example, smaller than the distance between two adjacent second portions 28b. The distance between two adjacent second portions 28b is, for example, 3 μm or more and 30 μm or less. The width of the second crosslinking region 38 in the second direction is, for example, 1 μm or more and 10 μm or less.

[0225] The distance between two adjacent second parts 28b is substantially equal to, for example, the distance between two adjacent first parts 28a.

[0226] The second crosslinking region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the second crosslinking region 38 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm -3 The following applies: The p-type impurity concentration in the second cross-linking region 38 is substantially the same as, for example, the p-type impurity concentration in the anode region 34. The p-type impurity concentration in the second cross-linking region 38 is substantially the same as, for example, the p-type impurity concentration in the first cross-linking region 36.

[0227] The depth of the second crosslinking region 38 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the second crosslinking region 38 is, for example, substantially the same as the depth of the anode region 34. The depth of the second crosslinking region 38 is, for example, substantially the same as the depth of the first crosslinking region 36.

[0228] Although Figure 29 illustrates the case where two second bridging regions 38 are arranged in the second direction, there may be three or more second bridging regions 38.

[0229] Figures 30(a), 30(b), and 31 show the boundary between the transistor region 101 and the diode region 102.

[0230] As shown in Figures 30(b) and 31, the silicon carbide layer 10 at the boundary between the transistor region 101 and the diode region 102 includes a p-type third bridging region 40 (seventh silicon carbide region).

[0231] The p-shaped third bridging region 40 is provided between the drift region 28 and the first surface P1. The third bridging region 40 is repeatedly arranged in the second direction.

[0232] The third bridging region 40 connects the adjacent body region 30 and anode region 34 in the first direction.

[0233] The third bridging region 40 divides the drift region 28 that extends in the second direction on the first surface. The third bridging region 40 connects adjacent body regions 30 and anode region 34, which are separated by an n-type drift region 28, with a p-type silicon carbide region.

[0234] The first bridging region 36, the second bridging region 38, and the third bridging region 40 are arranged side by side in a first direction, for example.

[0235] The distance between two adjacent third bridging regions 40 in the second direction is, for example, smaller than the width of the transistor region 101 in the first direction. The distance between two adjacent third bridging regions 40 in the second direction is, for example, 10 μm or more and 200 μm or less.

[0236] The width of the third crosslinking region 40 in the second direction is, for example, smaller than the distance between two adjacent second portions 28b. The distance between two adjacent second portions 28b is, for example, 3 μm or more and 30 μm or less. The width of the third crosslinking region 40 in the second direction is, for example, 1 μm or more and 10 μm or less.

[0237] The third crosslinking region 40 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the third crosslinking region 40 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 21 cm -3 The following applies: The p-type impurity concentration in the third crosslinking region 40 is substantially the same as, for example, the p-type impurity concentration in the body region 30 and the anode region 34. The p-type impurity concentration in the third crosslinking region 40 is substantially the same as, for example, the p-type impurity concentration in the first crosslinking region 36. The p-type impurity concentration in the third crosslinking region 40 is substantially the same as, for example, the p-type impurity concentration in the second crosslinking region 38.

[0238] The depth of the third crosslinking region 40 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the third crosslinking region 40 is, for example, substantially the same as the depth of the body region 30 and the anode region 34. The depth of the third crosslinking region 40 is, for example, substantially the same as the depth of the first crosslinking region 36. The depth of the third crosslinking region 40 is, for example, substantially the same as the depth of the second crosslinking region 38.

[0239] Although Figure 31 illustrates a case where two third bridging regions 40 are arranged in the second direction, there may be three or more third bridging regions 40.

[0240] The occupation rate per unit area of the anode region 34 projected onto the first surface P1 on the first surface P1 is larger than the occupation rate per unit area of the body region 30 projected onto the first surface P1 on the first surface P1. In other words, in a region of a predetermined size, the occupation rate of the anode region 34 projected onto the first surface P1 on the first surface P1 is larger than the occupation rate of the body region 30 projected onto the first surface P1 on the first surface P1. That is, the occupation ratio of the pn junction diode in the diode region 102 is larger than the occupation ratio of the pn junction diode in the transistor region 101.

[0241] The occupation rate per unit area of the anode region 34 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times or less the occupation rate per unit area of the body region 30 projected onto the first surface P1.

[0242] The unit area is not particularly limited as long as it has a size that allows comparison between the average occupation rate of the body region 30 in the transistor region 101 and the average occupation rate of the anode region 34 in the diode region 102. The unit area is, for example, 30 μm × 30 μm = 900 μm 2 .

[0243] Further, the contact area per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0244] In the MOSFET 200 according to the second embodiment, similar to the MOSFET 100 according to the first embodiment, by including a p-type first bridge region 36 (fourth silicon carbide region), a p-type second bridge region 38 (sixth silicon carbide region), and a p-type third bridge region 40 (seventh silicon carbide region), the p-type body region 30 and the p-type anode region 34 extending in the second direction are connected by the p-type regions in the first direction. The first bridge region 36, the second bridge region 38, and the third bridge region 40 that connect the body region 30 and the anode region 34 promote the movement of holes in the first direction, whereby the start of operation of the pn junction diodes provided in the diode region 102 and the transistor region 101, and the rise of the forward current after the start of operation can be made uniform within the chip.

[0245] According to the MOSFET 200 of the second embodiment, variation in surge current flowing through the MOSFET within the chip can be suppressed. Therefore, according to the MOSFET 200 of the second embodiment, the surge current tolerance is improved.

[0246] Note that in the MOSFET 200 of the second embodiment, the depth of the p-type first bridge region 36 (fourth silicon carbide region) can be made greater than the depth of the p-type body region 30 (second silicon carbide region). Further, the depth of the p-type second bridge region 38 (sixth silicon carbide region) can be made greater than the depth of the p-type anode region 34 (fifth silicon carbide region).

[0247] Further, in the MOSFET 200 of the second embodiment, the p-type impurity concentration of the p-type first bridge region 36 (fourth silicon carbide region) can be made higher than the p-type impurity concentration of the p-type body region 30 (second silicon carbide region). Further, the p-type impurity concentration of the p-type second bridge region 38 (sixth silicon carbide region) can be made higher than the p-type impurity concentration of the p-type anode region 34 (fifth silicon carbide region).

[0248] Furthermore, in the MOSFET 200 of the second embodiment, the plurality of first bridging regions 36 do not necessarily have to be aligned along the first direction. Similarly, the plurality of second bridging regions 38 do not necessarily have to be aligned along the first direction. Also, the first bridging region 36, the second bridging region 38, and the third bridging region 40 do not necessarily have to be arranged in line along the first direction.

[0249] As described above, according to the second embodiment, a semiconductor device with improved surge current withstand capability can be provided.

[0250] In the first and second embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0251] In the first and second embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Furthermore, while nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, arsenic (As), antimony (Sb), etc., can also be applied.

[0252] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0253] 10. Silicon carbide layer 12 Source electrode (first electrode) 14. Drain electrode (second electrode) 16 Gate insulating layer 18 Guard gate 28. Drift region (first silicon carbide region) 28a Part 1 28b Second part 30 Body region (second silicon carbide region) 32. Source region (third silicon carbide region) 34. Anode region (5th silicon carbide region) 36. First bridging region (fourth silicon carbide region) 38. Second bridging region (sixth silicon carbide region) 40. Third bridging region (seventh silicon carbide region) 100 MOSFETs (Semiconductor Devices) 101 Transistor Region 102 Diode region P1 First side P2 Second side

Claims

1. It comprises a plurality of transistor regions and a plurality of diode regions arranged alternately in a first direction, The aforementioned transistor region is A silicon carbide layer having a first surface and a second surface facing the first surface, An n-type first silicon carbide region having a plurality of first portions that are in contact with the first surface, extend in a second direction perpendicular to the first direction, and are arranged in the first direction, A plurality of p-shaped second silicon carbide regions are provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction, An n-type third silicon carbide region is provided between the second silicon carbide region and the first surface, A plurality of p-shaped fourth silicon carbide regions are provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting two adjacent second silicon carbide regions, A silicon carbide layer containing, A first electrode in contact with the first portion, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region, A second electrode in contact with the second surface, A plurality of gate electrodes facing the second silicon carbide region, extending in the second direction and arranged in the first direction, A gate insulating layer is provided between the gate electrode and the second silicon carbide region, Includes, The diode region is The first n-type silicon carbide region having a plurality of second portions that are in contact with the first surface and extend in the second direction, A plurality of p-shaped fifth silicon carbide regions are provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction, A plurality of p-shaped sixth silicon carbide regions are provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting two adjacent fifth silicon carbide regions, The silicon carbide layer containing, The first electrode in contact with the second portion, the fifth silicon carbide region, and the sixth silicon carbide region, The above second electrode and, The semiconductor device further includes a plurality of p-type seventh silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting adjacent second silicon carbide regions and fifth silicon carbide regions.

2. The semiconductor device according to claim 1, wherein the occupancy rate per unit area of ​​the fifth silicon carbide region projected onto the first surface is greater than the occupancy rate per unit area of ​​the second silicon carbide region projected onto the first surface.

3. The semiconductor device according to claim 2, wherein the contact area per unit area between the first electrode and the fifth silicon carbide region is greater than the contact area per unit area between the first electrode and the second silicon carbide region.

4. The semiconductor device according to claim 1, wherein the width of the sixth silicon carbide region in the second direction is smaller than the width of the fifth silicon carbide region in the first direction.

5. The semiconductor device according to claim 1, wherein the distance between two adjacent fourth silicon carbide regions in the second direction is smaller than the width of the transistor region in the first direction.

6. The fourth silicon carbide region extends in the first direction, and the fourth silicon carbide region intersects with the second silicon carbide region. The sixth silicon carbide region extends in the first direction, and the sixth silicon carbide region intersects with the fifth silicon carbide region. The semiconductor device according to claim 1, wherein the fourth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region are continuous in the first direction.

7. The depth of the fourth silicon carbide region is greater than the depth of the second silicon carbide region. The semiconductor device according to claim 1, wherein the depth of the sixth silicon carbide region is greater than the depth of the fifth silicon carbide region.

8. The p-type impurity concentration in the fourth silicon carbide region is higher than the p-type impurity concentration in the second silicon carbide region. The semiconductor device according to claim 1, wherein the p-type impurity concentration in the sixth silicon carbide region is higher than the p-type impurity concentration in the fifth silicon carbide region.

9. The semiconductor device according to claim 1, wherein the second distance in the first direction between two adjacent second portions with the fifth silicon carbide region in between is equal to the first distance in the first direction between two adjacent first portions with the second silicon carbide region in between.

10. The semiconductor device according to claim 1, wherein the width of the transistor region in the first direction is greater than the width of the diode region in the first direction.

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