Process for generating physical implementation guidance during network-on-chip synthesis

Abstract

To provide a system and method for augmenting a synthesized network-on-chip (NoC) with data that guides the physical implementation of a NoC topology to match topology synthesis results and reducing timing violations in a final physical design.SOLUTION: A NoC, during the physical implementation of a synthesized NoC, generates physical implementation guidance, inserts a link as a pipeline placeholder, and assigns a minimal set of created module regions to a particular link in a topology. Each route has a new link and a corresponding module region inserted into a physical path.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] Technical Field The present technology resides in the field of electronic system design, and more specifically relates to physical implementation guidance during generation of a network-on-chip (NoC).

Background Art

[0002] Background Multiprocessor systems are implemented in system-on-chip (SoC) that communicate via NoC. A SoC includes instances of initiator intellectual property (IP) and target IP. Transactions in the form of packets are sent from an initiator to one or more targets using industry standard protocols. An initiator connected to the NoC sends a request transaction to a target using an address to select the target. The NoC decodes the address and transports the request from the initiator to the target. The target handles the transaction and sends a response transaction, which is transported back to the initiator by the NoC.

[0003] Given a given set of performance requirements, such as connectivity and latency between source and destination, frequencies of various elements, maximum area available for NoC logic and its associated routing (wiring), minimum throughput between source and destination, power consumption requirements for the NoC, and the placement of elements attached to the NoC on the floor plan, creating an optimal NoC that satisfies all requirements with the minimum amount of logic and wire is a complex task. This is typically the job of a chip engineer or chip designer to create this optimal NoC, and it is a difficult and time-consuming task. In addition to being a difficult challenge, the NoC design is revised whenever one of the requirements changes, such as a change in the chip floor plan, the addition or removal of IP components, or a change in expected performance. As a result, this task needs to be frequently re-executed throughout the chip design time. This process is time-consuming and leads to production delays. Therefore, what is needed is a system and method for efficiently generating a NoC from a set of constraints and inputs enumerated as requirements. The system should produce a NoC in which all its elements are placed on the chip's floor plan.

[0004] A current technical challenge in creating NoCs is the lack of physical floor plan information. For example, if two components are logically plugged into a network in an adjacent configuration, or are logically adjacent to each other, they might communicate through a single switch. However, in a physical floor plan, the two components may be far apart. As a result, if an NoC is implemented on the actual floor plan, it can be difficult, and / or even impossible, to meet timing requirements. Timing requirements are passed to downstream tools. Timing requirements specify parameters, for example, between component A and component B. For example, the timing between component A and component B must be within a certain range. If the measured value from component A to component B exceeds the range of the timing requirement, it is essentially impossible to meet the time requirement, as it is now known that attempting to meet the time requirement will overwork downstream tools, causing them to work longer than normal. Therefore, it would be more desirable to create a NoC that can be successfully implemented by downstream tools while satisfying all timing, power, area, and congestion design constraints. [Overview of the project] [Problems that the invention aims to solve]

[0005] overview According to various embodiments and aspects of the present invention, a process for generating implementation guidance during the synthesis of a NoC is described. A system and method for producing or generating a NoC having all its elements is disclosed, using constraints and steps having inputs. The elements of the NoC are arranged on a floor plan of the chip. The advantage of the present invention is the simplification of the design process and the work of the chip engineer or designer. Furthermore, the technical solution provides a technical effect that, by having instructions for the physical floor plan, makes it easier to create the NoC, to the extent that automating mechanisms such as adding distance pipe components, though not limited to the present technology, becomes easier. [Means for solving the problem]

[0006] In one embodiment, creating a synthesized NoC is configured to provide floorplan instructions so that the NoC is augmented with information to ensure that it meets the performance criteria supplied in the specification for the NoC when implemented in downstream tools, and so that timing estimations can be implemented to determine how far a first component is from a second component. The timing estimations may provide data indicating, for example, that the first component of the NoC is too far from the second component of the NoC, exceeding the timing requirement. As a result of exceeding the timing requirement, at least one distance pipeline or link may be inserted into the floorplan. Adding a distance pipe to the floorplan solves many of the problems associated with two components of the NoC exceeding the timing requirement. However, adding a distance pipe to the NoC floorplan contributes to added latency by adding clock cycles for data to pass through the distance pipe. It is more desirable to add distance pipes at the same time and create a NoC topology that requires as few distance pipes as possible. As a result, overall performance, bandwidth, and latency can be optimized considering the constraints of the floorplan. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a logical diagram of NoC that includes various elements that generate NoC. [Figure 1B] This diagram shows the NoC (Network Center) elements placed on a network floor plan. [Figure 2A] This figure shows a method for generating a NoC description based on a set of constraints according to various aspects and embodiments of the present invention. [Figure 2B] This is a block diagram of a NoC synthesis tool according to various aspects and embodiments of the present invention. [Figure 3] This is a graphic diagram of the chip floor plan having the location of the occluded area and interface with the NoC according to various aspects and embodiments of the present invention. [Figure 4] This figure shows a connectivity table of NoC according to various aspects and embodiments of the present invention. [Figure 5] This figure shows a scenario table having read and write transaction throughput definitions according to various aspects and embodiments of the present invention. [Figure 6] This figure shows the creation of a network having three traffic classes according to various aspects and embodiments of the present invention. [Figure 7] This figure shows the network decomposition of Figure 6 using mergers and splitters according to various aspects and embodiments of the present invention. [Figure 8] This figure shows a roadmap in the floor plan of one initiator in the network of Figure 6 according to various aspects and embodiments of the present invention. [Figure 9] This figure shows a roadmap in the floor plan of one target of the network in Figure 6 according to various aspects and embodiments of the present invention. [Figure 10] This figure shows the decomposition of the main node splitter into a cascade of physically distributed splitters according to the roadmap of Figure 8, according to various aspects and embodiments of the present invention. [Figure 11]This figure shows the decomposition of a main node merger into a cascade of physically distributed mergers according to the roadmap of Figure 9, according to various aspects and embodiments of the present invention. [Figure 12] This figure shows an example of two adjacently merged nodes according to various aspects and embodiments of the present invention. [Figure 13] This flowchart shows a method for creating a synthetic NoC using data that provides potential guidance for physical implementation. [Figure 14] This flowchart shows an alternative method for creating a synthetic NoC using data that provides potential guidance for physical implementation. [Figure 15A] Figure 14 is a flowchart of the method for synthesizing chip topologies according to various embodiments of the present invention. [Figure 15B] Figure 15A is an illustrative diagram of the process diagram for synthesizing the chip topology according to various embodiments of the present invention. [Modes for carrying out the invention]

[0008] Detailed explanation The following describes various examples of the Art illustrating various aspects and embodiments of the Invention. In general, the examples can be used in any combination of the described aspects. All descriptions in this specification listing principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both their structural and functional equivalents. Furthermore, such equivalents are intended to include both currently known equivalents and equivalents to be developed in the future, i.e., any developed elements that perform the same function regardless of their structure.

[0009] Where used herein, the singular forms “a,” “an,” and “the” refer to multiple objects unless the context clearly indicates otherwise. Throughout this specification, references to “one aspect,” “aspect,” “specific aspect,” “various aspects,” or similar phrases mean that specific aspects, features, structures, or characteristics described in relation to any embodiment are included in at least one embodiment of the present invention.

[0010] Throughout this specification, occurrences of phrases such as “in one embodiment,” “in at least one embodiment,” “in an embodiment,” “in a particular embodiment,” and similar expressions may all, though not necessarily, refer to the same embodiment or a similar embodiment. Furthermore, the aspects and embodiments of the invention described herein are merely illustrative and should not be construed as limiting the scope or spirit of the invention as understood by those skilled in the art. The disclosed invention may be effectively created or used in any embodiment, including any novel aspects described herein. All descriptions herein enumerating the principles, aspects, and embodiments of the invention are intended to encompass both their structural and functional equivalents. Such equivalents are intended to include both currently known equivalents and equivalents to be developed in the future.

[0011] As used herein, a transaction can be a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0012] As used herein, a node is defined as a distribution point or communication endpoint capable of creating, receiving, and / or transmitting information via a communication path or channel. A node may refer to any one of a switch, a splitter, a merger, a buffer, and an adapter. As used herein, splitters and mergers are switches, but not all switches are splitters or mergers. As used herein, in accordance with various aspects and embodiments of the present invention, the term "splitter" refers to a switch having a single inlet port and a plurality of outlet ports. As used herein, in accordance with various aspects and embodiments of the present invention, the term "merger" refers to a switch having a single outlet port and a plurality of inlet ports.

[0013] Referring here to Figure 1A, NoC100 according to various aspects and embodiments of the present invention is shown. NoC100 is an example of a network. According to various aspects and embodiments of the present invention, the network includes a set of nodes and a set of edges, each of which has a model that performs and implements transformations on the network and can be used in a synthesis center to converge to the best solution that fits the given requirements. NoC100 includes nodes and endpoints and uses assembled basic network functions such as network interface units (NIUs, also called AIUs or agent interface units) 102, 104, 106, 108, 110, 112, 130, 132, and 134, node / switches 114, 116, 118, 120, and 122, adapters such as adapter 126, and buffers such as buffer 124. The NoC basic network functions use an internal transport protocol specific to NoC100 to communicate with each other, typically based on packet transmission. The NIU translates the protocol used by the attached SoC unit (not shown) to the transport protocol used within the NoC100. The switch is configured to route the flow of traffic between source and destination. Buffer 124 is used to store packets to insert pipeline elements over long distances or to handle rate adaptation between a high-speed transmitter and a low-speed receiver, or vice versa. Adapter 126 handles various conversions between data width, clock, and power domains. The transport protocol may include, but is not limited to, a proprietary protocol and / or an industry-standard protocol.

[0014] Referring now to FIG. 1B, there is shown a NoC 150 having various elements such as NIUs, switches, and occlusion areas in a floorplan. The NoC 150 includes various connectivity elements via various switches. According to one aspect of the present invention, a set of constraints is used as an input to a tool, which will be described in more detail below. According to some aspects of the present invention, the tool executes a set of sub-steps to produce a description (synthesis) of the resulting NoC, such as NoC 150, using its configured elements and the position of each element on the floorplan. The generated description is used to actually implement the NoC hardware, using the physical information created to provide guidance to the backend implementation flow. It is within the scope of the present invention that a NoC component is an abstraction of what becomes a much larger number of semiconductor gates in a SoC. It is also an important aspect that the components have locations such as the centroid of individual gates. Individual gates may comprise components that are placed and routed by downstream tools.

[0015] Referring now to FIG. 2A, in accordance with some aspects of the present invention, a set of constraints (210, 212, 214, 216, and scenarios) is provided to a synthesis tool 220. In accordance with some embodiments and aspects of the present invention, the performance and functionality of tool 220 may include third-party ASIC implementation tools such as logic synthesis, backend tool placement and routing. A designer and / or user constructs the set of constraints that are provided to tool 220. The constraints are captured in a machine-readable format, such as a computer file using a defined format to capture information that is understood and processed by the tool. According to one aspect of the invention, the format is XML. According to another aspect of the invention, the format is JSON. The scope of the present invention is not limited by the particular format used.

[0016] Referring to Figure 2B, the tool reads a file containing a description of constraints and executes the synthesis process. According to some aspects of the present invention, the synthesis process is subdivided into multiple steps. The sequencer 250 is responsible for executing each step of the process. According to some aspects of the present invention, the sequencer 250 of the tool 220 executes a set of steps in light of constraints indicated by the user / designer. The scope of the present invention is not limited by the number and type of steps that the sequencer 250 can call and execute.

[0017] Referring again to Figure 2A along with Figure 2B, according to various aspects of the present invention, the network designer provides and defines a set of constraints such as constraints 210, 212, 214, and 216. The PLC 250 receives various inputs, including: input 251, which includes a global integrated roadmap with connectivity between initiators and targets, including roadmap creation and information between each initiator and target; input 252, which includes traffic classification and main switch creation; input 254, which includes main switch decomposition into mergers and splitters; input 258, which includes information on the physical distribution of splitters and mergers in the roadmap; input 259, which includes information on edge clustering; and input 260, which includes information on performance-aware node clustering. According to one aspect of the present invention, the PLC 250 also receives input 262, which includes information on optimization and network reconstruction. According to one aspect of the present invention, the PLC 250 receives input 264, which includes information on routing and legalization. According to various aspects and embodiments of the present invention, the PLC 250 uses all inputs 251-264 to generate the network. According to various aspects and embodiments of the present invention, the sequencer 250 uses a combination of inputs 251 to 264 to generate a network.

[0018] According to various aspects of the present invention, input 251 includes an input relating to a global integration roadmap. The global integration roadmap includes an integration model that captures a global physical view of connectivity between initiators and targets, as well as connectivity between available spaces in a floor plan. The global integration roadmap is modeled by a graph of physical nodes and standard segments used to position nodes (splitters, mergers, switches, adapters) in the network being built. The global integration roadmap is used to speed up computation. According to various aspects of the present invention, the global integration roadmap is persistent, meaning that it is data that the system exports and reuses in incremental synthesis and subsequent executions.

[0019] According to some aspects of the present invention, input 259 includes information regarding edge clustering. Edge clustering aims to minimize resources and improve performance targets through appropriate algorithms and techniques. According to some aspects of the present invention, edge clustering is applied in conjunction with node clustering of input 260. Edge clustering and node clustering can be used in combination by mixing, by applying concurrently, or by applying sequentially. The advantages and goals are to expand the range of synthesis and span a larger solution space for the network.

[0020] According to various aspects of the present invention, input 262 includes information relating to restructuring. Restructuring includes various transformations and capabilities. According to some aspects of the present invention, transformation is logical in that there is a change in the structure of the network. According to some aspects of the present invention, transformation is physical because there is a physical change to the network, such as moving a node to a new location. Other examples of restructuring include subdividing a node into smaller nodes, changing the parent between nodes, overlapping network subparts to avoid deadlocks and address congestion, and physically rerouting links to avoid congested areas or to satisfy timing constraints.

[0021] According to various aspects of the present invention, other constraints include extensions of the clock domain, and a power domain 212 may also be provided. Domain 212 includes an area of ​​the chip where logic belonging to a particular domain can be located.

[0022] Referring here to Figure 3, according to various aspects of the present invention, a floor plan 300 of a chip on which a NoC is implemented is shown, having various initiator and target interface locations. The physical constraints 210 provide physical information relating to the design, which includes the size of the chip on which the NoC is implemented, various occupying areas on the floor plan which are rectangles representing areas of the chip where NoC logic cannot exist or be located, free spaces which are areas of the chip where NoC logic can exist and are defined by areas not covered by occupies, and the locations of interfaces between the SoC unit and the NoC, which are initiator and target interfaces such as NIUs. The occupies may be represented at the top level of the floor plan or may be included in the hierarchical representation of physical / logical blocks in the design and then used at the top level in the same manner.

[0023] According to various aspects of the present invention, the functionality of a logic library used to implement NoC is provided. This information includes the size of the reference logic gate and the time it takes for the signal to cover a distance of 1 mm.

[0024] Referring again to Figure 2A, according to various aspects of the present invention, the SoC includes multiple clock domains and multiple power domains. A clock domain is defined by all logic supplied by a given clock input. The clock input is characterized by its most important parameter, the clock frequency. A power domain is defined by all logic that receives power from the same power source. According to various aspects of the present invention, the power sources are gated, and therefore power domains can be turned on or off, or isolated from other power domains. Thus, the designer provides a set of clock domain constraints and power domain constraints 212 as part of the initial design.

[0025] According to various aspects of the present invention, initiators and targets are communicatively connected to a Network Interface Unit (NC). An initiator is a unit that sends a request. Initiators are typically configured to read and write commands. A target is a unit that responds to or grants a request. Targets are typically configured to read and write commands. Each initiator is attached to or connected to the NC via an NIU. An NIU attached to an initiator is called an Initiator Network Interface Unit (INIU). Furthermore, each target is attached to the NC via an NIU. An NIU attached to a target is called a Target Network Interface Unit (TNIU). The main function of the NC is to transport each request from an initiator to the desired destination target, and if the request solicits or requires a response, the NC transports the response from each target to the corresponding requesting initiator. Initiators and targets have many different parameters that characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which they belong are defined. The width of the data bus they use to transmit and receive write and read payloads is a few bits. According to various aspects of the present invention, the width of the data bus for the connection (communication path to and from the target) used to transmit write requests and receive write responses is also defined. Furthermore, the clock and power domain definitions are references to the aforementioned clock and power domains present in the SoC, as described herein.

[0026] Continuing with reference to Figures 2A and 2B, and also to Figure 4, the connectivity table 400 is shown. According to various aspects of the present invention, table 400 allows traffic to be defined by classification. The tool allows the use of traffic class labels for each connection between initiators and targets. As shown in table 400, there are three traffic classes: L1, L2, and L3. Traffic class labels are arbitrary labels selected by the user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. Each label represents the need for an independent network resource. Each label may be physically different or use a virtual network, provided that a separate subnetwork is provided by the present invention and supported by the underlying NoC technology.

[0027] According to various aspects of the present invention, an initiator does not need to be able to send requests to all targets or targets connected to a NoC. The precise definition of targets that can receive requests from an initiator is outlined or described in a connectivity table, such as Table 400. Connectivity and traffic class labeling information can be represented as explicit or conceptual matrices. Each initiator has a row, and each target has a column. If an initiator must be able to send traffic to a target, a traffic class label must be present at the intersection of the initiator row and the target column. If there is no label at the intersection, the tool does not require connectivity between that initiator and its target. For example, initiator 1 (M1) connects to target 1 (S1) using a defined label 1 (L1), but M1 does not communicate with S2, and therefore there is no label at the intersection of M1 and S2. According to various aspects of the present invention, the actual format used to represent connectivity may differ, as long as each initiator-target combination has a precise definition of its traffic class, or, in the case of no connectivity, has no classification label. It is within the scope of the invention that an initiator / target connection supports multiple traffic classes.

[0028] Referring here to Figure 5, Table 500 is shown, representing various aspects of the present invention, including various scenarios for read (RD) and write (WR) transactions (shown in Figure 2A). Table 500 contains information defining various throughput rates provided to the tool. Each scenario defines the expected performance in terms of data throughput between the initiator and the target. Each scenario describes the expected required read bandwidth and expected required write bandwidth between each initiator and each target. Throughput is defined in bytes per second (B / s). A typical SoC has multiple operating modes. For example, an SoC for a smartphone may have a game operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that depend on different throughput rates. Thus, the set of scenarios represents the different operating modes supported by the SoC, and correspondingly, the expected minimum NoC performance in terms of throughput between the initiator and the target.

[0029] A scenario can be represented as two matrices, one defining read throughput and the other defining write throughput. According to various aspects of the present invention, the read throughput requirement is used to size the response network that handles data returning from the target to the initiator. The write throughput requirement is used, according to various aspects of the present invention, to size the request network, which is data moving from the initiator to the target. Table 500 shows examples of throughput requirements for various scenarios according to various aspects of the present invention. The actual format used to represent a scenario may differ, insofar as each pair of (initiator, target) has a precise definition of the minimum throughput required for reading and writing. In Table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100 MB / s. In Table 500, a write transaction from M1 to S1 has a minimum throughput of 50 MB / s.

[0030] It is within the scope of this invention that latency refers to the number of clock cycles it takes for data to travel through a network. Latency causes problems in transport networks, even with high bandwidth (frequency). An example of a "real-time traffic class" is video data from a camera in an autonomous vehicle. Long latency in data propagation is unacceptable. If some data is lost, the vehicle becomes unsafe. A traffic class that is still real-time but less critical is for audio and / or video in entertainment systems. Having gaps in that data is undesirable, but not dangerous. An example of non-real-time data is data from a gas gauge sensor in a car. If the data is delayed by a few seconds, it is not a problem because the rate of change of the data is very slow compared to the operating speed of the SoC.

[0031] According to some aspects of the present invention, the tool scenario is not defined, in which case the tool optimizes the NoC synthesis process for physical costs such as the lowest gate cost and / or lowest wire cost.

[0032] Referring here to Figure 6 together with Figure 2B, an initial network 600 is created according to various embodiments of the present invention. The network 600 implements a connectivity matrix having the following defined parameters or components.

[0033] • One network interface unit per initiator. • One network interface unit per target, • One switch is created for each defined traffic class, called the main switch for the class. • After each initiator / initiator NIU, there is one switch that splits the traffic to the different main switches that this initiator needs to reach. • One switch in front of each target / target NIU merges traffic from different main switches that are sending traffic to that target. The data width of each switch and the clock domain to which it belongs are calculated using the data width and clock domain of each attached interface as input to the tool. According to various aspects of the present invention, each step of transforming a network that is part of a NoC also performs the calculation of the data width and clock domain of the newly created network elements.

[0034] Referring here to Figures 7 and 2B, the network 600 of Figure 6 is shown, and the tool process transforms the network 600 according to various embodiments of the present invention. Sequencer 250 has input 254 representing the decomposition of main switches into mergers and splitters. The tool decomposes each main switch of the network 600 into equivalent implementations using splitters and mergers. According to various embodiments of the present invention, some switches have a single inlet port and multiple outlet ports. According to various embodiments of the present invention, some switches have multiple inlet ports and a single outlet port. Each main switch inlet port is connected to a splitter, and each main switch outlet port is connected to a merger. For the main switches, the splitters and mergers are connected together according to a connectivity table.

[0035] Referring here to Figure 8, floor plans 800 according to various embodiments of the present invention are shown. The sequencer 250 has an input 256 representing the creation of a roadmap between each initiator and target. The floor plan 800 includes an initiator interface (M0) on the floor plan and a physical path 802 calculated between each of its connected targets, such as target S0, target S1, target S2, and target S3. The path 802 is called the splitter roadmap for initiator M0 and, although not shown, all initiators have a splitter roadmap. The tool uses any algorithm suitable for finding a path between a source point and multiple destination points, including an algorithm that minimizes the length of the path.

[0036] Referring here to Figure 9, the floor plan 800 is shown with the calculated physical paths 902 between the target interface of target S0 on the floor plan and each of its connected initiators. The paths 902 are the merger roadmap of target S0. As is obvious, all targets have a merger roadmap. The tool uses any algorithm suitable for finding paths between multiple source and destination points, including an algorithm that minimizes the length of the paths. According to various aspects of the present invention, the tool transforms the network to maintain its functionality and add location information to the network elements.

[0037] Referring here to Figure 10, the floor plan 800 is shown along with routes 1002 according to various embodiments of the present invention. The sequencer 250 has an input 258 that provides the physical distribution of splitters and mergers on the roadmap. Using this tool, each switch is broken down into mergers and splitters. Using the tool, each splitter in the main switch is further broken down into a cascade of splitters, and each splitter in the cascade is placed at a branch point in the splitter roadmap of the attached initiator. A branch point in the roadmap is defined by the fact that a route is divided into two or more branches.

[0038] Referring here to Figure 11, the floor plan 800 is shown along with the routes 1102 according to various aspects of the present invention. Using the tool, each switch in each merger within the main switch is further broken down into a cascade of mergers, and each merger in the cascade is placed at a branch point in the merger roadmap of the attached target. A branch point in the roadmap is defined by the fact that the route is divided into two or more branches. The process of breaking down a splitter within a cascade of splitters maintains the original splitter function because the number of inputs to the cascade remains one and the number of outputs in the cascade is the same as the number of outputs in the original splitter. The process of breaking down a merger within a cascade of mergers maintains the original merger function because the number of outputs in the cascade remains one and the number of inputs to the cascade is the same as the number of inputs to the original merger. According to various aspects of the present invention, the effect of the process is to obtain a set of basic switches represented by mergers and splitters, physically placed near where actual connections between switches are required.

[0039] According to various aspects of the present invention, the tool transforms the network to reduce the number of wires used between switches that can be achieved while maintaining performance defined in a scenario, which is a set of the minimum required throughput between an initiator and a target. According to various aspects of the present invention, the switches are clustered for performance-aware switching, and mergers and splitters distributed on a roadmap are treated like ordinary switches.

[0040] According to one aspect of the present invention, the tool uses an iterative process to merge switches under conditions that still satisfy performance requirements until no further switch merges can occur. The tool uses a process described below.

[0041] 1) While further switch fusion is not possible, do the following: a) Select a candidate switch to merge with one of its neighbors. The selection process ensures that all switches in the network are ultimately candidates.

[0042] b) Once a candidate is selected, a neighbor to merge with is searched. The adjacency criterion is based on an evaluation of a cost function. The cost function shall return the switch that is "most suitable" for merging with the candidate. The definition of "most suitable" is implementation-dependent, but the cost function must be such that the potential merging of the two switches maximizes the gain with respect to at least one metric, including congestion, wire length, logic area, power, and performance.

[0043] c) If fusion occurs, test whether all performance scenarios still meet the minimum throughput requirements. If not, these two switches cannot be merged. The process performed by the tool searches for other neighbors until it can no longer find any more neighbors, in which case the network is corrected by merging the candidate switch with its neighbor until all switches remain as they are, or until a neighbor is found that can be merged with the candidate without violating the minimum throughput requirements for all scenarios.

[0044] According to various aspects of the present invention, the process can ensure that the switches do not exceed a certain size (maximum number of inlet ports, maximum number of outlet ports). If the combined switches exceed a set threshold, merging is prevented.

[0045] Referring here to Figure 12, a candidate switch SW3 is shown next to switch SW4 for merging according to various aspects of the present invention. Sequencer 250 has input 260 that provides performance-aware switching clustering. The tool performs the process of merging two switches. When switches are merged, the wires that were coming out of the different switches are simplified into a single wire from each connected switch to the merged switch. According to various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1 and SW4 and SW3 are combined and replaced by a single connection between SW1 and SW3_4. Thus, long connections between distant switches are eliminated and minimized, while connections between close switches are eliminated and made within the switches themselves.

[0046] Referring again to Figure 2B, the input 262 to the sequencer 250 includes various optimizations that can be performed to further reduce the number of wires used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include detecting links that can be removed because they are not in use or because their traffic can be rerouted, reducing the width of links if they are wider than required in the scenario, and performing wire length optimization by finding the optimal placement of all switch elements that minimizes the total wire length of the network, which is the sum of the products of the distance spanned by each connection between network elements and the width of that connection.

[0047] Continuing to refer to Figure 2B, the input 264 to the sequencer 250 includes creating a valid NoC by modifying the location of the network elements so that they fit into the allocated free space, do not overlap, and are within the limits of the corresponding clock and power domains. According to various aspects of the present invention, the area occupied on the die by each network element is calculated using information provided regarding the capabilities of the present technology, such as the area of ​​a reference logic gate. Each element is then tested for accuracy of its placement (sufficient free space exists for the element and no other elements overlap). If the test fails, the element is moved until a suitable location is found in which the test passes.

[0048] According to another aspect of the present invention, extensions of clock and power domains on a floor plan are provided, and each element is tested to ensure that it is located within the boundaries of the designated clock and power domains. If the test fails, the element is moved until a suitable location is found in which the test passes. Once a suitable placement is found for each element, routing is performed for each connection between the elements. The routing process finds a suitable path for the set of wires making connections between the elements. After routing is performed, distance-span pipeline elements are inserted into the links as needed, using information provided regarding the capabilities of the present technology, based on the time it takes for a signal to cover a distance of 1 mm.

[0049] According to some aspects and embodiments of the present invention, the tool generates one or more computer files describing the generated NoC, which include the following:

[0050] List of network elements and their configuration: data width, clock domain. The location of each generated network element on the floor plan.

[0051] A set of routes that pass through network elements that implement a connection. According to an aspect of the present invention, a route is an ordered list of network elements, where there is one network element for each pair of (initiator, target) and one for each pair of (target, initiator). The route describes how traffic flows between pairs and which elements it passes through.

[0052] According to various aspects of the present invention, the tool is used to generate metrics related to the generated NoC, such as a histogram of wire length distribution, a histogram of switches by number of switches, and a histogram of switches by size.

[0053] According to another aspect of the present invention, the tool automatically inserts various adapters and buffers into the network. The tool inserts adapters based on the adaptations required between two elements having different data widths, different clock and power domains. The tool inserts buffers based on the scenario and detected rate mismatches.

[0054] According to some aspects and embodiments, the tool can be used to ensure that multiple iterations of synthesis are performed for incremental optimization of NoC, including situations where one constraint provided to the tool is information about a previous run.

[0055] After the software synthesis process is executed, the results are generated in a machine-readable format, such as a computer file, using a clearly defined format for capturing information. An example of such a format is XML, and another example of such a format is JSON. The scope of the present invention is not limited by any particular format.

[0056] Figure 13 shows a method 1300 performed by a tool that augments the synthetic NoC with data that serves as guidance for the physical implementation of the synthetic NoC. In step 1302, constraint parameters for the network are received by the tool, and the constraint parameters are selected from a set of constraints that include at least physical constraints and performance constraints. In step 1304, the physical floor plan of the NoC is augmented with additional information that helps guide the physical implementation. For example, the information may relate to placeholders for potential pipelines in the physical floor plan. In step 1306, the tool constrains the physical implementation of connections to locations on the physical floor plan within the constraint parameters, based on the physical floor plan or the augmented information added thereto. In step 1308, the tool is used to direct the gates of connections to the shortest routing distance from the connection by comparing the gates with a list of routing distances between the gates and connections detected by the tool. In step 1310, the tool is used to calibrate the parts of the logical interconnection to fit the size of the tool by dividing the logical interconnection into parts.

[0057] Figure 14 shows a flowchart illustrating an alternative method 1400 used by a tool to create a synthetic NoC using data that provides potential guidance for physical implementation. In step 1402, the tool receives timing requirements for the NoC. In step 1404, the tool receives performance constraints for the NoC. In step 1406, the tool augments the physical floor plan of the NoC with information that can be used to guide the implementation of the synthesized NoC. In step 1408, the tool implements a timing estimation configured to determine whether the length between a first component and a second component located on the physical floor plan exceeds the timing requirements (timing constraints). In step 1410, in response to exceeding the timing requirements, the tool identifies a physical insertion point for at least one link into the physical floor plan. In step 1412, at least one link is inserted into the floor plan using parameters specific to the wire delay technique according to some aspects and embodiments of the present invention. In step 1414, the tool identifies the minimum set of module areas that can be assigned to a particular link of the at least one link in the NoC topology.

[0058] Figures 15A and 15B illustrate the processes used by the tools in Figures 13 and 14 to physically implement the topologies of the synthesized NoC according to various embodiments of the present invention. Any physical implementation tools are provided, including but not limited to the Synopsys SNPS Design Compiler, which has NoC topology information 1502 including a physical floor plan, component locations, and / or specification inputs. Routes are produced by topology synthesis (also called NoC generation) 1504 and configured to follow floor plan areas or a set of checkpoints. Mechanisms 1506 include, but not limited to, timing realizations such as distance pipe insertion configured to improve timing between two components. Distance pipeline placeholder insertion 1510 may involve inserting placeholders for potential pipelines using parameters specific to wire delay techniques. Using this method, many segments in the network fall within a legal length range for timing closure. In other words, the length between two components falls within parameters established in the timing constraints. Placeholders are typical components of the topology known as links.

[0059] Referring again to Figures 15A and 15B, the automated module area creation 1512 facilitates the creation of a minimum set of module areas to which specific links in the topology are assigned. Links inserted as pipeline placeholders may be reused as checkpoints. For each route generated by topology synthesis 1504, if placement guidance calculation 1508 detects a problem to be avoided based on information 1502, a new link and corresponding module area are inserted into the physical path. In one example, when a given wire distance traverses two hops along both X and Y, a new link and corresponding module area are inserted into the physical topology 1510 and 1512. In other words, the distance between the two components is too large, exceeding the timing requirements. This process ensures that downstream tools route the topology wires approximately following the path of topology synthesis. Furthermore, because the routing is similar, the pipeline placeholders generated by the generated topology synthesis process have a high probability of reducing timing violations in the final design.

[0060] It is more desirable to guide physical implementation tools to position the NoC topology in a new way, similar to the topology synthesis results, while still allowing physical implementation tools enough flexibility to move logical elements as needed. Rather than forcing the precise location of switches, the route follows a floor plan area or a set of checkpoints.

[0061] In one embodiment, a mechanism for achieving timing between a first component and a second component within a NoC may include, but is not limited to, distance pipe insertion, addition of buffer stages, switching buffers to higher drive buffers or faster buffers, wire width adjustment, and / or indication of which wire layer is being used.

[0062] It is within the scope of the invention that different mechanisms are physically implemented to overcome timing problems in the synthesized topology and to resolve timing problems before they occur by communicating constraints and / or guidance for physical implementation. The physical implementation of connections, including the physical arrangement of objects, components, and / or gates around the NoC topology, is within the scope of the invention, but is not limited to that which downstream tools do not place a first connection far enough away from a second connection to exceed time limits. It is more desirable to synthesize the network for all connections that can satisfy connectivity requirements and to minimize the number of gates in the synthesized network. Minimizing the number of gates in the synthesized network is important, but is not limited to that which allows the NoC to fit within topology parameters, ensures that timing requirements can be met, allows for more efficient construction of smaller networks, and minimizes the overall power used for interconnecting signals.

[0063] In other embodiments, the speed is increased by replacing the driving component with a component having greater drive strength. For example, when a signal is transferred from a first switch to a second switch, the timing requirements are exceeded because the distance between the first and second switches is too large, and a distance pipe may be placed between the first and second switches, or the drive strength may be increased to make the signal faster by using a larger wire with lower resistance to reduce parasitic elements on a particular line.

[0064] In one embodiment, the floorplan area is a mechanism that may include, but is not limited to, constraining components such as switches and / or distance pipe stages to physical and / or approximate physical locations, and / or dividing logical interconnects into multiple parts that are sized to fit downstream tools for proper synthesis. The physical and logical configurations of the interconnects are configured together to form a logical interconnect. The floorplan area is used to constrain components to specific locations. The need for the floorplan area is a response to the increasing size of the network or interconnect of the SoC being developed. In other words, the network or interconnect of the SoC is growing beyond the capacity of downstream implementation tools, which may include wider interconnects and / or more components to be interconnected.

[0065] In the first embodiment, since the performance of the switch may be adversely affected if the switch is moved to a location outside of its constrained location, it may be more desirable to have the switch in a specific constrained location based on data related to the signals received and transmitted by the switch.

[0066] In a second embodiment, additional constraints may be used to place, for example, the gates of components for a switch or pipe stage as close together as possible within each individual component. A current problem in existing placement programs is that components tend to be placed too far apart from one another. It is within the scope of the present invention that a switch is a single component with multiple gates, and each gate needs to be placed. A netlist facilitates the interconnection of these components, while downstream tools physically place the components and create routes for connecting specified logical connectivitys.

[0067] In a third embodiment, the two distinct constraints of the first and second embodiments may be used simultaneously. For example, if the components of a switch designated to have a certain performance are distributed over a wider area than specified, the switch will have lower performance than initially designated. Therefore, it is more desirable to keep the components of this switch in close proximity to each other. Furthermore, based on a larger network, it is more desirable to keep the components within a specific area or region of available space in the floor plan so that the entire network functions as specified or analyzed.

[0068] In one embodiment, in an approximation of a given semiconductor process, the maximum length of a single wire can be established to ensure that the overall timing of that particular path is met. Furthermore, it is important that the signal moves from a first component to a second component within a given time. Due to the excessive length between the first and second components, it may not be possible to move the signal from the first component to the second component within a given time. Consequently, the need for a technical solution of inserting distance pipe stages would solve this technical problem compared to current technology.

[0069] In one embodiment, area estimates of the first and second components are received, and timing and other performance requirements in the optimization of the NoC are balanced to ensure that the resulting NoC gates are positioned, i.e., to fit within the available space in the floor plan allocated to the NoC.

[0070] In one embodiment, power requirements for the NoC are further received, and timing and other performance requirements in optimizing the NoC are balanced to ensure that the resulting NoC does not exceed the power requirements specified by the constraints.

[0071] In one embodiment, physical routing congestion data obtained as an estimate based on the NoC netlist structure or as feedback from downstream implementation tools is further incorporated to balance timing and other performance requirements in NoC optimization, thereby ensuring that the resulting NoC is routable in the available space of the floor plan allocated to the NoC.

[0072] According to several aspects and embodiments of the present invention, a method for guiding the physical generation of a NoC from a synthesized representation is disclosed. The method includes receiving at least one constraint parameter for the NoC with a tool, wherein the at least one constraint parameter is selected from a group of constraint parameters including at least one physical constraint and at least one performance constraint; using the tool to augment a physical floor plan for the NoC with information guiding the physical implementation of the NoC; and using the physical floor plan to constrain the physical implementation of connections to locations on the physical floor plan based on the at least one constraint parameter.

[0073] According to some aspects and embodiments of the present invention, a method is disclosed in which, using a tool, the gate of a connection is directed to the shortest routing distance from the connection by comparing it with a list of routing distances between the gate and the connection detected by the tool.

[0074] According to some aspects and embodiments of the present invention, a method is disclosed which involves dividing a logical interconnection into multiple parts using a tool, thereby calibrating the multiple parts of the logical interconnection to fit the size of the tool.

[0075] According to several aspects and embodiments of the present invention, a method for guiding the physical implementation of a synthesized topology of a NoC is disclosed. The method includes receiving at least one timing requirement for the NoC with a tool, receiving at least one performance constraint for the NoC with a tool, using the tool to augment a physical floor plan for the NoC with information for guiding the physical implementation, implementing a timing estimation configured to determine whether the length between a first component and a second component located on the physical floor plan exceeds at least one timing requirement, and inserting at least one link into the physical floor plan in response to exceeding at least one timing requirement.

[0076] According to some aspects and embodiments of the present invention, a method is disclosed in which at least one link is inserted using parameters specific to wire delay technology. According to some aspects and embodiments of the present invention, a method is disclosed in which a tool further comprises creating at least one module region, and the at least one link of the NoC is assigned to at least one module region.

[0077] According to some aspects and embodiments of the present invention, a method is disclosed that includes receiving area estimates for a first component and a second component.

[0078] According to some aspects and embodiments of the present invention, a method is disclosed which includes performing an equilibration for at least one timing requirement in optimizing a NoC in order to identify that at least one gate of the NoC may be located in at least a portion of the physical floor plan.

[0079] According to some aspects and embodiments of the present invention, a method is disclosed which includes performing an equilibration for at least one performance constraint in optimizing a NoC in order to identify that at least one gate of the NoC may be located in at least a portion of the physical floor plan.

[0080] According to some aspects and embodiments of the present invention, a method is disclosed that includes receiving power requirements for NoC.

[0081] According to some aspects and embodiments of the present invention, a method is disclosed which includes performing an equilibration for at least one timing requirement in optimizing the NoC in order to identify that the NoC does not exceed the power requirement specified by at least one timing requirement.

[0082] According to some aspects and embodiments of the present invention, a method is disclosed which includes performing an equilibration for at least one performance constraint in optimizing a NoC in order to identify that the NoC does not exceed the power requirements specified by at least one performance constraint. According to some aspects and embodiments of the present invention, a method is disclosed which includes providing physical routing congestion data.

[0083] According to some aspects and embodiments of the present invention, a method is disclosed which includes performing balancing for at least one timing requirement in optimizing a NoC in order to identify that the NoC may be routable to at least a portion of the physical floor plan.

[0084] According to some aspects and embodiments of the present invention, a method is disclosed which includes performing a balancer for at least one performance constraint in optimizing a NoC in order to identify that at least one gate of the NoC may be routeable to at least a portion of the physical floor plan.

[0085] Certain methods according to various aspects of the present invention may be performed by instructions stored in a non-temporary computer-readable medium. The non-temporary computer-readable medium stores code, which, when executed by one or more processors, causes a system or computer to perform steps of the methods described herein. The non-temporary computer-readable medium includes rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is suitable for storing code, which includes instructions according to various examples.

[0086] While specific examples have been described herein, it should be noted that different combinations of different components may be possible from different examples. Notable features are presented to better illustrate the examples, but it is clear that certain features can be added, modified, and / or omitted without altering the functional aspects of these examples as described.

[0087] Various examples are methods that utilize the behavior of any or a combination of machines. Examples of methods are completed wherever most configuration steps are performed. For example, according to various aspects and embodiments of the present invention, an IP element or unit includes a processor (e.g., CPU or GPU), RAM, e.g., off-chip dynamic RAM or DRAM, Ethernet®, Wi-Fi, 3G, 4G Long-Term Evolution (LTE), 5G, and other wireless interface standards, and network interfaces for wired or wireless connections. The IP may also include, as needed, various I / O interface devices for various peripheral devices such as touchscreen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (in particular, keyboards and mice). The processor performs the steps of the method described herein by executing instructions stored in the RAM device.

[0088] Some examples are one or more non-temporary computer-readable media configured to store instructions for the methods described herein. Any machine holding a non-temporary computer-readable medium containing any of the required codes may implement one example. Some examples may be implemented as physical devices such as semiconductor chips, hardware description language representations of the logical or functional behavior of such devices, and one or more non-temporary computer-readable media configured to store such hardware description language representations. All descriptions herein enumerating principles, aspects, and embodiments encompass both their structural and functional equivalents. Elements combined herein have effective relationships that can be realized by direct connections or indirectly by one or more other intervening elements.

[0089] Those skilled in the art will recognize numerous modifications and variations. These modifications and variations include any relevant combination of the disclosed features. All descriptions herein enumerating principles, aspects, and embodiments encompass both their structural and functional equivalents. Elements described herein as “coupled” or “communicatively coupled” have an effective relationship achievable by direct or indirect connection using one or more other intervening elements. Embodiments described herein as “communicating” or “being communicated” with other devices, modules, or elements include any form of communication or link and include an effective relationship. For example, a communication link may be established using a wired connection, a wireless protocol, a near-field protocol, or RFID.

[0090] To the extent that the terms “including,” “includes,” “having,” “has,” and “with,” or any variations thereof, are used in either the detailed description or the claims, such terms are intended to be as comprehensive as the term “comprising.”

[0091] Therefore, the scope of the present invention is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the invention are embodied in the appended claims.

Claims

1. A method for guiding the physical generation of NoC from a synthesized representation, The tool receives at least one constraint parameter for the NoC, wherein the at least one constraint parameter is selected from a group of constraint parameters including at least one physical constraint and at least one performance constraint. The process involves using the aforementioned tools to enhance a physical floor plan for the NoC that meets the supplied performance criteria, using information that guides the physical implementation of the NoC, wherein the information includes placeholders for potential pipelines in the physical floor plan. Using the physical floor plan, the physical implementation of the connection guided by the information is constrained to a location on the physical floor plan based on the at least one constraint parameter, Methods that include...

2. The method according to claim 1, wherein, using the tool, the gate of the connection is directed to the shortest routing distance from the connection by comparing it with a list of routing distances between the gate and the connection detected by the tool.

3. The method according to claim 1, further comprising dividing a logical interconnection into a plurality of parts using the tool, wherein the plurality of parts of the logical interconnection are calibrated to the size of the tool.

4. A method for guiding the physical implementation of a synthesized topology of a NoC, The tool receives at least one timing requirement for the aforementioned NoC, The tool receives at least one performance constraint for the NoC, The means of using the aforementioned tools to enhance the physical floor plan for the NoC to meet performance criteria, using information to guide the physical implementation, wherein the information includes placeholders for potential pipelines in the physical floor plan. Implementing a timing estimation configured to determine whether the length between a first component and a second component arranged on the physical floor plan exceeds at least one timing requirement, In response to exceeding at least one of the aforementioned timing requirements, at least one link is inserted into the physical floor plan, Methods that include...

5. The method according to claim 4, wherein the at least one link is inserted using parameters specific to the wire delay technique.

6. The method according to claim 4, further comprising creating at least one module region in the tool, wherein the at least one link of the NoC is assigned to the at least one module region.

7. The method according to claim 4, further comprising receiving area estimates for the first component and the second component.

8. The method according to claim 7, further comprising performing an equilibration for the at least one timing requirement in the optimization of the NoC in order to identify that at least one gate of the NoC may be located in at least a portion of the physical floor plan.

9. The method according to claim 7, further comprising performing a balancer for the at least one performance constraint in the optimization of the NoC in order to identify that at least one gate of the NoC may be located in at least a portion of the physical floor plan.

10. The method according to claim 4, further comprising receiving the power requirements for the NoC.

11. The method according to claim 10, further comprising performing an equilibration with respect to the at least one timing requirement in the optimization of the NoC in order to identify that the NoC does not exceed the power requirement specified by the at least one timing requirement.

12. The method according to claim 10, further comprising performing a balancer with respect to the at least one performance constraint in the optimization of the NoC in order to identify that the NoC does not exceed the power requirement specified by the at least one performance constraint.

13. The method according to claim 4, further comprising providing physical routing congestion data.

14. The method of claim 13, further comprising performing a balancer for the at least one timing requirement in the optimization of the NoC in order to identify that the NoC may be routable to at least a portion of the physical floor plan.

15. The method of claim 13, further comprising performing a balancer for the at least one performance constraint in the optimization of the NoC in order to identify that at least one gate of the NoC may be routeable to at least a portion of the physical floor plan.

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