Photoelectric converters, photoelectric converter systems, mobile devices and equipment

Abstract

To provide a photoelectric conversion device achieving both wide dynamic range and high-speed AD conversion operation.SOLUTION: A photoelectric conversion device includes an AD conversion part for performing analog to digital conversion for obtaining a digital value corresponding to a pixel signal using a pixel for outputting the pixel signal and a ramp signal whose signal voltage changes at a predetermined voltage change rate with respect to time. The AD conversion part includes: an amplification circuit for controlling the gain for the pixel signal; a gain changeover circuit for changing over the gain; a ramp signal changeover circuit for changing over the voltage change rate of the ramp signal; a comparator circuit for outputting a comparison result signal generated from an amplified pixel signal outputted from the amplification circuit and the ramp signal; and a memory part for storing a plurality of determined values according to the comparison result signal, in which the analog to digital conversion is performed with the voltage change rate of the ramp signal and the gain of the amplification circuit which are selected using a predetermined determination value.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion apparatus, a photoelectric conversion system, a moving object, and an electronic device.

Background Art

[0002] As for the performance of photoelectric conversion apparatuses, expansion of dynamic range, high-speed readout, and the like are demanded. Patent Document 1 discloses a technique for expanding the detection dynamic range by switching the pixel signal detection sensitivity and performing analog-to-digital conversion (hereinafter referred to as AD conversion) again based on the result of AD conversion of the pixel signal output from a pixel, to form an image.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the conventional photoelectric conversion apparatus has a problem that a long AD conversion period is required, making it difficult to achieve high-speed readout.

[0005] An object of the present invention is to provide a photoelectric conversion apparatus that achieves both a wide dynamic range and a high-speed AD conversion operation.

Means for Solving the Problems

[0006] A first aspect of the present invention includes an AD conversion unit that performs analog-to-digital conversion to obtain a digital value corresponding to a pixel signal, by using a pixel that outputs the pixel signal, and a ramp signal whose signal voltage changes at a predetermined voltage change rate with respect to time, wherein the AD conversion unit is configured to adjust the amplification factor of the pixel signal The system includes an amplification circuit that controls the amplification factor, an amplification factor switching circuit that switches the amplification factor, a lamp signal switching circuit that switches the voltage change rate of the lamp signal, a comparison circuit that outputs a comparison result signal generated from the amplified pixel signal output from the amplification circuit and the lamp signal, and a memory unit that holds a plurality of judgment values ​​corresponding to the comparison result signal, and the amplified pixel signal and M-1 (M>1) The threshold voltage value of 1 Each A first signal is generated by comparison with the first signal, and the lamp signal switching circuit can switch the voltage change rate of the lamp signal in M ​​ways based on a first determination value corresponding to the first signal, and the amplified pixel signal and N-1 (N>1) generated by the lamp signal The 2 threshold voltage values Each A second signal is generated by comparison with the first signal, and the amplification factor switching circuit can switch the amplification factor of the amplification circuit in N ways based on a second determination value corresponding to the second signal, and the AD conversion unit performs analog-to-digital conversion using the voltage change rate of the lamp signal and the amplification factor of the amplification circuit, selected from three or more combinations that are less than M × N combinations out of the M × N combinations of the switching of the voltage change rate of the lamp signal and the switching of the amplification factor of the amplification circuit, using the first determination value and the second determination value.

[0007] A second aspect of the present invention is a photoelectric conversion system characterized by comprising the above-described photoelectric conversion device and a signal processing unit that generates an image using the signal output by the photoelectric conversion device.

[0008] A third aspect of the present invention is a mobile body equipped with the above-described photoelectric converter, characterized in that it has a control unit that controls the movement of the mobile body using signals output by the photoelectric converter. It is a mobile object.

[0009] A fourth aspect of the present invention is a device characterized by comprising the above-described photoelectric converter, an optical device corresponding to the photoelectric converter, a control device for controlling the photoelectric converter, a processing device for processing signals output from the photoelectric converter, a display device for displaying information obtained from the photoelectric converter, a storage device for storing information obtained from the photoelectric converter, and a mechanical device that operates based on the information obtained from the photoelectric converter. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a photoelectric converter that achieves both a wide dynamic range and high-speed AD conversion operation. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram of the photoelectric converter in the first embodiment. [Figure 2] This is a diagram illustrating the circuit operation of a pixel in the first embodiment. [Figure 3] This is a block diagram of the column circuit in the first embodiment. [Figure 4] This is a timing chart illustrating the AD conversion in the first embodiment. [Figure 5] This is a flowchart illustrating the S-conversion sensitivity setting in the first embodiment. [Figure 6] This figure illustrates the magnification correction of the signal processing circuit in the first embodiment. [Figure 7] This figure illustrates the S-signal error correction in the first embodiment. [Figure 8] This figure illustrates the method for outputting the correction value in the first embodiment. [Figure 9] This is a timing chart illustrating the AD conversion in the second embodiment. [Figure 10] This is a flowchart illustrating the S-conversion sensitivity setting in the second embodiment. [Figure 11] This is a timing chart illustrating the AD conversion in the third embodiment. [Figure 12] This is a flowchart for explaining S conversion sensitivity setting in the third embodiment. [Figure 13] This is a diagram for explaining magnification correction of the signal processing circuit in the third embodiment. [Figure 14] This is a block diagram of a column circuit in the fourth embodiment. [Figure 15] This is a timing chart for explaining AD conversion in the fourth embodiment. [Figure 16] This is a flowchart for explaining S conversion sensitivity setting in the fourth embodiment. [Figure 17] This is a diagram for explaining correction processing of the photoelectric conversion device according to the fourth embodiment. [Figure 18] This is a diagram for explaining correction processing of the photoelectric conversion device according to the fourth embodiment. [Figure 19] This is a diagram for explaining a correction value acquisition method in the fourth embodiment. [Figure 20] This is a diagram for explaining a photoelectric conversion system according to the fifth embodiment. [Figure 21] This is a diagram for explaining a photoelectric conversion system and a moving object according to the sixth embodiment. [Figure 22] This is a diagram for explaining a distance image sensor according to the seventh embodiment. [Figure 23] This is a diagram for explaining an endoscopic surgery system according to the eighth embodiment. [Figure 24] This is a diagram for explaining smart glasses according to the ninth embodiment. [Figure 25] This is a diagram for explaining an electronic apparatus according to the tenth embodiment. [Figure 26] This is a diagram for explaining an apparatus according to the eleventh embodiment. [Description of Embodiments]

[0012] The outline of each embodiment will be described below. In the photoelectric conversion device of the present invention, the pixel signal detection sensitivity is adjusted based on the selection operation of the amplification factor of the column amplifier and the selection operation of the ramp signal during the determination period. The first embodiment is an example in which the selection operation of the ramp signal is performed first during the determination period. The second and third embodiments are examples in which the selection operation of the amplification factor of the column amplifier is performed first during the determination period. The fourth embodiment is an example in which the AD conversion sensitivity to be switched by the selection operation is multi-stage compared to the other embodiments. The AD conversion sensitivity will be described later.

[0013] The following describes each embodiment with reference to the drawings. <First Embodiment> A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figures 1 to 8. First, the configuration of the photoelectric conversion device in this embodiment will be described. Figure 1 is a block diagram of the photoelectric conversion device. As shown in Figure 1, the photoelectric conversion device is provided with a plurality of pixels 101 arranged in a matrix. In an actual photoelectric conversion device, tens of millions of pixels 101 are arranged, but Figure 1 shows an example in which 16 pixels 101, which are a selection of these pixels, are arranged in 4 rows and 4 columns. This photoelectric conversion device is a so-called CMOS image sensor.

[0014] Pixel 101 generates a pixel signal corresponding to the amount of light received by photoelectric conversion. The pixel signal is output to the vertical output line 102. A current source 103 that supplies current is connected to the vertical output line 102. The pixel signal is input via the vertical output line 102 to a column circuit 104, which is provided individually for each vertical output line 102.

[0015] The column circuit 104 functions as an AD conversion unit that amplifies the pixel signal and performs analog-to-digital conversion (hereinafter referred to as AD conversion). In addition to the pixel signal, the column circuit 104 receives a ramp signal used for AD conversion and a count signal. The ramp signal is generated by the ramp signal output circuit 105. The ramp signal is a signal voltage whose output voltage changes at a predetermined rate of change with respect to time. The ramp signal output circuit 105 also inputs multiple ramp signals with different rates of change to the column circuit 104.

[0016] The count signal is generated by the counter circuit 106. The counter circuit 106 starts measuring the number of pulses supplied from a clock pulse supply unit (not shown) in synchronization with the output change of the ramp signal. The count signal is a signal indicating the count value measured by the counter circuit 106.

[0017] In the column circuit 104, pixel signals in the row direction are converted using AD conversion in a single operation within the same period. The signals converted using AD conversion in the column circuit 104 are sequentially output to the outside of the photoelectric converter via the horizontal scanning circuit 107, horizontal output line 108, and signal processing circuit 109.

[0018] The vertical scanning circuit 110 repeatedly switches the pixel rows to be converted by the column circuit 104 and outputs the sequentially converted results to the signal processing circuit 109, thereby performing AD conversion on all pixels.

[0019] The timing generation unit 111 supplies drive signals to the vertical scanning circuit 110, the horizontal scanning circuit 107, the column circuit 104, the ramp signal output circuit 105, and the counter circuit 106. This completes the configuration of the photoelectric conversion device in this embodiment.

[0020] Next, the operation of pixel 101 will be explained using the circuit diagram of pixel 101 shown in Figure 2. The photoelectric conversion unit 201 converts incident light into electric charge. The charge generated in the photoelectric conversion unit 201 is transferred to the floating diffusion (FD) 203 via the transfer MOS transistor 202. The FD 203 functions as a charge-voltage conversion unit that temporarily holds the transferred charge and converts the held charge into a voltage signal.

[0021] When the selection MOS transistor 205 is turned on, the amplification MOS transistor 204 outputs the voltage signal generated at FD203 to the vertical output line 102. Subsequently, the reset MOS transistor 206 resets the voltage at FD203 and the voltage at the photoelectric conversion unit (photodiode) 201 to the pixel voltage SVDD.

[0022] The transfer MOS transistor 202, reset MOS transistor 206, and selection MOS transistor 205 receive the transfer pulse PTX and reset pulse respectively from the vertical scanning circuit 110. It is controlled by the PRES and the select pulse PSEL. This completes the operation of the pixel.

[0023] Next, we will describe the column circuit 104 that performs AD conversion. Figure 3 is a block diagram of the column circuit 104 in this embodiment. The pixel signal is input to the column amplifier 301 via the vertical output line 102. The column amplifier 301 functions as an amplification circuit and has an input capacitor C0, an amplifier AMP, feedback capacitors Cf1, Cf2, Cf3, Cf4, and switches SW1, SW2, SW3, SW4, SW5.

[0024] The amplification factor of the column amplifier 301 is determined by the ratio of the combined capacitance value of the active feedback capacitors Cf1, Cf2, Cf3, and Cf4, which are located on the feedback path of the amplifier AMP, to the capacitance value of the input capacitor C0. The combined capacitance of the feedback path is changed by switching switches SW1, SW2, SW3, and SW4 using a control signal from the amplification factor switching circuit 302. Switch SW5 is controlled by the C0 reset pulse PC0R from the timing generation unit 111. The amplification factor of the column amplifier 301 may be either amplification or attenuation.

[0025] The amplified pixel signal, amplified at a predetermined amplification factor by the column amplifier 301 and output, is input to one input terminal of the comparator 303. A lamp signal is input to the other input terminal of the comparator 303 from the lamp signal switching circuit 304. The lamp signal switching circuit 304 selects the lamp signal to be input to the comparator 303 from among multiple lamp signals input from the lamp signal output circuit 105. The comparator 303 functions as a comparator circuit.

[0026] The lamp signal output circuit 105 inputs the lamp signals VRAMP_H, VRAMP_L, and VRAMP_J to the lamp signal switching circuit 304. In this embodiment, the lamp signal VRAMP_L is a signal whose voltage change rate is 1 / 4 of that of the lamp signal VRAMP_H (the AD conversion sensitivity during AD conversion is 4 times). The lamp signal VRAMP_J is a signal used in the determination period described later.

[0027] Thus, the comparator 303 compares the amplified pixel signal input from the column amplifier 301 with the ramp signal supplied from the ramp signal switching circuit 304 and outputs a comparison result signal. In the comparator 303, when the ramp signal is smaller than the amplified pixel signal, the comparison result signal outputs a low level, and when the magnitude relationship is reversed, it outputs a high level. The comparison result signal is output to the output node. The N memory 305A, S memory 305B, judgment value memory 305C, and selection circuit 306 are connected to this node.

[0028] Next, the N memory 305A, S memory 305B, and judgment value memory 305C will be described. The count signal CNT from the counter circuit 106 is connected to the N memory 305A and the S memory 305B. The N memory 305A and the S memory 305B each hold the value of the count signal CNT at the time the comparison result signal changes polarity during their respective operating periods. The value held by the N memory 305A is called the N signal, and the signal held by the S memory 305B is called the S signal. The judgment value memory 305C holds the judgment value which is the judgment result of the comparator 303.

[0029] The selection circuit 306 outputs control signals to the amplification factor switching circuit 302 and the ramp signal switching circuit 304 based on the judgment value held in the judgment value memory 305C. The amplification factor switching circuit 302 switches the amplification factor of the column amplifier 301 based on the control signal. The ramp signal switching circuit 304 also switches the ramp signal input to the comparator 303 based on the control signal. The S signal, N signal, and judgment value are output to the signal processing circuit 109 via the horizontal output line 108 by the control signal from the horizontal scanning circuit 107. This concludes the explanation of the operation of the column circuit 104.

[0030] Next, we will explain how to acquire the N signal, decision value, and S signal using AD conversion. Figure 4 is a timing chart illustrating the AD conversion. The period from time t400 to time t406 is the N signal acquisition period. At time t400, the vertical scanning circuit 110 sets the selection pulse PSEL to a high level and selects pixel 101 to output the pixel signal PIXOUT. At the same time, the reset pulse PRES is high level, and the voltage of FD203 is reset.

[0031] At time t401, the vertical scanning circuit 110 sets the reset pulse PRES to a low level. At this time, the pixel signal PIXOUT output to the vertical output line 102 is used as the pixel reference signal. The pixel reference signal is a signal that includes the noise component of pixel 101.

[0032] At time t402, the horizontal scanning circuit 107 sets the C0 reset pulse PC0R to a low level, releasing the reset state of the column amplifier AMP and input capacitor C0 of the column amplifier 301. The input capacitor C0 retains a charge based on the voltage of the pixel reference signal when the C0 reset pulse PC0R is set to a low level, and the column amplifier 301 outputs the amplified pixel signal AMPOUT.

[0033] Here, we will provide some supplementary information regarding the amplification factor of the column amplifier 301 in this embodiment. As mentioned above, the amplification factor of the column amplifier 301 is determined by the ratio of the combined capacitance of the feedback path of the amplifier AMP to the input capacitance. In this embodiment, the capacitance values ​​of the feedback capacitors Cf1, Cf2, Cf3, and Cf4 are set to 1 / 8, 1 / 8, 1 / 4, and 1 / 2 times the capacitance value of the input capacitance C0, respectively. When only feedback capacitors Cf1 and Cf2 are used, the amplification factor of the column amplifier 301 is 1 / (1 / 8 + 1 / 8) = 4 times, and this is defined as the first amplification factor. When all feedback capacitors Cf1, Cf2, Cf3, and Cf4 are used, the amplification factor of the column amplifier 301 is 1 / (1 / 8 + 1 / 8 + 1 / 4 + 1 / 2) = 1 time, and this is defined as the second amplification factor.

[0034] At time t402, with switches SW3 and SW4 turned off, and using feedback capacitors Cf1 and Cf2, the amplification factor of the column amplifier 301 becomes 4 times, which is the first amplification factor.

[0035] At time t403, the horizontal scanning circuit 107 sets the comparator reset pulse COMPRES to a high level for a predetermined period of time to initialize the comparator 303.

[0036] During the period from time t404 to time t406, AD conversion of the pixel reference signal is performed. The output of the column amplifier 301 is the signal obtained from the pixel reference signal, which is output as an amplified image signal. At this time, the ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303. Also, the counter circuit 106 starts counting in synchronization with the change in the output of the ramp signal VRAMP_L.

[0037] At time t405, if the ramp signal VRAMP_L exceeds the amplified pixel signal AMPOUT, the signal polarity of the comparison result signal COMPOUT changes. At time t405, the N memory 305A holds the count value indicated by the count signal CNT input to the N memory 305A as the N signal.

[0038] After time t406, the lamp signal VRAMP and count signal CNT are reset and initialized.

[0039] The period from time t407 to time t414 is a determination period, which is a period for acquiring a determination value. In the present embodiment, the determination value is 2-bit information. First, a first determination value J1 is acquired in the period from time t407 to time t411.

[0040] From time t407 to time t408, the transfer pulse PTX is set to a high level. The photoelectric Charges that are incident on the conversion unit 201 and photoelectrically converted are transferred to the FD 203, and output as the pixel signal PIXOUT. The pixel signal PIXOUT at this time is defined as a pixel output signal. The pixel output signal passes through the vertical output line 102 and the column amplifier 301 of the column circuit 104, becomes an amplified pixel signal, and is input to the comparator 303. At this time, the amplified pixel signal from the column amplifier 301 is an output obtained by inverting and amplifying the voltage difference between the pixel reference signal and the pixel output signal.

[0041] At time t409, the ramp signal switching circuit 304 inputs the ramp signal VRAMP_J to the comparator 303. The ramp signal VRAMP_J performs an operation of increasing the voltage value in the period from time t409 to time t410, and holding the voltage value for a certain period from time t410 to time t411. At this time, the voltage value of the ramp signal VRAMP_J held between time t410 and time t411 is defined as a first threshold voltage value VREF1, and the same period is defined as determination period 1.

[0042] In determination period 1, the comparator 303 compares the first threshold voltage value VREF1 with the amplified pixel signal AMPOUT, and outputs a comparison result signal. The comparison result signal at this time is defined as a first comparison result signal, which serves as the first determination value J1. When the amplified pixel signal AMPOUT is lower than the first threshold voltage value VREF1 (AMPOUT < VREF1), the comparator output COMPOUT changes polarity from a low level to a high level. Accordingly, the first determination value J1 becomes "1".

[0043] On the other hand, when the voltage value of the amplified pixel signal AMPOUT is equal to or higher than the first threshold voltage value VREF1 (AMPOUT≧VREF1), the comparator output COMPOUT maintains a low level. At this time, the first determination value J1 is "0".

[0044] The first determination value J1 is input to and held in the first bit of the determination value memory 305C. After time t411, the ramp signal VRAMP is reset. In the case of Figure 4, since the amplified pixel signal AMPOUT is larger than the first threshold voltage value VREF1, the first determination value J1 is "0", and "0" is held in the first bit of the determination value memory 305C.

[0045] During the period from time t412 to time t414, the second determination value J2 is acquired. At time t412, the ramp signal switching circuit 304 inputs the ramp signal VRAMP_J to the comparator 303 again. The ramp signal VRAMP_J performs an operation of increasing the voltage value during the period from time t412 to time t413, and holding the voltage value at the time when the increase is stopped for a certain period. The voltage value of the ramp signal VRAMP_J from time t413 to time t414 is defined as a second threshold voltage value VREF2, and this period is defined as determination period 2.

[0046] In the determination period 2, the comparator 303 compares the second threshold voltage value VREF2 with the amplified pixel signal AMPOUT, and outputs a comparison result signal. The comparison result signal at this time is set as a second comparison result signal, which becomes the second determination value J2. When the amplified pixel signal AMPOUT is lower than the second threshold voltage value VREF2 (AMPOUT<VREF2), the comparator output COMPOUT changes polarity from a low level to a high level. At this time, the second determination value J2 is "1".

[0047] On the other hand, if the amplified pixel signal AMPOUT is higher than the second threshold voltage value VREF2 (AMPOUT ≥ VREF2), the comparator output COMPOUT remains at a low level. In this case, the second judgment value J2 becomes "0". The second judgment value J2 is stored in the second bit of the judgment value memory 305C. After time t414, the ramp signal VRAMP is reset. In the case of Figure 4, since the amplified pixel signal AMPOUT is greater than the second threshold voltage value VREF2, the first judgment value J1 becomes "0", and "0" is stored in the second bit of the judgment value memory 305C.

[0048] The period from time t414 to time t417 is the S signal acquisition period. During the period from time t414 to time t415, the selection circuit 306 sends a control signal to the amplification factor switching circuit 302 based on the second determination value J2. During the same period, the amplification factor switching circuit 302 switches the switches SW1, SW2, SW3, and SW4 of the column amplifier 301 based on the control signal.

[0049] In the case of Figure 4, the selection circuit 306 determines that the second determination value J2 is "0" and sends a control signal to the amplification factor switching circuit 302 so that the amplification factor of the column amplifier 301 changes from 4 times (first amplification factor) to 1 time (second amplification factor). Based on the control signal, the amplification factor switching circuit 302 turns on switches SW3 and SW4. The amplification factor of the column amplifier 301 changes from 4 times to 1 time, and the signal level of the amplified pixel signal AMPOUT decreases.

[0050] On the other hand, if the second determination value held in the determination value memory 305C is "1", the selection circuit 306 does not output a control signal to the column amplifier 301 to the amplification factor switching circuit 302. Subsequently, during the same period, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304 based on the first determination value J1 held in the determination value memory 305C. Based on the control signal, the lamp signal switching circuit 304 selects the lamp signal to input to the comparator 303 at time t415.

[0051] In the case of Figure 4, the first determination value J1 held in the determination value memory 305C is "0". Therefore, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304 so that the lamp signal VRAMP_H is input to the comparator 303. On the other hand, if the first determination value J1 held in the determination value memory 305C is "1", the selection circuit 306 inputs the lamp signal VRAMP_L to the comparator 303.

[0052] At time t415, the ramp signal begins to change output at a constant rate of change. The counter circuit 106 starts counting the clock pulse signal in synchronization with the change in the ramp signal output.

[0053] In this embodiment, at time t415, the ramp signal VRAMP_H is input to the comparator 303. At time t416, if the voltage of the ramp signal VRAMP_H exceeds the amplified pixel signal AMPOUT, the signal polarity of the comparison result signal COMPOUT output by the comparator 303 changes. The S memory 305B stores the value of the count signal CNT at time t416 as the S signal.

[0054] After time t417, the lamp signal VRAMP and count signal CNT are reset and initialized. In the case of Figure 4, the amplified pixel signal AMPOUT is large when the pixel captures a high-brightness object, but the amplification factor of the column amplifier 301 and the voltage change rate of the lamp signal are switched to reduce the S-conversion sensitivity, which is defined by the integrated value, enabling appropriate AD conversion.

[0055] On the other hand, in contrast to this embodiment, if the output of the amplified pixel signal is too small, the amplification factor of the column amplifier 301 is increased, reducing the voltage change rate of the lamp signal and improving the S-conversion sensitivity, thereby enabling high-resolution signal detection even with weak light levels. In this way, a wide detection dynamic range is achieved.

[0056] Here, let's add some information about AD conversion sensitivity. In this embodiment, during the AD conversion period of the S signal from time t415 to time t417, the voltage change rate of VRAMP_H is four times that of the ramp signal VRAMP_L. As mentioned above, the AD conversion value is the value of the count signal CNT output by the counter circuit 106 at the time when the relative magnitudes of the ramp signal and the amplified pixel signal are reversed. The earlier the relative magnitudes of the ramp signal and the amplified pixel signal are reversed, the smaller the value of the count signal CNT becomes, resulting in a smaller AD conversion value.

[0057] As shown in Figure 4 from time t415 to time t417, the ramp signal VRAMP_H, which has a large rate of voltage change, reverses the above-mentioned magnitude relationship faster than the ramp signal VRAMP_L, which has a small rate of voltage change. In other words, the ramp signal VRAMP_H yields a small AD conversion value, resulting in low AD conversion sensitivity. On the other hand, the ramp signal VRAML_L, which has a small rate of voltage change, reverses the above-mentioned magnitude relationship more slowly, resulting in a large AD conversion value, resulting in high AD conversion sensitivity. The ratio of the voltage change rates of the ramp signals produces a difference in counter values, which is the reciprocal of that ratio.

[0058] Here, we will provide further explanation regarding the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 in this embodiment. If the amplified pixel signal input to the comparator 303 is always greater than the ramp signal during the S signal acquisition period, the polarity inversion of the comparison signal COMPOUT will not occur, and the correct count signal CNT cannot be obtained. Therefore, there must always be an inversion period during the S signal acquisition period in which the amplified pixel signal is smaller than the ramp signal.

[0059] The first threshold voltage value VREF1 is the threshold voltage for switching the ramp signal input to the comparator 303 when acquiring the S signal. If the first threshold voltage value VREF1 is smaller than the ramp signal VRAMP_L at time t417, there is an inversion period when acquiring the S signal using the ramp signal VRAMP_L. Therefore, it is desirable to set the first threshold voltage value VREF1 to be equal to or less than the signal level of VRAMP_L at time t417, as shown in (Equation-1) below. VREF1≦VRAMP_L(t417) (Equation-1) When the amplified pixel signal is greater than VREF1, it switches to the ramp signal VRAMP_H during S signal acquisition.

[0060] The second threshold voltage value VREF2 is a threshold voltage for switching the amplification factor of the column amplifier 301 during S signal acquisition. The second threshold voltage value VREF2 serves as a reference signal that reduces the amplification factor of the column amplifier 301 so that an inversion period occurs when the amplified pixel signal becomes larger than the ramp signal VRAMP_H at time t417. Therefore, it is desirable that the second threshold voltage value VREF2 is set to be equal to or less than the ramp signal VRAMP_H at time t417, as shown in the following (Equation-2). VREF2≦VRAMP_H(t417) (Equation-2)

[0061] Further, from the ratio of the voltage change rates of the ramp signal VRAMP_L and the ramp signal VRAMP_H, the following Equation-3 is obtained. VREF1<VREF2 (Equation-3) Here, the maximum threshold voltage value included in the first threshold voltage value is smaller than the minimum threshold voltage value included in the second threshold voltage value. The reason for excluding the equal sign in the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 is for the purpose of S signal correction, which will be described later.

[0062] Next, in the present embodiment, a method for selecting the amplification factor of the column amplifier 301 during S signal acquisition and the ramp signal to be input to the comparator 303 according to the signal level of the amplified pixel signal AMPOUT input to the comparator 303 during the determination period will be described.

[0063] Figure 5 is a flowchart for describing the amplification factor of the column amplifier 301 and the selection of the ramp signal input to the comparator 303 when acquiring the S signal of the photoelectric conversion device according to the present embodiment. There are three patterns of combinations of the amplification factor of the column amplifier 301 and the ramp signal input to the comparator 303 in the present embodiment, which are "Setting A", "Setting B", and "Setting C", and each will be described. First, the amplification factor of the column amplifier 301 is set to 4 times, which is the first amplification factor. Further, the ramp signal VRAMP_L is input from the ramp signal switching circuit 304 to the comparator 303 . Under this condition, N signal acquisition is performed. The above is common to all settings.

[0064] Hereinafter, each setting will be described respectively. First, "Setting A" will be described. "Setting A" shows an example in which the signal level of the amplified pixel signal AMPOUT is low, and the pixel is irradiated with low-luminance light. In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting A", AMPOUT<VREF1 is satisfied, and the first determination value J1 becomes "1". "1" is held in the first bit of the determination value memory 305C.

[0065] In determination period 2, the amplified pixel signal AMPOUT is compared with the second threshold voltage value VREF2. From the relationship of VREF1<VREF2, AMPOUT<VREF2 is satisfied. Accordingly, the second determination value J2 becomes "1", and "1" is held in the second bit of the determination value memory 305C.

[0066] The amplification factor of the column amplifier is maintained at 4 times, which is the second amplification factor. At time t415, based on the first determination value J1=1 held in the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303, so that the AD conversion sensitivity becomes 4 times. Thus, in "Setting A", the ramp signal VRAMP_L, for which the amplification factor of the column amplifier 301 is 4 times as the first amplification factor and the AD conversion sensitivity is also 4 times, is input to the comparator 303. At this time, the S signal is acquired in a state where the S conversion sensitivity defined by the integrated value of the aforementioned amplification factor of the column amplifier 301 and the AD conversion sensitivity based on the voltage change rate of the ramp signal is 4×4=16 times.

[0067] Next, "Setting B" will be described. "Setting B" shows an example in which the signal level of the amplified pixel signal AMPOUT is medium, and the pixel is irradiated with light of medium luminance. In the determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting B", AMPOUT≧VREF1 is satisfied, and J1 becomes "0" as the first determination value. "0" is held in the first bit of the determination value memory 305C.

[0068] Next, in the determination period 2, the amplified pixel signal AMPOUT is compared with the second threshold voltage value VREF2. In "Setting B", AMPOUT<VREF2 is satisfied, and the second determination value J2 becomes "1". "1" is held in the second bit of the determination value memory 305C. At the same time, the amplification factor of the column amplifier is switched to the second amplification factor, changing from 4 times to 1 time. At time t415, based on the first determination value J1=0 held in the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304.

[0069] The ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303, so that the AD conversion sensitivity becomes 1 time. Thus, in "Setting B", the ramp signal VRAMP_L, for which the amplification factor of the column amplifier 301 is 4 times as the first amplification factor and the AD conversion sensitivity is 1 time, is input to the comparator 303. At this time, the S signal is acquired with the S conversion sensitivity of 4×1=4 times.

[0070] Finally, "Setting C" will be explained. "Setting C" represents an example where the signal level of the amplified pixel signal AMPOUT is high, and the pixel is illuminated with high-luminosity light. During judgment period 1, the amplified pixel signal AMPOUT, which includes the image signal, is compared with the first threshold voltage value VREF1. In "Setting C," AMPOUT ≥ VREF1, and the first judgment value J1 becomes "0". The first bit of the judgment value memory 305C is kept at "0".

[0071] Next, during judgment period 2, the amplified pixel signal AMPOUT, which includes the image signal, is compared with the second threshold voltage value VREF2. In "Setting C," AMPOUT ≥ VREF2, and the second judgment value J2 becomes "0". The second bit of the judgment value memory 305C holds "0". This is done. At the same time, the amplification factor of the column amplifier switches to the second amplification factor, from 4 times to 1 time. At time t415, based on the first judgment value "0" held in the judgment value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs the lamp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1 time. Thus, in "setting C", the lamp signal VRAMP_L, which results in an AD conversion sensitivity of 1 time, is input to the comparator 303 at the first amplification factor where the amplification factor of the column amplifier 301 is 1 time. At this time, the S-signal is acquired with an S-conversion sensitivity of 1 × 1 = 1 time.

[0072] As described above, based on the result of judging the amplified image signal AMPOUT from the column amplifier 301 during the judgment period, the S-conversion sensitivity can be switched to 16x, 4x, and 1x to obtain the S-signal value.

[0073] In terms of settings, the column amplifier's amplification factor can be set to 4x or 1x, and the AD conversion sensitivity of the ramp signal can also be selected from 4x or 1x. This results in 2 x 2 = 4 possible combinations, but in this embodiment, S-signal conversion is performed using 3 of these 4 settings. This ensures that when switching from "Setting A" to "Setting B" and from "Setting B" to "Setting C," only one of the amplification factor of the column amplifier 301 or the voltage change rate of the ramp signal is changed. Here, we have shown an example of 2 x 2 = 4 combinations, but this embodiment is not limited to this. For example, if the amplification factor can be selected in N ways and the AD conversion sensitivity of the ramp signal can be set in M ​​ways, there can be M x N combinations of AD conversion sensitivity and column amplifier amplification factor settings. In this case, S-signal conversion is performed with fewer than M x N switching combinations. At this time, the first threshold voltage value consists of M-1 (M>1) threshold voltages, and the second threshold voltage value consists of N-1 (N>1) threshold voltages.

[0074] When the settings are switched, the S signal requires the correction process described later. However, if only one of the settings is changed, the occurrence of correction errors due to the complexity of the correction process can be prevented, and good signal characteristics can be obtained. Also, as shown in (Equation-3), the reason why the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 must be VREF1 ≠ VREF2 is the same. If they are equal, then when the pattern is switched, the amplification factor switching of the column amplifier 301 and the switching of the ramp signal will occur simultaneously.

[0075] Next, the magnification correction process of the S signal in the signal processing circuit 109 in this embodiment will be explained with reference to Figure 6. The horizontal axis represents the signal level (in voltage value V) of the pixel signal PIXOUT, which is correlated with the amount of light incident on pixel 101. The vertical axis represents the output value (in LSB) after correction processing by the signal processing circuit 109.

[0076] First, using Figure 6(a), we will explain the difference in the correction magnification of the S signal due to the difference in the second judgment value J2 stored in the judgment value memory 305C when the S signal is acquired. The pixel signal PIXOUT is assumed to produce an amplitude change up to a maximum voltage value VA2[V] depending on the amount of light incident on the pixel 101. When the amplification factor of the column amplifier 301 is 4 times, the AD conversion value DA1[LSB] is obtained when the pixel signal PIXOUT is at a voltage value VA1[V], which is 1 / 4 of the voltage value VA2[V]. Also, when the amplification factor of the column amplifier 301 is 1 time, the AD conversion value DA1[LSB] is obtained even when the pixel signal PIXOUT is at a voltage value VA2[V].

[0077] The signal processing circuit 109 receives the N signal, S signal, and a judgment value, and can detect from the judgment value which of the settings A / B / C the S signal obtained by AD conversion was obtained under. In other words, the magnification correction of the S signal is performed based on the judgment value. The amplification factor of the column amplifier 301 when the S signal is acquired is stored in the judgment value memory 305C as a second judgment value J2. If the second judgment value J2 is J2=0, the S signal input to the signal processing circuit 109 is not corrected. On the other hand, If the judgment value J2 for step 2 is J2=1, the S signal is multiplied by 4 by the magnification correction process.

[0078] Furthermore, the voltage value VA1[V] is the voltage value that serves as the boundary for switching the amplification factor of the column amplifier 301 when acquiring the S signal. When the voltage value VA1[V] is converted to the amplified pixel signal AMPOUT at the first amplification factor (×4 times) of the column amplifier 301, it corresponds to the second threshold voltage value VREF2. In the range of the pixel signal PIXOUT from voltage value 0[V] to voltage value VA1[V] (thick line), the amplification factor of the column amplifier 301 when acquiring the S signal is the first amplification factor (×4 times). At this time, the S signal is not subjected to magnification correction processing by the signal processing circuit 109.

[0079] On the other hand, in the range of the pixel signal PIXOUT from voltage value VA1[V] to voltage value VA2[V] (dotted line), the amplification factor of the column amplifier 301 when acquiring the S signal becomes the second amplification factor (×1). At this time, the S signal undergoes a magnification correction process in the signal processing circuit, which multiplies its value by 4 (thick dotted line). The magnification-corrected S signal has a coarser output resolution by the correction factor, but the output bits are expanded. In this way, the signal processing circuit 109 corrects the S signal, providing high resolution at low brightness and reducing resolution at high brightness to widen the light detection range, thereby expanding the dynamic range.

[0080] Next, using Figure 6(b), we will explain the correction ratio, which takes into account not only the difference in the amplification factor of the column amplifier 301 when acquiring the S signal, but also the difference in the voltage change rate of the ramp signal.

[0081] In this embodiment, the column amplifier 301, as shown in Figure 6(a), performs AD conversion with an amplification factor of 4. For a voltage value in the range from 0[V] to VA1[V], a voltage value VR1[ is 1 / 4 of that range. Up to V], the ramp signal VRAMP_L is input to comparator 303. Above that, The ramp signal VRAMP_H is input to comparator 303.

[0082] When the pixel signal PIXOUT is a voltage value VR1[V], under condition A, the AD conversion value DR1[LSB] is obtained. The AD conversion value DR1[LSB] is the maximum value counted by the counter circuit 106 during the period from time t415 to time t417. On the other hand, when the pixel signal PIXOUT is a voltage value VA1[V] which is four times the voltage value VR1[V], under condition B, the AD conversion value DR1[LSB] is also obtained. When the pixel signal PIXOUT is a voltage value VA2[V] which is 4×4=16 times the voltage value VR1[V], under condition C, the AD conversion value DR1[LSB] is also obtained. The AD conversion values, which are S signals obtained under these different settings, are magnified based on the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C.

[0083] If the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C are J1="1" and J2="1" respectively, the S signal is not corrected. This applies to the range of the pixel signal PIXOUT from voltage value 0[V] to voltage value VR1[V] (thick line). If the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C are J1="0" and J2="1" respectively, the S signal receives a 4x magnification correction. This applies to the range of the pixel signal PIXOUT from voltage value VR1[V] to voltage value VA1[V], and the S signal before correction (single dotted line) is magnified to become the 4x multiplied S signal (thick single dotted line). Here, the pixel signal PIXOUT switches between "Setting A" and "Setting B" at voltage value VR1[V].

[0084] The voltage value VR1[V] corresponds to the first threshold voltage value VREF1 when converted to the amplified pixel signal AMPOUT at the first amplification factor. Furthermore, the pixel signal PIXOUT switches between "Setting B" and "Setting C" at the voltage value VA1[V]. The output where the pixel signal PIXOUT has a voltage value VA1[V] corresponds to the second threshold voltage value VREF2 when converted to the amplified pixel signal AMPOUT at the first amplification factor. When the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C are J1=“0” and J2=“0” respectively, the S signal undergoes a 16x magnification correction. This applies to the range of the pixel signal PIXOUT from voltage value VA1[V] to voltage value VA2[V], where the S signal before correction (dotted line) is the 16x multiplied S signal (thick dotted line). This is the result.

[0085] In this way, the amplification factor of the column amplifier 301 when acquiring the S signal and the combination with the ramp signal are subjected to magnification correction processing based on a determination value. In this way, a dynamic range exceeding the number of output bits that can be acquired as an S signal and high resolution at low brightness can be achieved simultaneously with a single AD conversion. However, in reality, ratio errors in the configurable amplification factors of the column amplifier 301 and ratio errors in the voltage change rates between the selected ramp signals may occur. These ratio errors can cause an offset in the digital signal at the boundary points where the above settings switch. Also, if there is a difference in the linearity of the signals output in "Setting A," "Setting B," and "Setting C," an offset can also occur at the boundary points.

[0086] The following describes an error correction processing method to reduce such offset and linearity errors. Figure 7 is a diagram illustrating S-signal error correction in this embodiment. In the error correction processing, correction values ​​used in the error correction processing are acquired by a dedicated correction value acquisition operation. In the correction value acquisition operation, the signals input to the column circuit 104 are not pixel signals from pixels, but correction operation input values ​​V1, V2, and V3 from a reference voltage source (not shown) connected to the vertical output line 102. Correction values ​​are obtained by performing AD conversion on these correction operation input values ​​in each of the settings "Setting A", "Setting B", and "Setting C" used during the S-signal acquisition period.

[0087] The correction values ​​obtained by inputting the correction operation input value V1 to the column circuit 104 will be explained. The value obtained by AD conversion with "Setting A" will be designated as correction value D1. The value obtained by AD conversion with "Setting B" will be designated as correction value D3. The value obtained by AD conversion with "Setting C" will be designated as correction value D6. Next, the correction values ​​obtained by inputting the correction operation input value V2 to the column circuit 104 will be explained.

[0088] AD conversion is performed using "Setting A," and the resulting value is set as correction value D2. AD conversion is performed using "Setting B," and the resulting value is set as correction value D4. Next, the correction values ​​obtained by inputting the correction operation input value V3 to the column circuit 104 will be explained. AD conversion is performed using "Setting B," and the resulting value is set as correction value D5. AD conversion is performed using "Setting C," and the resulting value is set as correction value D7.

[0089] The following describes how to calculate the ratio error of the amplification factor of the column amplifier 301 and the ratio error of the voltage change rate of the ramp signal using the obtained correction values. First, the ratio error of the voltage change rate of the ramp signal is obtained from the ratio of the slope (or difference value) of each line obtained by connecting the correction value D2 and correction value D1 obtained in "Setting A", and the correction value D4 and correction value D3 obtained in "Setting B". This is called the linearity correction value α1. α1 = (D2 - D1) / (D4 - D3) / 4 (Equation - 4)

[0090] The linearity correction value α1 is multiplied by the S signal obtained in "Setting B" to correct the linearity of the S signal obtained in "Setting B" to match the linearity of the signal obtained in "Setting A". In other words, the linearity standard is the linearity of the signal obtained in "Setting A". Similarly, the ratio error of the amplification factor of the column amplifier 301 is obtained from the ratio of the slopes (or difference values) of each line obtained by connecting the correction values ​​D5 and D3 obtained in "Setting B", and the correction values ​​D7 and D6 obtained in "Setting C". This is taken as the linearity correction value α2. α² = (D5 - D3) / (D7 - D6) / 4 (Equation - 5)

[0091] The linearity correction value α2 corrects the linearity of the S signal obtained under "Setting C" to match the linearity of the S signal obtained under "Setting B". However, the S signal obtained under "Setting B" is multiplied by the linearity correction value α1 to match the linearity of "Setting A". Therefore, in addition to α2, α1 is also multiplied when correcting the signal obtained under "Setting C". As a result, the linearity of the signal obtained under "Setting C" is corrected to match the linearity of the signal obtained under "Setting A".

[0092] Next, we will explain the method for calculating the amount of inter-pattern offset that may occur at the boundary point where the settings switch, and the output value output from the signal processing circuit 109 after correcting for linearity and offset.

[0093] First, let's explain how to calculate the offset correction value β1 that occurs when switching from "Setting A" to "Setting B". The correction value D4 obtained in "Setting B" during the correction value acquisition operation becomes the corrected output 4 × α1 × D4 after magnification correction and linearity correction. If this corrected output is equal to the correction value D2, no offset occurs. In other words, the difference between D2 and 4 × α1 × D4 becomes the offset correction value β1. β1=D2-4×α1×D4 (Formula-6) Therefore, the signal SB output by the signal processing circuit 109 after correcting the S signal obtained in "Setting B" is as follows: SB = 4 × α¹ × S + β¹ - N (Equation -7) N is an N signal.

[0094] Next, we will explain how to calculate the offset correction value β2 that occurs when switching from "Setting B" to "Setting C". The correction value D7 obtained in "Setting C" during the correction value acquisition operation becomes a corrected output of 16 × α1 × α2 × D7 after magnification correction and linearity correction. If this corrected output is equal to the corrected output 4 × α1 × D5 obtained by applying magnification correction and linearity correction to the correction value D5, then no offset occurs. In other words, the difference between the corrected outputs becomes the offset correction value β2. β2=4×α1×D5-16×α1×α2×D7 (Formula-8) Therefore, the signal SC, which is obtained by correcting the S signal obtained in "Setting C" in the signal processing circuit 109 and outputting it, is obtained by subtracting the N signal as follows. SC=16×α1×α2×S+β2-N (Formula-9)

[0095] The S signal obtained in "Setting A" is not subjected to correction processing by the signal processing circuit 109, and the output from the signal processing circuit 109 is as follows. SA = SN (Equation -10)

[0096] In this way, by correcting the S signal using the linearity correction values ​​α1 and α2 obtained by the correction operation and the offset correction values ​​β1 and β2, a signal exhibiting good linearity characteristics with respect to the amount of incident light can be obtained. In this embodiment, the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 is defined by (Equation-3), so that when the setting is switched, only one of either the voltage change rate of the lamp signal or the amplification factor of the column amplifier is changed. This simplifies the correction and suppresses the occurrence of correction errors due to the complexity of the correction process. Here, it is desirable that the correction operation input values ​​V2 and V3 are the same values ​​as the pixel signal PIXOUT when the pattern is switched. If the output characteristics include nonlinearity, the offset error can be reduced.

[0097] Next, we will explain how to obtain correction values ​​during the imaging process. Figure 8 illustrates the method for outputting correction values ​​in the photoelectric converter according to this embodiment. Here, the time required to read out one row of pixels 101 arranged on the matrix is ​​defined as 1H. Figure 8 shows the settings of the correction operation input value, the voltage change rate of the lamp signal, and the amplification factor of the column amplifier input to the column circuit 104 in 1H time units over time. The correction values ​​D1, D2, D3, D4, D5, D6, and D7 are output for each row by sequentially switching the correction operation input value, the amplification factor of the column amplifier, and the voltage change rate of the lamp signal using the readout time for eight rows from 1H to 8H. This operation is preferably performed using rows consisting of non-photosensitive pixels that are not used for imaging, such as optical black rows.

[0098] During the correction value acquisition operation, the correction value D1 is acquired from time 0 to time 1H. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with "setting A". The S signal of the row output during this period becomes the correction value D1.

[0099] From time 1H to time 2H, the correction value D3 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with "Setting B". The S signal of the row output during this period will have the correction value D3.

[0100] From time 2H to time 3H, the correction value D2 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with "Setting A". The S signal of the row output during this period will then be the correction value D2.

[0101] From time 3H to time 4H, the correction value D4 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with "Setting B". The S signal of the row output during this period will have the correction value D4.

[0102] The period from time 4H to time 5H is the same as the period from time 1H to time 2H, and the correction value D3 is output. The measurement is performed considering the symmetry of the time series.

[0103] From time 5H to time 6H, the correction value D6 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with "setting C". The S signal of the row output during this period will have the correction value D6.

[0104] From time 6H to time 7H, the correction value D5 is acquired. During this period, the correction operation input value V3 is input, and column circuit 104 performs AD conversion with "Setting B". The S signal of the row output during this period will have the correction value D5.

[0105] From time 7H to time 8H, the correction value D7 is acquired. During this period, the correction operation input value V3 is input, and the column circuit 104 performs AD conversion with "setting C". The S signal of the row output during this period becomes the correction value D7. The correction values ​​D1, D2, D3, D4, D5, D6, and D7 obtained over 8H are input to the signal processing circuit 109 and used for correction processing.

[0106] As described above, by setting the first threshold voltage for determining the voltage change rate of the ramp signal to be smaller than the second threshold voltage for determining the amplification factor of the column amplifier, a wider dynamic range and faster processing are achieved with a single S-signal conversion without complex correction processing. In the above example, the first comparison result signal and the second comparison result signal are generated in that order, but they may also be generated in that order. In that case, it is preferable that the maximum threshold voltage value included in the second threshold voltage value be smaller than the minimum threshold voltage value included in the first threshold voltage value.

[0107] In this embodiment, the amplification factor of the column amplifier 301 and the voltage change rate of the ramp signal are set to 4 times, but are not limited to this. Furthermore, the method for obtaining the correction value, as well as the correction of magnification, linearity error, and offset error, are not limited to what is described here, and the settings used as the basis for correction can be arbitrarily changed. The combination of input capacitance and feedback capacitance of the column amplifier, and the number of capacitors installed, are also examples. The signal amplification factor of the ramp signal is also an example; these can be arbitrarily changed. Also, in this embodiment, the judgment value is set to 2 bits of information, but is not limited to this, and may be 2 bits or more.

[0108] <Second Embodiment> The photoelectric conversion device in the second embodiment will be described with reference to Figures 9 to 10. In the second embodiment, the selection operation of the amplification factor of the column amplifier during the S signal acquisition period is performed first during the determination period. The configuration of the photoelectric conversion device, the pixel circuit, and the column circuit are the same as in the first embodiment, so their description will be omitted.

[0109] Figure 9 shows the timing chart for AD conversion in this embodiment. Here, we will explain the operation of the judgment period, which is a characteristic feature of this embodiment.

[0110] During the judgment period 1, the comparator 303 compares the first threshold voltage value VREF1 with the amplified pixel signal, and the output comparison result signal becomes the first judgment value J1. The first judgment value J1 is input to the first bit of the judgment value memory 305C and held therein. At time t411, the selection circuit 306 sends a control signal to the amplification factor switching circuit 302 based on the first judgment value J1. The amplification factor switching circuit 302 switches its switch based on the control signal.

[0111] In the case of amplified pixel signal 1 (dash-dot line) in Figure 9, during judgment period 1, it is greater than the first threshold voltage value VREF1, so switches SW3 and SW4 are set to high level (solid line). The amplification factor of the column amplifier 301 decreases, and during judgment period 2, the signal level of amplified pixel signal 1 becomes less than VREF2, and the comparator output COMPOUT becomes high level (solid line). On the other hand, in the case of amplified pixel signal 2 (double-dot line) in Figure 9, during judgment period 1, it is less than the first threshold voltage value VREF1, so the comparator output COMPOUT becomes high level (dashed line). Switches SW3 and SW4 do not switch (dashed line), and the amplification factor of the column amplifier does not change. The signal level of the amplified pixel signal remains unchanged and becomes greater than VREF2 during judgment period 2.

[0112] Next, the method for obtaining the second judgment value J2 will be explained. The comparator 303 compares the second threshold voltage value VREF2 with the amplified pixel signal during the judgment period 2. The comparison result signal from the comparator 303 is taken as the second judgment value J2. The second judgment value J2 is stored in the second bit of the judgment value memory 305C.

[0113] In the example of amplified pixel signal 1 (dash-dot line) in Figure 9, since the signal is smaller than the second threshold voltage value VREF2, the second determination value J2 becomes J2=1, and "1" is stored in the second bit of the determination value memory 305C. The comparator output COMPOUT is at a high level (solid line). On the other hand, in the example of amplified pixel signal 2 (double-dot line) in Figure 9, since the signal is larger than the second threshold voltage value VREF2, the first determination value J1 becomes J1=0, and "0" is stored in the second bit of the determination value memory 305C. The comparator output COMPOUT remains at a low level (dashed line).

[0114] The ramp signal input to the comparator 303 at time t415 during the S signal acquisition period is set based on the second determination value J2 in the determination value memory 305C. The selection circuit 306 sends a control signal to the ramp signal switching circuit 304 based on the value of the second determination value J2. When the second determination value J2 is "1", the ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303 from time t415. When the second determination value J2 is "0", the ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303 from time t415. The subsequent processing during the S signal acquisition period is the same as in the first embodiment and is therefore omitted.

[0115] In Figure 9, the amplified pixel signal 1 has an amplification factor of 1 for the column amplifier 301 during the S signal acquisition period, and the ramp signal VRAMP_L is input to the comparator 303. This combination is defined as "Setting D". At time t416A, the polarity of the comparator output COMPOUT (solid line) changes. The value of the count signal CNT is stored in S memory as the S signal. Meanwhile, during the S signal acquisition period, the amplification factor of the column amplifier 301 is 4, and the ramp signal VRAMP_H is input to the comparator 303. This combination corresponds to "Setting B" as defined in the first embodiment. At time t416B, when the polarity of the comparator output COMPOUT (dashed line) changes, the value of the count signal CNT is stored in S memory as the S signal. To elaborate, if the amplified pixel signal is small to the first threshold voltage value VREF1 and the second threshold voltage value VREF2, the S signal is acquired using "Setting A" as defined in the first embodiment. Furthermore, if the amplified pixel signal is large to the first threshold voltage value VREF1 and the second threshold voltage value VREF2, the S signal is acquired using "Setting C" as defined in the first embodiment.

[0116] In other words, in this embodiment, as the signal level of the amplified pixel signal increases, the settings for acquiring the S signal switch in the order of "Setting A" → "Setting B" → "Setting D" → "Setting C". At this time, when switching between "Setting B" and "Setting D", both the amplification factor of the column amplifier 301 and the ramp signal input to the comparator 303 switch. As explained in the first embodiment, when these two switch simultaneously, correction errors in the output value offset at the boundary point are likely to occur. Therefore, in this embodiment, the amplification factor of the column amplifier 301 and the selection of the ramp signal input to the comparator 303 during the S signal acquisition period are controlled based on the result of the judgment value, and in this case, the operation is performed so as to not generate "Setting D", thereby achieving the same signal output as in the first embodiment.

[0117] Next, we will explain the operation of "Setting C" which skips "Setting D" based on the judgment value stored in judgment value memory 305C.

[0118] Figure 10 is a flowchart illustrating the amplification factor of the column amplifier 301 and the selection of the ramp signal input to the comparator 303 when acquiring the S signal. In this embodiment as well, we will explain how to control the system to have one of three settings: "Setting A," "Setting B," and "Setting C."

[0119] First, the amplification factor of the column amplifier 301 is set to 4 times, which is the first amplification factor. The ramp signal VRAMP_L is input from the ramp signal switching circuit 304 to the comparator 303. Under these conditions, N signal acquisition is performed.

[0120] Hereinafter, the differences between the three "settings" will be described respectively. First, "Setting A" will be described. "Setting A" shows an example in which the signal level of the amplified pixel signal AMPOUT is low, and the pixel is irradiated with low-luminance light. In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting A", AMPOUT < VREF1 is satisfied, and the first determination value J1 is held as "1" at the first bit of the determination value memory 305C.

[0121] Next, in determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2. In "Setting A", AMPOUT < VREF2 is satisfied, and the second determination value J2 is held as "1" at the first bit of the determination value memory 305C. The amplification factor of the column amplifier 301 remains the first amplification factor, which is 4 times. Then, at time t415 in the S signal acquisition period, based on the second determination value J2=1 held at the second bit of the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303, and the AD conversion sensitivity becomes 4 times.

[0122] Thus, in "Setting A", the ramp signal VRAMP_L with an AD conversion sensitivity of 4 times is input to the comparator 304 at the first amplification factor where the amplification factor of the column amplifier 301 is 4 times. That is, S signal acquisition is performed with an S conversion sensitivity of 4×4=16 times.

[0123] Next, "Setting B" will be described. "Setting B" shows an example in which the signal level of the amplified pixel signal AMPOUT is medium, that is, the pixel is irradiated with medium-luminance light.

[0124] In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting B", AMPOUT<VREF1 is satisfied, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C.

[0125] Next, in determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2. In "Setting B", AMPOUT≧VREF2 is satisfied, and the second determination value J2 is held as "0" in the second bit of the determination value J of the determination value memory 305C. Then, at time t415 in the S signal acquisition period, based on the first determination value "0" held in the second bit of the determination value J of the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1 time.

[0126] In this way, in "Setting B", the ramp signal VRAMP_H with AD conversion sensitivity of 1 time is input to the comparator 303 at the first amplification factor at which the amplification factor of the column amplifier 301 is 4 times. That is, S signal acquisition is performed at an AD conversion sensitivity defined by an integrated value of 4×1=4 times.

[0127] Finally, "Setting C" will be described. "Setting C" shows an example in which the signal level of the amplified pixel signal AMPOUT is high, and high-luminance light is irradiated to the pixel.

[0128] The amplified pixel signal AMPOUT including the image signal is compared with the first threshold voltage value VREF1. In "Setting C", AMPOUT≧VREF1 is satisfied, and "0" is held as the first determination value J1 in the second bit of the determination value memory 305C. Next, regarding determination period 2, when the first determination value J1 is "0", the logic is such that the second determination value J2 is also forcibly set to "0".

[0129] For example, as shown in the following formula, the second determination value is an integrated value of the first determination value and the determination value obtained in determination period 2. First determination value J1 = determination result of determination period 1 (Equation-11) The second judgment value J2 = the first judgment value J1 × the judgment result for judgment period 2 (Equation-12)

[0130] This allows the system to operate such that when the first judgment value is 1, the judgment value for judgment period 2 is valid, and when the first judgment value is 0, the second judgment value is set to 0 regardless of the judgment result. In other words, the second judgment value J2 is determined in combination with the first judgment value. As a result, even if the first judgment value J1 becomes J1=0 and the amplification factor of the column amplifier 301 is reduced, and the amplified pixel signal falls below the second threshold voltage value VREF2, the "setting D" state does not occur. Therefore, the AD conversion and S signal correction processing can be performed using the same method as in the first embodiment. The subsequent methods for correcting the magnification of the S signal and the amplification ratio error are common, so their explanation is omitted.

[0131] As shown in the second embodiment, even if the amplification factor of the column amplifier 301 is determined first during the determination period, the processing can be carried out in the same manner as in the first embodiment.

[0132] In this embodiment, the second determination value J2 is the product of the first determination value J1, but it is not limited to this.

[0133] <Third Embodiment> A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 11 to 14. In the third embodiment, similar to the second embodiment, the selection operation of the amplification factor of the column amplifier during the S signal acquisition period is performed first during the determination period.

[0134] In this embodiment, transitions to unnecessary settings are suppressed by defining the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2. These setting transitions are suppressed by setting the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 as follows. VREF1≦VREF2 (Formula-13)

[0135] In the present embodiment, for convenience, a ramp signal VRAMP_M whose rate of change is twice that of the ramp signal VRAMP_L (with AD conversion sensitivity being 1 / 2 times) is used in place of the ramp signal VRAMP_L. For the sake of description, the configurations of the photoelectric conversion apparatus, the pixel circuits, and the column circuits are the same as those in the first embodiment, and descriptions thereof are omitted.

[0136] FIG. 11 is a timing chart for describing the AD conversion operation in the present embodiment. As shown in the determination period of FIG. 11, here VREF1=VREF2 such that the magnitude relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 satisfies the relationship represented by (Equation-8). The methods for acquiring the N signal, the determination value, and the S signal are the same as those in the second embodiment, and descriptions thereof are omitted.

[0137] The combination setting of the amplification factor of the column amplifier 301 and the ramp signal to be input to the comparator 303 in the present embodiment will be described. FIG. 12 is a flowchart for describing setting of S conversion sensitivity in the present embodiment.

[0138] The following is common to the three settings. First, the amplification factor of the column amplifier 301 is set to 4 times, which is the first amplification factor. In addition, the ramp signal VRAMP_M is input from the ramp signal switching circuit 304 to the comparator 303. Under these conditions, N signal acquisition is performed.

[0139] Hereinafter, the differences among the three "settings" will be respectively described. First, "Setting E" will be described. "Setting E" shows an example where the signal level of the amplified pixel signal AMPOUT is low, that is, light of low luminance is emitted to the pixel.

[0140] In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting E", AMPOUT<VREF1 is satisfied, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C. The amplification factor of the column amplifier 301 remains the first amplification factor, which is 4 times.

[0141] Next, in determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2. As described above, since the relationship between the first voltage value and the second voltage value satisfies VREF1<VREF2, AMPOUT inevitably becomes smaller than VREF2. The second determination value J2 is held as "1" in the first bit of the determination value memory 305C.

[0142] Then, at time t415 in the S signal acquisition period, based on the second determination value J2=1 held in the second bit of the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_M to the comparator 303, and the AD conversion sensitivity is doubled.

[0143] Thus, under "Setting E", the ramp signal VRAMP_M that doubles the AD conversion sensitivity is input to the comparator 303 at the first amplification factor that quadruples the amplification factor of the column amplifier 301. That is, S signal acquisition is performed with the S conversion sensitivity set to 4×2=8 times.

[0144] Next, "Setting F" will be described. "Setting F" shows an example in which the signal level of the amplified pixel signal AMPOUT is medium, that is, the pixel is irradiated with light of medium luminance. In determination period 1 , the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. Under "Setting F", AMPOUT>VREF1 is satisfied, and the first determination value J1 is held as "0" in the first bit of the determination value memory 305C. The amplification factor of the column amplifier 301 is switched to the second amplification factor, which is 1 time.

[0145] Next, in determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2.

[0146] In "Setting F", AMPOUT<VREF2 is satisfied, and the second determination value J2 is held as "1" in the second bit of the determination value J in the determination value memory 305C. Then, at time t415 in the S signal acquisition period, based on the first determination value "1" held in the second bit of the determination value J in the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_M to the comparator 303, and the AD conversion sensitivity is doubled.

[0147] In this way, in "Setting F", the ramp signal VRAMP_H that doubles the AD conversion sensitivity is input to the comparator 303 at the first amplification factor at which the amplification factor of the column amplifier 301 is 1 time. That is, S signal acquisition is performed with the S conversion sensitivity being 1×2=2 times.

[0148] Finally, regarding "Setting C", since it is the same as Setting C described in the first embodiment, the description thereof is omitted.

[0149] Next, the magnification correction of the S signal in the present embodiment will be described with reference to FIG. 13. The pixel signal PIXOUT shall have an amplitude change up to a maximum voltage value VR2' V]. In the S signal acquisition period, up to the voltage value VR1' which is 1 / 2 of the voltage value VR2'[V], AD conversion is performed with the ramp signal VRAMP_M, and beyond that, AD conversion is performed with the ramp signal VRAMP_H. Up to the voltage value VA1'[V] which is 1 / 4 of the voltage value VR1'[V], the pixel signal PIXOUT is AD-converted at the first amplification factor of the column amplifier 301, and at a pixel signal level higher than that, AD conversion is performed at the second amplification factor.

[0150] When the pixel signal PIXOUT is a voltage value VA1'[V], the AD conversion value DA1'[LSB] is obtained in “Setting E”. The AD conversion value DA1'[LSB] is the maximum value counted by the counter circuit 106 during the period from time t415 to time t417. On the other hand, when the pixel signal PIXOUT is a voltage value VR1'[V] which is four times the voltage value VR1[V], the AD conversion value DA1'[LSB] is also obtained in “Setting F”. Furthermore, when the pixel signal PIXOUT is a voltage value VR2'[V] which is 4 × 2 = 8 times the voltage value VA1'[V], the AD conversion value DA1'[LSB] is also obtained in “Setting C”. The S signals acquired with these different settings are magnified based on the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C.

[0151] If the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C are J1 = "1" and J2 = "1", respectively, the S signal is not corrected. This applies to the range of the pixel signal PIXOUT from voltage value 0[V] to voltage value VA1'[V] (thick line).

[0152] When the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C are J1="0" and J2="1", respectively, the S signal undergoes a 4x magnification correction. This applies to the range of voltage value VA1'[V] to voltage value VR1'[V] for the pixel signal PIXOUT. The S signal before correction (dotted line) is magnified and becomes the 4x multiplied S signal (thick dotted line). Here, the pixel signal PIXOUT switches between "Setting E" and "Setting F" at the voltage value VA1'[V]. The voltage value VA1'[V] corresponds to the first threshold voltage value VREF1 when converted to the amplified pixel signal AMPOUT from the column amplifier 301 at the first amplification factor (x4). Also, the pixel signal PIXOUT switches between "setting F" and "setting C" at the voltage value VR1'[V]. The output where the pixel signal PIXOUT has a voltage value VR1'[V] corresponds to the second threshold voltage value VREF2 when converted to the amplified pixel signal AMPOUT at the second amplification factor (x1).

[0153] If the first judgment value J1 and the second judgment value J2 held in the judgment value memory 305C are J1 = "0" and J2 = "0", respectively, the S signal undergoes an 8x magnification correction. This applies to the range of the pixel signal PIXOUT from voltage value VR1'[V] to voltage value VR2'[V], and the S signal before correction (dotted line) becomes the 8x multiplied S signal (thick dotted line). In this way, the S signal obtained for each setting is subjected to magnification correction processing based on the judgment value. The calculation of the ratio error between the amplification factor of the column amplifier 301 and the voltage change rate of the lamp signal, and the method of obtaining the correction value are the same as in other embodiments, so they are omitted.

[0154] In summary, even if the selection operation of the column amplifier's amplification factor is performed first during the S signal acquisition period in the judgment period, by setting the first threshold voltage value VREF1 to less than or equal to the second threshold voltage value VREF2, transitions to unnecessary settings can be suppressed. Therefore, it is possible to achieve an expanded dynamic range and high speed, while also obtaining good signal characteristics.

[0155] <Fourth Embodiment> The photoelectric converter in the fourth embodiment will be described with reference to Figures 14 to 19. In this embodiment, four lamp signals are input to the lamp signal switching circuit 304, and three of these lamp signals are used to set the amplification factor of the AD conversion.

[0156] There are three possible settings for the ramp signal when acquiring the S signal, and two possible settings for the gain of the column amplifier, resulting in 3 × 2 = 6 possible combinations. However, as explained in other embodiments, in this example, four settings are used for AD conversion of the amplified pixel signal to prevent these two settings from switching simultaneously. This suppresses output errors at the setting switching points and achieves good output characteristics.

[0157] First, the configuration of the photoelectric converter of this embodiment will be described. Figure 14 is a block diagram of the column circuit 104 of the photoelectric converter according to this embodiment. As shown in Figure 14, four lamp signals, VRAMP_L, VRAMP_M, VRAMP_H, and VRAMP_J, are input to the lamp signal switching circuit 304. The voltage change rate of each lamp signal is the same as that of the lamp signals with the same names described in the first to third embodiments. That is, lamp signal VRAMP_M has twice the voltage change rate of lamp signal VRAMP_L, and lamp signal VRAMP_H has four times the voltage change rate. The judgment value memory 305C is 3 bits and can hold three judgment result values. The other components are the same as in the first embodiment, so their description will be omitted.

[0158] Next, we will explain how to acquire the N signal, decision value, and S signal by AD conversion in the column circuit 104. Figure 15 is a timing chart illustrating the AD conversion operation in the column amplifier. The operation during the N signal acquisition period is the same as in other embodiments and will therefore be omitted.

[0159] This section explains how to obtain the judgment value during the judgment period. The period from time t407 to time t414 is the judgment period, and this is the period during which the judgment value is obtained.

[0160] First, the first determination value J1 is obtained during the period from time t407 to time t411A, but the method is the same as in the first embodiment, so the explanation will be omitted. The first determination value J1 is J1=0, and "0" is stored in the first bit of the determination value memory 305C.

[0161] Furthermore, a second determination value J2 is obtained during the period from time t412 to time t414, but the method is the same as in the first embodiment, so the explanation is omitted. The second determination value J2 becomes "0", and "0" is stored in the second bit of the determination value memory 305C.

[0162] A method for obtaining the third determination value J3, which is a characteristic part of the present embodiment, will be described. The third determination value J3 is obtained during the period from time t411A to time t411B.

[0163] The ramp signal VRAMP_J further increases the voltage value in the period from time t411A to time t410B, and performs an operation of holding the voltage value for a certain period from time t410B to time t411B. At this time, the voltage value held between time t410B and time t411B is defined as a third threshold voltage value VREF3, and the same period is defined as determination period 3. At this time, the first threshold voltage value VREF1 and the third threshold voltage value VREF3 satisfy the following relationship. VREF1<VREF3 (Equation-14)

[0164] In addition, for the purpose of securing the inversion period of the comparison signal COMPRES for obtaining a correct AD conversion value in the S signal acquisition period, which was described in the first embodiment, the third threshold voltage value VREF3 and the second voltage value satisfy the following relationship. VREF3<VREF2 (Equation-15)

[0165] The threshold voltage value for determining the amplification factor of the column amplifier 301 is larger than the maximum value of the plurality of threshold voltages for determining the voltage change rate of the ramp signal. In the determination period 3, the comparator 303 compares the third threshold voltage value VREF3 with the amplified pixel signal AMPOUT, and the output comparison result signal becomes the third determination value J3. The third determination value J3 is input to and held in the 3rd bit of the determination value memory 305C. After time t411B, the ramp signal VRAMP is reset. In the case of FIG. 15, since the amplified pixel signal AMPOUT is larger than the third threshold voltage value VREF3, the third determination value J3 is "0", and "0" is held in the 3rd bit of the determination value memory 305C.

[0166] The period from time t414 to time t417 is the S signal acquisition period. The setting of the amplification factor of the column amplifier is the same as in the first embodiment, so the explanation will be omitted. The selection of the ramp signal to be input to the comparator 303 will be explained. The selection circuit 306 selects the ramp signal based on the first determination value J1 and the third determination value J3 held in the determination value memory 305C. A control signal is sent to the lamp signal switching circuit 304. Based on the control signal, the lamp signal switching circuit 304 selects the lamp signal to input to the comparator 303 at time t415.

[0167] In the case of Figure 15, the first determination value J1 held in the determination value memory 305C is "0" and the third determination value J3 is "0". At this time, the selection circuit 306 sends a lamp signal to the comparator 303. A control signal is sent to the lamp signal switching circuit 304 so that the signal VRAMP_H is input. On the other hand, if the first determination value J1 held in the determination value memory 305C is "0" and the third determination value J3 is "1", the selection circuit 306 sends the lamp signal VRAMP_M to the comparator 303. Enter the following: Alternatively, if the first determination value J1 held in the determination value memory 305C is "1" and the third determination value J3 is "1", the selection circuit 306 sends a ramp signal VR to the comparator 303. Enter AMP_L. The state where the first judgment value J1 is "0" and the third judgment value J3 is "1" is impossible and therefore not considered.

[0168] At time t415, the ramp signal input to comparator 303 begins to change output at a constant rate of change. The counter circuit 106 starts counting the clock pulse signal in synchronization with the change in the ramp signal output. In the example in Figure 15, at time t415, the ramp signal VRAMP_H is input to comparator 303. At time t416, the voltage of the ramp signal VRAMP_H is amplified. When the pixel signal AMPOUT is exceeded, the signal polarity of the comparison result signal COMPOUT output by the comparator 303 changes. The S memory 305B holds the value of the count signal CNT at time t416 as the S signal. From time t417 onward, the ramp signal VRAMP and the count signal CNT are reset and initialized.

[0169] The above is the AD conversion performed by the column circuit 104 in the present embodiment. Next, the setting of the combination of the amplification factor of the column amplifier and the signal change rate of the ramp signal in the present embodiment will be described. Figure 16 is a flowchart for explaining S conversion sensitivity in the present embodiment.

[0170] Since there are three types of ramp signal settings and two types of amplification factor settings for the column amplifier, there can be 3×2=6 possible combinations of settings. However, as described in other embodiments, in order to prevent these two settings from being switched at the same time during setting switching, four settings are used in this example to perform AD conversion of the amplified pixel signal.

[0171] The following points are common to the four configurable settings. First, the amplification factor of the column amplifier 301 is set to 4 times, which is the first amplification factor. Further, the ramp signal VRAMP_L is input from the ramp signal switching circuit 304 to the comparator 303. Under this condition, N signal acquisition is performed. Hereinafter, the differences between the four settings will be respectively described.

[0172] First, "Setting A" will be described. "Setting A" shows an example where the signal level of the amplified pixel signal AMPOUT is low, that is, the pixel is irradiated with low-luminance light. In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting A", AMPOUT<VREF1 holds, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C. Next, in determination period 3, the amplified pixel signal AMPOUT including the image signal is compared with the third threshold voltage value VREF3. At this time, since the relationship between the first threshold voltage value VREF1 and the third threshold voltage value VREF3 is VREF1<VREF3, AMPOUT<VREF3 is inevitably satisfied. The third determination value J3 is held as "1" in the third bit of the determination value memory 305C. Similarly, "1" is also held for the second determination value . The amplification factor of the column amplifier 301 is not changed.

[0173] Then, at time t415 in the S signal acquisition period, based on the first determination value J1 (=1) and the third determination value J3 (=1) in the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303, so that the AD conversion sensitivity becomes 4 times. Thus, in "Setting A", the ramp signal VRAMP_M with AD conversion sensitivity of 4 times is input to the comparator 303 at the first amplification factor at which the amplification factor of the column amplifier 301 is 4 times. That is, S signal acquisition is performed with the S conversion sensitivity being 4×4=16 times.

[0174] Next, "Setting E" will be described. "Setting E" shows an example where the signal level of the amplified pixel signal AMPOUT is a medium level that is relatively low, that is, the pixels are irradiated with medium light that is closer to low luminance. In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting E", AMPOUT≧VREF1 is satisfied, and the first determination value J1 is held as "0" in the first bit of the determination value memory 305C.

[0175] Next, in determination period 3, in "Setting E", AMPOUT<VREF3 is satisfied. The third determination value J3 is held as "1" in the third bit of the determination value memory 305C. For the second determina tion value, "1" is similarly held. The amplification factor of the column amplifier 301 is not changed. Then, at time t415 in the S signal acquisition period, based on the first determination value J1 (=0) and the third determination value J3 (=1) in the determination value memory 305C, the selection circuit 306 sends the ramp signal switching circuit 304 a control signal. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_M to the comparator 303, so that the AD conversion sensitivity becomes 2 times. Thus, in "Setting E", the ramp signal VRAMP_M with AD conversion sensitivity of 2 times is input to the comparator 303 at the first amplification factor at which the amplification factor of the column amplifier 301 is 4 times. That is, S signal acquisition is performed with the S conversion sensitivity being 4×2=8 times.

[0176] Next, "Setting B" will be described. "Setting B" shows an example in which the signal level of the amplified pixel signal AMPOUT is a moderately high level, that is, the pixel is irradiated with moderate light that is closer to high luminance.

[0177] In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting B", AMPOUT≧VREF1 is satisfied, and the first determination value J1 is held as "0" in the first bit of the determination value memory 305C.

[0178] Next, in determination period 3, in "Setting B", AMPOUT≧VREF3 is satisfied. The third determination value J3 is held as "0" in the third bit of the determination value memory 305C.

[0179] Next, in determination period 2, in "Setting B", AMPOUT<VREF2 is satisfied. "1" is held as the second determination value. The amplification factor of the column amplifier 301 is not changed. Then, at time t415 in the S signal acquisition period, based on the first determination value J1 (=0) and the third determination value J3 (=0) in the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1 time. In this way, in "Setting B", the ramp signal VRAMP_H with the AD conversion sensitivity of 1 time is input to the comparator 303 at the first amplification factor at which the amplification factor of the column amplifier 301 is 4 times. That is, S signal acquisition is performed with the S conversion sensitivity of 4×1=4 times.

[0180] Finally, "Setting C" will be described. "Setting C" shows an example in which the signal level of the amplified pixel signal AMPOUT is high, that is, the pixel is irradiated with high-luminance light.

[0181] In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting C", AMPOUT≧VREF1 is satisfied, and the first determination value J1 is held as "0" in the first bit of the determination value memory 305C.

[0182] Next, during judgment period 3, in "Setting C", AMPOUT ≥ VREF3. The third judgment value J3 is stored as "0" in the 3rd bit of judgment value memory 305C.

[0183] Next, during the judgment period 2, in "Setting C", AMPOUT ≥ VREF2. The second judgment value is held as "0". The amplification factor of the column amplifier 301 switches from the first amplification factor to the second amplification factor, becoming 1x. Then, at time t415 of the S signal acquisition period, based on the first judgment value J1 (=0) and the third judgment value J3 (=0) in the judgment value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs the lamp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1x. Thus, in "Setting C", the lamp signal VRAMP_H, which results in an AD conversion sensitivity of 1x, is input to the comparator 303 at the second amplification factor where the amplification factor of the column amplifier 301 is 1x. In other words, the S signal is acquired with an S conversion sensitivity of 1 × 1 = 4x.

[0184] The above describes the state set for the S signal acquisition period in this embodiment. Next, the correction magnification of the S signal will be explained using Figure 17. In this embodiment, setting E is added compared to the first embodiment. The pixel signal PIXOUT receives a magnification correction of 2x in the range of voltage value VR1[V] to voltage value VR2[V]. The additions compared to the first embodiment are the existence of a boundary between "Setting A" and "Setting E" at the point where PIXOUT becomes voltage value VR1[V], and a boundary between "Setting E" and "Setting B" at the point where the pixel signal PIXOUT becomes voltage value VR2[V]. The magnification correction of the S signal obtained in the other patterns shown in the first embodiment is the same process and is therefore omitted.

[0185] Figure 18 illustrates the correction value obtained in the correction value acquisition operation of the photoelectric converter according to this embodiment. Except for the acquisition of the correction value in “Setting E”, it is the same as in the first embodiment, so redundant explanations are omitted. The correction value obtained by inputting the correction operation input value V1 to the column circuit 104 will be explained. The value obtained by AD conversion in “Setting E” will be the correction value D8. Next, the correction value obtained by inputting the correction operation input value V2 to the column circuit 104 will be explained. The value obtained by AD conversion in “Setting E” will be the correction value D9.

[0186] The following describes how to calculate the ratio error of the amplification factor of the column amplifier 301 and the ratio error of the voltage change rate of the ramp signal in this embodiment, using the correction values ​​D1, D2, D3, D4, D5, D6, D7, D8, and D9.

[0187] First, the ratio error of the voltage change rates of the ramp signals VRAMP_L and VRAMP_M is obtained from the ratio of the slope (or difference value) of each line obtained by connecting the correction value D2 and correction value D1 obtained in "Setting A", and the correction value D9 and correction value D8 obtained in "Setting E". This is called the linearity correction value α1. α1=(D2-D1) / (D9-D8) / 2 (Formula-16)

[0188] The linearity of the S signal obtained with "Setting E" is corrected to match the linearity of the signal obtained with "Setting A". In other words, the linearity standard is the linearity of the signal obtained with "Setting A".

[0189] Next, the ratio error of the voltage change rates of the ramp signals VRAMP_M and VRAMP_H is obtained from the ratio of the slopes (or differences) of the lines obtained by connecting the correction values ​​D9 and D8 obtained in "Setting E", and the correction values ​​D4 and D3 obtained in "Setting B". This is called the linearity correction value α2. α2=(D9-D8) / (D4-D3) / 2 (Formula-17)

[0190] The linearity correction value α2 is multiplied by the S signal obtained in "Setting B," correcting the linearity of the S signal obtained in "Setting B" to match the linearity of the signal obtained in "Setting E." In addition, α2 is further multiplied by the S signal to match the linearity of "Setting A."

[0191] Similarly, the ratio error of the amplification factor of the column amplifier 301 is obtained from the ratio of the slopes (or difference values) of the lines obtained by connecting the correction values ​​D5 and D3 obtained in "Setting B", and the correction values ​​D7 and D6 obtained in "Setting C". This is called the linearity correction value α3. α3=(D5-D3) / (D7-D6) / 4 (Formula-18)

[0192] The linearity correction value α3 corrects the linearity of the S signal obtained under "Setting C" to match the linearity of the S signal obtained under "Setting B". However, since it is necessary to match the linearity of "Setting A", the S signal under "Setting C" must also be multiplied by the linearity correction values ​​α1 and α2.

[0193] Next, we will explain the method for calculating the offset amount caused by the setting difference that may occur at the boundary point where the settings switch, and the output value output from the signal processing circuit 109 after correcting for linearity and offset.

[0194] First, let's explain how to calculate the offset correction value β1 that occurs when switching from "Setting A" to "Setting E". The correction value D9 obtained in "Setting E" during the correction value acquisition operation becomes the corrected output 2 × α1 × D9 after magnification correction and linearity correction. If this corrected output is equal to the correction value D2, no offset occurs. In other words, the difference between D2 and 2 × α1 × D9 becomes the offset correction value β1. β1=D2-2×α1×D9 (Formula-19)

[0195] Therefore, the S signal obtained in “Setting E” is corrected by the signal processing circuit 109 and the output signal SB is as follows. SB = 2 × α¹ × S + β¹ - N (Equation -20)

[0196] N is the digital value of the N signal. Next, we will explain how to calculate the offset correction value β2 that occurs when switching from "Setting E" to "Setting B". The correction value D9 obtained in "Setting C" during the correction value acquisition operation becomes a corrected output of 4 × α1 × α2 × D4 after magnification correction and linearity correction. If this corrected output is equal to the corrected output 2 × α1 × D9 obtained by applying magnification correction and linearity correction to the correction value D9, then no offset occurs. In other words, the difference between the corrected outputs becomes the offset correction value β2. β2=2×α1×D9 - 4×α1×α2×D4 (Formula-21)

[0197] Therefore, the signal SC, which is obtained by correcting the S signal in "Setting B" in the signal processing circuit 109 and outputting it, is obtained by subtracting the N signal as follows. SC=4×α1×α2×S+β2-N (Formula-22)

[0198] Finally, we will explain how to calculate the offset correction value β3 that occurs when switching from "Setting B" to "Setting C". The correction value D7 obtained in "Setting C" during the correction value acquisition operation is corrected to a corrected output of 16 × α1 × α2 × α3 × D7 by applying magnification correction and linearity correction. If this corrected output is equal to the corrected output 4 × α1 × α2 × D5 obtained by applying magnification correction and linearity correction to the correction value D5, then no offset occurs. In other words, the difference between the corrected outputs becomes the offset correction value β2. β2=4×α1×α2×D5-16×α1×α2×α3×D7 (Formula-23)

[0199] Therefore, the signal SD, which is output after the S signal obtained in "Setting C" is corrected by the signal processing circuit 109, is obtained by subtracting the N signal as follows. SD=16×α1×α2×α3×S+β2-N (Formula-24)

[0200] The S signal obtained in "Setting A" is not subjected to correction processing by the signal processing circuit 109, and the output from the signal processing circuit 109 is as follows. SA = SN (Equation -25)

[0201] In this way, by correcting the S signal using the linearity correction values ​​α1, α2, and α3 obtained through the correction operation, and the offset correction values ​​β1, β2, and β3, it is possible to obtain a signal that exhibits good linearity characteristics with respect to the amount of incident light.

[0202] Next, we will explain how to obtain correction values ​​during the imaging process. Figure 19 illustrates the method for outputting correction values ​​in the photoelectric converter according to this embodiment. Here, the time required to read out one row of pixels 101 arranged on the matrix is ​​defined as 1H. Figure 19 shows the correction operation input value input to the column circuit 104, the voltage change rate of the lamp signal, and the setting state of the amplification factor of the column amplifier in 1H time units over time. The positive values ​​are generated by sequentially switching the correction operation input value, the amplification factor of the column amplifier, and the voltage change rate of the ramp signal using the readout time for 10 rows from 1H to 10H, outputting correction values ​​D1, D2, D3, D4, D5, D6, D7, D8, and D9 for each row. This operation is best performed using rows consisting of non-photosensitive pixels that are not used for imaging, such as optical black rows.

[0203] The following describes the correction value acquisition process up to time 6H, as shown in Figure 19(a). During the correction value acquisition operation, the correction value D1 is acquired from time 0 to time 1H. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with setting "Setting A". The S signal of the row output during this period will be the correction value D1.

[0204] From time 1H to time 2H, the correction value D8 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with the setting "Setting E". The S signal of the row output during this period will have the correction value D8.

[0205] From time 2H to time 3H, the correction value D3 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with setting "Setting B". The S signal of the row output during this period will have the correction value D3.

[0206] From time 3H to time 4H, the correction value D2 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with setting "Setting A". The S signal of the row output during this period will then be the correction value D2.

[0207] From time 4H to time 5H, the correction value D9 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with the setting "Setting E". The S signal of the row output during this period will have the correction value D9.

[0208] From time 5H to time 6H, the correction value D4 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with setting "Setting B". The S signal of the row output during this period will have the correction value D4.

[0209] The following describes the correction value acquisition operation from time 6H to time 10H, as shown in Figure 19(b).

[0210] The period from time 6H to time 7H is the same as the period from time 2H to time 3H, and the correction value D3 is output. The measurement is performed considering the symmetry of the time series. From time 7H to time 8H, the correction value D6 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with the setting "Setting C". The S signal of the row output during this period will have the correction value D6.

[0211] From time 8H to time 9H, the correction value D5 is acquired. During this period, the correction operation input value V3 is input, and the column circuit 104 performs AD conversion with the setting "Setting B". The S signal of the row output during this period will have the correction value D5.

[0212] From time 9H to time 10H, the correction value D7 is acquired. During this period, the correction operation input value V3 is input, and the column circuit 104 performs AD conversion with the setting "Setting C". The S signal of the row output during this period becomes the correction value D7. The correction values ​​D1, D2, D3, D4, D5, D6, D7, D8, and D9 obtained over a period of 10H are input to the signal processing circuit 109 and used in the correction process explained using Figure 7.

[0213] In this embodiment, the threshold voltage value that determines the rate of change of the lamp signal voltage during the determination period is multiplied. An example of multi-stage configuration to increase the configurable AD conversion sensitivity was shown. This is not the only example; the amplification factor of a column amplifier could also be multi-stage. The threshold voltage determining the rate of change of the ramp signal was also set in a stepped manner, but the ramp signal could be reset and set each time.

[0214] In the embodiments described above, a comparator 303, which is a comparison circuit, is shown to perform a comparison between a threshold voltage value that determines the voltage change rate of the lamp signal and the pixel signal, and a comparison between a threshold voltage value that determines the setting state of the amplification factor of the column amplifier and the pixel signal. The embodiment is not limited to this form, and a determination circuit provided separately from the comparator 303 may perform these functions. This determination circuit only needs to be provided with a comparison circuit that compares the pixel signal with the threshold voltage value and outputs a determination value corresponding to a first signal that indicates the comparison result and a determination value corresponding to a second signal.

[0215] Furthermore, while the embodiments described above show a ramp signal in which the signal voltage changes in a slope-like manner, the ramp signal is not limited to this form. For example, the signal voltage may change in a step-like manner, and such a form is also included in ramp signals that change at a predetermined rate of change. Also, the rate of change of the ramp signal does not always have to be constant. For example, the signal voltage of the ramp signal may change at a relatively small rate of change at the start of the change, and after a predetermined period of time, the signal voltage of the ramp signal may change at a relatively large rate of change.

[0216] Furthermore, in the embodiments described above, a column circuit 104 was provided for one row of pixels 101, but this correspondence is not limited to this. In other words, multiple column circuits 104 may be provided for one row of pixels 101, or one column circuit 104 may be provided for multiple rows of pixels 101.

[0217] Furthermore, the photoelectric conversion devices of each embodiment described above can be applied to stacked sensors formed by stacking multiple substrates, or to single-layer sensors in which the components shown in Figure 1 are arranged on a single substrate. In the case of stacked sensors, how the components shown in Figure 1 are arranged on multiple substrates can be designed as appropriate. For example, when stacking two substrates, an array of pixels 101 arranged in multiple rows and columns can be placed on the first substrate, and the components other than the array shown in Figure 1 can be placed on the second substrate. When stacking three substrates, the photodiode 201 and transfer MOS transistor 202 of the pixel 101 configuration can be placed on the first substrate, and the other components of the pixel 101 can be placed on the second substrate. Then, the components other than the array of pixels 101 arranged in multiple rows and columns can be placed on the third substrate. This arrangement is just one example and can be changed as appropriate. For example, an array of pixels 101 arranged in multiple rows and columns may be placed on the first substrate, and components other than the array shown in Figure 1 may be placed on the second substrate. A memory array for holding signals (e.g., DRAM) and an arithmetic unit for processing signals (which may have machine learning capabilities) may be placed on the third substrate. The stacked sensor may also be a sensor in which even more substrates are stacked.

[0218] The following describes the photoelectric conversion system, mobile unit, and equipment of the embodiment.

[0219] <Fifth Embodiment> The photoelectric conversion system according to this embodiment will be described with reference to Figure 20. Figure 20 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0220] The photoelectric conversion devices described in the first to fourth embodiments are applicable to various photoelectric conversion systems. A photoelectric conversion system comprises at least the photoelectric conversion device according to the above embodiment and a signal processing unit that processes the signal output from the photoelectric conversion device. Examples of devices to which such a photoelectric conversion system can be applied include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, sensors, measuring instruments, etc. These include camera modules, which are equipped with optical systems such as lenses and photoelectric conversion devices, as well as other devices that utilize photoelectric conversion systems. Figure 9 shows a block diagram of a digital still camera as an example of these.

[0221] The photoelectric conversion system illustrated in Figure 9 includes an imaging device 2504 to which the photoelectric conversion device of each embodiment described above is applied, and a lens 2502 that forms an optical image of a subject onto the imaging device 2504. The photoelectric conversion system also includes an aperture 2503 for varying the amount of light passing through the lens 2502, and a barrier 2501 for protecting the lens 2502. The lens 2502 and aperture 2503 are an optical system that focuses light onto the imaging device 2504. The imaging device 2504 is a photoelectric conversion device of any of the embodiments described above, which converts the optical image formed by the lens 2502 into an electrical signal.

[0222] The photoelectric conversion system also includes a signal processing unit 2507, which is an image generation unit that generates an image by processing the output signal output from the imaging device 2504. The signal processing unit 2507 performs various corrections and compressions as needed and outputs the image data. The signal processing unit 2507 may be formed on the semiconductor substrate on which the imaging device 2504 is mounted, or it may be formed on a semiconductor substrate separate from the imaging device 2504. Alternatively, the imaging device 2504 and the signal processing unit 2507 may be formed on the same semiconductor substrate.

[0223] The photoelectric conversion system further includes a memory unit 2510 for temporarily storing image data, and an external interface unit (external I / F unit) 2513 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system includes a recording medium 2512 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 2511 for recording or reading data from the recording medium 2512. The recording medium 2512 may be built into the photoelectric conversion system or may be detachable.

[0224] Furthermore, the photoelectric conversion system includes an overall control and calculation unit 2509 that controls various calculations and the entire digital still camera, and a timing generation unit 2508 that outputs various timing signals to the imaging device 2504 and the signal processing unit 2507. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system only needs to have at least an imaging device 2504 and a signal processing unit 2507 that processes the output signals output from the imaging device 2504.

[0225] The imaging device 2504 outputs the imaging signal to the signal processing unit 2507. The signal processing unit 2507 performs predetermined signal processing on the imaging signal output from the imaging device 2504 and outputs image data. The signal processing unit 2507 generates an image using the imaging signal.

[0226] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying any of the photoelectric conversion devices of the first to fourth embodiments described above.

[0227] <Fourth Embodiment> The photoelectric conversion system and mobile body of this embodiment will be described using Figures 21(A) and 21(B). Figure 21(A) is a diagram showing the configuration of the photoelectric conversion system of this embodiment, and Figure 21(B) is a diagram showing the configuration of the mobile body of this embodiment.

[0228] Figure 21(A) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 2600 includes an imaging device 2610. The imaging device 2610 is the photoelectric conversion device described in any of the first to fourth embodiments above. The photoelectric conversion system 2600 includes an image processing unit 2612 that performs image processing on a plurality of image data acquired by the imaging device 2610. The photoelectric conversion system 2600 also calculates the distance to the target object. The system includes a distance acquisition unit 2616 and a collision determination unit 2618 that determines whether a collision is possible based on the calculated distance. Here, the distance acquisition unit 2616 may acquire distance information to a Time of Flight (ToF) object, or it may acquire distance information using parallax information, etc. That is, distance information is information related to parallax, defocus amount, distance to object, etc. The collision determination unit 2618 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc., or by a combination thereof.

[0229] The photoelectric conversion system 2600 is connected to the vehicle information acquisition device 2620 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2600 is also connected to the ECU 2630, which is a control unit that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 2618. The photoelectric conversion system 2600 is also connected to the warning device 2640, which issues a warning to the driver based on the judgment result of the collision judgment unit 2618. For example, if the collision judgment unit 2618 determines that there is a high probability of collision, the ECU 2630 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 2640 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0230] In this embodiment, the photoelectric conversion system 2600 images the area around the vehicle, for example, in front of or behind it. Figure 21(B) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 2650). The vehicle information acquisition device 2620 sends instructions to the photoelectric conversion system 2600 or the imaging device 2610. This configuration can further improve the accuracy of distance measurement.

[0231] The above example describes control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or control systems that automatically stay within their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as automobiles, but also to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. This mobile body mainly includes a drive force generation unit that generates the driving force used for the movement of the mobile body, and one or both of the rotating body mainly used for the movement of the mobile body. The drive force generation unit can be an engine, motor, etc. The rotating body can be a tire, wheel, ship's propeller, aircraft propeller, etc. In addition, it can be applied not only to mobile bodies, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0232] <Seventh Embodiment> The photoelectric conversion system of this embodiment will be described with reference to Figure 22. Figure 22 is a block diagram showing an example configuration of a distance image sensor, which is the photoelectric conversion system of this embodiment.

[0233] As shown in Figure 22, the distance image sensor 2701 is comprised of an optical system 2707, a photoelectric converter 2708, an image processing circuit 2704, a monitor 2705, and a memory 2706. The distance image sensor 2701 receives light (modulated light or pulsed light) that is projected from the light source device 2709 toward the subject and reflected from the surface of the subject, thereby acquiring a distance image corresponding to the distance to the subject.

[0234] The optical system 2707 is composed of one or more lenses and guides the image light (incident light) from the subject to the photoelectric converter 2708, and the light-receiving surface (sensor part) of the photoelectric converter 2708 To form an image.

[0235] The photoelectric converter 2708 is one of the photoelectric converters of the first to fourth embodiments described above, and a distance signal indicating the distance obtained from the light received signal output from the photoelectric converter 2708 is supplied to the image processing circuit 2704.

[0236] The image processing circuit 2704 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric converter 2708. The distance image (image data) obtained through this image processing is then supplied to the monitor 2705 for display or supplied to the memory 2706 for storage (recording).

[0237] With the distance image sensor 2701 configured in this way, by applying the photoelectric conversion device described above, the characteristics of the pixels are improved, and for example, more accurate distance images can be acquired.

[0238] (Eighth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Figure 23. Figure 23 is a diagram showing an example of a schematic configuration of an endoscopic surgical system, which is the photoelectric conversion system of this embodiment.

[0239] Figure 23 illustrates a surgeon (physician) 2831 performing surgery on a patient 2832 on a patient bed 2833 using an endoscopic surgical system 2850. As shown in the figure, the endoscopic surgical system 2850 consists of an endoscope 2800, surgical instruments 2810, and a cart 2834 equipped with various devices for endoscopic surgery.

[0240] The endoscope 2800 consists of a barrel 2801, the tip of which is inserted into the body cavity of the patient 2832 for a predetermined length, and a camera head 2802 connected to the proximal end of the barrel 2801. In the illustrated example, the endoscope 2800 is shown as a so-called rigid endoscope having a rigid barrel 2801, but the endoscope 2800 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0241] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 2801. A light source device 2803 is connected to the endoscope 2800. Light generated by the light source device 2803 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 2801, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 2832. The endoscope 2800 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0242] The camera head 2802 contains an optical system and a photoelectric converter. Reflected light from the object being observed (observation light) is focused by the optical system into the photoelectric converter. The photoelectric converter captures the observation light, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The photoelectric converter can be any of the photoelectric converters described in the embodiments described above. The image signal is transmitted as RAW data to the camera control unit (CCU) 2835.

[0243] The CCU 2835 is configured by a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and the like, and integrally controls the operations of the endoscope 2800 and the display device 2836. Further, the CCU 2835 receives an image signal from the camera head 2802, and performs various image processes for displaying an image based on the image signal, such as development processing (demosaicing processing), on the image signal .

[0244] The display device 2836 displays an image based on the image signal that has been subjected to the image processing by the CCU 2835 under the control of the CCU 2835.

[0245] The light source device 2803 is configured by a light source such as an LED (Light Emitting Diode), and supplies irradiation light for imaging a surgical site or the like to the endoscope 2800.

[0246] The input device 2837 is an input interface for the endoscopic surgery system 2850. A user can input various types of information and input instructions to the endoscopic surgery system 2850 via the input device 2837.

[0247] The treatment instrument control device 2838 controls driving of the energy treatment instrument 2812 for cauterization and incision of tissue, sealing of blood vessels, or the like.

[0248] The light source device 2803 that supplies irradiation light for imaging a surgical site to the endoscope 2800 can be composed of a white light source configured by, for example, an LED, a laser light source, or a combination thereof. When a white light source is configured by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the light source device 2803 can adjust the white balance of the captured image. In this case, it is also possible to time-divisionally irradiate the observation target with laser light from each of the RGB laser light sources, and control the driving of the image sensor of the camera head 2802 in synchronization with the irradiation timing, so as to capture images corresponding to each of RGB in a time-division manner. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0249] Further, the driving of the light source device 2803 may be controlled so as to change the intensity of the output light every predetermined time. By controlling the driving of the image sensor of the camera head 2802 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and synthesizing the images, a so-called high dynamic range image without crushed blacks and blown-out highlights can be generated.

[0250] Further, the light source device 2803 may be configured to be capable of supplying light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissues is utilized. Specifically, by irradiating light with a narrower band than the irradiation light during normal observation (that is, white light), predetermined tissues such as blood vessels in the surface layer of the mucous membrane are imaged with high contrast. Alternatively, in the special light observation, fluorescence observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light. In fluorescence observation, it is possible to irradiate a body tissue with excitation light to observe fluorescence from the body tissue, or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 2803 can be configured to be capable of supplying narrowband light and / or excitation light corresponding to such special light observation.

[0251] <Ninth Embodiment> The photoelectric conversion system of this embodiment will be described using Figures 24(A) and 24(B). Figure 24(A) illustrates the eyeglasses 2900 (smart glasses), which are the photoelectric conversion system of this embodiment. The eyeglasses 2900 have a photoelectric conversion device 2902. The photoelectric conversion device 2902 is the photoelectric conversion device described in the first to fourth embodiments above. In addition, a display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 2901. There may be one or more photoelectric conversion devices 2902. In addition, multiple types of photoelectric conversion devices may be used in combination. The arrangement position of the photoelectric conversion device 2902 is limited to that shown in Figure 24(A). do not have.

[0252] The eyeglasses 2900 further include a control device 2903. The control device 2903 functions as a power source that supplies power to the photoelectric converter 2902 and the display device. The control device 2903 also controls the operation of the photoelectric converter 2902 and the display device. The lens 2901 has an optical system formed therein for focusing light onto the photoelectric converter 2902.

[0253] Figure 24(B) illustrates a pair of glasses 2910 (smart glasses) relating to one application example. The glasses 2910 have a control device 2912, which is equipped with a photoelectric converter corresponding to a photoelectric converter 2902 and a display device. The lens 2911 has an optical system formed therein for projecting light emitted from the photoelectric converter in the control device 2912 and from the display device, and an image is projected onto the lens 2911. The control device 2912 functions as a power supply that provides power to the photoelectric converter and the display device, and also controls the operation of the photoelectric converter and the display device. The control device may have a gaze detection unit that detects the wearer's gaze. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light towards the eyeball of the user who is fixating on the displayed image. An imaging unit having a light-receiving element detects the reflected light from the eyeball of the emitted infrared light, thereby obtaining an image of the eyeball. By having a reduction means that reduces the light from the infrared light emitter to the display unit in planar view, the deterioration of image quality is reduced.

[0254] The user's gaze towards the displayed image is detected from an image of the eyeball obtained by imaging with infrared light. Any known method can be applied to gaze detection using an image of the eyeball. For example, a gaze detection method based on the Purkinje image obtained by the reflection of the irradiated light from the cornea can be used.

[0255] More specifically, gaze detection processing is performed based on the pupil-corneal reflection method. Using the pupil-corneal reflection method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the pupil image and Purkinje image contained in the captured image of the eyeball, thereby detecting the user's gaze.

[0256] The display device of this embodiment includes a photoelectric converter having a light-receiving element, and may control the display image of the display device based on the user's gaze information from the photoelectric converter.

[0257] Specifically, the display device determines a first field of view that the user is fixated on, and a second field of view that is not the first field of view, based on gaze information. The first and second field of view may be determined by the control device of the display device, or they may be determined by an external control device and received by the display device. Within the display area of ​​the display device, the display resolution of the first field of view may be controlled to be higher than that of the second field of view. In other words, the resolution of the second field of view may be lower than that of the first field of view.

[0258] Furthermore, the display area may have a first display area and a second display area different from the first display area, and a higher priority area may be determined from the first and second display areas based on gaze information. The first and second display areas may be determined by the control device of the display device, or they may be determined by an external control device and received. The resolution of the higher priority area may be controlled to be higher than the resolution of the areas other than the higher priority area. In other words, the resolution of areas with relatively lower priority may be set lower.

[0259] AI may be used to determine the first field of view area and the areas with higher priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to the target object at the end of the line of sight from the image of the eye, using the image of the eye and the direction the eye was actually looking in that image as training data. The AI ​​program may be installed in the display device, the photoelectric converter, or an external device. If installed in an external device, it will be transmitted to the display device via communication.

[0260] When display control is based on visual detection, this method is preferably applicable to smart glasses that further include a photoelectric converter for capturing images of the surrounding environment. The smart glasses can display the captured external information in real time.

[0261] <Tenth Embodiment> The photoelectric conversion device and photoelectric conversion system described above may be applied to electronic devices such as smartphones and tablets.

[0262] Figures 25(A) and 25(B) show an example of an electronic device 3000 equipped with a photoelectric converter. Figure 25(A) shows the front side of the electronic device 3000, and Figure 25(B) shows the back side of the electronic device 3000.

[0263] As shown in Figure 25(A), a display 3010 for displaying images is positioned in the center of the surface of the electronic device 3000. Along the top edge of the surface of the electronic device 3000, front cameras 3021 and 3022, which use photoelectric converters, an IR light source 3030 that emits infrared light, and a visible light source 3040 that emits visible light are positioned.

[0264] Furthermore, as shown in Figure 25(B), rear cameras 3051 and 3052, which use photoelectric converters, an IR light source 3060 that emits infrared light, and a visible light source 3070 that emits visible light are arranged along the upper edge of the back of the electronic device 3000.

[0265] In the electronic apparatus 3000 configured as described above, by applying the photoelectric conversion device according to any one of the first to fourth embodiments described above, for example, a higher-quality image can be captured. In addition, the photoelectric conversion device can also be applied to other electronic apparatuses such as infrared sensors, ranging sensors using active infrared light sources, security cameras, and personal or biometric authentication cameras. Thereby, the accuracy, performance and the like of these electronic apparatuses can be improved.

[0266] <Eleventh Embodiment> A photoelectric conversion system according to the eleventh embodiment will be described with reference to Figure 26. Figure 26 is a block diagram showing a schematic configuration of a photoelectric conversion system SYS which is the photoelectric conversion system according to the eleventh embodiment. The photoelectric conversion system SYS at least includes the photoelectric conversion device according to any one of the first to fourth embodiments described above, and a signal processing unit that processes a signal output from the photoelectric conversion device.

[0267] The photoelectric conversion system SYS is a camera or an information terminal having an imaging function. The photoelectric conversion system SYS is constructed using the photoelectric conversion device IS. The photoelectric conversion device IS can further include a package PKG that accommodates the imaging device IC. The package PKG can include a base body to which the imaging device IC is fixed, and a lid body facing the imaging device IC. The package PKG can include a connection member (a member that connects a terminal provided on the base body and a terminal provided on the imaging device IC). The photoelectric conversion device IS can also mount a plurality of imaging devices IC side by side in the common package PKG. In addition, the photoelectric conversion device IS can also mount the imaging device IC and another semiconductor device IC in a stacked manner in the common package PKG.

[0268] The photoelectric conversion system SYS can include an optical system OU (optical apparatus) that forms an image on the photoelectric conversion device IS. In addition, the photoelectric conversion system SYS can include at least any one of a control apparatus CU, a processing apparatus PU, a display apparatus DU, and a storage apparatus MU. The control apparatus CU controls the photoelectric conversion device IS, and the processing apparatus PU processes a signal obtained from the photoelectric conversion device IS. In addition, the display appa The DU displays the image obtained from the photoelectric converter IS, and the memory device MU stores the image obtained from the photoelectric converter IS.

[0269] (others) Although various devices have been described in the above embodiments, further mechanical devices may be included. In a camera, the mechanical device can drive components of the optical system for zooming, focusing, and shutter operation. Alternatively, the mechanical device in a camera can move a photoelectric converter for vibration damping.

[0270] Furthermore, the equipment may be transportation equipment such as vehicles, ships, or aircraft. Mechanical devices in transportation equipment can be used as moving devices. Equipment as transportation equipment is suitable for transporting photoelectric converters or for assisting and / or automating driving (piloting) through imaging functions. Processing devices for assisting and / or automating driving (piloting) can perform processing to operate mechanical devices as moving devices based on information obtained from the photoelectric converter.

[0271] The embodiments described above may be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only those described herein, but also all matters that can be understood from this specification and the drawings attached thereto.

[0272] This embodiment includes the following configuration. (Composition 1) The system includes an AD conversion unit that performs analog-to-digital conversion to obtain a digital value corresponding to the pixel signal, using a pixel that outputs a pixel signal and a ramp signal whose signal voltage changes with respect to time at a predetermined rate of voltage change. The AD conversion unit includes an amplification circuit for controlling the amplification ratio of the pixel signal, an amplification ratio switching circuit for switching the amplification ratio, a lamp signal switching circuit for switching the voltage change rate of the lamp signal, a comparison circuit for outputting a comparison result signal generated from the amplified pixel signal output from the amplification circuit and the lamp signal, and a memory unit for holding a plurality of judgment values ​​corresponding to the comparison result signal. A first signal is generated by comparing the amplified pixel signal with one first threshold voltage value selected from M-1 (M>1) threshold voltages, and the lamp signal switching circuit can switch the voltage change rate of the lamp signal in M ​​ways based on a first determination value corresponding to the first signal. A second signal is generated by comparing the amplified pixel signal with one second threshold voltage value selected from N-1 (N>1) threshold voltages generated by the lamp signal, and the amplification factor switching circuit can switch the amplification factor of the amplification circuit in N ways based on a second determination value corresponding to the second signal. The photoelectric converter is characterized in that the AD conversion unit performs analog-to-digital conversion using the voltage change rate of the lamp signal and the amplification factor of the amplifier circuit, selected from among three or more combinations that are less than M × N combinations out of the M × N combinations resulting from the switching of the voltage change rate of the lamp signal and the switching of the amplification factor of the amplifier circuit, using the voltage change rate of the lamp signal and the amplification factor of the amplifier circuit, selected using the first determination value and the second determination value. (Configuration 2) The photoelectric conversion device according to configuration 1, characterized in that the first signal and the second signal are generated in that order, and the maximum threshold voltage value included in the first threshold voltage value is smaller than the minimum threshold voltage value included in the second threshold voltage value. (Composition 3) The photoelectric converter according to configuration 1 is characterized in that the second signal and the first signal are generated in that order, and the first determination value is a value set in combination with the second determination value. Place. (Composition 4) The photoelectric conversion device according to configuration 1, characterized in that the second signal and the first signal are generated in that order, and the maximum threshold voltage value included in the second threshold voltage value is smaller than the minimum threshold voltage value included in the first threshold voltage value. (Composition 5) The photoelectric converter according to any one of configurations 1 to 4, characterized in that the memory section holds two or more bits of information. (Composition 6) The aforementioned pixels are arranged across multiple rows and multiple columns, Each of the AD conversion units comprises a plurality of AD conversion units arranged in a corresponding column among the plurality of columns, The pixel signals are output from the multiple rows of pixels to the corresponding AD conversion unit among the multiple AD conversion units, row by row. The photoelectric converter according to any one of configurations 1 to 5, characterized in that, during the period from when the pixel signal output from a pixel in a predetermined row is input to the plurality of AD conversion units until the next pixel signal output from a pixel in another row is input to the plurality of AD conversion units, each of the plurality of AD conversion units performs analog-to-digital conversion of the pixel signal output from the pixel in the predetermined row, using the voltage change rate of the lamp signal and the amplification factor of the amplification circuit, selected from three or more combinations using the first determination value and the second determination value, with a total of M × N combinations. (Composition 7) A photoelectric conversion device as described in any of configurations 1 to 6, A signal processing unit that generates an image using the signal output by the aforementioned photoelectric converter, A photoelectric conversion system characterized by having the following features. (Composition 8) A mobile body comprising a photoelectric conversion device as described in any of configurations 1 to 6, The photoelectric converter has a control unit that controls the movement of the mobile body using the signal output by the photoelectric converter. A mobile body characterized by the following features. (Composition 9) A photoelectric conversion device as described in any of configurations 1 to 6, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the photoelectric converter, and A mechanical device that operates based on information obtained from the aforementioned photoelectric converter, At least one of the above A device characterized by having the following features. [Explanation of Symbols]

[0273] 101 pixels 104 column circuit 301-row amplifier 302 Amplification Factor Switching Circuit 303 Comparison circuit 304 Lamp signal switching circuit 305A N Memory 305B S memory 305C Judgment Value Memory

Claims

1. The system includes an AD conversion unit that performs analog-to-digital conversion to obtain a digital value corresponding to the pixel signal, using a pixel that outputs a pixel signal and a ramp signal whose signal voltage changes with respect to time at a predetermined rate of voltage change. The AD conversion unit includes an amplification circuit for controlling the amplification ratio of the pixel signal, an amplification ratio switching circuit for switching the amplification ratio, a lamp signal switching circuit for switching the voltage change rate of the lamp signal, a comparison circuit for outputting a comparison result signal generated from the amplified pixel signal output from the amplification circuit and the lamp signal, and a memory unit for holding a plurality of judgment values ​​corresponding to the comparison result signal. A first signal is generated by comparing the amplified pixel signal with each of M-1 (M>1) first threshold voltage values, and the lamp signal switching circuit can switch the voltage change rate of the lamp signal according to M based on a first determination value corresponding to the first signal. A second signal is generated by comparing the amplified pixel signal with each of the N-1 (N>1) second threshold voltage values ​​generated by the lamp signal, and the amplification factor switching circuit can switch the amplification factor of the amplification circuit in N ways based on a second determination value corresponding to the second signal. The photoelectric converter is characterized in that the AD conversion unit performs analog-to-digital conversion using the voltage change rate of the lamp signal and the amplification rate of the amplifier circuit, selected from among three or more combinations that are less than M x N combinations out of the M x N combinations resulting from the switching of the voltage change rate of the lamp signal and the switching of the amplification rate of the amplifier circuit, using the first determination value and the second determination value.

2. The photoelectric conversion device according to claim 1, characterized in that the first signal and the second signal are generated in that order, and the maximum threshold voltage value included in the first threshold voltage value is smaller than the minimum threshold voltage value included in the second threshold voltage value.

3. The photoelectric conversion according to claim 1, characterized in that the second signal and the first signal are generated in that order, and the first determination value is a value set in combination with the second determination value. Device.

4. The photoelectric conversion device according to claim 1, characterized in that the second signal and the first signal are generated in that order, and the maximum threshold voltage value included in the second threshold voltage value is smaller than the minimum threshold voltage value included in the first threshold voltage value.

5. The photoelectric converter according to claim 1, characterized in that the memory unit holds two or more bits of information.

6. The aforementioned pixels are arranged across multiple rows and multiple columns, Each is an AD conversion unit, and each has a plurality of AD conversion units arranged in a corresponding column among the plurality of columns, The pixel signals are output from the multiple rows of pixels to the corresponding AD conversion unit among the multiple AD conversion units, row by row. The photoelectric converter according to claim 1, characterized in that, during the period from when the pixel signal output from a pixel in a predetermined row is input to the plurality of AD conversion units until the next pixel signal output from a pixel in another row is input to the plurality of AD conversion units, each of the plurality of AD conversion units performs analog-to-digital conversion of the pixel signal output from the pixel in the predetermined row, using the voltage change rate of the lamp signal and the amplification factor of the amplification circuit, selected from three or more combinations using the first determination value and the second determination value, in a number of combinations less than M × N.

7. A photoelectric conversion device according to any one of claims 1 to 6, A signal processing unit that generates an image using the signal output by the aforementioned photoelectric converter, A photoelectric conversion system characterized by having the following features.

8. A mobile body comprising a photoelectric converter according to any one of claims 1 to 6, The photoelectric converter has a control unit that controls the movement of the mobile body using the signal output by the photoelectric converter. A mobile body characterized by the following features.

9. A photoelectric conversion device according to any one of claims 1 to 6, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the photoelectric converter, and A mechanical device that operates based on information obtained from the aforementioned photoelectric converter, At least one of the above A device characterized by having the following features.

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