Formation of memory dies and logic dies with wafer-on-wafer bonding.

Abstract

Methods, systems, and devices relating to forming wafer-on-wafer bonds between memory and logic dies. A plurality of first metal pads can be formed on a first wafer and a plurality of second metal pads can be formed on a second wafer. A subset of the first metal pads can be bonded to a subset of the second metal pads via a wafer-on-wafer bonding process. Each of a plurality of memory devices on the first wafer can be mated with at least a respective one of a plurality of logic devices on the second wafer. The bonded first and second wafers can be singulated into individual wafer-on-wafer bonded memory and logic dies.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory, and more specifically, to apparatuses and methods associated with forming a memory die and a logic die that have been subjected to wafer-on-wafer bonding.

BACKGROUND ART

[0002] Memory devices are typically provided as semiconductor, integrated circuits embedded in computers or other electronic devices. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to maintain its data, and includes, among others, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when not powered, and includes, among others, NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), as well as resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0003] Memory is also utilized as volatile and non-volatile data storage for various electronic applications, including but not limited to personal computers, portable memory sticks, digital cameras, mobile phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in arrays, and the arrays are used in memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] [Figure 1] Figure 1 shows a block diagram of an apparatus in the form of a system including a memory die and a logic die, in accordance with some embodiments of the present disclosure. [Figure 2A] This is a top view of a memory wafer according to some embodiments of the present disclosure. [Figure 2B] This is a top view of a logic wafer according to some embodiments of the present disclosure. [Figure 2C] These are cross-sections of portions of a wafer-on-wafer bonded memory die and logic die according to some embodiments of the present disclosure. [Figure 2D] The images show portions of the memory die and logic die with a singuled wafer-on-wafer bond according to some embodiments of the present disclosure. [Figure 3] The following are portions of two memory dies and logic dies bonded with wafer-on-wafer bonding, according to some embodiments of the present disclosure. [Figure 4] The stack and logic die portions of the memory die are shown according to some embodiments of this disclosure. [Figure 5] Circuit diagrams of memory dies according to some embodiments of this disclosure are shown. [Figure 6] The following are schematic diagrams of memory banks according to some embodiments of this disclosure. [Figure 7A] Circuit diagrams of sense amplifiers and multiplexers according to some embodiments of the present disclosure are shown. [Figure 7B] The following are schematic diagrams of local input / output (LIO) lines according to some embodiments of the present disclosure. [Figure 8] This is a flowchart corresponding to a method for forming wafer-on-wafer bonded memory dies and logic dies according to some embodiments of the present disclosure. [Figure 9] This is a flowchart corresponding to a method for forming wafer-on-wafer bonded memory dies and logic dies according to some embodiments of the present disclosure. [Figure 10] This is a flowchart corresponding to a method for forming wafer-on-wafer bonded memory dies and logic dies according to some embodiments of the present disclosure. [Figure 11] This is a flowchart corresponding to a method for forming wafer-on-wafer bonded memory dies and logic dies according to some embodiments of the present disclosure. [Figure 12] This is a flowchart corresponding to a method for forming a stack of wafer-on-wafer bonded memory dies and logic dies according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0005] This disclosure includes apparatus and methods relating to the formation of packages including wafer-on-wafer bonded memory devices and logic devices. Inexpensive and energy-efficient logic circuits are proposed, which benefit from being tightly coupled to memory devices. Logic devices may be accelerators. Accelerators that can reside on a logic die may include artificial intelligence accelerators, such as deep learning accelerators (DLAs). As used herein, “resident on” refers to something physically located on a particular component. The term “resident on” is interchangeable herein with other terms such as “deployed on” or “located on.” AI refers to the ability of a machine to improve through “learning,” such as by memorizing patterns and / or examples that can be used to take action at a later time. Deep learning refers to the ability of a device to learn from data provided as examples. Deep learning may be a subset of AI. Neural networks, among other types of networks, can be classified as deep learning. The low-power and low-cost design of deep learning accelerators allows for implementation in Internet of Things (IoT) devices. DLA can process and perform intelligent decisions at runtime. Furthermore, memory devices containing DLA can be deployed in remote locations without cloud or offload capabilities.

[0006] Three-dimensional integrated circuits (3D ICs) are metal-oxide-semiconductor (MOS) ICs manufactured by stacking semiconductor dies and interconnecting them vertically, for example, using through-silicon vias (TSVs) or metal connections. These function as a single device, achieving performance improvements with reduced power consumption and smaller footprint compared to conventional two-dimensional processes. Examples of 3D ICs include, among others, hybrid memory cubes (HMCs) and high-bandwidth memory (HBMs).

[0007] The implementation of AI such as DLA may involve performing a large number of calculations (e.g., thousands of times) in parallel and performing a large number of iterations. The term "in parallel" can be used herein as a synonym for "simultaneously occurring." Signals indicating data can be input to the DLA from a memory device coupled to it. The amount of data that can be input to the DLA in parallel may be a limit to the rate at which the DLA can perform calculations. Therefore, it may be beneficial to increase the amount of data input to the DLA in parallel.

[0008] Some of the aforementioned approaches to increase the amount of data input to the DLA in parallel may include increasing the amount of interconnects (e.g., jumpers) that couple the memory device to the DLA. However, increasing the amount of interconnects requires increasing the size of the memory die on which the memory device resides. Some of the aforementioned approaches may include components such as transistors in the data path on the memory die from the memory device to the DLA.

[0009] Implementing memory devices in which memory dies and logic dies are bonded using wafer-on-wafer bonding can benefit from efficient data transfer between the memory dies and logic dies. Data transfer from the memory die to the logic die may include transferring data from the memory die to a global data bus and transferring data from the global data bus to the logic die. However, data transfer from the global data bus to the logic die can be inefficient.

[0010] Aspects of this disclosure address the aforementioned and other shortcomings of the approaches described herein. Some embodiments of this disclosure involve forming a wafer-on-wafer bond between a first wafer containing memory dies and a second wafer containing logic dies, thereby aligning and coupling at least one of the memory dies with at least one of the logic dies. Such embodiments can increase the bandwidth between the memory dies and the logic dies, which may include DLA. Wafer-on-wafer bonds according to this disclosure do not require an increase in the size of the memory dies or logic dies. Wafer-on-wafer bonds can enable more precisely controlled alignment of memory dies and logic dies than can be achieved through chip-to-chip bonds alone. For example, wafer-on-wafer bonds can enable such precise pitch control as enabling the connection of individual local input / output lines of memory dies to input circuits of logic dies, as will be described in more detail herein.

[0011] In some embodiments, forming a wafer-on-wafer bond may involve arranging a memory die facing a logic die. The facing orientation or arrangement means that both substrates (wafers) are distal to the wafer-on-wafer bond, while the memory die and logic die are proximal to the wafer-on-wafer bond. In some embodiments, forming a wafer-on-wafer bond between the memory die and the logic die may involve forming one or more metallic materials that bond the memory die to the logic die. In at least one embodiment, the wafer-on-wafer bond may consist solely of metallic materials. The data path between the memory die and the logic die provided by the wafer-on-wafer bond may be on-pitch with the memory cells of the memory die.

[0012] As used herein, the singular “a,” “an,” and “the” include singular and plural referents unless the context clearly indicates otherwise. Furthermore, the word “may” is used throughout this application in an allowable sense (i.e., it may, it is possible) rather than an obligatory sense (i.e., it must). The term “include” and its derivatives mean “including, but not limited to.” As used herein, “coupled to” or “coupled with” generally refers to connections between components that may be indirect or direct communication connections (e.g., without intervening components), whether wired or wireless, including electrical, optical, magnetic, and other connections. As used herein, “a number of” may refer to one or more such things. For example, “a number of memory devices” may refer to one or more memory devices. “Plurality” intends two or more.

[0013] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number, and the remaining digits identify an element or component of the drawing. Similar elements or components in different drawings may be identified by using similar digits. For example, 102 may refer to element "02" in Figure 1, and a similar element is called 202 in Figure 2A. Similar elements in the figures may be referred to by hyphens and additional digits or letters. For example, see elements 419-1 and 419-2 in Figure 4. As recognized, elements shown in various embodiments herein may be added, replaced, and / or removed to provide several additional embodiments of the disclosure. Furthermore, as recognized, the proportions and relative sizes of elements provided in the figures are intended to illustrate specific embodiments of the disclosure and should not be construed as limiting.

[0014] Figure 1 shows a block diagram of a device in the form of a system 100 including a memory die 102 and a logic die 104, according to some embodiments of the present disclosure. As used herein, the memory die 102, memory array 110, and / or logic die 104 may also be considered separately as “devices,” for example.

[0015] As shown in Figure 1, system 100 includes a memory die 102 coupled to a logic die 104. The memory die 102 may include an interface (I / F) 112 (e.g., an input / output (IO) (I / F)). System 100 can be coupled to various types of hosts, including personal laptop computers, desktop computers, digital cameras, mobile phones, memory card readers, servers, vehicles, or IoT-enabled devices.

[0016] The logic die 104 may include a logic device such as an AI circuit. The AI circuit may be an AI accelerator, also referred to herein as DLA 117. The DLA 117 may be coupled to the I / O circuit 112, and thus to the data path 114 that is coupled to a memory device such as the memory array 110. In some embodiments, the logic die 104 may be bonded to the memory die 102. In some embodiments, bonding the logic die 104 to the memory die 102 may include bonding the DLA 117 to the memory array 110. The logic die 104 may include a control circuit 118. The control circuit 118 can control the transceiver of the memory die 102 to communicate data from the memory die 102 to the logic die 104 and / or from the logic die 104 to the memory die 102 (for example, through TSVs that couple the memory die to the logic die). The DLA 117 can be coupled to the control circuit 118. In some embodiments, the control circuit 118 can control the DLA 117. For example, the control circuit 118 can provide signals to the control circuit 116 of the memory die 102, a row decoder (not shown), and / or a column decoder (not shown) to direct communication of data from the memory array 110 to the DLA 117. The data can be provided as an input to the DLA 117 and / or as an input to an artificial neural network (ANN) hosted by the DLA 117. The control circuit 118 can provide the output of the DLA 117 and / or the ANN to the I / F 112 and / or store the output in the memory array 110.

[0017] The ANN model can be trained by DLA117, control circuit 118, and / or the host. For example, the host and / or control circuit 118 can train an ANN model that can be provided to DLA117. DLA117 can implement the trained ANN model as directed by control circuit 118. The ANN model can be trained to perform a desired function. Non-limiting examples of embodiments of system 100 include digital signal processors (DSPs), graphics processing units (GPUs), systems on a chip (SoCs), 5G antennas, safety monitoring, biometrics (e.g., facial recognition), data center network switches, autonomous vehicles, hardware accelerators for genomics, protenomics, and / or gene sequencing, augmented virtual reality, blockchain, and streaming devices (providing local processing).

[0018] For clarity, system 100 has been simplified to focus on features particularly relevant to this disclosure. Non-limiting examples of memory arrays 110 include DRAM arrays, SRAM arrays, STT RAM arrays, PCRAM arrays, TRAM arrays, RRAM arrays, NAND flash arrays, NOR flash arrays, and / or 3DXPoint arrays. Memory array 110 may, for example, be referred to herein as a DRAM array. Memory array 110 may include memory cells, which are arranged in rows joined by access lines (which may be referred to herein as word lines or selection lines) and in columns joined by sense lines (which may be referred to herein as digit lines or data lines). Although memory array 110 is shown as a single memory array, memory array 110 may represent multiple memory arrays arranged within a bank of memory die 102.

[0019] Although not specifically illustrated, the memory die 102 may include an address circuit that latches address signals provided through a host interface. With respect to the system 100, a host (not shown) is a device separate from the memory die 102 and the logic die 104, and can be coupled to either or both of the memory die 102 and the logic die 104. The host interface may include, for example, a physical interface using a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combination of data / address / command buses). Such a protocol may be custom or proprietary, or the host interface may employ a standard protocol such as Peripheral Component Interconnect Express (PCIe), Gen-Z interconnect, Cache Coherent Interconnect for Accelerators (CCIX), and the like. The address signals are received and decoded by a row decoder and a column decoder to access the memory array 110. Sensing circuitry can be used to read data from the memory array 110 by sensing changes in voltage and / or current on sense lines. The sensing circuitry can be coupled to the memory array 110. Each of the memory arrays 110 and the corresponding sensing circuitry can constitute a bank of the memory die 102. The sensing circuitry may include, for example, a sense amplifier capable of reading and latching a page (e.g., a row) of data from the memory array 110. The I / F 112 can be used for bidirectional data communication with the logic die 104 along the data path 114. Read / write circuitry can be used to write data to the memory array 110 or read data from the memory array 110. The read / write circuitry may include various drivers, latch circuits, and the like.

[0020] The control circuit 116 of the memory die (e.g., a local controller) can decode signals provided by a host (not shown). Signals from the host may, for example, indicate commands. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 110, including data read operations, data write operations, and data erase operations. In some embodiments, the control circuit 116 is responsible for executing instructions from the host. The control circuit 116 may include a state machine, a sequencer, and / or several other types of control circuits, which may be implemented in the form of hardware, firmware, software, or any combination thereof. Data can be provided to and / or from the logic die 104 via data lines connecting the logic die 104 to the I / F 112.

[0021] According to some of the approaches described herein, after fabricating electronic devices (e.g., memory array 110 and DLA 117) on a first wafer and a second wafer, the first wafer and the second wafer can be diced (e.g., by dicing with a rotary saw blade that cuts along the streets of the first and second wafers) to form a memory die 102 and a logic die 104, respectively. However, according to at least one embodiment of this disclosure, after fabricating devices on the first and second wafers and before dicing, the first wafer and the second wafer can be bonded together by a wafer-on-wafer bonding process. Following the wafer-on-wafer bonding process, the dies (e.g., memory die 102 and logic die 104) can be singulate. As used herein, “singulate” refers to separating a combined unit into individual units. For example, a memory wafer can be bonded to a logic wafer in a face-to-face orientation, meaning that both wafers (substrates) are distal to the bond area, while the memory dies and logic dies are proximal to the bond area. This makes it possible to singulate the individual memory dies and logic dies together as a single package after bonding the memory wafer and logic wafer together.

[0022] Figure 2A is a top view of a memory wafer 203 according to some embodiments of the present disclosure. Figure 2B is a top view of a logic wafer 205 according to some embodiments of the present disclosure. Memory dies 202 and 204 may be analogous to memory dies 102 and 104 described in relation to Figure 1, respectively. Memory wafers 203 and / or logic wafers 205 may include, but are not limited to, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, an epitaxial layer of silicon supported by a base semiconductor substrate, and other semiconductor structures.

[0023] As illustrated in Figures 2A and 2B, the memory wafer 203 and / or logic wafer 205 may have rounded peripheral edges. The memory wafer 203 and / or logic wafer 205 may include several dies (e.g., memory die 202 as shown in Figure 2A, or logic die 204 as shown in Figure 2B) having streets 237 (e.g., streets 237-1 and 237-2) located between them. Streets 237 may be referred to herein as saw streets or scribe streets. Streets 237 may be paths through which a tool can be cut in order to singulate the die. Before cutting, streets 237 may be etched to a certain depth to help guide the saw blade. Furthermore, one or more side marks along the top edge of the memory wafer 203 and / or logic wafer 205 may be used to align the saw blade before cutting. In many cases, as shown in Figures 2A and 2B, the die can be formed on a memory wafer 203 and / or a logic wafer 205 such that the streets 237 are formed in vertical rows and columns.

[0024] A die may comprise electronic devices such as transistors, capacitors, diodes, memory devices, processors, other devices, and / or integrated circuits. In some embodiments, each die on a particular wafer may be of the same type. For example, each die 202 on memory wafer 203 may be a memory die (e.g., memory die 102 as described in relation to Figure 1), and each die 204 on logic wafer 205 may be a logic die (e.g., logic die 104). Non-limiting examples of logic dies include DLAs, radio frequency communication circuits, gene sequencing circuits, video or imaging circuits, and audio circuits, sensor circuits, radar circuits, packet routing circuits, intrusion detection circuits, security monitoring circuits, cryptographic circuits, blockchain circuits, smart sensor circuits, 5G communication circuits, and application-specific integrated circuits (ASICs).

[0025] The memory die 202 may include an array of memory cells (e.g., memory array 110) residing on the die or chip. One or more of the memory dies 202 may include local input / output (LIO) lines for data communication. Data communication between the memory die 202 and the logic die 204 can be controlled by transceivers that may be located on the memory die 202 and / or the logic die 204. In some embodiments, the electrical path through which signals indicating data communicate between the memory die 202 and the logic die 204 is also coupled to a transceiver that controls whether such data continues on the electrical path of a receiving device. As used herein, “receiving device” refers to the destination of signaling between the memory die 202 and the logic die 204. For example, the receiving device for signaling data from the memory die 202 to the logic die 204 is a logic die (or one or more logic devices formed thereon). When one or more transceivers are on, a signal indicating data from the electrical path coupled to the transceiver is received by the receiving device, meaning the signal passes through the transceiver and continues within the receiving device. When one or more transceivers are off, a signal indicating data from the electrical path coupled to the transceiver is not received by the receiving device, meaning the signal does not pass through the transceiver and does not continue within the receiving device. Non-limiting examples of electrical paths include the global data bus and LIO lines. The memory die 202 may include transceivers associated with (e.g., coupled to) the LIO lines. Thus, transceivers may selectively enable the communication of data-indicating signals between the memory die 202 and the logic die 204. Transceivers are further described in relation to Figures 7A and 7B.

[0026] In relation to exemplary operation, the memory die 202 can perform read operations on data stored in the memory cells. Signals indicating data can be transmitted from the memory cells, along the LIO, through the sensing circuit, to the global data bus and the host (if the host requests data). Signals can also pass from the LIO through the memory / logic circuit 222 (described in relation to Figure 2C), through the wafer-on-wafer bond 211 (described in relation to Figure 2C), to the logic / memory circuit 224 (described in relation to Figure 2C). If the transceiver in the logic / memory circuit is on, the signal indicating data is transmitted to the logic die 204 and operated on the logic die 204 by one or more logic devices. If the transistor is off, the signal indicating data will not be transmitted to the logic die 204. With respect to the operation of the memory die 202, in some embodiments, there is no functional difference between a read operation on data intended to be transferred to the logic die 204 and a read operation on data intended to be transferred to an external host. The read operation can proceed normally, and the transceiver associated with the logic die 204 can control whether or not the logic die receives data. The transfer of data from the memory die 202 to the logic die 204 is not limited to the read operation, as will be described in more detail below. For example, data can be transferred from the memory die 202 to the logic die 204 using other operations such as test mode operation and refresh operation.

[0027] In some of the approaches described herein, after an electronic device is fabricated on the wafer, the wafer can be singulated (e.g., diced by a rotary saw blade cutting along a street). In contrast, in some embodiments of this disclosure, after an electronic device is fabricated on the memory wafer 203 and / or logic wafer 205, but before dicing, the memory wafer 203 and / or logic wafer 205 can be bonded together by a wafer-on-wafer bonding process. Following the wafer-on-wafer bonding process, the dies of the memory wafer 203 and / or logic wafer 205 can be singulated (e.g., diced by a rotary saw blade cutting along a street). As described herein, the memory wafer 203 can be bonded to the logic wafer 205 in a face-to-face configuration.

[0028] In some embodiments, the size of the electronic devices on the memory wafer 203 may be the same as the size of the electronic devices on the logic wafer 205. A street 237 on the memory wafer 203 may be in the same relative position as a street 237 on the logic wafer 205. This allows the individual memory dies and logic dies to be singulated together as a single package after the memory wafer 203 and / or logic wafer 205 have been bonded together.

[0029] Although not specifically illustrated, in some embodiments, the sizes of the electronic devices on memory wafer 203 and logic wafer 205 may differ proportionally. For example, one logic die may have the same or similar mounting area as four of the memory dies. After bonding memory wafer 202 and / or logic die 204 together, the four memory dies and logic dies can singulate as a single package. Conversely, one memory die may have the same mounting area as four of the logic dies, and the four logic dies and memory dies can singulate as a single package. Such a package may be called a network-on-wafer package. Multiple embodiments are not limited to a 4:1 ratio of die sizes.

[0030] Figure 2C shows cross-sections of portions of a memory die 202 and logic wafer 204 with a wafer-on-wafer bond 211, according to several embodiments of the present disclosure. The memory die 202 and logic die 204 may be similar to the memory die 102 and logic die 104 described in relation to Figure 1, respectively.

[0031] In some embodiments, the memory die 202 may include a memory / logic circuit 222 formed thereon. The memory / logic circuit 222 can provide electrical connections and signaling for the transfer of data and / or control signals between one or more memory arrays (e.g., memory array 110) of the memory die 202 and one or more logic dies (e.g., logic die 204) bonded thereto. In some embodiments, the memory / logic circuit 222 may include just two additional metal layers relative to the metal layer of the memory die 202.

[0032] In some embodiments, the logic die 204 includes a logic / memory circuit 224 formed thereon. The logic / memory circuit 224 can provide electrical connections and signaling for the transfer of data and / or control signals between one or more DLAs (e.g., DLA 117) of the logic die 204 and one or more memory dies (e.g., memory die 202) bonded thereto.

[0033] A wafer-on-wafer bond 211 can be formed between a memory die 202 and a logic die 204. As shown in Figure 2C, in some embodiments, the wafer-on-wafer bond 211 is formed between a memory / logic circuit 222 and a logic / memory circuit 224. The wafer-on-wafer bond 211 may include one or more metal bonds and / or direct dielectric / dielectric bonds. The wafer-on-wafer bond 211 can enable the transmission of electrical signals between the memory die 202 (e.g., via the memory / logic circuit 222) and the logic die 204 (e.g., via the logic / memory circuit 224).

[0034] The memory / logic circuit 222 and / or wafer-on-wafer bond 211 may include bond pads to the transceivers of the logic / memory circuit 224. The transceivers may be associated with a LIO prefetch bus and / or sense amplifier (sense amp) stripe. In some embodiments, the sense amp stripe may include 188 LIO connection pairs covering nine array cores, with 9,216 pairs per channel. In some embodiments, the sense amp stripe may include 288 LIO connection pairs, with 4,608 pairs per channel. However, multiple embodiments are not limited thereto.

[0035] The interconnection load of the wafer-on-wafer bond 211 may be less than 1.0 femtofarad and 0.5 ohms. In some embodiments, the maximum number of memory rows that can be activated at one time (e.g., 32 rows) can be activated and data can be transmitted to the logic die 204 via the wafer-on-wafer bond 211. The memory / logic circuit 222 and / or wafer-on-wafer bond 211 may include power and ground connections to each transceiver. Power connections may allow the activation of multiple memory rows at once. The wafer-on-wafer bond 211 can provide, for example, 256k data connections at a 1.2 micrometer pitch.

[0036] In some embodiments, the wafer-on-wafer bond 211 may include analog circuits (e.g., jumpers) that do not have transistors in the data path between the memory die and the logic die. The memory die can drive signals between them, and the logic die can sink signals between them, and vice versa. Instead of transmitting signals between the memory die and the logic die via logic gates, signals are transmitted directly between the memory die and the logic die. In some embodiments, the wafer-on-wafer bond 211 can be formed by a low-temperature (e.g., room temperature) bonding process. In some embodiments, the wafer-on-wafer bond 211 can be further processed in an annealing step (e.g., at 300°C).

[0037] Although not specifically illustrated, a redistribution layer can be formed between the memory die 202 and the logic die 204. The redistribution layer can enable compatibility between a single memory design and multiple ASIC designs. The redistribution layer can enable scaling up of the memory technology without necessarily scaling down the logic design at the same speed as the memory technology. For example, the circuitry of the memory die 202 can be formed with a different resolution than the circuitry of the logic die 204 without the need to adjust the wafer-on-wafer bond 211 and / or other circuitry between the memory die 202 and the logic die 204.

[0038] Figure 2D shows a portion 221 of a memory die 202 and a logic die 204 with a wafer-on-wafer bond 211, after singuling, according to some embodiments of the present disclosure. The memory die 202 is shown to be bonded to a substrate 218. However, in some embodiments, the logic die 204 may be bonded to the substrate 218 instead of the memory die 202. The substrate 218, the memory die 202, the wafer-on-wafer bond 211, and the logic die 204 can form a unit such as an integrated circuit configured to perform one or more desired functions. Although not specifically shown, the substrate 218 may include additional circuitry for operating, controlling, and / or communicating with the memory die 202, the logic die 204, and / or other off-chip devices.

[0039] The functionality of the memory die 202 may not change with respect to memory operation, but data can be transferred directly via the wafer-on-wafer bond 211 instead of being routed alternately from the memory die 202 to the logic die 204 via the I / O circuitry of the memory die 202 (e.g., to an external host device). For example, data can be transferred round trip to the logic die 204 via the wafer-on-wafer bond 211 (e.g., via the LIO lines of the memory die 202) using the test mode and / or refresh cycle of the memory die 202. For example, using a DRAM memory device refresh cycle with 8 rows active per bank, a refresh cycle time of 80 nanoseconds (60 nanoseconds per row), 4 banks in parallel, and a bank sequencing of 16 nanoseconds, the bandwidth would be 443 gigabytes / second. In contrast, in some embodiments of the present disclosure, using a wafer-on-wafer bond 211 which is a DRAM memory device with 32 rows active per bank, the refresh cycle time can approach 60 nanoseconds in parallel for 32 banks, and without bank sequencing, the bandwidth is 5 terabytes / second using 8 watts. While such a significant bandwidth (e.g., 5 terabytes / second) of data from the memory device can overwhelm other interfaces and / or host devices, logic devices such as DLA can utilize such data bandwidth through the connectivity provided by the wafer-on-wafer bond 211. Reducing off-chip data movement can reduce the power consumption associated with operating the memory device and provide significant data bandwidth.

[0040] Although not specifically illustrated, multiple memory dies 202 can be stacked on each other via bonds similar to wafer-on-wafer bonds 211. Such additional memory dies 202 may include memory / memory circuits similar to the memory / logic circuit 222 described in relation to Figure 2C. Alternatively, or additionally, TSVs can be used for data communication between or through the stack of memory dies 202. Pads between stacked memory dies 202 may be located where they are replicated on the vertically stacked memory dies 202 (as shown) so that the stacked memory dies 202 are aligned. In different embodiments, the stacked memory dies 202 can be formed by conventional processes and / or by wafer-on-wafer bonding (between two memory dies 202).

[0041] Although not specifically illustrated, a wafer bonded to the substrate 218 (e.g., a memory die 202 (shown), or a logic die 204) may include a TSV formed therein to enable communication with circuits outside the wafer. The TSV can also be used to provide power and ground contacts. Generally, TSVs have greater capacitance and pitch than wafer-on-wafer bonds, but do not offer as much bandwidth as wafer-on-wafer bonds.

[0042] Although not specifically illustrated, in some embodiments, additional components can be bonded to part 221. For example, a thermal solution component can be bonded to the top of the logic die 204 to provide cooling. The wafer-on-wafer bond 211 brings the logic die 204 and the memory die 202 close together so that heat can be generated. The thermal solution component can help dissipate the generated heat. In some embodiments, a non-volatile memory component may be included, for example, to permanently store the ANN model. However, in some embodiments, non-volatile memory may not be necessary because the model does not require separate or large storage space and may be updated frequently.

[0043] Figure 3 shows a portion 331 of two memory dies 302-1 and 302-2 and a logic die 304 according to some embodiments of the present disclosure. The two memory dies 302-1 and 302-2, and the logic die 304, may be analogous to the memory die 102 and logic die 104 described in relation to Figure 1, respectively. In the example of Figure 3, two lines 313 Line 323 reflects separate connections between memory die 302-2 and DLA317, and between memory die 302-1 and the circuitry of logic die 304 other than DLA317. The connection represented by line 313 may be of the same type as the connection represented by line 323, or it may be of a different type.

[0044] Although DLA317 is shown as a separate or distinct component from logic die 304, in some embodiments, DLA317 is a component of logic die 304. Showing DLA317 as separate or distinct from logic die 304 is intended to distinguish DLA317 from other components or circuits of logic die 304.

[0045] The arrangement of memory dies 302-1 and 302-2, logic die 304, and DLA317 as illustrated in Figure 3 can provide flexibility during manufacturing. A memory die that is communicatively coupled to DLA317 (e.g., memory die 302-2) may have different operation and / or performance requirements than another memory die that is not communicatively coupled to DLA317 (e.g., memory die 302-1). Therefore, during manufacturing, one or more memory dies to be communicatively coupled to DLA317 can be selected based on performance metrics (e.g., from a pool of memory dies). Examples of performance metrics include test results, low-bit error rate, input / output per second, etc.

[0046] As an exemplary example, whether a prospective memory die (e.g., selected from a pool of memory dies) is communicatively coupled to DLA317 or to a circuit of a logic die 304 other than DLA317 can be determined based on the performance metric value of the prospective memory die. In some embodiments, if the performance metric value of the prospective memory die meets a performance metric threshold, the prospective memory die may be memory die 302-2. If the performance metric value of the prospective memory die does not meet a performance metric threshold, it may be memory die 302-1. In some embodiments, if a prospective memory die has a more favorable performance metric value than another prospective memory die (e.g., selected from the same pool of memory dies), the prospective memory die may be memory die 302-2, and the other prospective memory die may be memory die 302-1.

[0047] In some embodiments, the circuitry of logic die 304 other than DLA317 can manage memory die 302-1. In some embodiments, there may be no direct signaling communication between memory dies 302-1 and 302-2 and the substrate 318. Rather, signaling between memory dies 302-1 and 302-2 and the substrate 318 is handled by the circuitry of logic die 304 (which may include DLA317), as indicated by jumpers 315-1 and 315-2.

[0048] Figure 3 shows logic dies 304 and DLA317 bonded to substrate 318. However, in at least one embodiment, memory dies 302-1 and 302-2 can be bonded to substrate 318 instead of logic dies 304 and DLA317. Although not specifically shown, substrate 318 may include circuitry for operating, controlling, and / or communicating with memory dies 302-1 and 302-2, logic die 304, and / or other off-chip devices. While Figure 3 is illustrated using two memory dies coupled to logic die 304, embodiments of this disclosure are not limited thereto. For example, two or more memory dies can be coupled to DLA317, and / or two or more memory dies can be coupled to DLA317. In some embodiments, three memory dies having more preferred values ​​of performance metrics can be communicably coupled to DLA317, and memory dies having less preferred values ​​of performance metrics can be coupled to circuitry on logic die 304 other than DLA317.

[0049] Figure 4 shows a portion 441 of the stack of memory dies 402-1, 402-2, and 402-3 and logic die 404 according to some embodiments of the present disclosure. The memory dies 402-1, 402-2, and 402-3, and logic die 404 may be analogous to the memory die 102 and logic die 104 described in relation to Figure 1, respectively. Although not specifically shown, the substrate 418 may include circuitry for operating, controlling, and / or communicating the memory dies 402-1, 402-2, and 402-3, logic die 404, and / or other off-chip devices.

[0050] In the example shown in Figure 4, multiple memory dies 402-1, 402-2, and 402-3 are stacked between the logic die 404 and the substrate 418. The memory dies 402-1, 402-2, and 402-3 are stacked vertically. In-plane bump contacts 419-1 and 419-2 connect the logic die 404 to the substrate 418. In some embodiments, a ball grid array (BGA) can be formed on the substrate 418 before the stacking of memory dies 402-1, 402-2, and 402-3 and / or before the logic die 404 is connected to the substrate 418. Thus, the in-plane bump contacts 419-1 and 419-2 may be parts of the BGA formed on the substrate 418.

[0051] Figure 5 shows a schematic of a memory die 502 according to some embodiments of the present disclosure. The memory die 502 includes 16 memory banks 525 arranged in four bank groups 524. Each of the bank groups 524 is coupled to a global data bus 551 (e.g., a 256-bit wide bus). Multiple embodiments are not limited to these specific examples. The global data bus 551 can be modeled as a charge / discharge capacitor. The global data bus 551 can conform to a memory standard for transmitting data from the memory die 502 over an I / O bus. However, although not specifically shown in Figure 5, in some embodiments, a logic die coupled to the memory die 502 via a wafer-on-wafer bond may include a transceiver for communicating data from the memory die 502 to the logic die via the wafer-on-wafer bond.

[0052] Figure 6 shows a memory bank 625 according to several embodiments of the present disclosure. The memory bank 625 comprises a number of memory devices 633, each of which contains a number of rows and columns of a number of memory cells (e.g., 1024 × 1024). Each of the memory devices 633 may contain a number of LIO lines 631, each represented by a number of filled dots. For example, each tile may contain 32 LIO lines 631. The LIO lines 631 within each tile are coupled to a global I / O line 632 via a multiplexer 662. The multiplexer 662 may also be called a transceiver in the art, but is referred to as a multiplexer herein. This is to distinguish it from a logic die transceiver configured to receive signals from the LIO lines 631, the global I / O line 632, and / or the global data bus 651.

[0053] Multiplexer 662 can be configured to receive a signal from LIO line 631. Multiplexer 662 selects a portion of LIO line 631. Multiplexer 662 can amplify the signal received from the selected portion of LIO line 631. Multiplexer 662 can also transmit the amplified signal via global I / O line 632. Multiplexer 662 can also receive a signal from global I / O line 632 and reduce the received signal. Multiplexer 662 can further transmit the reduced signal to LIO line 631.

[0054] The global I / O line 632 is coupled to the global data bus 661. Signals from multiple sense amplifiers can be multiplexed onto the LIO line 631. The LIO line 631 can be coupled to the logic die multiplexer 662 and transceiver (not shown) via a wafer-on-wafer bond. The logic die transceiver (not shown) can receive signals from the LIO line 631 via the wafer-on-wafer bond. The wafer-on-wafer bond provides pitch control that is precise enough to enable contact between the transceiver (not shown) and the LIO line 631, which would otherwise not be possible.

[0055] In some embodiments, a logic die transceiver (not shown) can receive enable / disable commands from a corresponding logic die (as opposed to, for example, receiving commands from a host). In some embodiments, enable / disable commands can be received by multiple logic die transceivers (for example, enable / disable commands may cause the corresponding transceivers to transmit signals indicating data from each particular row of memory bank 625). The control and operation of multiple logic die transceivers is similar to having thousands of memory controllers, except that they transmit data rather than control all operations. Such operation may be beneficial for applications involving, for example, large-scale parallel memory access operations. For an example of a memory device configured to contain 8-kilobit rows, each logic die transceiver can prefetch 256 bits of data. Thus, each logic die transceiver can bond out 256 bits. In other words, in some embodiments, (in this exemplary architecture) 256 bits of data can be transmitted for every 8 kilobits of stored data. In contrast, according to some of the aforementioned approaches using similar architectures, a typical memory interface (e.g., via global I / O lines) would only be able to transfer 256 bits for 4 gigabits of stored data.

[0056] Figure 7A shows circuit diagrams of sense amplifiers 763-1, 763-2, ..., 763-N, 763-N+1, 763-N+2, ..., 763-M, 763-M+1, 763-M+2, ..., 763-P, and multiplexers 764-1, 764-2, ..., 764-S according to some embodiments of the present disclosure. Sense amplifiers 763-1, 763-2, ..., 763-N, 763-N+1, 763-N+2, ..., 763-M, 763-M+1, 763-M+2, ..., 763-P may be referred to as sense amplifiers 763. Multiplexers 764-1, 764-2, ..., 764-S may be referred to as multiplexers 764. Figure 7A also includes a multiplexer 761 for a memory die. For clarity, Figure 7A has been simplified to focus on the components and circuits of the memory die and logic die, in particular to the present disclosure.

[0057] Multiplexer 761 is distinguished from transceivers 765-1, 765-2, ..., 765-S. Multiplexer 761 can be configured to receive signals from LIO line 731. Multiplexer 761 selects a portion of LIO line 731. Multiplexer 761 can amplify the signal received from the selected portion of LIO line 731. Multiplexer 761 can also transmit the amplified signal via global IO line 732. Multiplexer 761 can also receive signals from global IO line 732 and reduce the received signal. Multiplexer 761 can further transmit the reduced signal to LIO line 731. Although multiplexer 761 is called a multiplexer, multiplexer 761 is different from multiplexer 764 and has different functions.

[0058] The transceivers 765-1, 765-2, ..., 765-S can also receive signals, select a portion of the signal, amplify a portion of the signal, and transmit the amplified signal. However, the transceivers 765-1, 765-2, ..., 765-S can transmit the amplified signal to the logic die, but not to the global I / O line 732.

[0059] The memory die may include sense amplifier 763, multiplexer 764, and multiplexer 761. The memory die may also include LIO 731 and global I / O line 732. In various examples, a wafer-on-wafer bond 711 can couple the output of sense amplifier 773 to a logic die transceiver 765. The transceiver 765 is controlled by the logic die and can provide the output of sense amplifier 763 to the logic die's circuitry. For example, transceiver 765-1 can provide signals output from sense amplifiers 763-1, 763-2, ..., 763-N to the logic die's circuitry downstream from transceiver 765-1. Although a single transceiver 765-1 is shown, transceiver 765-1 can represent multiple transceivers, thereby providing sense amplifiers 763-1, 763-2, ..., 763-N simultaneously to downstream circuits from multiple transceivers on the logic die. Transceiver 765-2 can provide the outputs of sense amplifiers 763-N-1, 763-N+2, ..., 763-M to circuits on the logic die. Transceiver 765-S can provide the outputs of sense amplifiers 763-M+1, 763-M+2, ..., 763-P to circuits on the logic die.

[0060] The control circuit of the logic die (e.g., control circuit 118 as described in relation to Figure 1) can transmit signals to the transceiver 765 in order to selectively route signals representing data-off chips (e.g., to the logic die). The illustrated path from the sense amplifier 763 to the logic die transceiver 765 is a representation of the electrical path between the memory die and the logic die. Embodiments of this disclosure enable the functionality and fabrication of an additional high-bandwidth interface from the memory die to the logic die via the wafer-on-wafer bond 711, while preserving the functionality and fabrication of a standard memory interface.

[0061] In various examples, each transceiver 765 can be coupled to multiple sense amplifiers 763. For example, transceiver 765-1 can be coupled to sense amplifiers 763-1, 763-2, ..., 763-N. Transceiver 765-2 can be coupled to sense amplifiers 763-N+1, 763-N+2, ..., 763-M. Transceiver 765-S can be coupled to sense amplifiers 763-M+1, 763-M+2, ..., 763-P. In various examples, each transceiver 765 can transmit multiple signals. For example, transceiver 765-1 can simultaneously transmit signals provided by sense amplifiers 763-1, 763-2, ..., 763-N. Transceiver 765-2 can simultaneously retransmit signals provided by sense amplifiers 763-N+1, 763-N+2, ..., 763-M. Transceiver 765-S can simultaneously transmit signals provided by sense amplifiers 763-M+1, 763-M+2, ..., 763-P.

[0062] The logic die's control circuit includes the LIO731, which uses the transceiver 765 to transmit signals representing data. TypicalThe logic die can receive signals from the I / O path. The control circuit of the memory die (for example, control circuit 116 as described in relation to Figure 1) can utilize LIO 731, multiplexer 761, and global I / O line 732 to provide signals representing data via typical input / output paths. In various examples, transceivers 765 can route signals simultaneously. For example, transceiver 765-1 can route signals between the logic die and sense amplifiers 763-1, 763-2, ..., 763-N, which is done simultaneously with signal routing by transceivers 765-2 and / or transceiver 765-S. In various examples, transceiver 765-1 can simultaneously route signals between the logic die and sense amplifiers 763-1, 763-2, ..., 763-2.

[0063] Although not shown, transceivers on a logic die coupled to multiple memory devices can simultaneously route signals from the memory die to the logic die. For example, transceiver 765 can simultaneously route data together with other transceivers coupled to different memory devices. The control circuit can simultaneously activate rows of multiple memory devices to have the corresponding sense amplifiers (including, for example, sense amplifier 763) latch signals. Transceivers coupled to different memory devices (including, for example, transceiver 765) can simultaneously route signals from the sense amplifiers of the memory devices to the logic die. The logic die can simultaneously receive more signals from the memory die via transceiver 765 than would be possible to output via the global I / O line 732 or the global bus. The logic die can simultaneously supply more signals to the memory die via transceiver 765 than would be possible via the global I / O line 732 or the global bus. Transceiver 765 can route signals simultaneously with data routing by transceivers coupled to different banks via the wafer-on-wafer bond 711. In various examples, the memory die can simultaneously output data to the global I / O line 732 and the transceiver 765. For example, the control circuit of the memory die can activate LIO731 and the global I / O line 732 simultaneously with the activation of the transceiver 765 by the control circuit of the logic die, output a signal to the logic die, and output the signal via conventional I / O circuits, including the global I / O line 732.

[0064] In various examples, signals can be provided from the global bus of the memory die to the logic die. Transceivers on the logic die coupled to the global bus can be configured to route data from the memory die to the logic die. For example, a transceiver on the logic die can be activated to route signals from the global bus to the logic die. A transceiver configured to route signals from the global bus to the logic die may be different from a transceiver configured to route signals from LIO line 731 to the logic die. Two independent paths can be provided for routing signals from the memory die to the logic die. The first path may begin at LIO line 731. The second path may begin at the global bus of the memory die. The first path can be made available by activating one or more transceivers on the logic die. The second path can be made available by activating one or more transceivers on the logic die. In various examples, the amount of signals that can be routed simultaneously from LIO line 731 to the logic die may be greater than the amount of signals that can be routed simultaneously from the global bus to the logic die.

[0065] Figure 7B shows a schematic of LIO line 731 according to some embodiments of the present disclosure. In Figure 7B, the transceiver 765 is coupled to LIO line 731, compared to Figure 7A where the transceiver 765 is coupled to sense amplifier 763.

[0066] In Figure 7B, the sense amplifier 763 can output multiple signals. It can output signals to the multiplexer 764. For example, sense amplifiers 763-1, 763-2, ..., 763-N can output a first set of multiple signals to the multiplexer 764-1. Sense amplifiers 763-N+1, 763-N+2, ..., 763-M can output a second set of multiple signals to the multiplexer 764-2, while sense amplifiers 763-M+1, 763-M+2, ..., 763-P can output S sets of multiple signals to the multiplexer 764-S. As used herein, "S sets of multiple signals" represents a variable such that "S sets of multiple signals" represent multiple variable signals.

[0067] Each multiplexer 764 can output multiple signals to the LIO731. For example, multiplexer 764-1 can output the first part of a first set of multiple signals, multiplexer 764-2 can output the second part of a second set of multiple signals, and multiplexer 764-S can output S parts of S sets of multiple signals.

[0068] The transceiver 765 can, for example, route signals from the memory die's LIO line 731 to the logic die's LIO line 762. In various examples, the memory die can activate the multiplexer 761 and output signals from LIO line 731 to global I / O line 732 via the memory device's conventional I / O circuitry. The logic die can activate the transceiver 765 simultaneously with the activation of LIO line 731 and global I / O line 732, and output data to the logic die simultaneously with the output of data via the memory die's I / O circuitry. For example, the control circuitry of the memory device can determine whether to output data via the memory device's conventional I / O circuitry, and the control circuitry of the logic die can determine whether to output data to the logic die.

[0069] Although a single transceiver 765 is shown, multiple transceivers can be used to route signals from multiple LIO lines on a memory die to a logic die. For example, one transceiver can be coupled to the LIO line of a memory device on the memory die. Another transceiver can be coupled to the LIO line of another memory device on the memory die. Each transceiver can route signals to the logic die by routing the signal to the LIO line 762 on the logic die. Each transceiver can route signals simultaneously. In various examples, transceiver 765 can be coupled to the global I / O line 732 instead of the sense amplifier 763 or the LIO line 731. Similarly, transceivers coupled to the global I / O line can simultaneously route signals to the logic die.

[0070] Figure 8 is a flowchart corresponding to Method 867 for forming wafer-on-wafer bonded memory dies and logic dies according to several embodiments of the present disclosure. Although shown in a specific sequence or order, the order of the processes can be changed unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the shown processes can be performed in a different order, and some processes can be performed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in all embodiments. Other process flows are also possible.

[0071] In 868, method 867 may include forming a plurality of first metal pads on a first wafer. Forming the first metal pads may include forming memory / logic circuits on a plurality of memory devices. Forming the memory / logic circuits may include coupling a plurality of LIO lines of a memory device to a subset of the first metal pads, to different subsets of the first metal pads. A subset of the first metal pads may be dedicated to communication between the plurality of memory devices and the plurality of logic devices via the memory / logic circuits. Different subsets of the first pads may be dedicated to communication outside of the wafer-on-wafer bonded memory dies and logic dies.

[0072] In 869, method 867 may include forming a plurality of second metal pads on a second wafer. Forming a plurality of second metal pads may include forming logic / memory circuits on a plurality of logic devices.

[0073] In 870, method 867 may include bonding a subset of first metal pads to a subset of second metal pads via a wafer-on-wafer bonding process. Bonding can be performed such that each of a plurality of memory devices on the first wafer is aligned and coupled to at least one of a plurality of logic devices on the second wafer. Bonding the first metal pads and the subset of second metal pads may include coupling each I / O line of each of the plurality of memory devices to one I / O line of each of the plurality of logic devices. The first metal pads and the subset of second metal pads can be bonded such that four memory devices on the first wafer are aligned and coupled to one of the logic devices on the second wafer. The four memory devices and one of the logic devices have the same mounting area.

[0074] Method 867 may include forming a plurality of memory devices on a first wafer and / or a plurality of logic devices on a second wafer before bonding a subset of first metal pads to a subset of second metal pads. In 871, Method 867 may include singulating the bonded first and second wafers into individual wafer-on-wafer bonded memories and logic dies.

[0075] Figure 9 is a flowchart corresponding to method 972 for forming wafer-on-wafer bonded memory dies and logic dies according to several embodiments of the present disclosure. Although shown in a specific sequence or order, the order of the processes can be changed unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the shown processes can be performed in a different order, and some processes can be performed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in all embodiments. Other process flows are also possible.

[0076] In 973, method 972 may include forming a wafer-on-wafer bond between a first wafer on which a memory die is formed and a second wafer on which a logic die is formed. The memory die includes a memory array and a plurality of I / O lines coupled to the memory array. Forming the wafer-on-wafer bond may include providing a plurality of data paths directly from the memory die to the logic die and coupling the plurality of I / O lines to a DLA formed on the logic die. Before forming the wafer-on-wafer bond, method 972 may include positioning the first wafer and the second wafer so that the memory die and the logic die are facing each other. The wafer-on-wafer bond can be formed so that the memory die and the logic die remain facing each other.

[0077] Forming a wafer-on-wafer bond may involve forming a metallic material that contacts the memory die and logic die. The metallic material can be annealed. Forming a wafer-on-wafer bond may involve bonding the metallic material to the memory die and logic die at room temperature. Forming a wafer-on-wafer bond may involve bonding a first metallic material of the logic die to a second metallic material of the memory die. The first and second metallic materials can be fused to a third metallic material that contacts the memory die and logic die by heat treatment. In some embodiments, the first and second metallic materials may be the same metallic material, such as copper.

[0078] Figure 10 is a flowchart corresponding to Method 1080 for forming wafer-on-wafer bonded memory dies and logic dies according to several embodiments of the present disclosure. Although shown in a specific sequence or order, the order of the processes can be changed unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the shown processes can be performed in a different order, and some processes can be performed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in all embodiments. Other process flows are also possible.

[0079] In 1081, method 1080 may include forming a logic die including a DLA on a substrate. The DLA may be distinct from other circuits on the logic die. In 1082, method 1080 may include communicatively coupling a first memory die to the DLA in a face-to-face configuration. The first memory die has a more preferable value of a performance metric. For example, a performance metric value that satisfies a threshold of the performance metric may be a more preferable value. The first and second memory dies can be selected from a pool of memory dies. In 1083, method 1080 may include communicatively coupling a second memory die to other circuits on the logic die in a face-to-face configuration. The second memory die has an unfavorable value of a performance metric. For example, a performance metric value that does not satisfy a threshold of the performance metric may be an unfavorable value.

[0080] Although not specifically illustrated, method 1080 may include determining whether the first memory die has a more preferable value and whether the second memory die has an unfavorable value before communicatively coupling the first and second memory dies. The first memory die can be communicatively coupled to the DLA in response to the determination that the first memory die has a more preferable value. The second memory die can be communicatively coupled to other circuits of the logic die in response to the determination that the second memory die has an unfavorable value.

[0081] Figure 11 is a flowchart corresponding to Method 1190 for forming wafer-on-wafer bonded memory devices and logic devices according to several embodiments of the present disclosure. While shown in a specific sequence or order, the order of the processes can be changed unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the shown processes can be performed in a different order, and some processes can be performed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in all embodiments. Other process flows are also possible.

[0082] In 1191, method 1190 may include forming a plurality of memory devices on a first wafer. In 1192, method 1190 may form a plurality of logic devices on a second wafer. In 1193, method 1190 may form a wafer-on-wafer bond that directly couples the plurality of memory devices to the plurality of logic devices. The wafer-on-wafer bond couples memory / logic circuits formed on the plurality of memory devices to the plurality of logic devices and can provide a plurality of data paths dedicated to data communication between the memory / logic circuits and the plurality of logic devices.

[0083] Forming a wafer-on-wafer bond may involve aligning multiple pads on a second wafer coupled to multiple logic devices with multiple transceivers on a first wafer. Forming a wafer-on-wafer bond may also involve forming a metallic material that contacts multiple memory devices and multiple logic devices.

[0084] Figure 12 is a flowchart corresponding to Method 1295 for forming stacks of wafer-on-wafer bonded memory dies and logic dies according to several embodiments of the present disclosure. Although shown in a specific sequence or order, the order of processes can be changed unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the shown processes can be performed in a different order, and some processes can be performed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are required in all embodiments. Other process flows are also possible.

[0085] In 1296, method 1295 may include bonding a stack of memory dies to a substrate, the substrate including each first memory die proximal to the substrate and each last memory die distal to the substrate. In 1297, method 1295 may include bonding logic dies to a substrate using a plurality of bump contacts coplane with the stack of memory dies, the logic dies in contact with each last memory die. In 1299, method 1295 may include forming a plurality of bump contacts coplane with the stack of memory dies, the plurality of bump contacts enabling the substrate to bond to the logic dies.

[0086] Although not specifically illustrated, method 1295 may include forming a plurality of bump contacts as a BGA on a substrate. Bonding a stack of memory dies and bonding logic dies may include bonding the first surface of each last memory die to another memory die in the stack of memory dies, and bonding the second surface of each last memory die, opposite the first surface, to a logic die.

[0087] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that configurations intended to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative and not limiting. Combinations of the above embodiments with other embodiments not specifically described herein will be apparent to those skilled in the art by considering the above description. The scope of the various embodiments of this disclosure includes other uses in which the above structures and methods are used. Accordingly, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims, together with the entire scope of equivalents to which such claims are granted rights.

[0088] In the embodiments for carrying out the invention described herein, various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. The method of this disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of this disclosure must use more features than those explicitly described in each claim. Rather, as reflected in the following claims, the subject matter of the invention is not contained in all the features of the single disclosed embodiment. Accordingly, the following claims are incorporated herein into embodiments for carrying out the invention, and each claim stands on its own as a separate embodiment.

Claims

1. Forming a plurality of dynamic random access memory (DRAM) devices on a first wafer (203), Forming multiple logic devices on a second wafer (205), This involves forming a memory / logic circuit (222), Forming a plurality of first metal pads on the first wafer (203) (868), For each of the plurality of DRAM devices, the method includes coupling a plurality of local input / output (LIO) lines (631, 731) to each subset of the plurality of first metal pads. To form, This involves forming a logic / memory circuit (224), Forming a plurality of second metal pads on the second wafer (205) (869), To couple each transceiver (765) on the second wafer to each subset of the plurality of second metal pads, Forming which includes, Bonding (870) a subset of the first metal pads to a subset of the second metal pads via a wafer-on-wafer bonding process, wherein each of the plurality of DRAM devices (633) on the first wafer is aligned and coupled to at least one of the plurality of logic devices on the second wafer. The bonded first and second wafers are singulated into a memory and logic die, each individually bonded with wafer-on-wafer bonding (871), Includes, A method wherein each subset of the first metal pad and each subset of the second metal pad are dedicated to communication selectively enabled by each transceiver between the plurality of LIO lines and each of the plurality of logic devices.

2. The method according to claim 1, wherein bonding the subset of the first metal pads to the subset of the second metal pads comprises bonding each of the LIO lines (631, 632, 731, 732) of each of the plurality of memory devices to each of the I / O lines (762) of each of the plurality of logic devices.

3. Forming the memory / logic circuit further includes coupling the plurality of LIO lines (631, 731) of the memory device to different subsets of the first metal pads, The method according to claim 1, wherein the different subsets of the first metal pads are dedicated to communication with the outside of the wafer-on-wafer bonded memory die and logic die.

4. Bonding the subset of the first metal pads to the subset of the second metal pads includes bonding such that four of the plurality of DRAM devices on the first wafer are aligned and coupled with one of the plurality of logic devices on the second wafer, The method according to claim 1, wherein four of the plurality of DRAM devices and one of the plurality of logic devices have the same mounting area.

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