High-performance computing and high-capacity homogeneous / heterogeneous integrated systems

Abstract

To provide more powerful and efficient system-on-chip (SOC) or artificial intelligence (AI) chips and integrated systems based on monolithic integration.SOLUTION: An integrated system includes a first monolithic die and a second monolithic die. The first monolithic die includes a processing device circuit formed therein and the second monolithic die having a plurality of SRAM arrays formed therein. The second monolithic die has at least 2 GBytes, and the first monolithic die is electrically connected to the second monolithic die.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] This disclosure generally relates to integrated systems that include semiconductor structures, in particular logic chips having high-performance computing capabilities, and SRAM chips having large memory capacities. [Background technology]

[0002] Information technology (IT) systems are rapidly evolving in all businesses and operations, including those in factories, healthcare, and transportation. Today, systems-on-a-chip (SOCs) or artificial intelligence (AI) are at the heart of IT systems that make factories smarter, improve patient outcomes, and enhance the safety of autonomous vehicles. Data from manufacturing equipment, sensors, and machine vision systems can easily total one petabyte per day. Therefore, handling such petabyte-scale data requires high-performance computing (HPC) SOCs, or AI chips.

[0003] Generally, AI chips can be classified into graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). GPUs were originally designed to process graphical processing applications using parallel computing, but they have increasingly been used for AI training. The training speed and efficiency of GPUs are generally 10 to 1000 times greater than that of general-purpose CPUs.

[0004] FPGAs have logic blocks that interact with each other and can be designed by engineers to support specific algorithms, making them suitable for AI inference. FPGAs are preferred over ASIC designs due to their shorter time to market, lower cost, and flexibility, despite having drawbacks such as larger size, slower speed, and higher power consumption. The flexibility of FPGAs allows for partial programming of any part of the FPGA, depending on the requirements. FPGA inference speed and efficiency are 10 to 100 times greater than that of general-purpose CPUs.

[0005] On the other hand, ASICs are directly fitted into circuits and are generally more efficient than FPGAs. In the case of customized ASICs, their learning / inference speed and efficiency can be 10 to 1000 times greater than that of general-purpose CPUs. However, unlike FPGAs, which become easier to customize as AI algorithms continue to evolve, ASICs are gradually becoming obsolete as new AI algorithms are developed.

[0006] In GPUs, FPGAs, and ASICs (or similar SOCs, CPUs, NPUs, etc.), logic circuits and SRAM circuits are the two main types of circuits, and their combination accounts for approximately 90% of the AI ​​chip size. The remaining 10% of the AI ​​chip may include I / O pad circuits. However, miniaturization process / technology nodes for manufacturing AI chips are increasingly necessary to train AI machines efficiently and quickly, as they lead to better efficiency and performance. The improvement in performance and cost of integrated circuits has been mainly achieved through process miniaturization technologies based on Moore's Law, but such miniaturization technologies from 3nm to 5nm have faced many technical problems, thus dramatically increasing the investment costs and capital in research and development for the semiconductor industry.

[0007] For example, miniaturizing SRAM devices for increased memory density, reducing operating voltage (VDD) for lower standby power consumption, and achieving the improved yield required to realize larger capacity SRAMs are becoming increasingly difficult due to the challenges of miniaturizing to 28nm (or lower) manufacturing processes.

[0008] Figure 1 shows the SRAM cell architecture, namely a 6-transistor (6-T) SRAM cell. It consists of two cross-coupled inverters (PMOS pull-up transistors PU-1 and PU-2, and NMOS pull-down transistors PD-1 and PD-2), and two access transistors (NMOS pass-gate transistors PG-1 and PG-2). A high-level voltage VDD is coupled to the PMOS pull-up transistors PU-1 and PU-2, and a low-level voltage VSS is coupled to the NMOS pull-down transistors PD-1 and PD-2. When a word line (WL) is enabled (i.e., a row is selected in the array), the access transistors are turned on, connecting the storage node (Node-1 / Node-2) to the vertically extending bit lines (BL and BL Bar).

[0009] Figure 2 shows a "stick diagram" representing the layout and connections of the six transistors in an SRAM. A stick diagram typically includes only the active region (vertical bars) and gate lines (horizontal bars), forming the pull-down transistors PD and pull-up transistors PU of the six transistors in the SRAM. Of course, there are still many other connections, some directly coupled to the six transistors, and others coupled to the word line (WL), bit lines (BL and BL bars), high-level voltage VDD, and low-level voltage VSS, etc.

[0010] When the minimum feature size decreases, λ 2 or F 2Part of the reason for the dramatic increase in the total area of ​​the SRAM cell represented by can be explained as follows: A conventional 6T SRAM has six transistors connected by using multiple interconnects, and has a first interconnect layer M1 for connecting the gate level ("gate") of the transistors to the diffusion level of the source and drain regions (regions commonly called "diffusion"). To facilitate signal transmission without increasing the die size by simply using M1, it is necessary to add a second interconnect layer M2 and / or a third interconnect layer M3 (e.g., word lines (WL) and / or bit lines (BL and BL Bar)), and thus a structure Via-1 made of a specific type of conductive material is formed to connect M2 to M1.

[0011] Therefore, a vertical structure exists formed from diffusion through a contact (Con) connection to M1, i.e., "diffusion-Con-M1". Similarly, another structure for connecting a gate to M1 through a contact structure can be formed as "gate-Con-M1". Furthermore, if a connection structure needs to be formed from the M1 interconnect to the M2 interconnect through via 1, it is called "M1-via 1-M2". A more complex structure from the gate level to the M2 interconnect can be represented as "gate-Con-M1-via 1-M2". Furthermore, stacked interconnect systems may have structures such as "M1-via 1-M2-via 2-M3" or "M1-via 1-M2-via 2-M3-via 3-M4", etc.

[0012] The gates and diffuses within the two access transistors (NMOS pass-gate transistors PG-1 and PG-2, as shown in Figure 1) are connected to the word lines (WL) and / or bit lines (BL and BL Bar), which are located within the second interconnection layer M2 or the third interconnection layer M3. Therefore, in conventional SRAMs, such metallic connections must first pass through the interconnection layer M1. In other words, modern interconnection systems in SRAMs may not allow gates or diffuses to connect directly to M2 without bypassing the M1 structure.

[0013] As a result, the required space between one M1 interconnect and the other increases the die size, and in some cases, the wiring connection may hinder the specific intention of efficient channeling, which is to directly use M2 to cross the M1 area. Furthermore, it is difficult to form a self-alignment structure between via 1 and contact, and at the same time, it is difficult for both via 1 and contact to connect to their respective interconnection systems.

[0014] Furthermore, in conventional 6T SRAM, there is at least one NMOS transistor and one PMOS transistor located within several adjacent regions of the p-substrate and n-wells, respectively, which are formed adjacent to each other within a close range. A parasitic junction structure called an n+ / p / n / p+ parasitic bipolar device is formed by its contour, starting from the n+ region of the NMOS transistor, extending to the p-well, to the adjacent n-well, and even to the p+ region of the PMOS transistor.

[0015] Large noises can occur at n+ / p or p+ / n junctions, causing very large currents to flow abnormally through these n+ / p / n / p+ junctions. This can, in some cases, disrupt the operation of parts of the CMOS circuit and lead to malfunctions of the entire chip. Such abnormal phenomena, called latch-up, negatively impact CMOS operation and must be avoided. One way to improve resistance to latch-up, which is indeed a weakness of CMOS, is to increase the distance from the n+ region to the p+ region. As a result, increasing the distance from the n+ region to the p+ region to avoid the latch-up problem also increases the size of the SRAM cell.

[0016] However, even with the miniaturization of the manufacturing process to 28nm or less (the so-called "minimum processing dimension," "lambda (λ)," or "F"), λ 2 or F 2The total area of ​​the SRAM cell, as shown by , increases dramatically as the minimum machining dimensions decrease, as shown in Figure 3, due to interference between contact sizes, and interference between the layout of metal wiring connecting word lines (WL), bit lines (BL and BL Bar), high-level voltage VDD, and low-level voltage VSS, etc. (quoted from "15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications, 2020 IEEE International Solid-State Circuits Conference - (ISSCC), 2020, pp. 238-240) by J. Chang et al.).

[0017] A similar situation arises with the miniaturization of logic circuits. Miniaturizing logic circuits for increased memory density, reducing operating voltage (Vdd) for lower standby power consumption, and achieving the higher yield required for larger capacity logic circuits are becoming increasingly difficult. Standard cells are commonly used and are fundamental elements within logic circuits. Standard cells can comprise basic logic function cells (e.g., inverter cells, NOR cells, NAND cells).

[0018] Similarly, in miniaturizing the manufacturing process to 28nm or less, λ 2 or F 2 The total area of ​​a standard cell, as expressed by [formula], increases dramatically as the minimum machining dimensions decrease due to the size of the contacts and interference between the layout of the metal wiring.

[0019] Figure 4(a) shows a "stick diagram" representing the layout and connections of PMOS and NMOS transistors in a 5 nm (UHD) standard cell of a semiconductor enterprise. The stick diagram includes only active regions (horizontal lines) and gate lines (vertical lines). Hereinafter, the active regions may be referred to as "fins". Naturally, there are still many contacts that are directly coupled to the PMOS and NMOS transistors on one hand, and on the other hand, coupled to the input terminal, output terminal, high-level voltage Vdd, low-level voltage VSS (or ground "GND"), and the like. In particular, each transistor includes two active regions or fins (marked by gray dashed rectangles) to form the channel of the transistor, so that the W / L ratio can be maintained within an allowable range. The area size of the inverter cell is equal to X×Y, where X=2×Cpp, Y=cell_height, and Cpp is the contact-to-poly pitch distance (Cpp).

[0020] It can be seen that some active regions or fins between the PMOS and NMOS (referred to as "dummy fins") are not utilized within the PMOS / NMOS of this standard cell, and the potential reason therefor is most likely related to the latch-up issue between the PMOS and NMOS. Therefore, the latch-up distance between PMOS and NMOS in Figure 4(a) is 3×Fp, where Fp is the fin pitch. Based on the available data regarding Cpp (54 nm) and cell height (216 nm) in the 5 nm standard cell, the cell area is 23328 nm 2 (or 933.12λ 2 where lambda (λ) is the minimum feature size of 5 nm) can be calculated by X×Y. Figure 4(b) shows the aforementioned 5 nm standard cell and its dimensions. As shown in Figure 4(b), the latch-up distance between PMOS and NMOS is 15λ, Cpp is 10.8λ, and the cell height is 43.2λ.

[0021] For three foundries, the scaling trend regarding area size (2Cpp × cell_height) versus different process technology nodes can be shown in Figure 5. As the technology node decreases (e.g., from 22 nm to 5 nm), λ 2 In terms of conversion, it is clear that the area size of conventional standard cells (2Cpp × cell_height) increases dramatically. Within conventional standard cells, the smaller the technology process node, the λ 2 In terms of conversion, the area size becomes larger. Such λ 2 The dramatic increase in can be brought about by, as λ decreases, the difficulty in proportionally reducing the sizes of gate contacts / source contacts / drain contacts, the difficulty in proportionally reducing the latch-up distance between PMOS and NMOS, and interferences in metal layers corresponding to the reduction of λ, both in SRAM and logic circuits.

[0022] From another perspective, any high-performance computing (HPC) chips such as SOC, AI, NPU (Network Processing Unit), GPU, CPU, and FPGA, etc., currently use monolithic integration to arrange as many and more circuits as possible. However, as shown in Figure 6(a), maximizing the die area of each monolithic die is limited by the maximum reticle size of the lithography stepper, which is difficult to expand due to existing state-of-the-art photolithography exposure tools. For example, as shown in Figure 6(b), current i193 and EUV lithography steppers have a maximum reticle size, thus, a monolithic SOC die is 26 mm × 33 mm, that is, 858 mm 2 has a scanner maximum field area (SMFA) (https: / / en.wikichip.org / wiki / mask). However, for high-performance computing or AI purposes, high-end consumer GPUs are 500~600 mm 2appears to be reaching. As a result, implementing two or more major functional blocks such as (for example) a GPU and an FPGA on a single die has become more difficult or impossible. Furthermore, the most widely used 6-transistor CMOS SRAM cell is extremely large, which increases the size of sufficient embedded SRAM (eSRAM) for both major blocks. In addition, external DRAM capacity needs to be expanded, but discrete PoP (Package on Package, for example, HBM~SOC) or POD (Packaged DRAM on SOC Die) are still constrained by the difficulty of achieving the desired performance of poorer die-to-die or package-to-die signal interconnections.

[0023] Accordingly, there is a need in the near future to propose a new integrated system including a logic chip with HPC and an SRAM chip with high storage capacity, which can solve the above-mentioned problems so that a more powerful and efficient SOC or AI single chip based on monolithic integration can be realized. SUMMARY OF THE INVENTION

[0024] One aspect of the present disclosure provides an integrated system, where the integrated system includes a first monolithic die and a second monolithic die. The first monolithic die has a processor circuit formed therein, and the second monolithic die has a plurality of SRAM arrays formed therein. The second monolithic die has a capacity of at least 2 GB, and the first monolithic die is electrically connected to the second monolithic die.

[0025] In one embodiment of the present disclosure, the first monolithic die has a die area equal to or substantially equal to the maximum scanner patterning area defined by a specific technology process node, and the second monolithic die has a die area equal to or substantially equal to the maximum scanner patterning area defined by the specific technology process node.

[0026] In one embodiment of this disclosure, the maximum drawing area of ​​the scanner is 26 mm × 33 mm or 858 mm 2 It's not bigger than that.

[0027] In one embodiment of the present disclosure, the first monolithic die and the second monolithic die are housed in a single package.

[0028] In one embodiment of this disclosure, the plurality of SRAM arrays include at least 20 GB.

[0029] In one embodiment of the present disclosure, the processing unit circuit comprises a first processing unit circuit and a second processing unit circuit, the first processing unit circuit comprising a plurality of first logic cores, each of which comprises a first SRAM size, and the second processing unit circuit comprising a plurality of second logic cores, each of which comprises a second SRAM size.

[0030] In one embodiment of this disclosure, the main function performed by the first processing unit circuit is different from the main function performed by the second processing unit circuit.

[0031] In one embodiment of the present disclosure, the first or second processing unit circuit is selected from the group consisting of a graphics processing unit (GPU), a central processing unit (CPU), a tensor processing unit (TPU), a network processing unit (NPU), and a field-programmable gate array (FPGA).

[0032] In one embodiment of the present disclosure, the first monolithic die further includes L1 caches and L2 caches utilized by the processing circuitry during the operation of the first monolithic die, and the plurality of SRAM arrays include L3 caches and L4 caches utilized by the processing circuitry during the operation of the first monolithic die.

[0033] In one embodiment of the present disclosure, the integrated system further comprises a third monolithic die in which a plurality of SRAM arrays are formed therein, the third monolithic die comprises at least 2 to 20 GB, the first monolithic die, the second monolithic die, and the third monolithic die are housed in a single package, the first monolithic die has a die area equal to or approximately equal to the maximum scanner drawing area defined by a particular technology process node, the second monolithic die has a die area equal to or approximately equal to the maximum scanner drawing area defined by the particular technology process node, and the third monolithic die has a die area equal to or approximately equal to the maximum scanner drawing area defined by the particular technology process node.

[0034] In one embodiment of the present disclosure, the first monolithic die, the second monolithic die, and the third monolithic die are stacked in the vertical direction.

[0035] Another aspect of the present disclosure provides an integrated system comprising a first monolithic die and a second monolithic die. The first monolithic die has processing circuitry, the second monolithic die has a plurality of SRAM arrays, the plurality of SRAM arrays comprising at least 2 GB, the first monolithic die is physically separated from the second monolithic die, the first monolithic die is electrically connected to the second monolithic die, and the integrated system does not include high-bandwidth memory (HBM).

[0036] In one embodiment of the present disclosure, the second monolithic die has an area size equal to or approximately equal to the maximum scanner drawing area defined by a specific technology process node, and the first monolithic die has an area size equal to or approximately equal to the maximum scanner drawing area defined by the specific technology process node.

[0037] In one embodiment of the present disclosure, the first monolithic die and the second monolithic die are housed in a single package, and the first monolithic chip is electrically connected to the second monolithic chip by wire bonding, flip-chip bonding, solder bonding, interposed through-silicon (TSV) bonding, or micro-copper pillar direct bonding.

[0038] Another aspect of the present disclosure provides an integrated system comprising a first monolithic circuit and a second monolithic circuit. The first monolithic circuit has a processing circuit, the second monolithic circuit has a plurality of SRAM arrays, the plurality of SRAM arrays comprising at least 2 to 20 GB, the first monolithic circuit is electrically connected to the second monolithic circuit, the first monolithic circuit is formed in a first monolithic die, the second monolithic circuit is formed in a second monolithic die, the first monolithic die and the second monolithic die are housed in a single package, or the first monolithic die and the second monolithic die are housed in a first package and a second package, respectively. [Brief explanation of the drawing]

[0039] The above and other aspects of this disclosure will be better understood in relation to the following detailed description of preferred but not limited embodiments. The following description is made with reference to the accompanying drawings.

[0040] [Figure 1] (Conventional Technology) This is a schematic diagram of a typical 6T SRAM cell. [Figure 2] (Conventional Technology) This is a stick diagram corresponding to the 6T SRAM in Figure 1. [Figure 3](Prior Art) This figure shows the total area of ​​SRAM cells by λ² (or F²) for different process dimensions λ (or F) using currently available manufacturing processes. [Figure 4(a)] (Conventional Technology) This shows a "stick diagram" representing the layout and connections of PMOS and NMOS transistors in a 5nm (UHD) standard cell from a semiconductor company (Samsung). [Figure 4(b)] (Prior Art) Figure 4(a) shows a stick diagram illustrating the dimensions of Samsung's 5nm (UHD) standard cell. [Figure 5] (Conventional Technology) This shows the miniaturization trend for area size versus different process technology nodes for three foundries. [Figure 6(a)] This figure shows a monolithic SOC die with a limited maximum scanner drawing area (SMFA) due to the maximum reticle size of the lithography stepper (conventional technology). [Figure 6(b)] This figure shows a monolithic SOC die with a limited maximum scanner drawing area (SMFA) due to the maximum reticle size of the lithography stepper (conventional technology). [Figure 7(a)] A top view showing an mMOSFET used in a new standard cell according to one embodiment of the present disclosure. [Figure 7(b)] This is a cross-sectional view obtained along the cutting line C7J1, as shown in Figure 7(a). [Figure 7(c)] This is a cross-sectional view obtained along the cutting line C7J2, as shown in Figure 7(a). [Figure 8(a)] This is a top view showing a combination structure of PMOS transistors and NMOS transistors used in a new standard cell according to one embodiment of this invention. [Figure 8(b)] These are cross-sectional views of a PMOS transistor and an NMOS transistor obtained along the cutting line (X-axis) in Figure 8(a). [Figure 9(a)] This figure shows that SRAM bit cell sizes (λ² equivalent) can be observed across three different companies and different technology nodes from the present invention. [Figure 9(b)] This figure shows a comparison of the area size of the new standard cell provided by the present invention with that of conventional products provided by various other companies. [Figure 10] This figure shows an integrated system provided by an integrated scaling and stretching platform according to one embodiment of the present invention, compared to a conventional system. [Figure 11(a)] This figure shows a single monolithic die of an integrated system provided by an integrated scaling and stretching platform according to one embodiment of the present disclosure. [Figure 11(b)] This figure shows a single monolithic die of an integrated system provided by an integrated scaling and stretching platform according to another embodiment of the present disclosure. [Figure 11(c)] This figure shows a single monolithic die of an integrated system provided by an integrated scaling and stretching platform according to another embodiment of the present disclosure. [Figure 11(d)] This figure shows a single monolithic die of an integrated system provided by an integrated scaling and stretching platform according to yet another embodiment of the present disclosure. [Figure 12(a)] This figure shows an integrated system provided by an integrated scaling and stretching platform, according to yet another embodiment of the present disclosure, compared to a conventional one. [Figure 12(b)] This figure shows a comparison of the SRAM cell area of ​​the integrated system of the present invention and those of three foundries, based on different technology nodes. [Figure 13(a)] This figure shows a single monolithic die of an integrated system provided by an integrated scaling and stretching platform, according to yet another embodiment of the present disclosure. [Figure 13(b)]This figure shows a single monolithic die of an integrated system provided by an integrated scaling and stretching platform, according to yet another embodiment of the present disclosure. [Figure 14] This figure shows an integrated system provided by an Integrated Scaling and Stretching Platform (ISSP) according to yet another embodiment of the present disclosure. [Figure 15] This figure shows an integrated system provided by an Integrated Scaling and Stretching Platform (ISSP) according to yet another embodiment of the present disclosure. [Modes for carrying out the invention]

[0041] This disclosure provides an integrated system. The above and other aspects of this disclosure will be better understood by the following detailed description of preferred, but not limited, embodiments. The following description is made with reference to the accompanying drawings:

[0042] Several embodiments of this disclosure are disclosed below with reference to the accompanying drawings. However, the structures and contents disclosed in the embodiments are for illustrative and explanatory purposes only, and the scope of protection of this disclosure is not limited to these embodiments. It should be noted that this disclosure does not show all possible embodiments, and that a person skilled in the art of this disclosure can make suitable modifications or changes based on this specification disclosed below to meet their actual needs without departing from the spirit of this disclosure. This disclosure is applicable to other embodiments not disclosed herein.

[0043] Embodiment 1

[0044] This disclosure proposes incorporating the following inventions: a. Novel transistors (disclosed in U.S. Patent Application No. 17 / 138,918, filed on December 31, 2020, titled "MINIATURIZED TRANSISTOR STRUCTURE WITH CONTROLLED DIMENSIONS OF SOURCE / DRAIN AND CONTACT-OPENING AND RELATED MANUFACTURE METHOD," the entire content of U.S. Patent Application No. 17 / 138,918 is incorporated herein by reference; disclosed in U.S. Patent Application No. 16 / 991,044, filed on August 12, 2020, titled "TRANSISTOR STRUCTURE AND RELATED INVERTER," the entire content of U.S. Patent Application No. 16 / 991,044 is incorporated herein by reference; and disclosed in "COMPLEMENTARY MOSFET STRUCTURE WITH LOCALIZED ISOLATIONS IN SILICON SUBSTRATE TO REDUCE LEAKAGES," filed on May 12, 2021) This is presented in U.S. Patent Application No. 17 / 318,097, entitled “AND PREVENT LATCH-UP,” the entirety of which is incorporated herein by reference. b. Interconnection with transistors (discussed in U.S. Patent Application No. 17 / 528,957, filed on November 17, 2021, entitled “INTERCONNECTION STRUCTURE AND MANUFACTURE METHOD THEREOF,” the entirety of which is incorporated herein by reference), c. SRAM cells (disclosed in U.S. Patent Application No. 17 / 395,922, filed on August 6, 2021, entitled “NEW SRAM CELL STRUCTURES,” the entirety of which is incorporated herein by reference), and d. Standard cell design (presented in U.S. Provisional Patent Application No. 63 / 238,826, filed on 31 August 2021 and titled “STANDARD CELL STRUCTURES,” the entirety of which is incorporated herein by reference)

[0045] For example, Figure 7(a) is a top view showing a MOSFET structure according to one embodiment of the present disclosure. Figure 7(b) is a cross-sectional view obtained along the cutting line C7J1 as shown in Figure 7(a). Figure 7(c) is a cross-sectional view obtained along the cutting line C7J2 as shown in Figure 7(a). In the proposed MOSFET, the silicon region of the gate terminal (e.g., silicon region 702c) and the silicon region of the source / drain terminals are exposed and have seed regions for selective epitaxial growth technology (SEG) to grow pillars (e.g., a first conductor pillar portion 731a and a third conductor pillar portion 731b) based on the seed region.

[0046] Furthermore, the first conductor pillar portion 731a and the third conductor pillar portion 731b each further have seed regions or seed pillars within their upper parts, which can be used for subsequent selective epitaxial growth. Subsequently, a second conductor pillar portion 732a is formed on the first conductor pillar 731a by a second selective epitaxial growth, and a fourth conductor pillar 732b is formed on the third conductor pillar portion 731b.

[0047] This embodiment may be applied to allow the M1 interconnect (a type of conductive terminal) or conductive layer to be directly connected to the MX interconnect layer (without connecting to conductive layers M2, M3, ...MX-1) in a self-aligning manner through a single vertical conductive or conductive plug, as shown in Figures 7(a) to 7(c), provided that a seed portion or seed pillar is present above the conductive terminal and conductive pillar portion configured for the subsequent selective epitaxial growth technique. The seed portion or seed pillar is not limited to silicon, and any material that can be used as a seed configured for the subsequent selective epitaxial growth is permitted.

[0048] Figure 8(a) is a top view showing a combined structure of a PMOS transistor 52 and an NMOS transistor 51 according to one embodiment of this embodiment. Figure 8(b) is a cross-sectional view of the PMOS transistor 52 and the NMOS transistor 51 obtained along the cutting line (X-axis) in Figure 8(a). The structure of the PMOS transistor 52 is identical to that of the NMOS transistor 51. A gate structure 33 comprising a gate dielectric layer 331 and a gate conductive layer 332 (e.g., gate metal) is formed on the horizontal or initial surface of a semiconductor substrate (such as a silicon substrate). A dielectric cap 333 (such as a composite of an oxide layer and a nitride layer) is placed on the gate conductive layer 332. Furthermore, a spacer 34, which may include a composite of an oxide layer 341 and a nitride layer 342, is used to cover the sidewalls of the gate structure 33. Trenches are formed in the silicon substrate, and all or at least part of the source region 55 and the drain region 56 are located in the corresponding trenches, respectively. The source (or drain) region within the MOS transistor 52 may include the N+ region or other suitable doping profile regions (e.g., a gradual or stepwise change from the P- and P+ regions).

[0049] Furthermore, localized isolation 48 (such as nitride or other high-k dielectric material) is placed in one trench and positioned below the source region, and another localized isolation 48 is placed in another trench and positioned below the drain region. Such localized isolation 48 lies below the horizontal silicon surface (HSS) of the silicon substrate and may be called localized isolation into the silicon substrate (LISS) 48. LISS 48 may be a composite of thick nitride or dielectric layers. For example, a localized isolation or LISS 48 may comprise a composite localized isolation including an oxide layer 481 covering at least a portion of the sidewalls of the trench and another oxide layer 482 covering at least a portion of the bottom wall of the trench. The oxide layers 481 and 482 may be L-shaped oxide layers formed by thermal oxidation.

[0050] The composite localized isolation 48 may further include a nitrided layer 483 on top of the oxide layer 482 and / or oxide layer 481. The shallow trench isolation (STI) region may comprise a composite STI 49 including an STI-1 layer 491 and an STI-2 layer 492, where the STI-1 layer 491 and the STI-2 layer 492 may each be made of a thick oxide material by different processes.

[0051] Furthermore, the source (or drain) region may comprise a composite source region 55 and / or drain region 56. For example, within an NMOS transistor 52, the composite source region 55 (or drain region 56) comprises at least a low-concentration doped drain (LDD) 551 and an N+ high-concentration doped region 552 within the trench. The low-concentration doped drain (LDD) 551, in particular, abuts an exposed silicon surface having a uniform (110) crystal orientation. The exposed silicon surface has a longitudinal boundary of appropriate thickness that is embedded, in contrast to the edge of the gate structure. The exposed silicon surface is substantially aligned with the gate structure. The exposed silicon surface may be the end face of the transistor channel.

[0052] The low-concentration doped drain (LDD) 551 and the N+ high-concentration doped region 552 may be formed based on selective epitaxial growth (SEG) techniques (or other preferred methods, such as atomic layer deposition ALD or selective growth ALD-SALD) for growing silicon from exposed TEC regions used as crystal seeds to form a new, orderly (110) lattice across LISS regions that do not have a seeding effect on the changing (110) crystal structure of the newly formed crystal of the composite source region 55 or drain region 56. Such newly formed crystals (including the low-concentration doped drain (LDD) 551 and the N+ high-concentration doped region 552) may be called TEC-Si.

[0053] In one embodiment, the TEC is aligned or substantially aligned with the edge of the gate structure 33, the length of the LDD 551 is adjustable, and the sidewall of the LDD 551 opposite to the TEC is aligned or substantially aligned with the sidewall of the spacer 34. The composite source (or drain) region may further comprise several tungsten (or other suitable metallic material, e.g., TiN / tungsten) plugs 553 formed in lateral connections with the TEC-Si portion for completion of the entire source / drain region. Active channel currents flowing to future metal interconnects, such as a metal-1 layer, reach the tungsten 553 (or other metallic material) connected directly to metal-1 via several good metal-metal ohmic contacts having much lower resistance than conventional silicon-metal contacts, through the LDD 551 and the N+ high-concentration doped region 552.

[0054] The source / drain contact resistance of the NMOS transistor 52 can be kept within a suitable range due to the fused metal-semiconductor junction structure utilized within the source / drain structure. This fused metal-semiconductor junction within the source / drain structure can improve the current crowding effect and reduce contact resistance. Furthermore, since the bottom of the source / drain structure is insulated from the substrate by the bottom oxide (oxide layer 482), the isolation between n+~n+ or p+~p+ can be kept within a suitable range. Thus, the distance between two adjacent active regions of a PMOS transistor (not shown) can be reduced to 2λ. The bottom oxide (oxide layer 482) can significantly reduce source / drain coupling leakage current, thereby reducing n+~n+ or p+~p+ leakage current.

[0055] TIFF0007933924000001.tif66164

[0056] Furthermore, the composite STI 49 can be elevated (for example, the STI-2 layer 492 is higher than the initial semiconductor surface and extends to the top surface of the gate structure), so that the selectively grown source / drain region may be confined by the composite STI and not extend beyond the composite STI 49. A metal contact plug (such as a tungsten plug 553) can be deposited in the hole between the composite STI 49 and the gate structure without using a separate contact mask to form the contact hole. Moreover, the top surface and one side wall of the highly doped region 552 can be in direct contact with the metal contact plug, and the contact resistance of the source / drain region can be dramatically reduced.

[0057] Furthermore, in conventional designs, the metal traces for the high-level voltage Vdd and / or low-level voltage Vss (or ground) are distributed above the initial silicon surface of the silicon substrate, and such distribution interferes with multiple other metal traces if there is not enough space between them. The present invention also discloses a new standard cell or SRAM cell in which the metal traces for the high-level voltage Vdd and / or low-level voltage Vss can be distributed below the initial silicon surface of the silicon substrate, thereby avoiding interference between contact sizes, interference between the layout of metal traces connecting the high-level voltage Vdd and low-level voltage Vss, etc., even when the size of the standard cell is reduced.

[0058] For example, within the drain region of the NMOS 51, tungsten or other metallic material 553 is directly coupled (by removing LISS 48) to a P-well electrically coupled to Vdd. Similarly, within the source region of the NMOS 51, tungsten or other metallic material 553 is directly coupled (by removing LISS 48) to a p-well or P-substrate electrically coupled to ground. Thus, the source / drain region openings originally used to electrically couple the source / drain region to a metal-2 layer (M2) or metal-3 layer (M3) for Vdd or ground connection can be omitted in new standard cells and standard cells.

[0059] In summary, at least the following advantages exist: (1) The source, drain, and gate lengths of transistors in a standard cell / SRAM can be precisely controlled, and these lengths can be as small as the minimum machining dimension, lambda (λ), as shown in the cited U.S. Patent Application No. 17 / 138,918. Thus, when two adjacent transistors are connected to each other through the drain / source, the transistor length is as small as 3λ, and the distance between the gate edges of two adjacent transistors is as small as 2λ. Of course, due to tolerances, the transistor length is approximately 3λ to 6λ or more, and the distance between the gate edges of two adjacent transistors may be 8λ or more. (2) The first metal interconnect (M1 layer) connects directly to the gate, source, and / or drain regions through self-aligning miniaturized contacts without using conventional contact hole opening masks and / or metal-to-0 conversion layers for M1 connections. (3) The gate and / or diffusion (source / drain) regions are self-aligned and directly connected to the metal-2 (M2) interconnection layer without connecting to the metal-1 layer (M1). Thus, the required space between one metal-1 layer (M1) interconnection layer and the other metal-1 layer (M1) interconnection layer, and blocking problems in some wiring connections are reduced. Furthermore, the same structure applies even when the lower metal layer is directly connected to the upper metal layer by a conductor pillar, but the conductor pillar is not electrically connected to any intermediate metal layer between the lower and upper metal layers. (4) The metal wiring for the high-level voltage Vdd and / or low-level voltage VSS within the standard cell can be distributed beneath the initial silicon surface of the silicon substrate, thus avoiding interference between contact sizes and between the layouts of the metal wiring connecting the high-level voltage Vdd and the low-level voltage Vss, etc., even when the size of the standard cell is reduced. Furthermore, the source / drain region openings originally used to electrically couple the source / drain region to the metal-2 layer (M2) or metal-3 layer (M3) for Vdd or ground connection can be omitted in new standard cells and in standard cells.

[0060] Based on the above, Figure 9(a) shows the SRAM bit cell size (λ) that can be seen across different technology nodes from three different companies and the present invention. 2 Figure 9(b) shows the area size of the new standard cell provided by the present invention, compared to that of conventional products provided by various other companies. As shown in Figure 9(a), the area of ​​the newly proposed SRAM cell (the present invention) is approximately 100λ 2 This can be approximately 1 / 8 the area of ​​a conventional 5nm DRAM cell (from three different companies), as shown in Figure 3. Furthermore, as shown in Figure 9(b), the area of ​​a newly proposed standard cell (for example, an inverter cell of 200λ) 2 (It can be as small as or even smaller than) the area of ​​a conventional 5nm standard DRAM cell, as shown in Figure 5, is about 1 / 3.5.

[0061] Therefore, the innovations in the monolithic die design of the Integrated Scaling and / or Stretching Platform (ISSP), along with any combination of proposed techniques (e.g., new transistors, interconnects with transistors, SRAM cells, and standard cell designs), are proposed to provide an integrated system such that the circuit in the original diagram of the die can be reduced in area by two to three times or more.

[0062] From another perspective, more SRAM, or more major different functional blocks (CPU or GPU), can be formed within the original size of a single monolithic die. Thus, the device density and computing performance of integrated systems (such as AI chips or SOCs) can be significantly increased compared to conventional ones of the same size without shrinking the technology nodes required to manufacture the integrated system.

[0063] For example, using a 5nm technology process node, the CMOS 6-T SRAM cell size is approximately 100F, as shown in Figure 9(a). 2 (F is the minimum fabrication dimension on a silicon wafer) can be reduced to this size. That is, if F=5nm, then according to publications, it is approximately 800F. 2 In contrast to the latest cell area, approximately 2500nm 2 In some cases, it can occupy (i.e., be reduced by 8 times). Furthermore, the 8-finger CMOS inverter (shown in Figures 4(a) and 4(b)) is, according to the present invention, 700F of the conventional CMOS inverters that have been published. 2 In contrast to those exceeding 200F 2 This consumes the die area (5nm process node in Figure 9(b)).

[0064] In other words, a single monolithic die has a die area based on the technology process node (for example, Ynm). 2 ) When a monolithic die has circuits occupying the same area (for example, SRAM circuits, logic circuits, a combination of SRAM and logic circuits, or main functional block circuits such as CPU, GPU, FPGA, etc.), with the help of the present invention, the total area of ​​a monolithic die having the same circuits on the same drawing can be shrunk, even if the monolithic die is still manufactured by the same technological process node. The new die area occupied by the same circuits on the same drawing in a monolithic die is Ynm 2 The die area becomes smaller than the original die area, such that it is 20% to 80% (or 30% to 70%) of the original die area.

[0065] For example, Figure 10 shows an integrated system 1000 based on the Integrated Scaling and Stretching Platform (ISSP) of the present invention in comparison with a conventional system. As shown in Figure 10, the ISSP integrated system 1000 and the conventional system 1010 include at least one single monolithic die 1011 having at least one processing unit / circuit or main functional block (e.g., logic circuit 1011A and SRAM circuit 1011B), as well as a pad area 1011C, while the integrated system 1000 provided by the ISSP of the present invention also includes at least one single monolithic die 1001 having logic circuit 1001A, SRAM circuit 801B, and a pad area 1001C. By comparing the configurations of monolithic dies 1011 and 1001 between the conventional system 1010 and the ISSP integrated system 1000, it can be shown that the ISSP of the present invention can reduce the size of the integrated system (monolithic die 1001) or add more devices within the same maximum scanner drawing area (monolithic die 1001') without degrading conventional performance.

[0066] One aspect of reducing the size of the ISSP integrated system 1000 is that, as shown in the center of Figure 10, the single monolithic die 1001 of the ISSP integrated system 1000 has the same circuitry or main functional blocks as the conventional monolithic die 1011 (i.e., the logic circuitry 1001A and SRAM circuitry 1010B of the single monolithic die 1001 are identical to the logic circuitry 1011A and SRAM circuitry 1011B of the single monolithic die 1011), and the single monolithic die 1001 occupies only 20% to 80% (or 30% to 70%) of the maximum scanner drawing area of ​​the conventional monolithic die 1011.

[0067] In one embodiment, the combined area of ​​the SRAM circuit 1001B and logic circuit 1001A within a single monolithic die 1001 shrinks by 3.4 times compared to the area of ​​a conventional monolithic die 1011. That is, compared to a conventional monolithic die 1011, the ISSP of the present invention can lead to a 5.3-fold reduction in the area of ​​the logic circuit 1001A within a single monolithic die 1001, a 5.3-fold reduction in the area of ​​the SRAM circuit 1001B within a single monolithic die 1001, and (as shown in the center of Figure 10) a 3.4-fold reduction in the combined area of ​​the SRAM circuit 1001B and logic circuit 1001A within a single monolithic die 1001.

[0068] From another perspective of adding more devices, as shown on the right in Figure 10, a single monolithic die 1001' and a conventional monolithic die 1001 have the same scanner maximum drawing area. That is, a single monolithic die 1001' is manufactured based on the same technology node as a conventional monolithic die 1011 (such as 5nm or 7nm), and the area of ​​the SRAM circuit 1001B' within the single monolithic die 1001' may not only contain more SRAM cells but also additional major functional blocks not present in the conventional monolithic die 1011. In another embodiment of this disclosure, the die area of ​​a single monolithic die 1001' (as shown on the right in Figure 10) may be similar to, or substantially the same as, the scanner maximum drawing area (SMFA) of a conventional single monolithic die 1011, as defined by a particular technology process node. In other words, based on the ISSP of the present invention, there is additional space within the scanner's maximum drawing area (SMFA) to accommodate additional SRAM cells or additional major functional blocks other than those included in the conventional monolithic die 1011 (logic circuit 1011A and SRAM circuit 1001B).

[0069] Figure 11(a) shows another ISSP integrated system 1100 of the present disclosure. The ISSP integrated system 1100 includes at least one monolithic die 1101 having the size of an SMFA. The monolithic die 1101 includes a processing unit / circuit (e.g., XPU 1101A), an SRAM cache (including high-level and low-level caches), and an I / O circuit 1101B. Each of the SRAM caches includes a set of SRAM arrays. The I / O circuit 1101B is electrically connected to the multiple SRAM caches and / or XPU 1101A.

[0070] In this embodiment, the monolithic die 1101 of the ISSP integrated system 1100 includes different levels of caches L1, L2, and L3, which are generally composed of SRAM. Caches L1 and L2 (collectively "low-level caches") are typically allocated one per CPU or GPU core unit. Cache L1 is divided into L1i and L1d, used for storing instructions and data, respectively; cache L2 does not distinguish between instructions and data; and cache L3 (which may be one of the "high-level caches") is shared by multiple cores and typically does not distinguish between instructions and data. Caches L1 / L2 are typically one per CPU or GPU core.

[0071] For high-speed operation, and therefore based on the ISSP of this disclosure, the die area of ​​the monolithic die 1101 may be the same as or approximately the same as the scanner maximum drawing area (SMFA) defined by a particular technology process node. However, the storage capacity of the cache L1 / L2 (low-level cache) and cache L3 (high-level cache) of the ISSP integrated system 1100 may be increased. As shown in Figure 11(a), a GPU with multiple cores may have an SMFA (e.g., 26mm × 33mm, i.e., 858mm) with a high-level cache of 64MB or more (e.g., 128MB, 256, or 512MB) of SRAM. 2) may have. Furthermore, additional logic cores of the GPU may be inserted into the same SMFA to improve performance. Similarly, for another embodiment, a memory controller (not shown) within the highband I / O 1101B is also possible.

[0072] Alternatively, in addition to the existing major functional blocks, other different major functional blocks, such as FPGAs, may be integrated together within the same monolithic die. Figure 11(b) shows a single monolithic die 1101' of an ISSP integrated system 1100' according to another embodiment of the present disclosure. In this embodiment, the monolithic die 1101' includes at least one broadband I / O 1101B', as well as a plurality of processors / circuits such as XPU 1101A' and YPU 1101C. The processors (XPU 1101A' and YPU 1101C) have major functional blocks, each of which can function as an NPU, GPU, CPU, FPGA, or TPU (tensor processor). The major functional block of XPU 1101A' may differ from that of YPU 1101C.

[0073] For example, the XPU1101A' of the ISSP integrated system 1100' may function as a CPU, and the YPU1101C of the ISSP integrated system 1100' may function as a GPU. Both the XPU1101A' and YPU1101C have multiple logic cores, each core having a low-level cache (e.g., cache L1 / L2 with 512K or 1M / 128K bits) and a high-capacity high-level cache (e.g., cache L3 with 32MB, 64MB or more) shared by the XPU1101A' and YPU1101C, and each of these three levels of cache may include multiple SRAM arrays.

[0074] Given the increasing importance of GPUs for AI learning, FPGAs, which have blocks of logic that interact with each other and can be designed by engineers to support specific algorithms, are well-suited for AI inference. Thus, in some embodiments of this disclosure, an ISSP integrated system 1100” having a single monolithic die 1101” may include a GPU and an FPGA, as shown in Figure 11(c). The configuration of the monolithic die 1101” in Figure 11(c) is the same as that of the monolithic die 1101” in Figure 11(b), except that the XPU 1101A” of the monolithic die 1101” is a GPU or CPU, and the YPU 1101C’ of the monolithic die 1101” is an FPGA. This approach gives the monolithic die 1101” superior parallel computing, learning speed, and efficiency on the one hand, and superior AI inference capabilities with shorter time to market, lower cost, and flexibility on the other hand.

[0075] Furthermore, as shown in Figure 11(c), the processing units / circuits (i.e., XPU1101A” and YPU1101C’) share a high-level cache (e.g., cache L3). The high-level cache (e.g., cache L3) shared between 1101A” and YPU1101C’ can be configured by setting it in a separate mode register (not shown) or adaptively configured during the operation of the monolithic die 1101”. For example, in one embodiment, by setting the mode register, one-third of the high-level cache may be used by XPU1101A” and two-thirds of the high-level cache may be used by YPU1101C’. Such allocated capacity of the high-level cache (e.g., cache L3) for XPU1101A” or YPU1101C’ can also be dynamically changed based on the operation of the Integrated Scaling and / or Stretching Platform (ISSP) for forming the integrated system 1100”.

[0076] Figure 11(d) shows a single monolithic die 1101'' of an ISSP integrated system 1100'''' according to yet another embodiment of the present disclosure. The arrangement of the monolithic die 1101'''' in Figure 11(d) is the same as that of the monolithic die 1101'' in Figure 11(b), except that the high-level cache includes cache L3 and cache L4, each processing unit / circuit (such as XPU 1101A'''' and YPU 1101C'') has cache L3 shared by its own core, and cache L4 having 32 MB or more is shared by the XPU and YPU.

[0077] In some embodiments of this disclosure, a somewhat larger capacity shared SRAM (or embedded SRAM, "eSRAM") may be designed within a single monolithic die for a smaller area of ​​SRAM cell design according to the present invention. Because the high storage capacity of eSRAM can be used, it is faster and more efficient compared to conventional embedded DRAM or external DRAM. Thus, the maximum scanner drawing area (SMFA, e.g., 26 mm × 33 mm, i.e., 858 mm²) 2 It is reasonable and possible to have high-bandwidth / high-capacity SRAM within a single monolithic die having the same or nearly the same die size (e.g., 80% to 99%) as the other.

[0078] Accordingly, the integrated system 1200 provided by the Integrated Scaling and / or Stretching Platform (ISSP) of the present disclosure comprises at least two single monolithic dies, the two monolithic dies of the same or substantially the same size. For example, Figure 12(a) is a diagram showing another ISSP integrated system 1200 according to yet another embodiment of the present disclosure compared to a conventional one 1210. The ISSP integrated system 1200 comprises a single monolithic die 1201 and a single monolithic die 1202 in a single package. The single monolithic die 1201 mainly has logic processing unit circuits and low-level cache formed therein, and the second monolithic die 1202 has only multiple SRAM arrays and I / O circuits formed therein. The multiple SRAM arrays include at least 2 to 20 GB, for example, 2 to 10 GB.

[0079] As shown in Figure 12(a), a single monolithic die 1201 mainly includes logic and I / O circuits 1201A, as well as a small low-level cache (such as L1 and L2 caches) consisting of an SRAM array 1201B, while a single monolithic die 1202 includes only a high-bandwidth SRAM circuit 1202B having 2 to 10 GB or more (e.g., 1 to 20 GB), and I / O circuits 1202A for the high-bandwidth SRAM circuit 1202B. In this embodiment, the SMFA of a single monolithic die 1201 and a single monolithic die 1202 may be approximately 26 mm × 33 mm. If 50% of the SMFA of a single monolithic die 1202 (50% SRAM cell utilization) is used for the SRAM cells of the high-bandwidth SRAM circuit 1202B, the remainder of the SMFA is used for the I / O circuits of the high-bandwidth SRAM circuit 1202B.

[0080] Figure 12(b) shows a comparison of the SRAM cell areas of the integrated system 1200 of the present invention and those of three foundries based on different technology nodes. The total number of bytes (1 bit per SRAM cell) in a 26mm × 33mm SMFA of a single monolithic die (e.g., single monolithic die 1202) can be estimated by referring to the SRAM cell area as shown in Figure 12(b). For example, in this embodiment, the SMFA (26mm × 33mm) of a single monolithic die 1200 can accommodate 21GB of SRAM at a 5nm technology node, and can provide 24GB or more if the SRAM cell utilization rate can be increased.

[0081] As shown in Figure 12(b), the conventional SRAM cell area (of the three foundries) may be 2 to 8 times that of the SRAM cell area of ​​the present invention. Therefore, the ISSP integrated system 1200 can accommodate more bytes (1 bit per SRAM cell) in a 26 mm × 33 mm SMFA than conventional systems. The total number of bytes (1 bit per SRAM cell) in a 26 mm × 33 mm SMFA based on different technology nodes is shown in Table 1 below.

[0082] [Table 1]

[0083] Naturally, considering the various technologies proposed here and the selective use of conventional wiring process techniques, a single monolithic die 1202 SMFA (26mm x 33mm) can accommodate smaller capacities of SRAM, for example, 1 / 4 to 3 / 4 times the SRAM size at the various technology nodes in Table 1 above. For example, a single monolithic die 1202 can accommodate approximately 5 to 15 GB of SRAM, or 2.5 GB to 7.5 GB, through the selective use of the various technologies proposed here and conventional wiring process techniques.

[0084] Figure 13(a) shows a single monolithic die 1301 of another ISSP integrated system 1300 according to the present invention. The arrangement of the single monolithic die 1301 is similar to that of the single monolithic die 1201 in Figure 12(a), except that the single monolithic die 1301 of this embodiment may be a high-performance computing (HPC) monolithic die including a broadband I / O circuit 1301A and two or more main functional blocks such as XPU1301B and YPU1101C, each having multiple cores, and each core of XPU1301B and YPU1301C has its own cache L1 and / or cache L2 (L1 ~ 128KB and L2 ~ 512KB to 1MB). The main functional blocks of XPU1301B or YPU1301C in Figure 13(a) may be an NPU, GPU, CPU, FPGA, or TPU (tensor processing unit), each of which has a main functional block. The XPU1301B or YPU1301C may have different main functional blocks.

[0085] Figure 13(b) shows a single monolithic die 1302 of the ISSP integrated system 1300. The arrangement of the single monolithic die 1302 is the same as that of the single monolithic die 1202 in Figure 12(a), except that the single monolithic die 1302 is a high-bandwidth SRAM (HBSRAM). In this embodiment, the single monolithic die 1302 has an SMFA identical to (or having about 80-90% of the area of) a modern SMFA, and includes only a cache L3 and / or L4 with multiple SRAM arrays, as well as an SRAM I / O circuit 1302A with high-bandwidth 1302B I / O for the SRAM I / O circuit 1302A. The total SRAM within the single monolithic die 1302 can be 2-5GB, 5-10GB, 10-15GB, 15-20GB, or more, depending on the utilization rate of the SRAM cells. Such a single monolithic die 1302 could be a high-bandwidth DRAM (HBSRAM).

[0086] As shown in Figures 13(a) and 13(b), a single monolithic die 1301 and a single monolithic die 1302 each have a broadband I / O bus, for example, a 64-bit, 128-bit, or 256-bit data bus. The single monolithic die 1301 and the single monolithic die 1302 may be in the same IC package or in separate IC packages. For example, in some embodiments, a single monolithic die 1301 (e.g., an HPC die) is coupled to a single monolithic die 1302 (e.g., by wire bonding, flip-chip bonding, solder bonding, 2.5D interposed through-silicon (TSV) bonding, 3D micro-copper pillar direct bonding), as shown in Figure 14, and housed in a single package to form an integrated system 1400. In embodiments, both a single monolithic die 1301 and a single monolithic die 1302 have the same or substantially the same SMFA, and such coupling may be completed by directly coupling a wafer 14A having at least one monolithic die 1301 (or having multiple dies) to another wafer 14B having at least one monolithic die 1302 (or having multiple dies), and the coupled wafers 14A and 14B are then sliced ​​into multiple SMFA blocks to form an integrated system 1400 provided by the ISSP of this disclosure. It is conceivable that another interpolation having TSVs may be inserted between the single monolithic die 1301 and the single monolithic die 1302.

[0087] Figure 15 shows another ISSP integration system 1500 according to the present disclosure. The integration system 1500 includes two or more single monolithic dies 1302 coupled together (i.e., two HBSRAM dies as shown in Figure 13(b)), one of the two single monolithic dies 1302 then coupled to a single monolithic die 1301 (e.g., an HPC die as shown in Figure 13(a)), and then all three or more dies are housed in a single package. Thus, such a package may include an HPC die and more than 42, 48, or 96 GB of HBSRAM. Naturally, two or more single monolithic dies 1302 and a single monolithic die 1301 with a high-bandwidth I / O bus can be stacked vertically and coupled together based on state-of-the-art coupling techniques.

[0088] Naturally, three, four, or five or more HBSRAM dies may be integrated within a single package of the integrated system 1500, in which case the caches L3 and L4 within the integrated system 1500 may be larger than 128GB or 256GB of SRAM. In some embodiments of this disclosure, the single monolithic dies 1301 and 1302 of the integrated system 1500 may be housed within the same IC package.

[0089] Compared to currently available HBM DRAM memory, which includes approximately 24GB based on a stack of 12 DRAM chips, the present invention can replace HBM3 memory with more HBSRAM (e.g., one HBSRAM chip having approximately 5-10GB or 15-20GB). Therefore, within the ISSP, HMB memory is not required, or only a small amount of HBM memory (e.g., less than 4GB or 8GB of HBM) is needed.

[0090] Monolithic integration on a single die, which would enable the achievement of Moore's Law, is currently facing its limitations, particularly due to the limitations of photographic printing technology. On the one hand, the minimum processing dimensions printed on the die are extremely costly to miniaturize to that dimension, while on the other hand, the die size is limited by the maximum scanning area. However, the emergence of more diverse and multifaceted functions in processors makes them difficult to integrate on a monolithic die. Furthermore, the presence of small eSRAM on each major function die, and the somewhat overlapping presence of external or embedded DRAM, is not a desirable or optimized solution. Based on an Integrated Scaling and / or Stretching Platform (ISSP) within a monolithic die or SOC die, (1) A single main functional block such as an FPGA, TPU, NPU, CPU, or GPU can be reduced to a much smaller size. (2) More SRAM can be formed within a monolithic die, and (3) Two or more major functional blocks, such as a GPU and an FPGA (or any other combination thereof), which have also been miniaturized through this ISSP, can be integrated together on the same monolithic die. (4) More levels of cache may exist within the monolithic die. (5) Such ISSP monolithic dies can be combined with other dies (e.g., eDRAM) based on heterogeneous integration. (6) The HPC die 1 having the L1 and L2 caches is electrically connected (e.g., by wire bonding or flip-chip bonding) to one or more HBSRAM dies 2 which are used as L3 and L4 caches in a single package, and each of the HPC die 1 and HBSRAM die 2 has an SMFA. (7) Within the ISSP, HMB memory is not required, or only a small amount of HMB memory is required.

[0091] While the present invention has been described by example and by preferred embodiments, it should be understood that the invention is not limited thereto. In contrast, it is intended to encompass various modifications, as well as similar arrangements and procedures, and therefore the scope of the appended claims should be given the broadest interpretation to encompass all such modifications, as well as similar arrangements and procedures.

Claims

1. A first monolithic die in which a processing unit circuit is formed therein, wherein the processing unit circuit comprises a first processing unit circuit and a second processing unit circuit, the first processing unit circuit includes a plurality of first logic cores, each of the plurality of first logic cores corresponding to a first low-level cache, the second processing unit circuit includes a plurality of second logic cores, each of the plurality of second logic cores corresponding to a second low-level cache, the main function performed by the first processing unit circuit is different from the main function performed by the second processing unit circuit, and the first processing unit circuit or the second processing unit circuit is selected from the group consisting of a graphics processing unit (GPU), a central processing unit (CPU), a tensor processing unit (TPU), a network processing unit (NPU), and a field-programmable gate array (FPGA), and A second monolithic die in which multiple SRAM arrays are formed It is equipped with, The first processing unit circuit, the second processing unit circuit, or one transistor in the plurality of SRAM arrays comprises a semiconductor substrate including an initial semiconductor surface, a gate structure within the semiconductor substrate, a spacer covering the side wall of the gate structure, a first trench and a second trench formed within the semiconductor substrate, a source region disposed within the first trench, a drain region disposed within the second trench, and a shallow trench isolation (STI) region surrounding the first trench and the second trench, the upper surface of which is not lower than the upper surface of the source region or the drain region. The first monolithic die is electrically connected to the second monolithic die. An integrated system in which the die area of ​​the first monolithic die is the same as or approximately the same as the die area of ​​the second monolithic die.

2. The die area of ​​the first monolithic die is the same as or approximately the same as the maximum scanner drawing area defined by a specific technology process node, and is 858 mm². 2 Do not exceed, The integrated system according to claim 1.

3. The localized isolation region below the initial semiconductor surface, the localized isolation region located below the source region or the drain region, and the edges of the source region or the drain region are aligned or substantially aligned with the edges of the gate structure or the spacer. The integrated system according to claim 1.

4. The first monolithic die and the second monolithic die are housed in a single package. The plurality of SRAM arrays comprises at least 2 to 20 GB. The integrated system according to claim 1.

5. The first low-level cache of the first monolithic die includes at least an L1 cache that is used by the processing unit circuit during the operation of the first monolithic die. The second low-level cache of the first monolithic die includes at least an L1 cache that is used by the processing unit circuit during the operation of the first monolithic die. The plurality of SRAM arrays include at least an L3 cache that is used by the processing unit circuit during the operation of the first monolithic die. The integrated system according to claim 1.

6. It further comprises a third monolithic die in which multiple SRAM arrays are formed, The third monolithic die described above has at least 2 to 20 GB, The first monolithic die, the second monolithic die, and the third monolithic die are housed in a single package. The die area of ​​the third monolithic die is the same as or approximately the same as the die area of ​​the first monolithic die. The integrated system according to claim 1.

7. The first monolithic die, the second monolithic die, and the third monolithic die are stacked in the vertical direction. The integration system according to claim 6.

8. The upper surface of the STI region is higher than the initial semiconductor surface. The source region or the drain region has substantially upright side walls surrounded by the STI region. The integrated system according to claim 1.

9. It is an integrated system, A first monolithic die having a processing circuit, wherein the processing circuit comprises a first processing circuit and a second processing circuit, the first processing circuit includes a plurality of first logic cores, each of the plurality of first logic cores corresponding to a first SRAM size including an L1 cache and an L2 cache, the second processing circuit includes a plurality of second logic cores, each of the plurality of second logic cores corresponding to a second SRAM size, the main function performed by the first processing circuit is different from the main function performed by the second processing circuit, and the first processing circuit or the second processing circuit is selected from the group consisting of GPU, CPU, TPU, NPU, and FPGA, and A second monolithic die having multiple SRAM arrays It is equipped with, The first processing unit circuit, the second processing unit circuit, or one transistor in the plurality of SRAM arrays comprises a semiconductor substrate having an initial semiconductor surface, a gate structure within the semiconductor substrate, a spacer covering the side wall of the gate structure, a first trench and a second trench formed in the semiconductor substrate, a source region disposed in the first trench, a drain region disposed in the second trench, and a shallow trench isolation (STI) region surrounding the source region and the drain region, the upper surface of which is higher than the initial semiconductor surface. The first monolithic die is physically separated from the second monolithic die. The first monolithic die is electrically connected to the second monolithic die. The die area of ​​the first monolithic die is the same as or approximately the same as the die area of ​​the second monolithic die, and the die area of ​​the first monolithic die is 858 mm². 2 It does not exceed that.

10. The system further comprises a metal contact plug deposited in the hole between the STI region and the gate structure. The integrated system according to claim 9.

11. The die area of ​​the first monolithic die is the same as or approximately the same as the maximum scanner drawing area defined by a specific technology process node. The first monolithic die and the second monolithic die are housed in a single package. The first monolithic die is electrically connected to the second monolithic die by wire bonding, flip-chip bonding, solder bonding, interposed through-silicon (TSV) bonding, or micro-copper pillar direct bonding. The integrated system according to claim 9.

12. The aforementioned integrated system does not include high-bandwidth memory (HBM). The integrated system according to claim 9.

13. A first monolithic die having a processing circuit, wherein the processing circuit comprises a first processing circuit and a second processing circuit, the first processing circuit includes a plurality of first logic cores, each of the plurality of first logic cores corresponding to a first SRAM size including an L1 cache and an L2 cache, the second processing circuit includes a plurality of second logic cores, each of the plurality of second logic cores corresponding to a second SRAM size, the main functions performed by the first processing circuit are different from the main functions performed by the second processing circuit, and the first processing circuit or the second processing circuit is selected from the group consisting of GPU, CPU, TPU, NPU, and FPGA, and A second monolithic die having multiple SRAM arrays It is equipped with, The first processing unit circuit, the second processing unit circuit, or one transistor in the plurality of SRAM arrays comprises a semiconductor substrate having an initial semiconductor surface, a gate structure in the semiconductor substrate, a spacer covering the sidewall of the gate structure, a first trench and a second trench formed in the semiconductor substrate, a source region disposed in the first trench, a drain region disposed in the second trench, wherein the source region or the drain region includes an epitaxially doped semiconductor layer and a metal layer in contact with the outermost sidewall of the epitaxially doped semiconductor layer, and a shallow trench isolation (STI) region surrounding the first trench and the second trench. The first monolithic die is electrically connected to the second monolithic die. The first monolithic die and the second monolithic die are housed in a single package, or the first monolithic die and the second monolithic die are housed in a first package and a second package, respectively. The die area of ​​the first monolithic die is the same as or approximately the same as the die area of ​​the second monolithic die, and the die area of ​​the first monolithic die is 858 mm². 2 An integrated system that does not exceed a certain limit.

14. The upper surface of the STI region is higher than the initial semiconductor surface. The integration system according to claim 13.

15. The source region or the drain region has substantially upright side walls surrounded by the STI region. The integration system according to claim 14.

Images