Hybrid bonding contact structure for 3D memory devices

Abstract

To provide a through array contact structure of a 3D memory device and a manufacturing method thereof.SOLUTION: A memory device includes an alternate layer stack arranged on a first substrate. The alternate layer stack is constituted of a first region including an alternate dielectric stack and a second region including an alternate conductor / dielectric stack. The memory device further includes: a barrier structure extended vertically through the alternate layer stack so as to horizontally separate the first region from the second region; a plurality of through array contacts in the first region in which the through array contacts are respectively vertically extended through the alternate dielectric stack; an array interconnection layer brought into contact with the through array contact; a peripheral circuit formed on a second substrate; and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is combined on the peripheral interconnection layer so that the peripheral circuit is electrically connected to at least one through array contact.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001] (Cross-Reference to Related Applications) This application claims the priority benefit of Chinese Patent Application No. 201710135655.3 filed on March 8, 2017, the entire content of which is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Background Art

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become more challenging and costly. As a result, the memory density for planar memory cells approaches an upper limit.

[0004] 3D memory architectures can address the density limitations in planar memory cells. This 3D memory architecture includes a memory array and peripheral devices that control signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of a Through Array Contact (TAC) structure for 3D memory devices and fabrication methods thereof are disclosed herein.

[0006] A three-dimensional (3D) NAND memory device is disclosed, which includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack comprising a plurality of dielectric layer pairs, and a second region including an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs. The 3D NAND memory device further includes a barrier structure extending perpendicularly through the alternating layer stack so as to laterally separate the first region from the second region, a plurality of through-array contacts within the first region, each through-array contact extending perpendicularly through the alternating dielectric stack, an array interconnection layer in contact with the plurality of through-array contacts, a peripheral circuit formed on the second substrate, and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is coupled on the peripheral interconnection layer such that the peripheral circuit is electrically connected to at least one of the plurality of through-array contacts.

[0007] In some embodiments, the array interconnect layer is disposed on the alternating layer stack at the end of the alternating layer stack opposite the first substrate. In some other embodiments, the array interconnect layer is disposed on the surface of the first substrate opposite the alternating layer stack.

[0008] The array interconnect layer includes at least one first interconnect structure embedded in the first dielectric layer. The peripheral interconnect layer includes at least one second interconnect structure embedded in the second dielectric layer. The peripheral circuit is electrically connected to at least one of a plurality of through-array contacts via at least one first interconnect structure and at least one second interconnect structure.

[0009] The barrier structure is composed of silicon oxide and silicon nitride. Each of the multiple dielectric layer pairs consists of a silicon oxide layer and a silicon nitride layer, and each of the multiple conductor / dielectric layer pairs consists of a metal layer and a silicon oxide layer. The number of multiple dielectric layer pairs is at least 32, and the number of multiple conductor / dielectric layer pairs is at least 32.

[0010] The 3D NAND memory device further includes multiple slit structures extending vertically and laterally along the word line direction, respectively, through the alternating conductor / dielectric stack to divide the alternating conductor / dielectric stack into multiple memory fingers.

[0011] In some embodiments, the barrier structure extends laterally along the word line direction. The first region is separated from the second region by the barrier structure and is sandwiched between two adjacent slit structures.

[0012] In some embodiments, the barrier structure extends laterally along a bit line direction different from the word line direction, so as to laterally separate a first region from a second region. The bit line direction may be perpendicular to the word line direction.

[0013] In some embodiments, the width of the first region surrounded by the bit-line barrier structure is greater than the distance between two adjacent slit structures.

[0014] In some embodiments, a first region surrounded by a barrier structure is sandwiched between two top selective gate stair regions in the word line direction. At least two upper layers of the alternating conductor / dielectric stack away from the first substrate within each top selective gate stair region have a stair structure. At least one conductive layer on the stair structure within the top selective gate stair region is configured to interconnect top select gates located above the alternating conductor / dielectric stack in a second region and on both sides of the first region surrounded by a barrier structure in the word line direction. At least two first regions are surrounded by corresponding barrier structures, with each first region extending parallel to the bit line direction.

[0015] The 3D NAND memory device further includes multiple barrier structures surrounding a plurality of first regions from a second region such that the plurality of first regions are aligned in the bit line direction. Each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction. The plurality of first regions are aligned so as to form at least two columns in the bit line direction.

[0016] In some embodiments, at least one slit structure, sandwiched between two adjacent barrier structures in the bit line direction, includes a gap, and the at least one slit structure is configured to interconnect the word lines of adjacent memory fingers among a plurality of memory fingers.

[0017] In some embodiments, the first region is separated by a barrier structure from a stepped structure on the edge of the alternating conductor / dielectric layer stack along the bit line direction. The opening of the barrier structure is located at the edge of the alternating layer stack along the bit line direction. The width of the first region in the bit line direction is greater than the distance between two adjacent slit structures. Alternatively, the width of the first region in the bit line direction is less than the maximum distance between two adjacent slit structures in the stepped structure on the edge of the alternating layer stack along the bit line direction.

[0018] A 3D NAND memory device comprises multiple dummy channel structures adjacent to a barrier structure, each dummy channel structure further comprising multiple dummy channel structures extending vertically through an alternating conductor / dielectric stack.

[0019] Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) NAND memory device, comprising the steps of forming an alternating dielectric stack on a first substrate, the alternating dielectric stack comprising a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; and forming at least one barrier structure, each extending perpendicularly through the alternating dielectric stack. The at least one barrier structure separates the alternating dielectric stack into at least one first region and a second region, each laterally surrounded by at least the barrier structure. The method further includes the steps of forming a plurality of slits to form an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs, and replacing a first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits; depositing a conductive material in the slits to form a plurality of slit structures; forming a plurality of through-array contacts in a first region, each through-array contact extending perpendicularly through the alternating dielectric stack; forming an array interconnect layer in contact with the plurality of through-array contacts; and coupling the array interconnect layer to a peripheral interconnect layer on a second substrate such that at least one of the plurality of through-array contacts is electrically connected to a peripheral circuit on a second substrate.

[0020] In some embodiments, the step of forming an array interconnect layer includes forming at least one first interconnect structure on a first dielectric layer located on the alternating layer stack at the end of the alternating layer stack opposite the first substrate. In some other embodiments, the step of forming an array interconnect layer includes forming at least one first interconnect structure on a first dielectric layer located on the surface of the first substrate opposite the alternating layer stack.

[0021] The method further includes forming a peripheral circuit on a second substrate before coupling the array interconnect layer to the peripheral interconnect layer, forming the peripheral interconnect layer on the peripheral circuit such that at least one second interconnect structure in the peripheral interconnect layer is electrically connected to the peripheral circuit, and disposing the array interconnect layer and the peripheral interconnect layer such that each at least one first interconnect structure corresponds to the at least one second interconnect structure, respectively.

[0022] The method further includes, before the step of forming slits, forming a plurality of doped regions in the first substrate such that each slit structure is in contact with the corresponding doped region.

[0023] The method further includes laterally forming a plurality of slit structures extending along the word line direction so as to divide the alternating conductor / dielectric stack into a plurality of memory fingers.

[0024] The method further includes laterally forming two parallel barrier structures extending along the word line direction such that the first region is separated from the second region by the two parallel barrier structures and is sandwiched between two adjacent slit structures.

[0025] The method further includes forming a barrier structure extending laterally along a bit line direction different from the word line direction so as to laterally separate the first region from the second region.

[0026] The method further includes the step of forming a barrier structure extending laterally along the bit line direction orthogonal to the word line direction.

[0027] The method further includes forming the barrier structure such that the width in the bit line direction of the first region surrounded by the barrier structure is greater than the distance between two adjacent slit structures.

[0028] The method further includes the step of forming a staircase structure in the alternating dielectric stack adjacent to the barrier structure.

[0029] The method further comprises forming at least one conductive layer on the staircase structure adjacent to the barrier structure so as to interconnect upper select gates on both sides of the first region, which is above the alternating conductor / dielectric stack in the second region and surrounded by the barrier structure in the word line direction.

[0030] The method further comprises forming at least two barrier structures to enclose the at least two first regions extending parallel along the bit line direction.

[0031] The method further comprises forming a plurality of barrier structures surrounding the plurality of first regions arranged in the bit line direction from the second region, such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction.

[0032] The method further comprises forming the plurality of barrier structures such that the plurality of first regions surrounded by the plurality of barrier structures are arranged in at least two columns in the bit line direction.

[0033] The method further comprises forming a gap in at least one slit structure sandwiched by two adjacent barrier structures in the bit line direction, so as to interconnect the word lines of adjacent memory fingers.

[0034] The method further comprises forming a barrier structure to separate the first region in the staircase structure at the edge of the alternating stack. The opening of the barrier structure is located at the edge of the alternating layer stack along the bit line direction different from the word line direction.

[0035] The method further comprises forming the barrier structure such that the width of the first region in the bit line direction is greater than the distance between two adjacent slit structures.

[0036] The method further includes the step of forming a barrier structure such that the width of a first region in the bit line direction is less than the maximum distance between two adjacent slit structures within the staircase structure.

[0037] The method further includes the step of forming a plurality of dummy channel structures adjacent to a barrier structure, each dummy channel structure extending vertically through an alternating conductor / dielectric stack.

[0038] Other aspects of this disclosure will be understood by those skilled in the art in view of the specification, claims, and drawings of this disclosure.

[0039] The accompanying drawings incorporated herein and forming part thereof illustrate embodiments of the present disclosure, and together with the detailed description, further explain the principles of the present disclosure and enable those skilled in the art to construct and use the present disclosure. [Brief explanation of the drawing]

[0040] [Figure 1] This is a schematic diagram in plan view of an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 2] A schematic enlarged plan view of a region of a 3D memory device, including an exemplary bit-line through-array contact region according to some embodiments of the present disclosure. [Figure 3A] This disclosure shows schematic enlarged plan views of regions of a 3D memory device, including various exemplary word line through array contact regions according to several embodiments of this disclosure. [Figure 3B] This disclosure shows schematic enlarged plan views of regions of a 3D memory device, including various exemplary word line through array contact regions according to several embodiments of this disclosure. [Figure 3C] This disclosure shows schematic enlarged plan views of regions of a 3D memory device, including various exemplary word line through array contact regions according to several embodiments of this disclosure. [Figure 3D]This disclosure shows schematic enlarged plan views of regions of a 3D memory device, including various exemplary word line through array contact regions according to several embodiments of this disclosure. [Figure 4A] A schematic enlarged plan view of a region of a 3D memory device including various exemplary stepped through-array contact regions according to several embodiments of the present disclosure. [Figure 4B] A schematic enlarged plan view of a region of a 3D memory device including various exemplary stepped through-array contact regions according to several embodiments of the present disclosure. [Figure 5A] The following are schematic cross-sectional views of exemplary 3D memory devices at several manufacturing stages according to some embodiments of the present disclosure. [Figure 5B] The following are schematic cross-sectional views of exemplary 3D memory devices at several manufacturing stages according to some embodiments of the present disclosure. [Figure 6A] This is a flowchart illustrating an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 6B] This is a flowchart illustrating an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 7A] These are schematic cross-sectional views of an exemplary 3D memory device at some manufacturing stages of the method shown in Figures 6A-6B according to some embodiments of the present disclosure. [Figure 7B] These are schematic cross-sectional views of an exemplary 3D memory device at some manufacturing stages of the method shown in Figures 6A-6B according to some embodiments of the present disclosure. [Figure 7C] These are schematic cross-sectional views of an exemplary 3D memory device at some manufacturing stages of the method shown in Figures 6A-6B according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0041] Embodiments of this disclosure will be described with reference to the attached drawings.

[0042] While specific configurations and arrangements are described, it should be understood that these are done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the gist and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other purposes.

[0043] It should be noted that references in this specification such as “one embodiment,” “embodiment,” “exemplary embodiment,” and “several embodiments” indicate that the described embodiments may include certain features, structures, or characteristics, but not all embodiments may necessarily include these features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when certain features, structures, or characteristics are described in relation to an embodiment, it is within the knowledge of those skilled in the art that such features, structures, or characteristics may result in other embodiments, whether explicitly stated or not.

[0044] In general, technical terms can be understood, at least in part, from their usage in context. For example, when used herein, the term “one or more” can be used, at least in part, in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe any combination of features, structures, or characteristics, depending at least in part, in context. Similarly, terms such as “a,” “an,” or “the” can also be understood, at least in part, to convey either a singular or plural usage.

[0045] The meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, so that it should be easily understood that “on” not only means “directly on” something, but also means “on” something with an intermediate feature or layer between them, and that “above” or “over” means not only “above” or “over” something, but also means “above” or “over” something (i.e., directly on something) without an intermediate feature or layer between them.

[0046] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate the description of the relative relationship between one element or feature and another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. Otherwise, the device may be oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0047] As used herein, the term “substrate” refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or unpatterned. Furthermore, the substrate can consist of a wide array of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0048] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend across the entire substrate or superstructure, or may have a smaller extent than the substrate or superstructure. Furthermore, a layer may be a region of a uniform continuous structure, or a non-uniform continuous structure having a thickness less than the thickness of the uniform continuous structure. For example, a layer may be located between any pair of horizontal planes, either between continuous structures or on an upper and lower surface. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, may contain one or more layers internally, and / or have one or more layers on top of, above, and / or below it. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductive layers and contact layers (on which contacts, interconnection lines, and / or vias are formed) and one or more dielectric layers.

[0049] When used herein, the term “nominal / nominal” refers to a desired or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​is obtained due to slight variations or tolerances in the manufacturing process. When used herein, the term “about” indicates a value of a given quantity that may vary based on a particular technology node related to the semiconductor device of the subject. Based on a particular technology node, the term “about” may indicate a value of a given quantity that varies, for example, within a range of 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0050] As used herein, the term “3D memory device” refers to a semiconductor device having a vertically oriented string of memory cell transistors on a substrate oriented laterally such that the memory strings extend perpendicularly to the substrate (i.e., a region as used herein, such as NAND strings, or “memory strings”). As used herein, the term “vertical / perpendicular” nominally means perpendicular to the side of the substrate.

[0051] Various embodiments of this disclosure provide 3D memory devices having through-array contact (TAC) structures for memory arrays (also referred to herein as “array devices”). The TAC structure allows contacts between the memory and various peripheral circuits and / or peripheral devices (e.g., page buffers, latches, decoders, etc.) to be manufactured in a limited number of steps (e.g., in one or two steps), thereby reducing process complexity and manufacturing costs. The disclosed TACs are formed through a stack of alternating dielectric layers, which may make etching to form through-holes inside easier compared to a stack of alternating conductive layers and dielectric layers.

[0052] TACs can enable vertical interconnection between stacked array devices and peripheral devices (e.g., for power buses and metal routing), thereby reducing the metal level and the size of the shrinking die. In some embodiments, TACs can interconnect with various lines in the upper and / or lower conductive layers, which is suitable for 3D memory architectures where array devices and peripheral devices formed on different substrates are formed sequentially or joined face-to-face by hybrid bonding. In some embodiments, the TACs in the through-array contact structures disclosed herein are formed through a stack of alternating dielectric layers, which may make etching to form through-holes internally easier compared to a stack of alternating conductor and dielectric layers, thereby reducing process complexity and manufacturing costs.

[0053] Figure 1 shows a schematic plan view of an exemplary 3D memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 may include a plurality of channel structure regions (e.g., memory planes, memory blocks, memory fingers, etc., which will be described in detail in relation to the various figures below), while one or more TAC structures may be formed between two adjacent channel structure regions (e.g., two adjacent channel structure regions).

[0054] As shown in Figure 1, the 3D memory device 100 may include four or more memory planes 110, and each memory plane 110 may include multiple memory blocks 115. Note that the arrangement of the memory planes 110 within the 3D memory device 100 and the arrangement of the memory blocks 115 within each memory plane 100 shown in Figure 1 are for illustrative purposes only and do not limit the scope of this disclosure.

[0055] The TAC structure may include one or more bit line (BL) TAC regions 160 that are sandwiched between two adjacent memory blocks 115 in the bit line direction of the 3D memory device (named "BL" in the figure) and extend along the word line direction of the 3D memory device (named "WL" in the figure), one or more word line (WL) TAC regions 170 that are sandwiched between two adjacent memory blocks 115 in the word line direction (WL) and extend along the bit line direction (BL), and one or more stepped structure (SS) TAC regions 180 located at the edges of each memory plane 110.

[0056] In some embodiments, the 3D memory device 100 may include a plurality of contact pads 120 arranged in a row along the edge of the 3D memory device 100. The interconnection contacts can be used to electrically interconnect the 3D memory device 100 to any suitable device and / or interface that provides driving power, receives control signals, transmits response signals, and so on.

[0057] Figure 2 shows an enlarged plan view of region 130 shown in Figure 1, including an exemplary bit line (BL) TAC region 160 of the 3D memory device. Figures 3A to 3D show enlarged plan views of region 140 shown in Figure 1, including various exemplary word line (WL) TAC regions 170 of the 3D memory device. Figures 4A and 4B show enlarged plan views of region 150 shown in Figure 1, including various exemplary stepped structure (SS) TAC regions 180 of the 3D memory device.

[0058] Referring to Figure 2, an enlarged plan view of region 130 shown in Figure 1 is shown, which includes an exemplary bit line (BL)TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 200 of the 3D memory device (i.e., region 130 as shown in Figure 1) may include two channel structure regions 210 (e.g., adjacent memory blocks 115 in the BL direction) and a bit line (BL)TAC region 233 (e.g., BL TAC region 160 as shown in Figure 1).

[0059] The channel structure region 210 may include an array of channel structures 212, each of which is part of a NAND string containing multiple stacked memory cells. The channel structures 212 extend through multiple pairs of conductive and dielectric layers arranged along a direction perpendicular to the plan view, also called the direction perpendicular to the surface of the substrate of the 3D memory device, and / or along the “perpendicular direction” (shown in the cross-sectional view in relation to Figure 5, which will be described in detail below).

[0060] Multiple conductor / dielectric layer pairs are also referred to herein as “alternating conductor / dielectric stacks.” The number of conductor / dielectric layer pairs in an alternating conductor / dielectric stack (e.g., 32, 64, or 96) can determine the number of memory cells in the 3D memory device 100. The conduction and dielectric layers in the alternating conductor / dielectric stack are alternating in the vertical direction. In other words, except for those at the top or bottom of the alternating conductor / dielectric stack, each conduction layer may be adjacent to two dielectric layers on either side, and each dielectric layer may be adjacent to two conduction layers on either side.

[0061] The conductive layer may consist of conductive materials including, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer may consist of dielectric materials including, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer consists of a metal layer such as W, and the dielectric layer consists of silicon oxide.

[0062] In some embodiments, the BL TAC region 233 may be sandwiched between two adjacent channel structure regions 210 in the BL direction and may extend in the WL direction. The TAC region 233 may be defined by a barrier structure 224 in relation to the edge of the BL TAC region 233 of the 3D memory device. Multiple TACs 226 can be formed within the BL TAC region 233, which is laterally surrounded by the barrier structure 224 and the edge of the BL TAC region 233. In some embodiments, multiple TACs 226 within the BL TAC region 233 may penetrate the alternating dielectric stack to switch routing and reduce bit line capacitance.

[0063] An alternating dielectric stack may include a plurality of dielectric layer pairs arranged perpendicular to the surface of the substrate of a 3D memory device (as shown in the cross-sectional view in relation to Figure 5, which will be described in detail below). Each dielectric layer pair includes a first dielectric layer and a second dielectric layer distinct from the first dielectric layer. In some embodiments, the first and second dielectric layers include silicon nitride and silicon oxide, respectively. The first dielectric layer in the alternating dielectric stack may be the same as the dielectric layer in the alternating conductor / dielectric stack described above. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack is the same as the number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack.

[0064] As shown in Figure 2, each channel structure region 210 may include one or more slit structures 214 extending in the WL direction. At least some of the slit structures 214 can function as common source contacts for the array of channel structures 212 within the channel structure region 210. The slit structures 214 can also divide the 3D memory device into multiple memory fingers 242 and / or dummy memory fingers 246. A top select gate cut 255 may be located in the center of each memory finger 242 to divide the top select gate (TSG) of the memory finger into two parts. The top select gate cut 255 may be made of a dielectric material including, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0065] In some embodiments, the dummy channel structure 222 is formed, for example, in a portion of the channel structure region 210 within a dummy memory finger 246 adjacent to the BL TAC region 233 in the BL direction. The dummy channel structure 222 can provide mechanical support to the memory array structure. The dummy memory finger 246 does not have memory functionality, and therefore no bit lines and associated interconnection lines are formed within the dummy memory finger 246.

[0066] Referring to Figure 3A, an enlarged plan view of region 140 shown in Figure 1 is shown, including an exemplary word line (WL)TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 300A of the 3D memory device (i.e., region 140 as shown in Figure 1) may include a channel structure region 320, a word line (WL)TAC region 372 (e.g., a WL TAC region 170 as shown in Figure 1), and an upper selection gate (TSG) stair region 330.

[0067] As shown in Figure 3A, the channel structure region 320 may include an array of channel structures 312, each containing multiple stacked memory cells. The TSG stair region 330 may be located on both sides of the channel structure region 320 and adjacent to the WL TAC region 372 in the plan view. That is, the WL TAC region 372 is sandwiched between two TSG stair regions 330 in the WL direction. The WL TAC region 372 may be defined by a barrier structure 324. Multiple TACs 326 used for routing switching and reducing word line capacitance may be formed within the WL TAC region 372, which is surrounded laterally by the barrier structure 324.

[0068] In some embodiments, the dummy channel structure 322 is formed outside the WL TAC region 372 to provide mechanical support to the memory array structure. It is understood that the dummy channel structure 322 may be formed in any region outside the WL TAC region 372, for example, within the TSG stair region 330 and along the edge of the channel structure region 320 adjacent to the TSG stair region 330. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0069] In some embodiments, multiple slit structures 314, each extending in the WL direction, can divide the 3D memory device into multiple memory fingers 342, 344. At least some slit structures 314 can function as common source contacts for an array of channel structures 312 within a channel structure region 320. The sidewalls of the slit structures 314 may contain dielectric materials, but are not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The fillers of the slit structures 314 may contain conductive materials, but are not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof.

[0070] The upper select gate cut 355 may be located in the center of each memory finger 342, 344 to divide the upper select gate (TSG) of the memory finger into two parts. The upper select gate cut 355 may be made of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0071] It should be noted that the width of the WL TAC region 372 in the BL direction can be greater than the width of each memory finger 342 or 344. That is, the barrier structure 324 in the BL direction can span at least two adjacent slit structures 314. Thus, the conductive layer in the channel structure region 320 within the memory finger 344 can be completely blocked by the barrier structure 324. Consequently, the upper select gates of the channel structure 312 between the two channel structure regions 320 within the memory finger 344 on either side of the WL TAC region 372 are not interconnected by the upper conductive layer in the alternating conductor / dielectric stack.

[0072] To interconnect the upper selection gates of the channel structure 312 between the two channel structure regions 320 within the memory fingers 344 on either side of the WL TAC region 372, the TSG stair region 330 may include one or more conductive wires (not shown in Figure 3A) formed in a stair structure (e.g., within the upper 2-4 levels) to electrically interconnect with the upper selection gates of the channel structure 312 between the two channel structure regions 320 within the memory fingers 344 separated by the WL TAC region 372.

[0073] For example, a slit structure 314 cut out by the WL TAC region 372 may extend into the TSG step region 330. The top two conductive layers in the alternating conductor / dielectric stack may have a one-sided step structure. One or more interconnection layers having contacts may be formed on the one-sided step structure to provide an electrical interconnection between the upper select gate of the channel structure 312 in the channel structure region 320 separated by the WL TAC region 372 and the upper select gate of the channel structure 312 of the memory finger 344.

[0074] Therefore, by introducing TSG stair regions 330 that interconnect upper selection gates on both sides of the WL TAC region 372, the WL TAC region 372 can extend along the BL direction to give it a size sufficient to enclose a desired number of TACs 326. Furthermore, each memory plane 110 can include multiple WL TAC regions 372 arranged in the WL direction, as shown in Figure 1. That is, multiple memory blocks 115 may be arranged in the WL direction within each memory plane 110.

[0075] Referring to Figure 3B, an enlarged plan view of region 140 shown in Figure 1 is shown, including another exemplary word line (WL)TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300B of the 3D memory device (i.e., region 140 as shown in Figure 1) may include a channel structure region 320 and a dummy channel region 350 surrounding a word line (WL)TAC region 372 (e.g., WL TAC region 170 as shown in Figure 1).

[0076] As shown in Figure 3B, the channel structure region 320 may contain an array of channel structures 312, each containing multiple stacked memory cells. The dummy channel region 350 is sandwiched between two channel structure regions 320 in the WL direction. The WL TAC region 372 is surrounded by the dummy channel region 350. The WL TAC region 372 may be defined by a barrier structure 324. Multiple TACs 326 can be formed within the WL TAC region 372, which is surrounded laterally by the barrier structure 324.

[0077] In some embodiments, the dummy channel structure 322 is formed outside the WL TAC region 372 to provide mechanical support to the memory array structure. It is understood that the dummy channel structure 322 may be formed in any region outside the WL TAC region 372, for example, within the dummy channel region 350 and along the edge of the channel structure region 320 adjacent to the dummy channel region 350. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0078] In some embodiments, multiple slit structures 314, each extending in the WL direction, can divide the 3D memory device into multiple memory fingers 342, 344. An upper select gate cut 355 may be positioned in the center of each memory finger 342, 344 to divide the upper select gate (TSG) of the memory finger into two parts.

[0079] It should be noted that the width of the WL TAC region 372 in the BL direction can be greater than the width of each memory finger 342 or 344. That is, the barrier structure 324 in the BL direction can span at least two adjacent slit structures 314. Thus, the conductive layer in the channel structure region 320 within the memory finger 344 can be completely blocked by the barrier structure 324. Consequently, the upper select gates of the channel structure 312 between the two channel structure regions 320 within the memory finger 344 on either side of the WL TAC region 372 are not interconnected by the upper conductive layer in the alternating conductor / dielectric stack.

[0080] Therefore, in some embodiments relating to such a design of the WL TAC region 372, one memory plane 110 may contain only two memory blocks 115 in the WL direction. The WL TAC region 372 is sandwiched between two memory blocks (i.e., channel structure regions 320 as shown in Figure 3B), while the outer side of the channel structure regions 320 in the WL direction may have a stepped structure (not shown in Figure 3B). Thus, the upper selection gate of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 can be interconnected by using a stepped structure on the edge of the memory plane 110 of the 3D NAND device. Such a design may be suitable for zigzag word line decoder (X-DEC) routing.

[0081] Referring to Figure 3C, an enlarged plan view of region 140 shown in Figure 1 is shown, including other exemplary word line (WL)TAC regions of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300C of the 3D memory device (i.e., region 140 as shown in Figure 1) may include a channel structure region 320 and a dummy channel region 350 surrounding a plurality of word line (WL)TAC regions 376.

[0082] As shown in Figure 3C, in some embodiments, multiple slit structures 314, each extending in the WL direction, can divide the 3D memory device into multiple memory fingers 342. An upper select gate cut 355 may be located in the center of each memory finger 342 to divide the upper select gate (TSG) of the memory finger into two parts.

[0083] The channel structure region 320 may contain an array of channel structures 312, each containing multiple stacked memory cells. A dummy channel region 350 is sandwiched between two channel structure regions 320 in the WL direction. Multiple WL TAC regions 376 arranged in columns along the BL direction are surrounded by the dummy channel region 350. Each WL TAC region 376 may be defined by a barrier structure 324. Multiple TACs 326 can be formed within each WL TAC region 376, which is surrounded laterally by a barrier structure 324.

[0084] In some embodiments, the width of each WL TAC region 376 in the BL direction can be smaller than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 can be located between two adjacent slit structures 314. Since the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper select gate of the channel structure 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376 can be interconnected by the upper conductive layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0085] In some embodiments, the dummy channel structure 322 is formed outside the WL TAC region 376 to provide mechanical support to the memory array structure. It is understood that the dummy channel structure 322 may be formed in any region outside the WL TAC region 376, for example, within the dummy channel region 350 and along the edge of the channel structure region 320 adjacent to the dummy channel region 350. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0086] Therefore, by arranging one WL TAC region 376 within each memory finger 342, the upper conductive layer in the alternating conductor / dielectric stack does not have to be blocked by the WL TAC region 376. Thus, no additional structure is required to further interconnect the upper selection gate of the channel structure 312 between the two channel structure regions 320 within each memory finger 342 on either side of the WL TAC region 376. Therefore, multiple WL TAC regions 376 can be arranged within each memory finger 342 along the WL direction. That is, the memory 110 can contain multiple memory blocks 115 in the WL direction.

[0087] Referring to Figure 3D, an enlarged plan view of region 140 shown in Figure 1 is shown, including other exemplary word line (WL)TAC regions of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300D of the 3D memory device (i.e., region 140 as shown in Figure 1) may include a channel structure region 320 and a dummy channel region 350 surrounding a plurality of word line (WL)TAC regions 376.

[0088] As shown in Figure 3D, in some embodiments, multiple slit structures 314, 316, each extending in the WL direction, can divide the 3D memory device into multiple memory fingers 342. In some embodiments, the slit structure 314 can extend all the way in the WL direction through two or more channel structure regions 320 and one or more dummy channel regions 350. As shown in Figure 3D, at least one slit structure 316 can include a gap 318 within the dummy channel region 350. An upper select gate cut 355 may be located in the center of each memory finger 342 to divide the upper select gate (TSG) of the memory finger into two parts.

[0089] The channel structure region 320 may contain an array of channel structures 312, each containing multiple stacked memory cells. A dummy channel region 350 is sandwiched between two channel structure regions 320 in the WL direction. Multiple WL TAC regions 376 arranged in columns along the BL direction are surrounded by the dummy channel region 350. Each WL TAC region 376 may be defined by a barrier structure 324. Multiple TACs 326 can be formed within each WL TAC region 376, which is surrounded laterally by a barrier structure 324.

[0090] In some embodiments, the width of each WL TAC region 376 in the BL direction can be smaller than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 can be located between two adjacent slit structures 314. Since the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper select gate of the channel structure 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376 can be interconnected by the upper conductive layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0091] In some embodiments, the dummy channel structure 322 is formed outside the WL TAC region 376 to provide mechanical support to the memory array structure. It is understood that the dummy channel structure 322 may be formed in any region outside the WL TAC region 376, for example, within the dummy channel region 350 and along the edge of the channel structure region 320 adjacent to the dummy channel region 350. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0092] In some embodiments, one or more slit structures 316 may include a gap 318 within a dummy channel region 350. Word lines in adjacent memory fingers 342 can be interconnected by using conductive wires passing through the gap 318. For example, as shown in Figure 3D, a slit structure 314 on the edge of a memory block 115 may extend all the way in the WL direction through two or more channel structure regions 320 and one or more dummy channel regions 350, while each slit structure 316 inside each memory block 115 may include one or more gaps 318 within its corresponding dummy channel region 350. Thus, all upper select gates and / or word lines within the same memory block 115 can be interconnected without further structure.

[0093] Therefore, by arranging the WL TAC region 376 within the memory finger 342 and providing a gap 318 within the slit structure 316, the upper conductive layer in the alternating conductor / dielectric stack does not need to be blocked by the WL TAC region 376, and word lines in adjacent memory fingers 342 can be interconnected. Thus, multiple WL TAC regions 376 can be arranged within each memory finger 342 along the WL direction. That is, the memory 110 can include multiple memory blocks 115 in the WL direction. Such a structure can have a high level of integration and a simple layout that is easy to manufacture.

[0094] Referring to Figure 4A, an enlarged plan view of region 150 shown in Figure 1 is shown, which includes an exemplary stepped structure (SS)TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 400A of the 3D memory device (i.e., region 150 as shown in Figure 1) may include a channel structure region 420, a stepped region 410, and a stepped structure (SS)TAC region 482.

[0095] The channel structure region 420 may include an array of channel structures 412, each containing a plurality of stacked memory cells. The step region 410 may include a step structure and an array of word line contacts 432 formed on the step structure. In some embodiments, the SS TAC region 482 is located within the step region 410. The SS TAC region 482 may be defined by a barrier structure 424, either alone or together with the edge of the step region 410 of the 3D memory device. Multiple TACs 426 may be formed within the SS TAC region 482, which is surrounded laterally by at least the barrier structure 424.

[0096] As shown in Figure 4A, in some embodiments, multiple slit structures 414, 416, each extending in the WL direction, can divide the 3D memory device into multiple memory fingers 442, 444. In some embodiments, the slit structures 414 can extend in the WL direction within at least a portion of the stepped region 410. At least some of the slit structures 416 can include one or more gaps 418 within the stepped region 410. An upper select gate cut 455 may be located in the center of each memory finger 442, 444 to divide the upper select gate (TSG) of the memory finger into two parts.

[0097] In some embodiments, one or more slit structures 416 may include a gap 418 within the stepped region 410. Word line contacts 432 in adjacent memory fingers 442 can be interconnected by using conductive wires passing through the gap 418. For example, as shown in Figure 4A, a slit structure 414 on the edge of a memory block 115 may extend all the way in the WL direction through the channel structure region 420 and the stepped region 410, while an inner slit structure 416 of each memory block 115 may include one or more gaps 418 within the stepped region 410. Thus, all word line contacts 432 within the same memory block 115 can be interconnected without further structure.

[0098] It should be noted that the width of the SS TAC region 482 in the BL direction can be greater than the width of each memory finger 442, 444. That is, the barrier structure 424 in the BL direction can span at least two adjacent slit structures 414. Since the SS TAC region 482 occupies a portion of the stepped region 410 corresponding to the memory finger 444 which is completely blocked by the barrier structure 424, the stepped structure within the SS TAC region 482 is used to form the TAC 426 rather than the word line contact 432 for the memory finger 444. Therefore, the stepped structure corresponding to the memory finger 444 on the other side of the memory plane 110 (not shown in Figure 4B) may be used to form the word line contact 432 rather than the SS TAC region 482.

[0099] Therefore, in some embodiments relating to such a design of the SS TAC region 482, the SS TAC regions 482 on both sides of the memory plane 110 do not extend in the WL direction. That is, one memory finger corresponds to at most one SS TAC region 482. Such a design may be suitable for zigzag word line decoder (X-DEC) routing. Furthermore, in some embodiments relating to the design of the SS TAC region 482, and for the same reasons relating to the design of the WL TAC region 372 described above in relation to Figure 3B, the SS TAC region 482 and the WL TAC region 372 do not extend in the WL direction. That is, one memory finger corresponds to at most one SS TAC region 482 or one WL TAC region 372.

[0100] Referring to Figure 4B, an enlarged plan view of region 150 shown in Figure 1 is shown, including other exemplary stepped structure (SS)TAC regions of a 3D memory device according to some alternative embodiments of the present disclosure. Region 400B of the 3D memory device (i.e., region 150 as shown in Figure 1) may include a channel structure region 420, a stepped region 410, and multiple stepped structure (SS)TAC regions 484.

[0101] The channel structure region 420 may include an array of channel structures 412, each containing a plurality of stacked memory cells. The step region 410 may include a step structure and an array of word line contacts 432 formed on the step structure. In some embodiments, the SS TAC region 484 is located within the step region 410. Each SS TAC region 484 may be defined by a barrier structure 424, either alone or together with the edge of the step region 410 of the 3D memory device. A plurality of TACs 426 may be formed within the SS TAC region 482, which is surrounded laterally by at least a barrier structure 424.

[0102] As shown in Figure 4B, in some embodiments, multiple slit structures 414, each extending in the WL direction within the channel structure region 420, can divide the 3D memory device into multiple memory fingers 442. An upper select gate cut 455 may be located in the center of each memory finger 442 to divide the upper select gate (TSG) of the memory finger into two parts. In some embodiments, the slit structures 414 can extend in the WL direction within at least a portion of the stair region 410. In some embodiments, the stair region 410 may further include multiple slit structures 416 that are not aligned with the slit structures 414 in the WL direction. That is, the distance between adjacent slit structures within the stair region 410 may be non-uniform. Some adjacent pairs of slit structures may have a first distance greater than the second distance between other adjacent pairs of slit structures.

[0103] In some embodiments, each SS TAC region 484 may be located between adjacent pairs of slit structures having a first distance. That is, the width of the SS TAC region 484 in the BL direction can be less than the first distance. Thus, in addition to the space occupied by the SS TAC region 484, the stair regions 410 between such adjacent pairs of slit structures having the first distance may have extra space to form word line contacts 432.

[0104] Referring to Figures 5A and 5B, schematic cross-sectional views of exemplary 3D memory devices at several manufacturing stages according to several embodiments of the present disclosure are shown. Figure 5A shows two separated chips 500A and 500B before bonding, while Figure 5B shows the 3D memory device 500C formed by bonding the first chip 500A and the second chip 500B. It should be noted that the 3D memory device 500C shown in Figure 5B may be part of a non-monolithic 3D memory device in which components (e.g., peripheral devices and array devices) may be formed separately on different substrates. For example, the 3D memory device 500C may be region 130, region 140, or region 150 as described above in relation to Figure 1.

[0105] As shown in Figure 5A, the first chip 500A may include a first substrate 570 and an array device above the first substrate 570. Note that the X and Y axes have been added to Figures 5A and 5B to further illustrate the spatial relationships of the components in chips 500A and 500B, as well as the 3D memory device 500C. The first substrate 570 includes a first bonding interface 534 which may be a lateral bottom surface (lateral direction, e.g., WL direction or BL direction) extending laterally in the X direction.

[0106] When used herein, whether one component (e.g., a layer or device) is "above," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., an array device) is determined with respect to the substrate of the semiconductor device (e.g., the first substrate 570) in the Y direction (vertical direction) when the substrate is located (or otherwise positioned) within the lowest plane of the semiconductor device in the Y direction. The cross-sectional views of the 3D memory device shown in Figures 5A and 5B are aligned in the BL direction and the Y direction planes. The same idea for describing spatial relationships applies throughout this disclosure.

[0107] The first substrate 570 can be used to support the array device and may include an array interconnect layer 530 and a base substrate 540. The array interconnect layer 530 may be a wiring-end-of-life (BEOL) interconnect layer including one or more interconnect structures 532 embedded in a dielectric layer. The interconnect structures 532 may include, but are not limited to, contacts, single-layer / multilayer vias, conductive wires, plugs, pads, and / or any other suitable conductive structures, made from a conductive material containing W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The dielectric layer may consist of a dielectric material containing, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. One or more portions of the interconnect structures 532 may be exposed on the first bonding surface 534 of the first substrate 570.

[0108] The base substrate 540 may consist of any suitable semiconductor material, which may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. In some embodiments, the base substrate 540 is a thinned substrate (e.g., a semiconductor layer), which is thinned by grinding, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, the base substrate 540 may be a single-layer substrate or a multilayer substrate, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, or a polysilicon and metal multilayer substrate.

[0109] Furthermore, one or more openings 542 may be formed within a region of the base substrate 540 corresponding to one or more through-array contact (TAC) structures of the array device. In some embodiments, multiple TACs 526 can pass through one or more openings 542 to be electrically connected to one or more interconnect structures 532 in the array interconnect layer 530. In some other embodiments, multiple conductive plugs (not shown) passing through one or more openings 542 may be used to electrically connect multiple TACs to one or more interconnect structures 532 in the array interconnect layer 530. It should be noted that one or more openings 542 are filled with dielectric material to insulate the multiple TACs 526 and / or the multiple conductive plugs.

[0110] In some embodiments, the array device may be a NAND flash memory device in which memory cells are provided in the form of an array of channel structures (not shown in Figures 5A and 5B) extending in the Y direction above the substrate 570. The array device may include multiple channel structures extending through an alternating conductor / dielectric stack 580, which includes multiple pairs of conductive layers 580A and dielectric layers 580B. The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580 (e.g., 32, 64, or 96) can determine the number of memory cells in the 3D memory device.

[0111] The conductive layers 580A and dielectric layers 580B within the alternating conductor / dielectric stack 580 are alternating in the Y direction. In other words, except for those at the top or bottom of the alternating conductor / dielectric stack 580, each conductive layer 580A may be adjacent to two dielectric layers 580B on either side, and each dielectric layer 580B may be adjacent to two conductive layers 580A on either side. Each conductive layer 580A may have the same thickness or different thicknesses. Similarly, each dielectric layer 580B may have the same thickness or different thicknesses. The conductive layers 580A may be composed of conductive materials including, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer 580B may consist of a dielectric material including, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer 580A is composed of a metal layer such as W, and the dielectric layer 580B is composed of silicon oxide.

[0112] In some embodiments, the array device further includes slit structures 514. Each slit structure 514 extends in the Y direction through the alternating conductor / dielectric stack 580. The slit structures 514 may also extend laterally (i.e., substantially parallel to the substrate) to separate the alternating conductor / dielectric stack 580 into multiple blocks. The slit structures 514 may include slits filled with conductive material, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The slit structures 514 may further include a dielectric layer having any suitable dielectric material between the filled conductive material and the alternating conductor / dielectric stack 580 to electrically insulate the filled conductive material from the surrounding conductive layer 580A within the alternating conductor / dielectric stack 580. As a result, the slit structures 514 can separate the 3D memory device 500 into multiple memory fingers (for example, as shown in Figures 2, 3A-3D, and 4A-4B in plan view).

[0113] In some embodiments, the slit structure 514 functions as a source contact for channel structures within the same memory finger that share the same array common source. Thus, the slit structure 514 may be referred to as a “common source contact” for multiple channel structures. In some embodiments, the base substrate 540 includes a doped region 544 (containing a p-type dopant or an n-type dopant at a desired doping level), and the lower end of the slit structure 514 is in contact with the doped region 544 of the base substrate 540.

[0114] In some embodiments, the alternating dielectric stack 560 may be located within a region laterally enclosed by a barrier structure 516 on the base substrate 540. The alternating dielectric stack 560 may include multiple dielectric layer pairs. For example, the alternating dielectric stack 560 is formed by an alternating stack of a first dielectric layer 560A and a second dielectric layer 560B distinct from the first dielectric layer 560A. In some embodiments, the first dielectric layer 560A is composed of silicon nitride and the second dielectric layer 560B is composed of silicon oxide. The second dielectric layer 560B in the alternating dielectric stack 560 may be the same as the dielectric layer 580B in the alternating conductor / dielectric stack 580. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack 560 is the same as the number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580.

[0115] In some embodiments, the barrier structure 516 extends in the Y direction so as to separate the alternating conductor / dielectric stack 580 and the alternating dielectric stack 560 from the side. That is, the barrier structure 516 can be a boundary between the alternating conductor / dielectric stack 580 and the alternating dielectric stack 560. The alternating dielectric stack 560 is obtained by being surrounded from the side at least by the barrier structure 516. In some embodiments, the barrier structure 516 has a closed shape in plan view (e.g., rectangular, square, circular, etc.) to completely enclose the alternating dielectric stack 560. For example, as shown in Figures 3A to 3D, the barrier structure 324 is rectangular in plan view to completely enclose the alternating dielectric stack in the WL TAC region 372, 376. In some embodiments, the barrier structure 516 does not have a closed shape in plan view but can enclose the alternating dielectric stack 560 together with one or more edges of the array device. For example, as shown in Figures 4A and 4B, the barrier structure 424 surrounds the alternating dielectric stacks within the SS TAC regions 482 and 484, along with the edges of the 3D memory device.

[0116] As shown in Figure 5A, the first chip 500A further includes a plurality of TACs 526, each extending in the Y direction through the alternating dielectric stack 560. The TACs 526 can only be formed inside an area laterally surrounded by at least a barrier structure 516 containing a plurality of dielectric layer pairs. That is, the TACs 526 can extend perpendicularly through the dielectric layers (e.g., the first dielectric layer 560A and the second dielectric layer 560B), but not through any conductive layer (e.g., conductive layer 580A). Each TAC 526 can extend through the entire thickness of the alternating dielectric stack 560 (e.g., all the dielectric layer pairs in the Y direction). In some embodiments, the TACs 526 further penetrate the base substrate 540 through an opening 542 and electrically contact the interconnect structure 532.

[0117] The TAC526 can transmit electrical signals from and to array devices, such as part of a power bus, using shortened interconnect routing. In some embodiments, the TAC526 can provide electrical connections between array devices and peripheral devices (not shown in Figures 5A and 5B) through one or more interconnect structures 532. The TAC526 can also provide mechanical support to the alternating dielectric stack 560. Each TAC526 may include vertical openings filled with a conductive material consisting of W, Co, Cu, Al, doped silicon, silicide, or any combination thereof, through and not limited to the alternating dielectric stack 560. In some embodiments, when the TAC526 is formed by the alternating dielectric stack 560 (surrounded by a dielectric layer), no further dielectric layers between the TAC526 and the alternating dielectric stack 560 are required for insulation.

[0118] The second chip 500B may include a second substrate 510 and a peripheral interconnection layer 520 on the second substrate 510. The second substrate 510 may be made of any suitable semiconductor material, which may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. The second substrate 510 may be a single-layer substrate or a multilayer substrate, e.g., a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multilayer substrate, etc. In some embodiments, the second substrate 510 is a thinned substrate (e.g., a semiconductor layer), which is thinned by grinding, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0119] One or more peripheral circuits (not shown in Figures 5A and 5B) can be formed on the second substrate 510. These one or more peripheral circuits may include any suitable digital signal, analog signal, and / or mixed signal peripherals used to assist the operation of the 3D memory device. For example, these one or more peripheral circuits may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), latches, sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, one or more peripheral circuits may be formed on the second substrate 510 using complementary metal-oxide-semiconductor (CMOS) technology (also known as "CMOS chips").

[0120] In some embodiments, the peripheral interconnection layer 520 may include one or more interconnection structures 522 embedded in the dielectric layer to electrically connect one or more peripheral circuits to an array device above the first substrate 570. The one or more interconnection structures 522 may include, but are not limited to, any suitable conductive structures, including contacts, monolayer / multilayer vias, conductive layers, plugs, pads, and / or any other suitable conductive structures, and may be made of a conductive material containing W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The dielectric layer of the peripheral interconnection layer 520 may have a monolayer or multilayer structure and may include, but are not limited to, a dielectric material containing silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, or any combination thereof.

[0121] The second chip 500B may include a second bonding interface 524, which may be a lateral top surface extending laterally in the X direction (lateral direction, e.g., WL direction or BL direction). In some embodiments, the first bonding surface 534 of the first chip 500A is bonded to the second bonding surface 524 of the second chip 500B. That is, the peripheral interconnect layer 520 and the array interconnect 530 can be bonded in a face-to-face manner. Thus, as shown in Figure 5B, the first chip 500A and the second chip 500B can be bonded at the bonding interface 555 to form a 3D memory device 500C.

[0122] The bonding interface 555 is located between the peripheral interconnect layer 520 and the array interconnect 530. That is, the bonding interface 555 can be between two dielectric layers, such as between a silicon nitride layer and a silicon oxide layer. The bonding interface 555 can also be between two conductive layers, such as between two metal (e.g., Cu) layers. In some embodiments, the bonding interface includes both the interface between dielectric layers and the interface between conductive layers. In some embodiments, one or more interconnect structures 532 in the first chip 500A and one or more interconnect structures 522 in the second chip 500B can be brought into contact with each other at the bonding interface 555 to electrically interconnect one or more TACs 526 in the first chip 500A and peripheral circuits in the second chip 500B.

[0123] The bonding interface 555 may be formed by chemical bonding between dielectric and / or conductive layers on both sides of the bonding interface, for example, the first bonding surface 534 and the second surface 524, as shown in Figure 5A. The bonding interface 555 may also be formed by physical interaction (e.g., interdiffusion) between the dielectric and / or conductive layers on both sides of the bonding interface. In some embodiments, the bonding interface is formed after plasma treatment or heat treatment of the surfaces on both sides of the bonding interface prior to the bonding process.

[0124] By using through-contact holes for coupling on the back side of the first substrate, the pad layer of the interconnection structure can be formed on the back side of the first substrate corresponding to the array device. Since the pad layer is formed on the back side of the first substrate rather than in the peripheral region of the first substrate, the size of the 3D memory device can be reduced and the degree of integration of the 3D memory device can be improved.

[0125] Referring to Figures 6A and 6B, schematic flowcharts of exemplary methods for forming a 3D memory device according to some embodiments of the present disclosure are shown. It should be understood that the operations shown in Figures 6A and 6B are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Figures 7A and 7C show schematic cross-sectional views of another exemplary 3D memory device at some stage of the manufacturing process shown in Figures 6A and 6B according to some other embodiments of the present disclosure.

[0126] Referring to Figure 6A, a flowchart of an exemplary method 600A for forming an array device and an array interconnect layer according to several embodiments is shown. As shown in Figure 6A, method 600A begins in operation 604 in which an alternating dielectric stack is formed on a first substrate. In some embodiments, the first substrate can be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, a polysilicon and metal multilayer substrate, and so on.

[0127] Multiple dielectric layer pairs (also referred to herein as “alternating dielectric stacks”) can be formed on a first substrate. An alternating dielectric stack may include an alternating stack of a first dielectric layer and a second dielectric layer different from the first dielectric layer. In some embodiments, each dielectric layer pair includes a silicon nitride layer and a silicon oxide layer. In some embodiments, there are more layers in the alternating dielectric stack than dielectric layer pairs made of different materials and having different thicknesses. Alternating dielectric stacks can be formed by one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0128] Method 600A proceeds to operation 606, which forms a stepped structure on one or more edges of the alternating dielectric stack. In some embodiments, the trim etch process can be performed on at least one side of the alternating dielectric stack (laterally) to form a stepped structure at multiple levels. Each level may include one or more pairs of dielectric layers having alternating first and second dielectric layers.

[0129] Method 600A proceeds to operation 608, which forms a plurality of channel structures and one or more barrier structures. Each channel structure and each barrier structure can extend vertically through the alternating dielectric stack.

[0130] In some embodiments, the manufacturing process for forming the channel structure includes, for example, the step of forming channel holes that extend perpendicularly through the alternating dielectric stack by wet etching and / or dry etching. In some embodiments, the manufacturing process for forming the channel structure further includes the step of forming semiconductor channels and memory films between semiconductor channels and dielectric layer pairs in the alternating dielectric stack. The semiconductor channels may be composed of a semiconductor material such as polysilicon. The memory films may be composite dielectric layers such as a combination of tunnel layers, recording layers, and blocking layers.

[0131] The tunnel layer may consist of a dielectric material including, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Electrons or holes from the semiconductor channel can tunnel through the tunnel layer to the recording layer. The recording layer may contain a material that stores charge for memory operation. The recording layer material may include, but is not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. The blocking layer may consist of a dielectric material including, but is not limited to, silicon oxide, or a combination of silicon oxide / silicon nitride / silicon oxide (ONO). The blocking layer may further include a high-k dielectric layer, such as an aluminum oxide (Al2O3) layer. The semiconductor channel and memory film may be formed by one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0132] In some embodiments, the manufacturing process for forming the barrier structure is carried out similarly to and simultaneously with the manufacturing process for forming the channel structure, thereby reducing the complexity and cost of manufacturing. In some other embodiments, the channel structure and the barrier structure are formed in different manufacturing steps, thereby the barrier structure may be filled with a different material than the material that fills the channel structure.

[0133] In some embodiments, the manufacturing process for forming the barrier structure includes, for example, the step of forming trenches extending vertically through the alternating dielectric stack by wet etching and / or dry etching. After the trenches have been formed through the alternating dielectric stack, one or more thin-film deposition processes may be performed to fill the trenches with dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxide / silicon nitride / silicon oxide (ONO), aluminum oxide (Al2O3), or any combination thereof.

[0134] By forming one or more barrier structures, the alternating dielectric stack can be separated into two types of regions: one or more inner regions, each surrounded laterally by at least the barrier structure (along with the edges of the alternating dielectric stack in some embodiments), and outer regions on which channel structures and / or word line contacts can be formed. Note that each inner region corresponds to an opening in the first substrate.

[0135] In some embodiments, at least one inner region can be used to form a BL TAC structure as described above in relation to Figure 2. Thus, the barrier structure surrounding such an inner region may include two parallel barrier walls extending along the WL direction.

[0136] In some embodiments, at least one inner region can be used to form a BL TAC structure as described above in relation to Figure 3A or Figure 3B. Thus, the barrier structure surrounding such an inner region can have a rectangular shape. The width of the barrier structure in the BL direction can be greater than the distance between two adjacent slit structures formed in a subsequent process.

[0137] In some embodiments, at least one inner region can be used to form a BL TAC structure as described above in relation to Figure 3C or Figure 3D. Thus, the barrier structure surrounding such an inner region can have a rectangular shape. The width of the barrier structure in the BL direction can be smaller than the distance between two adjacent slit structures formed in a subsequent process.

[0138] In some embodiments, at least one inner region can be used to form an SS TAC structure as described above in relation to Figure 4A. Thus, the barrier structure separating such inner regions may have a rectangle with one open edge facing the edge of the stair structure. The width of the barrier structure in the BL direction can be greater than the distance between two adjacent slit structures formed in a subsequent process.

[0139] In some embodiments, at least one inner region can be used to form an SS TAC structure, as described above in relation to Figure 4B. Thus, the barrier structure separating such an inner region may have a rectangle with one open edge facing the edge of the stair structure. The width of the barrier structure in the BL direction can be smaller than the maximum distance between two adjacent slit structures formed within the stair region in a subsequent process.

[0140] In some embodiments, dummy channel structures can be formed simultaneously with the channel structures. Dummy channel structures can extend vertically through the alternating layer stack and can be filled with the same material as the channel structures. Unlike channel structures, contacts are not formed on the dummy channel structures to provide electrical connections with other components of the 3D memory device. Therefore, dummy channel structures cannot be used to form memory cells in a 3D memory device.

[0141] Method 600A proceeds to operation 610, in which a plurality of slits are formed and a first dielectric layer in a portion of the alternating dielectric stack is replaced with a conductive layer through the plurality of slits. For example, first, a plurality of parallel slits extending in the WL direction can be formed by wet etching and / or dry etching of the dielectric (e.g., silicon oxide and silicon nitride) through the alternating dielectric stack in the outer area. In some embodiments, doped regions are then formed in the first substrate beneath each slit, for example, by ion implantation and / or thermal diffusion through the slits. According to some embodiments, it will be understood that the doped regions can be formed in an earlier manufacturing step, for example, before the formation of the slits.

[0142] In some embodiments, the formed slits are used in a gate replacement process (also known as a "word line replacement" process) to replace a first dielectric layer (e.g., silicon nitride) with a conductive layer (e.g., W) within the outer area of ​​the alternating dielectric stack. It should be noted that the gate replacement is performed only within the outer area of ​​the alternating dielectric stack and not within the inner area due to the formation of the barrier structure. Since the barrier structure is a filler material that cannot be etched by the etching step of the gate replacement process, this barrier structure can prevent etching of the first dielectric layer (e.g., silicon nitride) within the inner area of ​​the alternating dielectric stack.

[0143] As a result, modifying the alternating dielectric stack outside the region after the gate replacement process will result in modifying the alternating conductor / dielectric stack. Replacement of the first dielectric layer having a conductive layer can be performed by selectively wet etching the first dielectric layer (e.g., silicon nitride) relative to a second dielectric layer (e.g., silicon oxide) and filling the structure with a conductive layer (e.g., W). The conductive layer may be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. The conductive layer may consist of conductive materials including, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. The formed alternating conductor / dielectric stack and the remaining alternating dielectric stack can constitute an alternating stack.

[0144] Method 600A proceeds to Operation 612, which forms a slit structure by filling (e.g., depositing) a conductive material into the slit by PVD, CVD, ALD, any other suitable process, or any combination thereof. The slit structure may consist of a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, for insulating purposes, a dielectric layer (e.g., a silicon oxide layer) is first formed between the conductive material of the slit structure and the conductive layer surrounding the slit structure in the alternating conductor / dielectric stack. The lower end of the slit structure may be in contact with the doped region.

[0145] Method 600A proceeds to Operation 614, which forms multiple TACs through an alternating dielectric stack. TACs can be formed within one or more inner regions by first etching vertical openings (e.g., by wet etching and / or dry etching) and then filling the openings with a conductive material using ALD, CVD, PVD, any other suitable process, or any combination thereof. Conductive materials used to fill local contacts may include, but are not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, other conductive materials may also be used to fill openings that function as barrier layers, adhesive layers, and / or seed layers.

[0146] TACs can be formed by etching through the entire thickness of the alternating dielectric stack. Since the alternating dielectric stack contains alternating layers of dielectrics such as silicon oxide and silicon nitride, the openings in the TACs can be formed by deep etching of the dielectric material (e.g., by a deep reactive-ion etching (DRIE) process, or any other suitable anisotropic etching process). In some embodiments, the TACs are formed after gate replacement, but by preserving areas of the alternating dielectric stack that are unaffected by the gate replacement process (and not transformed into alternating conductor / dielectric stacks), the TACs can be further formed through the dielectric layers (without passing through any conductive layers), thereby simplifying the manufacturing process and reducing costs.

[0147] Method 600A proceeds to operation 616, which forms an array interconnect layer on an alternating stack. The array interconnect layer may be used to transmit electrical signals between the TAC and other parts of the 3D memory device, such as peripheral circuits. In some embodiments, the manufacturing process for forming the array interconnect layer includes forming a dielectric layer, followed by forming a plurality of interconnect structures. One or more of the interconnect structures may each be in contact with the TAC.

[0148] The dielectric layer may include one or more layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The interconnection structure may consist of, but is not limited to, contacts, single-layer / multilayer vias, conductive wires, plugs, pads, and / or any other suitable conductive structure made of conductive materials containing, but is not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0149] In some embodiments, the manufacturing process for forming an interconnect structure includes the steps of forming openings in a dielectric layer and subsequently filling the openings with a conductive material. The openings in the dielectric layer may be filled with the conductive material by ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the manufacturing process for forming an interconnect structure further includes the step of forming one or more conductive layers and one or more contact layers within the dielectric layer. The conductive layers and conductive contact layers may be formed by any suitable known BEOL method.

[0150] Referring to Figure 6B, a flowchart of an exemplary method 600B for forming peripheral circuits and peripheral interconnect layers according to several embodiments is shown. As shown in Figure 6B, method 600B begins with operation 622 for forming peripheral circuits on a second substrate. In some embodiments, the second substrate can be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, a polysilicon and metal multilayer substrate, and so on.

[0151] The peripheral circuit may include any suitable peripheral devices formed on the second substrate and any suitable interconnection circuits between the peripheral devices. One or more peripheral devices and / or interconnection circuits may be formed by a number of process steps, including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, injection, CMP, or any combination thereof.

[0152] Method 600B proceeds to operation 624, which involves forming a peripheral interconnect layer on the peripheral circuit. The peripheral interconnect layer may include a dielectric layer above the peripheral circuit and one or more interconnect structures formed within the dielectric layer. The dielectric layer may include one or more layers of dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The interconnect structures may include, but are not limited to, contacts, single-layer / multilayer vias, conductive wires, plugs, pads, and / or any other suitable conductive structures, which are made from conductive material containing, but are not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0153] In some embodiments, interconnect structures can be formed by any suitable known middle-end-of-line (MEOL) method. For example, a manufacturing process for forming an interconnect structure may include the steps of forming openings in a dielectric layer and subsequently filling the openings with a conductive material. The openings in the dielectric layer may be filled with a conductive material by ALD, CVD, PVD, any other suitable process, or any combination thereof. Furthermore, a manufacturing process for forming an interconnect structure may include the steps of forming one or more conductive layers and one or more contact layers within the dielectric layer. The conductive layers and conductive contact layers may consist of conductive material deposited by one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the conductive layers and contact layers may also include photolithography, CMP, wet / dry etching, or any combination thereof.

[0154] As shown in Figure 7A, the dielectric layer 740 is formed on the second substrate 750, while the multiple interconnection structures 742 are formed within the dielectric layer 740. Note that the peripheral circuitry is not shown in Figure 7A. The multiple interconnection structures 742 are in electrical contact with the peripheral circuitry.

[0155] Method 600B proceeds to operation 626, which involves positioning (or otherwise locating) the array device (and array interconnect layer) below the first substrate (for example, by inverting the first substrate), so that the array interconnect layer is aligned with the peripheral interconnect layer. As shown in Figure 7A, the array interconnect layer 730 may be positioned below the second silicon substrate 710. The TAC 726 can penetrate the alternating stack 720. In some embodiments, aligning the array interconnect layer 730 with the peripheral interconnect layer 740 is done by aligning the interconnect structure 733 within the array interconnect layer 730 with the interconnect structure 742 within the peripheral interconnect layer 740. As a result, the interconnect structure 733 can electrically contact the interconnect structure 742 when the array device is joined to the peripheral circuitry in a subsequent operation.

[0156] Method 600B proceeds to operation 628, which bonds the array interconnect layer to the peripheral interconnect layer, as shown in Figure 6B. The array interconnect layer can be bonded to the peripheral interconnect layer by flip-chip bonding of the first and second substrates. In some embodiments, the array interconnect layer and the peripheral interconnect layer are bonded by hybrid bonding of the first and second substrates in a face-to-face manner, so that the array interconnect layer is above and in contact with the peripheral interconnect layer in the resulting 3D memory device.

[0157] Hybrid bonding (also known as "metal / dielectric hybrid bonding") can be a direct bonding technique that simultaneously obtains metal-metal bonding and dielectric-dielectric bonding (for example, forming bonding between surfaces without using an intermediate layer such as solder or adhesive). As shown in Figure 7B, the array interconnect layer 730 can bond with the peripheral interconnect layer 740, thereby forming a bonding interface 734.

[0158] In some embodiments, a processing process may be used to enhance the bonding strength between the array interconnect layer 730 and the peripheral interconnect layer 740 before or during the bonding process of the two interconnect layers. In some embodiments, each dielectric layer in the array interconnect layer 730 and the peripheral interconnect layer 740 is composed of silicon oxide or silicon nitride. For example, plasma processing may be used to treat each surface of the array interconnect layer 730 and the peripheral interconnect layer 740 so that the surfaces of the two interconnect layers form a chemical bond between the two dielectric layers. As another example, a wet process may be used to treat each surface of the array interconnect layer 730 and the peripheral interconnect layer 740 so that the surfaces of the two interconnect layers form a favorable chemical bond to enhance the bonding strength between the two dielectric layers. As yet another example, a thermal process may be carried out at a temperature of about 250°C to about 600°C (e.g., 250°C to 600°C). The thermal process may cause interdiffusion between interconnect structures 733 and 742. As a result, the corresponding interconnect structures 733 and 742 may be mixed after the bonding process. In some embodiments, the interconnection structures 733 and 742 may each contain Cu.

[0159] Method 600B proceeds to Operation 630, in which the first substrate is thinned so that the thinned first substrate acts as a semiconductor layer on top of an array device (e.g., NAND strings), as shown in Figure 6B. As shown in Figure 7C, the thinned first substrate 710 may be a single-crystal silicon layer. In some embodiments, after the thinning process, the single-crystal silicon layer 710 has a thickness between approximately 5 nm and approximately 50 μm (e.g., 5 nm, 50 nm, 500 nm, 5 μm, 50 μm, any range bounded at the lower end by any of these values, or any range defined by any two of these values). The first substrate 710 may be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0160] Method 600B proceeds to operation 632, in which a BEOL interconnect layer may be formed above the semiconductor layer, as shown in Figure 6B. As shown in Figure 7C, the BEOL interconnect layer is formed above the first substrate 710. The BEOL interconnect layer may include a dielectric layer 760 overlapping the first substrate 710 and a plurality of interconnect structures 762 within the dielectric layer 760.

[0161] In some embodiments, the manufacturing process for the interconnect structure 762 may include separate process steps to form one or more contact layers, conductive layers, and / or pad layers in the dielectric layer. The dielectric layer 760 may be a combination of multiple dielectric layers formed in separate process steps. The interconnect structure 762 may be composed of a conductive material including, but is not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. In some embodiments, the manufacturing process for the interconnect structure 762 may further include a step of forming one or more openings in the first substrate 710. One or more openings may correspond to one or more through-array contact TAC structures (e.g., a word line (WL) TAC structure as shown in Figure 2, a bit line (BL) TAC structure as shown in Figures 3A-3D, and a stepped structure (SS) TAC structure as shown in Figures 4A-4B). Thus, one or more interconnect structures 762 penetrate the dielectric layer 760 and the first substrate 710 and are electrically connected to a TAC 726, respectively. Therefore, the TAC726 can be used to electrically interconnect external circuits or devices in order to transmit electrical signals between joined arrays and / or peripheral circuits and external circuits or devices.

[0162] Various embodiments of this disclosure provide 3D memory devices with smaller die sizes, higher device density, and improved performance compared to other 3D memory devices. The density of 3D memory devices can be increased by vertically stacking array devices and BEOL interconnects above peripheral circuits. By providing the memory array in a through-array contact (TAC) structure, vertical interconnects between stacked array devices and peripheral devices (e.g., for power buses and metal routing) can be realized, reducing the metal level and decreasing the die size. In some embodiments, the through-array contact structures disclosed herein are formed through a stack of alternating dielectric layers, which can be etched more easily to form through-holes internally compared to a stack of alternating conductor and dielectric layers, thereby reducing process complexity and manufacturing costs.

[0163] Accordingly, one aspect of the present invention discloses a three-dimensional (3D) NAND memory device comprising an alternating layer stack disposed on a first substrate. The alternating layer stack may include a first region comprising an alternating dielectric stack comprising a plurality of dielectric layer pairs, and a second region comprising an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs. The 3D NAND memory device further includes a barrier structure extending perpendicularly through the alternating layer stack so as to laterally separate the first region from the second region, and a plurality of through-array contacts within the first region. Each through-array contact extends perpendicularly through the alternating dielectric stack. The 3D NAND memory device further includes an array interconnection layer disposed on the alternating layer stack at the end of the alternating layer stack opposite to the first substrate. The array interconnection layer includes at least one first interconnection structure electrically connected to at least one through-array contact. The 3D NAND memory device further includes peripheral circuits formed on a second substrate and a peripheral interconnection layer on at least one of the peripheral circuits, and includes at least one second interconnection structure electrically connected to the peripheral circuits. The array interconnection layer is coupled on the peripheral interconnection layer such that the peripheral circuits are electrically connected to at least one of a plurality through at least one first interconnection structure and at least one second interconnection structure.

[0164] The barrier structure is composed of silicon oxide and silicon nitride. Each of the multiple dielectric layer pairs consists of a silicon oxide layer and a silicon nitride layer, and each of the multiple conductor / dielectric layer pairs consists of a metal layer and a silicon oxide layer. The number of multiple dielectric layer pairs is at least 32, and the number of multiple conductor / dielectric layer pairs is at least 32.

[0165] The 3D NAND memory device further includes multiple slit structures extending vertically and laterally along the word line direction, respectively, through the alternating conductor / dielectric stack to divide the alternating conductor / dielectric stack into multiple memory fingers.

[0166] In some embodiments, the barrier structure extends laterally along the word line direction. The first region is separated from the second region by the barrier structure and is sandwiched between two adjacent slit structures.

[0167] In some embodiments, the barrier structure extends laterally along a bit line direction different from the word line direction, so as to laterally separate a first region from a second region. The bit line direction may be perpendicular to the word line direction.

[0168] In some embodiments, the width of the first region surrounded by the bit-line barrier structure may be greater than the distance between two adjacent slit structures.

[0169] In some embodiments, the first region surrounded by a barrier structure may be sandwiched between two upper select gate stair regions in the word line direction. At least two upper layers of alternating conductor / dielectric stacks away from the first substrate within each upper select gate stair region may have a stair structure. At least one conductive layer on the stair structure within the upper select gate stair region is configured to interconnect the upper select gates located above the alternating conductor / dielectric stacks in the second region and on both sides of the first region surrounded by a barrier structure in the word line direction.

[0170] The 3D NAND memory device further includes at least two first regions surrounded by a corresponding barrier structure, each first region extending parallel to the bit line direction.

[0171] The 3D NAND memory device further includes a plurality of barrier structures surrounding a plurality of first regions from a second region such that the plurality of first regions are aligned in the bit line direction. Each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction. In some embodiments, the plurality of first regions are aligned to form at least two columns in the bit line direction.

[0172] In some embodiments, at least one slit structure, sandwiched between two adjacent barrier structures in the bit line direction, includes a gap, and the at least one slit structure is configured to interconnect the word lines of adjacent memory fingers among a plurality of memory fingers.

[0173] In some embodiments, the first region is separated by a barrier structure from a stepped structure on the edge of the alternating conductor / dielectric layer stack along the bit line direction. The opening of the barrier structure is located at the edge of the alternating layer stack along the bit line direction.

[0174] In some embodiments, the width of the first region in the bit line direction is greater than the distance between two adjacent slit structures.

[0175] In some embodiments, the width of the first region in the bit line direction is smaller than the maximum distance between two adjacent slit structures in the stepped structure on the edge of the alternating layer stack along the bit line direction.

[0176] The 3D memory device comprises a plurality of dummy channel structures adjacent to a barrier structure, each dummy channel structure further comprising a plurality of dummy channel structures extending vertically through an alternating conductor / dielectric stack.

[0177] Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) NAND memory device. The method includes the steps of: forming an alternating dielectric stack on a first substrate, the alternating dielectric stack comprising a plurality of dielectric layer pairs, each of which comprises a first dielectric layer and a second dielectric layer distinct from the first dielectric layer; forming at least one barrier structure, each extending perpendicularly through the alternating dielectric stack, separating the alternating dielectric stack into at least one first region and a second region surrounded laterally by at least the barrier structure; forming a plurality of slits to form an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs, and replacing the first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits; and forming a plurality of slit structures The steps may include: depositing a conductive material in a slit; forming a plurality of through-array contacts in a first region, each through-array contact extending perpendicularly through an alternating dielectric stack; forming an array interconnect layer including at least one first interconnect structure on the alternating layer stack and electrically connected to at least one through-array contact; and coupling the array interconnect layer to a peripheral interconnect layer on the second substrate, which includes at least one second interconnect structure electrically connected to peripheral circuits formed on the second substrate such that peripheral circuits are electrically connected to at least one of a plurality through at least one first interconnect structure and at least one second interconnect structure.

[0178] The method may further include the steps of forming a peripheral circuit on a second substrate before coupling the array interconnect layer to the peripheral interconnect layer; forming a peripheral interconnect layer on the peripheral circuit so that at least one second interconnect structure within the peripheral interconnect layer is electrically connected to the peripheral circuit; and arranging the array interconnect layer and the peripheral interconnect layer so that at least one first interconnect structure corresponds to at least one second interconnect structure.

[0179] The method may further include the step of forming a plurality of doped regions on a first substrate such that each slit structure is in contact with a corresponding doped region, prior to the step of forming the slits.

[0180] The method may further include the step of laterally forming multiple slit structures extending along the word line direction so as to divide the alternating conductor / dielectric stack into multiple memory fingers.

[0181] The method may further include the step of forming two parallel barrier structures laterally, extending along the word line direction, such that the first region is separated from the second region by two parallel barrier structures and sandwiched between two adjacent slit structures.

[0182] The method may further include the step of forming a barrier structure that extends laterally along a bit line direction different from the word line direction, so as to laterally separate the first region from the second region.

[0183] The method may further include the step of forming a barrier structure that extends laterally along the bit line direction perpendicular to the word line direction.

[0184] The method may further include the step of forming a barrier structure such that the width in the bit line direction of the first region surrounded by the barrier structure is greater than the distance between two adjacent slit structures.

[0185] The method may further include the step of forming a stepped structure in an alternating dielectric stack adjacent to the barrier structure.

[0186] The method may further include the step of forming at least one conductive layer on a stepped structure adjacent to a barrier structure so as to interconnect upper select gates on both sides of a first region which are above an alternating conductor / dielectric stack in a second region and surrounded by a barrier structure in the word line direction.

[0187] The method may further include the step of forming at least two barrier structures so as to surround at least two first regions that extend parallel along the bit line direction.

[0188] The method may further include the step of forming a plurality of barrier structures surrounding a plurality of first regions that are aligned in the bit line direction from a second region, such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction.

[0189] The method may further include the step of forming a plurality of barrier structures such that a plurality of first regions surrounded by the plurality of barrier structures are arranged in a sequence of at least two in the bit line direction.

[0190] The method may further include the step of forming a gap in at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction so as to interconnect the word lines of adjacent memory fingers.

[0191] The method may further include the step of forming a barrier structure so as to separate a first region within a staircase structure at the edge of an alternating stack. The opening of the barrier structure may be at the edge of the alternating layer stack along a bit line direction different from the word line direction.

[0192] The method may further include the step of forming a barrier structure such that the width of a first region in the bit line direction is greater than the distance between two adjacent slit structures.

[0193] The method may further include the step of forming a barrier structure such that the width of a first region in the bit line direction is less than the maximum distance between two adjacent slit structures within the staircase structure.

[0194] The method may further include the step of forming a plurality of dummy channel structures adjacent to a barrier structure, each dummy channel structure extending vertically through an alternating conductor / dielectric stack.

[0195] The foregoing descriptions of specific embodiments fully illustrate the general nature of the disclosure so that others, by applying knowledge of the art, can readily modify and / or adapt such specific embodiments to various uses without diverting from the general concepts of the disclosure and without excessive experimentation. Accordingly, any adaptations and modifications based on the teachings and guidance provided herein are intended to be within the meaning and equivalents of the disclosed embodiments. It should be understood that the terms and technical terms herein are for illustrative purposes only, not limiting purposes, and are intended to be interpreted by those skilled in the art in light of the teachings and guidance provided herein.

[0196] Embodiments of the present disclosure are described above using functional configuration blocks that demonstrate the implementation of specific functions and their relationships. The boundaries of these functional configuration blocks are arbitrarily defined herein for the sake of simplicity of explanation. Alternative boundaries may be defined, as long as the specific functions and their relationships are adequately performed.

[0197] The Summary and Abstract chapters may describe one or more, but not necessarily all, exemplary embodiments of the present disclosure as conceived by the inventors, and are therefore not intended to limit the scope of the present disclosure and the appended claims in any way.

[0198] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be determined solely by the appended claims and their equivalents.

[0199] [Additional note 1] An alternating layer stack disposed on a first substrate, A first region including an alternating dielectric stack comprising multiple dielectric layer pairs, and A second region including an alternating conductor / dielectric stack comprising multiple conductor / dielectric layer pairs. An alternating layer stack equipped with, A barrier structure extending vertically through the alternating layer stack so as to laterally separate the first region from the second region, A plurality of through-array contacts within the first region, wherein each through-array contact is a through-array contact extending vertically through the alternating dielectric stack, The array interconnection layer that contacts the plurality of through-array contacts, Peripheral circuits formed on the second substrate, The peripheral interconnection layer on the aforementioned peripheral circuit and A three-dimensional (3D) NAND memory device equipped with, A three-dimensional (3D) NAND memory device in which the array interconnect layer is coupled on the peripheral interconnect layer such that the peripheral circuit is electrically connected to at least one of the plurality of through-array contacts. [Additional note 2] The memory device according to Appendix 1, wherein the array interconnection layer is disposed on the alternating layer stack at the end of the alternating layer stack opposite to the first substrate. [Additional note 3] The memory device according to Appendix 1, wherein the array interconnection layer is disposed on the surface of the first substrate opposite to the alternating layer stack. [Additional note 4] The array interconnection layer includes at least one first interconnection structure embedded in the first dielectric layer, The peripheral interconnection layer includes at least one second interconnection structure embedded in the second dielectric layer. The peripheral circuit is electrically connected to at least one of the plurality of through-array contacts via the at least one first interconnection structure and the at least one second interconnection structure. A memory device as described in any one of the appendices 1 to 3. [Additional note 5] The memory device according to any one of the appendices 1 to 4, wherein the barrier structure is composed of silicon oxide and silicon nitride. [Additional note 6] The memory device according to any one of the appendices 1 to 5, wherein each of the plurality of dielectric layer pairs is composed of a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs is composed of a metal layer and a silicon oxide layer. [Additional note 7] The number of the plurality of dielectric layer pairs is at least 32. The number of the aforementioned multiple conductor / dielectric layer pairs is at least 32. A memory device as described in any one of the appendices 1 to 6. [Additional note 8] Multiple slit structures extending vertically and laterally along the word line direction through the alternating conductor / dielectric stack divide the alternating conductor / dielectric stack into multiple memory fingers. A memory device as described in any one of the appendices 1 to 7, further comprising the above. [Additional note 9] The barrier structure extends laterally along the direction of the word line, The first region is separated from the second region by the barrier structure and sandwiched between two adjacent slit structures. The memory device described in Appendix 8. [Additional Note 10] The barrier structure extends laterally along a bit line direction different from the word line direction so as to laterally separate the first region from the second region. The memory device described in Appendix 8. [Additional Note 11] The bit line direction is perpendicular to the word line direction. The memory device described in Appendix 10. [Additional Note 12] The width of the first region surrounded by the barrier structure in the bit line direction is greater than the distance between two adjacent slit structures. The memory devices described in Appendix 10 or 11. [Additional Note 13] The first region surrounded by the barrier structure is sandwiched between two upper selection gate stair regions in the direction of the word line. A memory device as described in any one of the appendices 10 to 12. [Additional Note 14] At least the top two layers of the alternating conductor / dielectric stack, separated from the first substrate within each upper selection gate stair region, have a stair structure. The memory device described in Appendix 13. [Additional Note 15] The system further comprises at least one conductive layer on the stair structure within the upper selection gate stair region, configured to interconnect the upper selection gates located on both sides of the first region, which is above the alternating conductor / dielectric stack in the second region and surrounded by the barrier structure in the word line direction. The memory device described in Appendix 14. [Additional Note 16] At least two first regions surrounded by a corresponding barrier structure, each of the two first regions extending parallel to the bit line direction. A memory device as described in any one of appendices 13 to 15, further comprising the above. [Additional Note 17] The system further comprises a plurality of barrier structures that surround the plurality of first regions from the second region so that the plurality of first regions are aligned in the direction of the bit line, Each of the plurality of first regions is sandwiched between two adjacent slit structures in the direction of the bit line. The memory devices described in Appendix 10 or 11. [Additional Note 18] The plurality of first regions are arranged to form at least two columns in the bit line direction. The memory device described in Appendix 17. [Additional Note 19] The at least one slit structure, sandwiched between two adjacent barrier structures in the bit line direction, includes a gap, and the at least one slit structure is configured to interconnect the word lines of adjacent memory fingers among the plurality of memory fingers. The memory device described in Appendix 17. [Additional Note 20] The first region is separated by the barrier structure from the stepped structure on the edge of the alternating conductor / dielectric layer stack along the bit line direction, The opening of the barrier structure is located at the edge of the alternating layer stack along the bit line direction. The memory devices described in Appendix 10 or 11. [Additional Note 21] The width of the first region in the bit line direction is greater than the distance between two adjacent slit structures. The memory device described in Appendix 20. [Additional Note 22] The width of the first region in the bit line direction is smaller than the maximum distance between two adjacent slit structures in the step structure on the edge of the alternating layer stack along the bit line direction. The memory device described in Appendix 20. [Additional note 23] A plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack, A memory device as described in any one of the appendices 1 to 22, further comprising the above. [Additional note 24] A method for forming a three-dimensional (3D) NAND memory device, The step of forming an alternating dielectric stack on a first substrate, wherein each of the plurality of dielectric layer pairs comprises a first dielectric layer and a second dielectric layer different from the first dielectric layer, The steps of forming at least one barrier structure, each extending perpendicularly through the alternating dielectric stack, which separates the alternating dielectric stack into at least one first region and a second region surrounded laterally by at least the barrier structure, The steps include forming a plurality of slits to form an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs, and replacing a first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits, The steps include depositing a conductive material in the slits to form a plurality of slit structures, The steps of: a plurality of through-array contacts within the first region, wherein each through-array contact forms a through-array contact that extends vertically through the alternating dielectric stack; The steps include forming an array interconnection layer that contacts the plurality of through-array contacts, A method comprising the step of coupling the array interconnect layer to a peripheral interconnect layer on a second substrate such that at least one of the plurality of through-array contacts is electrically connected to a peripheral circuit on a second substrate. [Additional note 25] The step of forming the array interconnection layer is, The method according to appendix 24, comprising the step of forming at least one first interconnection structure on a first dielectric layer located on the alternating layer stack at the end of the alternating layer stack opposite to the first substrate. [Additional note 26] The step of forming the array interconnection layer is, The method according to Appendix 24, comprising the step of forming at least one first interconnection structure on a first dielectric layer located on the surface of the first substrate opposite to the alternating layer stack. [Additional note 27] Before coupling the array interconnection layer to the peripheral interconnection layer, the step of forming the peripheral circuit on the second substrate, The steps include forming the peripheral interconnection layer on the peripheral circuit such that at least one second interconnection structure within the peripheral interconnection layer is electrically connected to the peripheral circuit, The steps include arranging the array interconnect layer and the peripheral interconnect layer such that each of the at least one first interconnect structure corresponds to each of the at least one second interconnect structure, The method described in any one of the appendices 24 to 26, further including: [Additional note 28] Prior to the step of forming the slits, a step of forming a plurality of doped regions on the first substrate so that each slit structure is in contact with the corresponding doped region. The method described in any one of the appendices 24 to 27, further including: [Additional note 29] The method according to any one of appendices 24 to 28, wherein the at least one barrier structure is formed from silicon oxide and silicon nitride. [Additional note 30] The method according to any one of appendices 24 to 29, wherein each of the plurality of dielectric layer pairs is formed from a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs is formed from a metal layer and a silicon oxide layer. [Additional Note 31] The steps include forming at least 32 pairs of dielectric layer pairs, The steps include forming at least 32 pairs of conductor / dielectric layer pairs and The method described in any one of the appendices 24 to 30, further including: [Additional note 32] The step of laterally forming the plurality of slit structures extending along the word line direction so as to divide the alternating conductor / dielectric stack into a plurality of memory fingers. The method described in any one of the appendices 24 to 31, further including the method described in any one of the appendices 24 to 31. [Additional note 33] The step of forming the two parallel barrier structures laterally so as to extend along the word line direction, such that the first region is separated from the second region by the two parallel barrier structures and sandwiched between two adjacent slit structures. The method described in Appendix 32, further including the method described in Appendix 32. [Additional note 34] The step of forming the barrier structure that extends laterally along a bit line direction different from the word line direction so as to laterally separate the first region from the second region. The method described in Appendix 32, further including the method described in Appendix 32. [Additional note 35] The step of forming the barrier structure so as to extend laterally along the bit line direction which is perpendicular to the word line direction. The method described in Appendix 34, further including the method described in Appendix 34. [Additional note 36] The step of forming the barrier structure such that the width in the bit line direction of the first region surrounded by the barrier structure is greater than the distance between two adjacent slit structures. The method described in Appendix 34 or 35, further including the method described in Appendix 34 or 35. [Additional note 37] The method according to any one of appendices 34 to 36, further comprising the step of forming a stepped structure in the alternating dielectric stack adjacent to the barrier structure. [Additional note 38] The step of forming at least one conductive layer on the stepped structure adjacent to the barrier structure so as to interconnect upper select gates on both sides of the first region, which is located above the alternating conductor / dielectric stack in the second region and surrounded by the barrier structure in the word line direction. The method described in Appendix 37, further including the method described in Appendix 37. [Additional note 39] The step of forming at least two barrier structures so as to surround at least two first regions that extend parallel along the bit line direction. The method described in any one of the appendices 34 to 38, further including: [Additional note 40] The step of forming a plurality of barrier structures surrounding a plurality of first regions arranged in the bit line direction from a second region, such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction. The method described in Appendix 34 or 35, further including the method described in Appendix 34 or 35. [Additional note 41] The step of forming the plurality of barrier structures such that the plurality of first regions surrounded by the plurality of barrier structures are arranged in at least two columns in the bit line direction. The method described in Appendix 40, further including the method described in Appendix 40. [Additional note 42] The step of forming a gap in the at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction so as to interconnect the word lines of adjacent memory fingers. The method described in Appendix 40, further including the method described in Appendix 40. [Additional note 43] The step further includes forming the barrier structure so as to separate the first region within the staircase structure at the edge of the alternating stack, wherein the opening of the barrier structure is at the edge of the alternating stack along a bit line direction different from the word line direction. The method described in Appendix 32. [Additional note 44] The step of forming the barrier structure such that the width of the first region in the bit line direction is greater than the distance between two adjacent slit structures. The method described in Appendix 43, further including the method described in Appendix 43. [Additional note 45] The step of forming the barrier structure such that the width of the first region in the bit line direction is smaller than the maximum distance between two adjacent slit structures in the staircase structure. The method described in Appendix 43, further including the method described in Appendix 43. [Additional note 46] A plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure forming a plurality of dummy channel structures extending vertically through the alternating conductor / dielectric stack. The method described in any one of the appendices 24 to 45, further including: [Explanation of Symbols]

[0200] 100 3D memory devices, memory 110 memory planes 115 memory blocks 120 Contact Pads 130 areas 140 areas 150 areas 160-bit line (BL) TAC area, BL TAC area 170 Word Line (WL) TAC Area 172 WL TAC area 180 Staircase structure (SS) TAC area 200 areas 210 Channel structure region 212-channel structure 214 Slit structure 222 Dummy channel structure 224 Barrier structure 226 Multiple TACs 233-bit line (BL) TAC area, BL TAC area, TAC area 242 Memory Fingers 246 Dummy Memory Finger 255 Upper Select Gate Cut 300A area 300B area 300C area 312 channel structure, channel structure 314 Slit structure 316 Slit structure 318 Gap 320 Channel Structure Region 322 Dummy channel structure 324 Barrier structure 326 TAC 330 Upper Selection Gate (TSG) Staircase Area, TSG Staircase Area 342 Memory Fingers 344 Memory Fingers 350 Dummy channel area 355 Upper Select Gate Cut 372 Word Line (WL) TAC Area, WL TAC Area 376 Word Line (WL) TAC Area, WL TAC Area 400A area 400B area 410 Stairs area 412 channel structure 414 Slit structure 416 Slit structure 418 Gap 420 Channel Structure Region 424 Barrier structure 426 Multiple TACs, TAC 432 Word Line Contacts 442 Memory Fingers 444 Memory Fingers 482 Staircase structure (SS) TAC area, SS TAC area 484 Staircase structure (SS) TAC area, SS TAC area 455 Upper Select Gate Cut 500 3D memory devices 500A chip, first chip 500B chip, second chip 500C 3D Memory Device 510 Second substrate 514 Slit structure 516 Barrier structure 520 Peripheral interconnection layer 522 Interconnection Structure 524 Second bonding interface, second bonding surface 526 TAC 530 Array Interconnection Layer 532 Interconnection Structure 534 First bonding interface, first bonding surface 540 base board 542 Opening 555 Bonding Interface 560 Alternating Dielectric Stack 560A First dielectric layer 560B Second dielectric layer 570 substrates, first substrate 580 Alternating Conductor / Dielectric Stack 580A Conduction Layer 580B Dielectric Layer 710 Second silicon substrate, thinned first substrate, single crystal silicon layer, first substrate 720 alternating stack 726 TAC 730 Array Interconnection Layer 733 Interconnection Structure 740 Dielectric layer, peripheral interconnection layer 742 Interconnection Structure 750 Second substrate 760 Dielectric Layer 762 Interconnection Structure

Claims

1. - Multiple first stacks and multiple second stacks, Each of the first stacks comprises a plurality of first dielectric layers and a plurality of second dielectric layers arranged alternately in the vertical direction. Each of the second stacks comprises a plurality of conductor layers and a plurality of third dielectric layers arranged alternately in the vertical direction, the first stack and the second stack, A plurality of barrier structures arranged along the bit line direction and laterally separating the first stack from the second stack, wherein each barrier structure extends vertically through a corresponding one of the first stacks and includes an opening, and the openings of the barrier structures are arranged along the bit line direction. - A through-array contact structure extending vertically through one of the first stacks, - Multiple dummy channel structures extending vertically through one of the second stacks, Equipped with, The dummy channel structure includes a plurality of columns arranged in the direction of the bit line, Each of the aforementioned rows comprises a plurality of dummy channel structures spaced apart in the word line direction perpendicular to the vertical direction and the bit line direction, One of the barrier structures comprises two parallel first sub-barrier structures extending in the direction of the word line, A memory device in which only two of the multiple rows of the dummy channel structure are located between the planes of two parallel first sub-barrier structures in the bit line direction.

2. The memory device according to claim 1, wherein the slit structure extends through one of the second stacks in the direction of the word line and comprises a conductor structure.

3. The memory device according to claim 2, wherein the conductor structure includes at least one of polysilicon and doped polysilicon.

4. The slit structure comprises a fourth dielectric layer, The memory device according to claim 2, wherein the fourth dielectric layer is located between one of the second stacks and the conductor structure.

5. The memory device according to claim 4, wherein the fourth dielectric layer comprises silicon oxide.

6. The memory device according to claim 1, wherein one of the barrier structures further comprises a second sub-barrier structure that extends along the bit line direction and is connected to two parallel first sub-barrier structures.

7. The memory device according to claim 1, wherein the first stack and the barrier structure are located in a stepped region.

8. The memory device according to claim 7, wherein each of the openings in the barrier structure is located at the corresponding edge of the first stack in the word line direction.

9. The first dielectric layer and the second dielectric layer contain different materials. The memory device according to claim 1, wherein the second dielectric layer and the third dielectric layer contain the same material.

10. The memory device according to claim 1, wherein the through-array contact structure is connected to a peripheral circuit.

11. The array further comprises an array interconnection layer and a peripheral interconnection layer. The memory device according to claim 10, wherein the array interconnection layer and the peripheral interconnection layer are coupled to each other.

12. The bonding interface is located between the peripheral interconnection layer and the array interconnection layer. The memory device according to claim 11, wherein the bonding interface comprises an interface between dielectric layers and an interface between conductive layers.

13. The first stack and the second stack are located on a base substrate. The memory device according to claim 11, wherein the array interconnection layer is located between the peripheral interconnection layer and the base substrate.

14. The aforementioned peripheral circuit is formed on the substrate, The memory device according to claim 13, wherein the peripheral circuit is located between the substrate and the array interconnection layer.

Images