Memory device

Abstract

To provide a semiconductor device with less variation in transistor characteristic.SOLUTION: A transistor includes an oxide semiconductor film, a source electrode and a drain electrode on the oxide semiconductor film, an interlayer insulating film disposed covering the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode on the oxide semiconductor film. The interlayer insulating film has an opening formed overlapping with a region between the source electrode and the drain electrode. The gate electrode is disposed in the opening of the interlayer insulating film. The source electrode and the drain electrode are formed of a conductive film with a compression stress.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to transistors, semiconductor devices, and electronic devices. Alternatively, one aspect of the present invention relates to a method for manufacturing semiconductor devices. Alternatively, one aspect of the present invention relates to semiconductor wafers and modules.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed significantly, with particularly remarkable advancements in LSIs, CPUs, and memory. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) separated from a semiconductor wafer, and on which electrodes, which are connection terminals, are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, low-power CPUs that take advantage of the low leakage current characteristic of transistors using oxide semiconductors have been disclosed (see Patent Document 1). Also, for example, memory devices that can retain stored data for a long period of time have been disclosed that take advantage of the low leakage current characteristic of transistors using oxide semiconductors (see Patent Document 2).

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Overview of the project] [Problems that the invention aims to solve]

[0010] One aspect of the present invention aims to provide a semiconductor device with less variation in transistor characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention is a transistor comprising an oxide semiconductor film, a source electrode and a drain electrode on the oxide semiconductor film, an interlayer insulating film disposed over the oxide semiconductor film, the source electrode and the drain electrode, and a gate electrode on the oxide semiconductor film, wherein the interlayer insulating film is superimposed in the region between the source electrode and the drain electrode and has an opening formed therein, the gate electrode is disposed within the opening in the interlayer insulating film, and the source electrode and the drain electrode are subjected to compressive stress.

[0013] Another aspect of the present invention is a transistor comprising an oxide semiconductor film, a source electrode and a drain electrode on the oxide semiconductor film, a barrier insulating film disposed covering the oxide semiconductor film, the source electrode and the drain electrode, an interlayer insulating film on the barrier insulating film, a gate insulating film on the oxide semiconductor film, and a gate electrode on the gate insulating film, wherein the barrier insulating film and the interlayer insulating film are superimposed in the region between the source electrode and the drain electrode, forming an opening, the gate insulating film and the gate electrode are disposed within the opening in the interlayer insulating film, the barrier insulating film contains silicon nitride, the source electrode and the drain electrode have compressive stress, and the oxide semiconductor film has a density in a first region superimposed on the source electrode or the drain electrode that is lower than that in a second region superimposed on the gate electrode.

[0014] In the above, it is preferable that the hydrogen concentration in the first region is higher than that in the second region.

[0015] In the above, it is preferable that the magnitude of the compressive stress is 1000 MPa or more. Furthermore, in the above, it is preferable that the source electrode and the drain electrode are nitrides containing tantalum. Furthermore, in the above, it is preferable that the source electrode and the drain electrode are formed using a sputtering method.

[0016] In the above, it is preferable that the oxide semiconductor film has one or more selected from In, Ga, or Zn.

[0017] Alternatively, another aspect of the present invention is an electronic device having the transistor described above. [Effects of the Invention]

[0018] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0020] [Figure 1] Figure 1A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 1B to 1D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 2] Figure 2 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 3] Figure 3A shows the calculation model shown in this embodiment. Figure 3B shows the calculation results shown in this embodiment. [Figure 4] Figure 4A illustrates the classification of IGZO crystal structures. Figure 4B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 4C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 5] Figure 5A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5B to 5D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 6]Figure 6A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B to 6D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 7] Figure 7A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] Figure 8A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figure 12A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] Figure 14A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14B to 14D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15] Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B to 15D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] Figure 16 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 17] Figure 17 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 18] Figure 18 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 19] Figures 19A and 19B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 20] Figure 20 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 21] Figure 21 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 22] Figure 22 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 23] Figures 23A and 23B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 24] Figure 24 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 25] Figure 25 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 26] Figure 26A is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention, and Figure 26B is a schematic diagram showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 27] Figures 27A to 27H are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 28] Figure 28A is a block diagram of a semiconductor device according to one aspect of the present invention, and Figure 28B is a schematic diagram of a semiconductor device according to one aspect of the present invention. [Figure 29] Figures 29A and 29B illustrate an example of an electronic component. [Figure 30] Figures 30A to 30E are schematic diagrams of a storage device according to one embodiment of the present invention. [Figure 31] Figures 31A to 31H show an electronic device that is one embodiment of the present invention. [Modes for carrying out the invention]

[0021] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0022] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Additionally, in drawings, the same reference numerals may be used across different drawings for identical parts or parts with similar functions, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the hatch patterns may be the same, and no specific reference numeral may be assigned.

[0023] Furthermore, in particular, in top views (also called "plan views") or perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted.

[0024] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0025] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0026] Furthermore, where it is explicitly stated in this specification that X and Y are connected, this specification shall disclose the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it shall be understood that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0028] Furthermore, the functions of the source or drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0029] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0031] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0032] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0033] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0034] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0035] In this specification, an oxidized nitride is defined as a material whose composition contains more oxygen than nitrogen. For example, silicon oxidized nitride has a higher oxygen content than nitrogen. Similarly, a nitride oxide is defined as a material whose composition contains more nitrogen than oxygen. For example, silicon nitride oxide has a higher nitrogen content than oxygen.

[0036] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0037] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0038] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0039] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0040] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, and a method for manufacturing the same, will be described with reference to Figures 1 to 19.

[0041] <Example of semiconductor device configuration> The configuration of a semiconductor device having a transistor 200 will be explained using Figures 1A to 1D. Figure 1A is a top view of the semiconductor device. Figures 1B to 1D are cross-sectional views of the semiconductor device. Here, Figure 1B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A. Note that some elements have been omitted from the top view of Figure 1A for clarity.

[0042] A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, and an insulator 285 on the insulator 283. The insulators 212, 214, 280, 282, 283, and 285 function as interlayer insulating films. It also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. An insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. Furthermore, conductors 246 (conductors 246a and 246b) are provided on the insulator 285 and on the conductor 240, electrically connected to the conductor 240 and functioning as wiring.

[0043] Insulator 241a is provided in contact with the inner wall of the opening of insulators 280, 282, 283, and 285, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inside. Insulator 241b is provided in contact with the inner wall of the opening of insulators 280, 282, 283, and 285, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inside. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 285 in the region overlapping with conductor 246 can be made to be approximately the same. Note that in transistor 200, a configuration in which the first conductor and the second conductor of conductor 240 are stacked is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned to distinguish it according to the order of formation.

[0044] [Transistor 200] As shown in Figures 1A to 1D, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductors 205a, 205b, and 205c) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) on the oxide 230b, a conductor 242a on the oxide 243a, and a conductor 242a It includes an upper insulator 271a, a conductor 242b on oxide 243b, an insulator 271b on conductor 242b, an insulator 250 (insulator 250a and insulator 250b) on oxide 230b, a conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with a portion of oxide 230b, and an insulator 275 arranged to cover insulator 222, insulator 224, oxide 230a, oxide 230b, oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 271a, and insulator 271b.

[0045] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242. Furthermore, insulators 271a and 271b may be collectively referred to as insulator 271.

[0046] Insulators 280 and 275 are provided with openings that reach oxide 230b. Insulator 250 and conductor 260 are arranged within these openings. Furthermore, in the channel length direction of transistor 200, conductor 260 and insulator 250 are provided between insulator 271a, conductor 242a and oxide 243a and insulator 271b, conductor 242b and oxide 243b. Insulator 250 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0047] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By arranging the oxide 230a below the oxide 230b, the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b can be suppressed.

[0048] In the transistor 200, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0049] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulator 250 functions as the first gate insulating film, and insulators 224 and 222 function as the second gate insulating film. Conductor 242a functions as either the source electrode or the drain electrode, and conductor 242b functions as either the source electrode or the drain electrode. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0050] Here, an enlarged view of the vicinity of the channel formation region in Figure 1B is shown in Figure 2. As shown in Figure 2, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and a pair of regions 230ba and 230bb that are provided so as to sandwich region 230bc and function as the source region or drain region. At least a portion of region 230bc is superimposed on the conductor 260. In other words, region 230bc is provided in the region between the pair of conductors 242a and conductor 242b. Region 230ba is provided superimposed on conductor 242a, and region 230bb is provided superimposed on conductor 242b.

[0051] Region 230bc, which functions as a channel-forming region, is a high-resistance region with a low carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to regions 230ba and 230bb. Regions 230ba and 230bb, which function as source or drain regions, are low-resistance regions with increased carrier concentrations due to more oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements. In other words, regions 230ba and 230bb have higher carrier concentrations and lower resistance compared to region 230bc.

[0052] Here, the carrier concentration in region 230bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm-3 is more preferably less than, 1×10 16 cm -3 is further preferably less than, 1×10 13 cm -3 is further preferably less than, 1×10 12 cm -3 is further preferably less than. Note that the lower limit value of the carrier concentration of the region 230bc functioning as a channel formation region is not particularly limited, and for example, may be 1×10 -9 cm -3 .

[0053] In addition, the carrier concentration of the region 230ba and the region 230bb functioning as a source region or a drain region is preferably, for example, 1×10 17 cm -3 or more, more preferably 1×10 18 cm -3 or more, further preferably 1×10 19 cm -3 or more. Note that the upper limit value of the carrier concentration of the region 230ba and the region 230bb functioning as a source region or a drain region is not particularly limited, and for example, may be 1×10 21 cm -3 .

[0054] In addition, a region whose carrier concentration is equal to or lower than the carrier concentration of the region 230ba and the region 230bb, and equal to or higher than the carrier concentration of the region 230bc may be formed between the region 230bc and the region 230ba or the region 230bb. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb. The hydrogen concentration in the junction region may be equal to or lower than the hydrogen concentration in the region 230ba and the region 230bb, and equal to or higher than the hydrogen concentration in the region 230bc. In addition, the junction region may have oxygen vacancies equal to or less than the oxygen vacancies in the region 230ba and the region 230bb, and equal to or more than the oxygen vacancies in the region 230bc.

[0055] Figure 2 shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0056] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0057] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0058] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0059] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0060] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0061] In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed.

[0062] Furthermore, because oxides 230a and 230b share a common element other than oxygen (as the main component), the defect level density at the interface between oxide 230a and oxide 230b can be reduced. Because the defect level density at the interface between oxide 230a and oxide 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0063] It is preferable that the oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 230b.

[0064] CAAC-OS has a highly crystalline, dense structure and is free from impurities or defects (e.g., oxygen deficiencies (V)). O It is a metal oxide with few impurities (such as ). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0065] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0066] Transistors using oxide semiconductors are prone to variations in electrical properties and can become unreliable if impurities or oxygen vacancies are present in the channel formation region of the oxide semiconductor. Furthermore, hydrogen near oxygen vacancies can fill the oxygen vacancies, creating defects (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0067] In contrast, in oxide semiconductors, the source and drain regions have high carrier concentrations and are preferably n-type. Therefore, in oxide semiconductors, the source and drain regions are preferable for generating electrons that become carriers. O It is preferable that H is included. However, V is included in the source region and drain region. O The diffusion of H into the channel-forming region must be suppressed. Therefore, V contained in the source and drain regions O H is preferably stable. In particular, V included in the source and drain regions O Variations in H within the substrate surface result in variations in the characteristics of semiconductor devices containing transistors.

[0068] In other words, in the oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type. On the other hand, the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. Furthermore, the i-type or substantially i-type region 230bc and the n-type regions 230ba and 230bb are preferably stable.

[0069] Therefore, in this embodiment, by forming the source electrode and drain electrode using a conductive film having compressive stress, a strain that expands in the tensile direction (hereinafter sometimes referred to as tensile strain) is formed in regions 230ba and 230bb. O By stably forming H, regions 230ba and 230bb can be transformed into stable n-type regions. Furthermore, by creating tensile strain in regions 230ba and 230bb, region 230bc is compressed, resulting in a denser structure. The strain in region 230bc is reduced in the compressive direction (hereinafter, this strain may be referred to as compressive strain), and the diffusion of hydrogen into this strain can be suppressed. As a result, region 230bc can be transformed into a stable i-type region.

[0070] The stress in the conductor 242 and the strain formed in the oxide 230b will be explained below using Figure 2.

[0071] As shown in Figure 2, the conductor 242a has stress 20a, and the conductor 242b has stress 20b. Hereafter, stress 20a and stress 20b may be collectively referred to as stress 20. Stress 20a is a compressive stress (a stress that attempts to relax the compressive shape of the conductor 242a) with a vector oriented from the center to the edges of the conductor 242a. Similarly, stress 20b is a compressive stress with a vector oriented from the center to the edges of the conductor 242b. The magnitude of stress 20a and stress 20b should be such that strains 30a and strain 30b, described later, can be formed. For example, the magnitude of stress 20a and stress 20b may be 1000 MPa or more, preferably 1500 MPa or more, and more preferably 2000 MPa or more. Alternatively, the magnitude of stress 20a and stress 20b may be determined by preparing a sample in which a film similar to that of the conductor 242 is deposited on a substrate, and measuring the stress of the sample.

[0072] Due to the action of stress 20, strain 30a is formed in region 230ba and strain 30b is formed in region 230bb. Here, strain 30a and strain 30b are strains (tensile strains) that are expanded in the tensile direction due to the action of stress 20. Oxygen deficiency V is present in strains 30a and strain 30b. O , and V O H is formed. Also, the distortion of the crystal lattice arrangement, which will be described later, is formed. In distortions 30a and 30b, V O and V O H atoms are easily formed, and these readily adopt stable structures. As a result, regions 230ba and 230bb become stable n-type regions with high carrier concentrations.

[0073] Furthermore, as strains are formed in regions 230ba and 230bb that are expanded in the tensile direction, region 230bc is compressed from both sides, and region 230bc takes on a dense structure. As a result, strain 30c is formed in region 230bc that is reduced in the compressive direction. Since strain 30c is a compressive strain, V O and V O H is less likely to form. Also, hydrogen does not easily diffuse into strain 30c, so a stable i-type region can be formed.

[0074] Alternatively, a conductive film having tensile stress may be used for the conductor 260. Since this tensile stress acts as a compressive external force on region 230bc, region 230bc can be made to have a denser structure.

[0075] Here, in strains 30a and 30b, the interatomic distances of the elements constituting the oxide 230b are larger, resulting in a lower density. In contrast, in strain 30c, the interatomic distances of the elements constituting the oxide 230b are smaller, resulting in a higher density. Therefore, the region 230ba (region 230bb) where strain 30a (strain 30b) is more prevalent has a lower density than the region 230bc where strain 30c is formed.

[0076] While the strain formed on oxide 230b has been described above, the present invention is not limited thereto. Similar strains 30a to 30c may be formed on oxide 230a.

[0077] <In strain in metal oxides, V O , and V O Ease of H formation > In this section, V in strain in metal oxides O , and V O The ease of H formation will be evaluated using calculations. Specifically, first-principles calculations will be used to evaluate the V strain model in metal oxides. O The formation energy, and V O Calculate the formation energy of H.

[0078] <<Computational Model>> This section describes the computational model used in first-principles calculations.

[0079] As a calculation model for strain in metal oxides, we prepare a model of amorphous In-Ga-Zn oxide. Hereafter, the amorphous In-Ga-Zn oxide model will be referred to as the a-IGZO model. The a-IGZO model was created using the melt-quench method.

[0080] The composition of the a-IGZO model is In:Ga:Zn:O = 1:1:1:4 [atomic ratio]. The a-IGZO model consists of 84 atoms. Three different a-IGZO models with varying densities are available, each with a density of 5.6 g / cm³. 3 5.8 g / cm³ 3 6.0 g / cm³ 3 Therefore, 5.6 g / cm³ 3 The a-IGZO model is a model in which tensile strain is formed in a metal oxide, with a density of 6.0 g / cm². 3 The a-IGZO model is a model in which compressive strain is formed in a metal oxide.

[0081] Next, for each of the a-IGZO models, one oxygen atom is replaced with one hydrogen atom. After substitution, each of the a-IGZO models is V O It has H. In the following, the model is referred to as V O It is sometimes called the a-IGZO model, which includes H. Here, V O The a-IGZO model including H is shown in Figure 3A. Note that the model shown in Figure 3A is V O This is an example of an a-IGZO model containing H. Since the a-IGZO model has 48 oxygen atoms, V is used for each density of a-IGZO model. O We will provide 48 a-IGZO models, including H.

[0082] Next, remove one oxygen atom from each of the a-IGZO models. After removal, each of the a-IGZO models is V O It has. In the following, the model is referred to as V O It is sometimes called the a-IGZO model, which includes V. O a-IGZO models, including V O Similar to the a-IGZO model including H, for each density of a-IGZO model, V O We will prepare 48 a-IGZO models that include this feature.

[0083] The above is an explanation of the computational model.

[0084] <<Calculation conditions>> Next, we will explain the calculation conditions for first-principles calculations.

[0085] The VASP package, a first-principles electronic state calculation package, was used for the first-principles calculations. The calculation conditions are shown in Table 1.

[0086] [Table 1]

[0087] The pseudopotential for the electronic state was generated using the PAW method, and the GGA / PBE functional was used. The k-point grid was set to 1×1×1.

[0088] Under the above calculation conditions, for each density of the a-IGZO model, V O The formation energy of H and V O The formation energy and were calculated.

[0089] V O The formation energy of H is calculated using the following equation (1).

[0090]

number

[0091] Here, E(IGZO) is the total energy of the a-IGZO model. Also, E(IGZO:V O H) is V O This is the total energy of the a-IGZO model including H. Note that V O The formation energy of H is 48 E(IGZO:V O This is the average value for H).

[0092] Also, μ O This is the chemical potential of oxygen, and was calculated using half the energy of an oxygen molecule. Also, μH This represents the chemical potential of hydrogen, calculated using half the energy of a hydrogen molecule.

[0093] V O The formation energy is calculated using the following equation (2).

[0094]

number

[0095] Here, E(IGZO:V O ) is V O This is the total energy of the a-IGZO model, including V. O The formation energy is 48 E(IGZO:V O This is the average value for ).

[0096] Using the above equation, for each density of a-IGZO model, V O The formation energy of H and V O The formation energy and the calculated results are shown in Figure 3B. Figure 3B shows the film density [g / cm³] for each calculation model on the horizontal axis. 3 The vertical axis is plotted as the formation energy [eV].

[0097] As shown in Figure 3B, V O The formation energy of H, and V O A positive correlation was observed between the formation energy and the film density of each computational model. In particular, V O A significant positive correlation was observed between the formation energy of H and the membrane density in each computational model.

[0098] From these calculation results, when tensile strain is formed in a metal oxide, V O H and V O The formation energy is low, that is, V O H and V O A tendency for the formation of [a certain structure] was shown. Furthermore, when compressive strain is formed in metal oxides, V O H and V OThe formation energy is high, that is, V O H and V O A tendency was shown to make it more difficult for them to form.

[0099] Therefore, as in the transistor shown in this embodiment, by forming tensile strain in the source region and drain region of the oxide semiconductor film using source electrodes and drain electrodes having compressive stress, V O H and V O This suggests that the formation of such regions becomes easier. As a result, in the transistor shown in this embodiment, stable n-type regions can be formed in the source region and drain region of the oxide semiconductor film.

[0100] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0101] In Figure 1 and other figures, the side surface of the opening into which the conductor 260 is embedded, including the groove portion of the oxide 230b, is generally perpendicular to the surface of the oxide 230b being formed. However, this embodiment is not limited to this. For example, the bottom of the opening may have a gently curved surface, resulting in a U-shape. Alternatively, for example, the side surface of the opening may be inclined with respect to the surface of the oxide 230b being formed.

[0102] Furthermore, as shown in Figure 1C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (also called rounded).

[0103] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0104] It is preferable that oxide 230 has a layered structure of multiple oxides with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230a is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used for oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0105] Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0106] Here, at the junction of oxide 230a and oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b.

[0107] Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0108] Specifically, for oxide 230a, a metal oxide with an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, may be used. Similarly, for oxide 230b, a metal oxide with an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, may be used. Note that "similar composition" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0109] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0110] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0111] It is preferable that at least one of insulators 212, 214, 271, 275, 282, and 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, and 283 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate through it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate through it).

[0112] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0113] As the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, and the insulator 283, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, or the like can be used. For example, it is preferable to use silicon nitride or the like which has a higher hydrogen barrier property as the insulator 212, the insulator 275, and the insulator 283. Further, for example, as the insulator 214, the insulator 271, and the insulator 282, it is preferable to use aluminum oxide, magnesium oxide, or the like which has a high function of capturing and fixing hydrogen. Accordingly, diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214 can be suppressed. Alternatively, diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed on the outer side of the insulator 283 to the transistor 200 side can be suppressed. Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214 can be suppressed. Alternatively, diffusion of oxygen contained in the insulator 280 or the like to the upper side of the transistor 200 through the insulator 282 or the like can be suppressed. As described above, it is preferable to employ a structure in which the transistor 200 is surrounded by the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, and the insulator 283, which have a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.

[0114] Here, as the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, and the insulator 283, an oxide having an amorphous structure is preferably used. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0115] Insulators 212, 214, 271, 275, 282, and 283 are preferably amorphous, but a region of polycrystalline structure may be formed in part. Insulators 212, 214, 271, 275, 282, and 283 may also be multilayer structures in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer may also be possible.

[0116] The insulators 212, 214, 271, 275, 282, and 283 may be deposited using, for example, a sputtering method. Since sputtering does not require the use of hydrogen as a deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, and 283 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0117] Furthermore, it may be preferable to lower the resistivity of insulators 212 and 283. For example, the resistivity of insulators 212 and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212 and 283 may be able to mitigate charge-up of conductors 205, 242, 260, or 246 during plasma-based processing in semiconductor device manufacturing processes. The resistivity of insulators 212 and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0118] Furthermore, it is preferable that insulators 216 and 280 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer insulating film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216 and 280.

[0119] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In addition, a portion of the conductor 205 may be embedded in the insulator 214.

[0120] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the top of conductor 205a and the height of the upper surface of insulator 216. In other words, conductor 205b is enclosed by conductors 205a and 205c.

[0121] Here, it is preferable to use conductive materials for conductors 205a and 205c that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0122] By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to prevent impurities such as hydrogen contained in conductor 205b from diffusing into oxide 230 via insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress oxidation of conductor 205b and a decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, conductors 205a and 205c may be made of the above conductive materials in a single layer or laminate. For example, titanium nitride may be used for conductors 205a and 205c.

[0123] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0124] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential applied to conductor 205, rather than in conjunction with the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current compared to when no potential is applied to conductor 205. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to when no potential is applied.

[0125] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0126] Furthermore, as shown in Figure 1A, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 1C, it is preferable that the conductor 205 extends to the region outside the ends that intersect with the channel width direction of the oxide 230a and oxide 230b. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the oxide 230 via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0127] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0128] Furthermore, as shown in Figure 1C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0129] In the transistor 200, the conductor 205 is shown as a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer, two layers, or a stacked structure of four or more layers. For example, it may be a two-layer structure of conductor 205a and conductor 205b.

[0130] Insulators 222 and 224 function as gate insulating films.

[0131] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0132] The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0133] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0134] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0135] For the insulator 224, silicon oxide, silicon oxynitride, or the like can be used as appropriate. By providing the insulator 224 containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0136] Further, the insulator 224 in contact with the oxide 230 may contain excess oxygen (oxygen is desorbed by heating). The oxide that desorbs oxygen by heating refers to an oxide in which the desorption amount of oxygen molecules is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, further preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more. Note that the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0137] Further, the insulator 224 is preferably processed into an island shape so as to overlap with the oxide 230a. In this case, the insulator 275 is configured to be in contact with the side surface of the insulator 224 and the top surface of the insulator 222. Accordingly, the insulator 224 and the insulator 280 can be separated by the insulator 275, so that oxygen contained in the insulator 280 is prevented from diffusing into the insulator 224 and causing excess oxygen in the insulator 224.

[0138] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment while the surface of the oxide 230 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0139] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0140] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Although Figure 1B and others show a configuration in which the insulator 224 is superimposed with the oxide 230a to form an island shape, the present invention is not limited to this. If the amount of oxygen contained in the insulator 224 can be appropriately adjusted, the insulator 224 may be configured without patterning, similar to the insulator 222.

[0141] Oxide 243a and oxide 243b are provided on oxide 230b. Oxide 243a and oxide 243b are provided separated by the conductor 260.

[0142] It is preferable that the oxide 243 (oxide 243a and oxide 243b) has the function of suppressing oxygen permeation. Placing the oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or drain electrode, and the oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and the oxide 230b. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. However, if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, a configuration without oxide 243 may be used.

[0143] As oxide 243, a metal oxide containing element M may be used. In particular, element M may be aluminum, gallium, yttrium, or tin. It is preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxide 243 is crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be suitably suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, the release of oxygen from oxide 230 can be suppressed.

[0144] It is preferable that the conductor 242a is provided in contact with the upper surface of the oxide 243a, and the conductor 242b is provided in contact with the upper surface of the oxide 243b. Conductors 242a and 242b function as the source electrode or drain electrode of the transistor 200, respectively.

[0145] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0146] Here, it is preferable to use a film with high compressive stress as the conductor 242, for example, tantalum nitride deposited by sputtering is preferred. The stress in the conductor 242 causes strain in the crystal structure of regions 230ba and 230bb, resulting in oxygen vacancies V in these regions. O This makes it easier for V to form in regions 230ba and 230bb. O Since the amount of H increases, the carrier concentrations in regions 230ba and 230bb can be increased, making it an n-type system.

[0147] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0148] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 1D. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0149] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. Preferably, the insulator 271 has the function of capturing impurities such as hydrogen. In that case, as the insulator 271, an amorphous metal oxide, such as aluminum oxide or magnesium oxide, may be used. In particular, using amorphous aluminum oxide or amorphous aluminum oxide as the insulator 271 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0150] Furthermore, it is preferable that the insulator 271 functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more effectively than the insulator 280. In this case, as the insulator 271, for example, a silicon-containing nitride such as silicon nitride may be used.

[0151] The insulator 275 is provided in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243, the side surface of the conductor 242, and the side surface and top surface of the insulator 271. The insulator 275 has openings formed in the regions where the insulator 250 and the conductor 260 are provided.

[0152] Furthermore, it is preferable that the insulator 275 functions as a barrier insulating film that suppresses oxygen permeation. It is also preferable that the insulator 275 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen, and preferably has the function of capturing impurities such as hydrogen. As the insulator 275, for example, an insulator such as aluminum oxide or silicon nitride may be used as a single layer or in a laminated form. For example, an amorphous aluminum oxide film may be provided, and a silicon nitride film may be laminated on top of it.

[0153] Furthermore, by providing insulators 214, 271, and 275, which have the function of capturing impurities such as hydrogen, within the region sandwiched between insulators 212 and 275, impurities such as hydrogen contained in insulator 224 or insulator 216 can be captured, and the amount of hydrogen in that region can be kept constant. In this case, it is preferable that insulator 275 contains amorphous aluminum oxide.

[0154] The insulator 250 has an insulator 250a and an insulator 250b on the insulator 250a, and functions as a gate insulating film. It is preferable that the insulator 250a is placed in contact with the upper surface of the oxide 230b, the side surface of the oxide 243, the side surface of the conductor 242, the side surface of the insulator 271, the side surface of the insulator 275, and the side surface of the insulator 280. It is also preferable that the film thickness of the insulator 250 be between 1 nm and 20 nm.

[0155] The insulator 250a can be silicon oxide, silicon oxide-nitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxide-nitride are particularly preferred because they are stable to heat.

[0156] Similar to insulator 224, it is preferable that the insulator 250a has a reduced concentration of impurities such as water and hydrogen in insulator 250.

[0157] Preferably, insulator 250a is formed using an insulator that releases oxygen upon heating, and insulator 250b is formed using an insulator that has the function of suppressing oxygen diffusion. With this configuration, the diffusion of oxygen contained in insulator 250a to conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, oxidation of conductor 260 by oxygen contained in insulator 250a can be suppressed. For example, insulator 250b can be provided using the same material as insulator 222.

[0158] Furthermore, when silicon oxide or silicon oxynitride is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0159] Specifically, as the insulator 250b, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used as oxide 230, can be used. In particular, it is preferable to use an insulator containing oxides of aluminum and hafnium, or both. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator. Furthermore, the film thickness of the insulator 250b is preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 1.5 nm or less.

[0160] Although Figures 1B and 1C show the insulator 250 as a two-layer laminated structure, the present invention is not limited to this. The insulator 250 may be a single layer or a laminated structure of three or more layers.

[0161] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0162] Furthermore, the above-mentioned metal oxide may be configured to function as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 can be used as the above-mentioned metal oxide. In that case, the electrical resistance of the above-mentioned metal oxide can be reduced by depositing the conductor 260a by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0163] By having the above-mentioned metal oxide, the on-current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, by maintaining the distance between the conductor 260 and the oxide 230 through the physical thickness of the insulator 250 and the above-mentioned metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a laminated structure of the insulator 250 and the above-mentioned metal oxide, the physical distance between the conductor 260 and the oxide 230, and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0164] The conductor 260 is provided on the insulator 250b and functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 1B and 1C, the top surface of the conductor 260 is approximately aligned with the top of the insulator 250. In Figures 1B and 1C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0165] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0166] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0167] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0168] Here, it is preferable to use a film with high tensile stress as the conductor 260. For example, a structure in which titanium nitride is used for conductor 260a and tungsten for conductor 260b may be used. In this case, conductors 260a and 260b may be deposited using the metal CVD method. The stress of conductor 260 makes the structure of region 230bc denser, thereby suppressing hydrogen diffusion. As a result, V is generated in region 230bc. O Since the amount of H decreases, region 230bc can be made i-type, or effectively i-type.

[0169] Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0170] Furthermore, as shown in Figure 1C, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, it becomes easier to apply the electric field of the conductor 260 to the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of the insulator 222, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0171] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may also be flattened. In this case, it is preferable that the upper surface of the insulator 280 substantially coincides with the uppermost part of the insulator 250 and the upper surface of the conductor 260.

[0172] The insulator 280, which functions as an interlayer insulating film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, parasitic capacitance occurring between wirings can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0173] The insulator 280, like the insulator 224, may have an excess oxygen region or excess oxygen. Furthermore, it is preferable that the insulator 280 has reduced concentrations of impurities such as water and hydrogen. For example, the insulator 280 may be made of a silicon-containing oxide such as silicon oxide or silicon oxynitride. By providing the insulator 280 in contact with the insulator 250a, oxygen can be supplied to the oxide 230 via the insulator 250a. This oxygen reduces oxygen deficiencies in the oxide 230, thereby improving the reliability of the transistor 200.

[0174] The insulator 282 is provided in contact with the upper surface of the insulator 280, the upper surface of the insulator 250, and the upper surface of the conductor 260. Preferably, the insulator 282 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, preferably the insulator 282 functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, for example, an insulator such as aluminum oxide may be used. By providing an insulator 282 in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283, and having the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, it is preferable to use aluminum oxide having an amorphous structure, or aluminum oxide with an amorphous structure, as the insulator 282, because it may be possible to capture or fix hydrogen more effectively. This makes it possible to fabricate a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0175] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a silicon nitride film with high density and less susceptibility to porosity can be formed. Alternatively, as the insulator 283, silicon nitride deposited by ALD may be further laminated on top of the silicon nitride deposited by sputtering. This structure is preferable because even if defects, such as voids, occur in the silicon nitride deposited by sputtering, these voids can be filled by the silicon nitride deposited by the ALD method, which has good coverage, thereby improving sealing performance.

[0176] The insulator 285 is provided on the insulator 283. It is preferable that the insulator 285 be provided using the same material as the insulator 280. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. While Figures 1B and 1C illustrate a structure in which the insulator 285 is provided, the present invention is not limited to this. Alternatively, the insulator 285 may not be provided, and the conductor 246 may be provided in contact with the insulator 283.

[0177] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0178] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 241. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above the insulator 283 into the oxide 230 through the conductor 240a and conductor 240b.

[0179] For insulators 241a and 241b, for example, insulators such as silicon nitride, aluminum oxide, and silicon oxide nitride may be used. Since insulators 241a and 241b are provided in contact with insulators 283, 282, 275, and 271, it is possible to suppress the mixing of impurities such as water and hydrogen contained in insulator 280, etc., into the oxide 230 through conductors 240a and 240b. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0180] Furthermore, conductors 246 (conductors 246a and 246b) that function as wiring may be placed in contact with the upper surfaces of conductors 240a and 240b. It is preferable that the conductors 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0181] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0182] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0183] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0184] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer insulating film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0185] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0186] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0187] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0188] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0189] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0190] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0191] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0192] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride or tantalum nitride may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0193] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 and oxide 243 according to the present invention will be described.

[0194] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0195] Here, a case is considered where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Other elements applicable as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like. However, a plurality of the aforementioned elements may sometimes be combined as element M.

[0196] Note that in this specification and the like, a metal oxide containing nitrogen may also be collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may also be referred to as a metal oxynitride.

[0197] <Classification of Crystal Structure> First, classification of crystal structures in an oxide semiconductor is described with reference to Figure 4A. Figure 4A is a diagram for explaining classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0198] As shown in Figure 4A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the "Crystalline" category. "Crystal" includes single crystal and poly crystal.

[0199] Note that the structure within the bold frame shown in FIG. 4A is an intermediate state between "Amorphous" and "Crystal", and is a structure belonging to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure completely different from "Amorphous" which is energetically unstable and "Crystal".

[0200] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, FIG. 4B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in FIG. 4B is simply referred to as an XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 4B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 4B is 500 nm.

[0201] As shown in FIG. 4B, in the XRD spectrum of the CAAC-IGZO film, a peak indicating clear crystallinity is detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ=31°. Note that as shown in FIG. 4B, the peak in the vicinity of 2θ=31° is asymmetrical about the angle at which the peak intensity is detected.

[0202] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 4C. Figure 4C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0203] As shown in Figure 4C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0204] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 4A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0205] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0206] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0207] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0208] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0209] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0210] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0211] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the sparse arrangement of oxygen atoms in the ab-plane direction, or because the bond distance between atoms changes due to the substitution of metal atoms.

[0212] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0213] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0214] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0215] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0216] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0217] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0218] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (also called a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0219] Here, the atomic ratios of In, Ga, and Zn relative to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0220] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. That is, the first region can be rephrased as a region containing In as a main component. The second region can be rephrased as a region containing Ga as a main component.

[0221] Note that a clear boundary may not be observable between the first region and the second region.

[0222] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by an EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the CAC-OS has a structure in which the region containing In as a main component (the first region) and the region containing Ga as a main component (the second region) are unevenly distributed and mixed.

[0223] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0224] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0225] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0226] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0227] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0228] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0229] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0230] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0231] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0232] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are measured as 2 × 10⁻¹⁰. 18atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0233] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0234] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0235] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these oxygen vacancies, electrons, which act as carriers, may be generated. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0236] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0237] <<Other Semiconductor Materials>> The semiconductor material that can be used for oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as the semiconductor material. In particular, it is preferable to use layered materials that function as semiconductors as the semiconductor material.

[0238] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0239] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0240] As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0241] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention, as shown in Figures 1A to 1D, will be explained using Figures 5A to 15A, 5B to 15B, 5C to 15C, and 5D to 15D.

[0242] Figures 5A to 15A show top views. Figures 5B to 15B are cross-sectional views corresponding to the area indicated by the dashed line A1-A2 in Figures 5A to 15A, and are also cross-sectional views of transistor 200 in the channel length direction. Figures 5C to 15C are cross-sectional views corresponding to the area indicated by the dashed line A3-A4 in Figures 5A to 15A, and are also cross-sectional views of transistor 200 in the channel width direction. Figures 5D to 15D are cross-sectional views of the area indicated by the dashed line A5-A6 in Figures 5A to 15A. Note that some elements have been omitted from the top views of Figures 5A to 15A for clarity.

[0243] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD as appropriate.

[0244] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0245] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma (sometimes called plasma chemical vapor deposition), thermal CVD (TCVD), which utilizes heat, and photo-CVD, which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used (sometimes called metal-organic chemical vapor deposition).

[0246] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0247] Furthermore, ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants.

[0248] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures. The PEALD method, by utilizing plasma, allows for even lower temperatures, which can be preferable in some cases. However, some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0249] Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0250] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by varying the flow rate ratio of the source gases during film deposition. When depositing films while varying the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because the time required for transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0251] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 5A to 5D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0252] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas-containing atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrodes, improving the sputtering rate and film quality.

[0253] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0254] Next, an insulator 214 is deposited on the insulator 212 (see Figures 5A to 5D). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0255] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm². 2The above is 1.86 W / cm². 2 The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0256] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture a transistor 200 and semiconductor device with good properties and high reliability.

[0257] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0258] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0259] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0260] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening includes, for example, grooves or slits. In some cases, the term "opening" refers to the region in which the opening is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214. Note that a recess may be formed in the insulator 214 superimposed on the opening in the insulator 216.

[0261] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0262] After the opening is formed, a conductive film that will become the conductor 205a is deposited. It is desirable that the conductive film that will become the conductor 205a contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film that will become the conductor 205a can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0263] In this embodiment, titanium nitride is deposited as a conductive film to form the conductor 205a. By providing such a metal nitride in contact with the lower and side surfaces of the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0264] Next, a conductive film to become the conductor 205b is deposited. As the conductive film to become the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc., can be used. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, tungsten is deposited as the conductive film to become the conductor 205b.

[0265] Next, by performing a CMP treatment, a portion of the conductive film that will become conductor 205a and the conductive film that will become conductor 205b is removed, exposing the insulator 216 (see Figures 5A to 5D). As a result, conductor 205a and conductor 205b remain only in the opening. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0266] Next, etching is performed to remove the upper part of the conductor 205b (see Figures 6A to 6D). As a result, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. Dry etching or wet etching can be used for etching the conductor 205b, but dry etching is preferable for microfabrication.

[0267] Next, a conductive film that will become conductor 205c is formed on the insulator 216, conductor 205a, and conductor 205b. It is desirable that the conductive film that will become conductor 205c contains a conductor that has the function of suppressing oxygen permeation, similar to the conductive film that will become conductor 205a.

[0268] In this embodiment, titanium nitride is deposited as a conductive film that forms the conductor 205c. By using such a metal nitride as the upper layer of the conductor 205b, oxidation of the conductor 205b by the insulator 222 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0269] Next, by performing CMP treatment, a portion of the conductive film that will become the conductor 205c is removed, exposing the insulator 216 (see Figures 7A to 7D). As a result, the conductors 205a, 205b, and 205c remain only in the openings. This makes it possible to form a conductor 205 with a flat top surface. Furthermore, the conductor 205b is enclosed by the conductors 205a and 205c. Therefore, it is possible to prevent impurities such as hydrogen from conductor 205b from diffusing out of conductors 205a and 205c, and to prevent oxygen from entering from outside conductors 205a and 205c and oxidizing conductor 205b. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0270] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 8A to 8D). It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0271] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method.

[0272] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0273] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0274] In this embodiment, as a heat treatment, after the insulator 222 is formed, a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm is used, and the treatment is performed at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the insulator 224 is formed.

[0275] Next, an insulating film 224A is deposited on the insulator 222. The insulating film 224A can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is deposited as the insulating film 224A using the sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0276] Next, oxide films 230A and 230B are sequentially deposited on the insulating film 224A (see Figures 8A to 8D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0277] The oxide films 230A and 230B can be deposited using sputtering, CVD, MOCVD, MBE, PLD, ALD, and other methods.

[0278] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0279] Furthermore, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0280] Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0281] In this embodiment, oxide film 230A is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1. Note that each oxide film may be formed according to the desired properties of oxide 230a and oxide 230b by appropriately selecting the deposition conditions and atomic ratios.

[0282] Next, an oxide film 243A is deposited on the oxide film 230B (see Figures 8A to 8D). The oxide film 243A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the atomic ratio of Ga to In in the oxide film 243A is greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is deposited by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4.

[0283] Furthermore, it is preferable to deposit the insulator 222, insulating film 224A, oxide film 230A, oxide film 230B, and oxide film 243A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus may be used. This allows for the deposition of the insulator 222, insulating film 224A, oxide film 230A, oxide film 230B, and oxide film 243A with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0284] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which oxide films 230A, 230B, and 243A do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0285] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A, oxide film 230B, and oxide film 243A, etc.

[0286] In this embodiment, the heat treatment involves treating the oxide film at 400°C for 1 hour in a nitrogen atmosphere, followed by a continuous treatment at 400°C for 1 hour in an oxygen atmosphere. This heat treatment can remove impurities such as water and hydrogen from oxide films 230A, 230B, and 243A. Furthermore, this heat treatment can improve the crystallinity of oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities within oxide film 230B.

[0287] Next, a conductive film 242A is deposited on the oxide film 243A (see Figures 8A to 8D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, oxide film 230B, and oxide film 243A can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0288] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 8A to 8D). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, aluminum oxide can be deposited as the insulating film 271A by sputtering.

[0289] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 271A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus may be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242A and the insulating film 271A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 271A, the hard mask film may also be deposited continuously without exposure to the atmosphere.

[0290] Next, the insulating film 224A, oxide film 230A, oxide film 230B, oxide film 243A, conductive film 242A, and insulating film 271A are processed into island-like structures using lithography to form the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B (see Figures 9A to 9D). This processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the insulating film 224A, oxide film 230A, oxide film 230B, oxide film 243A, conductive film 242A, insulating film 271A, and insulating layer 271B may each be processed under different conditions.

[0291] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0292] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulating layer 271B is used as the hard mask.

[0293] Here, the insulating layer 271B functions as a mask for the conductive layer 242B, so as shown in Figures 9B to 9D, the conductive layer 242B does not have a curved surface between its side and top surfaces. As a result, the conductors 242a and 242b shown in Figures 1B and 1D have angular ends where their side and top surfaces intersect. The angular shape of the ends where the side and top surfaces of the conductor 242 intersect increases the cross-sectional area of ​​the conductor 242 compared to when the ends have a curved surface. This reduces the resistance of the conductor 242, allowing the on-current of the transistor 200 to be increased.

[0294] Furthermore, the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B are formed so that at least a portion of them overlaps with the conductor 205. It is also preferable that the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B are approximately perpendicular to the upper surface of the insulator 222. Having the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B approximately perpendicular to the upper surface of the insulator 222 allows for smaller area and higher density when providing multiple transistors 200. Alternatively, the angle between the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B and the top surface of the insulator 222 may be low. In this case, the angle between the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B and the top surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0295] Furthermore, by-products generated in the etching process may form in layers on the sides of the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and the insulator 275. Similarly, layered by-products may also form on the insulator 224. Even if the insulator 275 is deposited with the layered by-products formed on the insulator 224, the addition of oxygen to the insulator 224 will be hindered by the layered by-products. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 224.

[0296] Next, an insulator 275 is deposited on the insulator 224 and the insulating layer 271B. (See Figures 10A to 10D.) The insulator 275 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation for the insulator 275. For example, silicon nitride can be deposited as the insulator 275 by sputtering. Alternatively, aluminum oxide can be deposited as the insulator 275 using sputtering, and then silicon nitride can be deposited on top of it.

[0297] In this way, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B can be covered with insulator 275 and insulating layer 271B, which have the function of suppressing oxygen diffusion. This reduces the diffusion of oxygen into oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B in subsequent processes.

[0298] Next, an insulating film, which will become an insulator 280, is deposited on the insulator 275. This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film that will become the insulator 280 using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, oxide layer 243B, and insulator 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0299] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 10A to 10D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0300] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. It is preferable that the opening be formed so as to overlap with the conductor 205. The formation of the opening creates the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b (see Figures 11A to 11D).

[0301] When forming the above-mentioned opening, the upper part of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the opening formation step or in a step different from the opening formation step.

[0302] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. In addition, each of these processes may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. Also, the processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B and the processing of a portion of the oxide 230b may be carried out under different conditions.

[0303] Here, impurities may adhere to the sides of oxide 230a, the top and sides of oxide 230b, the sides of conductor 242, the sides of insulator 280, etc., or diffuse into these surfaces. A step to remove such impurities may be performed. In addition, a damaged area may be formed on the surface of oxide 230b during the dry etching process. Such a damaged area may be removed. Examples of such impurities include those resulting from components contained in insulator 280, insulator 275, a part of insulating layer 271B, and conductive layer 242B, components contained in materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0304] In particular, impurities such as aluminum or silicon inhibit the CAAC-OS conversion of oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum or silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0305] Furthermore, the region of a metal oxide where CAAC-OS formation is inhibited by impurities such as aluminum or silicon, resulting in a pseudo-amorphous-like oxide semiconductor (a-like OS), is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230b is reduced or removed.

[0306] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0307] To remove the impurities mentioned above, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and heat treatment. These cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process.

[0308] For wet cleaning, cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0309] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0310] Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides such as 230b.

[0311] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0312] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior of oxides 230a and 230b. Furthermore, it can improve the crystallinity of oxide 230b.

[0313] Heat treatment may be performed after etching or cleaning as described above. The heat treatment should be performed at a temperature of 100°C to 500°C, preferably 300°C to 500°C, and more preferably 350°C to 400°C. The heat treatment may be performed in an atmosphere of nitrogen gas, an inert gas, or an oxidizing gas. Alternatively, it may be performed in an atmosphere containing nitrogen gas or an inert gas with an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby eliminating oxygen deficiency V O This can reduce the amount of waste. Furthermore, this heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere. In the case of performing heat treatment in an oxygen atmosphere followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere, the heat treatment in the oxygen atmosphere may be performed for a longer period than the heat treatment in the nitrogen atmosphere.

[0314] Next, an insulating film 250A is deposited (see Figures 12A to 12D). A heat treatment may be performed before depositing the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of oxide 230b can be removed, and the moisture and hydrogen concentrations in oxide 230a and oxide 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0315] The insulating film 250A can be deposited using methods such as sputtering, CVD, PECVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will become an insulator 250a that comes into contact with the oxide 230b in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0316] Furthermore, it is preferable to deposit the insulating film 250A using the ALD method. The thickness of the insulator 250, which functions as the gate insulating film of the miniaturized transistor 200, needs to be extremely thin (for example, about 5 nm to 30 nm) and have minimal variation. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (for example, an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Therefore, the accuracy of the gate insulating film thickness required by the miniaturized transistor 200 can be achieved. Also, as shown in Figures 12B and 12C, the insulating film 250A needs to be deposited with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be deposited with good coverage on the opening.

[0317] Furthermore, for example, when a hydrogen-containing gas such as SiH4 (or Si2H6) is used as the deposition gas to deposit insulating film 250A using the PECVD method, the hydrogen-containing deposition gas decomposes in the plasma, generating a large amount of hydrogen radicals. The reduction reaction of the hydrogen radicals extracts oxygen from the oxide 230b, resulting in V O When H is formed, the hydrogen concentration in oxide 230b increases. However, by depositing the insulating film 250A using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor is introduced and when the reactant is introduced. Therefore, by depositing the insulating film 250A using the ALD method, it is possible to prevent the hydrogen concentration in oxide 230b from increasing.

[0318] If the above-mentioned impurities are not removed before the deposition of the insulating film 250A, these impurities may remain between the oxide 230a, oxide 230b, conductor 242, insulator 280, etc., and the insulator 250a.

[0319] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere (see Figures 12A to 12D). Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves may also refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0320] As shown in Figures 12B to 12D, the dotted lines represent high-frequency oxygen plasma such as microwaves or RF, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. The power of the power supply for applying microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b.

[0321] Furthermore, the above microwave treatment is preferably carried out under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. For example, it may be 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less. The treatment temperature may be 750°C or less, preferably 500°C or less, for example, around 400°C. In addition, after the oxygen plasma treatment, heat treatment may be carried out continuously without exposure to the outside air. For example, it may be 100°C or more and 750°C or less, preferably 300°C or more and 500°C or less.

[0322] Furthermore, for example, the above microwave treatment may be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / O2+Ar) should be greater than 0% and 100% or less. Preferably, the oxygen flow rate ratio (O2 / O2+Ar) should be greater than 0% and 50% or less. More preferably, the oxygen flow rate ratio (O2 / O2+Ar) should be 10% or more and 40% or less. Even more preferably, the oxygen flow rate ratio (O2 / O2+Ar) should be 10% or more and 30% or less. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. Also, by preventing excessive amounts of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent excessive reduction of carrier concentration in regions 230ba and 230bb. Also, by preventing excessive amounts of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent excessive oxidation of the sides of conductors 242a and 242b.

[0323] As shown in Figures 12B to 12D, by performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 230bc. In other words, microwaves or high-frequency oxygen plasma such as RF can be applied to region 230bc shown in Figure 2. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen H can be removed from region 230bc. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, and V is included in region 230bc. O H can be reduced. Therefore, oxygen deficiency in region 230bc, and V OBy reducing H, the carrier concentration can be lowered. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancy formed in region 230bc, the oxygen vacancy in region 230bc can be further reduced, and the carrier concentration can be lowered.

[0324] Meanwhile, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Figure 2. Here, it is preferable that the conductor 242 functions as a shielding film against the effects of microwaves, high frequencies such as RF, and oxygen plasma when microwave processing is performed in an oxygen-containing atmosphere. For this reason, it is preferable that the conductor 242 has the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example between 2.4 GHz and 2.5 GHz.

[0325] As shown in Figures 12B to 12D, conductors 242a and 242b shield against the effects of microwaves or high-frequency oxygen plasma such as RF, so these effects do not extend to regions 230ba and 230bb. As a result, microwave processing does not affect regions 230ba and 230bb. O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0326] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0327] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability. Additionally, it is possible to provide a semiconductor device with good electrical characteristics.

[0328] Next, an insulating film that will become the insulator 250b is deposited. The insulating film that will become the insulator 250b can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable that the insulating film that will become the insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulating film 250A can be made using the same material as the insulator 250a described above, and the insulating film that will become the insulator 250b can be made using the same material as the insulator 222.

[0329] Specifically, as the insulating film that forms the insulator 250b, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used as oxide 230, can be used. In particular, it is preferable to use an insulator that contains oxides of aluminum and hafnium, or both.

[0330] In this embodiment, silicon oxynitride is deposited as the insulating film 250A by CVD, and hafnium oxide is deposited as the insulating film that will become the insulator 250b by thermal ALD.

[0331] Microwave treatment may be performed after the deposition of the insulating film that will become the insulator 250b. This microwave treatment may use the same microwave treatment conditions as those used after the deposition of the insulating film 250A. Alternatively, the microwave treatment performed after the deposition of the insulating film that will become the insulator 250b may be performed without performing the microwave treatment that is performed after the deposition of the insulating film 250A.

[0332] Furthermore, after the deposition of the insulating film 250A and after the deposition of the insulating film that will become the insulator 250b, a heat treatment may be performed while maintaining a reduced pressure state. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the insulating film that will become the insulator 250b, the oxide 230b, and the oxide 230a. In addition, some of the hydrogen may be gettered into the conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from the insulating film 250A, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C to 500°C.

[0333] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 250A and the insulating film 250b, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., to oxides 230b and 230a via the insulating film 250 can be suppressed.

[0334] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, the conductive film to become conductor 260a is deposited using the ALD method, and the conductive film to become conductor 260b is deposited using the CVD method.

[0335] Next, by CMP treatment, the insulating film 250A, the insulating film that will become the insulator 250b, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished until the insulator 280 is exposed, thereby forming the insulator 250a, the insulator 250b, the conductor 260a, and the conductor 260b (see Figures 13A to 13D). As a result, the insulator 250 is positioned to cover the openings that reach the oxide 230b and the inner walls (side walls and bottom surface) of the grooves in the oxide 230b. The conductor 260 is positioned to fill the openings and grooves via the insulator 250.

[0336] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0337] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280 (see Figures 14A to 14D). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 282 can be reduced. Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 while the film is being deposited. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate.

[0338] In this embodiment, aluminum oxide is deposited as the insulator 282 using pulsed DC sputtering with an aluminum target in an atmosphere containing oxygen gas. Using pulsed DC sputtering allows for a more uniform film thickness distribution, improving the sputtering rate and film quality. The RF power applied to the substrate is 1.86 W / cm². 2 The following applies: Preferably, 0 W / cm² 2 More than 0.31W / cm 2 The following applies: By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. In this embodiment, the insulator 282 is formed as a two-layer laminated structure. The lower layer of the insulator 282 is formed when the RF power applied to the substrate is 0 W / cm². 2 The film is formed as follows, and the upper layer of the insulator 282 is subjected to an RF power applied to the substrate at 0.31 W / cm². 2 It is used to form a film.

[0339] Next, an insulator 283 is formed on the insulator 282 (see Figures 14A to 14D). The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 283 using sputtering. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using CVD.

[0340] Next, a heat treatment may be performed. In this embodiment, the treatment is carried out at a temperature of 400°C for 1 hour in a nitrogen atmosphere. This heat treatment allows the oxygen added by the formation of the insulator 282 to diffuse into the insulators 280 and 250, as shown in Figure 2, and selectively supply it to the channel formation region of the oxide 230. Note that this heat treatment may be performed not only after the formation of the insulator 283, but also after the formation of the insulator 282, etc.

[0341] Next, an insulator 285 is deposited on the insulator 283. This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods. For example, a silicon oxide film can be deposited as the insulating film using the CVD method.

[0342] Next, openings reaching the conductor 242 are formed in insulators 271, 275, 280, 282, 283, and 285 (see Figures 15A to 15D). These openings may be formed using lithography. In Figure 15A, the shape of the opening is circular in a top view, but it is not limited to this. For example, the opening may be approximately circular, such as an ellipse, polygonal, such as a quadrilateral, or a polygonal shape with rounded corners in a top view.

[0343] Next, an insulating film to form the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241. (See Figures 15A to 15D.) The insulating film to form the insulator 241 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film to form the insulator 241. For example, it is preferable to deposit aluminum oxide using the ALD method. Alternatively, it is preferable to deposit silicon nitride using the PEALD method. Silicon nitride is preferred because it has high barrier properties against hydrogen.

[0344] Furthermore, for the anisotropic etching of the insulating film that will become the insulator 241, a dry etching method, for example, can be used. By providing the insulator 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b that will be formed next can be prevented. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0345] Next, conductive films that will become conductor 240a and conductor 240b are deposited. It is desirable that the conductive films that will become conductor 240a and conductor 240b have a laminated structure containing a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc., can be formed. The conductive film that will become conductor 240 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0346] Next, by performing a CMP treatment, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 15A to 15D). Note that this CMP treatment may remove a portion of the upper surface of the insulator 285.

[0347] Next, a conductive film to become conductor 246 is deposited. The conductive film to become conductor 246 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0348] Next, a conductive film to become the conductor 246 is processed by lithography to form a conductor 246a that contacts the upper surface of the conductor 240a, and a conductor 246b that contacts the upper surface of the conductor 240b. At this time, a portion of the insulator 285 in the region where the conductors 246a and 246b do not overlap with the insulator 285 may be removed.

[0349] As described above, a semiconductor device having the transistor 200 shown in Figures 1A to 1D can be fabricated. As shown in Figures 5A to 15A, 5B to 15B, 5C to 15C, and 5D to 15D, the transistor 200 can be fabricated using the semiconductor device fabrication method shown in this embodiment.

[0350] <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the manufacturing method of the semiconductor device described above.

[0351] First, we will explain the configuration of a manufacturing apparatus that can reduce the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 16, 17, and 18.

[0352] Figure 16 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0353] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0354] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0355] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ -4 Pa or less, preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a m / z of 28 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with m / z of 44 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 It should be Pa or less.

[0356] The total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also known as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0357] Furthermore, it is desirable that the transport chamber 2704 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 2704 and each chamber should be 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 18 is 1 × 10⁻⁶. -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 28 is 1 × 10⁻⁶. -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 Set to / s or less.

[0358] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on both external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system through tiny holes or faulty seals. Internal leaks are caused by leaks from valves or other partitions within the vacuum system, or by gases released from internal components. To keep the leak rate below the values ​​mentioned above, countermeasures must be taken from both external and internal leaks.

[0359] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage.

[0360] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0361] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0362] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0363] The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0364] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, thereby reducing the amount of impurities present in the transport chamber 2704 and each chamber. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the pressure can be maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0365] Next, chambers 2706b and 2706c will be explained using the schematic cross-sectional diagrams shown in Figure 17.

[0366] Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below.

[0367] Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside of chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0368] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0369] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has the function of heating the substrate 2811.

[0370] As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal.

[0371] Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0372] Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0373] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0374] The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0375] At this time, the substrate 2811 can be modified by ions and radicals generated in the high-density plasma 2810, which can alter the film on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using a high-frequency power supply 2816. For example, an RF power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used for the high-frequency power supply 2816. By applying a bias to the substrate, ions in the high-density plasma 2810 can be efficiently delivered to the back of openings in the film on the substrate 2811.

[0376] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0377] Next, chambers 2706a and 2706d will be explained using the schematic cross-sectional diagrams shown in Figure 18.

[0378] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below.

[0379] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0380] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0381] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0382] For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0383] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0384] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0385] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0386] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0387] <Examples of semiconductor device applications> In the following section, using Figures 19A and 19B, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, different from those shown in the previous <Example of Semiconductor Device Configuration> and <Modified Examples of Semiconductor Devices>, will be described. In the semiconductor device shown in Figures 19A and 19B, structures having the same function as those constituting the semiconductor device shown in <<Example of Semiconductor Device Configuration>> (see Figures 1A to 1D) will be denoted by the same reference numerals. In this section, the materials used for the transistor 200 can be those described in detail in <Example of Semiconductor Device Configuration>.

[0388] Figures 19A and 19B show a configuration in which multiple transistors 200_1 to 200_n are enclosed and sealed with insulators 283 and 212. Note that in Figures 19A and 19B, transistors 200_1 to 200_n appear to be aligned in the channel length direction, but this is not the only arrangement. Transistors 200_1 to 200_n may be aligned in the channel width direction, or arranged in a matrix. Furthermore, they may be arranged without any regularity depending on the design.

[0389] As shown in Figure 19A, a portion where the insulator 283 and the insulator 212 are in contact (hereinafter sometimes referred to as the sealing portion 265) is formed on the outside of multiple transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the multiple transistors 200_1 to 200_n. With this structure, multiple transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Thus, multiple groups of transistors surrounded by the sealing portion 265 are provided on the substrate. In this case, it is preferable that the insulator 285 is provided in the sealing portion 265 so as to fill the recess of the insulator 283.

[0390] As shown in Figure 19A, it is preferable that the insulators 216, 222, 275, 280, and 282 are patterned in the region surrounded by the sealing portion 265. Furthermore, the insulator 283 has a structure that covers the insulators 216, 222, 275, 280, and 282. In other words, the insulator 283 is in contact with the top surface of the insulator 282, the sides of the insulators 216, 222, 275, and 280, and the top surface of the insulator 214. As a result, the insulators 216, 222, 224, 280, and 282, which contain oxides 230, are isolated from the outside by the insulators 283, 214, and 212. In other words, the multiple transistors 200_1 to 200_n are arranged within a region sealed by insulators 283, 214, and 212.

[0391] For example, insulators 214 and 282 may be formed using materials that have the function of capturing and fixing hydrogen. Insulators 212 and 283 may be formed using materials that have the function of suppressing diffusion to hydrogen and oxygen. Typically, aluminum oxide can be used for insulators 214 and 282. Also typically, silicon nitride can be used for insulators 212 and 283.

[0392] By using the above configuration, it is possible to suppress the mixing of hydrogen contained outside the sealed region into the sealed region.

[0393] Furthermore, although the transistor 200 shown in Figure 19A is configured in which the insulator 212 and the insulator 283 are provided as single layers, the present invention is not limited to this. For example, the insulator 212 and the insulator 283 may each be provided as a laminated structure of two or more layers.

[0394] Furthermore, a dicing line (sometimes called a scribe line, division line, or cutting line) may be provided on top of the sealing portion 265. Since the substrate is divided at the dicing line, the group of transistors surrounded by the sealing portion 265 will be extracted as a single chip.

[0395] Furthermore, while Figure 19A shows an example where multiple transistors 200_1 to 200_n are enclosed by a single sealing portion 265, the configuration is not limited to this. As shown in Figure 19B, multiple transistors 200_1 to 200_n may be enclosed by multiple sealing portions. In Figure 19B, multiple transistors 200_1 to 200_n are enclosed by a sealing portion 265a, and further enclosed by an outer sealing portion 265b.

[0396] In this way, by surrounding multiple transistors 200_1 to 200_n with multiple sealing portions, the contact area between insulator 283 and insulator 214 increases, thereby improving the adhesion between insulator 283 and insulator 214. This allows for more reliable sealing of multiple transistors 200_1 to 200_n.

[0397] In this case, the dicing line may be provided on top of the sealing portion 265a or the sealing portion 265b, or the dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0398] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0399] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments.

[0400] (Embodiment 2) In this embodiment, one form of a semiconductor device will be described using Figures 20 to 25.

[0401] [Storage device 1] Figure 20 shows an example of a semiconductor device (memory device) according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, transistor 200 is provided above transistor 300, and capacitive element 100 is provided above transistor 300 and transistor 200. Note that the transistor 200 can be the same transistor 200 described in the previous embodiment.

[0402] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Because transistor 200 has a small off-current, it can be used in a memory device to retain stored data for a long period of time. In other words, because refresh operations are not required, or are performed very infrequently, the power consumption of the memory device can be significantly reduced.

[0403] In the semiconductor device shown in Figure 20, wire 1001 is electrically connected to the source of transistor 300, and wire 1002 is electrically connected to the drain of transistor 300. Wire 1003 is electrically connected to one of the source and drain of transistor 200, wire 1004 is electrically connected to the first gate of transistor 200, and wire 1006 is electrically connected to the second gate of transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitive element 100, and wire 1005 is electrically connected to the other electrode of capacitive element 100.

[0404] Furthermore, the memory devices shown in Figure 20 can be arranged in a matrix to form a memory cell array.

[0405] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0406] In Figure 20, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0407] Note that the transistor 300 shown in Figure 20 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0408] <Capacitive element 100> The capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, it is preferable to use an insulator 130 that can be used as the insulator 275 shown in the above embodiment.

[0409] Furthermore, for example, the conductor 112 provided on the conductor 240 and the conductor 110 can be formed simultaneously. The conductor 112 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300. The conductors 112 and 110 correspond to the conductor 246 shown in the previous embodiment.

[0410] In Figure 20, the conductors 112 and 110 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0411] Furthermore, the insulator 130 may be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, etc., and can be provided in a laminated or single layer.

[0412] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitive element 100 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 100.

[0413] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) that serve as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0414] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and porous silicon oxide or resins.

[0415] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0416] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0417] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0418] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 20, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0419] Similarly, insulators 210, 212, 214, and 216 have conductors 218 and conductors (conductors 205) that constitute the transistor 200 embedded in them. Conductors 218 function as plugs or wires that electrically connect to the capacitive element 100 or the transistor 300. Furthermore, insulators 150 are provided on conductors 120 and insulator 130.

[0420] Here, similar to the insulator 241 shown in the above embodiment, an insulator 217 is provided in contact with the side surface of the conductor 218, which functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, so the insulator 217 may also be formed in contact with the side surface of the conductor 205.

[0421] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with insulators 210, 212, 214, and 222, it is possible to suppress the incorporation of impurities such as water or hydrogen from insulators 210 or 216 into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in insulators 210 or 216 from being absorbed by the conductor 218.

[0422] The insulator 217 can be formed in the same manner as the insulator 241. For example, silicon nitride can be deposited using the PEALD method, and an opening reaching the conductor 356 can be formed using anisotropic etching.

[0423] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0424] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0425] For example, it is preferable that insulators 150, 210, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxidizite, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxidizite are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0426] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0427] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0428] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0429] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 218, and 112, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0430] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used in the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0431] For example, in Figure 20, an insulator 241 may be provided between the insulators 285 and 280, which have excess oxygen or impurities, and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 275, 282, and 283, the insulator 224 and the transistor 200 can be sealed by a barrier insulator.

[0432] In other words, by providing the insulator 241, it is possible to suppress the absorption of excess oxygen in the insulator 280 into the conductor 240. Furthermore, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, into the transistor 200 via the conductor 240.

[0433] Furthermore, as the insulator 241, an insulating material having the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferable. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide are preferred. Silicon nitride is particularly preferred because of its high barrier properties against hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0434] Furthermore, as shown in the above embodiment, the transistor 200 may be configured to be sealed with insulators 212, 214, 282, and 283. This configuration reduces the amount of hydrogen contained in insulators 285, 150, etc., that mixes into insulator 280, etc.

[0435] Here, the conductor 240 penetrates insulators 283 and 282, and the conductor 218 penetrates insulators 214 and 212. However, as described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This reduces the amount of hydrogen that enters the inside of insulators 212, 214, 282, and 283 via conductors 240 and 218. In this way, the transistor 200 is sealed with insulators 212, 214, 282, 283, 241, and 217, reducing the amount of impurities such as hydrogen contained in insulator 285, etc., that enter from the outside.

[0436] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0437] Here, for example, as shown in Figure 20, it is preferable to design the region where insulator 283 and insulator 212 are in contact to overlap with the dicing line. In other words, openings are provided in insulators 282, 280, 275, 222, 216, and 214 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0438] In other words, insulator 212 and insulator 283 are in contact with each other at the openings provided in insulators 282, 280, 275, 222, 216, and 214. For example, in this case, insulator 212 and insulator 283 may be formed using the same material and method. By providing insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride is preferably used.

[0439] This structure allows the transistor 200 to be enclosed by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor element shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into the transistor 200.

[0440] Furthermore, this structure prevents excess oxygen from the insulator 280 from diffusing to the outside. Therefore, excess oxygen from the insulator 280 is efficiently supplied to the oxide in which the channel in the transistor 200 is formed. This oxygen reduces oxygen vacancies in the oxide in which the channel in the transistor 200 is formed. As a result, the oxide in which the channel in the transistor 200 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of the transistor 200 can be suppressed and reliability can be improved.

[0441] In the memory device shown in Figure 20, the capacitive element 100 is of the planar type, but the memory device shown in this embodiment is not limited to this. For example, as shown in Figure 21, the capacitive element 100 may be of the cylindrical type. In the memory device shown in Figure 21, the configuration below the insulator 150 is the same as that of the semiconductor device shown in Figure 20.

[0442] The capacitive element 100 shown in Figure 21 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed within openings formed in insulators 150 and 142, an insulator 145 on the conductor 115 and insulator 142, a conductor 125 on insulator 145, and an insulator 152 on the conductor 125 and insulator 145. Here, at least a portion of the conductors 115, 145, and 125 are disposed within openings formed in insulators 150 and 142. In addition, an insulator 154 is disposed on insulator 152, and conductors 153 and 156 are disposed on insulator 154. Here, the conductor 140 is provided within openings formed in insulators 130, 150, 142, 145, 152, and 154.

[0443] The conductor 115 functions as the lower electrode of the capacitive element 100, the conductor 125 functions as the upper electrode of the capacitive element 100, and the insulator 145 functions as the dielectric of the capacitive element 100. In the openings of the insulators 150 and 142, the upper and lower electrodes of the capacitive element 100 are configured to face each other with the dielectric in between, not only on the bottom surface but also on the sides, allowing for a large capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0444] The insulator 152 may be any insulator that can be used for the insulator 280. Furthermore, the insulator 142 preferably functions as an etching stopper when forming the opening in the insulator 150, and may be any insulator that can be used for the insulator 214.

[0445] The shape of the openings formed in the insulators 150 and 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. In this case, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0446] The conductor 115 is positioned in contact with the openings formed in the insulators 142 and 150. Preferably, the uppermost part of the conductor 115 substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed using the ALD method or the CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0447] The insulator 145 is arranged to cover the conductor 115 and the insulator 142. For example, it is preferable to deposit the insulator 145 using the ALD method or the CVD method. The insulator 145 can be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium nitride, hafnium oxide, hafnium nitride, etc., and can be provided in a laminated or single layer. For example, as the insulator 145, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0448] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxidative nitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0449] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) used as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitive element 100 can be sufficiently secured even if the insulator 145 is made thicker. By making the insulator 145 thicker, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0450] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, and resins. For example, silicon nitride (SiN) deposited using the ALD method. x ), silicon oxide (SiO2) deposited using the PEALD method x ), silicon nitride (SiN) deposited using the ALD method x An insulating film can be used that is stacked in the order of ). By using such an insulator with high dielectric strength, the dielectric strength can be improved and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0451] The conductor 125 is positioned to fill the openings formed in the insulators 142 and 150. The conductor 125 is also electrically connected to the wiring 1005 via the conductors 140 and 153. The conductor 125 is preferably formed using the ALD method or CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0452] Furthermore, the conductor 153 is provided on the insulator 154 and covered by the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the upper surface of the conductor 140 and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.

[0453] [Storage device 2] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in Figure 22.

[0454] <Example of memory device configuration> Figure 22 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in Figure 22 has a capacitive device 292 in addition to the transistors 200 shown in Figures 1A to 1D. Figure 22 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0455] The capacitive device 292 comprises a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 275 covering the conductor 242b and the insulator 271b, and a conductor 294 on the insulator 275. In other words, the capacitive device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. One of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, can also serve as the source electrode of the transistor. Furthermore, the dielectric layer of the capacitive device 292 can also serve as the protective layer provided on the transistor, i.e., the insulators 271 and 275. Therefore, since part of the manufacturing process for the transistor can be shared in the manufacturing process for the capacitive device 292, a highly productive semiconductor device can be produced. In addition, since one of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area required for the placement of the transistor and the capacitive device.

[0456] For example, the conductor 294 can be any material that can be used for the conductor 242.

[0457] <Examples of memory devices> In the following section, using Figures 23A, 23B, 24, and 25, an example of a semiconductor device having a transistor 200 and a capacitive device 292 according to one aspect of the present invention, different from that shown in the previous <Example of Memory Device Configuration>, will be described. In the semiconductor device shown in Figures 23A, 23B, 24, and 25, structures having the same function as those constituting the semiconductor device shown in the previous embodiment and <Example of Memory Device Configuration> (see Figure 22) will be denoted by the same reference numerals. In this section, the materials used for the transistor 200 and the capacitive device 292 can be those described in detail in the previous embodiment and <Example of Memory Device Configuration>.

[0458] <<Differential Example of Memory Device 1>> In the following, an example of a semiconductor device 600 having transistors 200a, 200b, capacitive device 292a, and capacitive device 292b according to one aspect of the present invention will be described with reference to Figure 23A.

[0459] Figure 23A is a cross-sectional view in the channel length direction of a semiconductor device 600 having transistors 200a, 200b, capacitive devices 292a, and 292b. Here, the capacitive device 292a includes a conductor 242a, an insulator 271a provided on the conductor 242a, an insulator 275 provided covering the conductor 242a and the insulator 271a, and a conductor 294a provided on the insulator 275. The capacitive device 292b includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 275 provided covering the conductor 242b and the insulator 271b, and a conductor 294b provided on the insulator 275.

[0460] As shown in Figure 23A, the semiconductor device 600 has a symmetrical configuration with respect to the dashed line A3-A4 as the axis of symmetry. One of the source or drain electrodes of transistor 200a and the other of the source or drain electrode of transistor 200b are both provided by the conductor 242c. An insulator 271c is provided on the conductor 242c. An oxide 243c is provided beneath the conductor 242c. Furthermore, the conductor 246, which functions as wiring, and the conductor 240, which functions as a plug, are both provided. In this way, by providing the two transistors, two capacitive devices, and the connections between the wiring and plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0461] The configurations and effects of transistors 200a, 200b, capacitive device 292a, and 292b can be seen in the semiconductor device configuration examples shown in Figures 1A to 1D and Figure 22.

[0462] <<Modified Memory Device 2>> In the above, transistors 200a, 200b, capacitive device 292a, and 292b were given as examples of semiconductor device configurations, but the semiconductor device shown in this embodiment is not limited to these. For example, as shown in Figure 23B, a semiconductor device 600 and a semiconductor device having a similar configuration to semiconductor device 600 may be connected via a capacitive section. In this specification, a semiconductor device having transistors 200a, 200b, capacitive device 292a, and 292b is referred to as a cell. The configurations of transistors 200a, 200b, capacitive device 292a, and 292b can be considered in the above-mentioned descriptions relating to transistors 200a, 200b, capacitive device 292a, and 292b.

[0463] Figure 23B is a cross-sectional view showing a semiconductor device 600 having transistors 200a and 200b, a capacitive device 292a, and a capacitive device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitive section.

[0464] As shown in Figure 23B, the conductor 294b, which functions as one electrode of the capacitive device 292b of semiconductor device 600, also serves as one electrode of the capacitive device of semiconductor device 601, which has a similar configuration to semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitive device 292a of semiconductor device 600, also serves as one electrode of the capacitive device of the semiconductor device adjacent to the left side of semiconductor device 600, i.e., in the A1 direction in Figure 23B. The same configuration applies to the cells on the right side of semiconductor device 601, i.e., in the A2 direction in Figure 23B. In other words, a cell array (also called a memory device layer) can be formed. By using such a cell array configuration, the spacing between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and enabling high integration. Furthermore, by arranging the cell array configuration shown in Figure 23B in a matrix, a matrix-shaped cell array can be formed.

[0465] As described above, by forming transistors 200a, 200b, capacitive devices 292a, and 292b with the configuration shown in this embodiment, the cell area can be reduced, and the semiconductor device having a cell array can be miniaturized or highly integrated.

[0466] Furthermore, the cell array may be configured not only in a planar manner but also in a stacked manner. Figure 24 shows a cross-sectional view of a configuration in which n layers of cell array 610 are stacked. As shown in Figure 24, by stacking multiple cell arrays (cell array 610_1 to cell array 610_n), cells can be accumulated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be constructed.

[0467] <Example of a memory device 3> Figure 25 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0468] Each of the memory device layers 415_1 to 415_4 has a plurality of memory devices 420.

[0469] The memory device 420 is electrically connected to the memory device 420 on a different memory device layer 415 and the transistor 200T on the transistor layer 413 via the conductors 424 and 205.

[0470] The memory unit 470 is sealed by insulators 212, 214, 282, and 283 (referred to as the sealing structure below for convenience). An insulator 285 is provided around insulator 283. In addition, a conductor 440 is provided on insulators 285, 283, and 212, electrically connecting them to the element layer 411.

[0471] Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 has the function of releasing oxygen upon heating. Alternatively, the insulator 280 has an excess oxygen region.

[0472] Furthermore, it is preferable that insulators 212 and 283 are materials that have a high barrier function against hydrogen. In addition, it is preferable that insulators 214 and 282 are materials that have the function of capturing or fixing hydrogen.

[0473] For example, materials that have a high barrier function against hydrogen include silicon nitride or silicon nitride oxide. Materials that have the function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0474] There are no particular limitations on the crystal structure of the materials used for insulators 212, 214, 282, and 283, but they may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferable as a material that has the function of capturing or fixing hydrogen. Amorphous aluminum oxide may capture and fix hydrogen in greater quantities than highly crystalline aluminum oxide.

[0475] Furthermore, it is preferable that insulators 282 and 214 be provided between the transistor layer 413 and the memory device layer 415, or between each memory device layer 415. It is also preferable that an insulator 296 be provided between insulators 282 and 214. The insulator 296 can be made of the same material as insulator 283. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material may be used.

[0476] Here, the excess oxygen in the insulator 280 can be considered in relation to the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280, as described below.

[0477] Hydrogen present in the oxide semiconductor diffuses to other structures via the insulator 280 in contact with the oxide semiconductor. This hydrogen diffusion causes excess oxygen in the insulator 280 to react with the hydrogen in the oxide semiconductor, forming OH bonds, which then diffuse through the insulator 280. When the hydrogen atoms with OH bonds reach a material that has the function of capturing or fixing hydrogen (typically the insulator 282), they react with oxygen atoms bonded to atoms in the insulator 282 (e.g., metal atoms), and are captured or fixed within the insulator 282. Meanwhile, the oxygen atoms of the excess oxygen that had OH bonds are presumed to remain in the insulator 280 as excess oxygen. In other words, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.

[0478] To satisfy the above model, the semiconductor device manufacturing process is one of the important factors.

[0479] As an example, an insulator 280 containing excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. After that, it is preferable to perform a heat treatment. Specifically, this heat treatment is carried out at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, a nitrogen atmosphere, or a mixed atmosphere of oxygen and nitrogen. The heat treatment time is 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more.

[0480] The above heat treatment allows hydrogen in the oxide semiconductor to diffuse outward through insulators 280 and 282. In other words, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0481] After the above heat treatment, an insulator 283 is formed. Since the insulator 283 is a material with high barrier properties against hydrogen, it can suppress hydrogen that has diffused outward or hydrogen present in the outside from entering the interior, specifically the oxide semiconductor or the insulator 280 side.

[0482] The above heat treatment is illustrated as being performed after the formation of the insulator 282, but is not limited to this. For example, the heat treatment may be performed after the formation of the transistor layer 413, or after the formation of memory device layers 415_1 to 415_3. When hydrogen is diffused outward by the heat treatment, it diffuses upward or sideways to the transistor layer 413. Similarly, when the heat treatment is performed after the formation of memory device layers 415_1 to 415_3, the hydrogen diffuses upward or sideways.

[0483] Furthermore, by following the above manufacturing process, the insulator 212 and the insulator 283 are bonded together, thereby forming the aforementioned sealing structure.

[0484] As described above, by using the above structure and manufacturing process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Therefore, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided.

[0485] The configurations and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments.

[0486] (Embodiment 3) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 26A, 26B and 27A to 27H. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.

[0487] <Example of storage device configuration> Figure 26A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0488] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0489] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The memory device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0490] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0491] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0492] Although Figure 26A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 26B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0493] Figures 27A to 27H illustrate an example of a memory cell configuration that can be applied to the memory cell MC described above.

[0494] [DOSRAM] Figures 27A to 27C show examples of the circuit configuration of a DRAM memory cell. In this specification, a DRAM using a 1OS transistor, 1 capacitance element type memory cell may be referred to as DOSRAM (registered trademark, Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 27A has a transistor M1 and a capacitance element CA. The transistor M1 has a gate (sometimes called a top gate) and a back gate.

[0495] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitive element CA is connected to wiring LL.

[0496] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring LL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, wiring LL may be at ground potential or low-level potential. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0497] Here, the memory cell 1471 shown in Figure 27A corresponds to the memory device shown in Figure 22. In other words, transistor M1 corresponds to transistor 200, and capacitive element CA corresponds to capacitive device 292.

[0498] Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of transistor M1 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1472 in Figure 27B. Alternatively, the memory cell MC may be a memory cell composed of a single-gate transistor, i.e., a transistor M1 without a back gate, as shown in memory cell 1473 in Figure 27C.

[0499] When the semiconductor device shown in the above embodiment is used as a memory cell 1471, etc., transistor 200 can be used as transistor M1 and capacitive element 100 can be used as capacitive element CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 1471, 1472, and 1473.

[0500] Furthermore, in DOSRAM, by configuring the sense amplifier to overlap the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity can be reduced.

[0501] [NOSRAM] Figures 27D to 27G show an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 1474 shown in Figure 27D has a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 has a top gate (sometimes simply called a gate) and a back gate. In this specification, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 may be called NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0502] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0503] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing and reading data, it is preferable to apply a high-level potential to wiring CAL. When holding data, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0504] Here, the memory cell 1474 shown in Figure 27D corresponds to the memory device shown in Figure 20. In other words, transistor M2 corresponds to transistor 200, capacitive element CB corresponds to capacitive element 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, wiring CAL corresponds to wiring 1005, wiring RBL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0505] Furthermore, the memory cell MC is not limited to memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of transistor M2 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1475 in Figure 27E. Alternatively, the memory cell MC may be configured such that the memory cell MC is composed of a single-gate transistor, i.e., a transistor M2 without a back gate, as shown in memory cell 1476 in Figure 27F. Furthermore, the memory cell MC may be configured such that wiring WBL and wiring RBL are combined into a single wiring BIL, as shown in memory cell 1477 in Figure 27G.

[0506] When the semiconductor device shown in the above embodiment is used as a memory cell 1474, etc., transistor 200 can be used as transistor M2, transistor 300 as transistor M3, and capacitive element 100 as capacitive element CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made very small. As a result, the written data can be held by transistor M2 for a long time, and the frequency of memory cell refresh can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0507] Furthermore, transistor M3 may be a transistor having silicon in its channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be n-channel or p-channel. Si transistors may have higher field-effect mobility than OS transistors. Therefore, a Si transistor may be used as transistor M3, which functions as a readout transistor. Also, by using a Si transistor for transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the occupied area of ​​the memory cell and enabling high integration of the memory device.

[0508] Furthermore, transistor M3 may be an OS transistor. When OS transistors are used for transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.

[0509] Figure 27H also shows an example of a gain cell type memory cell with 3 transistors and 1 capacitance element. The memory cell 1478 shown in Figure 27H has transistors M4 to M6 and a capacitance element CC. The capacitance element CC is provided as appropriate. The memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that provides a low level potential. Note that the memory cell 1478 may be electrically connected to wiring RBL and wiring WBL instead of wiring BIL.

[0510] Transistor M4 is an OS transistor with a back gate, and the back gate is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a back gate.

[0511] Note that transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively. Alternatively, transistors M4 through M6 may be OS transistors; in this case, the memory cell array 1470 can be configured using only n-type transistors.

[0512] When the semiconductor device shown in the above embodiment is used as a memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitive element 100 can be used as capacitive element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made very small.

[0513] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary.

[0514] Generally, various types of memory devices are used in semiconductor devices such as computers, depending on the application. One embodiment of the present invention is suitably used, for example, as memory integrated as registers in an arithmetic processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0515] Memory integrated as registers into arithmetic processing units such as CPUs is frequently accessed by the arithmetic processing unit because it is used for temporary storage of calculation results. Therefore, faster operating speed is required than storage capacity. Registers also have the function of holding configuration information for the arithmetic processing unit.

[0516] SRAM is used, for example, as a cache. A cache has the function of duplicating and storing some of the information held in main memory. By duplicating frequently used data in the cache, the speed of accessing that data can be increased.

[0517] DRAM is used, for example, in main memory. Main memory has the function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm². 2 That is the case.

[0518] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored long-term, as well as various programs used by the processing unit. Therefore, storage requires a large storage capacity and high recording density rather than just operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm². 2 That is the case.

[0519] A storage device according to one aspect of the present invention has a high operating speed and is capable of long-term data retention. The storage device according to one aspect of the present invention can be suitably used as a storage device located in a boundary region that includes both the layer where the cache is located and the layer where the main memory is located. Alternatively, the storage device according to one aspect of the present invention can be suitably used as a storage device located in a boundary region that includes both the layer where the main memory is located and the layer where the storage is located.

[0520] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0521] (Embodiment 4) In this embodiment, Figures 28A and 28B show an example of a chip 1200 on which the semiconductor device of the present invention is mounted. Multiple circuits (systems) are mounted on the chip 1200. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0522] As shown in Figure 28A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0523] The chip 1200 is provided with bumps (not shown) and connects to the first surface of the printed circuit board (PCB) 1201, as shown in Figure 28B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connect to the motherboard 1203.

[0524] The motherboard 1203 may be equipped with storage devices such as DRAM 1221 and flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222.

[0525] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The memory can be the aforementioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing or multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit or multiply-accumulate operation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0526] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed on the GPU 1212.

[0527] The analog arithmetic unit 1213 includes one or both an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit.

[0528] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0529] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface).

[0530] The network circuit 1216 has a function to control connections to LANs (Local Area Networks), etc. It may also have a circuit for network security.

[0531] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0532] A PCB 1201 equipped with a chip 1200 having a GPU 1212, a motherboard 1203 equipped with DRAM 1221, and flash memory 1222 can be called a GPU module 1204.

[0533] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module.

[0534] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0535] (Embodiment 5) This embodiment shows an example of an electronic component and electronic device incorporating the storage device and other components described in the above embodiment.

[0536] <Electronic Components> First, an example of an electronic component incorporating the memory device 720 will be explained using Figures 29A and 29B.

[0537] Figure 29A shows a perspective view of an electronic component 700 and a circuit board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 29A has a memory device 720 inside a mold 711. Figure 29A is partially omitted to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 by a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted board 704.

[0538] The storage device 720 includes a drive circuit layer 721 and a storage circuit layer 722.

[0539] Figure 29B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple storage devices 720 are provided on the interposer 731.

[0540] Electronic component 730 shows an example where the memory device 720 is used as high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

[0541] The package substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 can be a silicon interposer, a resin interposer, or the like.

[0542] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0543] It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0544] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0545] Furthermore, in SiP or MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0546] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the memory device 720 and the semiconductor device 735.

[0547] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 29B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0548] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0549] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0550] (Embodiment 6) This embodiment describes application examples of a storage device using the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment can be applied to storage devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 30A to 30E schematically show some configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0551] Figure 30A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1105, etc.

[0552] Figure 30B is a schematic diagram of the external appearance of an SD card, and Figure 30C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. The capacity of the SD card 1110 can be increased by also providing a memory chip 1114 on the back side of the circuit board 1113. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114, etc.

[0553] Figure 30D is a schematic diagram of the external appearance of the SSD, and Figure 30E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. Semiconductor devices as shown in the above embodiment can be incorporated into memory chips 1154, etc.

[0554] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0555] (Embodiment 7) A semiconductor device according to one aspect of the present invention can be used as a processor such as a CPU or GPU, or as a chip. Figures 31A to 31H show specific examples of electronic devices equipped with a processor such as a CPU or GPU, or as a chip according to one aspect of the present invention.

[0556] <Electronic Equipment and Systems> A GPU or chip according to one aspect of the present invention can be mounted in various electronic devices. Examples of electronic devices include, for example, electronic devices with relatively large screens such as television equipment, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, personal information terminals, and audio playback devices. By providing a semiconductor device according to one aspect of the present invention in these electronic devices, highly reliable electronic devices can be provided. Alternatively, by providing a GPU or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be mounted in the electronic device.

[0557] An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images or information. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0558] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0559] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on. Figures 31A to 31H show examples of electronic devices.

[0560] [Information terminal] Figure 31A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. For input interfaces, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0561] The information terminal 5100 can execute applications utilizing artificial intelligence by applying a chip according to one aspect of the present invention. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the content of those conversations on the display unit 5102, applications that recognize characters, figures, etc., entered by the user on the touch panel provided on the display unit 5102 and display them on the display unit 5102, and applications that perform biometric authentication such as fingerprints or voiceprints.

[0562] Figure 31B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a main unit 5201, a display unit 5202, and a keyboard 5203.

[0563] The notebook-type information terminal 5200, like the information terminal 5100 described above, can run applications utilizing artificial intelligence by applying a chip according to one embodiment of the present invention. Examples of applications utilizing artificial intelligence include design support software, document editing software, and automatic menu generation software. Furthermore, the notebook-type information terminal 5200 can be used to develop new artificial intelligence.

[0564] In the above, smartphones and notebook computers were used as examples of electronic devices, as illustrated in Figures 31A and 31B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0565] [Game console] Figure 31C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a casing 5301, a casing 5302, a casing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Casings 5302 and 5303 can be detached from casing 5301. By attaching the connection unit 5305 provided on casing 5301 to another casing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). In this case, casings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. The chips shown in the above embodiment can be incorporated into the chips provided on the circuit boards of casings 5301, casing 5302, and casing 5303.

[0566] Figure 31D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0567] By applying a GPU or chip according to one aspect of the present invention to game consoles such as the handheld game console 5300 and the home game console 5400, a low-power game console can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0568] Furthermore, by applying a GPU or chip according to one aspect of the present invention to the portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0569] Normally, the progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the game's program. However, by applying artificial intelligence to the 5300 handheld game console, it becomes possible to create expressions that are not limited to the game's program. For example, it becomes possible to express changes in the content of questions asked by the player, the game's progress, the time of day, and the behavior of characters appearing in the game.

[0570] Furthermore, when playing games that require multiple players on the 5300 handheld game console, artificial intelligence can be used to create anthropomorphic game players. By using AI-generated game players as opponents, it becomes possible to play the game even by a single player.

[0571] Figures 31C and 31D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the GPU or chip of one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the GPU or chip of one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0572] [Large computer] A GPU or chip according to one aspect of the present invention can be applied to a large computer.

[0573] Figure 31E shows the supercomputer 5500, an example of a large-scale computer. Figure 31F shows the rack-mount computer 5502, which is part of the supercomputer 5500.

[0574] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. In addition, each computer 5502 is provided with a plurality of circuit boards 5504, on which the GPU or chip described in the above embodiment can be mounted.

[0575] The Supercomputer 5500 is a large computer primarily used for scientific and technical computing. Scientific and technical computing requires high-speed processing of enormous calculations, resulting in high power consumption and significant heat generation from the chip. By applying a GPU or chip according to one aspect of the present invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, the reduced power consumption reduces heat generation from the circuit, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0576] Figures 31E and 31F illustrate a supercomputer as an example of a large computer, but the large computer to which the GPU or chip according to one aspect of the present invention is applied is not limited to this. Examples of large computers to which the GPU or chip according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0577] [Mobile] A GPU or chip according to one aspect of the present invention can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0578] Figure 31G shows the area around the windshield inside an automobile, which is an example of a moving object. In Figure 31G, display panels 5701, 5702, and 5703 mounted on the dashboard are shown, as well as a display panel 5704 mounted on the pillar.

[0579] Display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, and more. Furthermore, the display items and layout on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0580] The display panel 5704 can display images from an imaging device (not shown) installed in the vehicle, thereby compensating for the blind spots obstructed by the pillars. In other words, by displaying images from an imaging device installed on the outside of the vehicle, blind spots can be compensated for, thereby enhancing safety. Furthermore, by displaying images that compensate for unseen areas, safety checks can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0581] A GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, and for example, the chip can be used in an autonomous driving system for an automobile. The chip can also be used in systems that perform tasks such as road guidance and hazard prediction. Display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0582] Although automobiles are described above as an example of a mobile device, mobile devices are not limited to automobiles. For example, mobile devices can also include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and by applying a chip according to one aspect of the present invention to these mobile devices, a system utilizing artificial intelligence can be provided.

[0583] [electric appliances] Figure 31H shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0584] By applying a chip according to one aspect of the present invention to an electric refrigerator 5800, an electric refrigerator 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5800 can have a function to automatically generate menus based on the ingredients stored in the electric refrigerator 5800 and their expiration dates, or a function to automatically adjust the temperature to suit the ingredients stored in the electric refrigerator 5800.

[0585] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0586] The electronic devices described in this embodiment, their functions, examples of artificial intelligence applications, and their effects can be appropriately combined with descriptions of other electronic devices.

[0587] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0588] BGL: Wiring, BIL: Wiring, CA: Capacitive element, CB: Capacitive element, CC: Capacitive element, CAL: Wiring, GNDL: Wiring, LL: Wiring, MC: Memory cell, M1: Transistor, M2: Transistor, M3: Transistor, M4: Transistor, M5: Transistor, M6: Transistor, RBL: Wiring, RWL: Wiring, SL: Wiring, WBL: Wiring, WOL: Wiring, WWL: Wiring, 20: Stress, 20a: Stress, 20b: Stress, 30a: Strain, 30b: Strain, 30c: Strain, 100: Capacitive element, 110: Conductor, 112: Conductor, 115: Conductor, 120: Conductor, 12 5: Conductor, 130: Insulator, 140: Conductor, 142: Insulator, 145: Insulator, 150: Insulator, 152: Insulator, 153: Conductor, 154: Insulator, 156: Insulator, 200: Transistor, 200_n: Transistor, 200_1: Transistor, 200a: Transistor, 200b: Transistor, 200T: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 217: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 224A: insulating film, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230ba: region, 230bb: region, 230bc: region, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 242c: conductor, 243: oxide, 243a: oxide, 243A: oxide film, 243b: oxide, 243B: oxide layer, 243c: oxide, 246: conductor, 246 a: conductor, 246b: conductor, 250: insulator, 250a: insulator, 250A: insulating film, 250b: insulator, 260: conductor, 260a: conductor, 260b: conductor, 265: sealing part, 265a: sealing part, 265b: sealing part, 271: insulator, 271a: insulator, 271A: insulating film, 271b: insulator, 271B: insulating layer, 271c: insulator, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 285: insulator, 290: memory device, 292: capacitive device, 292a: capacitive device, 292b: capacitive device, 294: conductor,294a: Conductor, 294b: Conductor, 296: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 411: Element layer, 413: Transistor layer, 415: Memory device layer, 415_1: Memory device layer, 415_3: Memory device layer, 415_4: Memory device Layer, 420: Memory device, 424: Conductor, 440: Conductor, 470: Memory unit, 600: Semiconductor, 601: Semiconductor, 610: Cell array, 610_n: Cell array, 610_1: Cell array, 700: Electronic component, 702: Printed circuit board, 704: Mounting board, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 720: Memory device, 721: Drive circuit layer, 722: Memory circuit layer, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor, 1001: Wiring, 1 002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1100: USB memory, 1101: Enclosure, 1102: Cap, 1103: USB connector, 1104: Circuit board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Enclosure, 1112: Connector, 1113: Circuit board, 1114: Memory chip, 1115: Contr...

Claims

1. A memory device having transistors, Oxide semiconductor film and The source electrode and drain electrode on the oxide semiconductor film, A first insulating film having a region in contact with the upper surface of the source electrode and a region in contact with the upper surface of the drain electrode, A second insulating film having a region in contact with the upper surface of the first insulating film, An interlayer insulating film provided on the second insulating film and having a region covering the oxide semiconductor film, the source electrode, the drain electrode, the first insulating film, and the second insulating film, The gate electrode has a region located on the oxide semiconductor film, The first insulating film has an amorphous metal oxide and does not have a side surface of the source electrode, a region in contact with the side surface of the drain electrode, or a region in contact with the side surface of the oxide semiconductor film. The second insulating film has aluminum oxide or silicon nitride and has a side surface of the source electrode, a region in contact with the side surface of the drain electrode, and a region in contact with the side surface of the oxide semiconductor film. The first insulating film, the second insulating film, and the interlayer insulating film are superimposed in the region between the source electrode and the drain electrode and have an opening. The gate electrode is positioned within the opening of the interlayer insulating film. A memory device in which each of the source electrode and the drain electrode is made of tantalum nitride.

2. A memory device having transistors, Oxide semiconductor film and The source electrode and drain electrode on the oxide semiconductor film, A first insulating film having a region in contact with the upper surface of the source electrode and a region in contact with the upper surface of the drain electrode, A second insulating film having a region in contact with the upper surface of the first insulating film, An interlayer insulating film provided on the second insulating film and having a region covering the oxide semiconductor film, the source electrode, the drain electrode, the first insulating film, and the second insulating film, The gate insulating film on the oxide semiconductor film, The gate electrode on the gate insulating film, The first insulating film has an amorphous metal oxide and does not have a side surface of the source electrode, a region in contact with the side surface of the drain electrode, or a region in contact with the side surface of the oxide semiconductor film. The second insulating film has aluminum oxide or silicon nitride and has a side surface of the source electrode, a region in contact with the side surface of the drain electrode, and a region in contact with the side surface of the oxide semiconductor film. The first insulating film, the second insulating film, and the interlayer insulating film are superimposed in the region between the source electrode and the drain electrode and have an opening. The gate insulating film and the gate electrode are arranged within the opening of the interlayer insulating film. Each of the source electrode and the drain electrode has tantalum nitride. The oxide semiconductor film has a first region superimposed on the source electrode or the drain electrode, and a second region superimposed on the gate electrode. A memory device in which the density of the first region is less than the density of the second region.

3. In Claim 2, The first region is a memory device in which the hydrogen concentration is greater than that of the second region.

4. In claim 2 or 3, A memory device in which the film thickness of the second region is smaller than the film thickness of the first region.

5. In any one of claims 1 to 4, A memory device wherein the oxide semiconductor film has one or more selected from In, Ga, or Zn.

6. In any one of claims 1 to 5, The oxide semiconductor film has In, M, and Zn (where element M is one or more selected from Al, Ga, Y, Sn, and Ti), and has a layered crystalline structure, and is a memory device.

7. In any one of claims 1 to 6, Below the oxide semiconductor film, there is a third insulating film, a fourth insulating film, a first conductor, and a second conductor. The third insulating film has an opening at a position superimposed on the gate electrode, The fourth insulating film has a region in contact with the upper surface of the third insulating film, The first conductor and the second conductor are provided within the opening of the third insulating film. The first conductor has a region in contact with the inner wall of the opening of the third insulating film, a region in contact with the side surface of the second conductor, and a region in contact with the lower surface of the second conductor. A memory device wherein the oxide semiconductor film has a region that overlaps with the first conductor and the second conductor via the fourth insulating film.

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