Energy storage device

Abstract

To suppress a failure of an FET due to heat generated by a parasitic diode.SOLUTION: A power storage device 50 includes: a cell 60; a relay 53 for cutting off current of the cell 60; a bypass circuit 120 connected to the relay 53 in parallel; and a management device 150. The bypass circuit 120 includes two FETs 121 and 123 which are back-to-back connected. When abnormality of the cell 60 is detected, the management device 150 OPENs the relay 53, CLOSEs one of the two FETs 121 and 123, OPENS the other, and allows discharge or charge of the cell 60 in a route passing a parasitic diode of the FET. If current of the FETs 121 and 123 and conduction time T reach a prescribed condition or a temperature of the FETs 121 and 123 reaches the prescribed condition during discharge or charge in the route passing the parasitic diode, the management device 150 CLOSEs the relay 53 and the other of the FETs 121 and 123 which is OPENed.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a technology for protecting FETs.

Background Art

[0002] A relay is one type of battery protection device. When an abnormality such as over-discharge or over-charge is detected, the relay is opened to interrupt the current, whereby the battery can be protected. Patent Document 1 below discloses that a bypass circuit is provided in parallel with the relay. The bypass circuit is composed of two FETs connected back-to-back.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of Invention

Problems to be Solved by the Invention

[0004] It is conceivable to control charging and discharging while the relay is open using the bypass circuit. Specifically, the parasitic diodes of the first FET and the second FET connected back-to-back are oriented in opposite directions, with the direction of the parasitic diode of the first FET set as the charging direction, and the direction of the parasitic diode of the second FET set as the discharging direction.

[0005] In this case, when the first FET is closed and the second FET is opened while the relay is open, only discharging is possible via the path passing through the parasitic diode of the second FET.

[0006] Therefore, for example, when over-charge is detected, by opening the relay, closing the first FET, and opening the second FET, charging is restricted, and only discharging is enabled via the path passing through the parasitic diode of the second FET.

[0007] However, since parasitic diodes generate heat when current flows through them, if a current exceeding the allowable limit flows through the parasitic diode for a specified period of time or longer, there was a possibility that the FET would fail.

[0008] Furthermore, in the case of over-discharge, by opening the relay, opening the first FET, and closing the second FET, it is possible to restrict discharge while only charging occurs through the parasitic diode of the first FET; however, the same problem existed in this case as well.

[0009] The objective of this invention is to suppress FET failure caused by heat generation from parasitic diodes. [Means for solving the problem]

[0010] The energy storage device includes a cell, a relay for interrupting the current to the cell, a bypass circuit connected in parallel to the relay, and a control device. The bypass circuit includes two FETs connected back-to-back.

[0011] When the control device detects an abnormality in the cell, it opens the relay, closes one of the two FETs, and opens the other, thereby enabling the cell to discharge or charge through the path passing through the parasitic diode of the FET.

[0012] The control device closes the relay and the other open FET when the current I and energizing time T of the FET reach predetermined conditions, or when the temperature of the FET reaches predetermined conditions, while the FET is being discharged or charged through the path passing through the parasitic diode.

[0013] When the control device is discharging or charging through the path passing through the parasitic diode, if the current I and energizing time T of the FET reach predetermined conditions, or if the temperature of the FET reaches predetermined conditions, the relay is kept open and the other open FET is closed. [Effects of the Invention]

[0014] The present technology can suppress failures of FETs caused by heat generation of parasitic diodes. Brief Description of the Drawings

[0015] [Figure 1] Side view of an automobile [Figure 2] Exploded perspective view of a battery [Figure 3] Plan view of a cell [Figure 4] Cross-sectional view taken along line A-A in Figure 3 [Figure 5] Block diagram showing the electrical configuration of a battery [Figure 6] I-T characteristic [Figure 7] Diagram showing the current path of a battery [Figure 8] Diagram showing the current path of a battery [Figure 9] I-T characteristic [Figure 10] Flowchart of FET protection processing [Figure 11] Flowchart of FET protection processing [Figure 12] Diagram showing the current path of a battery [Figure 13] Diagram showing the current path of a battery [Figure 14] Flowchart of FET protection processing [Figure 15] Block diagram showing the electrical configuration of a battery [Figure 16] Block diagram showing the electrical configuration of a battery Modes for Carrying Out the Invention

[0016] An outline of the power storage device will be described. (1) A power storage device according to an embodiment of the present invention includes a cell, a relay that interrupts current of the cell, a bypass circuit connected in parallel to the relay, and a management device. The bypass circuit includes two FETs connected back-to-back.

[0017] When the control device detects an abnormality in the cell, it opens the relay, closes one of the two FETs, and opens the other, thereby enabling the cell to discharge or charge through the path passing through the parasitic diode of the FET.

[0018] The control device closes the relay and the other open FET when the current I and energizing time T of the FET reach predetermined conditions, or when the temperature of the FET reaches predetermined conditions, while the FET is being discharged or charged through the path passing through the parasitic diode.

[0019] The energy storage device described in (1) above has the following effects. Assume that while the relay is open, one of the FETs is opened, and the cell is discharged or charged through the path passing through the parasitic diode of the open FET. In this case, if there is a risk of FET failure due to heat generation from the parasitic diode, closing the relay and the open FET simultaneously will cause the FET, which has no contacts, to close faster than the relay, which has contacts. Closing the FET increases the current that can be carried through the bypass circuit compared to before closing, thus suppressing heat generation in the FET and preventing FET failure. After the FET closes, the relay contacts close with a delay, but after the relay contacts close, the current that can be carried increases further, and most of the current flows through the relay, thus further suppressing FET failure.

[0020] (2) An energy storage device according to one embodiment of the present invention includes a cell, a relay for interrupting the current of the cell, a bypass circuit connected in parallel to the relay, and a control device. The bypass circuit includes two FETs connected back-to-back.

[0021] When the control device detects an abnormality in the cell, it opens the relay, closes one of the two FETs, and opens the other, thereby enabling the cell to discharge or charge through the path passing through the parasitic diode of the FET.

[0022] When the control device is discharging or charging through the path passing through the parasitic diode, if the current I and energizing time T of the FET reach predetermined conditions, or if the temperature of the FET reaches predetermined conditions, the relay is kept open and the other open FET is closed.

[0023] The energy storage device described in (2) above has the following effects. When the relay is open, one of the FETs is opened, and the cell is discharged or charged through the path passing through the parasitic diode of the open FET. In this case, if there is a risk of FET failure due to heat generation from the parasitic diode, closing the open FET increases the current that can be carried through the bypass circuit compared to before the FET was closed. By increasing the current that can be carried, heat generation of the FET can be suppressed, and FET failure can be suppressed. In addition, since the relay is kept open, there is no clicking noise associated with opening and closing contacts. Therefore, by applying this technology to an energy storage device installed in a car, for example, it can be expected to be effective in reducing unpleasant noise while riding.

[0024] (3) In the energy storage device described in (1) or (2) above, the abnormality of the cell may be due to overcharging or over-discharging. This configuration allows for protection against FET failure while protecting the cell from overcharging and over-discharging.

[0025] (4) In any of the energy storage devices described in (1) to (3) above, the energy storage device may also be used for engine starting. Since an energy storage device for engine starting discharges a large current, if cranking is performed with the relay controlled to OPEN, a large current flows through the parasitic diode of the bypass circuit, and there is a high possibility that the FET will fail. In particular, during overcharging, the cell voltage is high and the cranking current tends to be large, so there is a high possibility that the FET will fail. By applying this technology to an energy storage device for engine starting that discharges a large current, it is possible to supply cranking current while suppressing FET failure even when the energy storage device is in an overcharged state.

[0026] In the case of over-discharge, the cell voltage tends to be low and the current low. By turning on the two FETs, the resistance of the bypass circuit can be reduced, which suppresses the voltage drop in the energy storage device. Therefore, cranking problems caused by voltage drop and insufficient current can be suppressed.

[0027] <Embodiment 1> 1. Battery 50 Description As shown in Figure 1, the automobile 10 is equipped with an engine 20 and a battery 50 used for starting the engine 20, etc. The battery 50 is an example of an "energy storage device". The automobile 10 may also be equipped with an energy storage device for vehicle propulsion or a fuel cell.

[0028] As shown in Figure 2, the battery 50 comprises a battery pack 60, a circuit board unit 65, and a housing 71. The housing 71 comprises a main body 73 and a lid 74 made of synthetic resin material. The main body 73 is a bottomed cylindrical shape and comprises a bottom portion 75 and four side portions 76. The four side portions 76 form an opening 77 at the upper end of the main body 73.

[0029] The housing 71 houses the battery pack 60 and the circuit board unit 65. The circuit board unit 65 is a board unit on which various components (relay 53, bypass circuit 120 shown in Figure 5, and control device 150, etc.) are mounted on the circuit board 100, and is positioned adjacent to the battery pack 60, for example, above it, as shown in Figure 2. Alternatively, the circuit board unit 65 may be positioned adjacent to the side of the battery pack 60.

[0030] The cover 74 closes the opening 77 of the main body 73. An outer peripheral wall 78 is provided around the cover 74. The cover 74 has a projection 79 that is roughly T-shaped in plan view. A positive external terminal 51 is fixed to one corner of the front of the cover 74, and a negative external terminal 52 is fixed to the other corner. The circuit board unit 65 may be housed inside the cover 74 (for example, inside the projection 79) instead of the main body 73 of the housing 71.

[0031] The battery pack 60 is composed of multiple cells 62. As shown in Figure 4, each cell 62 houses an electrode body 83 together with a non-aqueous electrolyte within a rectangular parallelepiped (prismatic) case 82. The cell 62 is, for example, a lithium-ion secondary battery cell. The case 82 has a case body 84 and a lid 85 that closes the opening at its top.

[0032] The electrode body 83, although not shown in detail, consists of a negative electrode plate made of a copper foil substrate coated with an active material and a positive electrode plate made of an aluminum foil substrate coated with an active material, with a separator made of a porous resin film placed between them. Both are in the shape of a strip, and are wound flat so that they can be housed in the case body 84, with the negative electrode plate and positive electrode plate offset to opposite sides in the width direction relative to the separator. The electrode body 83 may be of a laminated type instead of the wound type.

[0033] A positive electrode terminal 87 is connected to the positive electrode plate via a positive electrode current collector 86, and a negative electrode terminal 89 is connected to the negative electrode plate via a negative electrode current collector 88. The positive electrode current collector 86 and the negative electrode current collector 88 each have a flat base portion 90 and legs 91 extending from the base portion 90. Through holes are formed in the base portion 90. The legs 91 are connected to the positive electrode plate or the negative electrode plate.

[0034] The positive terminal 87 and the negative terminal 89 each consist of a terminal body 92 and a shaft 93 that protrudes downward from the center of its lower surface. The terminal body 92 and shaft 93 of the positive terminal 87 are integrally molded from aluminum (a single material). In the negative terminal 89, the terminal body 92 is made of aluminum and the shaft 93 is made of copper, and these are assembled together. The terminal body 92 of the positive terminal 87 and the negative terminal 89 are positioned at both ends of the cover 85 via gaskets 94 made of insulating material, and are exposed to the outside from these gaskets 94, as shown in Figure 3.

[0035] The cover 85 has a pressure relief valve 95. The pressure relief valve 95 is located between the positive terminal 87 and the negative terminal 89. The pressure relief valve 95 is a safety valve. The pressure relief valve 95 opens when the internal pressure of the case 82 exceeds a limit, thereby reducing the internal pressure of the case 82.

[0036] Figure 5 is a block diagram showing the electrical configuration of the battery 50. The battery 50 comprises a battery pack 60, a relay 53, a voltage detection unit 54, a current sensor 55, a temperature sensor 58, a bypass circuit 120, and a control device 150.

[0037] The battery 50 is electrically connected to the engine starting device 160, the auxiliary electrical loads 170 and other electrical components, and the vehicle generator 180.

[0038] When the engine 20 is running, if the amount of power generated by the vehicle generator 180 is greater than the power consumption of the electrical load 170, the battery 50 is charged by the vehicle generator 180. If the amount of power generated by the vehicle generator 180 is less than the power consumption of the electrical load 170, the battery 50 is discharged to compensate for the deficit.

[0039] While the engine 20 is stopped, the vehicle generator 180 stops generating power. While power generation is stopped, the battery 50 is not charged and only discharges to the electrical load 170.

[0040] The battery pack 60 has, for example, 12 cells 62 (see Figure 2), connected in 3 parallel and 4 series. Figure 5 shows three cells 62 connected in parallel represented by a single battery symbol. The cells are not limited to prismatic cells; they may be cylindrical cells or pouch cells with a laminated film case.

[0041] The battery pack 60, relay 53, and current sensor 55 are connected in series via power lines 57P and 57N. Power lines 57P and 55N can be busbars BSB (see Figure 2), which are plate-shaped conductors made of metal materials such as copper.

[0042] As shown in Figure 5, power line 57P connects the positive external terminal 51 to the positive terminal of the battery pack 60. Power line 57N connects the negative external terminal 52 to the negative terminal of the battery pack 60.

[0043] External terminals 51 and 52 are terminals for connecting the battery 50 to the automobile 10 (engine starter 160, electrical load 170, and vehicle generator 180). The battery 50 can be electrically connected to the engine starter 160, electrical load 170, and vehicle generator 180 via external terminals 51 and 52.

[0044] The current sensor 55 is located on the negative power line 57N. The current sensor 55 may also be a metal plate resistor (shunt resistor). The current sensor 55 measures the current I of the battery pack 60 based on the voltage Vr across the resistor. The current sensor 55 can distinguish between discharge and charge based on the polarity (positive or negative) of the voltage Vr across its terminals.

[0045] The voltage detection unit 54 measures the cell voltage Vs of each cell 62 and the total voltage Vt of the battery pack 60. The temperature sensor 58 is attached to the battery pack 60 and detects the temperature of the battery pack 60 or its surroundings.

[0046] Relay 53 is provided on the positive power line 57P. Relay 53 is preferably a self-holding switch such as a latching relay. This embodiment uses a latching relay.

[0047] Relay 53 is a normally closed type and is controlled to be closed under normal circumstances. If there is any abnormality in battery 50, the relay 53 can be switched from closed to open, thereby interrupting the current I of the battery pack 60.

[0048] The bypass circuit 120 includes a first FET 121 and a second FET 123. In this embodiment, P-channel transistors are used for the first FET 121 and the second FET 123. FETs are field-effect transistors.

[0049] As shown in Figure 5, the first FET 121 has its source S connected to one end (point A) of the relay 53, and the second FET 123 has its source S connected to the other end (point B) of the relay 53.

[0050] The first FET121 and the second FET123 are connected via their drains, forming a back-to-back connection. A back-to-back connection is when the drains of two FETs are connected to each other, or the sources are connected to each other.

[0051] The first FET 121 has a parasitic diode D1, and the second FET 123 has a parasitic diode D2. Parasitic diode D1 has a forward charging direction, while parasitic diode D2 has a forward discharging direction; they are oriented in opposite directions.

[0052] The gate G of the first FET 121 and the gate G of the second FET 123 are connected to the control device 150 via signal lines L1 and L2. The control device 150 can individually control FETs 121 and 123 by sending control signals to each FET 121 and 123 via signal lines L1 and L2.

[0053] The bypass circuit 120 is connected in parallel with the relay 53. When the relay is open, the first FET 121 is closed and the second FET 123 is opened, allowing the battery pack 60 to discharge to the automobile 10 via the bypass circuit 120 (the source-drain path of the first FET 121 and the parasitic diode D2 of the second FET 123: see Figure 8). In this case, charging is blocked by the parasitic diode D2.

[0054] While the relay is open, the battery pack 60 can be charged by opening the first FET 121 and closing the second FET 123, via the bypass circuit 120 (the path through the source-drain of the second FET 123 and the parasitic diode D1 of the first FET: see Figure 13). In this case, discharge is prevented by the parasitic diode D1.

[0055] The management device 150 is mounted on the circuit board 100 (see Figure 2) and includes a CPU 151, memory 153, and timing unit 155, as shown in Figure 5.

[0056] The control device 150 monitors the status of the battery 50 based on the outputs of the voltage detection unit 54, the current sensor 55, and the temperature sensor 58. In other words, it monitors the temperature, current I, and total voltage Vt of the battery pack 60.

[0057] Memory 153 stores a battery monitoring program, an FET protection processing execution program, and data necessary for the execution of these programs. The programs may be stored on a recording medium such as a CD-ROM for use, transfer, or lending. The programs may also be distributed via telecommunications lines.

[0058] The timing unit 155 is used to measure the energizing time of the first FET 121 and the second FET 123.

[0059] 2. IT characteristics of FETs As shown in Figure 6, F1 is the IT characteristic of the FET, with the horizontal axis representing the energizing time T and the vertical axis representing the current I. Specifically, it is the IT characteristic of the FET when the second FET 123 is open and current is passed through the parasitic diode D2.

[0060] The area below F1 is the safe operating region where the second FET123 operates safely. In the area above F1, the second FET123 may fail due to heat generated by the parasitic diode D2.

[0061] For example, if the current value is 100A, the second FET123 will operate safely within the safe operating range if it is less than 30ms, but if it exceeds 30ms, it will be outside the safe operating range and may fail. The IT characteristics of the first FET121 are the same as those of the second FET123.

[0062] 3. Overcharge protection and parasitic diode overheating As shown in Figure 7, under normal conditions, relay 53, the first FET 121, and the second FET 123 are all controlled to the CLOSE position. The contact resistance of relay 53 is smaller than the on-resistance of the first FET 121 and the second FET 123, so most of the current I passes through relay 53. The total voltage Vt of the battery pack 60 increases with charging and decreases with discharging.

[0063] If the total voltage Vt of the battery pack 60 exceeds the upper limit during charging, the control device 150 determines that it is overcharging and switches the relay 53 from CLOSE to OPEN. In addition, the first FET 121 remains CLOSE and the second FET 123 switches from CLOSE to OPEN.

[0064] By closing the first FET 121 and opening the second FET 123, as shown in Figure 8, discharge is possible even after overcharge detection through the source-drain of the first FET 121 and the parasitic diode D2 of the second FET 123.

[0065] If a large discharge current flows through parasitic diode D2 and exceeds the safe operating range of the IT characteristics, the second FET 123 may fail due to the heat generated by parasitic diode D2.

[0066] To prevent failure of the second FET 123, one option is to close the relay 53 to reduce the current to the second FET 123.

[0067] However, since relay 53 is a mechanical contact 53A, it has a long operating time, and it takes time to switch contact 53A after a command is sent from the control device 150. Therefore, if a relatively large current is discharged into parasitic diode D2, there is a possibility that the second FET 123 may fail before contact 53A closes.

[0068] In this embodiment, after detecting an overcurrent, if there is a possibility of a failure of the second FET 123 while it is discharging through the parasitic diode D2, the control device 150 sends a command to the relay 53 to switch from OPEN to CLOSE, and at the same time sends a command to the second FET 123 to switch from OPEN to CLOSE.

[0069] Since the second FET 123 is a semiconductor switch, its operating time is shorter than that of the mechanical switch relay 53. Operating time is the time from when a command is sent to the switch until the state of the switch actually changes.

[0070] When commands are sent simultaneously to relay 53 and the second FET 123, the second FET 123 closes in tens of n seconds, and then, with a delay, the relay contacts close.

[0071] Since the allowable current between the drain and source of the second FET 123 is greater than the allowable current of the parasitic diode D2, the current that can be carried by the bypass circuit 120 can be increased for several tens of milliseconds after the second FET 123 closes until the contact 53A of the relay 53 closes. Therefore, failure of the second FET 123 due to heat generation can be suppressed.

[0072] Figure 9 shows F0 to F3, which represent the current-to-energy (IT) characteristics, with the horizontal axis representing the energizing time T and the vertical axis representing the current I. Specifically, F1 is the IT characteristic when relay 53 is OPEN, the first FET 121 is CLOSE, the second FET 123 is OPEN, and current is flowing through the parasitic diode D2. F2 is the IT characteristic when relay 53 is OPEN, the first FET 121 and second FET 123 are CLOSE, and current is flowing between the source and drain of the first FET 121 and second FET 123. F3 is the IT characteristic when relay 53 is CLOSE, the first FET 121 and second FET 123 are CLOSE, and current is flowing between the contacts of relay 53.

[0073] The safe operating range widens in the order of F3, F2, and F1, and the allowable current is highest for relay 53, then the source-drain of the second FET 123, and then the parasitic diode D2 of the second FET 123. Specifically, when T=100ms, the allowable current for relay 53 is approximately 2000A, the allowable current for the drain-source of the second FET 123 is 150A, and the allowable current for the parasitic diode of the second FET 123 is approximately 30A.

[0074] F0 is an IT determination line that switches relay 53 and the second FET 123 from OPEN to CLOSE to protect the FET.

[0075] Figure 10 is a flowchart of the FET protection process. The FET protection process is executed when, after the relay 53 is shut off due to overcharge detection, only discharge is allowed (charging is restricted) through the path passing through the parasitic diode D2 of the second FET 123, as shown in Figure 8.

[0076] At the start of the FET protection process, relay 53 is OPEN, the first FET 121 is CLOSE, and the second FET 123 is OPEN (see Figure 8).

[0077] The FET protection process consists of four steps, S10 to S40. In S10, the control device 150 determines the IT condition of the second FET 123. Specifically, it compares the operating point P, which is determined by the current I and energizing time T of the second FET 123, with the IT determination line F0 shown in Figure 9, and determines whether the operating point P of the second FET 123 is below the IT determination line F0. The IT condition is an example of a predetermined condition of the present invention.

[0078] If the operating point P of the second FET 123 is below the IT determination line F0, the control device 150 maintains the first FET 121 in the CLOSE state and the second FET 123 in the OPEN state.

[0079] If the operating point P of the second FET 123 moves above the IT determination line F0, the process transitions to S20, and the control device 150 simultaneously sends switching signals from OPEN to CLOSE to the relay 53 and the second FET 123.

[0080] Since the operating time of the FET is shorter than the operating time of relay 53, the second FET 123 closes first (S30). The allowable current between the drain and source of the second FET 123 is greater than the allowable current of the parasitic diode D2. For example, when T = 100 m sec, the allowable current between the drain and source is approximately 150 A, and the allowable current of the parasitic diode D2 of the second FET 123 is approximately 30 A.

[0081] Therefore, after the second FET 123 closes, the current that can be carried by the bypass circuit 120 can be increased. Consequently, failure of the second FET 123 due to heat generation can be suppressed.

[0082] After the second FET 123 closes, relay 53 closes with a delay (S40). Once relay 53 closes, most of the discharge current flows to relay 53, so the current in the bypass circuit 120 decreases, and the heat generation of the second FET 123 is further suppressed.

[0083] <Embodiment 2> Figure 11 is a flowchart of the FET protection process in Embodiment 2. Similar to Embodiment 1, the FET protection process is executed when, after the relay 53 is shut off in response to overcharge detection, the first FET 121 is controlled to CLOSE and the second FET 123 to OPEN, as shown in Figure 8, and only discharge is allowed (charging is restricted) through the path passing through the parasitic diode D2 of the second FET 123.

[0084] Similar to Embodiment 1, the control device 150 opens the relay 53 upon detection of overcharge, and then determines whether the operating point P of the bypass circuit 120 is below the IT determination line F0 (S10).

[0085] If the operating point P of the second FET 123 exceeds the IT determination line F0 (S10: YES), the control device 150 does not send a switching signal to the relay 53, but sends a switching signal from OPEN to CLOSE only to the second FET 123 (S23).

[0086] As shown in Figure 12, the second FET 123 switches from OPEN to CLOSE in response to the switching signal (S33), and the relay 53 remains OPEN (S43).

[0087] The allowable current of the drain-source of the second FET123 is greater than the allowable current of the parasitic diode D2. For example, when T=100ms, the allowable current of the drain-source is approximately 150A, while the allowable current of the parasitic diode D2 of the second FET123 is approximately 30A.

[0088] By closing the second FET123 and increasing the allowable current, the failure of the second FET123 can be suppressed compared to the case where current continues to flow through the parasitic diode D2.

[0089] If the control device 150 detects charging after the second FET 123 has closed (from S33 onwards), it can interrupt the charging by switching the second FET 123 from closed to open.

[0090] In Embodiment 2, since the FET protection process is performed only by the second FET 123, the number of times the relay 53 operates can be reduced compared to Embodiment 1, in which the FET protection process is performed using both the second FET 123 and the relay 53. Reducing the number of times the relay 53 operates can be expected to be effective in reducing unpleasant noises while riding.

[0091] <Embodiment 3> In Embodiment 1, when overcharging is detected, relay 53 is opened, the first FET 121 is closed, and the second FET 123 is opened, allowing discharge only through the bypass circuit 120 (parasitic diode D2), as shown in Figure 8.

[0092] If over-discharge is detected (when the total voltage Vt of the battery pack 60 falls below the lower limit voltage), the relay 53 may be opened, the first FET 121 may be opened, and the second FET 123 may be closed, allowing charging only through the bypass circuit 120 (parasitic diode D1), as shown in Figure 13.

[0093] If a large charging current flows through the parasitic diode D1 and exceeds the safe operating range of the IT characteristics, the first FET 121 may fail due to overheating of the parasitic diode D1.

[0094] Figure 14 is a flowchart of the FET protection process. The FET protection process is executed when, after the relay 53 is shut off due to over-discharge detection, the relay 53 is opened, the first FET 121 is opened, and the second FET 123 is closed, as shown in Figure 13, and charging is permitted only (discharging is restricted) through the path passing through the parasitic diode D1 of the first FET 121.

[0095] After detecting an overcharge, the control device 150 opens the relay 53 and then determines whether the operating point P of the first FET 121 is below the IT determination line F0 shown in Figure 9 (S10).

[0096] If the operating point P of the first FET 121 exceeds the IT determination line F0, the control device 150 sends a switching signal to the relay 53 and the first FET 121 (S25).

[0097] Since the operating time of the FET is shorter than the operating time of the relay 53, the first FET 121 closes first (S35). The allowable current between the drain and source of the first FET 121 is greater than the allowable current of the parasitic diode D2. Therefore, after the first FET 121 closes, the current that can be supplied to the bypass circuit 120 can be increased. Consequently, failure of the first FET 121 due to heat generation can be suppressed.

[0098] After the first FET 121 closes, relay 53 closes with a delay (S45). Once relay 53 closes, most of the discharge current flows to relay 53, so the current in the bypass circuit 120 decreases, and the heat generation of the first FET 121 is further suppressed.

[0099] <Embodiment 4> The control device 150 may use the bypass circuit 120 to detect a fault in the relay 53. Fault detection may also be performed during periods when the battery 50 is not in use, such as when the vehicle is parked.

[0100] The following describes the fault detection process. After switching the contact 53A of relay 53 from CLOSE to OPEN, the first FET 121 is closed and the second FET 123 is opened, and the control device 150 detects the voltage at point B shown in Figure 5.

[0101] When relay 53 is operating normally (contact 53A is OPEN), the voltage at point B will be lower than the voltage at the positive terminal of battery pack 60 (voltage at point A) by the amount of the voltage drop across parasitic diode D2.

[0102] If there is a problem with relay 53 (contact 53A is not OPEN), the voltage at point B will be at the same potential as the voltage at the positive terminal of battery pack 60 (voltage at point A). Therefore, a closed fault (a fault where the relay is stuck in the closed position and cannot be opened) of relay 53 can be detected based on the voltage at point B.

[0103] If it is confirmed that relay 53 opens normally, relay 53 is closed and the control device 150 detects the voltage at point B.

[0104] When relay 53 is functioning correctly (contact 53A is closed), the voltage at point B will be at the same potential as the voltage at the positive terminal of battery pack 60 (voltage at point A).

[0105] If there is a problem with relay 53 (contact 53A is not closed), the voltage at point B will be lower than the voltage at the positive terminal of battery pack 60 (voltage at point A) by the amount of the voltage drop across parasitic diode D2. Therefore, based on the voltage at point B, an open fault (a fault where the relay is stuck open and does not close) of relay 53 can be detected.

[0106] In this way, the relay 53 can be diagnosed for failure using the bypass circuit 120. Since the failure diagnosis of the relay 53 is performed using the bypass circuit 120, if the bypass circuit 120 is faulty or potentially faulty, the failure diagnosis may be avoided.

[0107] A possible failure in the bypass circuit 120 would occur, for example, when the FET protection operation is performed due to overheating of parasitic diodes D1 and D2.

[0108] <Embodiment 5> Figure 15 is a block diagram of the battery 200. The battery 200 differs from the battery 50 of Embodiment 1 in that the relay 53 is replaced by a current interruption device 210.

[0109] The current interruption device 210 consists of a first FET 211 and a second FET 213 that are connected back-to-back.

[0110] If the battery 200 becomes overcharged, the first FET 211 is closed and the second FET 123 is opened, allowing the battery 200 to discharge to the automobile 10 while limiting charging with the parasitic diode D2.

[0111] The control device 150 can suppress failure of the second FET 213 due to heat generation from the parasitic diode D2 by closing the second FET 213 when the operating point P of the second FET 213 exceeds the IT judgment line F0 while it is discharging through the path passing through the parasitic diode D2.

[0112] Furthermore, the first FET 211 may also be protected. That is, by opening the first FET 211 and closing the second FET 123, when the battery 200 is being charged through the path passing through the parasitic diode D1, if the operating point P of the first FET 211 exceeds the IT judgment line F0, closing the first FET 211 can suppress failure of the first FET 211 due to overheating of the parasitic diode D1.

[0113] <Other Embodiments> The present invention is not limited to the embodiments described above and in the drawings, and the following embodiments, for example, are also included in the technical scope of the present invention.

[0114] (1) The cell (a rechargeable energy storage cell) 62 is not limited to a lithium-ion secondary battery cell, but may also be other non-aqueous electrolyte secondary battery cells. The cell 62 may be connected in series or parallel, or it may be connected in series or as a single cell. A capacitor can also be used instead of a secondary battery cell. Secondary battery cells and capacitors are examples of cells.

[0115] (2) In the above embodiment, the battery 50 was mounted on the automobile 10, but it may also be mounted on a mobile body other than a vehicle, such as a ship or an aircraft. Furthermore, it may not be limited to mobile bodies, but may also be used for stationary applications such as energy storage devices for absorbing fluctuations in distributed power generation systems or UPS (uninterruptible power supply).

[0116] (3) In the above embodiment, the relay 53 is placed on the positive power line 57P and the current sensor 55 is placed on the negative power line 57N. Alternatively, the current sensor 55 may be placed on the positive power line 57P and the relay 53 may be placed on the negative power line 57N. Also, in the above embodiment, a P-channel FET was used in the bypass circuit 120, but an N-channel FET may be used.

[0117] (4) In the above embodiment 1, when the operating point P of the second FET 123 exceeds the IT determination line F0, the system proceeds to S20, and the control device 150 simultaneously sends switching signals from OPEN to CLOSE to the relay 53 and the second FET 123. If the second FET 123 can be closed before the contact 53A of the relay 53 closes, it is not necessarily required to send the switching signals simultaneously. The switching signal may be sent to the relay 53 first, and then to the second FET 123.

[0118] (5) In the above embodiment 1, the IT condition of the second FET 123 was determined (S10), and FET protection processing (S20 to S40) was performed. The execution of FET protection processing (S20 to S40) may be determined by other conditions, as long as it is based on the current I and energizing time T of the second FET 123.

[0119] (6) In the above embodiment 1, the IT condition of the second FET 123 was determined (S10), and FET protection processing (S20~S40) was executed. Alternatively, the temperature condition of the second FET 123 may be determined (S10), and FET protection processing (S20~S40) may be executed. In other words, FET protection processing (S20~S40) may be executed when the temperature of the second FET 123 exceeds a threshold. In this case, a temperature sensor 125 may be added to the bypass circuit 120 to measure the temperatures of the first FET 121 and the second FET 123 (Figure 16). [Explanation of symbols]

[0120] 50. Battery (energy storage device) 53 Relay 55 Current Sensor 60 battery packs 62 cells 120 Bypass Circuit 121 1st FET 123 2nd FET 150 Management device

Claims

1. It is an energy storage device, Cells and, A relay that interrupts the current to the cell, A bypass circuit connected in parallel to the relay, Includes a management device, The bypass circuit is It includes two FETs connected back-to-back, If the control device detects an abnormality in the cell, The relay is opened, one of the two FETs is closed, and the other is opened, allowing the cell to discharge or charge through the parasitic diode of the FET. The control device is an energy storage device that, when the current I and energizing time T of the FET reach predetermined conditions or the temperature of the FET reaches predetermined conditions while the FET is discharging or charging through the path passing through the parasitic diode, closes the relay and the other FET that is open.

2. It is an energy storage device, Cells and, A relay that interrupts the current to the cell, A bypass circuit connected in parallel to the relay, Includes a management device, The bypass circuit is It includes two FETs connected back-to-back, If the control device detects an abnormality in the cell, The relay is opened, one of the two FETs is closed, and the other is opened, allowing the cell to discharge or charge through the parasitic diode of the FET. The control device is an energy storage device in which, when the current I and energizing time T of the FET reach predetermined conditions or the temperature of the FET reaches predetermined conditions while the FET is being discharged or charged through the path passing through the parasitic diode, the relay is kept OPEN and the other FET that is OPEN is closed.

3. A power storage device according to claim 1 or claim 2, The abnormality of the aforementioned cell is due to overcharging or over-discharging in the energy storage device.

4. An energy storage device for starting an engine according to claim 1 or claim 2.

5. It is an energy storage device, Cells and, A current interruption device including a relay for interrupting the current of a cell and a bypass circuit connected in parallel to the relay, Includes a management device, The bypass circuit included in the current interruption device is It includes two FETs connected back-to-back, If the control device detects an abnormality in the cell, The relay is opened, one of the two FETs is closed, and the other is opened, allowing the cell to discharge or charge through the parasitic diode of the FET. The control device is an energy storage device that, when the current I and energizing time T of the FET reach predetermined conditions or the temperature of the FET reaches predetermined conditions while the FET is discharging or charging through the path passing through the parasitic diode, closes the relay and the other FET that is open.

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