Method for resetting a hardware unit in an integrated circuit and integrated circuit

Abstract

This disclosure provides a method and apparatus for resetting a hardware unit of an integrated circuit. [Solution] When it is detected that a reset of the first hardware unit is required in the first operating system, before the reset of the first hardware unit, the system determines the data channel adjustment policy between the second hardware unit in the second operating system that shares the bus with the first operating system and the first hardware unit based on the operating state of the interface between the first hardware unit and the bus, and adjusts the traffic control state of the data channel to complete any incomplete access requests between the first hardware unit and the second hardware unit, and blocks the transmission of newly generated access requests to the bus by the first hardware unit.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular, to a method for resetting a hardware unit in an integrated circuit and an integrated circuit.

Background Art

[0002] A system on chip (SoC), also referred to as an integrated circuit, may include multiple hardware units, which can support the execution of multiple operating systems (OS), thereby enabling the multiple operating systems to run on the integrated circuit. When executing their respective corresponding operating systems, the multiple hardware units can share some hardware resources (e.g., a bus) in the integrated circuit, that is, the multiple hardware units can access each other via the bus.

[0003] When an abnormality occurs in an operating system, by resetting the hardware unit that caused the abnormality (hereinafter abbreviated as "abnormal hardware unit"), the operating system in which the abnormality occurred (hereinafter abbreviated as "abnormal operating system") can be restored to normal operation.

Summary of the Invention

Problems to be Solved by the Invention

[0004] When resetting the abnormal hardware unit in the abnormal operating system, incomplete access requests in transmission cannot be processed normally, and the abnormal hardware unit continues to transmit new access requests to the bus, which causes an abnormality in the bus, abnormalities in other hardware units sharing the bus, and further, an abnormality also occurs in the operating system executed by these other hardware units.

[0005] This disclosure provides a method for resetting a hardware unit in an integrated circuit and an integrated circuit that can solve the problem of when a faulty hardware unit in a faulty operating system is reset, a fault occurs in other hardware units sharing the bus, and a fault occurs in the operating system run by these other hardware units, in order to solve the above technical problems. [Means for solving the problem]

[0006] A method for resetting a hardware unit in an integrated circuit according to a first aspect of the present disclosure includes: reading from a register the state of a reset signal for requesting a reset of a first hardware unit corresponding to a first operating system; determining the operational state of an interface between the first hardware unit and a bus based on the state of the reset signal; determining a coordination policy for two or more data channels between the first hardware unit and a second hardware unit corresponding to a second operating system based on the operational state of the interface; adjusting the traffic control state of the data channels based on the coordination policy; and resetting the first hardware unit based on the operational state of the interface after the traffic control state of the data channels has been adjusted.

[0007] An integrated circuit according to a second aspect of the present disclosure comprises a first hardware unit corresponding to a first operating system, a second hardware unit corresponding to a second operating system, a reset security module corresponding to the first hardware unit, and a register storing the state of a reset signal for requesting a reset of the first hardware unit, wherein the reset security module reads the state of the reset signal from the register, determines the operating state of the interface between the first hardware unit and the bus based on the state of the reset signal, determines a coordination policy for two or more data channels between the first hardware unit and the second hardware unit based on the operating state of the interface, adjusts the traffic control state of the data channels based on the coordination policy, and resets the first hardware unit based on the operating state of the interface after the traffic control state of the data channels has been adjusted.

[0008] A computer-readable storage medium according to the third aspect of this disclosure stores a computer program that performs a method for resetting a hardware unit in an integrated circuit according to the first aspect described above.

[0009] An electronic device according to a fourth aspect of the present disclosure comprises a processor and a memory for storing commands that the processor can execute, wherein the processor performs a method of resetting a hardware unit in the integrated circuit according to the first aspect, by reading and executing an executable command from the memory, or the electronic device comprises the integrated circuit according to the second aspect.

[0010] In the fifth aspect of the present disclosure, when a command in the computer program product is executed by a processor, a method for resetting a hardware unit in the integrated circuit according to the first aspect described above is executed. [Effects of the Invention]

[0011] According to the method for resetting a hardware unit in an integrated circuit according to this disclosure, when it is detected in the first operating system that the first hardware unit needs to be reset, before resetting the first hardware unit, the method determines the data channel adjustment policy between the first hardware unit and the second hardware unit in the second operating system that shares the bus with the first operating system, based on the operating state of the interface between the first hardware unit and the bus, and adjusts the traffic control state of the data channel to complete any incomplete access requests between the first hardware unit and the second hardware unit, and to block the transmission of newly generated access requests to the bus by the first hardware unit. As a result, when the first hardware unit is reset, the bus can still operate normally, the second hardware unit that shares the bus can still operate normally, and therefore the second operating system run by the second hardware unit can still operate normally, significantly improving the stability of the execution of each operating system. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram of the architecture of an integrated circuit according to one exemplary embodiment of the present disclosure. [Figure 2] This is a schematic diagram of the architecture of an integrated circuit relating to another exemplary embodiment of the present disclosure. [Figure 3] This is a schematic diagram of the architecture of an integrated circuit relating to yet another exemplary embodiment of the present disclosure. [Figure 4] This is a schematic diagram of a flow chart of a method for resetting a hardware unit in an integrated circuit according to one exemplary embodiment of the present disclosure. [Figure 5] This is a schematic diagram of a flow chart of a method for resetting a hardware unit in an integrated circuit according to another exemplary embodiment of the present disclosure. [Figure 6] This is a schematic diagram of a flow chart of a method for resetting a hardware unit in an integrated circuit according to yet another exemplary embodiment of the present disclosure. [Figure 7] This is a schematic diagram of a flow chart of a method for resetting a hardware unit in an integrated circuit according to yet another exemplary embodiment of the present disclosure. [Figure 8] This is a schematic diagram of a flow chart of a method for resetting a hardware unit in an integrated circuit according to yet another exemplary embodiment of the present disclosure. [Figure 9] This is a schematic diagram of a flow chart of a method for resetting a hardware unit in an integrated circuit according to yet another exemplary embodiment of the present disclosure. [Figure 10] This is a schematic diagram of the structure of an electronic device according to one exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0013] Hereinafter, illustrative embodiments of the Disclosure will be described in detail with reference to the drawings, but the embodiments described are not all embodiments, but only a selection of embodiments of the Disclosure, and the Disclosure is not limited to the illustrative embodiments.

[0014] The scope of this disclosure is not limited to the relative arrangements, formulas, and values ​​of the components and steps described in these embodiments, unless otherwise specified.

[0015] [Summary of the application] A system on chip (SoC), also referred to as an integrated circuit, may include multiple hardware units, which can support the execution of multiple operating systems (OS), thereby enabling the multiple operating systems to run on the integrated circuit. When executing their corresponding operating systems, the multiple hardware units can share some hardware resources (e.g., a bus) in the integrated circuit, that is, the multiple hardware units can access each other via the bus.

[0016] When an abnormality occurs in an operating system, the abnormal operating system can be recovered to operate normally by resetting the abnormal hardware unit.

[0017] However, when resetting the abnormal hardware unit, uncompleted transmitted access requests cannot be processed normally, and the abnormal hardware unit continues to transmit new access requests to the bus, which causes an abnormality in the bus, leading to abnormalities in other hardware units sharing the bus, and further, an abnormality may also occur in the operating system executed by these other hardware units.

[0018] Embodiments of the present disclosure provide an apparatus and method for resetting a hardware unit in an integrated circuit, so as to solve the above technical problems.

[0019] The device comprises a first hardware unit corresponding to a first operating system, a second hardware unit corresponding to a second operating system, a reset security module corresponding to the first hardware unit, and a register storing the state of a reset signal for requesting a reset of the first hardware unit. The reset security module reads the state of the reset signal from the register. The reset security module further determines the operational state of the interface between the first hardware unit and the bus based on the state of the reset signal. The reset security module further determines the coordination policy for two or more data channels between the first hardware unit and the second hardware unit based on the operational state of the interface. The reset security module further adjusts the traffic control state of the data channels based on the coordination policy. The reset security module further resets the first hardware unit based on the operational state of the interface after the traffic control state of the data channels has been adjusted.

[0020] When it is detected that a first hardware unit in a first operating system needs to be reset, before resetting the first hardware unit, an adjustment policy for a data channel between the first hardware unit and a second hardware unit in a second operating system that shares a bus with the first operating system is determined based on the operating state of the interface between the first hardware unit and the bus, and the traffic control state of the data channel is adjusted, so that uncompleted access requests between the first hardware unit and the second hardware unit are completed, and transmission of new access requests generated by the first hardware unit to the bus is blocked. As a result, when resetting the first hardware unit, the bus can still operate normally, the second hardware unit sharing the bus can still operate normally, and thus the second operating system executed by the second hardware unit can still run normally, which greatly improves the execution stability of each operating system.

[0021] Hereinafter, the method for resetting a hardware unit in an integrated circuit according to the present disclosure will be further described with reference to the drawings.

[0022] [Exemplary System] Figure 1 is a schematic diagram of an architecture of an integrated circuit according to an exemplary embodiment of the present disclosure.

[0023] As shown in Figure 1, this integrated circuit can run multiple operating systems, such as a first operating system 11 and a second operating system 12. Each operating system is run by at least one hardware unit; for example, the first operating system 11 can be run by a first hardware unit 13, and the second operating system 12 can be run by a second hardware unit 14. When the first hardware unit 13 and the second hardware unit 14 are running their respective operating systems, they can share a bus 15 in the integrated circuit, meaning that the first hardware unit 13 and the second hardware unit 14 can access each other via the bus 15.

[0024] This integrated circuit further includes reset security modules that correspond one-to-one with hardware units, and the hardware units are connected to the bus 15 via the corresponding reset security modules. For example, the first hardware unit 13 is connected to the bus 15 via the first reset security module 161, and the second hardware unit 14 is connected to the bus 15 via the second reset security module 162.

[0025] In some embodiments, before resetting a hardware unit, the reset security module corresponding to that hardware unit can monitor the state of the interface between the hardware unit and the bus, and adjust the traffic control state of the data channel between this hardware unit and other hardware units based on the interface state.

[0026] Figure 2 is a schematic diagram of the architecture of an integrated circuit according to another exemplary embodiment of the present disclosure.

[0027] In some examples, the structure of a reset security module is illustrated using the first reset security module 161 as an example, as shown in Figure 2, on the architecture shown in Figure 1 above. The first reset security module 161 may include three counters, such as a first counter 211 (e.g., an instruction read counter), a second counter 212 (e.g., an instruction write counter), and a third counter 213 (e.g., a data write counter). Here, the first counter 211 counts the number of incomplete instruction read requests transmitted between the first hardware unit 13 and the second hardware unit 14, the second counter 212 counts the number of incomplete instruction write requests transmitted between the first hardware unit 13 and the second hardware unit 14, and the third counter 213 counts the number of incomplete data write requests transmitted between the first hardware unit 13 and the second hardware unit 14.

[0028] The first reset security module 161 comprises multiple logical control unit groups, each logical control unit group containing at least one logical control unit. Here, different logical control unit groups correspond to data channels of different request types, and each logical control unit group controls the traffic control state of the data channel corresponding to the channel type.

[0029] For example, the first logical control unit group 222 corresponds to a data channel 221 for transmitting instruction read requests (hereinafter abbreviated as "instruction read channel") and controls the traffic control state of the instruction read channel.

[0030] For example, the second logical control unit group 232 corresponds to a data channel 231 for transmitting data read requests (hereinafter abbreviated as "data read channel") and controls the traffic control state of the data read channel.

[0031] For example, the third logical control unit group 242 corresponds to a data channel (hereinafter abbreviated as "instruction write channel") 241 for transmitting instruction write requests and controls the traffic control state of the instruction write channel.

[0032] For example, the fourth logical control unit group 252 corresponds to a data channel 251 for transmitting response write requests (hereinafter abbreviated as "response write channel") and controls the traffic control state of the response write channel.

[0033] For example, the fifth logical control unit group 262 corresponds to a data channel 261 for transmitting data writes (hereinafter abbreviated as "data write channel") and controls the traffic control state of the data write channel.

[0034] Here, the traffic control state of a data channel includes Release and Blocking. A Release state for a data channel indicates that the transmission of access requests through this data channel is permitted, while a Blocking state indicates that the transmission of access requests through this data channel is not permitted.

[0035] The reset security module further comprises a timeout count module, and as shown in Figure 2, the first reset security module 161 includes a timeout count module 27 for detecting whether the reset request was successful or not. Whether the reset request was successful or not indicates whether the first reset security module 161 reset the first hardware unit 13 based on the reset request. If the reset request is successful, the first reset security module 161 resets the first hardware unit 13 based on the reset request, and if the reset request fails, the first reset security module 161 does not reset the first hardware unit 13 based on the reset request.

[0036] In some embodiments, before resetting the hardware unit, the hardware unit and the bus can be further isolated by a reset security module.

[0037] Figure 3 is a schematic diagram of the architecture of an integrated circuit according to yet another exemplary embodiment of the present disclosure.

[0038] In some examples, in addition to the structure of the first reset security module 161 shown in Figure 2 above, the first reset security module 161 further comprises an isolation control unit 31 for isolating the first hardware unit 13 from the bus 15, as shown in Figure 3.

[0039] As shown in Figure 1, the integrated circuit further includes a register 17 for storing the state of the reset signal.

[0040] [Example Method] Figure 4 is a schematic flowchart of a method for resetting a hardware unit in an integrated circuit according to one exemplary embodiment of the present disclosure. This embodiment can be applied to electronic equipment comprising the integrated circuit shown in any one of Figures 1 to 3, and the embodiment of the present disclosure describes a method for resetting a hardware unit in an integrated circuit, taking as an example that the hardware unit to be reset is the first hardware unit 13.

[0041] As shown in Figure 4, this method includes the following steps 41 to 45.

[0042] In step 41, the state of the reset signal is read from the register.

[0043] Register 17 stores state information for a reset signal used to request a reset of the first hardware unit 13, and this reset signal state information can be state bits associated with the reset signal.

[0044] Here, the reset signal can carry state information, which indicates the state of the reset signal, and the state of the reset signal indicates whether or not to initiate a reset request to the hardware unit.

[0045] Exemplary, the states of the reset signal may include a first preset state and a fourth preset state, where the first preset state indicates that a reset request should be initiated and may also be called the enabled state, and the fourth preset state indicates that a reset request should not be initiated and may also be called the disabled state.

[0046] In some examples, the first preset state of the reset signal can be a high-level state, and the fourth preset state of the reset signal can be a low-level state.

[0047] Register 17 may also store indicator information for the hardware unit for which a reset has been requested by the reset signal. For example, if the reset signal is used to request a reset of the first hardware unit 13, then register 17 stores the indicator information for the first hardware unit 13.

[0048] In some examples, different hardware units correspond to different registers 17, making it easier to more accurately manage the relevant information for the reset signal used to request a reset for each hardware unit.

[0049] The first reset security module 161, which corresponds to the first hardware unit 13, reads the state information of the reset signal for requesting a reset of the first hardware unit 13 from the register 17, and can determine the state of the reset signal based on this state information, that is, whether or not to initiate a reset request to the first hardware unit 13.

[0050] In step 42, the operating state of the interface between the first hardware unit and the bus is determined based on the state of the reset signal.

[0051] Here, the operating state of the interface between the first hardware unit 13 and the bus 15 indicates whether or not there is an incomplete access request transmission between the first hardware unit 13 and the second hardware unit 14.

[0052] Exemplary, the operating states of the interface may include a second preset state and a third preset state. Here, the second preset state represents the existence of an incomplete access request transmission between the first hardware unit 13 and the second hardware unit 14, and is also called the non-idle state, while the third preset state represents the absence of an incomplete access request transmission between the first hardware unit 13 and the second hardware unit 14, and is also called the idle state.

[0053] When the first hardware unit 13 is reset, if the interface is in the second preset state (i.e., the interface is in an idle state), it indicates that there are incomplete access requests between the first hardware unit 13 and the second hardware unit 14. The first hardware unit 13 will continue to generate access requests to access the second hardware unit 14 and may transmit these newly generated access requests to the bus 15. Thus, resetting the first hardware unit 13 affects the bus 15 and also affects the second hardware unit 14. When the interface is in the third preset state (i.e., the interface is in an idle state), it indicates that there are no incomplete access requests between the first hardware unit 13 and the second hardware unit 14. However, the first hardware unit 13 will continue to generate access requests to access the second hardware unit 14 and may transmit these newly generated access requests to the bus 15. Thus, resetting the first hardware unit 13 also affects the bus 15 and the second hardware unit 14.

[0054] The first reset security module 161 can determine whether or not to initiate a reset request to the first hardware unit 13 based on the state of the reset signal.

[0055] Here, assuming the reset signal state indicates that a reset request is initiated to the first hardware unit 13, the first reset security module 161 needs to determine the operating state of the interface between the first hardware unit 13 and the bus 15 in order to prevent the reset of the first hardware unit 13 from affecting the bus 15 and the second hardware unit 14. This allows the module to then determine, based on the operating state of the interface, which access requests would affect the bus 15 and the second hardware unit 14 when the first hardware unit 13 is reset, and to perform corresponding processing for these access requests.

[0056] If the state of the reset signal indicates that no reset request is initiated to the first hardware unit 13, the first reset security module 161 can determine that it does not need to determine the operating state of the interface, that is, it can determine that it does not need to process access requests between the first hardware unit 13 and the second hardware unit 14.

[0057] In step 43, the coordination policy for two or more data channels between the first hardware unit and the second hardware unit is determined based on the operating status of the interface.

[0058] The first reset security module 161 determines, based on the operating state of the interface, the access requests that affect the bus 15 and the second hardware unit 14 when resetting the first hardware unit 13, and based on these access requests, it can determine the traffic control state to which each data channel between the first hardware unit 13 and the second hardware unit 14 should be adjusted. Furthermore, the first reset security module 161 can determine an adjustment policy corresponding to each data channel based on the traffic control state to which each data channel should be adjusted. This adjustment policy includes a method for adjusting the traffic control state of the corresponding data channel to the traffic control state to be adjusted, and exemplary this method may include a signal level state corresponding to the request type of access request transmitted on the data channel.

[0059] In step 44, the traffic control state of the data channel is adjusted based on the adjustment policy.

[0060] The first reset security module 161 adjusts the traffic control state of the data channel based on the adjustment policy. Here, the first reset security module 161 determines a target logical control unit group for adjusting the traffic control state of the data channel based on the adjustment policy, and this target logical control unit group can adjust the traffic control state of the corresponding data channel.

[0061] After the first reset security module 161 adjusts the traffic control state of the data channel, any incomplete access requests between the first hardware unit 13 and the second hardware unit 14 can be completed by the data channel with the adjusted traffic control state, and any new access requests generated by the first hardware unit 13 cannot be transmitted to the bus 15 via the data channel with the adjusted traffic control state. This effectively clears any incomplete access requests between the first hardware unit 13 and the second hardware unit 14 and blocks any new access requests generated by the first hardware unit 13 before resetting the first hardware unit 13.

[0062] In step 45, the first hardware unit is reset based on the operating state of the interface.

[0063] The first reset security module 161 can re-determine the operating state of the interface after adjusting the traffic control state of the data channel.

[0064] Here, when the interface is in the third preset state, it means that resetting the first hardware unit 13 does not affect the bus 15 and the second hardware unit 14, and the first reset security module 161 can reset the first hardware unit 13. For example, the first reset security module 161 can reset the first hardware unit 13 by generating first instruction information to indicate the success of the reset request. The first reset security module 161 writes the first instruction information to register 17 and can reset the first hardware unit 13 based on this first instruction information.

[0065] When the interface is in the second preset state, resetting the first hardware unit 13 will affect the bus 15 and the second hardware unit 14. Therefore, the first hardware unit 13 cannot be reset at this time, and it is necessary to wait until the interface changes to the third preset state before resetting the first hardware unit 13.

[0066] In a method for resetting a hardware unit in an integrated circuit according to an embodiment of the present disclosure, when the first reset security module 161 determines that the first hardware unit 13 in the first operating system 11 needs to be reset, before resetting the first hardware unit 13, it adjusts the traffic control state of the data channel between the first hardware unit 13 and the second hardware unit 14 based on the operating state of the interface between the first hardware unit 13 and the bus 15, thereby completing any incomplete access requests transmitted between the first hardware unit 13 and the second hardware unit 14, and blocking the transmission of newly generated access requests by the first hardware unit 13 to the bus 15. This allows the bus 15 to continue operating normally when the first hardware unit 13 is reset, the second hardware unit 14 sharing the bus 15 to continue operating normally, and therefore the second operating system 12 running on the second hardware unit 14 to continue running normally, improving the stability of the execution of the second operating system 12.

[0067] Figure 5 is a schematic flowchart of a method for resetting a hardware unit in an integrated circuit according to another exemplary embodiment of the present disclosure.

[0068] In some embodiments, as shown in Figure 5, step 42 above may include steps 421 to 422 in the embodiment shown in Figure 4 above.

[0069] In step 421, the number of first access requests is determined in response to the reset signal being in the first preset state.

[0070] The first reset security module 161, in response to the reset signal being in a first preset state, determines that it should initiate a reset request to the first hardware unit 13, that is, it needs to reset the first hardware unit 13. This allows the first reset security module 161 to determine the operational state of the interface between the first hardware unit 13 and the bus 15 before resetting the first hardware unit 13.

[0071] The interface's operating status indicates whether or not there are incomplete access requests between the first hardware unit 13 and the second hardware unit 14, and the first reset security module 161 determines the number of first access requests. Here, the first access requests are incomplete access requests among the access requests in which the first hardware unit 13 requests access to the second hardware unit 14.

[0072] In step 422, the operational state of the interface is determined based on the number of initial access requests.

[0073] A first access request count of 0 indicates that there are no incomplete access requests, and therefore the first reset security module 161 can determine that the interface's operating state is the third preset state (i.e., idle state).

[0074] If the number of first access requests is greater than 0, it indicates that there are access requests that have not been transmitted, and therefore the first reset security module 161 can determine that the operating state of the interface is the second preset state (i.e., the non-idle state).

[0075] In the method for resetting a hardware unit in an integrated circuit according to an embodiment of the present disclosure, the first reset security module 161, after determining that the first hardware unit 13 needs to be reset, can accurately determine the operating state of the interface between the first hardware unit 13 and the bus 15 based on the number of first access requests that have not yet been transmitted between the first hardware unit 13 and the second hardware unit 14, and further ensure the accuracy of determining the data channel adjustment policy based on this interface operating state.

[0076] Figure 6 is a schematic flowchart of a method for resetting a hardware unit in an integrated circuit according to yet another exemplary embodiment of the present disclosure.

[0077] In some embodiments, as shown in Figure 6, step 422 above may include steps 4221 to 4223 in the embodiment shown in Figure 5 above.

[0078] Step 4221 determines the request type for the first access request.

[0079] Here, the request types of the first access request include instruction read requests, instruction write requests, and data write requests.

[0080] Step 4222 determines the number of requests corresponding to the request type in the first access request.

[0081] Referring to Figures 2 and 3, the first counter 211 can be used to count the number of instruction read requests, the second counter 212 can be used to count the number of instruction write requests, and the third counter 213 can be used to count the number of data write requests.

[0082] For example, the first counter 211 increments its count value by 1 each time it detects an instruction read request transmitted by the first hardware unit 13 via the instruction read channel 221, and decrements its count value by 1 each time it detects a valid RLAST signal transmitted by the second hardware unit 14 via the data read channel 231. The first reset security module 161 can read the count value of the first counter 211 and determine this count value as the number of instruction read requests in the first access request.

[0083] For example, the second counter 212 increments its count value by 1 each time it detects an instruction write request transmitted by the first hardware unit 13 via the instruction write channel 241, and decrements its count value by 1 each time it detects a response write transmitted by the second hardware unit 14 via the response write channel 251. The first reset security module 161 can read the count value of the second counter 212 and determine this count value as the number of instruction write requests in the first access request.

[0084] For example, the third counter 213 increments its count value by 1 each time it detects a WLAST signal in a data write request transmitted by the first hardware unit 13 via the data write channel 261, and decrements its count value by 1 each time it detects a response write transmitted by the second hardware unit 14 via the response write channel 251. The first reset security module 161 can read the count value of the third counter 213 and determine this count value as the number of data write requests in the first access request.

[0085] In step 4223, the operational state of the interface is determined based on the number of requests.

[0086] Here, if the number of instruction read requests is greater than 0, the first reset security module 161 can determine that the data channel corresponding to the read operation is not idle, and if the number of instruction read requests is equal to 0, the first reset security module 161 can determine that the data channel corresponding to the read operation is idle.

[0087] If the number of requests of at least one request type among the number of instruction write requests and the number of data write requests is greater than 0, the first reset security module 161 can determine that the data channel corresponding to the write operation is not idle. If the number of instruction write requests and the number of data write requests are both equal to 0 and the third counter 213 determines that the WVALID signal transmitted by the detected first hardware unit 13 via the data write channel 261 corresponds to the last data write request, or if the number of instruction write requests and the number of data write requests are both equal to 0 and the third counter 213 does not detect a WVALID signal transmitted by the first hardware unit 13 via the data write channel 261, the first reset security module 161 can determine that the data channel corresponding to the write operation is idle.

[0088] The first reset security module 161 determines the operating state of the interface based on the state of the data channel corresponding to the read operation and the state of the data channel corresponding to the write operation. Here, if at least one of the states of the data channel corresponding to the read operation and the state of the data channel corresponding to the write operation is in a non-idle state, the first reset security module 161 can determine that the operating state of the interface is in a second preset state (i.e., a non-idle state). If both the state of the data channel corresponding to the read operation and the state of the data channel corresponding to the write operation are in an idle state, the first reset security module 161 can determine that the operating state of the interface is in a third preset state (i.e., an idle state).

[0089] In the method for resetting a hardware unit in an integrated circuit according to an embodiment of the present disclosure, the first reset security module 161, after determining that the first hardware unit 13 needs to be reset, can classify and monitor first access requests of different request types, thereby enabling rapid determination of the request type corresponding to the first access request after determining that the first access request exists. Because there is a correlation between the request type and the data channel, the efficiency of determining the data channel adjustment policy can be improved.

[0090] Figure 7 is a schematic flowchart of a method for resetting a hardware unit in an integrated circuit according to a further exemplary embodiment of the present disclosure.

[0091] In some embodiments, as shown in Figure 7, step 43 may include steps 431 to 432 in the embodiment shown in Figure 4 above.

[0092] In step 431, the first and second data channels are determined from two or more data channels based on the operating state of the interface.

[0093] Here, the traffic control state of the first data channel needs to be adjusted to blocking, and the traffic control state of the second data channel needs to be adjusted to release.

[0094] In some examples, when the interface is in a second preset state (i.e., a non-idle state), the first reset security module 161 determines the operation type corresponding to the first access request. The operation types corresponding to the first access request include read operations and write operations, where an instruction read request in the first access request corresponds to a read operation, and an instruction write request and a data write request in the first access request correspond to a write operation.

[0095] The first reset security module 161 determines the first data channel and the second data channel from two or more data channels between the first hardware unit 13 and the second hardware unit 14 based on the operation type corresponding to the first access request.

[0096] Here, if the operation type corresponding to the first access request is a read operation, the first reset security module 161 can determine that the first data channel includes the instruction read channel 221 and the second data channel includes the data read channel 231.

[0097] If the operation type corresponding to the first access request is a write operation, the first reset security module 161 can determine the relative size of the number of instruction write requests and the number of data write requests in the first access request. For example, the first reset security module 161 can read the current count value from the second counter 212, which is the number of instruction write requests, and the first reset security module 161 can read the current count value from the third counter 213, which is the number of data write requests. The first reset security module 161 compares these two count values ​​to determine the relative size of these two count values, which is the relative size of the number of instruction write requests and the number of data write requests. Based on this relative size, the first reset security module 161 can determine the first data channel and the second data channel.

[0098] For example, if this relationship is determined to be such that the number of data write requests is greater than or equal to the number of instruction write requests, and the third counter 213 has detected valid WVALID and WLAST signals transmitted by the first hardware unit 13 via the data write channel 261, then the first reset security module 161 can determine that the first data channel includes the data write channel 261 and the second data channel includes the instruction write channel 241.

[0099] Alternatively, if the magnitude relationship is such that the number of data write requests is equal to the number of instruction write requests, and the third counter 213 does not detect a WVALID signal transmitted by the first hardware unit 13 via the data write channel 261, the first reset security module 161 can determine that the first data channel includes the data write channel 261 and the second data channel includes the instruction write channel 241.

[0100] For example, if the order of magnitude is such that the number of instruction write requests is greater than or equal to the number of data write requests, the first reset security module 161 can determine that the first data channel includes the instruction write channel 241 and the second data channel includes the data write channel 261 and the response write channel 251.

[0101] In some examples, when the interface is in a third preset state (i.e., idle state), the first reset security module 161 can determine all two or more data channels between the first hardware unit 13 and the second hardware unit 14 as the first data channel, that is, it can adjust the traffic control state of all data channels to blocking, thereby preventing the transmission of newly generated access requests to the bus 15 by the first hardware unit 13.

[0102] In step 432, the adjustment policies corresponding to the first and second data channels are determined, respectively.

[0103] Here, the first reset security module 161 determines the adjustment policy corresponding to the first data channel, which is for adjusting the traffic control state of the first data channel to blocking.

[0104] For example, if the first data channel includes an instruction read channel, the first reset security module 161 can determine that the adjustment policy corresponding to the instruction read channel 221 adjusts the ARVALID signal transmitted on the instruction read channel 221 to a low level state and the ARREADY signal transmitted on the instruction read channel 221 to a high level state.

[0105] For example, if the first data channel includes an instruction write channel 241, the first reset security module 161 can determine that the adjustment policy corresponding to the instruction write channel 241 adjusts the AWVALID signal transmitted on the instruction write channel 241 to a low level state and the AWREADY signal transmitted on the instruction write channel 241 to a high level state.

[0106] For example, if the first data channel includes a data write channel 261, the first reset security module 161 can determine that the adjustment policy corresponding to the data write channel 261 adjusts the WVALID signal transmitted on the data write channel 261 to a low level state and the WREADY signal transmitted on the data write channel 261 to a high level state.

[0107] The first reset security module 161 determines the adjustment policy corresponding to the second data channel, which is used to adjust the traffic control state of the second data channel to release.

[0108] For example, if the second data channel includes a data read channel 231, the first reset security module 161 can determine that the adjustment policy corresponding to the data read channel 231 adjusts the RREADY signal transmitted on the data read channel 231 to a high level state.

[0109] For example, if the second data channel includes a response write channel 251, the first reset security module 161 can determine that the adjustment policy corresponding to the response write channel 251 adjusts the BREADY signal transmitted on the response write channel 251 to a high level state.

[0110] In some examples, when the reset request state is in the fourth preset state, i.e., when no reset request has been initiated to the first hardware unit 13, i.e., when the first hardware unit 13 and the second hardware unit 14 can be accessed normally, the traffic control state of both the instruction write channel 241 and the data write channel 261 is released. Thus, when the first reset security module 161 determines that the second data channel includes the instruction write channel 241 and / or the data write channel 261, it can determine that the corresponding adjustment policy maintains the original level state of the signals transmitted on each data channel.

[0111] In some examples, the first reset security module 161 can adjust the level state of signals transmitted on the corresponding data channel by a logical control unit group corresponding to an adjustment policy.

[0112] In the method for resetting a hardware unit in an integrated circuit according to the embodiment of this disclosure, based on a first access request, the traffic control state to which each data channel should be adjusted can be accurately determined, and based on the traffic control state to which each data channel should be adjusted, the adjustment policy corresponding to each data channel can be accurately determined. Based on this adjustment policy, after adjusting the traffic control state of each data channel, the effect of clearing incomplete access requests and blocking newly generated access requests by the first hardware unit 13 can be effectively achieved.

[0113] Figure 8 is a schematic flowchart of a method for resetting a hardware unit in an integrated circuit according to a further exemplary embodiment of the present disclosure.

[0114] In some embodiments, as shown in Figure 8, step 45 may include steps 451 to 453 in the embodiment shown in Figure 4 above.

[0115] In step 451, the first duration is read from the register.

[0116] When the first reset security module 161 determines that the first hardware unit 13 needs to be reset, the timeout count module 27 can determine the request state for requesting a reset from the first hardware unit 13. If the request state is successful, it can be determined that the first hardware unit 13 will actually be reset; if the request state is unsuccessful, it can be determined that the first hardware unit 13 will not be reset.

[0117] The timeout count module 27 can read a first duration from register 17 to monitor the timeout duration threshold when the reset signal is in a fourth preset state. In some examples, the timeout count module 27 can be controlled to adjust the QDENY signal to a low level state to indicate that no reset request has been initiated to the first hardware unit 13 at that time.

[0118] In step 452, the matching relationship between the operational state of the interface after the traffic control state of the data channel has been adjusted within the first duration and the third preset state is determined.

[0119] The timeout count module 27 starts timing from the time a first access request is made, or from the time when both the data channel corresponding to the write operation and the data channel corresponding to the read operation are not idle. Within a first duration, it monitors whether the operating state of the interface after the traffic control state of the data channel has been adjusted is in a third preset state, i.e., whether the adjustment policy is effective. In other words, after adjusting the traffic control state of the data channel, it can monitor whether the transmission of each first access request has been completed and whether all newly generated access requests have been blocked by the first hardware unit 13.

[0120] In step 453, the first hardware unit is reset based on the matching relationship.

[0121] Here, within the first duration, if the matching relationship between the operational state of the interface after the traffic control state of the data channel has been adjusted and the third preset state is a match, it indicates that the adjustment policy is effective, and the reset of the first hardware unit 13 does not affect the bus 15 and the second hardware unit 14, and the first hardware unit 13 can be reset. Correspondingly, the timeout count module 27 determines that the request state of the reset request is successful and generates instruction information indicating that the request state is successful, and the first reset security module 161 can reset the first hardware unit 13 based on this instruction information.

[0122] Within the first duration, if the matching relationship between the interface's operational state after the data channel's traffic control state has been adjusted and the third preset state is non-matching, it indicates that the adjustment policy is invalid, and the reset of the first hardware unit 13 cannot be performed because resetting the first hardware unit 13 would still affect the bus 15 and the second hardware unit 14. Correspondingly, the timeout count module 27 determines that the request state is a failure and generates instruction information indicating that the request state is a failure, and the first reset security module 161 does not reset the first hardware unit 13 based on this instruction information.

[0123] In the method for resetting a hardware unit in an integrated circuit according to an embodiment of the present disclosure, if it is monitored by a timeout monitoring method that the operating state of the interface has not been adjusted to an idle state within a specified duration, the reset of the first hardware unit 13 can be terminated in a timely manner, and furthermore, it is ensured that the bus 15 can still operate normally, and that the second hardware unit 14 sharing the bus 15 can also still operate normally.

[0124] Figure 9 is a schematic flowchart of a method for resetting a hardware unit in an integrated circuit according to a further exemplary embodiment of the present disclosure.

[0125] In some embodiments, as shown in Figure 9, step 453 may include steps 4531 to 4532 in the embodiment shown in Figure 8 above.

[0126] In step 4531, the interface's logical state is processed to the preset logical state based on the matching relationship indicating that the operational state of the interface after the data channel's traffic control state has been adjusted matches the third preset state.

[0127] When the matching relationship indicates that the operational state of the interface after the traffic control state of the data channel is adjusted matches the third preset state, the adjustment policy is determined to be effective, and when the third hardware unit 13 is reset, the problem of abnormalities occurring in bus 15 and the second hardware unit 14 due to incomplete access requests does not occur. However, when the first hardware unit 13 is reset, the first hardware unit 13 itself generates some unstable signals, and when these unstable signals are transmitted to bus 15, they affect bus 15 and the second hardware unit 14.

[0128] To solve this problem, the first reset security module 161 can isolate the first hardware unit 13 from the bus 15 using the isolation control unit 31. Here, the isolation control unit 31 processes the logical state of the interface between the first hardware unit 13 and the bus 15 into a preset logical state. This preset logical state is a fixed 0 or 1, and in this way, the first hardware unit 13 transmits a signal to the bus 15 in this preset logical state, that is, the first hardware unit 13 outputs a fixed 0 or 1 (i.e., a stable signal) to the bus 15. Since the stable signal output by the first hardware unit 13 does not affect the bus 15, this is equivalent to isolating the first hardware unit 13 from the bus 15.

[0129] Step 4532 resets the first hardware unit.

[0130] Even if the first hardware unit 13 is reset after the first reset security module 161 has isolated it, it will not affect the bus 15 and the second hardware unit 14, and the first hardware unit 13 will transmit a stable signal to the bus 15 in a preset logic state.

[0131] In the method for resetting a hardware unit in an integrated circuit according to an embodiment of the present disclosure, by setting the logic state of the interface between the first hardware unit 13 and the bus 15 to a preset logic state, when the first hardware unit 13 is reset, the first hardware unit 13 can output a stable signal to the bus 15 that does not affect the bus 15 in this preset logic state. Therefore, when the first hardware unit 13 is reset, the bus 15 can still operate normally, the second hardware unit 14 sharing the bus 15 can still operate normally, and therefore the second operating system 12 executed by the second hardware unit 14 can still run normally, significantly improving the stability of the execution of the second operating system 12.

[0132] [Example electronic device] Figure 10 is a schematic diagram of the structure of an electronic device according to one exemplary embodiment of the present disclosure. This electronic device comprises an integrated circuit 101, which may be the integrated circuit shown in any one of Figures 1, 2, and 3. The integrated circuit 101 comprises at least one processor 1011 and a memory 1012.

[0133] The processor 1011 can be a central processing unit (CPU) or another form of processing unit having data processing capability and / or command execution capability, and can control other components in the electronic device 10 to perform a desired function.

[0134] Memory 1012 can hold one or more computer program products, which may include various forms of computer-readable storage media such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard drives, flash memory, etc. Computer-readable storage media can store one or more computer program commands, and processor 1011 can execute one or more computer program commands to implement a method for resetting hardware units in the integrated circuits of each embodiment of the present disclosure and / or other desired functions.

[0135] As an example, the electronic device may further include an input device 102 and an output device 103 connected to each other via a bus system and / or other form of connection mechanism (not shown).

[0136] For simplification, Figure 10 shows only some of the components of this electronic device relevant to the disclosure, omitting components such as buses and input / output interfaces. The electronic device may further comprise any other suitable components depending on the specific application.

[0137] [Examples of computer program products and computer-readable storage media] Embodiments of the present disclosure may further provide computer program products, including computer program commands, in addition to the methods and devices described above. When the computer program commands are executed by the processor, the processor is caused to perform steps of a method for resetting hardware units in the integrated circuit in each embodiment of the present disclosure described in the “Exemplary Methods” portion above.

[0138] A computer program product can be created using any combination of one or more programming languages ​​to produce program code for performing the operations of the embodiments of this disclosure, and such programming languages ​​may include object-oriented programming languages ​​such as Java and C++, and may also include general procedural programming languages ​​such as the C language or similar programming languages. The program code may be executed as follows: it may be executed entirely on a user computing device, partially on a user device, as a standalone software package, partially on a user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0139] Furthermore, embodiments of the present disclosure may also be computer-readable storage media on which computer program commands are stored. When the computer program commands are executed by the processor, the processor causes the processor to perform the steps of a method for resetting the hardware units in the integrated circuit in each embodiment of the present disclosure as described in the “Exemplary Methods” portion above.

[0140] Any combination of one or more types of readable media can be used as a computer-readable storage medium. A readable medium can be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples (non-exclusive list) of readable storage media include electrical connections with one or more wires, portable disks, hard drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0141] While the basic principles of this disclosure have been explained above with reference to specific examples, the advantages, merits, and effects mentioned in this disclosure are illustrative and not limiting, and various examples of this disclosure do not necessarily possess these advantages, merits, and effects. Furthermore, the specific details of the above disclosure are for illustrative and easy-to-understand purposes only and are not limiting, and the above details do not necessarily restrict this disclosure to being realized by the above specific details.

[0142] The above description is provided for illustrative and illustrative purposes only. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. While several exemplary embodiments and examples have been described above, those skilled in the art will be able to recognize certain variations, modifications, changes, additions, and subcombinations thereof.

Claims

1. A method for resetting a hardware unit in an integrated circuit, wherein each step is performed by a device for resetting the hardware unit in the integrated circuit, The steps include reading the state of a reset signal from a register to request a reset of a first hardware unit corresponding to a first operating system, The steps include determining the operating state of the interface between the first hardware unit and the bus based on the state of the reset signal, The steps include determining the coordination policy for two or more data channels between the first hardware unit and a second hardware unit corresponding to the second operating system, based on the operating state of the interface, A step of adjusting the traffic control state of the data channel based on the adjustment policy, wherein the traffic control state of the data channel includes release and blocking. The step of resetting the first hardware unit based on the operating state of the interface after the traffic control state of the data channel has been adjusted, A method for resetting a hardware unit in an integrated circuit, characterized by the following:

2. The step of determining the operating state of the interface between the first hardware unit and the bus based on the state of the reset signal is as follows: A step of determining the number of first access requests in response to the state of the reset signal being a first preset state, wherein the first access requests are incomplete transmission access requests among access requests in which the first hardware unit requests access to the second hardware unit; Based on the number of the first access requests, the operating state of the interface is determined. A method for resetting a hardware unit in an integrated circuit according to feature 1.

3. The step of determining the operating state of the interface based on the number of the first access requests is: The steps include determining the request type in the first access request, The steps include determining the number of requests corresponding to the request type in the first access request, The step of determining the operating state of the interface based on the number of requests, A method for resetting a hardware unit in an integrated circuit according to feature 2.

4. The step of determining the coordination policy for two or more data channels between the first hardware unit and the second hardware unit based on the operating state of the interface is as follows: The steps include determining a first data channel and a second data channel from two or more data channels based on the operating state of the interface, The step includes determining the adjustment policy corresponding to the first data channel and the second data channel, respectively. A method for resetting a hardware unit in an integrated circuit according to feature 1.

5. The step of determining the first data channel and the second data channel from two or more data channels based on the operating state of the interface is as follows: In response to the operating state of the interface being a second preset state, the steps include determining the operation type corresponding to the first access request, The process includes the step of determining the first data channel and the second data channel from two or more data channels based on the operation type, A method for resetting a hardware unit in an integrated circuit according to feature 4.

6. The step of determining the first data channel and the second data channel from two or more data channels based on the operation type is: In response to the operation type being a write operation type, the steps include determining the relative size of the number of instruction write requests and the number of data write requests among the first access requests, The step of determining the first data channel and the second data channel from two or more data channels based on the aforementioned magnitude relationship, A method for resetting a hardware unit in an integrated circuit according to feature 5.

7. The step of determining the first data channel and the second data channel from two or more data channels based on the operating state of the interface is as follows: The step of determining all of two or more data channels as the first data channel in response to the operating state of the interface being a third preset state, A method for resetting a hardware unit in an integrated circuit according to feature 4.

8. The step of resetting the first hardware unit based on the operating state of the interface after the traffic control state of the data channel has been adjusted is as follows: The steps include reading a first duration from the register, Within the first duration, the steps include determining the matching relationship between the operating state of the interface after the traffic control state of the data channel has been adjusted and the third preset state, The step of resetting the first hardware unit based on the matching relationship is included, A method for resetting a hardware unit in an integrated circuit according to feature 1.

9. The step of resetting the first hardware unit based on the matching relationship is as follows: The steps include processing the logical state of the interface to a preset logical state based on the matching relationship indicating that the operating state of the interface after the traffic control state of the data channel has been adjusted matches the third preset state, The procedure includes the step of resetting the first hardware unit, A method for resetting a hardware unit in an integrated circuit according to feature 8.

10. A first hardware unit corresponding to a first operating system, A second hardware unit corresponding to a second operating system, A reset security module corresponding to the first hardware unit, The system comprises a register storing the state of a reset signal for requesting a reset of the first hardware unit, The aforementioned reset security module is The state of the reset signal is read from the register. Based on the state of the reset signal, the operating state of the interface between the first hardware unit and the bus is determined. Based on the operating state of the interface, the coordination policy for two or more data channels between the first hardware unit and the second hardware unit is determined. Based on the aforementioned adjustment policy, the traffic control state of the data channel is adjusted, and the traffic control state of the data channel includes release and blocking. Based on the operating state of the interface after the traffic control state of the data channel has been adjusted, the first hardware unit is reset. An integrated circuit characterized by the following features.

11. A computer program for performing a method for resetting a hardware unit in an integrated circuit according to any one of claims 1 to 9 is stored. A computer-readable storage medium characterized by the following features.

12. An electronic device comprising a processor and a memory for storing commands that the processor can execute, The processor performs a method for resetting a hardware unit in an integrated circuit according to any one of claims 1 to 9 by reading and executing the executable command from the memory. An electronic device characterized by the following features.

13. It is an electronic device, The integrated circuit according to claim 10 An electronic device characterized by the following features.

Images