Reference voltage generation circuit and electronic equipment

Abstract

The present invention reduces the minimum operating voltage in a circuit for generating a constant reference voltage.　A PTAT current generation unit is provided with: a first current source and a second current source that are connected in parallel to one of a power supply voltage and a ground voltage; a pair of bipolar transistors connected in parallel to a current mirror circuit that includes the first current source and the second current source; and, a first resistor connected to the emitter of one of the pair of bipolar transistors. A CTAT current generation unit is provided with a third current source and a second resistor that are inserted in series between the power supply voltage and the ground voltage. The connection node of the third current source and the second resistor is connected in common to the respective gates of the pair of bipolar transistors. An output unit outputs a reference voltage that corresponds to an addition value of a PTAT current supplied by the first and second current sources and a CTAT current supplied by the third current source.

Description

[Technical Field]

[0001] This technology relates to a reference voltage generation circuit. More specifically, it relates to a bandgap reference type reference voltage generation circuit and electronic equipment. [Background technology]

[0002] Conventionally, bandgap reference methods have been used to generate a constant voltage independent of power supply voltage and temperature. These bandgap reference methods are classified into voltage-adding and current-adding types. Of these, the voltage-adding type adds the PTAT (Proportional to Absolute Temperature) voltage and the CTAT (Complementary to Absolute Temperature) voltage. On the other hand, the current-adding type adds the PTAT current and the CTAT current. For example, a current-adding type reference voltage generation circuit has been proposed that generates the CTAT current using a circuit in which a drain-grounded transistor (i.e., a source follower) and a resistor are connected in series with a current mirror circuit, without using an operational amplifier (see, for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Jun Yin, et al., A system-on-Chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In the conventional technology described above, the reduction in the number of operational amplifiers reduces the minimum operating voltage, minimizes offset variation, and reduces the circuit area compared to the case where operational amplifiers are used. However, it is difficult to further reduce the minimum operating voltage in the reference voltage generation circuit described above.

[0005] This technology was developed in light of these circumstances, and aims to reduce the minimum operating voltage in a circuit that generates a constant reference voltage. [Means for solving the problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a reference voltage generation circuit comprising: a PTAT (Proportional to Absolute Temperature) current generation unit comprising a first current source and a second current source connected in parallel to one of the power supply voltage and the ground voltage, a pair of bipolar transistors connected in parallel to a current mirror circuit including the first current source and the second current source, and a first resistor connected to the emitter of one of the pair of bipolar transistors; a CTAT (Complementary to Absolute Temperature) current generation unit comprising a third current source and a second resistor inserted in series between the power supply voltage and the ground voltage, the connection nodes of the third current source and the second resistor being commonly connected to the gates of the pair of bipolar transistors; and an output unit that outputs a reference voltage corresponding to the sum of the PTAT current supplied by the first current source and the second current source and the CTAT current supplied by the third current source. This results in a reduction in the minimum operating voltage of the reference voltage generation circuit.

[0007] Furthermore, in this first aspect, the output unit may include a fourth current source that duplicates and supplies the CTAT current, a fifth current source that duplicates and supplies the PTAT current, and a third resistor that is commonly connected to the fourth and fifth current sources. This results in the generation of a reference voltage whose value is obtained by multiplying the sum of the currents by the resistance value.

[0008] Furthermore, in this first aspect, the first current source, the second current source, the third current source, the fourth current source, and the fifth current source may be MOS (Metal Oxide Semiconductor) transistors. This results in the effect of adding the current supplied by the MOS transistors.

[0009] Furthermore, in this first aspect, the first current source, the second current source, the third current source, the fourth current source, and the fifth current source may be bipolar transistors. This results in the effect of adding the current supplied by the bipolar transistors.

[0010] Furthermore, in this first aspect, the first current source, the second current source, the third current source, the fourth current source, and the fifth current source may be connected in parallel to the power supply voltage. This results in the effect of adding up the currents flowing from the current sources.

[0011] Furthermore, in this first aspect, the first current source, the second current source, the third current source, the fourth current source, and the fifth current source may be connected in parallel to the ground voltage. This results in the summation of the currents flowing through the current sources.

[0012] Furthermore, in this first aspect, the output unit may further include a sixth current source that duplicates and supplies the PTAT current, and the third resistor may be connected in common to the fourth current source, the fifth current source, and the sixth current source. This results in the effect of canceling the base current.

[0013] Furthermore, in this first aspect, the output section may further include a fourth resistor inserted between the third resistor and the fifth current source, the fourth current source being connected to the connection nodes of the third and fourth resistors. This results in the cancellation of the base current.

[0014] Furthermore, in this first aspect, the system may further include a base current detection unit for detecting the base current of the pair of bipolar transistors. This results in the effect of canceling the base current.

[0015] Furthermore, in this first aspect, the base current detection unit may add the base current to the CTAT current supplied by the third current source. This results in the effect of canceling the base current.

[0016] Furthermore, in this first aspect, the base current detection unit may subtract the base current from the current flowing through the third resistor. This results in the effect of canceling the base current.

[0017] Furthermore, in this first aspect, the base current detection unit may correct the PTAT current using the base current and output it. This results in the implementation of a temperature detection circuit and the like.

[0018] Furthermore, in this first aspect, the system may further include a replica circuit that generates the PTAT current and supplies it to the output unit, and the output unit may output a current obtained by adding the PTAT current supplied by the replica circuit to the CTAT current as a reference current, along with the reference voltage. This has the effect of preventing deterioration of stability when the output is expanded.

[0019] Furthermore, in this first aspect, the PTAT current generation unit may include a folded differential circuit. This results in a reduction in the minimum operating voltage.

[0020] Furthermore, in this first aspect, the circuit may further include a phase compensation capacitor inserted between the PTAT current generation unit and the connection node of the third current source and the second resistor, and the PTAT current generation unit may further include a pair of cascode-connected transistors, the connection node of the pair of transistors may be connected to the phase compensation capacitor. This has the effect of improving the stability of the circuit.

[0021] Furthermore, a second aspect of this technology is an electronic device comprising an integrated circuit, a PTAT (Proportional to Absolute Temperature) current generation unit comprising a first current source and a second current source connected in parallel to one of the power supply voltage and the ground voltage, a pair of bipolar transistors connected in parallel to a current mirror circuit including the first current source and the second current source, and a first resistor connected to the emitter of one of the pair of bipolar transistors, a CTAT (Complementary to Absolute Temperature) current generation unit comprising a third current source and a second resistor inserted in series between the power supply voltage and the ground voltage, the connection nodes of the third current source and the second resistor being commonly connected to the gates of the pair of bipolar transistors, and an output unit that outputs a reference voltage to the integrated circuit corresponding to the sum of the PTAT current supplied by the first current source and the second current source and the CTAT current supplied by the third current source. This results in a reduction in the minimum operating voltage of the reference voltage generation circuit within the electronic device. [Brief explanation of the drawing]

[0022] [Figure 1] This is a block diagram showing an example configuration of an electronic device in the first embodiment of this technology. [Figure 2] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in the first embodiment of this technology. [Figure 3] This is a circuit diagram showing a specific configuration example of a reference voltage generation circuit in the first embodiment of this technology. [Figure 4]This is a circuit diagram showing one example configuration of a reference voltage generation circuit in a comparative example. [Figure 5] This is an example of a graph showing the startup characteristics with respect to power supply voltage in the first embodiment of this technology and a comparative example. [Figure 6] This graph shows the Monte Carlo simulation results in the first embodiment of this technology. [Figure 7] This graph shows the Monte Carlo simulation results for the comparative example. [Figure 8] This figure shows the Monte Carlo simulation results for the first embodiment of this technology and a comparative example. [Figure 9] This graph shows an example of the power supply voltage dependence characteristics in the first embodiment of this technology. [Figure 10] This graph shows an example of the power supply voltage dependence characteristics in a comparative example. [Figure 11] This graph shows an example of the PSRR (Power Supply Rejection Ratio) characteristics at the same power supply voltage in the first embodiment of this technology and a comparative example. [Figure 12] This graph shows an example of the power supply voltage dependence characteristics of the PSRR characteristics in the low-frequency band in the first embodiment and comparative example of this technology. [Figure 13] This is a circuit diagram showing another example of the reference voltage generation circuit in the first embodiment of this technology. [Figure 14] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in a second embodiment of this technology. [Figure 15] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in a third embodiment of this technology. [Figure 16] This graph shows an example of the temperature-dependent characteristics in the third and first embodiments of this technology. [Figure 17] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in a modified example of the third embodiment of this technology. [Figure 18]This is a circuit diagram showing one example configuration of a reference voltage generation circuit in the fourth embodiment of this technology. [Figure 19] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in a modified version of the fourth embodiment of this technology. [Figure 20] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in the fifth embodiment of this technology. [Figure 21] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in the sixth embodiment of this technology. [Figure 22] This is a circuit diagram showing one example configuration of a reference voltage generation circuit in the seventh embodiment of this technology. [Modes for carrying out the invention]

[0023] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (Example of generating CTAT current using a current source and a resistor) 2. Second Embodiment (An example in which the current source is placed on the ground side and the CTAT current is generated by the current source and a resistor) 3. Third Embodiment (Example of canceling the base current and generating CTAT current using a current source and resistor) 4. Fourth Embodiment (An example in which the base current is detected and canceled, and the CTAT current is generated by a current source and a resistor) 5. Fifth Embodiment (An example of correcting the PTAT current and generating the CTAT current using a current source and a resistor) 6. Sixth Embodiment (Example of extending the output and generating CTAT current using a current source and resistor) 7. Seventh Embodiment (Example of reducing phase compensation capacitance and generating CTAT current using a current source and resistor)

[0024] <1. First Embodiment> [Example of electronic device configuration] Figure 1 is a block diagram showing an example configuration of an electronic device 100 in a first embodiment of the present technology. This electronic device 100 includes a reference voltage generation circuit 200 and an integrated circuit 110.

[0025] The reference voltage generation circuit 200 generates a constant voltage that is independent of the power supply voltage and temperature, which is the reference voltage V. BGR This is how it is generated. The reference voltage generation circuit 200 supplies the generated voltage to the integrated circuit 110 via the output signal line 209. The integrated circuit 110 receives the reference voltage V BGR It is driven by and performs predetermined processes such as arithmetic operations.

[0026] [Example of a reference voltage generation circuit configuration] Figure 2 is a circuit diagram showing one example configuration of a reference voltage generation circuit 200 in the first embodiment of this technology. This reference voltage generation circuit 200 comprises a PTAT current generation unit 300, a CTAT current generation unit 400, and an output unit 500.

[0027] The PTAT current generation unit 300 generates a PTAT current whose value changes in proportion to the absolute temperature, with a positive temperature coefficient. This PTAT current generation unit 300 comprises current sources 310 and 320, bipolar transistors 331 and 332, and a resistor 301.

[0028] The CTAT current generation unit 400 generates a CTAT current whose value changes in proportion to the absolute temperature, with a negative temperature coefficient. This CTAT current generation unit 400 includes a current source 430 and a resistor 402.

[0029] The output unit 500 outputs a voltage corresponding to the sum of the PTAT current and CTAT current to the reference voltage V BGR This outputs a current. The output unit 500 includes current sources 540 and 550 and a resistor 503.

[0030] In the PTAT current generation unit 300, current sources 310 and 320 are connected in parallel to either the power supply voltage VDD or the ground voltage VSS. In the configuration illustrated in the figure, current sources 310 and 320 are connected in parallel to the power supply voltage VDD. Furthermore, current sources 310, 320 and 550 constitute a current mirror circuit with current source 310 as the reference source. In the figure, the circuit enclosed by the dashed line represents the current mirror circuit.

[0031] Bipolar transistors 331 and 332 differ in size and are connected in parallel to a current mirror circuit that includes current sources 310 and 320. For example, the area of ​​bipolar transistor 332 is N (where N is an integer) times that of bipolar transistor 331. For example, NPN type bipolar transistors are used for bipolar transistors 331 and 332, and their bases are connected to each other. One end of resistor 301 is connected to the emitter of bipolar transistor 332. The emitter of bipolar transistor 331 and the other end of resistor 301 are connected to the ground voltage VSS.

[0032] Furthermore, in the CTAT current generation unit 400, the current source 430 and the resistor 402 are inserted in series between the power supply voltage VDD and the ground voltage VSS. The connection nodes of the current source 430 and the resistor 402 are also connected in common to the bases of the bipolar transistors 331 and 332. In addition, the current sources 430 and 540 constitute a current mirror circuit with the current source 430 as the reference source.

[0033] Furthermore, in the output section 500, current sources 540 and 550 are connected in parallel to one of the power supply voltage VDD and the ground voltage VSS (in this figure, the power supply voltage VDD). One end of the resistor 503 is connected to the current sources 540 and 550 in common, and the other end is connected to the ground voltage VSS. The voltage at the connection node between the current sources 540 and 550 and the resistor 503 is the reference voltage VSS. BGR It will be output as follows.

[0034] Note that current sources 310, 320, 430, 540 and 550 are examples of the first current source, the second current source, the third current source, the fourth current source and the fifth current source described in the claims. Further, resistors 301, 402 and 503 are examples of the first resistor, the second resistor and the third resistor described in the claims.

[0035] FIG. 3 is a circuit diagram showing a specific configuration example of the reference voltage generation circuit 200 according to the first embodiment of the present technology. As the current sources 310, 320, 430, 540 and 550, for example, p-channel Metal Oxide Semiconductor (pMOS) transistors 311, 321, 431, 541 and 551 are used. The sizes of the pMOS transistors 311, 321 and 551 constituting the current mirror circuit are the same, and the mirror ratio is assumed to be 1 time. Further, the sizes of the pMOS transistors 431 and 541 constituting the current mirror circuit are the same, and the mirror ratio is assumed to be 1 time. Note that the pMOS transistors 311, 321, 431, 540 and 551 are examples of the Metal Oxide Semiconductor (MOS) transistor described in the claims.

[0036] The gate of the pMOS transistor 311 is connected to its own drain and the gate of the pMOS transistor 321. The gate of the pMOS transistor 431 is connected to the collector of the bipolar transistor 332. The gate of the pMOS transistor 541 is connected to the gate of the pMOS transistor 431. The gate of the pMOS transistor 551 is connected to the gate of the pMOS transistor 311.

[0037] As described above, since the emitter areas of the bipolar transistors 331 and 332 are different, a difference occurs in their base-emitter voltages. This difference voltage ΔV be is expressed, for example, by the following equation. ΔV be =V be1 -V be2 =V T ln(N) =(kT / q)ln(N) ···Equation 1 In the above equation, V be1 and V be2 V is the base-emitter voltage of bipolar transistors 331 and 332. T is the thermal voltage. The unit of these voltages is, for example, volts (V). k is the Boltzmann constant, and its unit is, for example, joules per kelvin (J / K). T is the absolute temperature, and its unit is, for example, kelvin (K). q is the elementary charge, and its unit is, for example, coulomb (C). ln() is a function that returns the natural logarithm.

[0038] Differential voltage ΔV be Therefore, the current flowing through resistor 301 is proportional to the absolute temperature according to Equation 1, and becomes the PTAT current. This PTAT current I PTAT0 It can be expressed by the following formula: I PTAT0 =ΔV be / R1...expression 2 In the above equation, the PTAT current I PTAT0 The unit of is, for example, amperes (A). R1 ​​is the resistance value of resistor 301, and its unit is, for example, ohms (Ω). The value obtained by dividing the right-hand side of the above equation by T (in other words, the temperature coefficient) is a positive value.

[0039] Here, in the figure, the current amplification factors of bipolar transistors 331 and 332 are assumed to be sufficiently large, and their base currents can be ignored. The above-mentioned PTAT current I PTAT0 This is duplicated and output from pMOS transistor 551.

[0040] Furthermore, in the CTAT current generation unit 400, the pMOS transistor 431 and the resistor 402 constitute a common-source amplifier. The output of this common-source amplifier is connected to the bases of bipolar transistors 331 and 332 in common, and the gate of the pMOS transistor 431 is connected to the collector of the bipolar transistor 332, forming a feedback circuit. In this case, negative feedback is established, and the base-emitter voltage V of the bipolar transistor 331 is applied to the resistor 402.be1 This base-emitter voltage V is applied. be1 Since the voltage is generally proportional to temperature with a negative temperature coefficient, the current flowing through resistor 402 due to this voltage is the CTAT current. This CTAT current I CTAT0 It can be expressed by the following formula: I CTAT0 =V be1 / R2...expression 3 In the above equation, the CTAT current I CTAT0 The unit of is, for example, amperes (A). R2 is the resistance value of resistor 402, and its unit is, for example, ohms (Ω). The value obtained by dividing the right-hand side of the above equation by T (in other words, the temperature coefficient) is a negative value.

[0041] The above-mentioned CTAT current I CTAT0 This is duplicated and output from the pMOS transistor 541. In the output section 500, the PTAT current I is passed through the resistor 503. PTAT0 and CTAT current I CTAT0 A current equal to the sum of the two values ​​flows. This current becomes independent of absolute temperature by making the positive and negative temperature coefficients approximately the same. Therefore, the voltage generated across resistor 503 by this current is equal to the reference voltage V BGR It is output as this reference voltage V. BGR Based on equations 2 and 3, it can be expressed by the following equation: V BGR =R3(I PTAT0 +I CTAT0 ) =R3{(ΔV be / R1)+(V be1 / R2)} ...Formula 4 In the above equation, the reference voltage V BGR The unit of is, for example, volts (V). R3 is the resistance value of resistor 503, and its unit is, for example, ohms (Ω). PTAT0 The positive temperature coefficient of and CTAT0 The negative temperature coefficient is set to be approximately the same by adjusting N, R1, and R2.

[0042] As illustrated in the figure, a source-grounded amplifier is provided within the CTAT current generation unit 400 to perform feedback control and CTAT current generation simultaneously, and the minimum operating voltage V MIN It can be expressed by the following formula: V MIN =V be1 +V dsp ...Formula 5 In the above equation, V dsp V represents the overdrive voltage applied between the drain and source of the pMOS transistor 431. MIN and V dsp The unit is, for example, the volt (V).

[0043] Base-emitter voltage V under specified voltage and temperature conditions be1 Let the voltage be 0.8 volts (V), and the overdrive voltage V dsp If we assume that is 0.4 volts (V), then from Equation 5, the minimum operating voltage V MIN This will be 1.2 volts (V).

[0044] Here, we consider a circuit in which a source follower and a resistor are connected in series in the CTAT current generation unit 400 as a comparative example.

[0045] Figure 4 is a circuit diagram showing one example configuration of a reference voltage generation circuit in a comparative example. In this comparative example, an nMOS transistor MN is further arranged within the CTAT current generation unit 400. Also, the pMOS transistor 321 serves as the reference source for the current mirror circuit. The gate of the pMOS transistor 431 is connected to its drain. The nMOS transistor MN is inserted between the pMOS transistor 431 and the resistor 402, and its gate is connected to the connection nodes of the pMOS transistor 311 and the bipolar transistor 331. With this connection configuration, the nMOS transistor MN constitutes a source follower. The circuit in the figure is a simplified version of the circuit in Fig. 5 of Non-Patent Document 1.

[0046] Neither the first embodiment nor the comparative example uses an operational amplifier. Therefore, the minimum operating voltage can be lowered compared to the case where an operational amplifier is used. Furthermore, in both the first embodiment and the comparative example, it is not necessary to consider the offset variation of the operational amplifier, and the circuit area can be reduced compared to the case where an operational amplifier is used. However, in the comparative example in which a source follower is provided in the CTAT current generation unit 400, the minimum operating voltage V MIN It can be expressed by the following formula: V MIN =V be1 +V dsp +V gsn ...Formula 6 In the above equation, V gsn This indicates the threshold voltage applied between the gate and source of an nMOS transistor MN.

[0047] From Equations 5 and 6, in the first embodiment in which a common-source amplifier is provided within the CTAT current generation unit 400, the minimum operating voltage is lower than in the comparative example in which a source follower is provided within the CTAT current generation unit 400.

[0048] Figure 5 is an example of a graph showing the startup characteristics with respect to the power supply voltage VDD in the first embodiment of this technology and a comparative example. The vertical axis in the figure represents the reference voltage VDD. BGR The graph shows the power supply voltage VDD on the horizontal axis. The solid line curve shows the startup characteristics of the first embodiment, and the dotted line shows the startup characteristics of the comparative example.

[0049] As illustrated in the figure, the comparative example uses a source follower, resulting in a higher minimum operating voltage than the first embodiment. For example, the comparative example requires a minimum operating voltage of approximately 1.8 volts (V), while the first embodiment only requires approximately 1.2 volts (V).

[0050] Figure 6 is a graph showing the Monte Carlo simulation results in the first embodiment of this technology. In the figure, 'a' shows the temperature-dependent characteristics obtained by Monte Carlo simulation when the power supply voltage is 3 volts (V) in the first embodiment. 'b' in the figure shows the reference voltage V at a temperature of 27°C. BGR The histogram is shown below.

[0051] Figure 7 is a graph showing the Monte Carlo simulation results in the comparative example.

[0052] Figure 8 summarizes the results from Figures 6 and 7. In this figure, "MIN" and "MAX" indicate the minimum and maximum values ​​of the reference voltage. "AVE" and "SD" indicate the average and standard deviation of the reference voltage.

[0053] As shown in Figures 5 to 8, the MIN, MAX, AVE, SD, and σ / μ values ​​are equivalent between the first embodiment and the comparative example. However, the first embodiment has a minimum operating voltage of 1.2 volts, which is lower than the comparative example's minimum operating voltage of 1.8 volts.

[0054] Figure 9 is a graph showing an example of the power supply voltage dependence characteristics in the first embodiment of this technology. In the figure, 'a' represents the power supply voltage dependence characteristics. The vertical axis of 'a' in the figure is the reference voltage V BGR The figure shows the power supply voltage VDD on the horizontal axis. The thin solid line shows the temperature-dependent characteristics under the ff condition where the thresholds of pMOS and nMOS are low. The thick solid line shows the temperature-dependent characteristics under the ss condition where the thresholds of pMOS and nMOS are high. The dashed line shows the tt condition where the thresholds of pMOS and nMOS are intermediate. In the figure, b shows the line sensitivity LS to the power supply line in the range from the minimum operating voltage to 3 volts (V).

[0055] Figure 10 is a graph showing an example of the power supply voltage dependence characteristics in a comparative example.

[0056] As illustrated in Figures 9 and 10, the first embodiment allows for lower minimum operating voltages under the ss, ff, and tt conditions compared to the comparative example. Furthermore, the dependence of the first embodiment on the DC power supply voltage is significantly improved compared to the comparative example.

[0057] Figure 11 is a graph showing an example of PSRR characteristics at the same power supply voltage for the first embodiment of this technology and a comparative example. Figure a shows an example of PSRR characteristics when a capacitance of 50 picofarads (pF) is added to the reference voltage generation circuit. Figure b shows an example of PSRR characteristics when a resistor of 100 kilohms (kΩ) and a low-pass filter are added to the reference voltage generation circuit. In Figures a and b, the vertical axis represents PSRR, and the horizontal axis represents frequency. The solid curve represents the characteristics of the first embodiment, and the dotted line represents the characteristics of the comparative example.

[0058] As illustrated in the figure, in the first embodiment, by making the amplifier a common-source type, a higher gain can be obtained from a lower power supply voltage, resulting in a lower PSRR in the low-frequency band and better characteristics than the comparative example. On the other hand, while it has a high gain, in the high-frequency band, the deterioration of the PSRR characteristics starts at a lower frequency than in the comparative example, so this can be avoided by measures such as installing a low-pass filter.

[0059] Figure 12 is a graph showing an example of the power supply voltage dependence characteristics of the PSRR characteristics in the low-frequency band for the first embodiment of this technology and a comparative example. The vertical axis of the figure represents PSRR, and the horizontal axis represents the power supply voltage VDD. As illustrated in the figure, the PSRR is lower in the first embodiment than in the comparative example.

[0060] Although pMOS transistors are used as current sources such as current source 310, PNP type bipolar transistors can also be used, as illustrated in Figure 13. In this case, bipolar transistors 312, 322, 432, 542, and 552 are used instead of pMOS transistors 311, 321, 431, 541, and 551.

[0061] Thus, according to the first embodiment of this technology, since the CTAT current is generated by the source-grounded pMOS transistor 431 and resistor 402, the minimum operating voltage can be reduced compared to the case where a source follower is used.

[0062] <2. Second Embodiment> In the first embodiment described above, the pMOS transistors 311, 321, 431, 541, and 551 used as current sources were connected to the power supply voltage VDD, but they can also be connected to the ground voltage VSS. The reference voltage generation circuit 200 of this second embodiment differs from the first embodiment in that the current sources are placed on the ground side.

[0063] Figure 14 is a circuit diagram showing one example configuration of a reference voltage generation circuit 200 in a second embodiment of this technology. In this second embodiment of the reference voltage generation circuit 200, nMOS transistors 313, 323, 433, 543, and 553 are used instead of pMOS transistors 311, 321, 431, 541, and 551, and these are placed on the ground side. Also, PNP bipolar transistors 333 and 334 are used instead of NPN bipolar transistors 331 and 332. Reference voltage V BGR R3(I PTAT0 +I CTAT0 This is the value obtained by subtracting ).

[0064] Thus, according to the second embodiment of this technology, the current sources of nMOS transistors 313, 323, 433, 543 and 553 are placed on the ground side, so that the power supply voltage VDD is R3(I PTAT0 +I CTAT0 It can supply a reference voltage that is the value obtained by subtracting ).

[0065] <3. Third Embodiment> In the first embodiment described above, the base current was assumed to be negligible. However, in recent miniaturized CMOS (Complementary MOS) processes, parasitic bipolar transistors with well coupling are often used, which reduces the current amplification factor and can make it impossible to ignore the effect of the base current. The reference voltage generation circuit 200 of this third embodiment differs from the first embodiment in that it cancels the base current by adding a current source.

[0066] Figure 15 is a circuit diagram showing one example configuration of the reference voltage generation circuit 200 in the third embodiment of this technology. The reference voltage generation circuit 200 in this third embodiment differs from the first embodiment in that a pMOS transistor 561 is further arranged in the output section 500.

[0067] The pMOS transistor 561 is connected in parallel with pMOS transistors 541 and 551 between the power supply voltage VDD and resistor 503. The size of pMOS transistor 561 is the same as that of pMOS transistors 311, 321, and 551. The gate of pMOS transistor 561 is connected to the gate of pMOS transistor 311. Note that pMOS transistor 561 is an example of the sixth current source described in the claims.

[0068] In the PTAT current generation unit 300, if the current amplification factor for bipolar transistors 331 and 332 is β, then the collector current is equal to the base current I b It is β times. When the base currents of bipolar transistors 331 and 332 are approximately the same, the current flowing through resistor 301 is I PTAT0 Therefore, the collector currents I of bipolar transistors 331 and 332 are... PTAT1 It can be expressed by the following formula: I PTAT1 =β×I b =I PTAT0 ―I b ...Formula 7

[0069] Next, in the CTAT current generation unit 400, a current obtained by adding the respective base currents of bipolar transistors 331 and 332 flows. For this reason, when the current supplied by the pMOS transistor is I CTAT1 , and the current flowing through resistor 402 is I CTAT0 , I CTAT1 is expressed by the following equation. I CTAT1 =I CTAT0 +2I b ···Equation 8

[0070] When these PTAT current I PTAT1 and CTAT current I CTAT1 are extracted at a mirror ratio of 1, in the case of the first embodiment without the pMOS transistor 561, the reference voltage V BGR is expressed by the following equation based on Equation 7 and Equation 8. V BGR =R3(I PTAT1 +I CTAT1 ) =R3(I PTAT0 +I CTAT0 +I b ) ···Equation 9

[0071] As exemplified in Equation 9, in the first embodiment, when the current amplification factor is small, the term of base current I b remains. For this reason, when the current amplification factor β increases or decreases due to process variations of the bipolar transistors 331 and 332, the absolute value and temperature dependency of the reference voltage V BGR will vary significantly.

[0072] Accordingly, in the third embodiment, a pMOS transistor 561 is added in parallel to double the mirror ratio. Thereby, the reference voltage V BGR of the third embodiment takes the value of the following equation. V BGR =R3(2×I PTAT1 +I CTAT1 ) =R3(2×I PTAT0 +I CTAT0 ) ···Equation 10

[0073] From Equation 10, the base current I b can be canceled. The temperature coefficient of I PTAT0 is set to 1 / 2 of the temperature coefficient of I CTAT0 .

[0074] Here, since there are two bipolar transistors connected to the output of the CTAT current generation unit 400, the mirror ratio of the PTAT current is set to twice. However, the mirror ratio is not limited to twice. The value of the mirror ratio may be set to an appropriate value according to the number of bipolar transistors.

[0075] As described above, in the third embodiment, compensation of the base current I b can be realized very simply and easily only by changing the mirror ratio of the current mirror circuit, and both lower voltage operation and smaller area can be achieved.

[0076] Figure 16 is a diagram for explaining the effects of the third embodiment of the present technology. In the figure, a is a graph showing the temperature dependence characteristic of the reference voltage V in the first embodiment when the base current remains. BGR In the figure, b is a graph showing the temperature dependence characteristic of the reference voltage V in the third embodiment. BGR The vertical axes of a and b in the figure are the reference voltage V BGR , and the horizontal axis is the absolute temperature. The thin solid line indicates the temperature dependence characteristic under the ss condition. The thick solid line indicates the temperature dependence characteristic under the ff condition. The one-dot chain line indicates the tt condition.

[0077] As exemplified by a and b in the figure, in the third embodiment, compared with the first embodiment, it is possible to reduce the variation in the absolute value of the reference voltage V BGR and the variation in the temperature dependence of the reference voltage V BGR against absolute process variations.

[0078] Note that the second embodiment can be applied to the third embodiment.

[0079] Thus, according to the third embodiment of this technology, the base current can be canceled by adding the pMOS transistor 561. As a result, the reference voltage V BGR This can reduce variations in the absolute value and temperature dependence of the value.

[0080] [Differentiation] In the third embodiment described above, the base current was canceled by adding a current source, but the base current can also be canceled by adding a resistor. The reference voltage generation circuit 200 in this modified version of the third embodiment differs from the third embodiment in that the base current is canceled by adding a resistor.

[0081] Figure 17 is a circuit diagram showing one example configuration of a reference voltage generation circuit 200 in a modified example of the third embodiment of this technology. This modified example of the reference voltage generation circuit 200 of the third embodiment differs from the third embodiment in that a resistor 504 is used instead of a pMOS transistor 561.

[0082] Resistor 504 is inserted between pMOS transistor 551 and resistor 503. Additionally, the connection nodes of resistors 503 and 504 are connected to pMOS transistor 541, and the voltage at the connection nodes of pMOS transistor 551 and resistor 504 is set to a reference voltage V BGR It will be output as follows.

[0083] If the resistance value of resistor 504 is R3 × α (where α is an integer), then the reference voltage V BGR It can be expressed by the following formula: V BGR =R3×(I PTAT1 +I CTAT1 ) + R3 × α × I PTAT1 =R3×(I PTAT0 +I CTAT0 +I b ) +R3×α×(I PTAT0 ―I b ) =R3×{(1+α)I PTAT0 +I CTAT0 )} +R3×(1-α)I b ...Equation 11

[0084] Based on Equation 11, the base current can be canceled by setting α to 1. PTAT0 The temperature coefficient is I CTAT0 The temperature coefficient is set to 1 / (1+α).

[0085] However, it should be noted that this method makes it difficult to implement a trimming function because it requires resistor 504 to have a predetermined resistance ratio α.

[0086] Furthermore, the second embodiment can be applied to a modified version of the third embodiment.

[0087] Thus, according to the modified third embodiment of this technology, the base current can be canceled because the resistor 504 is inserted between the pMOS transistor 551 and the resistor 503.

[0088] <4. Fourth Embodiment> In the first embodiment described above, the base current was assumed to be negligible. However, in recent miniaturized CMOS processes, the current amplification factor becomes small, and the effect of the base current can no longer be ignored. The reference voltage generation circuit 200 of this fourth embodiment differs from the first embodiment in that the base current is canceled by adding a circuit that detects the base current.

[0089] Figure 18 is a circuit diagram showing one example configuration of the reference voltage generation circuit 200 in the fourth embodiment of this technology. The reference voltage generation circuit 200 of this fourth embodiment differs from the first embodiment in that it further includes a base current detection unit 610.

[0090] The base current detection unit 610 detects the base current and corrects the CTAT current based on that base current. This base current detection unit 610 comprises pMOS transistors 611 to 613, an nMOS transistor 614, and a bipolar transistor 615.

[0091] The pMOS transistors 611 through 613 are connected in parallel to the power supply voltage VDD. The drain of pMOS transistor 611 is connected to the connection node of pMOS transistor 431 and resistor 402. The gate of pMOS transistor 612 is connected to its own drain and to the gate of pMOS transistor 611.

[0092] The nMOS transistor 614 is inserted between the pMOS transistor 612 and the base of the bipolar transistor 615. The bipolar transistor 615 is inserted between the pMOS transistor 613 and the ground voltage VSS. The gate of the nMOS transistor 614 is connected to the connection node of the pMOS transistor 613 and the bipolar transistor 615.

[0093] pMOS transistors 611 and 612 form a current mirror circuit with pMOS transistor 612 as the reference, and the mirror ratio is set to 1. pMOS transistor 611 controls the base current I of pMOS transistor 612. b This is duplicated and supplied to the CTAT current generation unit 400. This base current Ib is the CTAT current I supplied by the pMOS transistor 431. CTAT2 It is added to. Based on Equation 8, I CTAT2 It can be expressed by the following formula: I CTAT2 =I CTAT1 -I b =I CTAT0 +I b ...Formula 12

[0094] Furthermore, pMOS transistors 613 and 311 form a current mirror circuit with pMOS transistor 311 as the reference, and the mirror ratio is 1. pMOS transistor 613 receives I from pMOS transistor 311. PTAT1 This is duplicated and supplied to the bipolar transistor 615.

[0095] The output unit 500 outputs the PTAT current I PTAT1 and CTAT current I CTAT2 Add this to the reference voltage V. BGR This is expressed by the following equation based on equations 7 and 12. V BGR =R3(I PTAT1 +I CTAT2 ) =R3(I PTAT0 +I CTAT0 )...Equation 13

[0096] From Equation 13, the base current can be canceled.

[0097] In the circuit shown in the figure, the stacking of bipolar transistor 615 and nMOS transistor 614 may increase the minimum operating voltage. However, this problem can be mitigated by using the nMOS transistor 614, which has a low threshold voltage.

[0098] Furthermore, the second embodiment can be applied to the fourth embodiment.

[0099] Thus, according to the fourth embodiment of this technology, the base current detection unit 610 detects the base current and corrects the CTAT current, so the base current can be canceled.

[0100] [Differentiation] In the fourth embodiment described above, the CTAT current I CTAT2 Base current I b Although it was being added, the base current I was calculated from the current flowing through resistor 503. bIt is also possible to subtract. In this modified fourth embodiment, the reference voltage generation circuit 200 subtracts the base current I from the current flowing through the resistor 503. b This differs from the fourth embodiment in that it subtracts [a certain value].

[0101] Figure 19 is a circuit diagram showing one example configuration of a reference voltage generation circuit 200 in a modified version of the fourth embodiment of this technology. This modified version of the reference voltage generation circuit 200 of the fourth embodiment differs from the fourth embodiment in that nMOS transistors 616 and 617 are further provided in the base current detection unit 610. Furthermore, the pMOS transistor 611 in this modified version of the fourth embodiment differs from the fourth embodiment in that it is not connected to the CTAT current generation unit 400.

[0102] The nMOS transistor 616 is inserted between the pMOS transistor 611 and the ground voltage VSS. The gate of the nMOS transistor 616 is connected to its drain and to the gate of the nMOS transistor 617. The nMOS transistor 617 is inserted between the connection node of the pMOS transistor 541 and resistor 503 and the ground voltage VSS.

[0103] nMOS transistors 616 and 617 form a current mirror circuit with nMOS transistor 616 as the reference, and the mirror ratio is set to 1. The base current I supplied by pMOS transistor 611 b This is replicated by the nMOS transistor 617. Since this nMOS transistor 617 is connected to the connection node of the pMOS transistor 541 and resistor 503, the base current I is derived from the current flowing through resistor 503. b This base current I is subtracted. b Subtracting from the reference voltage V BGR The value is expressed by the following formula. V BGR =R3(I PTAT1 +I CTAT1 -I b ) =R3(I PTAT0 +I CTAT0 )...Equation 14

[0104] According to Equation 14, the base current can be canceled.

[0105] Furthermore, the second embodiment can be applied to a modified version of the fourth embodiment.

[0106] Thus, according to the fourth embodiment of this technology, the base current detection unit 610 detects the base current and subtracts it from the current flowing through the resistor 503, thereby canceling the base current.

[0107] <5. Fifth Embodiment> In the fourth embodiment described above, the base current detection unit 610 corrected the base current remaining in the sum of the PTAT current and CTAT current in the output unit 500, but instead, it is also possible to correct the base current error portion with respect only to the PTAT current. The reference voltage generation circuit 200 in this fifth embodiment differs from the fourth embodiment in that the base current detection unit 610 corrects the PTAT current.

[0108] Figure 20 is a circuit diagram showing one example configuration of the reference voltage generation circuit 200 in the fifth embodiment of this technology. The reference voltage generation circuit 200 in this fifth embodiment differs from the fourth embodiment in that it further includes a pMOS transistor 618. Furthermore, the pMOS transistor 611 in the modified example of the fifth embodiment differs from the fourth embodiment in that it is not connected to the CTAT current generation unit 400.

[0109] The gate of pMOS transistor 311 is also connected to the gate of pMOS transistor 618, and the source of pMOS transistor 618 is connected to the power supply voltage VDD. In addition, the drain of pMOS transistor 618 is connected to the drain of pMOS transistor 611.

[0110] pMOS transistors 618 and 311 constitute a current mirror circuit with pMOS transistor 311 as the reference, and the mirror ratio is assumed to be 1. pMOS transistor 618 has a PTAT current I PTAT1 It duplicates and supplies. From the connection nodes of pMOS transistors 611 and 618, I PTAT1 Add the base current Ib (in other words, I PTAT1 to I b PTAT current I (corrected by) PTAT0 This PTAT current I is output externally. PTAT0 For example, it is used in circuits when mounting temperature detection circuits, such as temperature sensors, on the same semiconductor integrated circuit.

[0111] Furthermore, pMOS transistors 311 and 551 constitute a current mirror circuit with pMOS transistor 311 as the reference, and the Miller ratio is set to 2. By changing the Miller ratio, the base current is canceled, similar to the third embodiment.

[0112] Furthermore, the second embodiment can be applied to the fifth embodiment.

[0113] Thus, according to the fifth embodiment of this technology, the base current detection unit 610 detects the PTAT current I PTAT1 Because the output is corrected, the resulting current can be used to realize temperature detection circuits and other similar devices.

[0114] <6. Sixth Embodiment> In the first embodiment described above, the output unit 500 has a reference voltage V BGR While it previously output a reference voltage, it can also output a reference current that is independent of absolute temperature. The reference voltage generation circuit 200 in this sixth embodiment differs from the sixth embodiment in that it further outputs a reference current.

[0115] Figure 21 is a circuit diagram showing one example configuration of a reference voltage generation circuit 200 in a sixth embodiment of this technology. The reference voltage generation circuit 200 of this sixth embodiment comprises a replica circuit 620, a phase compensation capacitor 630, and pMOS transistors 561 and 571. The replica circuit 620 comprises a pMOS transistor 621 and a bipolar transistor 622.

[0116] The replica circuit 620 uses a circuit equivalent to the pMOS transistor 311 and the bipolar transistor 331 to generate the PTAT current I PTAT1 This generates the following. The pMOS transistor 621 and bipolar transistor 622 in the replica circuit 620 are connected in series between the power supply voltage VDD and the ground voltage VSS. The base of bipolar transistor 622 is connected to the base of bipolar transistor 331. The drain of pMOS transistor 621 is connected to its own gate and to the gate of pMOS transistor 571.

[0117] Furthermore, in the output section 500, pMOS transistors 561 and 571 are connected in parallel to the power supply voltage VDD. The gate of pMOS transistor 561 is connected to the gate of pMOS transistor 431. The drains of pMOS transistors 561 and 571 are connected, and the sum of the PTAT current and CTAT current is supplied from these connection nodes to the reference current I. BGR It will be output as follows.

[0118] The phase compensation capacitor 630 is inserted between the gate of the pMOS transistor 431 and the power supply voltage VDD.

[0119] Furthermore, since base current also flows through the bipolar transistor 622, the CTAT current I generated by the CTAT current generation unit 400 CTAT3 It can be expressed by the following formula: I CTAT3 =I CTAT0 +3I b ...Formula 15

[0120] To cancel the base current in Equation 15, the Miller ratio of the current mirror circuit, which includes pMOS transistors 311 and 551, is set to 3. Therefore, the reference voltage V BGR The value is expressed by the following formula. V BGR =R3(3I PTAT1 +I CTAT3 ) =R3(3I PTAT0 +I CTAT0 )...Equation 16 In the above equation, I PTAT0 The temperature coefficient is I CTAT0 It is set to 1 / 3 of the temperature coefficient.

[0121] When expanding the output, instead of providing the replica circuit 620 as shown in the figure, another method is to draw signal lines from nodes 701 and 702 in the current mirror circuit and add pMOS transistors to the output section 500. Here, node 701 is the gate and drain of pMOS transistor 311, and node 702 is the gate of pMOS transistor 431.

[0122] However, in the reference voltage generation circuit 200, the PTAT current generation unit 300 and the CTAT current generation unit 400 are operated as two-stage operational amplifiers, and a phase compensation capacitor 630 is connected to node 702, which is the input to the CTAT current generation unit 400, to form the primary pole. In addition, node 701 of the PTAT current generation unit 300 becomes the node that forms the secondary pole frequency.

[0123] Therefore, without the replica circuit 620, expanding the output would require adding a gate connection to node 701, resulting in a heavy capacitive load that affects circuit stability. This can be addressed by increasing the capacitance value of the phase compensation capacitor 630 at node 702, thereby reducing the bandwidth, but this has a significant impact on the circuit area. This is the trade-off for achieving low-voltage operation, but it can be easily avoided by adding the replica circuit 620, as illustrated in the figure.

[0124] In the diagram, a signal line is drawn from node 704 of the gate of bipolar transistor 331, and a bipolar transistor 622 is added that references bipolar transistor 331. Furthermore, a replica circuit 620 is used to draw the PTAT current, and the gate voltage for PTAT current expansion is taken from node 703 of the gate of pMOS transistor 621.

[0125] In this configuration, the impedance of node 704 is the input resistance of the base of bipolar transistor 331 and the parallel of resistor 402, and since its value is relatively low, its impact on stability is minimal.

[0126] Furthermore, the second embodiment can be applied to the sixth embodiment. Also, a modified version of the third embodiment can be applied. In this case, either a resistor 504 can be inserted between the resistor 503 and the pMOS transistor 551, or the resistor 503 can be divided. Additionally, the fourth and fifth embodiments can be applied to the sixth embodiment.

[0127] Furthermore, although the figure shows the phase compensation capacitor 630 inserted between node 702 and the power supply voltage VDD, Miller compensation may also be used, where one of the two phase compensation capacitors is connected to node 702 and the other to node 704. Miller compensation can reduce the capacitance value of the phase compensation capacitor. However, it should be noted that this will result in sacrificing the PSRR characteristics.

[0128] Thus, according to the sixth embodiment of this technology, since a replica circuit 620 is provided, the stability of the circuit can be improved when expanding the output.

[0129] <7. Seventh Embodiment> In the first embodiment described above, the reference voltage VBGR was generated without using a phase compensation capacitor, but this configuration may lead to circuit instability. The reference voltage generation circuit 200 in this seventh embodiment differs from the first embodiment in that a phase compensation capacitor is added.

[0130] Figure 22 is a circuit diagram showing one example configuration of a reference voltage generation circuit 200 in the seventh embodiment of this technology. The reference voltage generation circuit 200 of this seventh embodiment further comprises pMOS transistors 341 and 351, nMOS transistors 361, 371, 381 and 391, a resistor 641 and a phase compensation capacitor 642.

[0131] pMOS transistors 341 and 351 are connected in parallel to the power supply voltage VDD. pMOS transistors 341 and 311 form a current mirror circuit with pMOS transistor 311 as the reference. pMOS transistors 351 and 321 form a current mirror circuit with pMOS transistor 321 as the reference.

[0132] nMOS transistors 361 and 381 are connected in series between pMOS transistor 341 and the ground voltage VSS. The connection nodes of pMOS transistor 341 and nMOS transistor 361 are connected to the CTAT current generation unit 400. nMOS transistors 371 and 391 are connected in series between pMOS transistor 351 and the ground voltage VSS. In addition, the gate of nMOS transistor 371 is connected to its drain and to the gate of nMOS transistor 361. The gate of nMOS transistor 391 is connected to its drain and to the gate of nMOS transistor 381.

[0133] By adding pMOS transistors 341 and 351 and nMOS transistors 361, 371, 381, and 391, the PTAT current generation unit 300 forms a folded differential circuit.

[0134] The resistor 641 and the phase compensation capacitor 642 are connected in series between the connection nodes of the cascode-connected nMOS transistors 361 and 381 and the connection nodes of the pMOS transistor 431 and the resistor 402.

[0135] The connection nodes of the cascode-connected nMOS transistors 361 and 381 are potential-based on ground. The same applies to the connection nodes of the pMOS transistor 431 and resistor 402. By inserting a phase compensation capacitor 642 between these nodes, the capacitance value of the phase compensation capacitor 642 required for sufficient phase compensation can be reduced compared to inserting it elsewhere. Furthermore, immunity to power supply noise is improved, enabling both stability and maintenance of PSRR characteristics. However, this may lead to an increase or variation in the minimum operating voltage and potentially increased noise, so it is necessary to optimize the design by considering the trade-offs according to the design specifications.

[0136] Furthermore, each of the second to sixth embodiments can be applied to the seventh embodiment.

[0137] Thus, according to the seventh embodiment of this technology, since a phase compensation capacitor 642 is inserted between nodes whose potential is determined relative to ground, the capacitance value required when performing phase compensation can be reduced.

[0138] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0139] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0140] Furthermore, this technology can also be configured as follows. (1) A PTAT (Proportional to Absolute Temperature) current generation unit comprising: a first current source and a second current source connected in parallel to one of the power supply voltage and the ground voltage; a pair of bipolar transistors connected in parallel to a current mirror circuit including the first current source and the second current source; and a first resistor connected to the emitter of one of the pair of bipolar transistors. A CTAT (Complementary to Absolute Temperature) current generation unit comprising a third current source and a second resistor inserted in series between the power supply voltage and the ground voltage, wherein the connection nodes of the third current source and the second resistor are commonly connected to the gates of the pair of bipolar transistors, An output unit that outputs a reference voltage corresponding to the sum of the PTAT current supplied by the first current source and the second current source and the CTAT current supplied by the third current source. A reference voltage generating circuit equipped with the following features. (2) The output unit is, A fourth current source that replicates and supplies the aforementioned CTAT current, A fifth current source that replicates and supplies the aforementioned PTAT current, The third resistor, which is connected in common to the fourth current source and the fifth current source, The reference voltage generating circuit described in (1) above, comprising the above. (3) The first current source, the second current source, the third current source, the fourth current source and the fifth current source are MOS (Metal Oxide Semiconductor) transistors. The reference voltage generation circuit described in (2) above. (4) The first current source, the second current source, the third current source, the fourth current source and the fifth current source are bipolar transistors. The reference voltage generation circuit described in (2) above. (5) The first current source, the second current source, the third current source, the fourth current source and the fifth current source are connected in parallel to the power supply voltage. A reference voltage generating circuit as described in any of (2) to (4) above. (6) The first current source, the second current source, the third current source, the fourth current source and the fifth current source are connected in parallel to the ground voltage. A reference voltage generating circuit as described in any of (2) to (4) above. (7) The output unit further comprises a sixth current source that replicates and supplies the PTAT current, The third resistor is connected in common to the fourth current source, the fifth current source, and the sixth current source. A reference voltage generating circuit as described in any of (2) to (6) above. (8) The output section further includes a fourth resistor inserted between the third resistor and the fifth current source, The fourth current source is connected to the connection nodes of the third and fourth resistors. A reference voltage generating circuit as described in any of (2) to (6) above. (9) Further comprising a base current detection unit for detecting the base current of the pair of bipolar transistors A reference voltage generating circuit as described in any of (2) to (8) above. (10) The base current detection unit adds the base current to the CTAT current supplied by the third current source. The reference voltage generation circuit described in (9) above. (11) The base current detection unit subtracts the base current from the current flowing through the third resistor. The reference voltage generation circuit described in (9) above. (12) The base current detection unit corrects the PTAT current based on the base current and outputs it. The reference voltage generation circuit described in (9) above. (13) The device further comprises a replica circuit that generates the PTAT current and supplies it to the output unit, The output unit outputs a current obtained by adding the PTAT current supplied by the replica circuit to the CTAT current, using this current as the reference current, along with the reference voltage. A reference voltage generating circuit as described in any of (1) to (12) above. (14) The PTAT current generation unit includes a folded differential circuit A reference voltage generation circuit as described in any of (1) to (13) above. (15) The PTAT current generation unit further comprises a phase compensation capacitor inserted between the connection node of the third current source and the second resistor, The PTAT current generation unit further comprises a pair of cascode-connected transistors, The connection nodes of the pair of transistors are connected to the phase compensation capacitor. The reference voltage generation circuit described in (14) above. (16) Integrated circuits and, A PTAT (Proportional to Absolute Temperature) current generation unit comprising: a first current source and a second current source connected in parallel to either the power supply voltage or the ground voltage; a pair of bipolar transistors connected in parallel to a current mirror circuit including the first current source and the second current source; and a first resistor connected to the emitter of one of the pair of bipolar transistors; A CTAT (Complementary to Absolute Temperature) current generation unit includes a third current source and a second resistor inserted in series between the power supply voltage and the ground voltage, wherein the connection nodes of the third current source and the second resistor are commonly connected to the gates of the pair of bipolar transistors, An output unit that outputs a reference voltage to the integrated circuit corresponding to the sum of the PTAT current supplied by the first current source and the second current source and the CTAT current supplied by the third current source. An electronic device equipped with the following features. [Explanation of Symbols]

[0141] 100 Electronic equipment 110 Integrated Circuits 200 Reference voltage generation circuit 300 PTAT current generation section 301, 402, 503, 504, 641 resistors 310, 320, 430, 540, 550 current source 311, 321, 341, 351, 431, 541, 551, 561, 571, 611~613, 618, 621 pMOS transistors 312, 322, 331-334, 432, 542, 552, 615, 622 Bipolar Transistors 313, 323, 361, 371, 381, 391, 433, 543, 553, 614, 616, 617 nMOS transistors 400 CTAT current generation section 500 Output section 610 Base current detection unit 620 replica circuits 630, 642 Phase Compensation Capacitors

Claims

1. A PTAT (Proportional to Absolute Temperature) current generation unit comprising: a first current source and a second current source connected in parallel to one of the power supply voltage and the ground voltage; a pair of bipolar transistors connected in parallel to a current mirror circuit including the first current source and the second current source; and a first resistor connected to the emitter of one of the pair of bipolar transistors; A CTAT (Complementary to Absolute Temperature) current generation unit comprising a third current source and a second resistor inserted in series between the power supply voltage and the ground voltage, wherein the connection nodes of the third current source and the second resistor are commonly connected to the bases of the pair of bipolar transistors, An output unit that outputs a reference voltage corresponding to the sum of the PTAT current supplied by the first current source and the second current source and the CTAT current supplied by the third current source, A replica circuit that generates the PTAT current and supplies it to the output unit. It is equipped with, The output unit outputs a current obtained by adding the PTAT current supplied by the replica circuit to the CTAT current, using this current as the reference current, along with the reference voltage. The replica circuit comprises a replica-internal current source and a replica-internal bipolar transistor connected in series between the power supply voltage and the ground voltage. The base of the bipolar transistor in the replica is connected in common to the bases of each of the pair of bipolar transistors. The third current source and the second resistor constitute a source-grounded or emitter-grounded amplifier. The output of the amplifier is connected in common to the bases of each of the pair of bipolar transistors via the connection node. The input to the amplifier is connected to the collector of one of the pair of bipolar transistors. Reference voltage generation circuit.

2. The output unit is, A fourth current source that replicates and supplies the aforementioned CTAT current, A fifth current source that replicates and supplies the aforementioned PTAT current, The third resistor, which is connected in common to the fourth current source and the fifth current source, A reference voltage generating circuit according to claim 1, comprising:

3. The first current source, the second current source, the third current source, the fourth current source, and the fifth current source are MOS (Metal Oxide Semiconductor) transistors. The reference voltage generating circuit according to claim 2.

4. The first current source, the second current source, the third current source, the fourth current source, and the fifth current source are bipolar transistors. The reference voltage generating circuit according to claim 2.

5. The first current source, the second current source, the third current source, the fourth current source, and the fifth current source are connected in parallel to the power supply voltage. The reference voltage generating circuit according to claim 2.

6. The first current source, the second current source, the third current source, the fourth current source, and the fifth current source are connected in parallel to the ground voltage. The reference voltage generating circuit according to claim 2.

7. The output section further includes a fourth resistor inserted between the third resistor and the fifth current source, The fourth current source is connected to the connection node of the third resistor and the fourth resistor. The reference voltage generating circuit according to claim 2.

8. The output section further includes a fourth resistor inserted between the third resistor and the fifth current source, The fourth current source is connected to the connection node of the third resistor and the fourth resistor. The reference voltage generating circuit according to claim 2.

9. The system further comprises a base current detection unit for detecting the base current of the pair of bipolar transistors. The reference voltage generating circuit according to claim 2.

10. The base current detection unit adds the base current to the CTAT current supplied by the third current source. The reference voltage generating circuit according to claim 9.

11. The base current detection unit subtracts the base current from the current flowing through the third resistor. The reference voltage generating circuit according to claim 9.

12. The base current detection unit corrects the PTAT current based on the base current and outputs it. The reference voltage generating circuit according to claim 9.

13. The PTAT current generation unit includes a folded differential circuit. The reference voltage generation circuit according to claim 1.

14. The system further comprises a phase compensation capacitor inserted between the PTAT current generation unit and the connection node of the third current source and the second resistor, The PTAT current generation unit further comprises a pair of cascode-connected transistors, The connection nodes of the pair of transistors are connected to the phase compensation capacitor. The reference voltage generation circuit according to claim 1.

15. Integrated circuits and A PTAT (Proportional to Absolute Temperature) current generation unit comprising: a first current source and a second current source connected in parallel to one of the power supply voltage and the ground voltage; a pair of bipolar transistors connected in parallel to a current mirror circuit including the first current source and the second current source; and a first resistor connected to the emitter of one of the pair of bipolar transistors; A CTAT (Complementary to Absolute Temperature) current generation unit includes a third current source and a second resistor inserted in series between the power supply voltage and the ground voltage, wherein the connection nodes of the third current source and the second resistor are commonly connected to the bases of the pair of bipolar transistors, An output unit that outputs a reference voltage to the integrated circuit corresponding to the sum of the PTAT current supplied by the first current source and the second current source and the CTAT current supplied by the third current source, A replica circuit that generates the PTAT current and supplies it to the output unit. It is equipped with, The output unit outputs a current obtained by adding the PTAT current supplied by the replica circuit to the CTAT current, using this current as the reference current, along with the reference voltage. The replica circuit comprises a replica-internal current source and a replica-internal bipolar transistor connected in series between the power supply voltage and the ground voltage. The base of the bipolar transistor in the replica is connected in common to the bases of each of the pair of bipolar transistors. The third current source and the second resistor constitute a source-grounded or emitter-grounded amplifier. The output of the amplifier is connected in common to the bases of each of the pair of bipolar transistors via the connection node. The input to the amplifier is connected to the collector of one of the pair of bipolar transistors. electronic equipment.

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