Apparatus and method for controlling ion energy distribution

Abstract

To provide an apparatus and a method for controlling ion energy distribution during plasma processing.SOLUTION: An apparatus includes a substrate support including a substrate electrode that applies a substrate voltage to a substrate, a recessed edge ring electrode that applies an edge ring voltage to an edge ring, a substrate voltage control circuit coupled to the substrate electrode, and an edge ring voltage control circuit coupled to the edge ring electrode. The substrate electrode, the edge ring electrode, or both, are coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate, the edge ring, or both, to control the energy distribution function width of the ions during substrate processing.SELECTED DRAWING: Figure 5A

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to an apparatus and method for plasma processing a substrate, and specifically to an apparatus and method for controlling ion energy distribution during plasma processing.

BACKGROUND ART

[0002] During plasma processing of a substrate, ions play an important role in surface treatment, etching, and deposition of the substrate. Ions impinging on the substrate surface may have various energies, which are described by an ion energy distribution function (IEDF). Control over the IEDF can be an important factor in various substrate processing schemes. However, there are still challenges in controlling the IEDF. For example, when a periodically alternating voltage is applied to an electrode of a chamber, a plasma sheath may develop above the substrate. Ions flowing toward the substrate are accelerated by the plasma sheath voltage that correlates with the voltage applied to the electrode. At the same time, the ion current may charge the substrate and change the substrate potential, which in turn affects the plasma sheath voltage, and the IEDF at the substrate surface is also affected, for example, broadened. State-of-the-art methods for controlling the IEDF in such cases and others are based on inefficient iterative loops.

[0003] There is a need for new and improved methods to control the IEDF.

SUMMARY OF THE INVENTION

[0004] Embodiments of the present disclosure relate generally to an apparatus and method for plasma processing a substrate, and specifically to an apparatus and method for controlling ion energy distribution during plasma processing.

[0005] In one embodiment, a method for controlling the ion energy distribution function (IEDF) is provided. The method includes introducing a voltage to the electrodes of a processing chamber by activating a main pulser coupled to an IEDF width control module, and measuring the current of the IEDF width control module and the voltage or voltage derivative of the IEDF width control module. The method further includes calculating the ion current of the processing chamber and the capacity of the processing chamber based on the current and voltage or voltage derivative of the IEDF width control module. The method further includes determining a setpoint for the DC voltage of the main pulser, a setpoint for the voltage or voltage derivative of the IEDF width control module, or both, and controlling the width of the IEDF by adjusting the DC voltage of the main pulser, the voltage or voltage derivative of the IEDF width control module, or both, to the determined setpoints.

[0006] In another embodiment, a device for controlling ion energy distribution is provided. The device includes a substrate support having a main body having a substrate support portion in which substrate electrodes for applying a substrate voltage to a substrate are embedded. The main body further includes an edge ring portion disposed adjacent to the substrate support portion, in which an edge ring electrode for applying an edge ring voltage to the edge ring is embedded. The device further includes a substrate voltage control circuit coupled to the substrate electrodes and an edge ring voltage control circuit coupled to the edge ring electrodes. The substrate electrodes are coupled to a power module configured to actively control the energy distribution function width of ions reaching the substrate, or the edge ring electrodes are coupled to a power module configured to actively control the energy distribution function width of ions reaching the edge ring, or a combination thereof. The substrate voltage control circuit, the edge ring voltage control circuit, or both include a main pulser coupled to a current return path, the current return path is coupled to a power module and a processing chamber, and the power module includes a voltage source, a current source, or a combination thereof.

[0007] In another embodiment, a device for controlling ion energy distribution is provided. The device includes a substrate support having a main body having a substrate support portion in which substrate electrodes for applying a substrate voltage to a substrate are embedded. The main body further includes an edge ring portion disposed adjacent to the substrate support portion, in which an edge ring electrode for applying an edge ring voltage to the edge ring is embedded. The device further includes a substrate voltage control circuit coupled to the substrate electrodes and an edge ring voltage control circuit coupled to the edge ring electrodes. The substrate electrodes are coupled to a power module configured to actively control the energy distribution function width of ions reaching the substrate, or the edge ring electrodes are coupled to a power module configured to actively control the energy distribution function width of ions reaching the edge ring, or a combination thereof. The substrate voltage control circuit, the edge ring voltage control circuit, or both comprises a main pulser coupled to a power module, the power module is coupled to a processing chamber, and the power module comprises a voltage source, a current source, or a combination thereof.

[0008] In another embodiment, an apparatus for controlling ion energy distribution is provided. The apparatus includes a substrate support having a main body having a substrate support portion in which substrate electrodes for applying a substrate voltage to a substrate are embedded. The main body further includes an edge ring portion disposed adjacent to the substrate support portion, in which an edge ring electrode for applying an edge ring voltage to the edge ring is embedded. The apparatus further includes a substrate voltage control circuit coupled to the substrate electrodes and an edge ring voltage control circuit coupled to the edge ring electrodes. The substrate electrodes are coupled to a power module configured to actively control the energy distribution function width of ions reaching the substrate, or the edge ring electrodes are coupled to a power module configured to actively control the energy distribution function width of ions reaching the edge ring, or a combination thereof. The substrate voltage control circuit, the edge ring voltage control circuit, or both comprises a main pulser coupled to a power module, the power module is coupled to a processing chamber, the power module is in parallel with a substrate chucking and bias compensation module, and the power module comprises a voltage source, a current source, or a combination thereof.

[0009] The above-mentioned disclosure may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings, in a manner that allows for a more detailed understanding of the features of the disclosure listed above. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments of the disclosure and should not be considered to limit its scope, as the disclosure may permit other equally valid embodiments. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic cross-sectional view showing an example of a processing chamber according to at least one embodiment of the present disclosure. [Figure 2] This is a schematic diagram of an example of a processing chamber according to at least one embodiment of the present disclosure. [Figure 3A]This is an illustrative graph showing three different bias voltage waveforms on a substrate according to at least one embodiment of the present disclosure. [Figure 3B] This figure shows illustrative plots of IEDF vs. ion energy for three different bias voltage waveforms on the substrate shown in Figure 3A, according to at least one embodiment of the present disclosure. [Figure 4A] This is a schematic diagram of a circuit example according to at least one embodiment of the present disclosure. [Figure 4B] This is a schematic diagram of a circuit example according to at least one embodiment of the present disclosure. [Figure 4C] This is a schematic diagram of a circuit example according to at least one embodiment of the present disclosure. [Figure 4D] This is a schematic diagram of a circuit example according to at least one embodiment of the present disclosure. [Figure 5A] This is a schematic circuit diagram of an example showing an IEDF width control circuit for driving electrodes of a substrate support assembly, according to at least one embodiment of the present disclosure. [Figure 5B] This figure shows illustrative plots of the V2 voltage waveform and the substrate voltage waveform against an example schematic circuit diagram shown in Figure 5A, according to at least one embodiment of the present disclosure. [Figure 5C] This figure shows an example of a control circuit according to at least one embodiment of the present disclosure. [Figure 5D] This figure shows an example of a control circuit according to at least one embodiment of the present disclosure. [Figure 5E] This figure shows an exemplary sawtooth voltage output according to at least one embodiment of the present disclosure. [Figure 6A] This is a schematic circuit diagram of an example showing an IEDF width control circuit for driving electrodes of a substrate support assembly, according to at least one embodiment of the present disclosure. [Figure 6B] This figure shows an example of a control circuit according to at least one embodiment of the present disclosure. [Figure 6C] This figure shows an example of a control circuit according to at least one embodiment of the present disclosure. [Figure 7]1 is a schematic circuit diagram illustrating an example of an IEDF width control circuit for driving electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 8] 2 is a schematic circuit diagram illustrating an example of an IEDF width control circuit for driving electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 9] 3 is a schematic circuit diagram illustrating an example of an IEDF width control circuit for driving electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 10] 4 is a schematic circuit diagram illustrating an example of an IEDF width control circuit for driving electrodes of a substrate support assembly, in accordance with at least one embodiment of the present disclosure. [Figure 11] 5 is a flowchart illustrating a method for controlling an IEDF width, in accordance with at least one embodiment of the present disclosure. [Modes for Carrying Out the Invention]

[0011] To facilitate understanding, identical reference numerals are used, where possible, to designate identical elements that are common to the drawings. It is contemplated that elements and features of one embodiment may be beneficially utilized in other embodiments without further recitation.

[0012] Embodiments of the present disclosure relate generally to an apparatus and method for plasma processing a substrate, and specifically to an apparatus and method for controlling ion energy distribution during plasma processing. The methods and apparatus, such as circuits, described herein enable control over the shape (e.g., narrow or adjustable width) of the voltage waveform of a pulsed DC power supply. The embodiments described herein further enable control over an ion energy distribution function (IEDF) including, for example, single-energy ion acceleration.

[0013] IEDF is a parameter for etching high-aspect-ratio features. In general, a pulsed DC bias can provide a narrower IEDF compared to a sinusoidal RF bias through the following mechanism. Since ions are accelerated by an electric field with little temporal variation during the pulsed DC period, the energy acquired by the ions in the sheath also has less temporal variation than when the sinusoidal RF bias is varied. As a result, ions accelerated by the pulsed DC bias have a narrower IEDF than those under the sinusoidal RF bias. However, the ion current from the bulk plasma to the substrate distorts the voltage waveform at the substrate and broadens the ion energy distribution. The methods and apparatus described herein can, for example, compensate for this ion current and actively control the width of the ion energy distribution.

[0014] Conventional methods and apparatus use iterative control loops to control the width of the ion energy distribution. Before the control algorithm converges, estimates of plasma parameters (e.g., ion current, sheath thickness, and IEDF width) are inaccurate. Furthermore, controlling the width of the IEDF by using iterations is slow, and the control algorithm may not converge.

[0015] In contrast, the methods and apparatus described herein utilize a single non-iterative loop to determine the ion current and compensation current to achieve a given IEDF width. Thus, the methods and apparatus described herein reach a desired state of the IEDF, for example a narrow IEDF, faster than the state of the art. This is due, for example, to not using iterations when determining the solution for the compensation current.

[0016] In short, in some embodiments, the substrate support includes a body, which includes a substrate support portion and / or an edge ring portion. Substrate electrodes are embedded in the substrate support portion to apply a substrate voltage to the substrate. A substrate voltage control circuit is coupled to the substrate electrodes. The edge ring portion includes embedded edge ring electrodes that apply an edge ring voltage to the edge ring. An edge ring voltage control circuit is coupled to the edge ring electrodes. At least one shaped DC pulse source is coupled to the substrate voltage control circuit and / or the edge ring voltage control circuit. The substrate voltage circuit and / or edge ring voltage control circuit are adjustable. For example, the ion energy distribution is adjusted and controlled by adjusting the voltage amplitude via adjustment of the substrate voltage control circuit and / or edge ring voltage control circuit.

[0017] In some embodiments, the IEDF-width control circuit is coupled to a substrate support. The IEDF-width control circuit can be integrated within the main pulse DC power supply, as a separate module, or as a module integrated with a bias compensation module.

[0018] Example of a processing system configuration Figure 1 is a schematic cross-sectional view of a processing chamber 100 according to at least one embodiment of the present disclosure. The processing chamber 100 is configured to implement the scheme described herein. In this embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma-enhanced deposition chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber, a plasma-enhanced physical vapor deposition (PEPVD) chamber, or a plasma-enhanced atomic layer deposition (PEALD) chamber. In some other embodiments, the processing chamber is a plasma processing chamber, or a plasma-based ion embedding chamber, such as a plasma doping (PLAD) chamber.

[0019] The processing chamber 100 includes a chamber body 101 and a lid 102 disposed on top of it, both defining an internal volume 124. The chamber body 101 is generally coupled to electrical ground 103. A substrate support assembly 104 is disposed within the internal volume to support a substrate 105 on it during processing. An edge ring 106 is positioned on the substrate support assembly 104 and surrounds the substrate 105. The processing chamber 100 also includes an inductively coupled plasma device 107 that generates a plasma of reactive species within the processing chamber 100, and a controller 108 adapted to control the system and subsystems of the processing chamber 100. In some embodiments, the inductively coupled plasma device 107 can be replaced with a grounded showerhead, and RF power is delivered from electrodes located below the substrate to generate a capacitively coupled plasma.

[0020] The substrate support assembly 104 is disposed in the internal volume 124. The substrate support assembly 104 generally includes a substrate support 152. The substrate support 152 includes an electrostatic chuck 150 comprising a substrate support portion 154 configured to be placed under and support the substrate 105 to be processed, and an edge ring portion 156 configured to support the edge ring 106. The substrate support assembly 104 may further include a heater assembly 169. The substrate support assembly 104 may also include a cooling base 131. Alternatively, the cooling base 131 may be separate from the substrate support assembly 104. The substrate support assembly 104 may be removably coupled to a support pedestal 125. The support pedestal 125 is mounted on the chamber body 101. The support pedestal 125 may optionally include an equipment plate 180. The substrate support assembly 104 may be periodically detached from the support pedestal 125 to allow one or more components of the substrate support assembly 104 to be repaired or adjusted. As is conventionally known, lifting pins 146 are provided through a substrate support assembly 104 to facilitate substrate transfer.

[0021] The equipment plate 180 is configured to receive multiple fluid connections from the electrostatic chuck 150 and the cooling base 131. The equipment plate 180 is also configured to receive multiple electrical connections from the electrostatic chuck 150 and the heater assembly 169. The multiple electrical connections can pass outside or inside the substrate support assembly 104, and the equipment plate 180 provides an interface for connecting to each of their ends.

[0022] The substrate electrode 109 is embedded in the substrate support portion 154 of the electrostatic chuck 150 to apply a substrate voltage to the substrate 105 disposed on the upper surface 160 of the substrate support assembly 104. The edge ring electrode 111 is embedded in the edge ring portion 156 to apply an edge ring voltage to the edge ring 106. The edge ring IEDF width control circuit 155 is coupled to the edge ring electrode 111. The substrate IEDF width control circuit 158 ​​is coupled to the substrate electrode 109. In one embodiment, the first shaping DC pulse voltage source 159 is coupled to one or both of the edge ring IEDF width control circuit 155 and the substrate IEDF width control circuit 158. In another embodiment, as shown in Figure 1, the first shaping DC voltage source 159 is coupled to the edge ring IEDF width control circuit 155, and the second shaping DC voltage source 161 is coupled to the substrate IEDF width control circuit 158. The edge ring IEDF width control circuit 155 and the substrate IEDF width control circuit 158 ​​are independently adjustable. The substrate electrode 109 is further coupled to the chuck power supply 115 to facilitate chucking the substrate 105 to the top surface 160 by the electrostatic chuck 150 during processing.

[0023] The inductively coupled plasma apparatus 107 is positioned above the lid 102 and is configured to generate plasma 116 by dielectrically coupling RF power to the gas in the processing chamber 100. The inductively coupled plasma apparatus 107 includes a first coil 118 and a second coil 120 positioned above the lid 102. The relative position, diameter ratio, and / or number of turns of each coil 118, 120 can be adjusted as desired to control the profile or density of the plasma 116 that is formed. The first and second coils 118, 120 are each coupled to an RF power supply unit 121 via an RF power supply structure 123 and a matching network 122. The RF power supply unit 121 can, exemplary, generate up to approximately 4000W (but not limited to approximately 4000W) at an adjustable frequency in the range of 50kHz to 13.56MHz, but other frequencies and powers can be made available as desired for specific applications.

[0024] In some examples, a power distributor 126, such as a voltage divider capacitor, can be provided between the RF power supply structure 123 and the RF power supply device 121 to control the relative amount of RF power supplied to the first and second coils 118 and 120, respectively. In other embodiments, a capacitively coupled plasma device (not shown) can be used above the lid 102. A heater element 128 can be placed on top of the lid 102 to facilitate heating the inside of the processing chamber 100. The heater element 128 can be placed between the lid 102 and the first and second coils 118 and 120. In some examples, the heater element 128 is coupled to a power supply device 130, such as an AC power supply device, which includes a resistance heating element and is configured to provide sufficient energy to control the temperature of the heater element 128 within a desired range.

[0025] During operation, a substrate 105, such as a semiconductor substrate or another substrate suitable for plasma processing, is placed on a substrate support assembly 104. Substrate lifting pins 146 are movably disposed on the substrate support assembly 104 to assist in transferring the substrate 105 onto the substrate support assembly 104. After the substrate 105 is positioned, a processing gas is supplied from the gas panel 132 through the inlet port 134 into the internal volume 124 of the chamber body 101. The processing gas is ignited in the processing chamber 100 to form plasma 116 by applying power from the RF power supply unit 121 to the first and second coils 118, 120. The pressure in the internal volume 124 of the processing chamber 100 can be controlled using a valve 136 and a vacuum pump 138.

[0026] The processing chamber 100 includes a controller 108 that controls the operation of the processing chamber 100 during processing. The controller 108 comprises a central processing unit (CPU) 140, a memory 142, and support circuits 144 for the CPU 140, facilitating the control of the components of the processing chamber 100. The controller 108 can be any form of general-purpose computer processor that can be used in industrial equipment to control various chambers and subprocessors. The memory 142 stores software (source or object code) that can be executed or invoked to control the operation of the processing chamber 100 in the manner described herein. The controller 108 is configured to control a first shaping DC voltage source 159, a second shaping DC voltage source 161, an edge ring IEDF width control circuit 155, and a substrate IEDF width control circuit 158.

[0027] Figure 2 is a schematic diagram of a processing chamber 200 according to at least one embodiment of the present disclosure. The processing chamber 200 is configured to implement the scheme described herein. Similar to processing chamber 100, processing chamber 200 is a plasma processing chamber such as those described above.

[0028] The processing chamber 200 includes a substrate 105 disposed on a substrate support assembly 104, as shown in Figure 1. An edge ring 106 is positioned on the substrate support assembly 104 and surrounds the substrate 105. Although not shown, a capacitively coupled plasma device is disposed above the substrate (typically above the chamber lid). The capacitively coupled plasma device may include an ion suppressor and a showerhead, and RF power is delivered from electrodes located below the substrate to generate a capacitively coupled plasma. A controller 108 is adapted to control the system and subsystems of the processing chamber. The controller 108 comprises a central processing unit (CPU) 140, memory 142, and support circuits 144 for the CPU 140, facilitating control of the components of the processing chamber 100. The controller 108 can be any form of general-purpose computer processor that can be used in industrial equipment to control various chambers and subprocessors. Memory 142 stores software (source or object code) that can be executed or started to control the operation of the processing chamber 100 in the manner described herein. Controller 108 is configured to control the first shaping DC voltage source 159, the second shaping DC voltage source 161, the edge ring IEDF width control circuit 155, and / or the substrate IEDF width control circuit 158. Figures 4A to 4D, described later, show different configurations of connecting the IEDF width control module to the pulser.

[0029] The substrate support assembly 104, equipment plate 180, substrate electrode 109, and edge ring electrode 111 may be the same as those considered in Figure 1. The edge ring IEDF width control circuit 155 is coupled to the edge ring electrode 111. The substrate IEDF width control circuit 158 ​​is coupled to the substrate electrode 109. In one embodiment, the first shaping DC pulse voltage source 159 is coupled to one or both of the edge ring IEDF width control circuit 155 and the substrate IEDF width control circuit 158. In another embodiment, the first shaping DC voltage source 159 is coupled to the edge ring IEDF width control circuit 155, and the second shaping DC voltage source 161 is coupled to the substrate IEDF width control circuit 158. The edge ring IEDF width control circuit 155 and the substrate IEDF width control circuit 158 ​​are independently adjustable. The substrate electrode 109 is further coupled to the chuck power supply 115 to facilitate chucking the substrate 105 to the top surface 160 by the electrostatic chuck 150 during processing.

[0030] The operation of the processing chamber 200 and the processing of the substrate 105 can be carried out in a manner similar to that of the processing chamber 100. In some embodiments, the processing system configuration includes an ion suppressor located inside the processing chamber that controls the type and amount of plasma excited species reaching the substrate. In some embodiments, the ion suppressor unit is a perforated plate which may also act as an electrode for the plasma generation unit. In these and other embodiments, the ion suppressor can be a showerhead that distributes gas and excited species to a reaction region in contact with the substrate. In some embodiments, ion suppression is achieved by a perforated plate ion suppressor and a showerhead through which plasma excited species pass to reach the reaction region.

[0031] When a voltage is applied to the substrate (or wafer) by the shaped DC voltage source 159, a waveform develops. Figure 3A shows different bias voltage waveforms. The waveform includes two stages: an ion current stage and a sheath collapse stage. At the beginning of the ion current stage, a drop in wafer voltage creates a high-voltage sheath above the substrate, thereby accelerating cations toward the substrate. The cations deposit positive charge on the substrate surface, which tends to gradually increase the substrate voltage in the positive direction. When a square wave is supplied by the shaped DC voltage source 159, the ion current toward the substrate creates a positive slope in the substrate voltage, as shown by trace 305. The voltage difference between the beginning and end of the ion current phase determines the IEDF width. A larger voltage difference results in a wider IEDF width (Figure 3B). To achieve single-energy ions and a narrower IEDF width, an operation is performed to flatten the substrate voltage waveform (e.g., trace 310) in the ion current phase. In some embodiments, a voltage can be applied to achieve a specific IEDF width, such as shown by the substrate waveform of trace 315.

[0032] At the end of the ion current phase, the substrate voltage rises to the bulk plasma voltage, causing the sheath to collapse, which in turn causes electrons to move from the plasma to the substrate surface, neutralizing the positive charge on the substrate surface. As a result, the substrate surface is reset for the next cycle.

[0033] In some embodiments, the first and second shaped DC voltage sources 159 and 161 are positive pulsers. The positive pulsers generate pulses of positive voltage, which correspond to the sheath collapse stage. When each positive pulse is turned off, the ion current stage begins. In some embodiments, the first and second shaped DC voltage sources 159 and 161 are negative pulsers. The negative pulsers generate pulses of negative voltage, which correspond to the ion current stage. When each negative pulse is turned off, the sheath collapse stage begins.

[0034] Circuit example Figure 4A is a schematic diagram of an example circuit 465. As will be described later, in some embodiments, the example circuit shown in Figure 4A corresponds to the circuit diagrams in Figures 5A and 6A. Figures 5A and 6A differ, for example, depending on the circuit of the second power module.

[0035] One example circuit 465 includes a pulsed DC power supply 466 coupled to a second power module 470 through a series inductor 468 and a resistor 469. The second power module 470 modulates the width of the ion energy distribution function (IEDF). An optional blocking capacitor 471 may be present between the plasma chamber load 472 and the rest of the circuit 465. A controller, not shown, which may be implemented by hardware, software, firmware, or a combination thereof, is used to control the various components shown in Figure 4A.

[0036] The shaping DC power supply unit 466 generates a voltage waveform having two voltage levels: a low voltage level and a high voltage level. The low voltage level corresponds to the ion current phase. The high voltage level corresponds to the sheath collapse phase. In the ion current phase, the second power module 470 modulates the voltage-to-time slope, shown as traces 305, 310, and 315 in Figure 3A. Different slopes result in different IEDF widths, as shown in Figure 3B. The flattest slope (trace 305 in Figure 3A) corresponds to the narrowest IEDF width in Figure 3B.

[0037] Figure 4B is a schematic diagram of an example circuit 475. As shown, Figure 4B differs from Figure 4A by replacing the series inductor 468 and resistor 469 with a switch 479. The switch 479 is connected in series with the pulse DC power supply 476 and the second power module 478. During the ion current phase, the switch 479 is closed. During the sheath collapse phase, the switch may be either open or closed. A controller, not shown, which may be implemented by hardware, software, firmware, or a combination thereof, is used to control the various components shown in Figure 4B.

[0038] Figure 4C is a schematic diagram of an example circuit 485. As will be described later, in some embodiments, the example circuit 485 shown in Figure 4C is... 7 This corresponds to the circuit diagram in Figure 8. One example circuit 485 includes a shaped DC voltage source 486 coupled to ground. An optional blocking capacitor 487 may be present between the shaped DC voltage source 486 and a second power module 488. The second power module 488 modulates the width of the IEDF. The second power module 488 is further coupled to a plasma chamber load 489. A controller, not shown, which may be implemented by hardware, software, firmware, or a combination thereof, is used to control the various components shown in Figure 4C.

[0039] The shaped DC voltage source 486 generates a voltage waveform having two voltage levels: a low voltage level and a high voltage level. The low voltage level corresponds to the ion current stage. The high voltage level corresponds to the sheath collapse stage. In the ion current stage, the second power module 488 creates a voltage gradient over time. The resulting voltage waveform on the substrate is the sum of the output voltages of the shaped DC voltage source 486 and the second power module 488, which can be modulated, thereby modulating the IEDF width.

[0040] Figure 4D is a schematic diagram of an example circuit 490 according to at least one embodiment of the present disclosure. As will be described later, in some embodiments, the example circuit 490 corresponds to the circuit diagrams in Figures 9 and 10. The example circuit 490 includes a grounded shaped DC voltage source 491, a second power module 492, and a substrate chucking and bias compensation module 493. A switch 495 is connected in series with the substrate chucking and bias compensation module 493. The second power module 492 and the substrate chucking and bias compensation module 493 are connected in parallel, with one end connected to the shaped DC voltage source 491 and the other end connected to the plasma chamber load 494. The second power module 492 modulates the width of the IEDF. The second power module 492 and the substrate chucking and bias compensation module 493 are further connected to the plasma chamber load 494. A controller (not shown), which may be implemented by hardware, software, firmware, or a combination thereof, is used to control the various components shown in Figure 4D.

[0041] The shaped DC voltage source 491 generates a voltage waveform having two voltage levels: a low voltage level and a high voltage level. The low voltage level corresponds to the ion current stage. The high voltage level corresponds to the sheath collapse stage. In the ion current stage, the second power module 492 creates a voltage gradient over time. The resulting voltage waveform on the substrate is the sum of the output voltages of the shaped DC voltage source 491 and the second power module 492, which can be modulated, thereby modulating the IEDF width. Since switch 495 is open in the ion current stage, the chucking and bias compensation module 493 does not modulate the voltage of the plasma chamber load. In the sheath collapse stage, switch 495 is closed, and the chucking and bias compensation module 493 resets the substrate chucking voltage to a set point.

[0042] Figure 5A is a schematic circuit diagram showing one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 500 that drives the substrate electrodes 109 and / or edge ring electrodes 111 of a substrate support assembly 104. The circuit 500 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in Figure 3A). The main pulser 502 can be a first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to a current return path 503. The current return path 503 includes an inductor 504 coupled in series with a resistor 506 to an IEDF width control module 508 (e.g., the second power module in Figures 4A and 4B). The IEDF width control module 508 modulates the ion energy distribution function (IEDF) width.

[0043] The IEDF width control module 508 can be modeled as a circuit comprising a transistor-transistor logic (TTL) signal 510 coupled in parallel with a switch 512, an optional diode 514, an optional capacitance 516 coupled to ground 517, and a third shaped DC pulse voltage source 518. The diode 514 is a flyback diode protecting the switch 512 and the third shaped DC pulse voltage source 518. In some embodiments, a capacitance 520 exists between the current return path 503 and a chamber capacitance 536. The capacitance 536 can be, for example, the impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. In some embodiments, the capacitance is also coupled to a substrate chucking and bias compensation module 522.

[0044] The substrate chucking and bias compensation module 522 is a circuit including a diode 524 coupled in series with a resistor 526, a DC voltage source 528, and a resistor 530 coupled in series with a capacitor 532 and ground 534. The capacitor 536 is further coupled with a stray capacitor 538 and a plasma sheath 540. The substrate chucking and bias compensation module 522 is further coupled with the stray capacitor 538. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitor 542 coupled in parallel with a current source 544 and a diode 546 coupled to ground 548. In some embodiments, the series inductor 504 and resistor 506 in the current return path can be replaced with a switch 179 (Figure 4B). The switch 179 is closed during the ion current stage.

[0045] In use, in the configuration shown in Figure 5A, the third shaped DC pulse voltage source 518 acts as an active knob to control the slope of the voltage waveform during the ion current phase. Switch 512 is controlled by a TTL signal 510 synchronized with the main pulser 502, as shown in plot 550 in Figure 5B. Switch 512 can be closed before the voltage of the main pulser 502 rises and enters the sheath collapse phase. Switch 512 can remain closed during the sheath collapse phase, connecting the current return path 503 to ground. After the voltage of the main pulser 502 drops and enters the ion current phase, switch 512 can be opened so that the third shaped DC pulse voltage source 518 functions to modulate the IEDF during the ion current phase. An optional capacitor 516 can be used to adjust the sensitivity of the substrate voltage waveform to the third shaped DC pulse voltage source 518. Capacitor 542 is the plasma sheath capacitance, which varies under different processing conditions, and current source 544 is the ion current directed toward the substrate, which is also variable. Capacitors 536 and stray capacitance 538 are capacitances associated with the chamber and are constant. Capacitor 520 is the blocking capacitor and is also constant.

[0046] As shown in Figures 5C and 5D, during the ion current phase, when the IEDF width control module 508 (Figure 5A) is actively controlling the substrate or edge ring waveform, the active components of the circuit model include the ion current 544 (I0), the sheath capacitance 542 (C1), the chamber capacitance 536 (C2), the stray capacitance 538 (C3), the blocking capacitance 520 (C4), and an arbitrary capacitance 516 (C5) in parallel with the third shaping DC pulse voltage source 518 (V1). Since the inductor 504 and resistor 506 in the current return path have little effect on the IEDF width modulation, the inductor 504 and resistor 506 are treated as short circuits in the control circuit 560 in Figure 5C and the control circuit 570 in Figure 5D.

[0047] The intrinsic factor widening the IEDF is the ion current I0, which gradually increases the voltage on the substrate by depositing positive charge on the substrate, thereby decreasing the ion energy impacting the substrate (e.g., trace 305 in Figure 3A). The amount of IEDF widening is determined, for example, by the ion current I0, sheath capacitance C1, and / or other capacitances associated with chambers C2, C3, and C4, as well as the power supply modules V1 and C5 of the control circuits 560 and 570. The values ​​of all components of this control circuit (Figure 5C) are determined to compensate for the ion current effect of IEDF widening and / or to actively control the IEDF width. The capacitances associated with the chambers and power supply modules C2-C5 can be determined by product specifications or estimations using the dimensions of the chamber portion, or by previous measurements such as direct impedance measurements using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. The ion current I0 and sheath capacitance C1 vary with fluctuating plasma processing conditions and are determined by real-time measurements during the plasma process. The shaped DC pulsed voltage source V1 has a sawtooth voltage output (Figure 5E). By varying the slope dV1 / dt of the voltage output, the ion current I0 and sheath capacitance C1 can be determined, and / or the IEDF width can be modulated. In the configuration of Figure 5A, the output voltage of the shaped DC pulsed voltage source V1 is zero during the sheath collapse phase, as shown by trace 584. Traces 582 and 586 show other possible waveforms for the shaped DC pulsed voltage source V1, as described later.

[0048] The IEDF modulation method includes two parts: (1) determining the ion current I0 and the sheath capacitance C1, and (2) determining the slope dV1 / dt of the shaped DC pulse voltage source to achieve the target IEDF width. Since the sawtooth voltage source V1 and the shaped DC voltage source 159 or 161 supply power to the substrate 105 or edge ring 106, the IEDF width at the substrate or edge ring is the change in substrate or edge ring voltage from the beginning to the end of the ion current phase (Figures 3A and 3B). In the control circuit 560 in Figure 5C and the control circuit 570 in Figure 5D, the IEDF width corresponds to the change in voltage across the sheath capacitance C1 from the beginning to the end of the ion current phase, which is determined by the charge or discharge current I1 through the sheath capacitance C1. ΔV = I1 × T / C1 (1) In the formula, ΔV is the IEDF width and T is the duration of the ion current stage. To obtain the target IEDF width (ΔV), the sheath capacitance C1 and the desired current I1 through the sheath capacitance should be determined.

[0049] To determine the sheath capacitance C1 and the ion current I0, the relationship between current and voltage in the control circuit is analyzed. As shown in the figure, the currents passing through capacitors C1-C4 are called I1-I4, and the arrows in the schematic circuit diagram point in the positive direction. Based on Kirchhoff's current law, the ion current I0 is equal to the sum of the currents passing through capacitors C1 and C2. I0 = I1 + I2 (2)

[0050] The current flowing through capacitor C2 is equal to the sum of the currents flowing through capacitors C3 and C4. I2 = I3 + I4 (3)

[0051] Based on Kirchhoff's voltage law, the sum of the voltages across the closed loop C1, C2, and C3 is zero. The time derivative of the sum of the voltages across C1, C2, and C3 is also zero. Let V3 be the voltage at the intersection of capacitors C2 and C3. The time derivative of the voltage across capacitor C3 is dV3 / dt = I3 / C3. A similar relationship exists for capacitors C1 and C2, and equation (4) is obtained by Kirchhoff's voltage law. I1 / C1 = I2 / C2 + I3 / C3 (4)

[0052] By applying Kirchhoff's voltage law to the closed loop between capacitors C3 and C4 and voltage source V1, equation (5) is obtained. I3 / C3 = I4 / C4 + dV1 / dt (5)

[0053] In equations (2) to (5), C2, C3, and C4 are predetermined by product specifications or estimations based on the dimensions of the chamber portion, or by previous measurements such as direct measurement of impedance using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. The current I4 can be measured directly by a sensor such as a current probe and / or an integrated voltage-current (VI) sensor. The voltage V3 can be measured directly by a sensor such as a voltage probe and / or an integrated VI sensor. The current I3 can be calculated as I3 = C3 × dV3 / dt. The voltage gradient dV1 / dt is known and is user-controlled, such as zero or 1 volt / nanosecond (V / nsec). The currents I4, I4', and the time derivatives of the voltages dV3 / dt, dV3' / dt can be determined by setting the shaped DC pulse voltage source V1 to two different gradients dV1 / dt and dV1' / dt. The set of equations (2) to (5) for the two inclines dV1 / dt and dV1' / dt forms eight equations, and solving them yields the sheath capacity given by the following equation. TIFF0007936856000001.tif28170 and the ion current are given by the following equation. TIFF0007936856000002.tif18170

[0054] To obtain the target IEDF width (ΔV), the total current passing through the sheath capacitor C1 is given by the following equation. I1 = C1 × ΔV / T (8)

[0055] By substituting equations (6) to (8) into equations (2) to (5), the voltage gradient of the sawtooth voltage source V1 that achieves the IDEF width ΔV is obtained. TIFF0007936856000003.tif16170

[0056] In the case of the narrowest IEDF (ΔV=0), the voltage gradient of the sawtooth voltage source V1 is as follows: TIFF0007936856000004.tif18170

[0057] Figure 6A is a schematic circuit diagram showing one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 600 that drives the substrate electrodes 109 and / or edge ring electrodes 111 of the substrate support assembly 104. The circuit 600 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in Figure 3A). The main pulser 502 can be a first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to a current return path 503. The current return path 503 includes an inductor 504 coupled in series with a resistor 506 to an IEDF width control module 602 (e.g., the second power module in Figures 4A and 4B). The IEDF width control module 602 modulates the IEDF width. Unlike the configuration in Figure 5A, the IEDF width control module 602 may be modeled as a circuit comprising a TTL signal 510 coupled in parallel with the switch 512, a diode 514, an arbitrary capacitance 516 coupled to ground 517, and a DC voltage source 604 coupled in series with the resistor 606. The diode 514 is a flyback diode protecting the switch 512 and the DC voltage source 604. In some embodiments, a blocking capacitance 520 is present between the current return path 503 and the chamber capacitance 536. The capacitance 536 can be, for example, the impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. In some embodiments, a substrate chucking and bias compensation module 522 is also coupled to the blocking capacitance 520 and the chamber capacitance 536. The substrate chucking and bias compensation module 522 is further coupled to a stray capacitance 538. The board chucking and bias compensation module 522 is a circuit that includes a diode 524 connected in series with a resistor 526, a DC voltage source 528, and a resistor 530 connected in series with a capacitor 532 and ground 534.

[0058] The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with the current source 544 and a diode 546 coupled to ground 548.

[0059] In use, in the configuration shown in Figure 6A, the third shaping DC pulse voltage source 518 acts as an active knob to control the slope of the voltage waveform in the ion current stage, in contrast to the configuration shown in Figure 5A, where the DC voltage source 604, together with resistor 606, acts as an active knob to control the slope of the substrate or edge ring voltage waveform in the ion current stage. Switch 512 can be controlled by a TTL signal 510 synchronized with the main pulser 502, as shown in Figure 5B. Switch 512 can be closed before the voltage of the main pulser 502 rises and enters the sheath collapse stage. Switch 512 can remain closed during the sheath collapse stage, connecting the current return path 503 to ground. After the voltage of the main pulser 502 drops and enters the ion current stage, switch 512 can be opened so that the DC voltage source 604 functions to modulate the IEDF during the ion current stage. An optional capacitor 516 can be used to adjust the sensitivity of the substrate voltage waveform to the DC voltage source 604. Capacitor 542 is the plasma sheath capacitance and is variable. Current source 544 is the ion current directed toward the substrate and is also variable. Capacitor 536 can be, for example, the capacitance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. Capacitor 538 can be the capacitance between the substrate electrode 109 and ground, or between the edge ring electrode 111 and ground. Capacitor 520 is the blocking capacitor and is also constant.

[0060] As shown in Figures 6B and 6C, during the ion current phase, when the IEDF width control module 602 (Figure 6A) is actively controlling the substrate or edge ring waveform, the active components of the circuit model include the ion current 544 (I0), the sheath capacitance 542 (C1), the chamber capacitance 536 (C2), the stray capacitance 538 (C3), the blocking capacitance 520 (C4), and an arbitrary capacitance 516 (C5) in parallel with the DC voltage source 604 (V0) and resistor 606 (R). Since the inductor 504 and resistor 506 in the current return path have little effect on the IEDF width modulation, the inductor 504 and resistor 506 are treated as short circuits in the control circuit 650 in Figure 6B and the control circuit 660 in Figure 6C. The control circuit of Figure 6A is shown in Figure 6B and will be described later. 7 The control circuit is shown in Figure 6C.

[0061] The intrinsic factor widening the IEDF is the ionic current I0, which gradually increases the voltage on the substrate by depositing positive charge on the substrate, thereby decreasing the ionic energy impacting the substrate (trace 305 in Figure 3A). The amount of IEDF widening is determined, for example, by the ionic current I0, the sheath capacitance C1, and other capacitances associated with the chambers (C2, C3, and C4), as well as the power supply modules (V0, R, and C5) of the control circuits 650 and 660, respectively, in Figures 6B and 6C. The values ​​of all components of control circuits 650 and 660 are determined to compensate for the ionic current effect of IEDF widening and to actively control the IEDF width. The capacitances associated with the chambers and power supply modules C2-C5 can be determined by product specifications or estimations using the dimensions of the chamber portion, or by prior measurements such as direct impedance measurements using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. The resistor R is also predetermined by product specifications or by direct measurements using a multimeter. The ion current I0 and sheath capacitance C1 fluctuate with varying plasma processing conditions and are determined by real-time measurements during the plasma process. The DC voltage source V0 is an active control knob that can be varied to determine the ion current I0, determine the sheath capacitance C1, and / or modulate the IEDF width.

[0062] The IEDF modulation method involves two parts: (1) determining the ion current I0 and the sheath capacitance C1, and (2) determining the DC voltage V0 to achieve the target IEDF width. The IEDF width is the spread of the substrate or edge ring voltage from the beginning to the end of the ion current phase (Figures 3A and 3B). In the control circuit 650 in Figure 6B and the control circuit 660 in Figure 6C, the IEDF width corresponds to the change in voltage across the sheath capacitance C1 from the beginning to the end of the ion current phase, which is determined by the charge or discharge current I1 through the sheath capacitance C1. TIFF0007936856000005.tif17170 In the formula, ΔV is the IEDF width, and T is the duration of the ion current step. To obtain the target IEDF width (ΔV), the sheath capacitance C1 and the desired current I1 passing through the sheath capacitance should be determined.

[0063] To determine the sheath capacitance C1 and the ion current I0, the relationship between current and voltage in the control circuit is analyzed. Here, for example, the currents passing through capacitors C1 to C5 are referred to as I1 to I5, and the arrows in the schematic circuit diagram point to the positive direction. The voltage at the intersection of capacitors C2 and C3 is V3. There is a threshold voltage for the DC voltage source V0, referred to as Vth, below which the diode D3 bypasses the series connection of the DC voltage source V0 and the resistor R, so the output voltage of the IEDF width control module is zero. Vth depends on plasma conditions, and can be determined experimentally, for example, by gradually increasing the DC voltage V0 until the current I4 or the voltage V3 is affected by the DC voltage output V0.

[0064] When V0<Vth, based on Kirchhoff's current law, the ion current I0 is equal to the sum of the currents passing through capacitors C1 and C2. I0=I1+I2 (12)

[0065] The current passing through capacitor C2 is equal to the sum of the currents passing through capacitors C3 and C4. I2=I3+I4 (13)

[0066] Based on Kirchhoff's voltage law, the sum of the voltages of the closed loop C1, C2, and C3 is zero. The time derivative of the sum of the voltages of C1, C2, and C3 is also zero. The time derivative of the voltage across capacitor C3 is dV3 / dt=I3 / C3. The same relationship applies to capacitors C1 and C2. By applying Kirchhoff's voltage law to capacitors C1 and C2, equation (14) is obtained. I1 / C1=I2 / C2+I3 / C3 (14)

[0067] By applying Kirchhoff's voltage law to the closed loop of capacitors C3 and C4, and the diode bypass IEDF width control module, equation (15) is obtained. I3 / C3 = I4 / C4 (15)

[0068] If V0 > Vth, equations (12) to (14) still hold. By applying Kirchhoff's voltage law to the closed loop of capacitors C3, C4, and C5, we obtain equation (16). I3 / C3 = I4 / C4 + I5 / C5 (16)

[0069] By applying Kirchhoff's voltage law to a closed loop consisting of capacitor C5, DC voltage source V0, and resistor R, equation (17) is obtained. In formula TIFF0007936856000006.tif17170, (I4-I5) are the currents through the DC voltage source V0 and resistor R when diode D3 is inactive.

[0070] In some embodiments, capacitor C5 is absent. In such cases, equation (17) is absent, and equation (16) becomes the following: I3 / C3 = I4 / C4 + R × dI4 / dt (18)

[0071] In equations (12) to (18), C2, C3, C4, and C5 are predetermined by product specifications or estimations based on the dimensions of the chamber portion, or by previous measurements such as direct measurement of impedance using a multimeter or extracting capacitance values ​​from S-parameter or Z-parameter measurements. The current I4 can be measured directly by a sensor such as a current probe and / or integrated VI sensor. The voltage V3 can be measured directly by a sensor such as a voltage probe and / or integrated VI sensor. The current I3 can be calculated as I3 = C3 × dV3 / dt. The DC voltage V0 is known to be user-controlled, such as setting the DC voltage output V0 to a value from zero to several kV. By setting the DC voltage V0 to two different values ​​V0 and V0', and making at least one of them higher than the threshold voltage Vth, the currents I4, I4', and the time derivatives of the voltages dV3 / dt, dV3' / dt can be determined. The sheath capacitance C1 obtained by solving the set of equations (12) to (18) is given by the following equation. TIFF0007936856000007.tif27170 and the ion current I0 of the following equation. I0=(C1 / C2+C1 / C3+1)×I3+(C1 / C2+1)×I4 (20)

[0072] By substituting the sheath capacitance C1 and ion current I0 into the set of equations (12) to (18), the currents I1 to I5 can be calculated for any DC voltage V0.

[0073] By substituting the known capacitances C1-C5, resistance R, and DC voltage V0 into equation (11) in expression I1, we can obtain the relationship between the IEDF width (ΔV) and the DC voltage V0. Therefore, the required DC voltage V0 can be determined for a given target IEDF width (ΔV).

[0074] In some embodiments, the resistor R is sufficiently large (e.g., about 10 kΩ), and the current through the DC voltage source V0 is nearly constant over time during the ion current phase and is equal to V0 / R. In these embodiments, equation (17) becomes: I4 = I5 + V0 / R (21)

[0075] By solving equations (12), (13), (14), (16), and (21), the total current passing through the sheath capacitor C1 is obtained as equation (22). TIFF0007936856000008.tif18170In formula, k = C3C4 + C4C5 + C5C3 That is the case.

[0076] Using equation (8) for this approximate example of a constant current I1, the DC voltage V0 used to obtain the target IEDF width (ΔV) can be found using equation (23). TIFF0007936856000009.tif15170

[0077] In the case of the narrowest IEDF (ΔV=0), the DC voltage V0 is given by the following equation. TIFF0007936856000010.tif15170

[0078] figure 7 This is a schematic circuit diagram showing one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 700 that drives the substrate electrodes 109 and / or edge ring electrodes 111 of the substrate support assembly 104. The circuit 700 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in Figure 3A). The main pulser 502 can be a first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled directly or through a capacitor 701 to an IEDF width control module 702 (e.g., the second power module in Figure 4C).

[0079] The IEDF width control module 702 may be modeled as a circuit including a TTL signal 704 coupled in parallel with a switch 706. The TTL signal 704 is coupled in series with ground 716. The switch 706 is coupled in parallel with a diode 708, a DC voltage source 710, and an optional capacitor 714. The DC voltage source 710 is coupled in series with a resistor 712. The IEDF width control module 702 is coupled with a chamber capacitor 536. The capacitor 536 can be, for example, the impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. In some embodiments, the IEDF width control module 702 is also coupled with the substrate chucking and bias compensation module 522 described above. The substrate chucking and bias compensation module 522 is further coupled with a stray capacitor 538. The board chucking and bias compensation module 522 is a circuit that includes a diode 524 connected in series with a resistor 526, a DC voltage source 528, and a resistor 530 connected in series with a capacitor 532 and ground 534. Diode 708 is a flyback diode that protects the switch 706 and the DC voltage source 710.

[0080] The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with the current source 544 and a diode 546 coupled to ground 548.

[0081] When using, see the diagram. 7In the configuration shown, the DC voltage source 710, together with the resistor 712, acts as an active knob to control the slope of the voltage waveform during the ion current stage. Switch 706 can be controlled by a TTL signal 704 synchronized with the main pulser 502, as shown in the plot in Figure 5B. Switch 706 can be closed before the voltage of the main pulser 502 rises and enters the sheath collapse stage. Switch 512 can remain closed during the sheath collapse stage. After the voltage of the main pulser 502 drops and enters the ion current stage, switch 706 can be opened so that the DC voltage source 710 functions to modulate the IEDF during the ion current stage. An optional capacitor 714 can be used to adjust the sensitivity of the substrate voltage waveform to the DC voltage source 710. 7 The control mechanism is the same as the control mechanism in Figure 6A. One difference is that, 7 The control circuit for Figure 6A is shown in Figure 6C, and the control circuit for Figure 6A is shown in Figure 6B.

[0082] Figure 8 is a schematic circuit diagram showing one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 800 that drives the substrate electrodes 109 and / or edge ring electrodes 111 of the substrate support assembly 104. The circuit 800 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in Figure 3A). The main pulser 502 can be a first or second shaped DC voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled directly or through a capacitor 701 to an IEDF width control module 802 (e.g., the second power module in Figure 4C).

[0083] The IEDF width control module 802 may be modeled as a circuit comprising a TTL signal 704 coupled in parallel with a switch 706. The TTL signal 704 is also coupled in series with ground 716. The switch 706 is coupled in parallel with a diode 708, a third shaped DC pulse voltage source 804, and an optional capacitor 714. The IEDF width control module 802 is coupled with a chamber capacitor 536. The capacitor 536 can be, for example, the impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. In some embodiments, the IEDF width control module 802 is also coupled with the substrate chucking and bias compensation module 522 described above. The substrate chucking and bias compensation module 522 is a circuit comprising a diode 524 coupled in series with a resistor 526, a DC voltage source 528, and a resistor 530 coupled in series with capacitor 532 and ground 534. Diode 708 is a flyback diode that protects the switch and the third shaping DC pulse voltage source 804.

[0084] The substrate chucking and bias compensation module 522 is further coupled to the chamber capacitance 536. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with the current source 544 and a diode 546 coupled to ground 548.

[0085] When in use, in the configuration shown in Figure 8, the DC voltage source 710, together with the resistor 712, acts as an active knob to control the slope of the voltage waveform in the ion current stage. 7In contrast to the configuration shown, the third shaped DC pulse voltage source 804 acts as an active knob to control the slope of the voltage waveform in the ion current stage. Switch 706 can be controlled by a TTL signal 704 synchronized with the main pulser 502, as shown in the plot in Figure 5B. Switch 706 can be closed before the voltage of the main pulser 502 rises and enters the sheath collapse stage. Switch 706 remains closed during the sheath collapse stage. After the voltage of the main pulser 502 drops and enters the ion current stage, switch 706 can be opened so that the third shaped DC pulse voltage source 804 functions to modulate the IEDF during the ion current stage. An optional capacitor 714 can be used to adjust the sensitivity of the substrate voltage waveform to the third shaped DC pulse voltage source 804. The control mechanism in Figure 8 is similar to that in Figure 5A. One difference is that the control circuit in Figure 8 is shown in Figure 5D above, and the control circuit in Figure 5A is shown in Figure 5C.

[0086] In the configurations shown in Figures 5A, 6A, 7, and 8, it is conceivable that the substrate chucking and bias compensation module can be connected to the circuit in any preferred manner without departing from the scope of the embodiments described herein. Furthermore, it is conceivable that the substrate chucking and bias compensation module may include additional or different components without departing from the scope of the embodiments described herein.

[0087] Figure 9 is a schematic circuit diagram showing one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 900 that drives the substrate electrodes 109 and / or edge ring electrodes 111 of a substrate support assembly 104. The circuit 900 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in Figure 3A). The main pulser 502 can be a first or second shaped DC pulse voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to an IEDF width control module 902 (e.g., the second power module in Figure 4D).

[0088] The IEDF width control module 902 may be modeled as a circuit including a TTL signal 904 coupled in parallel with a switch 906. The TTL signal 904 is also coupled in series with ground 916. Switch 906 is coupled in parallel with diode 908. The combination of TTL signal 904, switch 906, and diode 908 controls whether a board chucking and bias compensation module 920 is connected to another part of the circuit. The board chucking and bias compensation module 920 is a circuit including a capacitor 926 coupled in parallel with a resistor 922 and a DC voltage source 924. The board chucking and bias compensation module 920 is coupled in series with the assembly of TTL signal 904, switch 906, and diode 908. The board chucking and bias compensation module 920 and switch 906 as a whole are coupled in parallel with a DC voltage source 910 in series with a resistor 912, and also in parallel with an optional capacitor 914. Diode 908 is a flyback diode that protects switch 906 and DC voltage sources 910 and 924.

[0089] Capacitance 536 may exist between the stray capacitance 538 and the plasma sheath 540, and may be, for example, the impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. Both the IEDF width control module 902 and the substrate chucking and bias compensation module 920 are coupled to either the substrate electrode 109 and / or the edge ring electrode 111. The IEDF width control module 902 is also coupled to the stray capacitance 538. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with the current source 544 and a diode 546 coupled to ground 548.

[0090] When in use, in the configuration shown in Figure 9, the DC voltage source 910, together with the resistor 912, acts as an active knob to control the slope of the voltage waveform during the ion current stage. Switch 906 can be controlled by a TTL signal 904 synchronized with the main pulser 502, as shown in Figure 5B. Switch 906 can be closed before the voltage of the main pulser 502 rises and enters the sheath collapse stage. Switch 512 can remain closed during the sheath collapse stage, thereby connecting the substrate chucking and bias compensation module 920 to another part of the circuit and resetting the substrate chucking voltage to a set point. After the voltage of the main pulser 502 drops and enters the ion current stage, switch 906 can be opened so that the DC voltage source 910 functions to modulate the IEDF during the ion current stage. An optional capacitor 914 can be used to adjust the sensitivity of the substrate voltage waveform to the DC voltage source 910. The control mechanism in Figure 9 is similar to that in Figure 6B described above. One difference is that capacitor C4 has been removed.

[0091] Figure 10 is a schematic circuit diagram showing one embodiment of an edge ring voltage control circuit / substrate voltage control circuit 1000 that drives electrodes 109, 111 of a substrate support assembly 104. The circuit 1000 includes a main pulser 502 that resets the substrate voltage at the beginning of each ion current phase (corresponding to the voltage droop in Figure 3A). The main pulser 502 can be a first or second shaped DC pulse voltage source 159, 161 coupled to ground 501. The main pulser 502 is coupled to an IEDF width control module 1002 (e.g., the second power module in Figure 4D).

[0092] The IEDF width control module 1002 may be modeled as a circuit including a TTL signal 904 coupled in parallel with a switch 906. The TTL signal 904 is also coupled in series with ground 916. Switch 906 is coupled in parallel with diode 908. The combination of TTL signal 904, switch 906, and diode 908 controls whether a board chucking and bias compensation module is connected to another part of the circuit. The board chucking and bias compensation module 920 is a circuit including a resistor 922 and a capacitor 926 coupled in parallel with a DC voltage source 924. Diode 908 is a flyback diode that protects the switch, DC voltage source 910, and DC voltage source 924. The board chucking and bias compensation module 920 is coupled in series with the assembly of TTL signal 904, switch 906, and diode 908. The board chucking and bias compensation module 920 and the switch 906 are coupled together in parallel to the DC pulse voltage source 1004 and to an optional capacitor 914.

[0093] Capacitance 536 may exist between the stray capacitance 538 and the plasma sheath 540, and may be, for example, the impedance between the substrate electrode 109 and the substrate, or between the edge ring electrode 111 and the edge ring. Both the IEDF width control module 1002 and the substrate chucking and bias compensation module 920 are coupled to either the substrate electrode 109 and / or the edge ring electrode 111. The IEDF width control module 1002 is also coupled to the stray capacitance 538. The plasma sheath 540 may be modeled (plasma sheath model) as a circuit comprising a sheath capacitance 542 coupled in parallel with the current source 544 and a diode 546 coupled to ground 548.

[0094] In use, in the configuration shown in Figure 10, the DC voltage source 910, together with the resistor 912, acts as an active knob to control the slope of the voltage waveform in the ion current stage, in contrast to the configuration shown in Figure 9, where the shaped DC pulse voltage source 1004 acts as an active knob to control the slope of the voltage waveform in the ion current stage. Switch 906 can be controlled by a TTL signal 904 synchronized with the main pulser 502, as shown in the plot in Figure 5B. Switch 906 can be closed before the voltage of the main pulser 502 rises and enters the sheath collapse stage. Switch 512 can be kept closed during the sheath collapse stage, thereby connecting the substrate chucking and bias compensation module to another part of the circuit and resetting the substrate chucking voltage to a set point. After the voltage of the main pulser 502 drops and enters the ion current stage, switch 906 can be opened so that the DC voltage source 910 functions to modulate the IEDF during the ion current stage. Any capacitor 914 can be used to adjust the sensitivity of the substrate voltage waveform to the shaped DC pulse voltage source 1004.

[0095] The control mechanism in Figure 10 is the same as in Figure 5A. One difference is that the capacitor C4 is removed. Another difference is that the output voltage of the shaping DC pulse voltage source 1004 during the sheath collapse phase is maintained at the output voltage of the substrate chucking and bias compensation module 920, rather than zero, as shown in traces 582 (positive chucking voltage) and 586 (negative chucking voltage) in Figure 5E.

[0096] Example of method Figure 11 is a flowchart of a method 1100 for controlling the IEDF width using an edge ring IEDF width control circuit 155 and / or a substrate IEDF width control circuit 158, according to at least one embodiment of the present disclosure. Method 1100 can be implemented using one or more of the circuit configurations shown in Figures 5 to 10. Method 1100 also provides a method for operating a processing chamber 100 or a processing chamber 200.

[0097] Method 1100 begins by applying or otherwise introducing a voltage to a suitable processing chamber by activating, i.e., powering on, a main pulser (e.g., main pulser 502) coupled to a power module (e.g., IEDF width control module). Here, the voltage is introduced to a substrate electrode, e.g., substrate electrode 109, and / or an edge ring electrode, e.g., edge ring electrode 111. The bias voltage to the substrate electrode and / or edge ring electrode develops in the ion current stage, accelerating the ions with energy equal to, for example, the product of the sheath voltage and the ion charge. In a collisionless sheath model, most ions can reach this maximum energy when they strike the substrate electrode and / or edge ring electrode. However, for example, the ion current deposits positive charge on the substrate electrode and / or edge ring electrode, causing the voltage on the substrate electrode and / or edge ring electrode to increase over time, reducing the sheath voltage and diffusing the ion energy.

[0098] In operation 1110, the current of a power module (e.g., an IEDF width control module) and / or the voltage or voltage derivative of the IEDF width control module are measured under two or more conditions to determine the sheath capacitance C1 and / or the ion current I0. Here, the current measured can be the current I4, which is the current through capacitor C4 in Figures 5A, 6A, 7, and 8. In addition or alternatively, the current measured can be the output current of the main pulser in Figures 9 and 10. The voltage derivative can be dV3 / dt. The measurement can be performed at the ion current stage. Two or more conditions can be achieved by setting the active knob of the IEDF width control module (e.g., DC voltage source V0 and / or shaped DC pulse voltage source dV1 / dt) to two different values.

[0099] As an example, in the configurations of Figures 5, 8, and 10, the shaped DC pulse voltage source can be set to any two different gradients dV1 / dt in the ion current stage. As another example, in the configurations of Figures 6, 7, and 9, if I4 is affected by the DC voltage V0, the DC voltage V0 can be gradually increased while monitoring I4 up to a certain point. This DC voltage is the threshold voltage Vth. At least one of the two setpoints for the DC voltage source V0 is greater than Vth. In other words, measuring the current of the IEDF width control module, the voltage or voltage derivative of the IEDF width control module, or both, includes setting the DC voltage source, the shaped DC pulse voltage source, or both to a first value and setting the DC voltage source, the shaped DC pulse voltage source, or both to a second value.

[0100] In operation 1115, the ion current I0 and sheath capacitance C1 are calculated based on equations (6) and (7) for the configurations in Figures 5, 8, and 10, or on equations (19) and (20) for the configurations in Figures 6, 7, and 9. The input values ​​for the calculation are as follows: I3 = C3 × dV3 / dt; I3' = C3 × dV3' / dt; and I4, I4'. The values ​​of C3 and C3' are known, and the values ​​of dV3 / dt, dV3' / dt, I4, and I4' are measured in operation 1110. Therefore, I3 and I3' can be calculated.

[0101] In operation 1120, a desired setpoint for the main pulser's DC voltage (V0), a desired setpoint for the IEDF width control module's voltage (V1) or voltage derivative (dV1 / dt), or both, is determined to achieve the target IEDF width (ΔV). This determination is based, for example, on determining a desired setting of the IEDF width control module to achieve a user-specified ion energy distribution width (ΔV). The slopes (dV1 / dt) of the main pulser's DC voltage (V0) and the shaping DC pulse voltage (V1) can be determined from equations (23) and (9), respectively. In operation 1125, the IEDF width control module's DC voltage (V0) and / or voltage (V1) or voltage derivative (dV1 / dt) are adjusted to the determined setpoint.

[0102] In contrast to conventional processes for controlling an IEDF, the method described herein does not involve looping to determine a desired setpoint for the IEDF width control module. However, in some embodiments, looping can be used to determine a desired setpoint. In such embodiments, the controller can monitor I4 and V3 at the ion current stage to detect any changes in plasma conditions and adjust the setpoint of the IEDF width control module accordingly.

[0103] The methods and apparatus, such as circuits, described herein enable control over the waveform shape (e.g., narrow or adjustable width) of a pulsed DC substrate voltage. Embodiments described herein further enable control over the ion energy distribution, including, for example, single-energy ion acceleration.

[0104] As will be evident from the overall description above and the specific embodiments, the forms of this disclosure have been illustrated and described, but various modifications can be made without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not intended to be limited in any way. Similarly, the term “equipment” is to be considered synonymous with the term “includes.” Similarly, whenever a configuration, element, or group of elements is followed by the transitional phrase “equipment,” it is understood that the same configuration or group of elements may also be associated with the transitional phrases “essentially consisting of,” “consisting of,” “selected from a group consisting of,” or “is,” before or after listing the configuration, element, or group of elements.

[0105] The foregoing applies to embodiments of the present disclosure, but other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which will be determined by subsequent claims.

Claims

1. A substrate electrode for applying a substrate voltage to a substrate, wherein the substrate electrode is coupled to a power module via a current return path, the power module includes a voltage source, and the power module is configured to control the energy distribution function width of ions reaching the substrate by applying a voltage to the current return path, A substrate voltage control circuit coupled to the substrate electrode, wherein the substrate voltage control circuit comprises the power module and a main pulser coupled to the current return path, Equipped with, The aforementioned substrate voltage control circuit is By activating the main pulser, a voltage is introduced to the substrate electrode in the processing chamber, Changing the first voltage derivative of the power module, The current of the power module is measured, and the second voltage derivative at the point between the main pulser and the substrate electrode is measured, Based on the measured current of the power module and the measured voltage derivative of the second voltage, the ion current of the processing chamber and the plasma sheath capacitance above the substrate in the processing chamber are calculated. Determining the setpoint for the DC voltage of the main pulser, the setpoint for the first voltage derivative of the power module, or both, To control the width of the IEDF, the DC voltage of the main pulser, the first voltage derivative of the power module, or both are adjusted to the determined setpoint. Configured to perform, Substrate support.

2. The substrate support according to claim 1, wherein the power module comprises a switch, an arbitrary diode, and a transistor-transistor logic signal coupled in parallel with a shaped DC pulse voltage source.

3. The substrate support according to claim 2, wherein the shaping DC pulse voltage source controls the slope of the voltage waveform of the substrate voltage.

4. The substrate support according to claim 1, wherein the power module comprises a transistor-transistor logic signal coupled in parallel with a switch and a diode.

5. The substrate support according to claim 1, wherein the power module comprises a transistor-transistor logic signal coupled in parallel with a DC voltage source.

6. The substrate support according to claim 5, wherein the DC voltage source is coupled in series with a resistor.

7. The substrate support according to claim 6, wherein the DC voltage source coupled in series with the resistor controls the slope of the voltage waveform of the substrate voltage.

8. The substrate support according to claim 1, wherein the power module comprises a switch, a diode, and a transistor-transistor logic signal coupled in parallel with a DC voltage source.

9. A substrate electrode that applies a substrate voltage to the substrate, A substrate voltage control circuit coupled to the substrate electrode, Equipped with, The substrate electrode is coupled to a power module, and the power module includes a voltage source and is configured to control the energy distribution function width of ions reaching the substrate by applying a voltage. The substrate voltage control circuit comprises the power module and a main pulser coupled to the power module. The aforementioned substrate voltage control circuit is By activating the main pulser, a voltage is introduced to the substrate electrode in the processing chamber, Changing the first voltage derivative of the power module, The current of the power module is measured, and the second voltage derivative at the point between the main pulser and the substrate electrode is measured, Based on the measured current of the power module and the measured voltage derivative of the second voltage, the ion current of the processing chamber and the plasma sheath capacitance above the substrate in the processing chamber are calculated. Determining the setpoint for the DC voltage of the main pulser, the setpoint for the first voltage derivative of the power module, or both, To control the width of the IEDF, the DC voltage of the main pulser, the first voltage derivative of the power module, or both are adjusted to the determined setpoint. Configured to perform, Substrate support.

10. The substrate support according to claim 9, wherein the blocking capacitance is coupled to both the main pulser and the power module.

11. The substrate support according to claim 9, wherein the power module comprises a transistor-transistor logic signal coupled in parallel with a switch, the switch is coupled in parallel with a diode and a DC voltage source, and the DC voltage source is coupled in series with a resistor.

12. The substrate support according to claim 11, wherein the DC voltage source coupled in series with the resistor controls the slope of the voltage waveform of the substrate voltage.

13. The substrate support according to claim 9, wherein the power module comprises a transistor-transistor logic signal coupled in parallel with a switch, and the switch is coupled in parallel with a diode and a shaped DC pulse voltage source.

14. The substrate support according to claim 13, wherein the shaping DC pulse voltage source controls the slope of the voltage waveform of the substrate voltage.

15. A substrate electrode that applies a substrate voltage to the substrate, A substrate voltage control circuit coupled to the substrate electrode, Equipped with, The substrate electrode is coupled to a power module, and the power module includes a voltage source and is configured to control the energy distribution function width of ions reaching the substrate by applying a voltage. The substrate voltage control circuit comprises a main pulser coupled to the power module, and the power module, wherein the power module is in parallel with the substrate chucking and bias compensation module and includes a voltage source. The aforementioned substrate voltage control circuit is By activating the main pulser, a voltage is introduced to the substrate electrode in the processing chamber, Changing the first voltage derivative of the power module, The current of the power module is measured, and the second voltage derivative at the point between the main pulser and the substrate electrode is measured, Based on the measured current of the power module and the measured voltage derivative of the second voltage, the ion current of the processing chamber and the plasma sheath capacitance above the substrate in the processing chamber are calculated. Determining the setpoint for the DC voltage of the main pulser, the setpoint for the first voltage derivative of the power module, or both, To control the width of the IEDF, the DC voltage of the main pulser, the first voltage derivative of the power module, or both are adjusted to the determined setpoint. Configured to perform, Substrate support.

16. The substrate support according to claim 15, wherein the blocking capacitance is coupled to both the main pulser and the power module.

17. The substrate support according to claim 15, wherein the power module comprises a transistor-transistor logic signal coupled in parallel with a switch, the switch is coupled in parallel with a diode and a DC voltage source, and the DC voltage source is coupled in series with a resistor.

18. The substrate support according to claim 17, wherein the DC voltage source coupled in series with the resistor controls the slope of the voltage waveform of the substrate voltage.

19. The substrate support according to claim 15, wherein the power module comprises a transistor-transistor logic signal coupled in parallel with a switch, and the switch is coupled in parallel with a diode and a shaped DC pulse voltage source.

20. The substrate support according to claim 19, wherein the shaping DC pulse voltage source controls the slope of the voltage waveform of the substrate voltage.

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