Carrier with tabs

Abstract

A carrier ring with tabs for use with semiconductor processing equipment is provided. The carrier ring may include a ring having an outer portion and an inner portion and defining a plane. The carrier ring may include tabs around an inner circumference of the inner portion. The ring and tabs may have physical characteristics configured to enable more backside deposition of a semiconductor substrate at locations of the semiconductor substrate corresponding to the tabs compared to a ring without the physical characteristics. Such characteristics of the ring and tabs may include an inner diameter of the ring, an inner diameter of the tabs, a quantity of tabs, a width of the tabs, and an angle of the tabs relative to the plane. These characteristics may reduce substrate contact area and increase deposition area near the substrate edge, which may increase film thickness uniformity.

Description

[Technical Field]

[0001] [References] As part of this application, a PCT application form is filed concurrently with this specification. Each application on which this application claims interest or priority, as identified in the concurrently filed PCT application form, is incorporated herein by reference and for all purposes. [Background technology]

[0002] Semiconductor device fabrication often involves depositing stacks of layers on a wafer substrate. The depositing and other processes for forming the device are often performed on one side of the substrate, often referred to as the front side. As the deposited layers accumulate, they can impart stress to the substrate. Large net compressive or tensile stresses can cause the substrate to warp, resulting in a deviation from the substrate's plane (e.g., the average central plane of the semiconductor substrate), which is undesirable. Such substrates can be extremely sensitive to such deviations. By depositing a film on the back side of the substrate, this warping can be counteracted, and the deposition area on the same substrate can be increased.

[0003] The background and contextual descriptions included herein are provided solely for the purpose of providing an overall context for the disclosure. The majority of this disclosure presents the inventors' research, and the mere fact that such research is described in the background section or presented as context elsewhere in this disclosure does not mean that such research is considered prior art. [Overview of the Initiative]

[0004] In one aspect of the present disclosure, a carrier ring is disclosed. In some embodiments, the carrier ring is configured to support a semiconductor substrate and includes a ring defining a plane having an outer portion and an inner portion, the inner portion having an inner circumference having a first diameter of about 298.4 to 299.5 millimeters (mm); and a plurality of inwardly extending tabs disposed around the inner circumference of the inner portion of the ring, the plurality of inwardly extending tabs having inner edges defining a circle having a second diameter of about 296.0 to 298.5 mm.

[0005] In some variations, the first diameter of the inner portion of the ring is approximately 299.0 mm, and the second diameter of the multiple inwardly extending tabs is approximately 297.0 mm.

[0006] In some variants, the multiple inwardly extending tabs comprise at least eight inwardly extending tabs.

[0007] In some variants, at least one of the multiple inwardly extending tabs has a width of approximately 0.5 to 1.5 mm.

[0008] In some variants, the width of at least one of the multiple inwardly extending tabs is approximately 1.0 mm.

[0009] In some variations, at least one of several inwardly extending tabs comprises at least a portion of the upper surface having an angle that is neither parallel nor perpendicular to the plane.

[0010] In some variants, the angle of the aforementioned portion of the upper surface is between approximately 5 and 20 degrees relative to the plane.

[0011] In some variants, the upper surface of at least one of the multiple inwardly extending tabs has a minimum contact area (MCA) configured to physically contact the semiconductor substrate.

[0012] In some variants, the outer portion is approximately 0.3–0.7 mm thick, while the inner portion is approximately 0.1–0.5 mm thick.

[0013] In some variations, at least a portion of a plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring is configured to form one or more conductive grounding points on the semiconductor substrate.

[0014] In some embodiments, the carrier ring is configured to support a semiconductor substrate, and the carrier ring is a ring having an inner portion configured to support the semiconductor substrate during back-side deposition on the semiconductor substrate, comprising a ring defining a plane, and 8 to 15 inwardly extending tabs disposed around the inner portion of the ring and configured to contact the semiconductor substrate during back-side deposition on the semiconductor substrate, at least one of the 8 to 15 inwardly extending tabs having a width of about 0.5 to 1.5 mm.

[0015] In some variations, at least one of the 8 to 15 inwardly extending tabs has an upper surface that is angled at about 15 degrees or less with respect to the plane.

[0016] In some variations, 8 to 15 inwardly extending tabs have an inner edge defining a first diameter of approximately 296.0 to 298.5 mm, and 8 to 15 inwardly extending tabs have an outer edge attached to the ring and defining a second diameter of approximately 298.4 to 299.5 mm.

[0017] In some variants, at least a portion of the 8 to 15 inwardly extending tabs are configured to allow the formation of one or more conductive grounding points on the semiconductor substrate.

[0018] Another aspect of the present disclosure discloses a method for depositing one or more layers on the back side of a semiconductor substrate. In some embodiments, the method includes (a) supporting a semiconductor substrate on a carrier ring, the carrier ring being a defining plane ring having an outer portion and an inner portion, the inner portion having an inner circumference having a first diameter of about 298.4 to 299.5 millimeters (mm), and a plurality of inwardly extending tabs disposed around the inner circumference of the inner portion of the ring, the plurality of inwardly extending tabs having inner edges defining circles having a second diameter of about 296.0 to 298.5 mm, and (b) exposing the back side of the semiconductor substrate to process conditions that cause one or more layers to be deposited on the back side of the semiconductor substrate.

[0019] In some variants, the process conditions that cause the deposition of one or more layers include exposure to at least one chemical precursor of the one or more layers.

[0020] In some variants, at least one of one or more layers on the back side of the semiconductor substrate comprises polysilicon, silicon oxide, silicon nitride, or any combination thereof.

[0021] In some variations, the first diameter of the inner portion of the ring is approximately 299.0 mm, and the second diameter of the multiple inwardly extending tabs is approximately 297.0 mm.

[0022] In some variations, the multiple inwardly extending tabs comprise at least eight inwardly extending tabs, with at least one of the eight inwardly extending tabs having a width of approximately 0.5 to 1.5 mm.

[0023] In some variations, at least one of several inwardly extending tabs comprises at least a portion of an upper surface having an angle that is neither parallel nor perpendicular to the plane, and the angle is approximately 5 to 20 degrees with respect to the plane.

[0024] These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] [Figure 1A] 1 is a block diagram illustrating a substrate processing system used to perform processing on a substrate according to some embodiments. [Figure 1B] FIG. 2A is a block diagram illustrating a substrate processing system used to perform processing on a substrate according to some embodiments.

[0026] [Figure 2A] 2B is a simplified diagram of a carrier ring and tab locations according to some embodiments.

[0027] [Figure 2B] 3 is a graph of film thickness versus exemplary angular position of the carrier ring of FIG. 2A.

[0028] [Figure 3A] FIG. 4 is a diagram illustrating a semiconductor substrate and various concentric radial points.

[0029] [Figure 3B] FIG. 5 is a map showing a map of exemplary radial data points.

[0030] [Figure 3C] FIG. 6 is a table showing exemplary average thicknesses of deposited films at various radii.

[0031] [Figure 3D] FIG. 7 is a graph illustrating the difference between an exemplary maximum average film thickness and an exemplary film thickness along the angular position of a circle defined by a given radius.

[0032] [Figure 3E]A graph is shown illustrating the exemplary level difference along angular position, determined by subtracting an exemplary given film thickness from an exemplary maximum average film thickness.

[0033] [Figure 4] This graph shows an example of the change in thickness difference with respect to radius of a substrate placed on a carrier ring.

[0034] [Figure 5A] This is a simplified diagram showing the components of a substrate processing system according to several embodiments.

[0035] [Figure 5B] This is an enlarged view of the cross-sectional portion of the carrier ring shown in Figure 5A, according to several embodiments. [Figure 5C] This is an enlarged view of the cross-sectional portion of the carrier ring shown in Figure 5A, according to several embodiments.

[0036] [Figure 6A] This is a perspective view of a carrier ring according to several embodiments.

[0037] [Figure 6B] This is a top-down view of the carrier ring in Figure 6A, according to several embodiments.

[0038] [Figure 6C] Figure 6A is a top-down enlarged view of the carrier ring tab according to several embodiments.

[0039] [Figure 6D] Figure 6C shows a perspective view of a tab according to several embodiments.

[0040] [Figure 6E] Figure 6C shows cross-sectional views of the tab and carrier ring across a section according to several embodiments.

[0041] [Figure 6F]Figure 6C shows cross-sectional views of non-tab positions and carrier rings across different sections according to several embodiments.

[0042] [Figure 7] This figure shows an exemplary embodiment with various optimizations related to at least one tab of the carrier ring.

[0043] [Figure 8] This figure shows a comparison between existing carrier rings and tabs and exemplary carrier rings and tabs disclosed herein, in tab and non-tab positions, according to several embodiments.

[0044] [Figure 9] This is a diagram of a semiconductor wafer arranged on a carrier ring having multiple tabs, according to several embodiments.

[0045] [Figure 10] This is a diagram of a processed substrate that can be clamped onto a base chuck, according to several embodiments.

[0046] [Figure 11] This flowchart illustrates a method for obtaining a device configured to support a semiconductor substrate, according to several embodiments.

[0047] [Figure 12] This flowchart illustrates a method for depositing one or more layers on the back side of a semiconductor substrate, according to several embodiments. [Modes for carrying out the invention]

[0048] This disclosure relates to carriers used for semiconductor processing.

[0049] The dimensions of features fabricated on a wafer substrate (e.g., lines, traces, circuits) can easily become distorted based on slight positional or warpage deviations of the substrate, as the features (which can reach the nanometer scale) may require precise processing. Furthermore, such substrates are generally thin and susceptible to internal stresses or tensile / compressive stresses, especially during the fabrication process (deposition, etching, heating, layering, etc.). Additionally, some processing steps (e.g., photolithography) are extremely precise, and if the substrate is not substantially flat, unsatisfactory results can occur. The problem arises as lithographic focus blur. Appear Warping can occur, especially when large stacks of material are deposited, in the context of, for example, 3D NAND (three-dimensional negative AND) devices and types of non-volatile flash memory where memory cells are stacked in multiple layers. If the warping is significant, it can have detrimental effects on subsequent processing steps. For example, if the warping is too great, the substrate may fail to chuck properly.

[0050] One exemplary stack that may cause these problems is one having alternating layers of oxides and nitrides (e.g., silicon oxide, silicon nitride, silicon oxide, silicon nitride). Another exemplary stack that may cause warping includes alternating layers of oxides and polysilicon (e.g., silicon oxide, polysilicon, silicon oxide, polysilicon). Other examples of stack materials that may cause problems include, but are not limited to, tungsten and titanium nitride. The materials in the stack may be deposited by chemical vapor deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD), etc. These examples are not limited to.

[0051] Several techniques devised to prevent warping involve modifying the deposition process to reduce or offset internal stresses in the deposited layer. For example, some processes involve depositing a film on the back side of the substrate, such as depositing a high-stress dielectric film using chemical vapor deposition (CVD) on the back side of the substrate. If the back side film has internal stresses of the same type (tensile or compressive) as the internal stresses on the front side, and of a magnitude equivalent to the internal stresses on the front side, the back side film effectively offsets and compensates for the warping. As a result, the substrate may have a more neutral warp, which means the substrate will be flatter with less warping.

[0052] The material deposited on the back of the substrate may, in various embodiments, be a dielectric material. In some cases, oxides and / or nitrides (e.g., silicon oxide / silicon nitride) may be used. Examples of silicon-containing reactants that may be used include, but are not limited to, silanes, halosilanes, and aminosilanes. Silanes contain hydrogen and / or carbon groups but do not contain halogens. Examples of silanes include silane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, texylsilane, isoamylsilane, t-butyldisilane, and di-t-butyldisilane. Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes include iodosilane, bromosilane, chlorosilane, and fluorosilane. Halosilanes, and especially fluorosilanes, can form reactive halide species that can etch silicon materials, although in some embodiments described herein, silicon-containing reactants are absent when the plasma is impacted. Specific chlorosilanes include tetrachlorosilane (SiCl4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), monochlorosilane (ClSiH3), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, and texyldimethylchlorosilane. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon.Examples of aminosilanes include mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted mono-, di-, tri-, and tetra-aminosilanes, such as t-butylaminosilane, methylaminosilane, tert-butylsilaneamine, and bis(tertiary butylamino)silane (SiH2(NHC(CH3)3). 2) Examples include (BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, and (Si(CH3)2NH)3. A further example of aminosilane is trisilylamine (N(SiH3)). Other potential silicon-containing reactants include tetraethyl orthosilicate (TEOS), tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethylcyclotetrasiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisilazane (HMDS), hexamethyldisiloxane (HMDSO), hexamethylcyclotrisiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisiloxane (TMDSO), divinyltetramethyldisiloxane (VSI2), and methyltriethoxysilane (MTE). This includes cyclic and acyclic TEOS variants such as OS, dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisilane (HMODS), bis(triethoxysilyl)ethane (BTEOSE), bis(trimethoxysilyl)ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetrakis(trimethylsiloxy)silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS), or tetrapropoxysilane (TPOS).

[0053] Exemplary nitrogen-containing reactants include, but are not limited to, ammonia, hydrazine, and amines (e.g., carbon-bearing amines) such as methylamine, dimethylamine, ethylamine, isopropylamine, t-butylamine, di-t-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isoamylamine, 2-methylbutan-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, and di-t-butylhydrazine, as well as aromatic-containing amines such as aniline, pyridine, and benzylamine. The amines may be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). Nitrogen-containing reactants may contain heteroatoms other than nitrogen; for example, hydroxylamine, t-butyloxycarbonylamine, and Nt-butylhydroxylamine are nitrogen-containing reactants.

[0054] Examples of oxygen-containing co-reactants include oxygen, ozone, nitrous oxide, carbon monoxide, nitric oxide, nitrogen dioxide, sulfur oxide, sulfur dioxide, oxygen-containing hydrocarbons (CxHyOz), water, and mixtures thereof.

[0055] In modern semiconductor processing equipment, the substrate may rest on a pedestal during semiconductor processing. The pedestal may be a so-called shower pedestal, which is a pedestal-like structure having numerous gas distribution ports distributed across its upper surface (similar to a showerhead with several gas distribution ports distributed across its underside). The gas distribution ports may be fluidically connected to one or more plenums located within the shower pedestal. These one or more plenums may be fluidically connected to one or more processing gas sources, which may be controllable to allow processing gases to flow from the shower pedestal through their gas distribution ports.

[0056] Such a semiconductor processing tool may also have one or more carrier ring supports, which may be configured to support carrier rings, and which may support a substrate during processing operations. One or more carrier ring supports may be designed to allow the carrier rings and any substrates thereby supported to be held in an elevated location above the shower base, so that there is a gap between the shower base and the substrate, to which processing gases can be delivered. Thus, such a semiconductor processing tool allows the underside of the substrate to undergo the substrate processing operation instead of the upper side of the substrate, enabling the deposition of a film on the underside of the substrate.

[0057] However, carriers may include tabs, which interfere with back-side film deposition on the substrate area overlapping with the tabs. To enable the fabrication of additional or larger components, it is desirable to maximize or optimize the available space for deposition. Even an increase of a few square millimeters on the back side of a 200, 300, or 450 mm substrate can improve space efficiency for fabrication.

[0058] Therefore, a carrier is desired that possesses physical characteristics that balance size, shape, quantity, and other parameters related to the carrier tab.

[0059] The following terms will be used throughout this specification.

[0060] As used herein, “wafer warping” may refer to deformation of a substrate or wafer. Wafer warping can occur during fabrication, for example, as a result of stress on the substrate during material deposition on the active surface of the substrate. Wafer warping can occur during various types of fabrication, such as when large stacks of material are deposited. Wafer warping can cause troublesome problems in subsequent processing steps. For example, if the amount of warping is too large, the substrate may fail to chuck properly. Furthermore, some processing steps (e.g., photolithography) may yield unsatisfactory results if performed on an excessively warped substrate.

[0061] Wafer warpage can be measured as the deviation of the mean or median distance of the substrate surface relative to a reference plane. The point on the central surface of the substrate may be the center point (for example, in the case of concave or domed warpage) or the edge point of the substrate and / or the mean edge point of the substrate (for example, in the case of distorted or convex warpage).

[0062] As used herein, “platen” refers to the upper surface of the electrostatic chuck (ESC) on which the fabricated substrate or wafer is placed. A gap may exist between the substrate and the platen surface (e.g., the upper surface), which is generally referred to herein as “d”.

[0063] As used herein, “base” may refer to a structure or housing that supports or includes a platen.

[0064] The terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” may be used interchangeably. Those skilled in the art will understand that the term “partially fabricated integrated circuit” may refer to a semiconductor wafer in any of the many stages of integrated circuit fabrication on a semiconductor wafer. Wafers or substrates used in the semiconductor device industry generally have a diameter of 200 mm, 300 mm, or 450 mm. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include a variety of articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices, or components such as backs for pixelated display devices, flat panel displays, and micro-mechanical devices. Workpieces may be of various shapes, sizes, and materials.

[0065] As used herein, “semiconductor device fabrication operations” refer to operations performed during the fabrication of a semiconductor device. As referred to herein, such fabrication operations may be simply called “processes” or “treatments.” Examples of treatments include the deposition of material on a substrate, the selective etching of material from a substrate, and the ashing of photoresist on a substrate. Generally, an overall fabrication process comprises several semiconductor device fabrication operations, each of which is performed in its own semiconductor fabrication tool, such as a plasma reactor, electroplating cell, chemical mechanical planarization tool, or wet etching tool. Categories of semiconductor device fabrication operations include subtractive processes, such as etching and planarization processes, and additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processes, a substrate etching process includes the process of etching a mask layer, or, more generally, the process of etching any layer of material that has been previously deposited on the substrate surface and / or otherwise exists on the substrate surface. Such an etching process can etch a stack of layers in the substrate.

[0066] "Manufacturing equipment" refers to equipment in which a manufacturing process is carried out. Manufacturing equipment often has a processing chamber in which a workpiece is located during processing. Generally, when in use, manufacturing equipment performs one or more semiconductor device fabrication operations. Examples of manufacturing equipment for semiconductor device fabrication include deposition reactors such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and removal process reactors such as dry etching reactors (e.g., chemical and / or physical etching reactors), wet etching reactors, and ashers.

[0067] As referred to herein, manufacturing equipment is sometimes simply called a “process chamber.” In various embodiments, a process chamber is generally a sealed enclosure in which a substrate is held in place during processing. A process chamber may include components related to the supply and removal of gases. A process chamber may also include components related to generating plasma and controlling the properties of the plasma within the chamber. A process chamber may include components for controlling pressure, including drawing a vacuum into the chamber. In the context of this disclosure, a process chamber may include a pedestal in which a substrate is positioned while it is being processed. The pedestal may be equipped with a chuck, such as an ESC, to hold the substrate in place during processing. PCB processing system

[0068] Figure 1A is a block diagram showing a substrate processing system 100 used to perform processing on a substrate 128 (also called a wafer), according to several embodiments. As shown, the substrate processing system may include a chamber 102. A central row may be configured to support a pedestal when the upper surface of the substrate 128 is being processed, for example, when a film is formed on the upper surface of the substrate 128 or on the back side of the substrate 128. The pedestal may be referred to as a showerhead pedestal ("show-ped") 106 according to some embodiments disclosed herein. A showerhead 104 may be disposed on the show-ped 106.

[0069] In some embodiments, the showerhead 104 may be electrically coupled to a power supply 122 via a matching network 125. The power supply 122 may be controlled by a control module 120, for example, a controller. In some embodiments, power may be supplied to a show-ped 106 instead of the showerhead 104. The control module 120 may be configured to operate the substrate processing system 100 by performing process inputs and controls for a specific process recipe. Depending on whether the upper surface of the substrate 128 is receiving the deposition film or the lower surface of the substrate 128 is receiving the deposition film, the controller ru Module 120 can configure various operational inputs for the process recipe, such as power level, timing parameters, process gas, mechanical movement of the substrate 128, and / or height of the substrate 128 relative to the show-ped 106.

[0070] In some embodiments, the center row may also include lift pins controlled by lift pin control. Such lift pins may be used to raise the substrate 128 from the show-ped 106 to allow an end effector (not shown) to take the substrate 128, and to lower the substrate 128 after it has been placed by the end effector. The end effector may also place the substrate 128 on a spacer 130. As described below, the spacer 130 may be sized to provide controlled separation of the substrate 128 between the upper surface of the showerhead 104 (facing the substrate 128) and the upper surface of the show-ped 106 (facing the substrate 128).

[0071] In some embodiments, the substrate processing system 100 may further include a first gas manifold 108 connected to a first gas source 110, for example, a chemistry supply and / or inert gas from the facility. Depending on the processing being carried out on the upper surface of the substrate 128, the control module 120 may control the delivery of the first gas source 110 through the first gas manifold 108. The selected gas is then supplied to the showerhead 104 Swept insideWhen the substrate 128 is placed on the base, it can be distributed into the spatial volume defined between the substrate 128 and the surface of the shower head 104 facing it.

[0072] In some embodiments, the substrate processing system 100 may further include a second gas manifold 112 connected to a second gas source 114, for example, a supply of gaseous chemicals from the facility and / or an inert gas. Depending on the processing being carried out on the lower surface of the substrate 128, the control module 120 may control the delivery of the second gas source 114 through the second gas manifold 112. The selected gas is then blown to a showerhead 104 and distributed into a defined spatial volume between the lower surface or underside (e.g., back side) of the substrate 128 and the surface of the show-ped 106 facing the substrate 128 when the substrate 128 is resting on the spacer 130. The spacer 130 may provide separation that optimizes deposition on the lower surface of the substrate 128 while reducing deposition on the upper surface of the substrate 128. In some embodiments, while deposition is targeting the lower surface of the substrate 128, an inert gas may be blown over the upper surface of the substrate 128 via a showerhead 104, which pushes the reaction gas away from the upper surface, allowing the reaction gas supplied from the show-ped 106 to be directed towards the lower surface of the substrate 128.

[0073] Furthermore, the gas may or may not be premixed. Appropriate valve adjustment and mass flow control mechanisms may be employed to ensure that the correct gas is delivered during the deposition and plasma processing phases of the process. The process gas may exit chamber 102 through the outlet. A vacuum pump (e.g., a one- or two-stage mechanical dry pump and / or turbomolecular pump) may draw the process gas, and a closed-loop controlled flow limiting device, such as a throttle valve or pendulum valve, maintains a sufficiently low pressure in the reactor.

[0074] In some embodiments, the carrier ring 124 may surround the outer region of the show-ped 106. When the upper surface of the substrate 128 is being processed, for example, when material is being deposited on the substrate 128, the carrier ring 124 may be configured to rest on a carrier ring support region that is one step lower than the wafer support region at the center of the show-ped 106. The upper surface of the carrier ring 124 is generally coplanar with the upper surface of the substrate 128. The carrier ring 124 may include an outer edge side of the disk structure of the carrier ring 124, for example, an outer radius, and an inner radius on the wafer edge side of the disk structure of the carrier ring 124, for example, the inner radius closest to where the substrate 128 rests. The carrier ring 124 may have an inner diameter (ID). The ID extends to the inner circumference of the carrier ring and generally surrounds the substrate (e.g., substrate 128) in the processing chamber. The wafer edge side of the carrier ring 124 may also include a plurality of contact support structures or “tabs,” which may be configured to lift the substrate 128 when the carrier ring 124 is held by the spacer 130. The carrier ring 124 may include a plurality of tabs in an amount selected from a range to support the substrate 128 during processing (for example, six tabs are shown in Figure 2A, which is described below). Additional details regarding embodiments of the tabs are as follows:

[0075] Figure 1B is a block diagram showing another substrate processing system 150 used to perform processing on a substrate 128 according to several embodiments. In some embodiments, a spider fork 132 may be used to lift a carrier ring 124 and maintain it at its processing height, for example, to allow deposition on the underside (back side) of the substrate 128. Thus, the carrier ring 124 may be lifted together with the substrate 128. In some configurations, the carrier ring 124 may be rotated to another station, for example, in a multi-station system. Film thickness variation

[0076] Figure 2A is a simplified diagram of the location of the carrier ring 200 and tabs 202 in several embodiments. In some embodiments, six tabs 202 may be arranged around the inner circumference of the carrier ring 200. The carrier ring tabs may create a "shadow" where the back deposit layer is not deposited on the substrate placed on the carrier ring, or the back deposit layer is deposited less on the area outside the tab shadow than on the area outside the tab shadow.

[0077] In some embodiments, the carrier ring 200 may have an internal dimension 204, for example, 299.0 mm. In some embodiments, a notch tab 206 may be present. The notch tab 206 may help prevent plasma from reaching the front side of the substrate because the substrate generally contains wafer notches that can be susceptible to such leakage. The notch tab 206 may help align the semiconductor substrate with the carrier ring so that the substrate is in a desired orientation (for example, for the plasma blocking described above) before processing is performed on the substrate. The processing may, for example, deposit a film on the back side of the substrate, as described elsewhere in this specification.

[0078] Figure 2B is a graph of the film thickness against exemplary angular positions of the carrier ring 200. The film thickness may not be uniform across the substrate surface. In particular, at the six angular positions corresponding to the locations of the six tabs 202 in Figure 2A, the deposited film thickness is relatively smaller. In this case, the six tabs significantly reduced the film thickness at the substrate edges, as indicated by box 220.

[0079] As shown in Figures 2A and 2B, the interference to deposition induced by tab 202 presents an opportunity to increase the amount of deposition, for example, by allowing more processing gas to diffuse beneath the tab. Increasing the amount of deposition offers advantages such as greater use of the substrate during processing (reduced shadowing effects, as well as more space- and cost-effective use of the "real estate") and / or reduced impedance fluctuations in carriering.

[0080] Figure 3A shows a semiconductor substrate 300 and various concentric radial points. For example, the first radial point 302 is r1 mm from the center point of the semiconductor substrate 300, and the second radial point 304 is r from the center point. 17 It is mm. The third radial point 306 is r6 mm from the center point. In Figure 3A, from the radius r1 mentioned above, r 17 Range up to the radius During Various other radial points may be observed. In one scenario, thickness variations and local deviations from planarity may occur, typically starting at a radius of r1 mm. r1, r6, and r 17 This represents the radius from the center point of the semiconductor substrate 300. Exemplary values ​​for these radii can range from 120 mm to 148.2 mm, but countless different values ​​and ranges (e.g., below 120 mm and / or above 148.2 mm) may be evaluated depending on the semiconductor substrate and its mounting configuration.

[0081] Figure 3B is a map 310 showing an exemplary radial data point map defined by xy coordinates, with its center at the origin 312 of a circle corresponding to the shape of the semiconductor substrate 300. 17 A second radial point 304 corresponding to a radius of mm can also be seen in Figure 3B.

[0082] Figure 3C is Table 320, which shows exemplary average thicknesses of deposited films at various radii. For example, suppose the average deposition thickness is determined to be 6138 arbitrary units (e.g., nanometers (nm)) at a radius of r6 mm. The film thickness can be measured using conventional means or measuring tools, such as spectroscopic ellipsometry, thickness monitors, interferometers, surface profilers, or scanning electron microscopy. In particular, in this example, the average thickness of r6 = 6138 arbitrary units is r1 mm ~ r 17 This is the highest of all average thicknesses measured from a radius of mm.

[0083] Figure 3D is a graph 330 showing the difference between an exemplary maximum average film thickness 332 and a given film thickness 334 along the angular position of a circle defined by a given radius along the carrier ring. In the example of Figure 3D, for comparison with the exemplary maximum average film thickness 332(r6), r 17 A radius of mm, i.e., the measured outermost radius, was selected. Graph 330 shows the exemplary maximum average film thickness 332 as a dotted line and a given film thickness 334 as a solid line representing data points (corresponding to, for example, map 310 shown in Figure 3B), where the data points correspond to the measured thickness (in degrees) at each radial position. The given film thickness 334 shows that the thickness may be relatively smaller at angular positions corresponding to tabs (for example, tab 202 shown in Figure 2A). The r6 mm and r of the substrate 17 A simplified diagram 340 showing two radii in mm is also provided.

[0084] Using the data described above, for example, data points related to map 310, data points related to table 320, and / or data points related to graph 330, the “level difference” (D) between the maximum average film thickness and a given film thickness 334 can be measured. Existing measurement techniques only measure the percentage of non-uniformity or average film thickness, and may provide an aggregate measure of uniformity. The level difference shows the film thickness delta at individual points and may be a clearer indication of the severity of how wide the range of thickness can be. Figure 3E shows an exemplary maximum average film thickness 332 from Graph 350 shows an exemplary level difference along the angular position, determined by subtracting a given film thickness 334. The solid line 351 showing the level difference clearly highlights the delta between the angular positions corresponding to the tab, where the peak 354 is located.

[0085] Performing photolithography or other downstream processes that rely on substrate uniformity, where there is little or no deviation from strict planarity anywhere on the substrate, can introduce errors, particularly in areas of the substrate where less backing material is deposited. Therefore, it is desirable to maintain a level difference below a certain amount. In some exemplary applications, it may be specified that the level difference should remain below a specified amount in arbitrary units, for example, below dashed line 352. One such example may be 700 nm. If the level difference is measured to exceed a certain amount (e.g., peak 354 where the tab is located if D exceeds dashed line 352 or another threshold level), the above "level difference" problem may indicate that the resulting substrate has non-uniform film deposition and / or unrealized deposition potential at its tab locations. In some cases, depending on the application, the configuration of the tabs and / or carriers (e.g., quantity, physical shape), and / or the post-processing of the resulting warpage, a level difference exceeding a certain amount (e.g., dashed line 352) may result in substrate yield loss and / or slower processing (e.g., slower lithography process), which can be costly or time-consuming and therefore undesirable.

[0086] Further, FIG. 4 is a graph 400 showing an exemplary variation of thickness difference with respect to the radius of a substrate placed on a carrier ring. As shown, the film thickness for the central portion of the substrate (e.g., beyond radius r1 mm) may decrease more rapidly (the "derivative" of the thickness change) as the radius approaches the far edge of the substrate (e.g., r 17 radius close to mm). A portion of the carrier ring (e.g., the portion that the substrate may abut) may, for example, at least partially physically block the reaction with the deposition gas. In some cases, the thickness may drop to zero at the very edge of the substrate (e.g., r edge near a radius of mm). In addition to the aforementioned problem of level difference spiking at the tab location (thickness variation with respect to radial position), the reduction in thickness near the edge of the substrate (the "edge effect" of thickness variation with respect to radial distance) can lead to non-uniform film thickness. However, it is desirable to keep the film thickness consistent across the entire radius of the substrate during substrate processing.

[0087] Accordingly, the present disclosure specifically describes optimized carrier rings and related structures (e.g., tabs) that minimize the substrate contact area (which increases the deposition area near the substrate edge, thus increasing film thickness uniformity) and minimize edge effects. Carrier Ring Configuration

[0088] Figure 5A is a simplified diagram showing the components of a substrate processing system 500 according to several embodiments. In some embodiments, the substrate processing system 500 may be an example of the substrate processing system 100 or 150. The substrate processing system 500 may include a shower head 502 disposed on a show-ped 504. A carrier ring 506 may be disposed between the shower head 502 and the show-ped 504 and may have a ring-shaped structure. Cross-sections of the carrier ring 506 are shown in Figure 5A, along with cross-sectional portions 506a (also labeled "A") and 506b (also labeled "B"). These cross-sectional portions may be symmetrical, and the dimensions of the cross-sectional portions may be applied substantially equally to any cross-section. For example, cross-sectional portion 506a may have a thickness of about 0.1 to 0.5 mm (for example, 0.3 mm in some embodiments) around the entire circumference of the carrier ring 506, and cross-sectional portion 506b The carrier ring 506 may have a thickness of 0.3 to 0.7 mm (for example, 0.5 mm in some embodiments) around its entire circumference. The carrier ring 506 may have an inner diameter (ID) 508 and an outer diameter (OD) 510, allowing a substrate (for example, a wafer 512) to be placed on the carrier ring 506, for example, above portion "A" and in contact with portion "B". The wafer 512 may have a circular shape to fit the carrier ring 506. Plasma 514 may be formed or extinguished beneath the wafer 512.

[0089] In some embodiments, the carrier ring ID 508 can be selected from a diameter of 298.4 to 299.5 mm. For example, in some cases, the carrier ring ID 508 may have a diameter of 299.0 mm. Thus, in the case of a 299.0 mm carrier ring ID, a 300 mm wafer rests on the carrier ring 506, and a large portion of the back surface of the wafer can be exposed for processing (backside deposition, etching, etc.).

[0090] Figures 5B and 5C are enlarged views of cross-sectional portions of the carrier ring 506 according to several embodiments. In some portions of the carrier ring 506, the inner diameter includes a tab 506c, as shown in Figure 5B. In some embodiments, the tab 506c may be a support structure for the wafer 512. The tab 506c may, for example, prevent the wafer 512 from falling through the carrier ring 506. In some configurations, the tab 506c may have an inclined or tapered surface at an angle 520 with respect to one or more of the upper surfaces 516a, 516b of the cross-sectional portions 506a, 506b. In various configurations, the angle 520 may not be parallel or perpendicular to the plane associated with the upper surface 516a or 516b (or both). In some cases, the angle 520 is between about 5 and 20 degrees from the plane 518 defined by the upper surface 516a, for example, less than about 15 degrees, for example, about 11.1 degrees. The upper surface 516a from which the tab extends inward may interface with the wafer 512 (for example, it may be supported via physical contact with the wafer 512).

[0091] In some implementations, multiple tabs may be arranged around the inner diameter of the carrier ring 506. Furthermore, the multiple tabs may be inwardly extending tabs with outer edges that are attached to the ring and define the inner diameter. In some cases, the inner diameter is selected from a range of 296.0 to 299.5 mm, for example, 297.0 mm. The number of multiple tabs may be selected to ensure that when the wafer 512 is placed on the carrier ring 506, the wafer 512 does not fall through the carrier ring 506 (for example, if one or more of the tabs are deformed or broken) and does not result in tilting of the wafer 512 (for example, an amount selected from a range of at least 8, or at least 5 to as many as 15, or at least 8 to as many as 15, for example, 12). It is essential to keep the wafer perfectly horizontal, as processing on a tilted wafer may partially or completely render the resulting deposition, etching, etc., unusable. For example, a good image may not be obtained for lithography, and line width may be lost. If there are fewer than a certain number of tabs (e.g., three or four), the carrier ring 506 may be further exposed to the risk of tilting or falling through when moved. If there are more than a certain number of tabs (e.g., fifteen), excessive diminishing returns may be incurred for the carrier ring 506 due to unnecessary obstruction of surface area (e.g., for back deposition) and / or unnecessary manufacturing costs.

[0092] As shown in Figure 5C, in some parts of the carrier ring 506, the inner diameter does not have a tab, as indicated by the cross-sectional portion 506a having a relatively untapered surface. However, in some embodiments, the cross-sectional portion 506a may have an angled portion 522. As shown in Figure 5B, the position containing the tab may have an angled portion that extends to the tab 506c.

[0093] Figure 6A is a perspective view of the carrier ring 600 according to several embodiments. In some embodiments, the carrier ring 600 may be an example of the carrier ring 506 described with respect to Figure 5A. The carrier ring 600 may have an inner diameter 602 measured between one end of the inner circumference 604 and the opposite end of the inner circumference 604. The inner circumference 604 may be defined by the inner wall of the inner portion of the carrier ring 600, where the cross section 506a is an example of the inner portion. In some implementations, the inner diameter 602 may be selected from the range of 298.4 mm to 299.5 mm. An example of an inner diameter 602 may be 299.0 mm.

[0094] Figure 6B is a top-down view of a carrier ring 600 according to several embodiments. The inner diameter 602 of the carrier ring 600 may extend between opposite ends of the inner circumference 604, as also shown in Figure 6A. In some embodiments, multiple inwardly extending tabs, such as tab 606, may be arranged around the inner circumference 604 (of the inner portion) of the carrier ring 600 and separated by non-tab positions 607. The majority of the inner circumference may be tab-free and have a non-tab cross-sectional configuration, as shown in Figure 5C.

[0095] In various implementations of the carrier ring 600, 5 to 15 tabs may extend inward from the inner circumference 604 of the carrier ring 600. For example, in one such implementation, 12 tabs may be arranged around the inner circumference 604. In some cases, the tabs may be spaced substantially equally apart from one another. However, in some cases, the tabs may be spaced apart at predetermined positions where they are not equally distanced from one another. For example, the tabs may be grouped together into two groups and placed at six equidistant and / or equiangled positions. In other cases, other grouping schemes may be possible, such as three, four, or six equal or unequal groups.

[0096] Figure 6C is a top-down enlarged view of the tab 606 in some embodiments. Figure 6D is a perspective view of the tab 606 in some embodiments. In some embodiments, the tab 606 extends or protrudes inward to at least partially support or provide support to a semiconductor substrate, such as a wafer 512. Figure 6E is a cross-sectional view of the tab 606 and carrier ring 600 across section AA of Figure 6C in some embodiments.

[0097] In some embodiments, the tab 606 may have an inclined upper surface that results in an angle with respect to a plane defined by the upper surface of the inner circumference 604. In some configurations, the angle may be about 11.1 degrees. This angle may be selected from a range, for example, 5 to 20 degrees including both ends, or 10 to 12 degrees including both ends. In other configurations, the angle may not be parallel or perpendicular to the plane, and may be an angle selected from, for example, 15 degrees or less, or 10 degrees or less. The inclined surface of the tab may allow, for example, the deposition gas to reach the back surface of the substrate. In some cases, several tabs may have different angles from each other. For example, at least one of the tabs may be inclined at 11.1 degrees from the plane, and at least another of the tabs may be inclined at 5 degrees from the plane. In some cases, the angle may be shaped to be non-uniform over the length of the tab. The angle may be measured at the base of the tab closest to the inner diameter of the carrier ring. In some cases, some tabs may not have an inclined upper surface, in which case the non-inclined tabs may be placed at a lower height than the inclined tabs to prevent direct contact between the non-inclined tabs and the substrate.

[0098] In some embodiments, the tab may have an inner diameter selected from the range of 296.0 to 299.5 mm, for example, 297.0 mm. In some cases, the inner diameter of the tab may be defined by the inner edge of the tab defining a circle, i.e., the inner edge defining the circle may have a diameter of 296.0 to 299.5 mm, for example, about 296.0 to 298.5 mm, for example, 270.0 mm. In some embodiments, the tab 606 may have a maximum length of 10.0 mm (for example, length 608 shown in Figure 6E). That is, in some implementations, the tab 606 may have lengths less than 10.0 mm, for example, 2.0 mm, 1.5 mm, and 1.0 mm. In some cases, several tabs may have different lengths from each other. For example, at least one of the tabs may be 2.0 mm long and at least another of the tabs may be 1.5 mm long.

[0099] In some embodiments, the tab 606 may have a maximum width of 2.0 mm. That is, in some mounting configurations, the tab 606 may be less than 2.0 mm, for example, 0.5 mm. From mm The width can be, for example, 1.0 mm, within a range of 1.5 mm. In some embodiments, the tab 606 may have a minimum width of about 0.5 mm. In some cases, several tabs may have different widths from one another. For example, at least one of the tabs may be 1.0 mm wide and at least another of the tabs may be 0.7 mm wide. In some cases, the width may not be uniform over the length of the tab. The width may be measured at the terminating end portion of the tab, and the tab may be wider or narrower than, for example, 1.0 mm along its length.

[0100] Figure 6F is a cross-sectional view of the non-tab position 607 and carrier ring 600 across the cross-section BB in Figure 6C, according to several embodiments. In some embodiments, the inner circumference may include an angled portion in at least one of the edges, such as the angled portion 522 shown in Figure 5C.

[0101] In different mounting configurations of the carrier ring 600 or inwardly extending tabs (e.g., tab 606), the amount of tabs, tab angles, inner diameter of the carrier ring, tab length, and / or tab width may be selected based on the type of gas used, the presence of plasma, the need for substrate real estate, and / or the application example. The dimensions described above can be summarized as follows:

[0102] In some embodiments, the carrier ring 704 may have an inner diameter selected from a range of approximately 298.4 mm to 299.5 mm, for example, 299.0 mm. In some embodiments, the carrier ring 704 may include a plurality of tabs (one of the tabs is shown). In some configurations, the plurality of tabs may have an inner diameter selected from a range of 296.0 to 299.5 mm, for example, 297.0 mm. In some configurations, the number of plurality of tabs may be selected from a range of at least 5 to an upper limit of 15 (for example, 12), and beyond this, the tabs may cause diminishing returns. In some embodiments, the width of at least one tab 702 may be approximately 0.5 to 2.0 mm, for example, 1.0 mm. In some embodiments, the length of at least one tab 702 may have a maximum length of approximately 10.0 mm. In some configurations, the downward tilt angle of at least one tab 702 with respect to the upper surface may be selected from a range of 15 degrees or less, for example, 11.1 degrees. Figure 7 shows an exemplary embodiment with various optimizations related to at least one tab 702 of the carrier ring 704.

[0103] The above physical properties of the carrier ring 704 and / or at least one tab 702 of the carrier ring 704 may, in some cases, represent a reduction or increase in some dimensions or parameters related to the tab and the carrier ring. For example, the tab may have a larger inner diameter, the tab width and / or length may be reduced, and / or the tab may include a slanted portion to adapt to increased deposition, for example by allowing more processing gas to reach the back area. Furthermore, the carrier ring may have a larger inner diameter to minimize edge effects. However, smaller tabs and larger inner diameters may increase the potential for the substrate held and supported by the carrier ring 704 to become unstable and, for example, more prone to tilting. For example, there may be a greater potential for the substrate to tilt while being housed on the carrier ring or to fall through the inner circumference of the carrier ring. Therefore, to further adapt to potential risks, the number of tabs may be increased (for example, to 12) to prevent such risks.

[0104] In one exemplary embodiment, at least one tab 702 may have a width of about 1.0 mm, a length of about 2.0 mm, and a downward inclination angle of about 11.1 degrees. Furthermore, the carrier ring 704 may have an inner diameter of about 299.0 mm and 12 tabs arranged substantially equidistant and / or at substantially equal angles.

[0105] In other examples, the above considerations can be balanced. Consider a mounting configuration in which the width is selected to be slightly smaller (e.g., 0.8 mm wide). To accommodate smaller tabs, the number of tabs can be increased (e.g., to 14 or 15) to ensure, for example, that the substrate does not fall or tilt. Consider another mounting configuration in which a smaller inner diameter (e.g., 298.5 mm) is preferred. Assuming increased stability of the substrate, the angle can be increased significantly to ensure that the processing gas reaches the tab area. Each of these mounting configurations, as well as countless other combinations of these ring and tab characteristics, can contribute to reducing level differences, minimizing the substrate contact area (e.g., the minimum contact area described below), and ultimately minimizing edge effects (e.g., mitigating the transition of film thickness with respect to radial distance) and enabling a consistent film thickness. Furthermore, minimizing the substrate contact area based on the aforementioned physical properties of the tabs (including the selection of the inner diameter of the carrier ring, the inner diameter of the tabs, the amount of the tabs, the width of the tabs, the downward angle of the tabs, or a combination thereof) allows for more back-side deposition on the substrate (e.g., the location of the substrate corresponding to the tabs) compared to another carrier ring having tabs that do not have these physical properties. For example, the tabs of the other carrier ring (without the aforementioned physical properties) would be larger and therefore, for example, reduce back-side deposition. Figure 7 shows a comparison with increasing the inner diameter of at least one tab 702 and decreasing the width of at least one tab 702.

[0106] Figure 8 shows a comparison between existing carrier rings and tabs and exemplary carrier rings and tabs disclosed herein in tab and non-tab positions according to several embodiments. In some embodiments, exemplary carrier rings and tabs 806a may be characterized by a smaller minimum contact area (MCA) 808 compared to conventional mounting configurations 802a and 804a. The MCA may refer to the area of ​​the carrier ring (e.g., the upper surface of the inner portion of the carrier ring) that can interface with the substrate (e.g., wafer 810) (e.g., physically contact with and / or support the substrate). It is desirable to reduce or minimize the MCA for reasons such as increasing the deposition area on the back side of wafer 810 and reducing particles. Particles may refer to foreign matter (e.g., dust particles) that interfere with deposition, etching, or other processes performed on wafer 810 and may arise from or be caused by contact with other surfaces such as the carrier ring. Therefore, particle formation can be minimized by reducing the contact area with the carrier ring.

[0107] In some embodiments, the exemplary carrier ring and tab 806a may be characterized by an inclined tab portion 812. In some implementations, the inclination may be an angle of 15 degrees or less (e.g., about 11.1 degrees), where the angle is measured with respect to a plane 814 defined by the upper area of ​​the inner portion of the carrier ring. The inclined tab portion 812 may terminate at an end portion having a defined height (e.g., about 0.09 mm). In some variations, such height may be variable according to the shape dimensions and physical characteristics of the tab (e.g., the angle of inclination of the tab, the inner diameter, or the length).

[0108] In contrast, in conventional mounting configurations 802a and 804a, the MCA can be significantly larger. Furthermore, the inclination may not be present in the tab. Consequently, the wafer 810 may have greater contact with the carrier ring.

[0109] In some embodiments, the non-tab positions of the exemplary carrier ring and tab 806b may further reduce the MCA by a reduced carrier ring inner diameter 818 compared to, for example, one or more of the existing mounting configurations 802b, 804b. In some embodiments, the thickness of the carrier ring may also be reduced. In some mounting configurations, the thicknesses of the inner and outer portions of the carrier ring may be about 0.3 mm and 0.5 mm, respectively. The smaller thicknesses of the inner and outer portions may help to adjust or match the wafer impedance, which may result in more uniform deposition and minimization of the edge effects described above. Backside grounding

[0110] Figure 9 shows a semiconductor wafer 900 placed on a carrier ring 902 having a plurality of tabs, according to several embodiments. The back of the semiconductor wafer 900 and the carrier ring are shown to illustrate one of the plurality of tabs, tab 904. In some embodiments, some or all of the plurality of tabs may be examples of inwardly extending tabs as described above with respect to Figures 5A to 8, for example. That is, the tabs may have physical properties (tab ID, smaller width, inclination angle, etc.) selected from the specified range described above. While the semiconductor wafer 900 is supported by the carrier ring 902 and the tabs including tab 904, processing (backside deposition, etching, etc.) may be carried out on the semiconductor wafer 900.

[0111] It should be understood that the above applies equally to some or all of the tabs that may be present on the carrier ring 902. Depending on the implementation, there may be up to six, eight, twelve, or fifteen tabs, some or all of which may have physical properties as described herein with respect to embodiments in Figures 5A to 8.

[0112] Figure 10 shows a processed wafer 900' (e.g., from Figure 9) that can be clamped on a base chuck 1002 (e.g., ESC) according to several embodiments. One potential cause of failure during subsequent processing on the processed wafer 900' is that current charges can accumulate when the back side of the processed wafer 900' is completely covered. This can have adverse effects. For example, electrons may be deflected by the application of an electron beam 1004.

[0113] However, some shadowing effects from the inner circumference of the tab and / or carrier ring 902, as described herein (including in Figure 9), may remain. By preserving a region of no deposition beneath the carrier ring tab, a clear conductive path 1006 can be provided as a conductive grounding point between the pedestal chuck 1002 and the processed wafer 900'. In some embodiments, multiple conductive grounding points may exist as a result of preserving multiple regions of no deposition beneath the carrier ring tab (e.g., one conductive grounding point or area per carrier ring tab).

[0114] The larger the grounding path, the less backside deposition occurs, so shadowing effects from the tab can be an additional factor to balance the considerations mentioned above. Other such considerations to balance may include increasing the deposition area, reducing the level difference, preventing frontside deposition while allowing backside deposition, and preventing the processed wafer 900' from tilting or falling through the inner circumference of the carrier ring.

[0115] For example, some embodiments of carrier rings and tabs described herein may, depending on the application or desired outcome, balance the desirability of reducing the level difference or the MCA (based on, for example, carrier ring ID, tab ID, tab width, and tab angle) with enabling an open electrical contact area using a larger contact area. However, in some cases, enabling a larger open electrical contact area may also be achieved by having additional tabs, e.g., 12 or more, some of which are not inclined and in contact with the processed wafer 900'. Innumerable combinations of the physical properties of the disclosed embodiments of carrier rings and tabs may be balanced to achieve the advantages described herein. method

[0116] Figure 11 is a flowchart showing a method 1100 for obtaining an apparatus configured to support a semiconductor substrate, according to several embodiments. One or more of the functions of method 1100 may be performed or caused by a computerized apparatus or system. The means for performing one or more of the functions shown in the steps shown in Figure 11 may include hardware and / or software components of such a computerized apparatus or system, such as a controller apparatus, computerized system, or computer-readable apparatus, which includes a storage medium for storing computer-readable instructions and / or computer-executable instructions, configured, for example, by a processor apparatus to cause at least one processor apparatus or computerized apparatus to perform an operation. A controller may be an example of a computerized apparatus or system. A process chamber may be another example of a computerized apparatus or system. Exemplary components of a process chamber (including a controller) are shown in Figures 1A and 1B, which are described in more detail above.

[0117] Furthermore, it should be noted that the operations of Method 1100 may be carried out in any preferred order, not necessarily in the order shown in Figure 11. In addition, Method 1100 may involve additional or fewer operations than those shown in Figure 11 in order to obtain the apparatus.

[0118] In block 1102, method 1100 may include fabricating a ring-shaped structure having an inner diameter. The ring-shaped structure may have a substantially circular structure (e.g., a carrier ring) having an inner portion and an outer portion. In some embodiments, the inner diameter of the ring-shaped structure may range from 298.4 to 299.5 mm and may extend from the center of the substantially circular structure to the inner circumference of the inner portion. In some implementations, the inner diameter may be about 299.0 mm.

[0119] In block 1104, method 1100 may include forming a plurality of inwardly extending tabs around the inner diameter of a ring-shaped structure. In some embodiments, the number of tabs may be selected from a range of 5 to 15. In some implementations, there may be 12 tabs arranged around the inner diameter of the ring-shaped structure. In some variations, the tabs may be formed at equidistant and equiangled positions. In some variations, the tabs 、 For example, two tabs at six positions that are equidistant and equiangled from each other. can be formed in the group .

[0120] In some embodiments, the plurality of inwardly extending tabs may have one or more physical properties, which allow for more back-side deposition of the semiconductor substrate compared to a ring-shaped structure with a plurality of tabs formed without one or more of these properties. In some implementations, the one or more physical properties may include one or more of the following: the inner diameter associated with the plurality of tabs, the width of the plurality of tabs, and the angle of at least a portion of the upper surface associated with the plurality of tabs with respect to the plane defined by the ring-shaped structure.

[0121] In some variations, the inner diameter associated with multiple tabs can range from 296.0 to 299.5 mm. In some examples, the inner diameter of the tabs can be approximately 297.0 mm.

[0122] In some variations, the angle of at least a portion of the upper surface may be selected from a range of 15 degrees or less, where at least a portion of the upper surface is collectively configured to interface with the semiconductor substrate (e.g., to physically contact and / or support the semiconductor substrate). In some examples, the angle may be approximately 11.1 degrees downward with respect to the plane defined by the ring-shaped structure. In some cases, the angle may be shaped to be non-uniform over the length of the tab. The angle may be measured at the base of the tab closest to the inner diameter of the carrier ring. Alternatively, the average value of the angle may be selected.

[0123] In some variations, the width of multiple tabs can range from 0.5 to 2.0 mm. In some examples, the width of a tab may be approximately 1.0 mm. In some cases, the width may not be uniform along the length of the tab. The width may be measured at the terminal end portion of the tab, and the tab may be wider or narrower than 1.0 mm along its length.

[0124] The above physical properties of the carrier and its tab can contribute to reduced MCA, increased processing or deposition (e.g., on the back side of the semiconductor substrate), reduced particle size, reduced edge effects, and ultimately a more consistent film thickness (e.g., measurable by reduced level differences). More specifically, the above physical properties of the tab enable more backside deposition by providing a minimum coverage on the back side of the semiconductor substrate compared to some existing carriers that may have larger tabs covering more of the backside area, which would, for example, hinder the deposition of the amounts that can be achieved using the carriers described herein.

[0125] Figure 12 is a flowchart illustrating a method 1200 for depositing one or more layers on the back side of a semiconductor substrate, according to several embodiments. One or more of the functions of method 1200 may be performed or caused by a computerized device or system. Such a computerized device or system may include hardware and / or software components, such as a controller device, computerized system, or computer-readable device, which includes a storage medium for storing computer-readable instructions and / or computer-executable instructions, configured, for example, by a processor device to cause at least one processor device or computerized device to perform an operation. A controller may be an example of a computerized device or system. A process chamber may be another example of a computerized device or system. Exemplary components of a process chamber (including a controller) are shown in Figures 1A and 1B, which are described in more detail above.

[0126] Furthermore, it should be noted that the operations of Method 1200 may be carried out in any preferred order, not necessarily in the order shown in Figure 12. In addition, Method 1200 may include additional or fewer operations than those shown in Figure 12 in order to deposit the layers.

[0127] In block 1202, method 1200 may include supporting a semiconductor substrate on a carrier ring. In some embodiments, the carrier ring may be an example of the carrier ring 600 shown in Figures 6A to 6F, the carrier ring 704 shown in Figure 7, or the carrier ring shown in Figure 8. The carrier ring may have one or more physical properties possessed by the carrier ring, including a specified inner diameter of the carrier ring, the inner diameter of a plurality of inwardly extending tabs, the amount of a plurality of inwardly extending tabs, the width of a plurality of inwardly extending tabs, and / or the angle of a plurality of inwardly extending tabs.

[0128] In some embodiments, the semiconductor substrate may be an example of the substrate 128 shown in Figures 1A and 1B. In some embodiments, the semiconductor substrate may be an example of the wafer 512 shown in Figures 5A to 5C, 6E and 6F, the wafer shown in Figure 8, or the semiconductor wafer 900 shown in Figure 9.

[0129] In some embodiments, the semiconductor substrate may be placed on top of the inner portion of the carrier ring and surrounded by the outer portion of the carrier ring. In some mounting configurations, as shown in Figures 5A to 5C, the inner portion may be defined by cross-sectional portion 506a and the outer portion may be defined by cross-sectional portion 506b.

[0130] In block 1204, method 1200 includes exposing the back side of a semiconductor substrate to process conditions that cause one or more layers to be deposited on the back side of the semiconductor substrate. In some embodiments, the process conditions include exposure to at least one chemical precursor of the one or more layers. For example, silicon-containing reactants, nitrogen-containing reactants, or oxygen-containing co-reactants may be used as chemical precursors. In some embodiments, at least one of the one or more layers on the back side of the semiconductor substrate includes polysilicon, silicon oxide, silicon nitride, or any combination thereof. In some configurations, the layers may be deposited or stacked in an alternating manner, for example, in alternating silicon oxide and silicon nitride layers. Other examples of chemical precursors and stacking materials are listed elsewhere in this specification.

[0131] In some implementations, the controller (e.g., 120) may be part of a system, which may be part of the examples described above, including a process chamber or another system including an ESC. Such a system may include semiconductor processing equipment, which may include one or more processing tools for processing, one or more chambers, one or more platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). These systems may be integrated with electronics to control their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may be referred to as the “controller,” which may control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, and wafer transfers, including tools and other transfer tools and / or load locks connected to or interfaced with a particular system.

[0132] Generally, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and so on. Integrated circuits may include chips defined as firmware storing program instructions, digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or chips in the form of one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, operating parameters may be part of a recipe defined by a process engineer to achieve one or more processing steps during the processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0133] In some implementations, a controller may be part of a computer, or coupled to that computer, or a combination thereof, integrated with, coupled to, or otherwise networked to the system. For example, a controller may be in the “cloud” or in all or part of a fab-host computer system that can enable remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of processing operations, examine the history of past processing operations, and examine trends or performance metrics from multiple processing operations in order to change the parameters of the current operation, set processing steps that follow the current operation, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Therefore, as described above, the controllers may be distributed, for example, by comprising one or more separate controllers that are networked together and function toward common purposes such as processes and control as described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (at the platform level or as part of a remote computer, for example) and are combined to control processes on the chamber.

[0134] Exemplary systems, though not limited to them, may include plasma etching chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, clean chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be related to or used in the processing and / or manufacture of semiconductor wafers.

[0135] As described above, depending on one or more process steps to be performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used in material transfer to carry wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing plant.

[0136] Systems and methods that provide improved chucking or clamping capabilities compared to conventional systems are provided herein. The methods, apparatus, and systems described above enable the flexible use of various clamping modes (e.g., bipolar and / or unipolar) compared to conventional systems, and they enable this using modifications to existing technologies. As a result, embodiments of the improved chucking systems herein include configurations with one or more power supplies.

[0137] Various modifications to the implementations described herein may be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Accordingly, the claims should not be limited to the implementations shown herein, but should be given the broadest scope that is consistent with the disclosure, principles and novel features disclosed herein.

[0138] Some features described herein in the context of separate implementations may also be implemented in combinations within a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations, or in any preferred partial combination. Furthermore, features are described above as working in several combinations, and may even be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from that combination, and the claimed combination may be a partial combination or a variation of a partial combination.

[0139] Similarly, while actions are shown in a specific order in the drawings, this should not be understood as requiring that such actions be performed in a specific or sequential order shown, or that all shown actions be performed, in order to achieve the desired result. Furthermore, drawings may schematically represent one or more exemplary processes in the form of flowcharts. However, other actions not shown may be incorporated into the schematically represented exemplary process. For example, one or more additional actions may occur before or after any of the shown actions. AndThese actions may be performed simultaneously or in between. In some situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged in multiple software products. In addition, other implementations fall within the scope of the following claims. In some cases, the actions described in the claims may be performed in a different order and still achieve the desired results. The present invention can also be realized in the following embodiments, for example. Application Example 1: A carrier ring configured to support a semiconductor substrate, wherein the carrier ring is A ring having an outer portion and an inner portion, defining a plane, wherein the inner portion has an inner circumference having a first diameter of approximately 298.4 to 299.5 millimeters (mm), A plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring, wherein the plurality of inwardly extending tabs have an inner edge defining a circle having a second diameter of approximately 296.0 to 298.5 mm, A carrier equipped with this feature. Application example 2: The carrier described in Application Example 1, The first diameter of the inner portion of the ring is approximately 299.0 mm. The second diameter of the plurality of inwardly extending tabs is approximately 297.0 mm. Carriering. Application Example 3: A carrier ring according to Application Example 1, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs. Application Example 4: A carrier ring according to Application Example 1, wherein at least one of the plurality of inwardly extending tabs has a width of approximately 0.5 to 1.5 mm. Application Example 5: A carrier ring according to Application Example 4, wherein the width of at least one of the plurality of inwardly extending tabs is approximately 1.0 mm. Application example 6: A carrier ring according to Application Example 1, wherein at least one of the plurality of inwardly extending tabs comprises at least a portion of the upper surface having an angle that is neither parallel nor perpendicular to the plane. Application example 7: A carrier ring as described in Application Example 6, wherein the angle of the portion of the upper surface is between approximately 5 and 20 degrees with respect to the plane. Application Example 8: A carrier ring according to Application Example 6, wherein the upper surface of at least one of the plurality of inwardly extending tabs has a minimum contact area (MCA) configured to physically contact the semiconductor substrate. Application example 9: A carrier ring as described in Application Example 1, wherein the outer portion is approximately 0.3 to 0.7 mm thick and the inner portion is approximately 0.1 to 0.5 mm thick. Application Example 10: A carrier ring according to Application Example 1, wherein at least a portion of the plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring is configured to form one or more conductive grounding points on the semiconductor substrate. Application Example 11: A carrier ring configured to support a semiconductor substrate, wherein the carrier ring is A ring having an inner portion configured to support the semiconductor substrate during back-side deposition on the semiconductor substrate, wherein the ring defines a plane, Distributed around the inner portion of the ring, and configured to contact the semiconductor substrate during back-side deposition on the semiconductor substrate, 8 to 15 inwardly extending tabs, Equipped with, A carrier ring in which at least one of the 8 to 15 inwardly extending tabs has a width of approximately 0.5 to 1.5 mm. Application Example 12: A carrier ring according to Application Example 11, wherein at least one of the 8 to 15 inwardly extending tabs has an upper surface having an angle of about 15 degrees or less with respect to the plane. Application Example 13: A carrier ring as described in Application Example 11, wherein the 8 to 15 inwardly extending tabs have an inner edge defining a first diameter of approximately 296.0 to 298.5 mm. The 8 to 15 inwardly extending tabs are attached to the ring and have outer edges defining a second diameter of approximately 298.4 to 299.5 mm. Carriering. Application Example 14: A carrier ring according to Application Example 11, wherein at least a portion of the 8 to 15 inwardly extending tabs is configured to enable the formation of one or more conductive grounding points on the semiconductor substrate. Application Example 15: A method for depositing one or more layers on the back side of a semiconductor substrate, wherein the method is (a) Supporting the semiconductor substrate on a carrier ring, wherein the carrier ring is A ring having an outer portion and an inner portion, defining a plane, wherein the inner portion has an inner circumference having a first diameter of approximately 298.4 to 299.5 millimeters (mm), A plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring, wherein the plurality of inwardly extending tabs have an inner edge defining a circle having a second diameter of approximately 296.0 to 298.5 mm, The support of the semiconductor substrate on the carrier ring, (b) Exposing the back side of the semiconductor substrate to process conditions that cause the one or more layers to be deposited on the back side of the semiconductor substrate, Methods that include... Application Example 16: A method according to Application Example 15, wherein the process conditions causing the deposition of the one or more layers include exposure to at least one chemical precursor of the one or more layers. Application Example 17: A method according to Application Example 15, wherein at least one of the one or more layers on the back side of the semiconductor substrate comprises polysilicon, silicon oxide, silicon nitride, or any combination thereof. Application Example 18: The method described in Application Example 15, The first diameter of the inner portion of the ring is approximately 299.0 mm. The second diameter of the plurality of inwardly extending tabs is approximately 297.0 mm. method. Application Example 19: A method according to Application Example 15, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs, and at least one of the at least eight inwardly extending tabs has a width of about 0.5 to 1.5 mm. Application Example 20: A method according to Application Example 15, wherein at least one of the plurality of inwardly extending tabs comprises at least a portion of its upper surface having an angle that is neither parallel nor perpendicular to the plane, and the angle is about 5 to 20 degrees with respect to the plane.

Claims

1. A carrier ring configured to support a semiconductor substrate, wherein the carrier ring is A ring having an outer portion and an inner portion, wherein the inner portion has one or more first upper surfaces defining a plane, and the inner portion has an inner circumference having a first diameter of 298.4 to 299.5 millimeters (mm), A plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring, wherein the plurality of inwardly extending tabs have an inner edge defining a circle having a second diameter of 296.0 to 298.5 mm, Equipped with, Each of the tabs extends inward from one of the one or more first upper surfaces. At least one of the plurality of inwardly extending tabs comprises at least a portion of the second upper surface having an angle that is neither parallel nor perpendicular to the plane, The one or more first upper surfaces are carrier rings that extend within a circular region with a diameter of 300 mm centered on the circle.

2. A carrier ring according to claim 1, The first diameter of the inner portion of the ring is 299.0 mm. The second diameter of the plurality of inwardly extending tabs is 297.0 mm. Carriering.

3. A carrier ring according to claim 1, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs.

4. A carrier ring according to claim 1, wherein at least one of the plurality of inwardly extending tabs has a width of 0.5 to 1.5 mm.

5. A carrier ring according to claim 4, wherein the width of at least one of the plurality of inwardly extending tabs is 1.0 mm.

6. A carrier ring according to Claim 1, wherein the angle of the portion of the second upper surface is between 5 and 20 degrees with respect to the plane.

7. A carrier ring according to claim 1, wherein the second upper surface of at least one of the plurality of inwardly extending tabs has a minimum contact area (MCA) configured to physically contact the semiconductor substrate.

8. A carrier ring according to claim 1, wherein the outer portion is 0.3 to 0.7 mm thick and the inner portion is 0.1 to 0.5 mm thick.

9. A carrier ring according to claim 1, wherein at least a portion of the plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring is configured to form one or more conductive grounding points on the semiconductor substrate.

10. A carrier ring configured to support a semiconductor substrate, wherein the carrier ring is A ring having an inner portion configured to support the semiconductor substrate during back-side deposition on the semiconductor substrate, wherein the inner portion has one or more first upper surfaces defining a plane, Eight to fifteen inwardly extending tabs are arranged around the inner portion of the ring and configured to contact the semiconductor substrate during back-side deposition on the semiconductor substrate, Equipped with, At least one of the 8 to 15 inwardly extending tabs has a width of 0.5 to 1.5 mm. Each of the tabs extends inward from one of the one or more first upper surfaces. At least one of the plurality of inwardly extending tabs comprises at least a portion of the second upper surface having an angle that is neither parallel nor perpendicular to the plane, The one or more first upper surfaces are carrier rings that extend within a circular region with a diameter of 300 mm centered on the circle.

11. A carrier ring according to claim 10, wherein at least one of the 8 to 15 inwardly extending tabs has an upper surface having an angle of 15 degrees or less with respect to the plane.

12. A carrier ring according to claim 10, wherein the 8 to 15 inwardly extending tabs have an inner edge defining a first diameter of 296.0 to 298.5 mm, The 8 to 15 inwardly extending tabs are attached to the ring and have outer edges defining a second diameter of 298.4 to 299.5 mm. Carriering.

13. A carrier ring according to claim 10, wherein at least a portion of the 8 to 15 inwardly extending tabs is configured to enable the formation of one or more conductive grounding points on the semiconductor substrate.

14. A method for depositing one or more layers on the back side of a semiconductor substrate, wherein the method is (a) Supporting the semiconductor substrate on the carrier ring, wherein the carrier ring A ring defining a plane, having an outer portion and an inner portion having one or more first upper surfaces, wherein the inner portion has an inner circumference having a first diameter of 298.4 to 299.5 millimeters (mm), A plurality of inwardly extending tabs arranged around the inner circumference of the inner portion of the ring, wherein the plurality of inwardly extending tabs have an inner edge defining a circle having a second diameter of 296.0 to 298.5 mm, Equipped with, Each of the tabs extends inward from one of the one or more first upper surfaces. At least one of the plurality of inwardly extending tabs comprises at least a portion of the second upper surface having an angle that is neither parallel nor perpendicular to the plane, The one or more first upper surfaces extend within a circular region with a diameter of 300 mm centered on the circle, supporting the semiconductor substrate on the carrier ring, (b) Exposing the back side of the semiconductor substrate to process conditions that cause the one or more layers to be deposited on the back side of the semiconductor substrate, Methods that include...

15. A method according to claim 14, wherein the process conditions causing the deposition of the one or more layers include exposure to at least one chemical precursor of the one or more layers.

16. A method according to claim 14, wherein at least one of the one or more layers on the back side of the semiconductor substrate comprises polysilicon, silicon oxide, silicon nitride, or any combination thereof.

17. The method according to claim 14, The first diameter of the inner portion of the ring is 299.0 mm. The second diameter of the plurality of inwardly extending tabs is 297.0 mm. method.

18. A method according to claim 14, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs, and at least one of the at least eight inwardly extending tabs has a width of 0.5 to 1.5 mm.

19. A method according to claim 14, wherein at least one of the plurality of inwardly extending tabs comprises at least a portion of its upper surface having an angle that is neither parallel nor perpendicular to the plane, and the angle is between 5 and 20 degrees with respect to the plane.

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