Information processing program, information processing method, and information processing device

Abstract

This information processing device (100) generates a logical bell state of two logical qubits by performing entanglement, between the two logical qubits, of ancillary qubits which are positioned in each of said two logical qubits. Specifically, the information processing device (100) performs entanglement, between two logical qubits without a data qubit therebetween, of all ancillary qubits positioned in each of the logical qubits on the side thereof which connects to another logical qubit instead of a data qubit. Specifically, according to an example in fig. 1, the information processing device (100) generates a logical bell state of two logical qubits by entangling ancillary qubits (10, 11) between two logical qubits without a data qubit therebetween.

Description

[Technical Field]

[0001] The present invention relates to an information processing program, an information processing method, and an information processing apparatus. [Background technology]

[0002] Conventionally, to mitigate errors caused by environmental noise and other factors, there existed logical qubits in which multiple data qubits and multiple auxiliary qubits for error correction are arranged in a two-dimensional lattice. Furthermore, there are techniques to generate logical bell states of two logical qubits, each with additional auxiliary qubits for merging. For example, it is conceivable to generate logical bell states of two logical qubits by entanglement of the auxiliary qubits for merging arranged on each logical qubit, performing a merge operation, and then performing a split operation to repair each logical qubit.

[0003] Prior art includes, for example, a method for determining the measured value of an encoded Bell measurement based on a calculated probability of the measured value of the encoded Bell measurement. Another example is a technique that uses a data qubit to hold a quantum state, a transfer qubit to transfer the quantum state of the data qubit, and a measurement qubit to measure the quantum state of the data qubit transferred via the transfer qubit. Yet another example is a technique for coupling physical qubits with logical qubits. And yet another example is a technique for coupling each data qubit with one or more auxiliary qubits. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-090341 [Patent Document 2] Japanese Patent Publication No. 2022-057269 [Patent Document 3] U.S. Patent Application Publication No. 2020-0394101 [Patent Document 4] U.S. Patent Application Publication No. 2020-0119748 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, conventional techniques can lead to increased processing time when generating logical bell states. For example, since auxiliary qubits for the merge process are entangled, the merge process is performed, and then a split process is performed to repair each logical qubit, the processing time required to generate logical bell states increases.

[0006] In one aspect, the present invention aims to suppress the increase in processing time required when generating logical bell states. [Means for solving the problem]

[0007] According to one embodiment, an information processing program, information processing method, and information processing device are proposed that generate a logical bell state of two logical qubits by entangling all of the auxiliary qubits, which are located on the side of each logical qubit that connects to the other logical qubit rather than the data qubits, between the two logical qubits without going through the data qubits, in the arrangement of a plurality of qubits, which includes a plurality of data qubits and a plurality of auxiliary qubits, in each logical qubit to be connected. [Effects of the Invention]

[0008] According to one embodiment, it becomes possible to suppress the increase in processing time required when generating a logical bell state. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is an explanatory diagram showing one embodiment of the information processing method according to the embodiment. [Figure 2]Figure 2 is a block diagram showing an example of the hardware configuration of the information processing device 100. [Figure 3] Figure 3 is a block diagram showing an example of the functional configuration of the information processing device 100. [Figure 4] Figure 4 is an explanatory diagram (part 1) showing an example of generating a logic bell state for logic qubits 410 and 420. [Figure 5] Figure 5 is an explanatory diagram (part 2) showing an example of generating a logic bell state for logic qubits 410 and 420. [Figure 6] Figure 6 is a flowchart (part 1) showing an example of the first connection processing procedure. [Figure 7] Figure 7 is a flowchart (part 2) showing an example of the first connection processing procedure. [Figure 8] Figure 8 is an explanatory diagram showing a quantum circuit 800 in which the information processing device 100 generates logical bell states for logical qubits 410 and 420, and also performs error correction. [Figure 9] Figure 9 is a flowchart (part 1) showing an example of the second connection processing procedure. [Figure 10] Figure 10 is a flowchart (part 2) showing an example of the second connection processing procedure. [Figure 11] Figure 11 is an explanatory diagram (part 1) showing a conventional example of generating a logic bell state for logic qubits 1110 and 1120. [Figure 12] Figure 12 is an explanatory diagram (part 2) showing a conventional example of generating a logic bell state for logic qubits 1110 and 1120. [Figure 13] Figure 13 is an explanatory diagram (part 3) showing a conventional example of generating logical bell states for logical qubits 1110 and 1120. [Figure 14] Figure 14 is a flowchart (part 1) showing an example of a conventional processing procedure. [Figure 15] Figure 15 is a flowchart (part 2) showing an example of a conventional processing procedure. [Figure 16] Figure 16 is a flowchart (part 3) showing an example of a conventional processing procedure. [Figure 17] Figure 17 is an explanatory diagram (part 1) showing an example of the accuracy of the measurement results of data qubits. [Figure 18] Figure 18 is an explanatory diagram (part 2) showing an example of the accuracy of the measurement results of data qubits. [Figure 19] Figure 19 is an explanatory diagram (part 3) showing an example of the accuracy of the measurement results of data qubits. [Figure 20] Figure 20 is an explanatory diagram (part 4) showing an example of the accuracy of the measurement results of data qubits. [Figure 21] Figure 21 is an explanatory diagram (part 5) showing an example of the accuracy of the measurement results of data qubits. [Figure 22] Figure 22 is an explanatory diagram (part 1) showing an example of the accuracy of the measurement results of data qubits. [Figure 23] Figure 23 is an explanatory diagram (part 2) showing an example of the accuracy of the measurement results of data qubits. [Figure 24] Figure 24 is an explanatory diagram (part 3) showing an example of the accuracy of the measurement results of data qubits. [Figure 25] Figure 25 is an explanatory diagram (part 4) showing an example of the accuracy of the measurement results of data qubits. [Figure 26] Figure 26 is an explanatory diagram (part 5) showing an example of the accuracy of the measurement results of data qubits. [Figure 27] Figure 27 is an explanatory diagram (part 6) showing an example of the accuracy of the measurement results of data qubits. [Figure 28] Figure 28 is an explanatory diagram (part 7) showing an example of the accuracy of the measurement results of data qubits. [Figure 29] Figure 29 is an explanatory diagram (part 1) showing an example of generating a logical bell state for logical qubits 2910 and 2920. [Figure 30] Figure 30 is an explanatory diagram (part 2) showing an example of generating a logic bell state for logic qubits 2910 and 2920. [Figure 31] Figure 31 is an explanatory diagram (part 1) illustrating the reasons for performing split processing. [Figure 32]Figure 32 is an explanatory diagram (part 2) illustrating the reasons for performing the split process. [Figure 33] Figure 33 is an explanatory diagram (part 1) showing why split processing can be avoided. [Figure 34] Figure 34 is an explanatory diagram (part 2) showing why split processing can be avoided. [Modes for carrying out the invention]

[0010] Embodiments of the information processing program, information processing method, and information processing apparatus according to the present invention will be described in detail below with reference to the drawings.

[0011] (An embodiment of the information processing method according to the embodiment) Figure 1 is an explanatory diagram showing one embodiment of the information processing method according to the embodiment. The information processing device 100 is a computer that handles logical qubits. The information processing device 100 is, for example, a quantum computer. Specifically, the information processing device 100 includes a qubit chip. The qubit chip represents, for example, a logical qubit.

[0012] A logical qubit is formed by arranging multiple qubits. These multiple qubits include multiple data qubits and multiple auxiliary qubits. The data qubits represent the values ​​of the data. The auxiliary qubits include auxiliary qubits for error correction and auxiliary qubits for merging.

[0013] A logical qubit includes multiple data qubits arranged in a matrix to provide redundancy for data qubits, for example, to mitigate errors caused by environmental noise. A logical qubit also includes an error-correction auxiliary qubit positioned adjacent to at least one data qubit, for example, to mitigate errors caused by environmental noise. Specifically, a logical qubit includes an error-correction auxiliary qubit positioned between two different data qubits.

[0014] A logical qubit includes, for example, an auxiliary qubit for merging operations, which is placed outside a matrix of data qubits to generate a logical bell state with other logical qubits. A logical bell state is a quantum entanglement state of two different logical qubits in which the value of one logical qubit is determined by observation, and in turn, the value of the other logical qubit is determined.

[0015] Conventionally, the logical bell state of two logical qubits is generated by entangling auxiliary qubits for merge processing, which are placed on each logical qubit, performing the merge process, and then performing a split process to repair each logical qubit. For example, the logical state of each logical qubit may be corrupted during the merge process, so a split process is performed to repair each logical qubit.

[0016] However, conventional methods have made it difficult to generate logical bell states for two different logical qubits. For example, generating logical bell states for two different logical qubits can lead to increased processing time. Specifically, the process involves entanglement of auxiliary qubits for merging, followed by a merge operation and then a split operation to repair each logical qubit, which increases the processing time required to generate the logical bell state. Furthermore, the merging operation carries the risk of error propagation.

[0017] Furthermore, conventional methods make it difficult to perform error correction using auxiliary qubits for error correction. For example, this can lead to an increase in the time required before error correction can begin. Specifically, there is a problem that error correction cannot be performed until the logical bell states of two different logical qubits have been generated. Consequently, when generating the logical bell states of two different logical qubits, there is a problem that the error rate of the data qubit tends to increase.

[0018] Therefore, this embodiment describes an information processing method that can facilitate the generation of logical bell states. For example, according to this information processing method, it is possible to suppress the increase in processing time required when generating logical bell states.

[0019] In Figure 1, there are two logical qubits to be connected, which are handled by the information processing device 100. The connection is the generation of a logical bell state. Each logical qubit contains multiple qubits. Multiple qubits include multiple data qubits and multiple auxiliary qubits. In the example in Figure 1, the two logical qubits are specifically the first logical qubit 110 and the second logical qubit 120.

[0020] The first logical qubit 110 specifically includes four data qubits 1-4 arranged in a 2x2 matrix. The first logical qubit 110 specifically includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. The first logical qubit 110 specifically includes an auxiliary qubit 10 for error correction Z measurement and merging, connected to data qubits 3 and 4. The auxiliary qubit 10 is for merging and is an entangled auxiliary qubit. The first logical qubit 110 specifically includes an auxiliary qubit 13 for error correction X measurement connected to data qubits 1-4.

[0021] The second logic qubit 120 specifically includes four data qubits 5-8 arranged in a 2x2 matrix. The second logic qubit 120 specifically includes an auxiliary qubit 12 for error correction Z measurement connected to data qubits 7 and 8. The second logic qubit 120 specifically includes an auxiliary qubit 11 for error correction Z measurement and merging, connected to data qubits 5 and 6. The auxiliary qubit 11 is for merging and is an entangled auxiliary qubit. The second logic qubit 120 specifically includes an auxiliary qubit 16 for error correction X measurement connected to data qubits 5-8.

[0022] Thus, in the example shown in Figure 1, qubits 1-13 and 16 are arranged such that the number of pairs of auxiliary qubits entangled between the first logical qubit 110 and the second logical qubit 120 is minimized. Specifically, the pair of auxiliary qubits that are entangled is one pair of auxiliary qubits 10 and 11.

[0023] (1-1) The information processing device 100 generates a logical bell state of two logical qubits. The information processing device 100 generates a logical bell state of two logical qubits by, for example, entangling the auxiliary qubits placed on each of the two logical qubits between the two logical qubits.

[0024] Specifically, the information processing device 100 entangles all of the auxiliary qubits located on the side of each logical qubit that connects to the other logical qubit rather than the data qubit, without involving the data qubit. Entanglement is achieved, for example, by quantum state transfer technology.

[0025] In the example shown in Figure 1, the auxiliary qubit positioned on the side of the first logical qubit 110 that connects to the second logical qubit 120 rather than the data qubit is specifically auxiliary qubit 10. Similarly, the auxiliary qubit positioned on the side of the second logical qubit 120 that connects to the first logical qubit 110 rather than the data qubit is specifically auxiliary qubit 11. Therefore, the information processing device 100 generates a logical bell state of the two logical qubits by entanglement of the auxiliary qubits 10 and 11 between the two logical qubits without going through the data qubit.

[0026] As a result, the information processing device 100 can prevent the logical state of each logical qubit from being corrupted in response to the merge process, and can avoid performing a split process to repair each logical qubit. Therefore, the information processing device 100 can easily generate logical bell states of two different logical qubits. The information processing device 100 can reduce the processing time required when generating logical bell states of two different logical qubits, for example. The information processing device 100 can reduce the error rate of data qubits by avoiding the need to perform a split process, for example.

[0027] Furthermore, the information processing device 100 can prevent the logical state of each logical qubit from being corrupted in response to the merge process, and can perform error correction before the logical bell states of two different logical qubits have been fully generated. Therefore, the information processing device 100 can reduce the time required to start performing error correction. The information processing device 100 can reduce the time required from the start of generating the logical bell states of two different logical qubits until the completion of error correction. The information processing device 100 can reduce the error rate of data qubits.

[0028] Here, we have described the case in which multiple qubits are arranged for each logic qubit in such a way that the number of pairs of entangled auxiliary qubits is minimized, but this is not the only case. For example, there may be cases in which multiple qubits are arranged for each logic qubit, regardless of the number of entangled auxiliary qubits. Specifically, as shown in Figure 1 for logic qubits 130 and 140, there may be cases where there are three pairs of entangled auxiliary qubits.

[0029] Here, we have described the case where the information processing device 100 is a quantum computer including a qubit chip, but it is not limited to this. For example, the information processing device 100 may run a quantum computer simulator. In this case, the information processing device 100 generates logical bell states of two different logical qubits in the quantum computer simulator.

[0030] (Example of hardware configuration of information processing device 100) Next, an example of the hardware configuration of the information processing device 100 will be described using Figure 2.

[0031] Figure 2 is a block diagram showing an example of the hardware configuration of the information processing device 100. In Figure 2, the information processing device 100 includes a CPU (Central Processing Unit) 201, memory 202, network interface 203, recording medium interface 204, and recording medium 205. The information processing device 100 further includes an arithmetic unit interface 206 and a quantum computing unit 207. Each component is connected by a bus 200.

[0032] Here, the CPU 201 is responsible for the overall control of the information processing device 100. The memory 202 includes, for example, ROM (Read Only Memory), RAM (Random Access Memory), and flash ROM. Specifically, for example, flash ROM and ROM store various programs, and RAM is used as the work area for the CPU 201. Programs stored in memory 202 are loaded into the CPU 201, causing the CPU 201 to execute the coded processes.

[0033] Network I / F 203 is connected to network 210 via a communication line, and then connects to other computers via network 210. Network I / F 203 manages the internal interface with network 210 and controls the input and output of data from other computers. Network I / F 203 is, for example, a modem or a LAN (Local Area Network) adapter.

[0034] The recording medium interface (I / F) 204 controls the reading and writing of data to the recording medium 205 according to the control of the CPU 201. The recording medium interface (I / F) 204 is, for example, a disk drive, an SSD (Solid State Drive), or a USB (Universal Serial Bus) port. The recording medium 205 is a non-volatile memory that stores the data written under the control of the recording medium interface (I / F) 204. The recording medium 205 is, for example, a disk, semiconductor memory, or USB memory. The recording medium 205 may be detachable from the information processing device 100.

[0035] The arithmetic unit interface (I / F) 206 controls access to the quantum computing unit (Quantum Computing Unit) 207 according to the control of the CPU 201. The I / F 206 uses a microwave pulse generator to convert the output signal from the CPU 201 into an input signal for the Quantum Computing Unit (Quantum Computing Unit) 207 and transmits it to the Quantum Computing Unit (Quantum Computing Unit) 206 uses a microwave pulse demodulator to convert the output signal from the Quantum Computing Unit (Quantum Computing Unit) 207 into an input signal for the CPU 201 and transmits it to the CPU 201. The Quantum Computing Unit (Quantum Computing Unit) 207 is an arithmetic unit equipped with one or more qubit chips cooled to an extremely low temperature of 10 mK (kelvin). A qubit chip represents, for example, a logical qubit. The Quantum Computing Unit (Quantum Computing Unit) 207 uses one or more qubit chips to perform a predetermined operation in response to an input signal and outputs an output signal corresponding to the result of the predetermined operation.

[0036] In addition to the components described above, the information processing device 100 may also have, for example, a keyboard, mouse, display, printer, scanner, microphone, speaker, etc. Furthermore, the information processing device 100 may have multiple recording medium interfaces 204 and recording mediums 205. Alternatively, the information processing device 100 may not have recording medium interfaces 204 and recording mediums 205.

[0037] (Example of the functional configuration of the information processing device 100) Next, an example of the functional configuration of the information processing device 100 will be described using Figure 3.

[0038] Figure 3 is a block diagram showing an example of the functional configuration of the information processing device 100. The information processing device 100 includes a storage unit 300, an acquisition unit 301, an arithmetic unit 302, an operation unit 303, and an output unit 304.

[0039] The storage unit 300 is implemented by a storage area such as the memory 202 or recording medium 205 shown in Figure 2. The following description will focus on the case where the storage unit 300 is included in the information processing device 100, but is not limited to this case. For example, the storage unit 300 may be included in a device different from the information processing device 100, and the contents of the storage unit 300 may be accessible from the information processing device 100.

[0040] The acquisition unit 301 to the output unit 304 function as an example of a control unit. Specifically, the acquisition unit 301 to the output unit 304 realize their functions, for example, by having the CPU 201 execute a program stored in a storage area such as the memory 202 or recording medium 205 shown in Figure 2, or by using the network interface 203. The processing results of each functional unit are stored in a storage area such as the memory 202 or recording medium 205 shown in Figure 2.

[0041] The memory unit 300 stores various types of information that are referenced or updated during the processing of each functional unit. For example, the memory unit 300 stores the arrangement of multiple qubits in a logical qubit. A logical qubit is formed by arranging multiple qubits.

[0042] A qubit is, for example, a superconducting qubit. A qubit may be, for example, not a superconducting qubit. Multiple qubits include multiple data qubits and multiple auxiliary qubits. A data qubit represents the value of the data. Multiple auxiliary qubits include auxiliary qubits for error correction and auxiliary qubits for merging.

[0043] Specifically, the memory unit 300 stores the arrangement of multiple qubits in each of the two logical qubits to be connected. For example, it is preferable that the arrangement of multiple qubits in each logical qubit satisfies the condition that all of the auxiliary qubits located on the side of the logical qubit that is closer to the other logical qubit than the data qubit are to be entangled.

[0044] Preferably, each logical qubit is a logical qubit in which multiple qubits are arranged such that the number of entangled auxiliary qubits is minimized. Each logical qubit is arranged in a binary tree-like structure, for example, with two or more data qubits placed on the side connected to the other logical qubit as leaves, and one auxiliary qubit that is directly entangled as the root, and one or more auxiliary qubits that form nodes.

[0045] Each logical qubit, specifically, has four data qubits arranged in a 2x2 matrix. Furthermore, each logical qubit has one auxiliary qubit that is directly connected to two data qubits located on the side that connects to the other logical qubit.

[0046] Each logical qubit consists of nine data qubits arranged in a 3x3 matrix. Furthermore, each logical qubit is arranged in a binary tree structure, with three data qubits on the side connected to the other logical qubit acting as leaves, and one auxiliary qubit directly entangled with them acting as the root. Three auxiliary qubits then act as nodes. This arrangement can be pre-configured by the user, for example.

[0047] The acquisition unit 301 acquires various types of information used in the processing of each functional unit. The acquisition unit 301 stores the acquired information in the storage unit 300 or outputs it to each functional unit. The acquisition unit 301 may also output the information stored in the storage unit 300 to each functional unit. The acquisition unit 301 acquires various types of information, for example, based on user input. The acquisition unit 301 may receive various types of information from a device other than the information processing device 100, for example. The acquisition unit 301 acquires a processing request that requests the generation of a logical bell state for two logical qubits.

[0048] The acquisition unit 301 may receive a start trigger to initiate processing in any of the functional units. A start trigger may be, for example, a predetermined operation input by a user. A start trigger may also be, for example, the receipt of predetermined information from another computer. A start trigger may also be, for example, the output of predetermined information by any of the functional units. Specifically, the acquisition unit 301 accepts the acquisition of a processing request as a start trigger to initiate processing in the operation unit 303.

[0049] The arithmetic unit 302 realizes logical qubits. The arithmetic unit 302 realizes logical qubits formed by multiple qubit chips, each representing a different qubit, in the arrangement described above. This allows the arithmetic unit 302 to make logical qubits available for use.

[0050] The operation unit 303 controls the calculation unit 302 to generate a logical bell state for two logical qubits. The operation unit 303 generates the logical bell state for two logical qubits by, for example, entangling the auxiliary qubits located on each of the two logical qubits between the two logical qubits. Specifically, the operation unit 303 entangles all the auxiliary qubits located on the side of each logical qubit that connects to the other logical qubit rather than the data qubit between the two logical qubits without going through the data qubit. This allows the operation unit 303 to reduce the processing time required to generate the logical bell state for two logical qubits.

[0051] When the operation unit 303 generates the logic bell state of two logic qubits, it uses an auxiliary qubit for error correction from among the multiple qubits in each logic qubit to perform error correction on the data qubit. This allows the operation unit 303 to reduce the time required to start performing error correction.

[0052] The output unit 304 outputs the processing result of at least one of the functional units. The output format is, for example, display on a display, print output to a printer, transmission to an external device via the network I / F 203, or storage in a storage area such as memory 202 or recording medium 205. This allows the output unit 304 to notify the user of the processing result of at least one of the functional units, thereby improving the usability of the information processing device 100. For example, the output unit 304 outputs a notification indicating that a logical bell state of two logical qubits has been generated, which can be viewed by the user.

[0053] (An example of the operation of the information processing device 100) Next, an example of the operation of the information processing device 100 will be described using Figures 4 to 32. Specifically, first, using Figures 4 and 5, an example of the information processing device 100 generating logical bell states for logical qubits 410 and 420 will be described.

[0054] Figures 4 and 5 are explanatory diagrams illustrating an example of generating a logical bell state for logical qubits 410 and 420. Specifically, Figure 4 shows an example of the arrangement of multiple qubits in logical qubits 410 and 420 that are targeted for generating the logical bell state.

[0055] For example, the arrangement of multiple qubits in logical qubits 410 and 420 satisfies the condition that all auxiliary qubits of one logical qubit that are closer to the other logical qubit than the data qubit are objects to be entangled.

[0056] As shown in Figure 4, the logical qubit 410 is located, for example, at node A. Specifically, the logical qubit 410 includes four data qubits 1 to 4 arranged in a 2x2 matrix. Specifically, the logical qubit 410 includes an auxiliary qubit 9 for error correction Z measurement, connected to data qubits 1 and 2. Specifically, the logical qubit 410 includes an auxiliary qubit 10 for error correction Z measurement and merging, connected to data qubits 3 and 4. Specifically, the logical qubit 410 includes an auxiliary qubit 13 for error correction X measurement, connected to data qubits 1 to 4.

[0057] As shown in Figure 4, the logical qubit 420 is located, for example, at node B. Specifically, the logical qubit 420 includes four data qubits 5-8 arranged in a 2x2 matrix. Specifically, the logical qubit 420 includes an auxiliary qubit 12 for error correction Z measurement connected to data qubits 7 and 8. Specifically, the logical qubit 420 includes an auxiliary qubit 11 for error correction Z measurement and merging, connected to data qubits 5 and 6. Specifically, the logical qubit 420 includes an auxiliary qubit 16 for error correction X measurement connected to data qubits 5-8. Next, we will move on to the explanation of Figure 5.

[0058] Figure 5 shows a quantum circuit 500 that generates logical Bell states for logical qubits 410 and 420. In Figure 5, each horizontal line in the quantum circuit 500 represents the time axis corresponding to one of the qubits.

[0059] Quantum bits 1-4 are in logical state |0 L A The notation |x> indicates a state in which x is observed with 100% probability. x is, for example, a value. Logical state |0 L A > is, for example, |0000> + |1111>. Quantum bits 5-8 are in the logical state |0 L B > is the logical state |0 L B For example, 〉 is |0000〉 + |1111〉. The qubits 10 and 11 are in state |0〉, respectively.

[0060] The information processing device 100 executes a quantum state transfer 501, which sets qubits 10 and 11 to the state |00〉+|11〉, respectively. This allows the information processing device 100 to entangle qubits 10 and 11. The information processing device 100 uses qubit 10 as the control bit and qubit 3 as the target bit and executes a controlled NOT gate 502. The information processing device 100 uses qubit 10 as the control bit and qubit 4 as the target bit and executes a controlled NOT gate 503.

[0061] The information processing device 100 executes a Hadamard gate 504 on qubit 10. The information processing device 100 uses qubit 11 as the control bit and qubit 5 as the target bit and executes a controlled NOT gate 505. The information processing device 100 uses qubit 11 as the control bit and qubit 6 as the target bit and executes a controlled NOT gate 506.

[0062] The information processing apparatus 100 executes a Hadamard gate 507 on the qubit 11. The information processing apparatus 100 performs Z measurement 508 on the qubits 10 and 11. If the product of the measurement results of the qubits 10 and 11 is 1, the information processing apparatus 100 executes a Z gate 509 on the qubits 1 and 3.

[0063] Thereby, the information processing apparatus 100 can generate the logical Bell state of the logical qubits 410 and 420 without performing splitting. Specifically, the information processing apparatus 100 converts the qubits 1 to 8 into the logical Bell state |Φ L + 〉. As a result, the information processing apparatus 100 can reduce the processing time required for generating the logical Bell state of the logical qubits 410 and 420.

[0064] (First connection processing procedure) Next, an example of the first connection processing procedure executed by the information processing apparatus 100 will be described with reference to FIG. 6 and FIG. 7. The first connection processing corresponds to the operation of generating the logical Bell state of the logical qubits 410 and 420 shown in FIG. 5. The first connection processing is implemented by, for example, the CPU 201 shown in FIG. 2, a storage area such as the memory 202 and the recording medium 205, and the network I / F 203.

[0065] FIG. 6 and FIG. 7 are flowcharts showing an example of the first connection processing procedure. In FIG. 6, the information processing apparatus 100 sets each of the qubits 1 to 4 to the logical state |0 L A 〉, and sets each of the qubits 5 to 8 to the logical state |0 L B 〉 (step S601).

[0066] The information processing apparatus 100 sets each of the qubits 10 and 11 to the state |0〉 (step S602). The information processing apparatus 100 executes quantum state transfer that sets the qubits 10 and 11 to the state |00〉+|11〉 respectively (step S603).

[0067] The information processing device 100 uses qubit 10 as the control bit and qubit 3 as the target bit and executes a controlled NOT gate (step S604). The information processing device 100 uses qubit 10 as the control bit and qubit 4 as the target bit and executes a controlled NOT gate (step S605). The information processing device 100 executes an Adamard gate on qubit 10 (step S606).

[0068] The information processing device 100 uses qubit 11 as the control bit and qubit 5 as the target bit to execute a controlled NOT gate (step S607). The information processing device 100 uses qubit 11 as the control bit and qubit 6 as the target bit to execute a controlled NOT gate (step S608). Next, we will move on to the explanation of Figure 7.

[0069] In Figure 7, the information processing device 100 performs an Adamard gate on qubit 11 (step S701). The information processing device 100 performs a Z measurement on qubits 10 and 11 (step S702). The information processing device 100 determines whether the product of the measurement results of qubits 10 and 11 is 1 or not (step S703).

[0070] Here, if the product of the measurement results of qubits 10 and 11 is not 1 (step S703: No), the information processing device 100 executes a Z gate on qubits 1 and 3 (step S704) and terminates the first connection process. On the other hand, if the product of the measurement results of qubits 10 and 11 is 1 (step S703: Yes), the information processing device 100 terminates the first connection process. As a result, the information processing device 100 enters the logical state |0 L A >|0 L B >+|1 L A >|1 L B > can be generated.

[0071] Next, using Figure 8, we will explain an example in which the information processing device 100 generates logical bell states for logical qubits 410 and 420 and performs error correction.

[0072] Figure 8 is an explanatory diagram showing a quantum circuit 800 in which the information processing device 100 generates logical bell states for logical qubits 410 and 420 and performs error correction. In Figure 8, each horizontal line of the quantum circuit 800 represents the time axis corresponding to one of the qubits.

[0073] Quantum bits 1-4 are in logical state |0 L A >. Quantum bits 5-8 are in logical state |0 L B >. Qubits 9-13 and 16 are each in state |0>. Specifically, the information processing device 100 performs multiple quantum operations on qubits 1-13 and 16 in a stepwise manner, as shown below. For example, two or more quantum operations belonging to the same stage may be executed in parallel. The thick lines in Figure 8 represent the quantum operations performed for error correction among the multiple quantum operations.

[0074] (8-1) In order to generate a logical Bell state, the information processing device 100 executes an Adamard gate 801 on the qubits 13 and 16 in step 1.

[0075] (8-2) In order to generate a logical bell state, the information processing device 100 executes a quantum state transfer 802 in step 2, setting qubits 10 and 11 to the state |00〉+|11〉, respectively. For error correction, in step 2, the information processing device 100 executes a controlled NOT gate 803 with qubits 13 and 16 as control bits and qubits 1 and 7 as target bits, respectively.

[0076] (8-3) In order to generate a logical bell state, the information processing device 100 executes a controlled NOT gate 804 in step 3, with qubit 10 as the control bit and qubit 3 as the target bit. In order to generate a logical bell state, the information processing device 100 executes a controlled NOT gate 804 in step 3, with qubit 11 as the control bit and qubit 5 as the target bit. For error correction, the information processing device 100 executes a controlled NOT gate 805 in step 3, with qubits 13 and 16 as control bits and qubits 2 and 8 as target bits.

[0077] (8-4) In order to generate a logical bell state, the information processing device 100 executes a controlled NOT gate 806 in step 4, with qubit 10 as the control bit and qubit 4 as the target bit. In order to generate a logical bell state, the information processing device 100 executes a controlled NOT gate 806 in step 4, with qubit 11 as the control bit and qubit 6 as the target bit. For error correction, the information processing device 100 executes a controlled NOT gate 807 in step 4, with qubits 13 and 16 as control bits and qubits 3 and 5 as target bits.

[0078] (8-5) In order to generate a logical Bell state, the information processing device 100 executes an Adamard gate 808 on the qubits 10 and 11 in step 5.

[0079] (8-6) In order to generate a logical bell state, the information processing device 100 performs a Z measurement 809 on qubits 10 and 11 in step 6. For error correction, in step 6, the information processing device 100 uses qubits 13 and 16 as control bits and qubits 4 and 6 as target bits and executes a controlled NOT gate 810 on each.

[0080] (8-7) For error correction, in step 7, the information processing device 100 uses qubits 1, 3, 5, and 7 as control bits and qubits 9, 10, 11, and 12 as target bits and executes a controlled NOT gate 811 for each.

[0081] (8-8) For error correction, in step 8, the information processing device 100 uses qubits 2, 4, 6, and 8 as control bits and qubits 9, 10, 11, and 12 as target bits and executes a controlled NOT gate 812 on each of them. For error correction, in step 8, the information processing device 100 executes a Hadamard gate 813 on qubits 13 and 16.

[0082] (8-9) For error correction, the information processing device 100 performs a Z measurement 814 on qubits 9-13 and 16. This allows the information processing device 100 to generate logical bell states for logical qubits 410 and 420 without performing a split. Specifically, the information processing device 100 generates logical bell states |Φ| for qubits 1-8. L + This allows the information processing device 100 to reduce the processing time required when generating the logical bell states of the logical qubits 410 and 420.

[0083] Furthermore, the information processing device 100 can generate logical Bell states for logical qubits 410 and 420, and can also perform error correction. Specifically, the information processing device 100 generates logical Bell states |Φ| for qubits 1 to 8. L + > This can be achieved. Therefore, the information processing device 100 can reduce the time required to start error correction. The information processing device 100 can reduce the time required from the start of generating the logical bell state of logical qubits 410 and 420 until the completion of error correction. The information processing device 100 can reduce the risk of error propagation.

[0084] (Second connection processing procedure) Next, an example of a second connection processing procedure performed by the information processing device 100 will be described using Figures 9 and 10. The second connection processing corresponds to the operation shown in Figure 8, which generates logical bell states for logical qubits 410 and 420 and performs error correction. The second connection processing is realized, for example, by the CPU 201 shown in Figure 2, storage areas such as memory 202 and recording medium 205, and network I / F 203.

[0085] Figures 9 and 10 are flowcharts of an example of the second connection processing procedure. In Figure 8, the information processing device 100 sets qubits 1 to 4 to the logical state |0 L A Set to > and set qubits 5-8 to the logical state |0 L B The information processing device 100 sets qubits 9-13 and 16 to state |0| (step S901).

[0086] The information processing device 100 executes a Hadamard gate on qubits 13 and 16 (step S903). The information processing device 100 performs a quantum state transfer to set qubits 10 and 11 to the state |00〉+|11〉, respectively (step S904).

[0087] The information processing device 100 uses qubits 13 and 16 as control bits and qubits 1 and 7 as target bits and executes controlled NOT gates on each (step S905). The information processing device 100 uses qubit 10 as a control bit and qubit 3 as a target bit and executes a controlled NOT gate (step S906). The information processing device 100 uses qubit 11 as a control bit and qubit 5 as a target bit and executes a controlled NOT gate (step S907).

[0088] The information processing device 100 uses qubits 13 and 16 as control bits and qubits 2 and 8 as target bits, and executes controlled NOT gates on each (step S908). The information processing device 100 uses qubit 10 as a control bit and qubit 4 as a target bit, and executes a controlled NOT gate on each (step S909). The information processing device 100 then proceeds to the process of step S1001, which will be described later in Figure 10.

[0089] In Figure 10, the information processing device 100 uses qubit 11 as the control bit and qubit 6 as the target bit to execute a controlled NOT gate (step S1001).

[0090] The information processing device 100 uses qubits 13 and 16 as control bits and qubits 3 and 5 as target bits, and executes controlled NOT gates on each (step S1002). The information processing device 100 executes an Adamard gate on qubits 10 and 11 (step S1003). The information processing device 100 performs a Z measurement on qubits 10 and 11 (step S1004).

[0091] The information processing device 100 uses qubits 13 and 16 as control bits and qubits 4 and 6 as target bits, and executes controlled NOT gates on each (step S1005). The information processing device 100 uses qubits 1, 3, 5, and 7 as control bits and qubits 9, 10, 11, and 12 as target bits, and executes controlled NOT gates on each (step S1006).

[0092] The information processing device 100 uses qubits 2, 4, 6, and 8 as control bits and qubits 9, 10, 11, and 12 as target bits, and executes controlled NOT gates on each (step S1007). The information processing device 100 executes Hadamard gates on qubits 13 and 16 (step S1008). The information processing device 100 performs Z measurements on qubits 9-13 and 16 (step S1009). The information processing device 100 terminates the second connection process. As a result, the information processing device 100 returns to the logical state |0 L A >|0L B >+|1 L A >|1 L B > can be generated.

[0093] Next, using Figures 11 to 13, we will explain conventional methods for generating logical bell states of logical qubits 1110 and 1120, and compare these conventional methods with the methods of the information processing device 100.

[0094] Figures 11 to 13 are explanatory diagrams illustrating a conventional example of generating a logical bell state for logical qubits 1110 and 1120. Specifically, Figure 11 shows a conventional example of the arrangement of multiple qubits in logical qubits 1110 and 1120 that are targeted for generating a logical bell state.

[0095] As shown in Figure 11, the logical qubit 1110 is located, for example, at node A. Specifically, the logical qubit 1110 includes four data qubits 1 to 4 arranged in a 2x2 matrix. Specifically, the logical qubit 1110 includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. Specifically, the logical qubit 1110 includes an auxiliary qubit 10 for error correction Z measurement connected to data qubits 3 and 4. Specifically, the logical qubit 1110 includes an auxiliary qubit 14 for merging connected to data qubit 3 and an auxiliary qubit 15 for merging connected to data qubit 4. Specifically, the logical qubit 1110 includes an auxiliary qubit 13 for error correction X measurement connected to data qubits 1 to 4.

[0096] As shown in Figure 11, the logical qubit 1120 is located, for example, at node B. Specifically, the logical qubit 1120 includes four data qubits 5-8 arranged in a 2x2 matrix. Specifically, the logical qubit 1120 includes an auxiliary qubit 12 for error correction Z measurement connected to data qubits 7 and 8. Specifically, the logical qubit 1120 includes an auxiliary qubit 11 for error correction Z measurement connected to data qubits 5 and 6. Specifically, the logical qubit 1120 includes an auxiliary qubit 17 for merging connected to data qubit 5, and an auxiliary qubit 18 for merging connected to data qubit 6. Specifically, the logical qubit 1120 includes an auxiliary qubit 16 for error correction X measurement connected to data qubits 5-8. Next, we will move on to the explanation of Figure 12.

[0097] Figures 12 and 13 show a quantum circuit 1200 that generates logical bell states for logical qubits 1110 and 1120, and also performs error correction. In Figure 12, each horizontal line in the quantum circuit 1200 represents the time axis corresponding to one of the qubits.

[0098] Quantum bits 1-4 are in logical state |0 L A >. Quantum bits 5-8 are in logical state |0 L B >. Qubits 9 to 18 are each in state |0>. A conventional computer implementing the conventional method performs multiple quantum operations on qubits 1 to 18 in a stepwise manner, as shown below. For example, two or more quantum operations belonging to the same stage may be executed in parallel. The thick lines in Figure 13 represent the quantum operations performed for error correction among the multiple quantum operations.

[0099] (12-1) In order to generate a logical bell state, a conventional computer performs a quantum state transfer 1201 in step 1, which sets qubits 14, 17 and qubits 15, 18 to the state |00〉+|11〉, respectively.

[0100] (12-2) In order to generate a logical bell state, a conventional computer executes a controlled NOT gate 1202 in step 2, with qubit 14 as the control bit and qubit 3 as the target bit. In order to generate a logical bell state, a conventional computer executes a controlled NOT gate 1202 in step 2, with qubit 17 as the control bit and qubit 5 as the target bit.

[0101] To generate a logical bell state, a conventional computer executes a controlled NOT gate 1202 in step 2, using qubit 15 as the control bit and qubit 4 as the target bit. To generate a logical bell state, a conventional computer executes a controlled NOT gate 1202 in step 2, using qubit 18 as the control bit and qubit 6 as the target bit.

[0102] (12-3) In order to generate a logical bell state, a conventional computer executes an Adamard gate 1203 on qubits 14-18 in step 3.

[0103] (12-4) In order to generate a logical Bell state, in step 4, the conventional computer performs a Z measurement 1204 on qubits 14-18. In order to generate a logical Bell state, in step 4, if the product of the measurement results of qubits 14-18 is 1, the conventional computer performs a Z gate 1205 on qubits 1 and 3.

[0104] (12-5) In order to generate a logical bell state, a conventional computer, in step 5, uses qubit 3 as the control bit and qubit 10 as the target bit, and executes a controlled NOT gate 1206.

[0105] (12-6) In order to generate a logical bell state, a conventional computer, in step 6, uses qubit 4 as the control bit and qubit 10 as the target bit, and executes a controlled NOT gate 1207. Next, we will move on to the explanation of Figure 13. Figure 13 specifically shows the continuation of the quantum circuit 1200.

[0106] (13-1) In order to generate a logical Bell state, the conventional computer performs a Z measurement 1301 on qubit 10 in step 7. For error correction, the conventional computer performs an Adamard gate 1302 on qubits 13 and 16 in step 7.

[0107] (13-2) For error correction, in step 8, the conventional computer uses qubits 13, 16, 3, and 7 as control bits and qubits 1, 5, 10, and 12 as target bits, and executes a controlled NOT gate 1303 for each.

[0108] (13-3) For error correction, in step 9, the conventional computer uses qubits 13, 16, 4, and 8 as control bits and qubits 2, 6, 10, and 12 as target bits, and executes a controlled NOT gate 1304 for each.

[0109] (13-4) For error correction, in step 10, the conventional computer uses qubits 13, 16, 1, and 5 as control bits and qubits 3, 7, 9, and 11 as target bits, and executes a controlled NOT gate 1306 for each. For error correction, in step 10, the conventional computer performs a Z measurement 1307 on qubits 10 and 12.

[0110] (13-5) For error correction, in step 11, the conventional computer uses qubits 13, 16, 2, and 6 as control bits and qubits 4, 8, 9, and 11 as target bits, and executes a controlled NOT gate 1308 for each.

[0111] (13-6) For error correction, the conventional computer executes the Hadamard gate 1309 on qubits 13 and 16 in step 12.

[0112] (13-7) For error correction, the conventional computer performs a Z measurement 1310 on qubits 9, 11, 13, and 16 in step 13. This allows the conventional computer to generate logical bell states for logical qubits 1110 and 1120 and perform error correction.

[0113] (Conventional processing procedure) Next, using Figures 14 to 16, we will explain an example of a conventional processing procedure performed by a conventional computer.

[0114] Figures 14 to 16 are flowcharts of an example of a conventional processing procedure. In Figure 14, the conventional computer sets qubits 1 to 4 to the logical state |0 L A Set to > and set qubits 5-8 to the logical state |0 L B Set to > (step S1401).

[0115] The conventional computer sets qubits 9 to 18 to state |0〉 (step S1402). The conventional computer then performs a quantum state transfer, setting qubits 14 and 17 and qubits 15 and 18 to state |00〉+|11〉 (step S1403).

[0116] A conventional computer uses qubit 14 as the control bit and qubit 3 as the target bit to execute a controlled NOT gate (step S1404). A conventional computer uses qubit 17 as the control bit and qubit 5 as the target bit to execute a controlled NOT gate (step S1405).

[0117] The conventional computer uses qubit 15 as the control bit and qubit 4 as the target bit to execute a controlled NOT gate (step S1406). The conventional computer uses qubit 18 as the control bit and qubit 6 as the target bit to execute a controlled NOT gate (step S1407). The conventional computer then proceeds to step S1501, which will be described later in Figure 15.

[0118] In Figure 15, the conventional computer performs an Adamard gate on qubits 14-18 (step S1501). The conventional computer then performs a Z measurement on qubits 14-18 (step S1502).

[0119] The conventional computer determines whether the product of the measurement results of qubits 14-18 is 1 or not (step S1503). If the product of the measurement results of qubits 14-18 is not 1 (step S1503: No), the conventional computer executes a Z gate on qubits 1 and 3 (step S1504) and proceeds to step S1505. On the other hand, if the product of the measurement results of qubits 14-18 is 1 (step S1503: Yes), the conventional computer proceeds to step S1505.

[0120] In step S1505, the conventional computer uses qubit 3 as the control bit and qubit 10 as the target bit to execute a controlled NOT gate (step S1505). The conventional computer uses qubit 4 as the control bit and qubit 10 as the target bit to execute a controlled NOT gate (step S1506).

[0121] The conventional computer performs a Z measurement on qubit 10 (step S1507). The conventional computer performs an Hadamard gate on qubits 13 and 16 (step S1508). The conventional computer then proceeds to step S1601, which will be described later in Figure 16.

[0122] In Figure 16, the conventional computer uses qubits 13, 16, 3, and 7 as control bits and qubits 1, 5, 10, and 12 as target bits, and executes controlled NOT gates for each (step S1601).

[0123] A conventional computer uses qubits 13, 16, 4, and 8 as control bits and qubits 2, 6, 10, and 12 as target bits, and executes controlled NOT gates on each (step S1602). A conventional computer uses qubits 13, 16, 1, and 5 as control bits and qubits 3, 7, 9, and 11 as target bits, and executes controlled NOT gates on each (step S1603).

[0124] The conventional computer uses qubits 13, 16, 2, and 6 as control bits and qubits 4, 8, 9, and 11 as target bits, and executes controlled NOT gates on each (step S1604). The conventional computer executes an Hadamard gate on qubits 13 and 16 (step S1605). The conventional computer performs a Z measurement on qubits 9-13 and 16 (step S1606). Then, the conventional computer terminates its conventional processing. As a result, the conventional computer enters the logical state |0 L A >|0 L B >+|1 L A >|1 L B > can be generated.

[0125] As shown in Figures 4 to 10, the information processing device 100 can generate the logical bell state of logical qubits 410 and 420 without performing a split process by performing the merge process in steps S601 to S608 and S701 to S704. On the other hand, as shown in Figures 11 to 16, in the conventional method, the merge process in steps S1401 to S1407 and S1501 to S1503 is performed, followed by the split process in steps S1504 to S1507. Thus, the information processing device 100 can reduce the processing time required to generate the logical bell state of logical qubits 410 and 420 compared to the conventional method.

[0126] As shown in Figures 4 to 10, the information processing device 100 can generate logical bell states for logical qubits 410 and 420 and perform error correction. For example, in steps S901 to S909 and S1001 to S1009, the information processing device 100 can generate logical bell states for logical qubits 410 and 420 and perform error correction.

[0127] On the other hand, as shown in Figures 11 to 16, in the conventional method, error correction is performed after generating the logical bell state of logical qubits 1110 and 1120. In the conventional method, for example, in steps S1401 to S1407 and S1501 to S1507, the logical bell state of logical qubits 1110 and 1120 is generated, and then in steps S1508 and S1601 to S1606, error correction is performed.

[0128] Thus, the information processing device 100 can reduce the time required to start error correction compared to conventional methods. The information processing device 100 can reduce the time required from the start of generating the logical bell states of logical qubits 410 and 420 to the completion of error correction compared to conventional methods.

[0129] Next, using Figures 17 to 21, we will explain an example of the accuracy of the measurement results of data qubits in the information processing device 100. Specifically, we will show an example of the accuracy of the measurement results of data qubits when the information processing device 100 generates the logical bell states of logical qubits 1710 and 1720 shown in Figure 17 and performs error correction.

[0130] Figures 17 to 21 are explanatory diagrams illustrating examples of the accuracy of the measurement results of data qubits. Specifically, Figure 17 shows an example of the arrangement of multiple qubits in logical qubits 1710 and 1720 that generate the logical bell state.

[0131] As shown in Figure 17, the logical qubit 1710 specifically includes four data qubits 1 to 4 arranged in a 2x2 matrix. Specifically, the logical qubit 1710 includes an auxiliary qubit 9 connected to data qubits 1 and 2 for error correction Z measurement. Specifically, the logical qubit 1710 includes an auxiliary qubit 10 connected to data qubits 3 and 4 for error correction Z measurement and merging. Specifically, the logical qubit 1710 includes an auxiliary qubit 11 connected to data qubits 1 to 4 for error correction X measurement.

[0132] As shown in Figure 17, the logical qubit 1720 specifically includes four data qubits 5-8 arranged in a 2x2 matrix. Specifically, the logical qubit 1720 includes an auxiliary qubit 13 for error correction Z measurement connected to data qubits 7 and 8. Specifically, the logical qubit 1720 includes an auxiliary qubit 12 for error correction Z measurement and merging processing connected to data qubits 5 and 6. Specifically, the logical qubit 1720 includes an auxiliary qubit 14 for error correction X measurement connected to data qubits 5-8.

[0133] The arrangement of multiple qubits in logical qubits 1710 and 1720 is determined to minimize the number of pairs of auxiliary qubits that directly entangle. For example, in the example in Figure 17, the pair of auxiliary qubits that entangle is one of the pairs of auxiliary qubits 10 and 12. Next, we will move on to the explanation of Figure 18.

[0134] Figure 18 shows a quantum circuit 1800 in which the information processing device 100 generates logical bell states for logical qubits 1710 and 1720, and also performs error correction. In Figure 18, each horizontal line in the quantum circuit 1800 represents the time axis corresponding to one of the qubits.

[0135] The information processing device 100 performs multiple quantum operations on qubits 1 to 14 in a stepwise manner. For example, two or more quantum operations belonging to the same step are executed in parallel. The thick lines in Figure 18 represent quantum operations performed for error correction among the multiple quantum operations. The information processing device 100 obtains measurement results for data qubits 1 to 8 by performing multiple simulations in which it performs multiple quantum operations on qubits 1 to 14 in a stepwise manner according to the quantum circuit 1800.

[0136] During the simulation, for example, the processing time for a one-qubit gate is assumed to be 5 ns. During the simulation, for example, the processing time for a two-qubit gate is assumed to be 20 ns. During the simulation, for example, the processing time for a measurement is assumed to be 35 ns. During the simulation, for example, the processing time for a state transfer is assumed to be 60 ns.

[0137] Here, qubits have the property that errors can occur probabilistically. For example, at each stage of performing a quantum operation, a qubit has a probability p 1G , probability p 2G , or probability p M An error occurs. Additionally, each time auxiliary qubits for the merge process are entangled, an error occurs in the qubit with probability p. Specifically, in quantum operation 1801 in Figure 18, an error occurs in the qubit with probability p.

[0138] Now, let's move on to the explanation of Figure 19, and assuming p=0.0, the probability p 1G , probability p 2G , and probability p M Without considering the above, an example of the accuracy of the measurement results for data qubits 1 to 8 when the information processing device 100 performs simulations 10,000 times will be described.

[0139] Table 1900 in Figure 19 shows the multiple values ​​that result from the measurement of data qubits 1 to 8, and the frequency with which the measurement results of data qubits 1 to 8 occur at each of these values. The multiple values ​​are, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no error occurs.

[0140] As shown in Table 1900, no errors were observed in the measurement results for data qubits 1 to 8, and the accuracy F (Fidelity) is 1.000 ± 0.000.

[0141] Next, we move on to the explanation of Figure 20, and assuming p=0.1, the probability p 1G , probability p 2G , and probability p M Without considering the above, an example of the accuracy of the measurement results for data qubits 1 to 8 when the information processing device 100 performs simulations 10,000 times will be described.

[0142] Table 2000 in Figure 20 shows the multiple values ​​that result from the measurement of data qubits 1 to 8, and the frequency with which the measurement results of data qubits 1 to 8 occur at each of these values. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no error occurs.

[0143] Multiple values ​​include, for example, 11110011, 00000011, 00001100, and 11111100. 11110011, 00000011, 00001100, and 11111100 are the values ​​where errors occurred.

[0144] As shown in Table 2000, errors may appear in the measurement results of data qubits 1 to 8. The fidelity (F) is 0.962 ± 0.002.

[0145] Next, we move on to the explanation of Figure 21, and assuming p=0.1, the probability p 1G , probability p 2G , and probability p M Taking this into consideration, we will now describe an example of the accuracy of the measurement results for data qubits 1 to 8 when the information processing device 100 performs simulations 10,000 times.

[0146] Table 2100 in Figure 21 shows the multiple values ​​that result from the measurement of data qubits 1 to 8, and the frequency with which the measurement results of data qubits 1 to 8 occur at each of these values. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no error occurs.

[0147] This includes multiple values, such as 11010000, 11110001, 00000100, 00100000, 00001110, 00000001, 11110011, and 11111100. 11010000, 11110001, 00000100, 00100000, 00001110, 00000001, 11110011, and 11111100 are the values ​​where the error occurred.

[0148] As shown in Table 2100, errors may appear in the measurement results of data qubits 1 to 8. The fidelity (F) is 0.778 ± 0.004.

[0149] Next, using Figures 22 to 28, we will explain an example of the accuracy of data qubit measurement results using conventional methods. Specifically, we will show an example of the accuracy of data qubit measurement results when a conventional computer generates the logical bell states of logical qubits 2210 and 2220 shown in Figure 22 and performs error correction.

[0150] Figures 22 to 28 are explanatory diagrams illustrating examples of the accuracy of the measurement results of data qubits. Specifically, Figure 22 shows an example of the arrangement of multiple qubits in logical qubits 2210 and 2220, which are the targets for generating the logical bell state.

[0151] As shown in Figure 22, the logic qubit 2210 specifically includes four data qubits 1 to 4 arranged in a 2x2 matrix. Specifically, the logic qubit 2210 includes an auxiliary qubit 9 for error correction Z measurement connected to data qubits 1 and 2. Specifically, the logic qubit 2210 includes auxiliary qubits 15 and 16 for error correction Z measurement connected to data qubits 3 and 4. Specifically, the logic qubit 2210 includes an auxiliary qubit 10 for merging operation connected to data qubits 3 and 4. Specifically, the logic qubit 2210 includes an auxiliary qubit 11 for error correction X measurement connected to data qubits 1 to 4.

[0152] As shown in Figure 22, the logical qubit 2220 specifically includes four data qubits 5-8 arranged in a 2x2 matrix. Specifically, the logical qubit 2220 includes an auxiliary qubit 13 for error correction Z measurement connected to data qubits 7 and 8. Specifically, the logical qubit 2220 includes auxiliary qubits 17 and 18 for error correction Z measurement connected to data qubits 5 and 6. Specifically, the logical qubit 2220 includes an auxiliary qubit 12 for merging. Specifically, the logical qubit 2220 includes an auxiliary qubit 14 for error correction X measurement connected to data qubits 5-8. Next, we will move on to the explanation of Figures 23-25.

[0153] Figures 23 to 25 show a quantum circuit 2300 in which a conventional computer generates logical bell states for logical qubits 2210 and 2220, and also performs error correction. In Figure 23, each horizontal line in the quantum circuit 2300 represents the time axis corresponding to one of the qubits.

[0154] Conventional computers perform multiple quantum operations on qubits 1 to 14 in a stepwise manner. For example, two or more quantum operations belonging to the same step are executed in parallel. The thick lines in Figures 23 to 25 represent the quantum operations performed for error correction among the multiple quantum operations. By performing multiple simulations in which the conventional computer performs multiple quantum operations on qubits 1 to 14 in a stepwise manner according to the quantum circuit 2300, the measurement results of data qubits 1 to 8 are obtained.

[0155] As mentioned above, qubits have the property that errors can occur probabilistically. For example, at each stage of performing a quantum operation, a qubit has a probability p 1G , probability p 2G , or probability p M An error occurs. Additionally, each time auxiliary qubits for the merge process are entangled, an error occurs in the qubit with probability p. Specifically, in quantum operations 2301 and 2302 in Figure 23, an error occurs in the qubit with probability p.

[0156] Now, let's move on to the explanation of Figure 26, and assuming p=0.0, the probability p 1G , probability p 2G , and probability p M Without considering the factors mentioned above, we will describe an example of the accuracy of the measurement results for data qubits 1 to 8 when a conventional computer performs simulations 10,000 times.

[0157] Table 2600 in Figure 26 shows the multiple values ​​that result from the measurement of data qubits 1 to 8, and the frequency with which the measurement results of data qubits 1 to 8 occur at each of these values. The multiple values ​​are, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no error occurs.

[0158] As shown in Table 2600, no errors were observed in the measurement results for data qubits 1 to 8, and the accuracy F (Fidelity) is 1.000 ± 0.000.

[0159] Next, we move on to the explanation of Figure 27, and assuming p=0.1, the probability p 1G , probability p 2G , and probability p M Without considering the factors mentioned above, we will describe an example of the accuracy of the measurement results for data qubits 1 to 8 when a conventional computer performs simulations 10,000 times.

[0160] Table 2700 in Figure 27 shows the multiple values ​​that result from the measurement of data qubits 1 to 8, and the frequency with which the measurement results of data qubits 1 to 8 occur at each of these values. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no error occurs.

[0161] It includes multiple values, for example, 00100011, 11011100, 11101111, 00010000, 11100000, 00011111, 11100011, 11101100, 00011100, and 00010011. 00100011, 11011100, 11101111, 00010000, 11100000, 00011111, 11100011, 11101100, 00011100, and 00010011 are the values ​​in which the error occurred.

[0162] As shown in Table 2700, errors may appear in the measurement results of data qubits 1 to 8. The fidelity (F) is 0.925 ± 0.002.

[0163] Next, we move on to the explanation of Figure 28, and assuming p=0.1, the probability p 1G , probability p 2G , and probability p M Taking this into consideration, we will describe an example of the accuracy of the measurement results for data qubits 1 to 8 when a conventional computer performs simulations 10,000 times.

[0164] Table 2800 in Figure 28 shows the multiple values ​​that result from the measurement of data qubits 1 to 8, and the frequency with which the measurement results of data qubits 1 to 8 occur at each of these values. The multiple values ​​include, for example, 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000. 11111111, 11110000, 11001100, 11000011, 00111100, 00110011, 00001111, and 00000000 are values ​​in which no error occurs.

[0165] This includes multiple values, such as 00100011, 00101100, 11101111, 00011111, 11100000, 00010000, 11100011, 00010011, 11101100, and 00011100. 00100011, 00101100, 11101111, 00011111, 11100000, 00010000, 11100011, 00010011, 11101100, and 00011100 are the values ​​in which the error occurred.

[0166] As shown in Table 2800, errors may appear in the measurement results of data qubits 1 to 8. The fidelity (F) is 0.670 ± 0.005.

[0167] As shown in Figures 17 to 21, the information processing device 100 can reduce the number of pairs of auxiliary qubits that directly entangle, and can reduce the number of quantum operations that entangle auxiliary qubits with each other. Therefore, the information processing device 100 can reduce the number of times an error may occur in a qubit with probability p. The information processing device 100 can more easily suppress situations in which errors occur in the measurement results of data qubits 1 to 8 due to quantum operations that entangle auxiliary qubits with each other.

[0168] Furthermore, the information processing device 100 can reduce the split processing, generate logical bell states for logical qubits 410 and 420, and perform error correction, thereby reducing processing time. Therefore, the information processing device 100 can reduce the number of steps required to perform quantum operations. The information processing device 100 assigns probability p to the qubits. 1G , probability p 2G , or probability p MThis makes it possible to reduce the number of times errors can occur. The information processing device 100 can easily suppress situations in which errors occur in the measurement results of data qubits 1 to 8 due to the length of processing time. The information processing device 100 can reduce the number of gates that form the quantum circuit. The information processing device 100 can easily avoid the occurrence of error propagation.

[0169] On the other hand, as shown in Figures 22 to 28, in conventional methods, the number of pairs of auxiliary qubits that directly entangle is two. Therefore, in conventional methods, it is difficult to suppress the occurrence of errors in the measurement results of data qubits 1 to 8 due to quantum operations that entangle auxiliary qubits.

[0170] Furthermore, conventional methods have the problem of easily increasing processing time because error correction is performed after generating the logical bell states of logical qubits 410 and 420. For this reason, conventional methods have difficulty preventing errors from occurring in the measurement results of data qubits 1 to 8 due to the length of processing time.

[0171] Thus, the information processing device 100 can more easily avoid situations where errors occur in the measurement results of data qubits 1 to 8 compared to conventional methods. As shown in Tables 1900, 2000, 2100 and Tables 2600, 2700, 2800, the information processing device 100 can improve the accuracy F (Fidelity) compared to conventional methods.

[0172] The above describes the case in which the information processing device 100 generates a logical bell state of two logical qubits, each containing four data qubits arranged in a 2x2 matrix, but it is not limited to this case. For example, the information processing device 100 may generate a logical bell state of N qubits arranged in an NxN matrix. 2 It is also possible to generate a logical bell state of two logical qubits, each containing a data qubit.

[0173] Next, using Figures 29 and 30, we will describe an example of generating logical bell states of logical qubits 2910 and 2920, each containing nine data qubits arranged in a 3x3 matrix.

[0174] Figures 29 and 30 are explanatory diagrams illustrating an example of generating a logical bell state for logical qubits 2910 and 2920. Specifically, Figure 29 shows an example of the arrangement of multiple qubits in logical qubits 2910 and 2920 that are targeted for generating the logical bell state.

[0175] As shown in Figure 29, the logical qubit 2910 is located, for example, at node A. Specifically, the logical qubit 2910 includes nine data qubits 1 to 9 arranged in a 3x3 matrix. Specifically, the logical qubit 2910 includes an auxiliary qubit 19 for error correction Z measurement connected to data qubits 2, 3, 5, and 6. Specifically, the logical qubit 2910 includes an auxiliary qubit 20 for error correction Z measurement connected to data qubits 4, 5, 7, and 8. Specifically, the logical qubit 2910 includes an auxiliary qubit 21 for error correction Z measurement connected to data qubits 1 and 2.

[0176] The logic qubit 2910 specifically includes an auxiliary qubit 22 for error correction Z measurement and merging, connected to data qubits 8 and 9. The logic qubit 2910 specifically includes an auxiliary qubit 27 for error correction X measurement, connected to data qubits 1, 2, 4, and 5. The logic qubit 2910 specifically includes an auxiliary qubit 28 for error correction X measurement, connected to data qubits 5, 6, 8, and 9. The logic qubit 2910 specifically includes an auxiliary qubit 29 for error correction X measurement, connected to data qubits 4 and 7. The logic qubit 2910 specifically includes an auxiliary qubit 30 for error correction X measurement, connected to data qubits 3 and 6.

[0177] The logical qubit 2910 specifically includes an auxiliary qubit 35 for merging, connected to data qubits 7 and 8. The logical qubit 2910 also specifically includes an auxiliary qubit 36 ​​for merging, connected to auxiliary qubits 22 and 35. Thus, the arrangement of the multiple qubits in the logical qubit 2910 is determined such that the number of pairs of auxiliary qubits that directly entangle is minimized.

[0178] As shown in Figure 29, the logical qubit 2920 is located, for example, at node B. Specifically, the logical qubit 2920 includes nine data qubits 10-18 arranged in a 3x3 matrix. Specifically, the logical qubit 2920 includes an auxiliary qubit 24 for error correction Z measurement connected to data qubits 14, 15, 17, and 18. Specifically, the logical qubit 2920 includes an auxiliary qubit 23 for error correction Z measurement connected to data qubits 10, 11, 13, and 14. Specifically, the logical qubit 2920 includes an auxiliary qubit 21 for error correction Z measurement connected to data qubits 16 and 17.

[0179] The logic qubit 2920 specifically includes an auxiliary qubit 25 connected to data qubits 11 and 12 for error correction Z measurement and merging. The logic qubit 2920 specifically includes an auxiliary qubit 32 connected to data qubits 13, 14, 16, and 17 for error correction X measurement. The logic qubit 2920 specifically includes an auxiliary qubit 31 connected to data qubits 11, 12, 14, and 15 for error correction X measurement. The logic qubit 2920 specifically includes an auxiliary qubit 33 connected to data qubits 10 and 13 for error correction X measurement. The logic qubit 2920 specifically includes an auxiliary qubit 34 connected to data qubits 15 and 18 for error correction X measurement.

[0180] Logical qubit 2920 specifically includes an auxiliary qubit 37 for merging, connected to data qubits 10 and 11. Logical qubit 2920 specifically includes an auxiliary qubit 38 for merging, connected to auxiliary qubits 25 and 37. Thus, the arrangement of multiple qubits in logical qubit 2920 is determined to minimize the number of pairs of auxiliary qubits that directly entangle. For example, in the example in Figure 29, the pair of auxiliary qubits that entangle is one of the pairs of auxiliary qubits 36 and 38. Next, we will move on to the explanation of Figure 30.

[0181] Figure 30 shows a quantum circuit 3000 that generates logical Bell states for logic qubits 2910 and 2920. In Figure 30, each horizontal line in the quantum circuit 3000 represents the time axis corresponding to one of the qubits. Specifically, the example in Figure 30 shows qubits 7-12, 22, 25, and 35-38 of logic qubits 2910 and 2920.

[0182] Qubits 22, 25, and 35-38 are each in state |0〉. The information processing device 100 performs a quantum state transfer 3001 to set qubits 36 and 38 to state |00〉+|11〉. This allows the information processing device 100 to entangle qubits 36 and 38.

[0183] The information processing device 100 uses qubit 36 ​​as the control bit and qubit 22 as the target bit to execute a controlled NOT gate 3002. The information processing device 100 uses qubit 38 as the control bit and qubit 25 as the target bit to execute a controlled NOT gate 3002.

[0184] The information processing device 100 executes a controlled NOT gate 3003 using qubit 36 ​​as the control bit and qubit 35 as the target bit. The information processing device 100 executes a controlled NOT gate 3003 using qubit 38 as the control bit and qubit 37 as the target bit.

[0185] The information processing apparatus 100 uses the qubit 35 as a control bit, uses the qubit 7 as a target bit, and executes a controlled NOT gate 3004. The information processing apparatus 100 uses the qubit 37 as a control bit, uses the qubit 7 as a target bit, and executes a controlled NOT gate 3004.

[0186] The information processing apparatus 100 uses the qubit 35 as a control bit, uses the qubit 8 as a target bit, and executes a controlled NOT gate 3005. The information processing apparatus 100 uses the qubit 37 as a control bit, uses the qubit 11 as a target bit, and executes a controlled NOT gate 3005. The information processing apparatus 100 uses the qubit 22 as a control bit, uses the qubit 9 as a target bit, and executes a controlled NOT gate 3005. The information processing apparatus 100 uses the qubit 25 as a control bit, uses the qubit 12 as a target bit, and executes a controlled NOT gate 3005.

[0187] The information processing apparatus 100 executes a Hadamard gate 3006 on the qubits 22, 25, 35 to 38. If the product of the measurement results of the qubits 22, 25, 35 to 38 is 1, the information processing apparatus 100 executes a logical Z gate 3007.

[0188] Thereby, the information processing apparatus 100 can generate the logical Bell state of the logical qubits 2910, 2920 without performing splitting. Specifically, the information processing apparatus 100 converts the qubits 1 to 8 into the logical Bell state |Φ L + 〉=|0 L A 〉|0 L B 〉+|1 L A 〉|1 L B 〉. Accordingly, the information processing apparatus 100 can reduce the processing time required when generating the logical Bell state of the logical qubits 2910, 2920.

[0189] Next, with reference to FIG. 31 to FIG. 34, the reason why the information processing apparatus 100 does not need to perform the split processing will be described. Specifically, first, with reference to FIG. 31 and FIG. 32, the reason for performing the split processing by the conventional method will be described.

[0190] FIG. 31 and FIG. 32 are explanatory diagrams illustrating the reason for performing the split processing. In the example of FIG. 31, for simplification of description, a case where logical qubits 3110 and 3120 are merged by a qubit 9 using a conventional method will be described.

[0191] As shown in FIG. 31, in the logical qubit 3110, auxiliary qubits that are not entangled are present on the logical qubit 3120 side rather than on the data qubits 1 to 4 side. Similarly, in the logical qubit 3120, auxiliary qubits that are not entangled are present on the logical qubit 3110 side rather than on the data qubits 5 to 8 side. Thus, in the logical qubits 3110 and 3120, auxiliary qubits that are not entangled exist between the data qubits 3 and 4 and the data qubits 5 and 6.

[0192] The logical state |0〉 of the logical qubit 3110: |0 L A 〉=|0000〉+|1111〉. The logical state |1〉 of the logical qubit 3110: |1 L A 〉=|0011〉+|1100〉. The logical state |0〉 of the logical qubit 3120: |0 L B 〉=|0000〉+|1111〉. The logical state |1〉 of the logical qubit 3120: |1 L B 〉=|0011〉+|1100〉. The error-corrected state is a state represented by the sum of products of the logical states described above. For example, the error-corrected state is a state represented by the following formula (1) or the following formula (2).

[0193] [Formula]

[0194]

number

[0195] Next, we will move on to the explanation of Figure 32. Figure 32 shows the quantum circuit 3200 that generates the logic bell states of logic qubits 3110 and 3120. In Figure 32, we will explain the changes in the quantum states of qubits 1 to 9 at each time point (a) to (e) represented by the dotted lines of the quantum circuit 3200.

[0196] At point (a), the quantum states of qubits 1 through 9 are represented by the following equation (3). The first digit of the quantum state corresponds to qubit 9.

[0197]

number

[0198] At point (b), the quantum states of qubits 1 to 9 are the quantum states represented by equation (4) below.

[0199]

number

[0200] At point (c), the quantum states of qubits 1 to 9 are the quantum states represented by equation (5) below.

[0201]

number

[0202] At point (d), the quantum states of qubits 1 to 9 are the quantum states represented by equation (6) below.

[0203]

number

[0204] At point (e), observations indicate that with a probability of 1 / 2, the quantum states of qubits 1 to 9 are the quantum states represented by equation (7) below.

[0205]

number

[0206] Thus, in the conventional method, the quantum states of qubits 1 to 8 in equation (7) above do not become error-corrected. In the conventional method, in logical qubits 3110 and 3120, there are auxiliary qubits that are not entangled between data qubits 3 and 4 and data qubits 5 and 6, so the quantum states of qubits 1 to 8 do not become error-corrected. Therefore, the conventional method performs a split operation. The conventional method has the problem of increasing the processing time required to generate the logical bell states of logical qubits 3110 and 3120.

[0207] Next, using Figures 33 and 34, we will explain why the information processing device 100 does not need to perform split processing.

[0208] Figures 33 and 34 are explanatory diagrams illustrating why split processing is not necessary. In the example in Figure 33, for the sake of simplicity, we will describe the case where the information processing device 100 merges logical qubits 3310 and 3320 with qubit 9.

[0209] As shown in Figure 33, logic qubit 3310 has no unentangled auxiliary qubits on the logic qubit 3320 side compared to data qubits 1-4. Similarly, logic qubit 3320 has no unentangled auxiliary qubits on the logic qubit 3310 side compared to data qubits 5-8. Thus, in logic qubits 3310 and 3320, there are no unentangled auxiliary qubits between data qubits 3 and 4 and data qubits 5 and 6. Next, we will move on to the explanation of Figure 34.

[0210] FIG. 34 illustrates a quantum circuit 3400 that generates a logical Bell state of logical qubits 3310 and 3320. In FIG. 34, changes in the quantum states of qubits 1 to 9 at respective time points (a) to (e) represented by dotted lines in the quantum circuit 3400 will be described.

[0211] At the time point (a), the quantum states of qubits 1 to 9 are the quantum states represented by the following formula (8). The first digit on the quantum state corresponds to qubit 9.

[0212] [Formula]

[0213] At the time point (b), the quantum states of qubits 1 to 9 are the quantum states represented by the following formula (9).

[0214] [Formula]

[0215] At the time point (c), the quantum states of qubits 1 to 9 are the quantum states represented by the following formula (10).

[0216] [Formula]

[0217] At the time point (d), the quantum states of qubits 1 to 9 are the quantum states represented by the following formula (11).

[0218] [Formula]

[0219] At the time point (e), by observation, with a probability of 1 / 2, the quantum states of qubits 1 to 9 are the quantum states represented by the following formula (12).

[0220]

number

[0221] Thus, the information processing device 100 can make the quantum states of qubits 1 to 8 in equation (12) above into an error-corrected state. The information processing device 100 can entangle all the auxiliary qubits between data qubits 3 and 4 and data qubits 5 and 6, and make the quantum states of qubits 1 to 8 into an error-corrected state. Therefore, the information processing device 100 can avoid performing a split operation. The information processing device 100 can reduce the processing time required to generate the logical bell states of logical qubits 3310 and 3320.

[0222] As explained above, the information processing device 100 can generate a logical bell state between two logical qubits by entanglement of all auxiliary qubits between the two logical qubits without the need for data qubits. This allows the information processing device 100 to avoid performing a split operation and reduces the processing time required to generate the logical bell state between the two logical qubits.

[0223] According to the information processing device 100, when generating the logical bell state of two logical qubits, error correction of the data qubit can be performed by utilizing an auxiliary qubit for error correction among the multiple qubits in each logical qubit. As a result, the information processing device 100 can perform error correction while generating the logical bell state of two logical qubits, thereby reducing the time required to start error correction. The information processing device 100 can reduce the processing time required to complete the generation of the logical bell state of two logical qubits and to complete the error correction. The information processing device 100 can more easily avoid an increase in the error rate that occurs with an increase in processing time.

[0224] According to the information processing device 100, a logical bell state of two logical qubits can be generated in which multiple qubits are arranged such that the number of entangled auxiliary qubits is minimized. The information processing device 100 can reduce the number of entanglements and reduce the processing time required to generate the logical bell state of two logical qubits. The information processing device 100 can also make it easier to avoid the increase in the error rate associated with entanglement.

[0225] According to the information processing device 100, a logical bell state of two logical qubits can be generated in a binary tree-like structure where two or more data qubits are used as leaves and one directly entangled auxiliary qubit is used as the root, with one or more auxiliary qubits acting as nodes. In this way, the information processing device 100 can generate a logical bell state of two logical qubits that minimizes the number of entangled auxiliary qubits.

[0226] According to the information processing device 100, a logical bell state of two logical qubits can be generated in which four data qubits are arranged in a 2x2 matrix, and one auxiliary qubit is directly connected to two of the data qubits. As a result, the information processing device 100 can generate a logical bell state of two logical qubits that minimizes the number of entangled auxiliary qubits.

[0227] According to the information processing device 100, a logical bell state of two logical qubits can be generated, in which nine data qubits are arranged in a 3x3 matrix. Each logical qubit has three auxiliary qubits arranged as nodes in a binary tree structure, with three data qubits on the side connected to the other logical qubit as leaves and one auxiliary qubit that is directly entangled as the root. As a result, the information processing device 100 can generate a logical bell state of two logical qubits with the minimum number of entangled auxiliary qubits.

[0228] The information processing method described in this embodiment can be implemented by executing a pre-prepared program on a computer such as a PC or workstation. The information processing program described in this embodiment is recorded on a computer-readable recording medium and executed by being read from the recording medium by the computer. The recording medium can be a hard disk, flexible disk, CD (Compact Disc)-ROM, MO (Magneto Optical Disc), DVD (Digital Versatile Disc), etc. Furthermore, the information processing program described in this embodiment may be distributed via a network such as the Internet.

[0229] With regard to the embodiments described above, the following additional information is disclosed.

[0230] (Note 1) In the arrangement of multiple qubits, including multiple data qubits and multiple auxiliary qubits, in each of the two logical qubits to be connected, all of the auxiliary qubits located on the side of the logical qubit that connects to the other logical qubit rather than the data qubit are entangled between the two logical qubits without going through the data qubit, thereby generating the logical bell state of the two logical qubits. An information processing program characterized by having a computer perform the processing.

[0231] (Note 2) The above generation process is: The information processing program according to Appendix 1, characterized in that, when generating the logical bell state of the two logical qubits, error correction of the data qubit is performed by using the auxiliary qubit for error correction from among the plurality of qubits in each of the logical qubits.

[0232] (Note 3) The information processing program according to Note 1 or 2, characterized in that each of the logical qubits is a logical qubit in which a plurality of qubits, including a plurality of data qubits and a plurality of auxiliary qubits, are arranged such that the number of auxiliary qubits that entangle is minimized.

[0233] (Note 4) The information processing program according to Note 3, characterized in that each of the logical qubits is a logical qubit in which one or more auxiliary qubits are arranged as nodes in a binary tree-like structure with two or more data qubits arranged on the side connected to the other logical qubit as leaves and one auxiliary qubit that is directly entangled as the root.

[0234] (Note 5) The information processing program according to Note 4, characterized in that each of the logical qubits is a logical qubit in which four data qubits are arranged in a 2x2 matrix, and one auxiliary qubit is arranged which is directly connected to two of the data qubits that are located on the side connected to the other logical qubit.

[0235] (Note 6) The information processing program according to Note 4, characterized in that each of the logical qubits is a logical qubit in which nine data qubits are arranged in a 3x3 matrix, and three auxiliary qubits are arranged as nodes in a binary tree-like structure with three data qubits arranged on the side connected to the other logical qubit as leaves and one auxiliary qubit that is directly entangled as the root.

[0236] (Note 7) In the arrangement of multiple qubits, including multiple data qubits and multiple auxiliary qubits, in each of the two logical qubits to be connected, all of the auxiliary qubits located on the side of the logical qubit that connects to the other logical qubit rather than the data qubit are entangled between the two logical qubits without going through the data qubit, thereby generating the logical bell state of the two logical qubits. An information processing method, wherein a computer executes the processing.

[0237] (Appendix 8) On the arrangement of a plurality of qubits including a plurality of data qubits and a plurality of auxiliary qubits in each of the two target logical qubits to be connected, all of the auxiliary qubits arranged on the side of the logical qubit that connects to the other logical qubit relative to the data qubits are entangled between the two logical qubits without passing through the data qubits, thereby generating a logical Bell state of the two logical qubits. An information processing apparatus comprising a control unit. [Description of Symbols]

[0238] 1 to 8, 10 to 18, 22, 25, 35 to 38 Qubit 100 Information processing apparatus 110 First logical qubit 120 Second logical qubit 200 Bus 201 CPU 202 Memory 203 Network I / F 204 Recording medium I / F 205 Recording medium 206 Arithmetic apparatus I / F 207 Quantum arithmetic apparatus 210 Network 300 Storage unit 301 Acquisition unit 302 Arithmetic unit 303 Operation unit 304 Output unit 410, 420, 1110, 1120, 1710, 1720, 2210, 2220, 2910, 2920, 3110, 3120, 3310, 3320 Logical qubit 500, 800, 1200, 1800, 2300, 3000, 3200, 3400 Quantum circuit 501, 802, 1201, 3001 Quantum state transfer 502, 503, 505, 506, 803~807, 810~812, 1202, 1206, 1207, 1303, 1304, 1306, 1308, 3002~3005 Controlled NOT gates 504, 507, 801, 808, 813, 1203, 1302, 1309, 3006 Adamar Gate 508,809,814,1204,1301,1307,1310 Z measurement 509,1205 Z gate 3007 Logic Z Gate 1801,2301,2302 quantum computation 1900,2000,2100,2600,2700,2800 Table

Claims

1. In the arrangement of multiple qubits, including multiple data qubits and multiple auxiliary qubits, in each of the two logical qubits to be connected, all of the auxiliary qubits located on the side of the logical qubit that connects to the other logical qubit rather than the data qubit are entangled between the two logical qubits without going through the data qubit, thereby generating the logical bell state of the two logical qubits. Let the computer perform the process, The aforementioned generation process is, An information processing program characterized in that, when generating the logical bell state of the two logical qubits, it uses the auxiliary qubit for error correction among the plurality of qubits in each of the logical qubits to perform error correction on the data qubit.

2. The information processing program according to Claim 1, characterized in that each of the logical qubits is a logical qubit in which a plurality of qubits, including a plurality of data qubits and a plurality of auxiliary qubits, are arranged such that the number of auxiliary qubits that entangle is minimized.

3. The information processing program according to claim 2, characterized in that each of the logical qubits is a logical qubit in which one or more auxiliary qubits that form nodes are arranged in a binary tree-like manner, with two or more data qubits arranged on the side connected to the other logical qubit as leaves and one auxiliary qubit that is directly entangled as the root.

4. In the arrangement of a plurality of qubits, including a plurality of data qubits and a plurality of auxiliary qubits, in each of the two logical qubits to be connected, all of the auxiliary qubits, which are located on the side of the logical qubit that connects to the other logical qubit rather than the data qubit, are entangled between the two logical qubits without going through the data qubit, thereby generating a logical bell state of the two logical qubits. The computer performs the process, The aforementioned generation process is, An information processing method characterized in that, when generating the logical bell state of the two logical qubits, error correction of the data qubit is performed by using the auxiliary qubit for error correction from among the plurality of qubits in each of the logical qubits.

5. In the arrangement of a plurality of qubits, including a plurality of data qubits and a plurality of auxiliary qubits, in each of the two logical qubits to be connected, all of the auxiliary qubits, which are located on the side of the logical qubit that connects to the other logical qubit rather than the data qubit, are entangled between the two logical qubits without going through the data qubit, thereby generating a logical bell state of the two logical qubits. It has a control unit, The control unit, An information processing apparatus characterized in that, when generating the logic bell state of the two logic qubits, it uses the auxiliary qubit for error correction among the plurality of qubits in each logic qubit to perform error correction on the data qubit.

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