Gaming machine

Abstract

To provide a game machine capable of executing a more effective performance through improving performance control centered on image display performance.SOLUTION: A game machine is capable of executing a specific performance that outputs reliability suggestion information for suggesting the reliability of the occurrence of a prescribed event, the reliability suggestion information including text information and voice information corresponding to the text information. The specific performance includes: a first specific performance for displaying text information, outputting a voice corresponding to the text information, and executing a speech operation performance corresponding to the voice; and a second specific performance for displaying text information, outputting a voice corresponding to the text information, and not executing a speech operation performance corresponding to the voice. In the first specific performance, an outputting period of the voice falls within a display period of the text information. In the second specific performance, it is possible that an outputting period of the voice fails to fall within a display period of the text information.SELECTED DRAWING: Figure 85

Description

Technical Field

[0001] The present invention relates to a gaming machine such as a pachinko machine.

Background Art

[0002] Gaming machines such as pachinko machines are capable of executing various performances centered on image display on image display means such as liquid crystal display means in accordance with the game state.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of Invention

Problem to be Solved by the Invention

[0004] In this type of gaming machine, not only arbitrary animations and other images are displayed on the image display means, but also LED light emission and audio output are combined therewith to enhance the performance effect and diversify the performances. However, it is considered that there is still room for improvement aiming at further enhancement of the performance effect, for the image display performance itself, or for the combination with other performance means. The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of executing more effective performances by improving performance control centered on image display performances.

Means for Solving the Problem

[0005] The present invention is capable of executing a specific performance that outputs reliability suggestion information suggesting the reliability related to the appearance of a predetermined event, the reliability suggestion information having character information and audio information corresponding to the character information, wherein the specific performance displays the character information, executes output of audio corresponding to the character information, and performs a speech motion corresponding to the audio Show imageA first specific performance, which displays the text information, outputs audio corresponding to the text information, and performs a speech action corresponding to the audio. Show image The first specific performance includes a second specific performance which does not include the first specific performance which does not include the audio output period which does not include the text information display period which does not include the second specific performance first specific performance which does not include the audio output period which does not include the text information display period which does not include the second specific performance which does not include the second specific performance which does not include the second specific performance which does not include the second specific performance which does not include the second specific performance which does not include the second specific performance which does not include the audio output period which does not include the text information display period A first pattern in which the audio output period does not extend beyond the display period of the text information, The audio output period extends beyond the display period of the text information. The second pattern, and, Possible The reliability is configured to be different between the first pattern and the second pattern. That is what happened. [Effects of the Invention]

[0006] According to the present invention, the control of effects, particularly those related to image display effects, is improved, making it possible to execute more effective effects. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing a pachinko machine according to the first embodiment. [Figure 2] Figure 1 is a front view showing the game area of ​​the gaming machine. [Figure 3] This is a block diagram showing the overall circuit configuration of the gaming machine in Figure 1. [Figure 4] This diagram illustrates the internal configuration of the performance interface board, the performance control board, and the liquid crystal interface board. [Figure 5] This is a circuit block diagram illustrating a composite chip, including its related circuit elements. [Figure 6] This is a diagram illustrating the index space and the virtual drawing space. [Figure 7] This is a diagram illustrating the display circuit. [Figure 8] This is a diagram illustrating the internal configuration of a data transfer circuit. [Figure 9] This diagram illustrates the transfer operation of display lists and voice command lists. [Figure 10] This is a diagram illustrating filtering based on a display list. [Figure 11] This is a diagram illustrating the playback procedure for IPB streamed video. [Figure 12] This is a drawing for explaining the internal configuration of a sound processing unit and the control procedure. [Figure 13] This is a drawing for explaining drawing pipeline processing of a drawing circuit. [Figure 14] This is a process diagram for explaining various drawing modes that use all or part of the drawing pipeline process. [Figure 15] This is a flowchart for explaining the control operation of a performance control CPU that does not include a preload operation. [Figure 16] This is a flowchart for explaining a part of Figure 15. [Figure 17] This is a flowchart for explaining the control operation of a performance control CPU that includes a preload operation. [Figure 18] This is a diagram showing an example of performance display by a display device. [Figure 19] This is an explanatory diagram showing variation of mini symbols. [Figure 20] This is a diagram showing the types of advance notice performances and the setting contents of the big win reliability. [Figure 21] This is a diagram showing the overall configuration of a step-up advance notice performance. [Figure 22] This is a diagram showing the types of the third latter-half performance and the fifth latter-half performance of the step-up advance notice performance. [Figure 23] This is a diagram showing an overview of a specific example of the step-up advance notice performance. [Figure 24] Among the specific examples of the step-up advance notice performance, this is a diagram (Part 1) showing details of image changes in the period from the start point of the high-brightness performance WO11 to the end of the high-brightness performance WO12 and the transition to the variation screen of decorative symbols. [Figure 25] Among the specific examples of the step-up advance notice performance, this is a diagram (Part 2) showing details of image changes in the period from the start point of the high-brightness performance WO11 to the end of the high-brightness performance WO12 and the transition to the variation screen of decorative symbols. [Figure 26]This is a diagram (Part 3) showing details of image changes in the period from the start point of high-luminance performance WO11 to the end of high-luminance performance WO12 and the transition to the decorative symbol variation screen, among the specific examples of the step-up announcement performance. [Figure 27] This is a diagram showing the types of performance modes of the reach announcement performance. [Figure 28] This is a diagram showing an outline of a specific example of the reach announcement performance. [Figure 29] This is a diagram (Part 1) showing details of image changes in the period from the start point of high-luminance performance WO21 to the transition to the decorative symbol variation screen, among the specific examples of the reach announcement performance. [Figure 30] This is a diagram (Part 2) showing details of image changes in the period from the start point of high-luminance performance WO21 to the transition to the decorative symbol variation screen, among the specific examples of the reach announcement performance. [Figure 31] This is a diagram (Part 3) showing details of image changes in the period from the start point of high-luminance performance WO21 to the transition to the decorative symbol variation screen, among the specific examples of the reach announcement performance. [Figure 32] This is a diagram showing an outline of a specific example of the button announcement performance 1. [Figure 33] This is a diagram showing details of image changes in the button introduction performance BA0, among the specific examples of the button announcement performance 1. [Figure 34] This is a diagram showing details of image changes in the high-luminance performance WO31, among the specific examples of the button announcement performance 1. [Figure 35] This is a diagram showing details of image changes from the high-luminance performance WO32 to the high-luminance performance WO33, among the specific examples of the button announcement performance 1. [Figure 36] This is a diagram showing the types and contents of the dialogue announcement performance 1, dialogue contents and display colors, and character types. [Figure 37] This is a diagram showing an outline of a specific example of the dialogue announcement performance 1. [Figure 38] This is a diagram (Part 1) showing details of image changes in the period from the start point of high-luminance performance WO41 to the end point of high-luminance performance WO42, among the specific examples of the dialogue announcement performance 1. [Figure 39] This is a diagram (part 2) showing details of image changes in the period from the start point of the high-brightness performance WO41 to the end point of the high-brightness performance WO42, among the specific examples of the dialogue preview performance 1. [Figure 40] This is a diagram (part 3) showing details of image changes in the period from the start point of the high-brightness performance WO41 to the end point of the high-brightness performance WO42, among the specific examples of the dialogue preview performance 1. [Figure 41] This is a diagram showing an outline of a specific example of the pseudo-continuous preview performance. [Figure 42] This is a diagram showing details of image changes in the period from the first pseudo-continuous first-half performance PF1A through the high-brightness performance WO51 to the start of the first pseudo-continuous second-half performance PF1B, among the specific examples of the pseudo-continuous preview performance. [Figure 43] This is a diagram showing details of image changes in the period from the second pseudo-continuous first-half performance PF2A through the high-brightness performance WO52 to the start of the second pseudo-continuous second-half performance PF2B, among the specific examples of the pseudo-continuous preview performance. [Figure 44] This is a diagram showing an outline of a specific example of the button preview performance 2. [Figure 45] This is a diagram (part 1) showing details of image changes in the button urging performance BB1, among the specific examples of the button preview performance 2. [Figure 46] This is a diagram (part 2) showing details of image changes in the button urging performance BB1, among the specific examples of the button preview performance 2. [Figure 47] This is a diagram (part 3) showing details of image changes in the button urging performance BB1, among the specific examples of the button preview performance 2. [Figure 48] This is a diagram showing types of performance modes of the interrupt preview performance. [Figure 49] This is a diagram showing an outline of a specific example of the interrupt preview performance. [Figure 50] This is a diagram (part 1) showing details of image changes in the period from the start point of the high-brightness performance WO71 to the end point of the high-brightness performance WO73, among the specific examples of the interrupt preview performance. [Figure 51](Fig. 2) is a diagram showing details of image changes in the period from the start point of the high-brightness performance WO71 to the end point of the high-brightness performance WO73, among the specific examples of the interruption announcement performance. [Figure 52] Among the specific examples of the interruption announcement performance, this is a diagram (part 3) showing details of image changes in the period from the start point of the high-brightness performance WO71 to the end point of the high-brightness performance WO73. [Figure 53] This is a diagram showing an outline of a specific example of the dialogue announcement performance 2. [Figure 54] Among the specific examples of the dialogue announcement performance 2, this is a diagram (part 1) showing details of image changes in the period from the character appearance performance SB1 to the dialogue output performance SB3. [Figure 55] Among the specific examples of the dialogue announcement performance 2, this is a diagram (part 2) showing details of image changes in the period from the character appearance performance SB1 to the dialogue output performance SB3. [Figure 56] This is a diagram showing the types of performance modes of the dialogue announcement performance 3. [Figure 57] This is a diagram showing an outline of a specific example of the dialogue announcement performance 3. [Figure 58] Among the specific examples of the dialogue announcement performance 3, this is a diagram (part 1) showing details of image changes in the period from the final stage of the introduction performance SC1, through the dialogue performance SC2, to the symbol variation screen. [Figure 59] Among the specific examples of the dialogue announcement performance 3, this is a diagram (part 2) showing details of image changes in the period from the final stage of the introduction performance SC1, through the dialogue performance SC2, to the symbol variation screen. [Figure 60] This is a diagram showing the types of performance modes of the dialogue announcement performance 4. [Figure 61] This is a diagram showing an outline of a specific example of the dialogue announcement performance 4. [Figure 62] Among the specific examples of the dialogue announcement performance 4, this is a diagram (part 1) showing details of image changes in the period from the final stage of the introduction performance SD1, through the dialogue performance SD2, to the symbol variation screen. [Figure 63]Fig. 2 (Part 2) shows details of image changes in the period from the final stage of the introductory effect SD1, through the dialogue effect SD2, up to the symbol variation screen, among the specific examples of the dialogue advance notification effect 4. [Figure 64] It is a diagram showing types of effect modes of the notification advance announcement effect. [Figure 65] It is a diagram showing an outline of a specific example of the notification advance announcement effect. [Figure 66] Among the specific examples of the notification advance announcement effect, this is a diagram (when executed during the normal game state) showing details of image changes in the period of the notification display effect AN2. [Figure 67] Among the specific examples of the notification advance announcement effect, this is a diagram (when executed during a special game state (such as a high-probability state)) showing details of image changes in the period of the notification display effect AN2. [Figure 68] It is a diagram showing types of level display images of the level-up advance announcement effect. [Figure 69] It is a diagram showing appearance patterns of level display images in the level-up advance announcement effect. [Figure 70] It is a diagram showing an outline of a specific example of the level-up advance announcement effect. [Figure 71] Among the specific examples of the notification advance announcement effect, this is a diagram (Part 1) showing details of image changes in the period from the first level effect LV1 to the third level effect LV3. [Figure 72] Among the specific examples of the notification advance announcement effect, this is a diagram (Part 2) showing details of image changes in the period from the first level effect LV1 to the third level effect LV3. [Figure 73] It is a diagram showing an outline of a specific example of the reliability suggesting effect. [Figure 74] Among the specific examples of the reliability suggesting effect, this is a diagram (Part 1) showing details of image changes in the period from the first character string start effect PR1 to the second dialogue output effect PR4. [Figure 75] Among the specific examples of the reliability suggesting effect, this is a diagram (Part 2) showing details of image changes in the period from the first character string start effect PR1 to the second dialogue output effect PR4. [Figure 76] It is a diagram showing an outline of a specific example of the ready-to-win title display effect. [Figure 77] This is a diagram showing details of image changes in the period from the title display start effect TS1 to the title notification effect TS, among the specific examples of the reach title display effect. [Figure 78] This is a diagram showing an overview of a specific example of the operation effect. [Figure 79] This is a diagram showing details of image changes in the period from the operation display start effect BC1 to the operation promotion effect BC2, among the specific examples of the operation effect. [Figure 80] This is a diagram showing an overview of a specific example of the reach development effect. [Figure 81] This is the first diagram showing details of image changes during the high-brightness effect WOB1 period, among the specific examples of the reach development effect. [Figure 82] This is the second diagram showing details of image changes during the high-brightness effect WOB1 period, among the specific examples of the reach development effect. [Figure 83] This is the third diagram showing details of image changes during the high-brightness effect WOB1 period, among the specific examples of the reach development effect. [Figure 84] This is the first half diagram comparing the time charts of the speech notice effect 3, the speech notice effect 4, and the notification notice effect. [Figure 85] This is the second half diagram comparing the time charts of the speech notice effect 3, the speech notice effect 4, and the notification notice effect. [Figure 86] This is a diagram showing the relationship between the respective appearance rates of the display image corresponding to red and the respective appearance rates of the display image corresponding to gold in the comparison between the speech notice effect 4 and the notification notice effect. [Figure 87] This is a diagram showing the relationship between the respective jackpot reliability of the display image corresponding to gold in the comparison of the speech notice effect 1 and notification notice effect executed before reach, and the speech notice effect 4 and speech notice effect 3 executed after reach. [Figure 88] This is a diagram comparing the variations corresponding to blue and the variations corresponding to red between the pre-reach speech notice effect 1 and the post-reach speech notice effect 4 in the second embodiment. [Figure 89]This figure compares the types of variations that can appear between all pre-announcement effects that can be performed before a reach and all pre-announcement effects that can be performed after a reach in the third embodiment. [Figure 90] This figure shows the number of variations for each reliability color in all possible preview effects in the fourth embodiment. [Figure 91] This is an explanatory diagram showing other examples of high-brightness images. [Best Mode for Carrying Out the Invention]

[0008] The present invention will now be described in detail based on the first embodiment. Figure 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached to the outer frame 1 via hinges 2 that are fixed to the outer frame 1 so as to be openable and closable. A game board 5 is detachably attached to the inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be openable and closable. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the front door member. The inner frame 3 in the state in which the front door member (glass door 6 and front panel 7) is pivotally attached is sometimes referred to as the game frame.

[0009] The outer perimeter of the glass door 6 is illuminated with LED lamps and other decorative lights. Meanwhile, a total of three speakers are positioned at the upper left and right positions and at the bottom of the glass door 6. The two speakers at the top output left and right channel (R and L) audio, respectively, while the lower speaker outputs bass.

[0010] The front panel 7 is fitted with an upper tray 8 for storing game balls to be launched, and the lower part of the inner frame 3 is provided with a lower tray 9 for storing game balls that overflow from the upper tray 8 or are removed, and a launching handle 10. The launching handle 10 is linked to a launching motor, and game balls are launched by a striking hammer that operates according to the rotation angle of the launching handle 10.

[0011] A chance button 11 is provided on the outer surface of the upper tray 8. This chance button 11 is positioned so that it can be operated with the player's left hand, allowing the player to operate the chance button 11 without taking their right hand off the launch handle 10. This chance button 11 is normally inactive, but when the game state becomes a button chance state, its built-in lamp lights up and it becomes operable. The button chance state is a game state that is set up as needed.

[0012] Furthermore, a rotary switch-type volume switch VLSW is located below the chance button 11, allowing the player to adjust the speaker volume in eight steps, from silent (=0) to maximum (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial volume is maintained unless the player operates the volume switch VLSW. In addition, an abnormal alert sound, which notifies the player of an abnormal situation, is emitted at the maximum volume regardless of the initial volume set by the attendant or the player's setting.

[0013] On the right side of the upper tray 8, there is an operation panel 12 for dispensing balls to a card-type ball dispensing machine, which includes a frequency display unit that shows the remaining balance on the card as a three-digit number, a ball dispensing switch that instructs the machine to dispense a predetermined amount of game balls, and a return switch that instructs the machine to return the card when the game is finished.

[0014] As shown in Figure 2, a guide rail 13 consisting of an outer and inner metal rail is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided approximately in the center. Below the central opening HO, a movable performance element (not shown) is concealed, and when a movable pre-announcement performance is performed, the movable performance element rises and becomes exposed, thereby realizing a pre-announcement performance with a predetermined reliability. Here, a pre-announcement performance is a performance that uncertainly notifies the player that a jackpot state advantageous to them is about to be brought about, and the reliability of the pre-announcement performance means the probability that the jackpot state will be brought about.

[0015] In the central opening HO, a display device (image display means) DS configured with a large-sized (for example, 1280 horizontal × 1024 vertical pixels) liquid crystal color display is disposed. The display device DS is composed of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that variably displays specific symbols (decorative symbols 164 to be described later) related to a jackpot state, and also displays background images, various characters and the like in an animated manner. This display device DS has special symbol display portions Da to Dc at the central portion and a normal symbol display portion 19 at the upper right portion. Then, in the special symbol display portions Da to Dc, a ready-to-win performance that makes players expect the arrival of a jackpot state may be executed, and appropriate notice performances and the like are executed in and around the special symbol display portions Da to Dc.

[0016] Meanwhile, in the game area where game balls fall and move, a first symbol starting port 15a, a second symbol starting port 15b, a first big winning port 16a, a second big winning port 16b, normal winning ports 17, and a gate 18 are arranged. Each of these winning ports 15 to 18 has a detection switch inside, and is configured to detect the passage of a game ball.

[0017] Above the first symbol starting port 15a, a performance stage 14 is arranged, which is configured to allow a game ball that has entered from the introduction port IN to move in a seesaw-like or roulette-like manner and then enter the first symbol starting port 15 to win a prize. Then, when a game ball enters the first symbol starting port 15a, the variation operation of the special symbol display portions Da to Dc is configured to start.

[0018] The second symbol starting port 15b is configured to be opened and closed by an electric tulip provided with a pair of left and right opening / closing claws, and when the stopped symbol after variation in the normal symbol display portion 19 displays a winning symbol, the opening / closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0019] The regular symbol display unit 19 displays regular symbols. When a game ball that has passed through the gate 18 is detected, the regular symbols change for a predetermined time, and then stop displaying a stopping symbol determined by a random value for the lottery extracted at the time the game ball passes through the gate 18.

[0020] The first large prize opening 16a is configured with a sliding plate that moves back and forth in the front-rear direction, and the second large prize opening 16b is configured with an opening / closing plate whose lower end is pivotally supported and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a corresponds to the first symbol start opening 15a, and the second large prize opening 16b corresponds to the second symbol start opening 15b.

[0021] In other words, when a game ball enters the first symbol starting opening 15a, the special symbol display section Da to Dc starts moving, and then when the predetermined jackpot symbols are aligned in the special symbol display section Da to Dc, the first jackpot special game (special profit state) begins, and the sliding plate of the first jackpot opening 16a opens forward, making it easier for game balls to enter.

[0022] On the other hand, as a result of the fluctuation operation initiated by a game ball entering the second symbol starting opening 15b, when predetermined jackpot symbols align in the special symbol display sections Da to Dc, a special game (special benefit state) which is a second jackpot is initiated, and the opening and closing plate of the second jackpot entry opening 16b is opened, making it easier for game balls to enter. The game value of the special game (jackpot state, special benefit state) varies depending on the aligning jackpot symbols, but which game value is assigned is predetermined based on the result of a lottery conducted according to the timing of the game ball's entry.

[0023] In a typical jackpot state, the opening and closing plate of the large prize winning slot 16 is opened, and then closes after a predetermined time has elapsed or a predetermined number of game balls (for example, 10) have entered. This operation continues for up to, for example, 15 times, and is controlled to be advantageous to the player. Furthermore, if the stopping symbols after the variation of the special symbol display units Da~Dc are specific symbols among the special symbols (a predetermined start condition is met), the game after the end of the special game (special benefit state) will be in a high probability state (probability variation state), which is a special benefit. This high probability state is an example of a special game state that is more advantageous to the player than the normal game state, and its occurrence is controlled by the special game state generation means. Furthermore, this special game state continues until a predetermined termination condition is met, such as the occurrence of the next special game (special benefit state) or a predetermined number of symbol variations.

[0024] Figure 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the operations described above. Figure 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNT located on the payout control board 25. As shown in Figure 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) along with AC24V, a main control board 21 that is primarily responsible for game control operations, an effects interface board 22 equipped with a digital amplifier 29 for sound effects, etc., an effects control board 23 that uniformly executes lamp effects, sound effects, and image effects based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the effects control board 23 and the display device DS, a payout control board 25 that controls the payout motor M to dispense game balls based on control commands CMD' received from the main control board 21, and a launch control board 26 that launches game balls in response to the player's operation.

[0025] Figure 4 is a slightly more detailed illustration of a part of Figure 3(a), and schematically shows the internal configuration of the performance interface board 22, the performance control board 23, and the liquid crystal interface board 24. As shown in Figures 4 and 3(a), the performance interface board 22, the performance control board 23, and the liquid crystal interface board 24 are directly connected by male and female connectors without the need for wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made more complex and sophisticated, the overall space required for the board can be minimized, and noise immunity can be improved by minimizing the connection lines.

[0026] As shown in Figure 3(a), the control command CMD' output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, both control commands CMD and CMD' are 16 bits long, but they are transmitted in parallel in two separate 8-bit segments.

[0027] The main control board 21 and the payout control board 25 are equipped with computer circuits, including a one-chip microcontroller. The performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as an integrated performance circuit (image generation means) 52 and an internal CPU circuit (image control means) 51. In this specification, these control boards 21, 25, and 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are functionally referred to collectively as the main control unit 21, the performance control unit 23, and the payout control unit 25. The performance control unit 23 and the payout control unit 25 are sub-control units with respect to the main control unit 21.

[0028] Furthermore, this pachinko machine GM is broadly divided into the frame-side member GM1, enclosed by the dashed line in Figure 3(a), and the board-side member GM2, which is fixed to the back of the game board 5. The frame-side member GM1 includes the inner frame 3 to which the glass door 6 and front panel 7 are pivotally attached, and the outer wooden frame 1 outside of it, and is permanently installed in the gaming hall for a long period of time regardless of changes in the machine model. On the other hand, the board-side member GM2 is replaced in response to changes in the machine model, and the new board-side member GM2 is attached to the frame-side member GM1 in place of the original board-side member. Note that everything except the frame-side member GM1 is the board-side member GM2.

[0029] As shown in the dashed box in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are fixed to the appropriate locations on the inner frame 3. On the other hand, the main control board 21 and the performance control board 23 are fixed to the back of the game board 5 together with the display device DS and other circuit boards. The frame-side member GM1 and the game board-side member GM2 are electrically connected by centralized connection connectors C1 to C3 which are located in one place.

[0030] The power supply board 20 generates three types of DC voltages (35V, 12V, and 5V) based on the AC voltage (AC24V) distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the central connection connector C2. The three types of DC voltages (35V, 12V, and 5V), along with the AC voltage (AC24V), are also distributed to the payout control board 25. The DC voltages (35V, 12V, and 5V) distributed to the payout control board 25, along with the backup power supply BAK, are then distributed to the main control board 21 via the central connection connector C1.

[0031] 35V DC is used as the power supply for the ball feeding solenoid and launch solenoid in relation to the launching operation of the game balls, and as the power supply for the electromagnetic solenoid that drives the opening and closing of the electric tulip (variable prize device) and the large prize opening 16. 12V DC is used as the power supply for the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier. Meanwhile, 5V DC is used as the power supply voltage for the one-chip microcontroller on the payout control board 25 and the main control board 21, and as the power supply voltage for the logic elements mounted on each control board. Furthermore, after the 5V DC voltage is reduced in level by the DC / DC converters on the performance interface board 22 and the performance control board 23, the reduced voltages are used as the power supply voltage for various computer circuits (such as the composite chip 50).

[0032] The backup power supply BAK is a DC 5V DC power supply used to retain data in the built-in RAM of the one-chip microcontrollers of the main control unit 21 and the payout control unit 25 after the power supply is cut off, and is implemented, for example, by an electric double-layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double-layer capacitor placed on the backup power supply board 33 is configured to be charged during game operation by the DC voltage of 5V received from the payout control board 25.

[0033] On the other hand, after the power is cut off, the backup power supply BAK retains the data from the built-in RAM of the one-chip microcontrollers of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the game operation that was in place before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with electric double-layer capacitors that can retain the contents of the built-in RAM of each one-chip microcontroller for at least several days.

[0034] In this embodiment, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC voltage AC24V, is generated not by the power supply board 20, but by the power supply monitor unit MNT of the payout control board 25. As shown in Figure 3(b), the power supply monitor unit MNT is configured to include a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light when energized, a phototransistor TR that uses the DC voltage 5V received from the power supply board 20 as its power source and turns ON based on the light emitted by the photodiode D, and an output unit that outputs a high-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransistor TR. The photodiode D and the phototransistor TR constitute a photocoupler PH.

[0035] In the above configuration, after power is turned on, the photocoupler PH quickly turns ON, causing the power abnormality signal ABN to reach a normal level (H). However, if the AC power then drops abnormally for any reason (normally a power outage), the photocoupler PH changes to the OFF state, causing the power abnormality signal ABN to change to an abnormal level (L). This power abnormality signal ABN is transmitted to the one-chip microcontroller on the payout control board 25, and is also transmitted to the one-chip microcontroller on the main control board 21 via the central connection connector C1. Therefore, each one-chip microcontroller that receives an abnormal level power abnormality signal ABN will perform a backup process to store the necessary information in its built-in RAM. As explained earlier, the information in the built-in RAM is maintained by the backup power supply BAK, so the game operation before the power outage can be resumed after power is turned on.

[0036] As shown in Figures 3(a) and 4, the performance interface board 22 is equipped with a reset circuit RST3 and a digital amplifier 29 (AMP), the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as an integrated performance circuit 52 and an internal CPU circuit 51, and the liquid crystal interface board 24 is equipped with a clock circuit 38 (RTC), a performance data memory 39 (SRAM) for storing performance data, and a power supply control circuit SPY.

[0037] In this embodiment, the integrated performance circuit 52 built into the composite chip 50 includes a video display processor (VDP), an audio processor (SND), a motor control unit (MT_CTL), and a lamp control unit (L_CTL). Based on control from the built-in CPU circuit 51, the integrated performance circuit 52 operates intermittently with an operating cycle δ (= 1 / 30 second) to execute image effects using the display device DS, sound effects driving speakers via the digital amplifier 29, motor effects moving props by rotating the performance motors M1 to Mn, and lamp effects flashing LED lamps, etc. In the following description, the built-in CPU circuit 51 may be abbreviated as CPU circuit 51.

[0038] The reset circuit RST3 generates a power reset signal based on the rise in the power supply voltage of 5V received from the power supply circuit 20 when the power is turned on, thereby resetting the internal circuits of the composite chip 50 and other electronic components. As explained earlier, the internal circuits of the composite chip 50 include the video processing unit VDP (Video Display Processor) and the audio processing unit SND (Audio Processor), but the power reset signal is none other than the system reset signal SYS of the composite chip 50, which synchronously resets the CPU circuit 51 and the integrated production circuit 52.

[0039] In this embodiment, during the L assertion period of the system reset signal SYS, all internal circuits are uniformly initialized, and the performance control register RGij of the composite chip 50 is set to a default value. Subsequently, when the system reset signal SYS transitions to the H level, the boot program is started, and the necessary initial setup operations are performed on the performance control register RGij. On the other hand, if the DC voltage of 5V drops (usually when the power is cut off), the system reset signal SYS drops to the L level, and the CPU circuit 51 and the integrated performance circuit 52 of the performance control board 23 enter a stopped state.

[0040] As will be described later, in this embodiment, the system reset signal SYS does not change even when the WDT (Watch Dog Timer) circuit 58 is activated, and even in the abnormal situation where the WDT 58 is activated, not all internal circuits are uniformly initialized. In other words, in this embodiment, a predetermined internal circuit that is arbitrarily selected is configured to be initialized.

[0041] Next, the clock circuit 38 and the performance data memory 39 mounted on the LCD interface board 24 are powered by a secondary battery (not shown), which is appropriately charged by the power supply voltage from the power supply board 20 during gameplay. Therefore, even after the power is cut off, the clock circuit 38 continues to keep time, and the game performance information stored in the performance data memory 39 is permanently retained (non-volatile).

[0042] The clock circuit 38 is configured to output an interrupt signal to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the day, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. In this embodiment, the alarm interrupt IRQ_RTC is used to update the daily game performance information at the end of each business day.

[0043] As shown in Figure 3(a), the main control unit 21 and the payout control board 25 are equipped with reset circuits RST1 and RST2, respectively, and are configured to generate a power reset signal when the power is turned on, thereby resetting each computer circuit. In this embodiment, reset circuits RST1 to RST3 are arranged on the main control unit 21, the payout control unit 25, and the performance interface board 22, respectively, so that, for example, the system reset signal generated by the power supply board 20 is not transmitted between circuit boards. In other words, since there is no wiring cable to transmit the system reset signal, the risk of the computer circuit being abnormally reset due to noise superimposed on the wiring cable is eliminated.

[0044] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21 or 25, each CPU is forcibly reset. In addition, the main control unit 21 is equipped with an initialization switch SW that can be operated by an operator, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW was turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcontrollers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of ​​the built-in RAM of the one-chip microcontrollers of each control unit 21 or 25.

[0045] As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball counting signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, a supply depletion signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

[0046] Furthermore, the main control unit 21 receives switch signals from detection switches built into each of the prize entry slots 16-18 on the game board, while also driving solenoids such as the electric tulips. The solenoids and detection switches are configured to operate with the power supply voltage VB (12V) distributed from the main control unit 21. In addition, the switch signals indicating the entry status into the symbol entry slot 15, etc., are converted into TTL level or CMOS level switch signals by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0047] As explained earlier, the performance interface board 22 receives DC voltages (5V, 12V, 35V) at various levels from the power supply board 20 via the central connection connector C2 (see Figures 3(a) and 4). The DC voltage of 12V is used as the power supply voltage for the digital amplifier 29 and as the driving voltage for LED lamps and the like. The DC voltage of 35V is distributed to the appropriate locations on the game frame and used as the driving voltage for solenoids that move movable parts back and forth.

[0048] Meanwhile, the 5V DC voltage is supplied as the power supply voltage to the circuit elements at various locations on the performance interface board 22, and is also supplied to the DC / DC converter DC to generate 3.3V (see Figure 4). The generated 3.3V DC voltage then becomes the base voltage for the power reset signal (system reset signal) SYS generated by the reset circuit RST3. The 5V DC voltage distributed to the performance interface board 22, along with the 3.3V generated by the DC / DC converter DC, is then distributed to the performance control board 23. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as the power supply voltage to the composite chip 50 and the external ROM 55.

[0049] As shown in Figure 4, the performance control board 23 is equipped with two DC / DC converters, DC1 and DC2, which generate 1.5V and 1.05V respectively based on the 5V DC voltage supplied to them. Here, the 1.05V DC voltage is the power supply voltage for the chip core of the composite chip 50, and the 1.5V DC voltage is the power supply voltage for I / O (input / output) with the VRAM 53 and expansion RAM 54. Therefore, the 1.5V DC voltage is also supplied to the VRAM 53 and expansion RAM 54 as a power supply voltage.

[0050] As shown in Figure 3(a), the performance interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and forwards them to the performance control board 23. More specifically, as shown in Figure 4, the control command CMD and the strobe signal STB are forwarded via the input buffer 40 to the composite chip 50 (CPU circuit 51) of the performance control board 23. Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the performance control CPU 57 obtains the control command CMD based on the interrupt processing program (interrupt handler) that is activated upon receiving the received interrupt signal IRQ_CMD.

[0051] As shown in Figure 4, the input buffer 44 of the performance interface board 22 receives switch signals from the frame relay board 36 for the chance button 11 and the volume switch VLSW, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits a 3-bit length of encoder output indicating the contact position (0-7) of the volume switch VLSW and a 1-bit length indicating the ON / OFF state of the chance button 11 to the CPU circuit 51.

[0052] Furthermore, the performance interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay board 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. In Figure 4, for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43. The input buffer 43a receives the output SN0~SNn of the origin sensor, which determines the current position of the movable performance object (the rotational position of the performance motors M1~Mn), and transmits this to the motor control unit MT_CTL of the performance control board 23.

[0053] The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 forwards the serial signals received from the lamp control unit L_CTL and motor control unit MT_CTL of the performance control board 23 to each driver IC. Specifically, the serial signals are the lamp (motor) drive signal SDATA and the clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock-synchronous manner, executing lamp effects using numerous LED lamps and illuminated lamps, as well as mechanical effects using performance motors M1 to Mn.

[0054] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2. The driver IC on the lamp drive board 37 receives the lamp drive signal SDATA0 for CH0, output by the lamp control unit L_CTL, via the frame relay board 36, synchronized with the clock signal CK0. The series of lamp drive signals SDATA0, transmitted as serial signals, are output from the driver IC to the lamp group CH0 when the operation control signal ENABLE0 output from the CPU circuit 51 (PIO62) changes to an active level, thereby simultaneously updating the lighting state of the lamp group CH0.

[0055] The same applies to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 output by the lamp control unit L_CTL in synchronization with the clock signal CK1. Then, when the operation control signal ENABLE1 output from the CPU circuit 51 (actually PIO62) changes to the active level, the lighting status of the lamp group CH1 is updated simultaneously.

[0056] Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted clock-synchronously from the motor control unit MT_CTL to drive the lamp group CH2, and also receives a motor drive signal transmitted clock-synchronously to drive the performance motor group M1 to Mn, which consists of multiple stepping motors. Since the lamp drive signal and the motor drive signal are serial signals of the same type, a series of composite serial signals SDATA2 are output from the motor control unit MT_CTL in synchronization with the clock signal CK2. The driver IC receives this signal and updates the drive state of the lamp group CH2 and the motor group M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0057] Thus, in this embodiment, for convenience, the motor control unit MT_CTL is responsible for both the motor and lamp effects on the motor lamp drive board 31, and therefore the operation control signal ENABLE2 is also output from the motor control unit MT_CTL. Alternatively, the lamp drive signals SDATA0 and SDATA1 for the lamp drive boards 37 and 30 may also be output from the motor control unit MT_CTL.

[0058] As shown in Figure 4, the data bus and address bus of the CPU circuit 51 of the performance control unit 23 also extend to the clock circuit (Real Time Clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51. When the clock circuit 38 is selected by the chip select signal, the CPU circuit 51 is configured to be able to arbitrarily access the internal register (which has a 4-bit address value).

[0059] Furthermore, the performance data memory 39 is a high-speed accessible memory element, SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus and the lower 16 bits of the data bus of the CPU circuit 51. When the chip is selected, game performance information and other data stored in the SRAM (performance data memory) 39 are accessed by the CPU circuit 51 as appropriate via read / write.

[0060] Furthermore, the liquid crystal interface board 24 is equipped with a power supply control circuit SPY that controls the power supply to the display device DS and the backlight board BL. Specifically, the power supply control circuit SPY controls the start timing of supplying power voltages of 12V and 5V to the display device DS and the backlight board BL using the control signal STBY, and controls the brightness and start timing of the backlight light using the control signal PWM.

[0061] As shown on the right side of Figure 4, the performance control board 23 is equipped with a composite chip 50 that incorporates a CPU circuit 51 and an integrated performance circuit 52, a VRAM 53 that is accessed at high speed by R / W from the CPU circuit 51 and the integrated performance circuit 52, an expanded RAM 54 that can store a large amount of data, and an external ROM 55 that stores CG data and other data nonvolatilously.

[0062] VRAM 53 is capable of high-speed access with a theoretical transfer speed of approximately 102 GB / second and has a storage capacity of approximately 48 MB. VRAM 53 is primarily used for (1) storing reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73 (see Figure 5(a)). It can also be used for (2) storing copies of data from the external ROM 55, and (3) as a work area for the CPU circuit 51.

[0063] The extended RAM 54 can operate at a theoretical transfer speed of approximately 17.0 GB / second and has a storage capacity of approximately 1 GB, allowing it to be used in the same way as the VRAM 53. Specifically, the extended RAM 54 can be used to (1) store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73, (2) store copies of data from the external ROM 55, and (3) be used as a work area for the CPU circuit 51.

[0064] The external ROM 55 in this embodiment is a non-volatile storage device that stores a boot program that starts when the power is turned on, control data including a control program and lamp drive data for the CPU circuit 51 that realizes the control of the effects, CG compressed data for image effects, and audio compressed data for sound effects. The storage capacity of the external ROM 55 is up to about 256 GB, but high-speed access is not possible, so in this embodiment, when the power is turned on, a portion of the data in the external ROM 55 is transferred to the expansion RAM 54. Specifically, the control program and control data that make the CPU circuit 51 function are transferred and copied from the external ROM 55 to the expansion RAM 54 by the boot program stored in the external ROM 55 when the power is turned on.

[0065] Figure 5(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of this embodiment incorporates a CPU circuit 51 that issues a display list DL and an audio command list VC, and an integrated performance circuit 52 that executes image performances based on the display list DL, audio performances based on the audio command list VC, as well as lamp performances and motor performances. The CPU circuit 51 and the integrated performance circuit 52 are connected through a CPU bus section 56 that relays data between them.

[0066] First, let's describe the CPU bus section 56, which is located between the CPU circuit 51 and the integrated production circuit 52. As shown in Figure 5(a), the CPU bus section 56 is connected to the VRAM 53, the expanded RAM 54, and the external ROM 55 via the VRAMIF section 53a, the expanded RAMIF section 54a, and the CG bus IF section 55a. Therefore, in this embodiment, the VRAM 53, the expanded RAM 54, and the external ROM 55 can be accessed not only from the integrated production circuit 52 but also from the CPU circuit 51.

[0067] The VRAMIF unit 53a, the extended RAMIF unit 54a, and the CG bus IF unit 55a are connected to the VRAM 53, the extended RAM 54, and the external ROM 55 via an arbitration circuit ICM (Inter Connect Module) (not shown). The arbitration circuit ICM is located between each functional block of the integrated production circuit 52 and the VRAMIF unit 53a, the extended RAMIF unit 54a, and the CG bus I / F unit 55a, arbitrating the data requests issued by each functional block as appropriate to establish the necessary connection relationships.

[0068] In any case, the CPU circuit 51 in this embodiment can access the VRAM 53, the expanded RAM 54, and the external ROM 55. However, after the CPU circuit 51 transfers and copies the control program and control data from the external ROM 55 to the expanded RAM 54 when the power is turned on, it does not access the external ROM 55 again. That is, after the copy operation, the CPU circuit 51 executes control operations based on the control program and control data copied to the expanded RAM 54.

[0069] The CPU circuit 51 can access various performance control registers RGij via read / write to control the internal operation of the integrated performance circuit 52. The data transfer circuit 70 can also transmit and receive data between the CPU circuit 51 and the integrated performance circuit 52 via the CPU bus 56. Data transmission from the CPU circuit 51 to the integrated performance circuit 52 includes issuing display list DLs and voice command list VCs.

[0070] As shown on the right side of Figure 5(a), the integrated production circuit 52 includes (1) a data transfer circuit 70, (2) a display circuit 71, (3) a preloader 72, (4) a GDEC (Graphic Decoder) circuit 73, (5) a drawing circuit 74, (6) an image filter circuit 75, (7) an index table IDXTBL, (8) a motor control unit MT_CTL, (9) a lamp control unit L_CTL, and (10) an audio processing unit SND. The production control register RGij is used by the CPU circuit 51 to appropriately control the internal circuits of this integrated production circuit 52.

[0071] Therefore, the performance control register RGij is broadly divided into (1) data transfer register, (2) display register, (3) preload register, (4) GDEC register, (5) drawing register, (6) image filter register, (7) index table register, (8) MT_CTL register, (9) L_CTL register, and (10) sound register, corresponding to each of the circuits (1) to (10) mentioned above, and a system control register is provided for overall system control (see Figure 5(b)). Note that the system control register and each of the individual circuit registers (1) to (10) are actually composed of multiple subdivided register groups.

[0072] Based on the above, the CPU circuit 51 will now be described. The CPU circuit 51 is a circuit with performance equivalent to that of a general-purpose one-chip microcontroller, and as shown on the left side of Figure 5(a), it consists of a performance control CPU 57 that comprehensively controls image / sound / lamp / motor effects based on a control program, a watchdog timer (WDT) 58 that forcibly resets the CPU if the program goes into a runaway state, an internal RAM 59 with a memory capacity of about 2 MB used as a working area for the performance control CPU 57, a DMAC (Direct Memory Access Controller) 60 that enables data transfer without going through the performance control CPU 57, a serial input / output port (SIO) 61 with multiple input ports Si and output port So, a parallel input / output port (PIO) 62 with multiple input ports Pi and output port Po, and an operation control register REG in which setting values ​​are set to control the internal configuration of the CPU circuit 51.

[0073] For convenience, this specification uses the term "input / output port," but in the performance control unit 23, the input / output port includes an input port and an output port that operate independently. This also applies to the input / output circuit 64p corresponding to the parallel input / output port 62 and the input / output circuit 63s corresponding to the serial input / output port 63, which will be described below.

[0074] The parallel input / output port (PIO) 62 is connected to an external device (performance interface board 22) via the input / output circuit 64p. The performance control CPU 57 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port 62 via the input / output circuit 64p.

[0075] Similarly, the received control command CMD is supplied to the parallel input / output port 62 via the input / output circuit 64p. The strobe signal STB is supplied to the interrupt terminal of the performance control CPU 57 via the input / output circuit 64p, thereby activating the receive interrupt process. Therefore, based on the receive interrupt process, the performance control CPU 57, having grasped the control command CMD, will then uniformly control the corresponding sound effects, lamp effects, motor effects, and image effects through processes such as performance lottery. The parallel input / output port 62 outputs the operation control signals ENABLE0 to ENABLE1 for the lamp effects via the input / output circuit 64p.

[0076] Furthermore, the serial input / output port (SIO) 61 is configured to send and receive serial signals via the input / output circuit 63s. Therefore, as shown by the dashed line in Figure 5(a), it is also possible to output a clock signal CK that realizes synchronous serial transmission and a drive serial signal SDATA via the input / output circuit 63s internally connected to the serial input / output port SIO 61. However, in this embodiment, the lamp / motor effects are realized using the lamp control unit L_CTL and motor control unit MT_CTL of the integrated effect circuit 52 without using the serial input / output port 61.

[0077] Incidentally, the built-in RAM 59 of the CPU circuit 51 is equipped with a DL buffer BUF that sequentially updates and stores a display list DL, which is a list of instruction commands that identify a frame of the display device DS. Furthermore, this DL buffer BUF is configured by partitioning the area, and a voice command list VC that identifies the content of the sound effects is also sequentially updated and stored there.

[0078] In this embodiment, the instruction commands of the display list DL that define one frame of the display screen include: (1) an index table control system command (first command) relating to the index table IDXTBL that manages the index space; (2) a texture loading system command (first command) such as the LOADTX command for reading image material (texture) from the external ROM 55 and decoding (decompressing / unpacking); (3) a filter execution system command (second command) that specifies the filtering process for the decompressed image data; (4) a drawing system command such as the SPRITE command for placing the decoded (unpacked) image material at a predetermined position in the virtual drawing space; (5) a pipeline system command relating to the drawing pipeline operation; and (6) an overall control system command that defines the overall operation of the integrated production circuit 52. All of these are composed of integer multiples of 32 bits (>0). The display list DL is configured to list an appropriate number of instruction commands and then terminate with a predetermined termination command EODL (32-bit length).

[0079] Furthermore, the audio command list VC, which defines the operation of the audio processing unit SND that executes the audio effects, lists an appropriate number of audio commands and then concludes with a predetermined termination command EOSC (32-bit length). Here, the audio commands are broadly classified into track-related commands that define the operation of the pre-processing unit FT shown in Figure 12(a), master effect-related commands that define the operation of the post-processing unit BK shown in Figure 12(a), and other system-related commands, but all audio commands are composed of integer multiples of 32 bits (>0).

[0080] As will be described later, the drawing pipeline operation of this embodiment is performed using the vertex buffer VB built into the drawing circuit 74, the frame buffer FB and depth / stencil buffer reserved as index space, and consists of an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO. The (5) pipeline command described above functions as a setting command that specifies the specific operation of each process (IA, TL, RS, TX, PS, PX, RO) and the R / W position of the vertex buffer VB.

[0081] Incidentally, while "texture" generally refers to the feel or texture of an object's surface, in this specification, the term "texture" is used as a general term for image data before and after decoding. For example, sprite image data that makes up a still image, frame image data that makes up a single frame of a video, and pasted image data that is applied to drawing primitives such as triangular polygons and quadrilateral polygons are all referred to as textures.

[0082] Then, (2) the texture loading command LOADTX reads the texture from the external ROM 55 and decodes it. (5) The SETTXINDEX command, which is part of the texture sampler process TX included in the pipeline commands, sets the source image data to be a texture. (4) The SPRITE command, part of the drawing commands, then virtually draws the texture in the virtual drawing space shown in Figure 6(c). The contents drawn in the virtual drawing space are output to the display device DS via the frame buffer FB, which will be described later.

[0083] Furthermore, the index space managed by the index table control system command (1) mentioned above refers to a one-dimensional or two-dimensional memory work area (logical address space) used by the integrated performance circuit 52 during drawing operations, etc. This index space is identified as a one-dimensional or two-dimensional logical address space by the index number specified in the instruction command of the display list DL.

[0084] In other words, in this embodiment, an index space is allocated in an appropriate location within the memory accessible as a memory work area (VRAM 53 and extended RAM 54), and this space is identified by an index number. Furthermore, VRAM 53 and extended RAM 54 are divided into virtual work areas (AAC area, page area, and arbitrary area), and an index space is allocated for each (see Figures 6(a) and 6(b)). As a result, the index number is a unique value for each virtual work area, simplifying texture loading commands, filter execution commands, drawing commands, pipeline commands, etc.

[0085] Furthermore, it enables unique operation for each virtual work area (AAC area, page area, and arbitrary area). For example, in the AAC area, the index space is automatically allocated and released as the area for expanding decoded data. Therefore, the index number is not required in the AAC area.

[0086] In terms of specific control operations, virtual work areas (AAC area, page area, arbitrary area) are defined during the initial processing after power-on, and the necessary index space is allocated in the required virtual work area at the required timing thereafter. The allocated index space is then managed by the index table IDXTBL, linked to the index number, thereby enabling subsequent operations based on the index number.

[0087] The following explains the relationship between the virtual work area and the actual work area, which consists of VRAM 53 and extended RAM 54. First, VRAM 53 is divided into a shared area that can be used as both an AAC area and a page area, and other arbitrary areas. Specifically, during the initial processing after power-on, the shared area of ​​VRAM 53 is secured by setting an appropriate starting address and area data size in the corresponding performance control register RGij. Then, the area of ​​VRAM 53 other than the shared area secured automatically becomes an arbitrary area of ​​VRAM 53 (Figure 6(a)).

[0088] The shared area allocated in VRAM53 can be used as an ACC area, which does not require index number management, or as a page area, which requires index space management using index numbers. Therefore, when using the shared area, by specifying that the index space should be allocated in the AAC area with the SETTXINDEX command, and then specifying the size and storage address of the texture (image material) with the LOADTX command, the expanded data of the loaded texture can be automatically expanded into the index space allocated in the ACC area.

[0089] Therefore, in this embodiment, taking the above-mentioned simplicity into consideration, the decoded data for still images and I-stream videos (S-stream videos consisting only of I-pictures, as described later) is expanded into the AAC area of ​​VRAM 53. In other words, in this embodiment, the shared area of ​​VRAM 53 is used exclusively as the AAC area.

[0090] Next, in the initial processing after power-on, the page area of ​​the extended RAM 54 is reserved by setting the starting address and area data size on the extended RAM 54 using the corresponding performance control register RGij, and the remaining area becomes an arbitrary area of ​​the extended RAM 54 (Figure 6(b)). Here, an arbitrary area means an area in the extended RAM 54 and VRAM 53 that is allowed to be used arbitrarily, and not only can an index space be reserved, but other uses are also possible. In this embodiment, a preload area for pre-transferring (preloading) CG data acquired from the external ROM 55 is reserved in the arbitrary area of ​​the extended RAM 54 (see Figure 6(b)), and a preload buffer that stores the rewritten list DL' obtained by the preloader 72 rewriting the display list DL is reserved in the arbitrary area of ​​VRAM 53 (see Figure 6(a)).

[0091] Furthermore, in this embodiment, the control program and control data stored in the external ROM 55 are transferred and copied to an arbitrary area of ​​the extended RAM 54 when the power is turned on (see Figure 6(b)). Of course, instead of the extended RAM 54, all or part of the control program and control data may be transferred and copied to the VRAM 53. Moreover, not limited to the control program and control data, a configuration may also be adopted in which all or part of the CG compressed data and audio compressed data are transferred and copied to RAM 53 and 54.

[0092] In any case, the index space can be appropriately allocated in the (1) ACC area, (2) VRAM page area, (3) VRAM arbitrary area, (4) extended RAM page area, and (5) extended RAM arbitrary area with respect to the extended RAM 54 and VRAM 53. However, in this embodiment, the shared area of ​​VRAM 53 is used exclusively as the AAC area. However, the area allocated as a shared area in VRAM 53 can be used as both a page area and an AAC area, so the explanation below will continue with this in mind.

[0093] When allocating an index space in the page area of ​​VRAM 53, it is necessary to set the index number and space size in the predetermined performance control register RGij for VRAM. Similarly, the index space in the page area of ​​extended RAM 54 is allocated by setting the index number and space size in the predetermined performance control register RGij for extended RAM. In this embodiment, the page area of ​​extended RAM 54 is used for expanding video frames. In the page area, the starting address of the index space is determined appropriately based on internal processing, which eliminates the need to manage the starting address. In other words, in the page area, there is no need to worry about overlap with existing index spaces when allocating an index space.

[0094] On the other hand, when allocating a two-dimensional index space in an arbitrary area of ​​VRAM 53 or an arbitrary area of ​​extended RAM 54, it is necessary to set the index number, the starting address of the index space, and the horizontal and vertical sizes of the index space in the corresponding predetermined performance control register RGij. Note that the vertical size is not required for a one-dimensional index space.

[0095] Thus, when allocating an index space in an arbitrary region, the starting address and size can be precisely set, which has the advantage of allowing for efficient use of memory. Therefore, in this embodiment, the frame buffer FB, which completes the image data for one frame of the display device DS, is allocated as a two-dimensional index space in an arbitrary region of VRAM 53 (see Figure 6(a)). Of course, the frame buffer FB may also be allocated in an arbitrary region of the extended RAM 54.

[0096] The frame buffer FB allocated in an arbitrary area of ​​VRAM53 corresponds to the drawing area of ​​the virtual drawing space that drawing commands such as the SPRITE command target. Figure 6(c) illustrates the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be arbitrarily set within the virtual drawing space, and the frame buffer FB that stores the image data to be output to the display device DS.

[0097] The frame buffer FB receives image data for one display screen frame by the drawing circuit 74, while the display circuit 71 reads out image data for one display screen frame. This frame buffer FB is a double buffer structure composed of a pair of index spaces, consisting of a first buffer with index number N1 and a second buffer with index number N2.

[0098] For the display circuit 71, the first buffer and the second buffer are image data reading areas, and by toggling the index numbers N1 / N2 based on the information embedded in a predetermined display register RGij, the image data from the first buffer and the second buffer is read sequentially at each operation cycle δ.

[0099] On the other hand, for the drawing circuit 74, the first buffer and the second buffer are areas for writing image data, and based on instruction commands on the display list DL, the index numbers N1 / N2 are toggled at each operation cycle δ, thereby alternately writing image data to the first buffer and the second buffer.

[0100] The writing operation of the drawing circuit 74 and the reading operation of the display circuit 71 correspond to each other. Image data written to the first buffer in one operation cycle is read out by the display circuit 71 in the next operation cycle. In the operation cycle in which the image data from the first buffer is read out, the drawing circuit 74 writes image data to the second buffer. Subsequent operations are the same, with the first and second buffers being used alternately as either a "writing area" or a "reading area".

[0101] In this embodiment, as a general workspace other than the frame buffer FB and the space for decompressing compressed data, an index space allocated in an arbitrary area of ​​VRAM 53 or extended RAM 54 is used. These various index spaces can be allocated when needed and released when not needed. When an index space is allocated or released, the contents of the index table IDXTBL, which stores the index space and index number in association, are updated, enabling consistent operation thereafter.

[0102] Having explained the index space and the CPU circuit 51, next we will explain the integrated production circuit 52.

[0103] The integrated production circuit 52 includes: (1) various production control registers RGij, in which setting values ​​defining internal operations are set by the production control CPU 57; (2) a data transfer circuit 70 that performs data transmission and reception between internal and external circuits of the chip; (3) an index table IDXTBL that manages the index space, which is a work area reserved in VRAM 53 and extended RAM 54; (4) a preloader 72 that can perform a preload operation that reads the external ROM 55 prior to drawing operations; and (5) a GDEC circuit (Graphic Decoder) that decodes compressed data for image production read from the external ROM 55. (1) A drawing circuit 74 that combines the decoded still image data and video data as appropriate to generate image data for one frame of the display device DS in the frame buffer FB, (2) a series of display circuits 71 that read the image data from the frame buffer FB generated by the drawing circuit 74, perform appropriate image processing, and output it, (3) an output selection unit 76 that appropriately selects and outputs the output of the series of display circuits 71, (4) an output unit 77 that converts the image data output by the output selection unit 76 into an LVDS signal or the like and outputs it, (5) an audio processing unit SND that executes audio effects based on the audio command list VC, (6) a motor control unit MT_CTL that executes motor effects, and (7) a lamp control unit L_CTL that executes lamp effects (see Figure 5(a)). The audio processing unit SND includes an audio decoder that decodes compressed data for audio effects read from the external ROM 55.

[0104] Motor effects are executed based on the control operations of the effect control CPU 57, specifically based on the setting value of a predetermined effect control register RGij for motor effects and the control data (motor drive data) copied to the extended RAM 54. Lamp effects are executed similarly, based on the control operations of the effect control CPU 57, specifically based on the setting value of a predetermined effect control register RGij for lamp effects and the control data (lamp drive data) copied to the extended RAM 54.

[0105] Figure 5(b) illustrates the relationship between the CPU bus section 56, the CG bus IF section 55a, the extended RAM IF section 54a, and the VRAM IF section 53a, and the performance control register RGij, the external ROM 55, the extended RAM 54, and the VRAM 53. As shown in the figure, the CG compressed data acquired from the external ROM 55 is supplied to the GDEC circuit 73 via the CG bus IF section 55a and the data transfer circuit 70, and the decompressed (decoded) data is expanded into a predetermined index space reserved in the extended RAM 54 or VRAM 53.

[0106] As explained earlier, in this embodiment, an ACC area for decompressing still images is reserved in VRAM 53, and a page area for decompressing video frames is reserved in extended RAM 54. Then, the decoded data of still images and videos is decompressed in a predetermined index space in the ACC area / page area. In addition, the decompressed data of compressed CG data acquired from the external ROM 55 may be transferred to the preload area of ​​extended RAM 54 as preload data.

[0107] Next, the display circuit 71 will be described based on Figure 7. The display circuit 71 is a circuit that reads the image data of the frame buffer FB in synchronization with the dot clock DCK, performs final image processing, and then outputs it. The final image processing includes, for example, scaling processing of the scaler to enlarge / reduce the image to a similar shape, subtle color correction processing, and dithering processing to minimize the quantization error of the entire image. These image processing processes are performed uniformly based on the setting value in the performance control register RGij (display register). The digital RGB signal that has undergone uniform image processing is then output along with the horizontal synchronization signal and the vertical synchronization signal.

[0108] As shown in Figure 7, three display circuits A / B / C are provided to perform the above operations in parallel. However, in this embodiment, since there is only one display device, only the frame buffer FB (=FBa) for display circuit A is reserved. However, if frame buffers FBa to FBc are reserved, it is also possible to drive the other two display devices that can perform independent image effects.

[0109] Next, we will return to Figure 5(a) and explain the data transfer circuit 70. The data transfer circuit 70 is a circuit that performs DMA (Direct Memory Access) data transfer operations between the internal resources of the integrated production circuit 52 and the external storage medium, with the internal resources and external storage medium being the source and destination of the transfer. Figure 8 is a block diagram showing the internal configuration of this data transfer circuit 70 along with the related circuit configurations.

[0110] In this embodiment, the data transfer source for the data transfer circuit 70 includes the CPU address space via the CPU bus 56, the external ROM 55, the extended RAM 54, and the VRAM 53, as well as the CPU register port PORT. On the other hand, the data transfer destination for the data transfer circuit 70 includes the CPU register port PORT, the CPU address space, the extended RAM 54, the VRAM 53, the checksum circuit, the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0111] Here, the CPU address space refers to the memory area accessible by the performance control CPU 57. The CPU register port PORT is a 32-bit register connected to the CPU bus 56, and the performance control CPU 57 can access it arbitrarily as a read / write.

[0112] Furthermore, virtual work areas such as page areas and arbitrary areas are defined in the extended RAM 54 and VRAM 53. Within these virtual work areas, an index space identified by an index number is allocated / deallocated. Therefore, the operation of the data transfer circuit 70 is performed by referring to the index table IDXTBL, which stores the relationship between the index space and the actual address space. The index space allocated in the extended RAM 54 or VRAM 53 can also be set as the data source or data destination of the data transfer circuit 70. Consequently, data from the frame buffer FB allocated in an arbitrary area of ​​VRAM 53 can also be transferred to the extended RAM 54.

[0113] By the way, in the circuit configuration shown in Figure 8, the transfer size that the data transfer circuit 70 can transfer is 32 bits × (01h to 4000_0000h) when passing through data relay units CH0 to CH1, and 32 bits × (01h to 100_0000h) when passing through data relay units CH2 to CH4. In other words, the data transfer circuit 70 in this embodiment can transfer data of any size that is an integer multiple of 32 bits, although there is a predetermined upper limit. Here, h means a hexadecimal number, and the upper limit of the transfer size is specifically 32 × 1,073,741,824 bits when passing through data relay units CH0 to CH1, and 32 × 16,777,216 bits when passing through data relay units CH2 to CH4.

[0114] As shown in Figure 8, the data transfer circuit 70 is configured to receive necessary data from the external ROM 55 via the arbitration circuit ICM, which has router functionality and arbitrates access paths, and to send and receive necessary data with the VRAM 53 and the extended RAM 54. The external ROM 55, VRAM 53, and extended RAM 54 are accessed via the CG bus IF unit 55a, the VRAM IF unit 53a, and the extended RAM IF unit 54a.

[0115] This data transfer circuit 70 consists of a 32-bit x 130-stage CPU data FIFO (First In First Out) circuit connected to a 32-bit CPU register port PORT, and five data relay sections CH0 to CH4. As explained earlier, the CPU register port PORT is configured to be read-only accessible from the performance control CPU 57.

[0116] The data relay section CH0 consists of a 1024-bit x 18-stage CH0 data FIFO circuit and a checksum circuit. Data relay sections CH1 to CH4 each consist of a 1024-bit x 18-stage CH0 data FIFO circuit. Furthermore, data relay sections CH2 to CH4 are unidirectionally connected to the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0117] On the other hand, the CPU data FIFO circuit and the data relay units CH0 to CH1 are configured to communicate bidirectionally. Therefore, a predetermined amount of data set in the data transfer register is transmitted and received from a predetermined source set in the data transfer register to a predetermined destination set in the data transfer register, via the CPU data FIFO circuit or the data relay units CH0 to CH1.

[0118] Regardless of which path (CH0-CH4) is used for data relay, the amount of data to be transferred (data size) must be set in 32-bit units, as described above, and there are also predetermined restrictions on the starting addresses of the source and destination. Specifically, the starting addresses of the source and destination must be set in 8-bit units in the CPU address space, and in 32-bit units in VRAM 53 and extended RAM 54. The source starting address in external ROM 55 is also set in 32-bit units.

[0119] When data is transmitted via the data relay section CH0~CH1, the source and / or destination are the external ROM 55, VRAM 53, or extended RAM 54. When data is transmitted via the CPU data FIFO circuit connected to the CPU register port PORT, the source or destination is the CPU address space. The CPU address space naturally includes the built-in RAM 59.

[0120] The above describes the bidirectional data relay units CH0 to CH1, but the data relay units CH2 to CH4 form a unidirectional communication path. The performance control CPU 57 can transmit the display list DL and the voice command list VC of the DL buffer BUF of the built-in RAM 59 to the data relay units CH2 to CH4 in one direction by writing to the CPU register port PORT in 32-bit units via the CPU bus unit 56.

[0121] Furthermore, the built-in RAM 59 can be selected as the data transfer source, so data can also be transferred via the data relay section CH2~CH4 (without going through the CPU register port PORT) using the DL buffer BUF as the data transfer source and the drawing circuit 74, preloader 72, or audio processing unit SND as the data transfer destination.

[0122] In this case, the starting address of the built-in RAM 59, the source of the data transfer, is defined in 8-bit units, so the lower 7 bits of the starting address of the DL buffer BUF must be zero. Also, regardless of whether or not the data is transferred via the CPU register port PORT, the amount of data to be transferred (data transfer size) must be set in 32-bit units.

[0123] In any case, data relay units CH2, CH3, and CH4 are each unidirectionally connected to the drawing circuit 74, the preloader 72, and the audio processing unit SND, respectively. Therefore, a display list DL of a predetermined data transfer size is transferred to the drawing circuit 74 via data relay unit CH2, and to the preloader 72 via data relay unit CH3. Similarly, an audio command list VC of a predetermined data transfer size is transferred to the audio processing unit SND via data relay unit CH4.

[0124] As described above, in this embodiment, the transfer paths for the display list DL and the voice command list VC are provided as follows: (1) a first path via the CPU register port PORT, and (2) a second path that does not go through the CPU register port PORT. Either of these can be used. This also applies to other data, where there is a first path via the CPU register port PORT and data relay units CH0~CH4, and a second path via only the data relay units CH0~CH4. The first path is used for data transfers in which the performance control CPU 57 is directly involved, and the second path is used for data transfers (DMA operation) in which the performance control CPU 57 is not directly involved.

[0125] Incidentally, as shown in Figure 8, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 are configured to receive data in 1024-bit units. Therefore, when the first path is utilized, once 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data will be transferred to one of the data relay units CH0 to CH4 (hereinafter referred to as the channel data FIFO).

[0126] In other words, if less than 32 stages of data are written to the CPU data FIFO circuit, no data transfer to the channel data FIFO will occur. Only when the 32nd stage of data is written will the 32 stages of accumulated data be transferred to the channel data FIFO, and then further data will be transferred to the destination. On the other hand, since the data transfer size is an arbitrary value that is an integer multiple of 32 bits, it is possible that the data in the CPU data FIFO circuit may end with less than 32 stages of data. However, when the cumulative size of the written data reaches the transfer size set in the data transfer register beforehand, the accumulated data of less than 32 stages will be transferred to the channel data FIFO and further destinations.

[0127] Thus, in this embodiment, the transfer size of the data transfer circuit 70 is an arbitrary value that is an integer multiple of 32 bits, regardless of whether it passes through the first path or the second path. Furthermore, the instruction commands that constitute the display list DL and the voice commands that constitute the voice command list VC are all composed of integer multiples of 32 bits. Therefore, in this embodiment, there are no restrictions on the number of commands in the display list DL or the voice command list VC, allowing for a free list configuration, and there is no need to adjust the total data size by adding dummy commands or the like.

[0128] Figure 9 shows the transfer operation of the display list DL to the drawing circuit 74 via the CPU register port PORT and data relay unit CH2 (Figure 9(a)), the transfer operation of the display list DL from the built-in RAM 59 to the drawing circuit 74 via the data relay unit CH2 (Figure 9(b)), and the transfer operation of the rewritten list DL', which is a modified display list, from the VRAM 53 to the drawing circuit 74 via the data relay unit CH2 (Figure 9(c)).

[0129] Figures 9(d) and 9(e) show the operation of transferring the display list DL to the preloader 72 via the CPU register port PORT and data relay unit CH3, and the operation of transferring the display list DL from the built-in RAM 59 to the preloader 72 via data relay unit CH3.

[0130] Furthermore, Figures 9(f) and 9(g) show the transfer operation of the voice command list VC to the voice processing unit SND via the CPU register port PORT and data relay unit CH4, and the transfer operation of the voice command list VC from the built-in RAM 59 to the voice processing unit SND via data relay unit CH4.

[0131] The CPU circuit 51 starts the operation of the drawing circuit 74, preloader 72, and audio processing unit SND prior to the start of operation of the data transfer circuit 70. The drawing circuit 74 then starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 72 performs the necessary preload operations based on the transferred display list DL. The transferred display list DL is determined by the display list analyzer built into the drawing circuit 74 and preloader 72, and processing is performed according to the type of instruction command. The audio processing unit SND then starts or proceeds with audio effects based on the transferred audio command list VC.

[0132] Furthermore, data in the CPU address space other than the display list DL and voice command list VC can be transmitted via the CPU bus 56, then via the CPU register port PORT, or directly to the data relay units CH0~CH4. The data relay units CH0~CH1 then transfer the transmitted data to a predetermined destination in the VRAM 53 or extended RAM 54 via the arbitration circuit ICM. The reverse transfer operation is similar; the data relay units CH0~CH1, having received data via the arbitration circuit ICM, transfer it either via the CPU register port PORT or directly to a predetermined destination in the CPU address space.

[0133] Next, the preloader 72 will be explained, but whether or not to utilize the preloader 72 is optional. When the display list analyzer interprets the display list DL transferred from the data relay section CH3 of the data transfer circuit 70 and detects a LOADTX command, the preloader 72 pre-transfers (preloads) the CG data on the external ROM 55 that the LOADTX command refers to to the preload area of ​​the extended RAM 54 (see Figure 6(b)).

[0134] Furthermore, the preloader 72 stores a rewrite list DL' in the DL buffer BUF' of VRAM 53 (see Figure 6(a)) in which the reference destination of the CG data for the LOADTX command described above has been rewritten to the address after the transfer. Note that the DL buffer BUF' and the preload area are allocated in advance during the initial processing after the CPU reset.

[0135] The rewrite list DL' is then transferred to the drawing circuit 74 via the arbitration circuit ICM of the data transfer circuit 70 and the data relay unit CH2 when the drawing operation of the drawing circuit 74 begins (see Figure 9(c)). The drawing circuit 74 then performs the drawing operation based on the rewrite list DL'. Therefore, CG data that should normally be obtained from the external ROM 55 based on commands such as LOADTX is quickly obtained from the preload area of ​​the extended RAM 54 as preloaded data that has been pre-read into the preload area. Taking this into consideration, the preloader 72 is activated in a typical equipment configuration.

[0136] In this embodiment, since the preload area is set in the external expansion RAM 54 which has sufficient memory capacity, it is possible to perform multiple preloads, for example, by preloading CG data for multiple frames at once. That is, regarding the operation period of the preloader 72, multiple preloads are realized by appropriately setting the operation period of a series of preload operations, including the pre-reading operation of CG data, within the range of an integer multiple of the operation period δ during the intermittent operation of the integrated production circuit 52.

[0137] However, for convenience, the following description will explain an embodiment without multiple preloads, so the preloader 72 in this embodiment will complete the preload operation for one frame during one operation cycle δ. In this embodiment, the operation cycle δ of the integrated production circuit 52 during intermittent operation is 1 / 30 of a second, which is twice the period of the vertical synchronization signal of the display device DS.

[0138] Next, the drawing circuit 74 sequentially analyzes the instruction command sequences of the display list DL and rewrite list DL' transferred via the data transfer circuit 70, and, in cooperation with the GDEC circuit 73 and the geometry engine, draws an image of one frame of the display device DS onto the frame buffer FB reserved in the VRAM 53.

[0139] As described above, when the preloader 72 is in operation, the CG data referenced in the rewrite list DL' is not the external ROM 55, but the preload area set in the extended RAM 54. Therefore, sequential access to the CG data that occurs during drawing by the drawing circuit 74 can be performed quickly, and even high-resolution videos with rapid movement can be drawn without problems.

[0140] Incidentally, regardless of whether the preloader 72 is activated or not, even if data bit corruption occurs during the transfer of the display list DL or the rewrite list DL', the drawing circuit 74 cannot detect it. Therefore, in this embodiment, a timeout monitoring circuit having a configuration similar to a watchdog timer is provided to detect an abnormality in which memory access is not performed for a certain period of time after the start of operation of the drawing circuit 74.

[0141] In order to detect malfunctions in the drawing circuit 74, this embodiment provides a time setting register (a predetermined register) TO from which a timeout period (malfunction detection period) can be arbitrarily set. The time setting register TO is a type of drawing register, and the operation of the drawing circuit 74 is configured to start based on the setting value of a predetermined drawing register (drawing operation permission / denial register).

[0142] When a predetermined timeout period is set in the time setting register TO, and start information is set in the drawing operation permission register, the drawing circuit 74 starts operating. In response, the timeout monitoring circuit (monitoring means) monitors the memory access cycle (memory access time interval). If no memory access occurs even after the timeout period has elapsed, the abnormal flag in a predetermined drawing register is set to ON and an abnormal interrupt is triggered.

[0143] While it is possible to respond to this abnormal interrupt by activating an interrupt handling program, in this embodiment, the appearance of an abnormal screen is prevented by checking the ON / OFF state of the abnormal flag at each operation cycle δ of the integrated display circuit 52. Specifically, if the abnormal flag is ON, the screen update is skipped for that operation cycle, even if the operation of the drawing circuit 74 has been completed.

[0144] Here, if measures such as activating the WDT58 or resetting the drawing circuit 74 are taken, as in the configurations of Patent Documents 1 and 2, there is a risk that an unnatural screen display may appear. However, in this embodiment, the appearance of abnormal screens is easily prevented with minimal intervention. Furthermore, the monitoring timeout period can be arbitrarily set considering the arrangement of commands such as the LOADTX command in the display list DL and the access time of the external ROM 55, so optimal monitoring operation can be achieved.

[0145] Incidentally, in the above configuration, the memory access cycle was monitored from the start to the end of operation of the drawing circuit 74. However, it is also preferable to adopt a configuration that monitors the operation time of the GDEC circuit 73 from the start to the end of operation, instead of this configuration, or in addition to this configuration. In this case as well, an optimal value considering the data capacity of the texture can be set in the time setting register TO', so optimal monitoring operation can be achieved.

[0146] In the latter configuration, the timeout monitoring circuit starts monitoring each time the GDEC circuit 73 starts decoding the CG compressed data, and ends the monitoring operation for that cycle when decoding is complete. In the case of a timeout, the abnormal flag in a predetermined drawing register is set to ON, triggering an abnormal interrupt, and when an abnormality is detected, the screen update for that operation cycle is skipped, just as in the former configuration. In this embodiment, a flag polling method is used to check the ON / OFF state of the abnormal flag at each operation cycle δ of the integrated presentation circuit 52, but a configuration may also be adopted in which an abnormal interrupt processing program is activated to skip the screen update for the operation cycle in which the problem occurred.

[0147] Next, the image filter circuit 75 functions based on instruction commands (filter execution commands) described in the display list DL, and performs appropriate filtering on textures temporarily stored in VRAM 53 or extended RAM 54. In other words, the image filter circuit 75 in this embodiment does not perform uniform filtering based on the setting value of the performance control register RGij, but rather allows for flexible filtering of necessary image data by arbitrarily describing appropriate instruction commands in the display list DL.

[0148] The content of the filtering process is determined by the selection of the filtering execution command and the setting parameters of the selected command, but the executable filtering processes include (1) FIR (Finite Impulse Response) filtering, (2) downsampling, and (3) linear interpolation. Here, downsampling is a different process from the scaling process in the display circuit 71, which operates based on the setting value in the performance control register RGij (display register).

[0149] In other words, downsampling involves reducing the image only in the vertical direction or only in the horizontal direction, rather than reducing it to a similar shape like scaling. While not particularly limited, downsampling reduces the texture by calculating the average value of the image information of pixels within a predetermined range surrounding the target pixel and applying a decimation process such as moving average processing.

[0150] Figure 10(a) is a diagram illustrating an example of operation in which FIR filtering is performed twice consecutively by a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be filtered should be saved (command processing L20). Subsequently, the LOADTX command retrieves the reference texture from the external ROM 55 indicated by the setting parameters of that command, and saves the decoded image data to the destination index space (command processing L21).

[0151] Then, the SETFTINDEX command sets the index space where the result texture will be saved (command processing L22), and the SETFTSAMP and SETFTCOEF commands set the filter coefficients and other information (command processing L23), and the FTEXECFIR command executes the FIR filter (command processing L24). Note that the SETFTINDEX command distinguishes whether to specify the index space for the reference texture or the index space for the result texture depending on the parameters set in the command.

[0152] As shown in Figure 10(b), the image data expanded into the index space for the reference texture specified by instruction command L20 is then stored in the index space for the result texture specified by instruction command L22 after undergoing the FIR filtering process specified by instruction command L23.

[0153] Next, the SETFTINDEX command is used to set the index space for the reference texture (command processing L25), and the SETTXINDEX command is used to set the index space where the result texture will be saved (command processing L26). Since the filtered image data is designated as the reference texture in instruction command L25, the result texture specified in instruction command L22 will be changed to the reference texture by instruction command L25.

[0154] After that, the necessary filter coefficients are set using the SETFTSAMP and SETFTCOEF commands, and other information is set (command processing L27), and then the necessary FIR filtering is performed using the FTEXECFIR command (command processing L28). The filtered image data is then stored in the index space specified by the instruction command L26, so after activating the SETTXMODE command, the SPRITE command is executed (command processing L29), and the image data that has undergone FIR filtering is drawn into the appropriate rectangular section of the virtual drawing space.

[0155] Figure 10(c) is a diagram illustrating an example of how scaling is performed by a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be scaled should be saved (command processing L30), and then the LOADTX command retrieves the reference texture from the external ROM 55 indicated by the command's setting parameters (command processing L31).

[0156] Next, the SETTXINDEX command is used to set up an index space for storing the auxiliary data necessary for scaling (command processing L32). Here, the auxiliary data is plane information extracted from the reference texture, which is information that characterizes the reference texture. The reason for considering such auxiliary data is that the scaling process in this example includes deformation of dissimilar shapes that are not similar in shape, and appropriate interpolation processing is performed to eliminate the unnaturalness of the deformed image.

[0157] Therefore, in the scaling process of this embodiment, the FTEXECGRD command is written following command L32 to generate auxiliary information (plane information) in the index space defined by command L32 (command processing L33). With the necessary preparations completed with the commands up to this point, the next step is to set the index space to be used as a texture with the SETTXINDEX command (command processing L34), set the necessary information with the SETTXSAMP command, and then execute the scaling process with the SETTXMODE command (command processing L35).

[0158] As a result of the above, the image data after scaling is stored in the index space specified by the instruction command L34. Therefore, after executing the SETTXMODE command, the SPRITE command is executed (command processing L36), and the image data after scaling is drawn into the appropriate rectangular section of the virtual drawing space.

[0159] The image filter circuit 75 has been described above, but the GDEC circuit 73 performs decoding processing on compressed data such as stream video, still images, and alpha values ​​using software processing corresponding to each compression algorithm. In this embodiment, the stream video is divided into S-stream, IP-stream, and IPB-stream, and the frames constituting the stream video are composed of I-pictures, S-pictures, P-pictures, or B-pictures in appropriate combinations.

[0160] An I (Intra-coded) picture refers to an intra-coded screen, meaning image data that is compressed as is, independently of other screens. On the other hand, an S picture is image data that performs predictive coding by referring to the most recent I pictures, and has the advantage of a higher compression ratio than an I picture. The S-stream video in this embodiment is a video that combines these I pictures and S pictures, and by arranging the I pictures according to a certain period, random access and reverse playback starting from the I pictures can be performed, enabling effective image effects. Note that S-stream videos without S pictures are also possible, and S-stream videos without S pictures are substantially the same as I-stream videos.

[0161] Next, P-pictures (Predictive coded) are image data that perform forward predictive coding, predicting the current frame from a frame that has been in the past in time. Predictive coding is performed from an I-picture or P-picture located in the past in time. On the other hand, B-pictures (Bidirectional coded) are image data that perform bidirectional predictive coding, performing both forward prediction and backward prediction, predicting the current frame from a future frame. Predictive coding is performed from an I-picture or P-picture located in the past and future in time.

[0162] Generally, interframe prediction techniques include forward prediction (predicting the current frame from frames in the past), backward prediction (predicting the current frame from future frames), and bidirectional prediction (performing both forward and backward prediction). B-picture performs bidirectional prediction, which can improve prediction accuracy.

[0163] Therefore, in this embodiment, in addition to S-stream videos which combine I-pictures and S-pictures, the system is configured to also play IP-stream videos and IPB-stream videos which appropriately combine I-pictures, P-pictures, and B-pictures. IP-stream videos are composed of a combination of I-pictures and P-pictures, while IPB-stream videos are composed of a combination of I-pictures, P-pictures, and B-pictures.

[0164] As is clear from the above relationship, in S-stream videos containing S-pictures and IPB-stream videos, due to the need for backward predictive coding, it becomes necessary to acquire and decode I-pictures and P-pictures that should be played later in time, prior to acquiring S-pictures and B-pictures.

[0165] Therefore, in this embodiment, a single LOADTX command is configured to identify multiple textures, namely the main frame's CG data and the subframe's CG data. Here, the main frame refers to the CG frame data that should be played back at the current time, and the subframe refers to the CG frame data that should be played back at a different time.

[0166] For example, in S-pictures, predictive coding is performed by referencing the most recent (previous or next) I-picture. Therefore, in S-stream videos where I-pictures and S-pictures are consecutive, the CG data of both the S-picture as the main frame and the I-picture as a subframe may be acquired and decoded with a single LOADTX command.

[0167] Furthermore, since B-picture (Bidirectional coded) performs bidirectional predictive coding, it is necessary that the CG data of past frames and the CG data of future frames be allocated in a decoded state prior to the decoding process of the B-picture. Therefore, in this embodiment, when playing back an IPB stream video, it is necessary to allocate a first reference buffer for storing past frames and a second reference buffer for storing future frames prior to this playback operation. The reference buffer is an index space with sufficient capacity to store the reference image, allocated in an arbitrary area of ​​VRAM 53 or extended RAM 54, and identified by a unique index number.

[0168] Figure 11 is a diagram illustrating the playback procedure for IPB stream video, with the playback operation progressing from the top to the bottom of the page. Figure 11 is divided into six sections horizontally, and from left to right, they show: (1) the LOADTX command on the display list DL, (2) the pictures that make up the IPB stream video, (3) the decoding process of the main frame and subframes, (4) the decoding process of the reference image, (5) the reference buffer where the reference image is stored, and (6) the index space (expansion space) where the decoded image displayed on the screen is stored.

[0169] The downward arrow in column 1 indicates the progression of the operating cycle of the intermittently operating integrated production circuit 52 (GDEC circuit 73), and the downward arrow in column 6 indicates the display order of the images displayed on the display device DS. For convenience, in the following explanation, a group of video frames played back at timings T1 to T7 is referred to as a GOP (Group Of Picture), but the GOP can be changed as appropriate based on the embedded parameters of the LOADTX command on a series of display lists for video playback.

[0170] First, the LOADTX command at timing T1, when the I-picture should be played back, identifies the addresses of the I-picture (I1) as the main frame and the P-picture (P1) as the subframe through its embedded parameters. The index number of the expansion space where the decoded data should be stored is also identified.

[0171] Therefore, the I-picture (I1) acquired based on the LOADTX command at timing T1 is decoded and stored in the first reference buffer, which stores past frames, along with its original expansion space. Also, the P-picture (P1) is acquired based on the LOADTX command at timing T1, and its decoded data is stored as a reference image in the second reference buffer, which stores future frames. The reference image is stored in a compressed state using a special method, although this is not particularly limited.

[0172] Next, the LOADTX command at timing T2 instructs only the B picture (B1) as the main frame. Then, as a bidirectional predictive operation, the image data B1 of the current frame is reconstructed and saved in the unfolded space based on the I picture (I1) in the first reference buffer, the P picture (P1) in the second reference buffer, and the B picture (B1). The same applies to the subsequent LOADTX command at timing T3, where the image data B2 of the current frame is reconstructed and saved in the unfolded space based on the I picture (I1) in the first reference buffer, the P picture (P1) in the second reference buffer, and the B picture (B2).

[0173] Next, in the LOADTX command at timing T4, when the P-picture should be played back, the embedded parameters of the command instruct that the main frame P-picture (P1) should be retrieved from the second reference buffer. The address of the subframe P-picture (P2) is also identified.

[0174] Therefore, at timing T4, the P-picture (P1) in the second reference buffer, which is compressed using a special method, is decompressed and saved in the decompression space. At the same time, the P-picture (P1) is stored in the first reference buffer as a past frame image for subsequent processing. In addition, a future P-picture (P2) is acquired by the LOADTX command at timing T4, and its decoded data is saved in the second reference buffer as a reference image for the future frame.

[0175] The subsequent operations at timings T5 and T6 are substantially the same as those at timings T2 and T3. That is, at timing T5, based on bidirectional prediction, the B3 picture image, which is based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B3), is unfolded into the unfolding space. At timing T6, the B4 picture image, which is based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B4), is unfolded into the unfolding space.

[0176] Next, the LOAD command at timing T7 instructs that the main frame, P picture (P2), be retrieved from the second reference buffer. The address of the subframe, I picture (I2), is also identified. Therefore, at timing T7, P picture (P2) in the second reference buffer is decompressed and saved in the decompression space. Simultaneously, the I picture (I2) is retrieved according to the instructions of the LOADTX command at timing T7, and its decoded data is saved in the second reference buffer as a reference image for future frames.

[0177] At the next timing T9, the system is instructed to retrieve the main frame, I-picture (I2), from the second reference buffer. Therefore, the I-picture (I2) in the second reference buffer is decompressed and saved in the decompression space, and at the same time, the I-picture (I2) is stored in the first reference buffer as a past frame image for subsequent processing. In addition, the LOAD command at timing T9 specifies the address of the subframe, P-picture (P3), so P-picture (P3) is retrieved, and its decoded data is saved in the second reference buffer as a reference image for future frames.

[0178] Figure 12(a) is a block diagram showing the internal configuration of the audio processing unit SND. As shown in the figure, the audio processing unit SND is divided into a pre-processing unit FT, in which 64 processing blocks are arranged to operate in parallel; a post-processing unit BK, which consists of a master effect unit, a master volume unit, an output protection unit, and a serializer; and a mixer MX, which transmits the output of the pre-processing unit FT to the post-processing unit BK.

[0179] As shown in the diagram, the pre-processing unit FT is equipped with 64 decoders that receive compressed audio data (compressed phrase data) from the external memory 55. On the other hand, the post-processing unit BK is configured to output the audio signals SDOUTA to SDOUTD of the four paths A / B / C / D as serial data, along with the clock signal SBCLK and the control signal SLRCLK, via a serializer. The serial data SDOUTA to SDOUTD of the four paths A / B / C / D each contain right data R and left data L on one data line, and depending on whether the control signal SLRCLK is in a high-level period or a low-level period, it is determined whether the serial data SDOUTA at that timing is left data L or right data R.

[0180] Next, regarding the internal operation of the pre-processing unit FT, the phrase data decompressed by the decoder has its volume adjusted appropriately by the primary volume, secondary volume, and pan pot section. Here, the primary and secondary volume controls two levels of volume adjustment, while the pan pot section adjusts the volume ratio between the left and right speakers. The specific operations of the primary volume, secondary volume, and pan pot section are defined by the voice commands listed in the voice command list VC.

[0181] By the way, phrase data is audio data that realizes a single unit of audio production, and includes a whole song of background sound, or a single unit of audio production such as sound effects or shouts. Then, one phrase data is output from the pan pot section of the pre-processing unit FT to 8 paths. As shown in the figure, in this embodiment, 64-track processing blocks (pre-processing unit FT) are arranged to operate in parallel, and at most 64 phrase data can be output to the mixer MX, and the audio data, which is grouped into 8 paths (4 paths A / B / C / D for left and right audio R / L), is transmitted to the post-processing unit BK.

[0182] The pan pot allows you to adjust the volume ratio between the left and right speakers. For example, you can set the pan pot of the first track to output only to the first line of the Mixer MX with the left-to-right volume ratio set to maximum:zero, while setting the pan pot of the second track to output only to the second line of the Mixer MX with the left-to-right volume ratio set to zero:maximum. As a result, for example, the first phrase data, which is the left audio, will be output only to the first line, and the second phrase data, which is the right audio, will be output only to the second line, enabling stereo playback using the left and right speakers of system A.

[0183] Next, regarding the internal operation of the post-processing unit BK, the master effect performs audio filtering, and the master volume makes the final volume determination. The specific details of these operations are defined by the audio commands listed in the audio command list VC. The master volume is used, for example, for silent warnings that instantly silence the volume effect, while the master effect is used, for example, for sound change warnings that drastically alter the sound quality.

[0184] Figure 12(b) illustrates the relationship between the voice command list VC and the voice effects realized by the voice commands listed in the voice command list VC. Here, the START command, which instructs the start of playback of a specific phrase data, the PAUSE command, which instructs the stop of playback of a specific phrase data, the RESUME command, which instructs the resume of playback of a specific phrase data, and the STOP command, which instructs the end of playback of a specific phrase data are shown as examples. The voice command list VC is composed of one or more voice commands, but it must be terminated with a predetermined termination command EOSC.

[0185] First, the voice command list VC1 is instructed to start playback of 64 types of phrase data by voice commands START1 to START64. Therefore, once the decoding process of the 64 types of compressed phrase data is complete, playback of the 64 types of phrase data will begin.

[0186] Next, since the voice command list VC2 contains the voice commands PAUSE1, PAUSE2, and STOP64, playback of phrase data 1, 2, and 64 is paused or stopped. After that, the voice command list VC3 contains the voice commands RESUME1 and RESUME2, so playback of the paused phrase data 1 and 2 is resumed.

[0187] Furthermore, the voice command list VC can be output not only at the start and end of phrase data playback, but also at any necessary timing within the operation cycle δ (= 1 / 30 second) of the integrated production circuit 52. In other words, the display list DL is output every operation cycle δ of the integrated production circuit 52, but the voice command list VC is generally output irregularly.

[0188] Next, the drawing pipeline processing that can be executed in the drawing circuit 74 will be described. Figure 13(a) shows a detailed illustration of the part of the drawing circuit 74 related to the drawing pipeline processing. The display list analyzer sequentially analyzes the instruction commands listed in the display list DL and transfers the instruction commands to the appropriate internal circuits according to their type. In Figure 13(a), instruction commands are specifically referred to as drawing commands, and in the following explanation, instruction commands may also be referred to as drawing commands.

[0189] The internal circuits that receive drawing commands are configured to operate in parallel, and the display list analyzer analyzes the drawing commands listed in the display list DL in the order they are written and forwards them one after another to the corresponding internal circuits (see Figure 13(a)).

[0190] Incidentally, the internal circuitry of the drawing circuit 74 operates asynchronously with respect to the CPU circuit 51 that issues the display list DL and the data transfer circuit 70 that sequentially transfers the configuration data of the display list DL. Generally, the operating speed of the internal circuitry of the drawing circuit 74 is significantly slower than the transfer speed of the configuration data of the display list DL.

[0191] Therefore, the internal circuitry that receives drawing commands is equipped with a waiting queue that stores drawing commands before processing begins. The display list analyzer places a drawing command into the waiting queue only if there is an empty slot in the queue. In other words, the display list analyzer stalls (pauses) the placement operation until the waiting queue becomes free, so there is no risk of losing a drawing command. The numbers indicated in the waiting queue are illustrative examples of the queue's stages.

[0192] As explained earlier, the instruction commands listed in the display list DL include: (1) index table control commands related to the index table IDXTBL that manages the index space; (2) texture loading commands such as the LOADTX command for reading image materials (textures) from the external ROM 55 and decoding (decompressing / unpacking); (3) filter execution commands that specify the filtering process for the decompressed image data; (4) drawing commands such as the SPRITE command for placing the decoded (unpacked) image materials in a predetermined position in the virtual rendering space; and (5) pipeline commands related to the operation of the rendering pipeline.

[0193] As shown in Figure 13(a), the index table control command (1) is transferred to the control circuit of the index table IDXTBL, the texture load command (2) is transferred to the GDEC circuit 73, and the filter execution command (3) is transferred to the image filter circuit 75, where each is processed appropriately. Specifically, the GDEC circuit 73 operates based on the transferred drawing commands (texture load commands) to obtain the necessary textures and expand the decompressed data into the decode space.

[0194] Furthermore, the index table IDXTBL is updated as needed by the operation of the control circuit for the index table IDXTBL. The image filter circuit 75 applies a specified filter to a predetermined reference texture and saves the filter result to a predetermined index space (see Figure 10). In addition, when a predetermined drawing command (high-speed transfer command) is received, the high-speed transfer circuit TRNS operates, enabling high-speed data transmission and reception between VRAM 53 and extended RAM 54. The high-speed transfer circuit TRNS is an internal circuit of the drawing circuit 74 and is a separate circuit from the data transfer circuit 70.

[0195] When using the data transfer circuit 70, the CPU circuit 51 needs to set the type of source medium and the start address of the transfer, the type of destination medium and the start address of the reception, and the transfer size in a predetermined performance control register RGij (data transfer register). However, the high-speed transfer circuit TRNS has the advantage of being able to be activated by an instruction command (transfer execution command) in the display list DL when needed, and moreover, it has the advantage of being able to transfer two-dimensional data at high speed using the index space as the unit. However, in a control program that is functioning on a regular basis, it is not easy from a program configuration standpoint to use the data transfer circuit 70 only when needed.

[0196] As explained earlier, the drawing pipeline operation is performed using the vertex buffer VB built into the drawing circuit 74, the frame buffer FB reserved as an index space, and the depth stencil buffer which manages the front-to-back relationships of polygons and whether or not pixels are displayed. The input assembler process (acquisition process) IA, the geometry engine process TL, the rasterizer process (primitive process) RS, the texture sampler process TX, the texture process PS, the pixel drawing process PX, and the render process (image generation process) RO are configured to be executed as needed.

[0197] In other words, the drawing pipeline process is executed from upstream to downstream, either by going through all processes or some of them, in the order of process IA → process TL (process VB) → process RS → process TX → process PS → process PX → process RO. Each process operates in parallel, but since the completion of drawing commands becomes slower as you move downstream, the number of stages in the waiting queue that accumulates drawing commands for each process is configured so that it does not fall below the number of stages in the waiting queue on the upstream side.

[0198] As illustrated in Figure 13(a), the number of stages in the standby queue corresponds to process IA → process TL → process RS → process TX → process PS → process PX → process RO, with 1 stage → 5 stages → 14 stages → 18 stages → 18 stages → 23 stages. The number of stages in each process is the same as or greater than the number of stages in the upstream standby queue.

[0199] By the way, the pipeline commands explained earlier are setting commands that define the operation of each pipeline process (IA, TL, VB, RS, TX, PS, PX, RO). The acquired pipeline commands are transferred to the parameter setting unit SET, which sets the necessary operating parameters for the required internal circuits, such as the geometry engine.

[0200] In this embodiment, as shown in Figure 13(b), the drawing pipeline consists of processes IA, TL, RS, TX, PS, PX, and RO. First, the input assembler process IA acquires the vertex stream of a three-dimensional 3D drawing object, which is usually defined in local coordinates, stores the information necessary for subsequent processing, and outputs vertex data having predetermined vertex information.

[0201] In this IA process, in addition to the setting commands for IA (pipeline commands), drawing commands such as the DRAW command and DRAWD command are used. The DRAW command specifies the starting address of the memory (external ROM 55 in this embodiment) where a series of vertex streams are stored, and the number of vertices.

[0202] On the other hand, the DRAWD command has a series of vertex streams embedded in it. The specific operation of the DRAW and DRAWD commands is defined by the embedded information of each command and the setting commands for process IA. In the vertex stream, a vertex color (RGBA color information) can be defined for each vertex, but if a vertex color is not defined, a default value is set as the vertex information in the input assembler process IA. Here, RGB means color information of R=Red, B=Blue, G=Green, and A is the alpha value α which indicates opacity and is used in the alpha blending process when compositing overlapping images.

[0203] In the subsequent geometry engine process TL, matrix operations are performed on the vertex data output from the input assembler process IA to transform the vertex coordinates of 3D rendering objects, as well as lighting processing related to light sources. The coordinate transformation process includes view matrix operations to convert local coordinates to view coordinates, and matrix operations for projection transformation (perspective projection).

[0204] Here, the view coordinate system is one in which the viewpoint is the origin and the point at infinity (0,0,-∞) is the point of line of sight. In projection transformation, to achieve perspective corresponding to the placement of the 3D rendering object, the transformation from the view coordinate system to the clip coordinate system is achieved by scaling the shape of the 3D rendering object.

[0205] The specific details of the matrix operations are defined by the setting commands for the TL process (pipeline commands), and the execution of the predetermined geometry matrix operations is instructed by the DRAW command or DRAWD command. Therefore, processes IA and TL can be executed together with a single drawing command (DRAW / DRAWD). However, in either case, the results of the geometry matrix operations performed by the drawing command (DRAW / DRAWD) are saved in the vertex buffer VB.

[0206] Note that the geometry engine process TL is not mandatory. If a vertex stream defined by clip coordinates is obtained from the external ROM 55, that information is stored directly in the vertex buffer VB via the input assembler process IA. Furthermore, the input assembler process IA and geometry engine process TL may be repeated for multiple 3D drawing objects, and the vertex buffer VB is configured to store a maximum of 256 vertices.

[0207] Next, in the rasterizer process RS, primitives are generated and drawn based on the vertex information in the vertex buffer VB. After eliminating unnecessary polygons through transformation from the clip coordinate system to the window coordinate system, clipping, culling, scissoring, etc., pixel data for the 3D drawing object is generated. In other words, the three-dimensional 3D image object is fixed in a predetermined position and orientation in the window coordinate system (world coordinates) corresponding to the virtual drawing space.

[0208] To generate primitives, you can use triangle drawing methods such as triangle lists, triangle strips, or triangle fans, and line drawing methods such as line lists, line strips, or line fans, which can be selected as appropriate.

[0209] In addition, in this rasterizer process (RS), in addition to setting commands for the RS process (pipeline commands) that specifically define the processing content, drawing commands such as DRAW, DRAWD, DRAWI, and SPRITE are used as appropriate.

[0210] Here, the DRAWI command generates and draws primitives based on vertex data obtained from the vertex buffer VB. On the other hand, the DRAW command generates and draws primitives based on a vertex stream obtained from the external ROM 55, while the DRAWD command generates and draws primitives based on a vertex stream embedded in the command.

[0211] Therefore, it is possible to perform the rasterizer process RS without going through the geometry engine process TL. For example, in the case of a two-dimensional 2D drawing object, the geometry engine process TL is not particularly necessary. In either case, each polygon generated through the rasterizer process RS has RGBA color information for each pixel based on the vertex color of each vertex.

[0212] Next, in the texture sampler process TX, the index space to be used as the texture is identified, and the texture coordinates for each pixel are also identified. Then, in the texture process PS, the pixel color obtained in the rasterizer process RS and the texture color are calculated as appropriate.

[0213] In these processes TX and PS, and in the following process PX, in addition to the setting commands (pipeline commands) for each process, the drawing commands DRAW, DRAWD, DRAWI, or SPRITE are used as appropriate. The DRAW, DRAWD, or DRAWI commands apply a texture to the area enclosed by the specified vertices, while the SPRITE command applies a texture to the specified rectangular area.

[0214] Next, in the pixel rendering process PX, the rendering color and background color are combined, tone mapping is performed to adjust the contrast, and inverse tone mapping is performed. In this PX process, pixel data containing predetermined information is input for each pixel from the texture process PS, and data (background color) stored at the rendering position of the pixel is input for each pixel from the frame buffer FB.

[0215] In the final rendering stage (RO), the depth and stencil buffers are referenced, and pixel tests are performed to determine whether or not to display a pixel based on its depth and stencil information. After alpha blending processing for overlapping rendering objects, the completed rendering object is written to the frame buffer FB. Writing to the frame buffer FB is equivalent to drawing into the virtual rendering space shown in Figure 6, and the SPRITE command is usually used for this purpose.

[0216] In addition to the DRAW, DRAWD, DRAWI, and SPRITE commands, the RO rendering process also allows the use of the CLEAR command, which fills the frame buffer (FB) with a single color, and the CLEARZ command, which fills the depth and stencil buffers with a single color. The CLEAR command is used to clear the frame buffer (FB) before the start of the rendering operation, while the CLEARZ command is used when depth information and stencil information are not needed.

[0217] Thus, in this invention, all or part of the series of drawing pipeline processes function, and two-dimensional or three-dimensional drawing objects are successively written to the frame buffer FB, ultimately completing the image data for one frame of the display device.

[0218] Figure 14 is a process diagram showing various rendering modes that utilize all or part of the rendering pipeline process. First, the rendering mode in Figure 14(a) is an operation mode that uses the CLEAR command and CLEARZ command described above, and only the render process RO is functional.

[0219] The sprite drawing mode in Figure 14(b) involves the rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, and render process RO. Note that the rasterizer process RS simply adds an offset value to the X and Y coordinates of the window vertices, and this offset value is related to the paste rectangle area of ​​the SPRITE command.

[0220] In practice, the SETTXINDEX command sets the target index space for the sprite, the LOADTX command retrieves the specified texture and loads it into the index space, and the SPRITE command reserves this loaded texture in its designated location. The information of the loaded texture is then referenced and finally written to the frame buffer FB. Video playback and playback of simple still images are, in principle, achieved using this sprite rendering mode.

[0221] The drawing mode shown in Figure 14(c) is an example of operation that uses the entire drawing pipeline to draw triangles and lines. The only difference between triangle drawing and line drawing is the method of primitive generation; in both cases, primitives are identified and drawn based on the vertex stream of the 3D drawing object supplied to the input assembler process IA.

[0222] Figure 14(d) shows a drawing operation using commands such as DRAW and DRAWD, in which pixel data of the drawing object is generated in the rasterizer process RS without performing coordinate transformation. This operation is typically used when displaying a two-dimensional 2D drawing object on a display screen, where the contour lines can be identified by the vertex stream.

[0223] Figures 14(e) and (f) show the operation modes when accumulating vertex data in the vertex buffer VB, and are divided into (e) when coordinate transformation processing is performed and (f) when coordinate transformation processing is not performed. These operations are performed by the DRAW command and the DRAWD command. Next, Figure 14(g) shows the operation mode that uses the vertex data accumulated in the vertex buffer VB, and is performed by the DRAWI command.

[0224] As described above, the drawing pipeline of this embodiment can be used in various ways, but for example, playback of 2D still images and streaming videos (S-stream, IPB-stream, IP-stream) can be achieved simply by drawing sprites, and as mentioned above, the playback operation is realized in the operating mode shown in Figure 14(b).

[0225] As explained above, the display list analyzer determines the drawing commands in the display list DL and forwards each command to the corresponding processing block in the pipeline process. The forwarded drawing commands are then first placed into the waiting queue of each pipeline process, and the processing corresponding to the drawing commands is executed in the order they were placed.

[0226] However, since the operation of the data transfer circuit 70 that transfers the display list DL is significantly faster than the progress of this rendering pipeline, if, for example, you want to display multiple 3D rendering objects on the screen, and also display other 2D rendering objects, the execution of the SPRITE command in the render process RO will be delayed for a long time.

[0227] In other words, processing the coordinate transformation matrix for 3D drawing objects takes a considerable amount of time, so a large number of SPRITE commands accumulate in the waiting queue, such as in the RO process. However, in this embodiment, as explained earlier, drawing commands are waited to be submitted until the waiting queue is empty (stall state), and furthermore, the number of stages in the waiting queue of the downstream process is the same as or greater than the number of stages in the waiting queue of the upstream process, so the operation of the commands listed in the display list DL is smoothly realized.

[0228] Furthermore, drawing commands that have been migrated from the waiting queue will also be held in a stall state until the necessary start conditions are met, so inconsistent drawing operations such as rewriting the index space will not occur.

[0229] The circuit configuration has been described above, so the control operation by the CPU circuit 51 will be described next. As described earlier, when the power is turned on, prior to the start of the control operation, a reset period occurs in which the system reset signal SYS maintains the L level for a predetermined time.

[0230] In this reset period, first, one or two oscillation circuits that control the operations of the overall effect circuit 52 and the built-in CPU circuit 51 start oscillating, and wait until the oscillation frequency of each system clock stabilizes. Next, the internal circuits of the composite chip 50 are initialized in synchronization with each system clock, and predetermined default values are set in the effect control register RGij and the operation control register REG. Hereinafter, in this specification, this operation is referred to as a hardware reset to distinguish it from a software reset described later.

[0231] When this hardware reset period ends, the effect control CPU 57 of the built-in CPU circuit 51 executes the boot program stored in the external ROM 55, and transfers the control program and control data from the external ROM 55 to the expansion RAM 54. Then, the subsequent effect control CPU 57 continues the control operation based on the control program transferred to the expansion RAM 54.

[0232] The control operations executed by the effect control CPU 57 are as shown in FIG. 15, and include a main process (a) composed of an initial process and a subsequent steady process, a timer interrupt process (b) that is activated every 1 ms, a VBLANK interrupt process (c) that is activated upon receiving the VBLANK signal output from the overall effect circuit 52 at the start timing of the vertical retrace period of the display device DS, and a reception interrupt process (not shown) for receiving the control command CMD. The VBLANK signal is generated every 1 / 60 seconds.

[0233] As shown in Figure 15(b), the timer interrupt processing acquires sensor signals to determine the motor position, etc. (ST20), and starts or progresses the lamp effect or motor effect when necessary (ST21). In this embodiment, the lamp effect is realized by the operation of the effect control CPU 57 and the lamp control unit L_CTL based on the lamp drive data, which is the control data. The motor effect is realized by the operation of the effect control CPU 57 and the motor control unit MT_CTL based on the lamp drive data, which is the control data. Furthermore, in the VBLANK interrupt processing, which is activated by receiving the VBLANK signal, the interrupt counter VCNT is incremented and the processing ends, as shown in Figure 15(c) (ST22).

[0234] First, let's explain the main process in the case where the preloader 72 is not used. As shown in Figure 15(a), the initial setup process (ST1) is executed first, and appropriate setting values ​​are set in the performance control register RGij of the integrated performance circuit 52 and the operation control register REG of the CPU circuit 51.

[0235] The setting process for the performance control register RGij includes allocating appropriate virtual work areas (AAC area, page area, arbitrary area) in VRAM 53 and extended RAM 54 (see Figures 6(a) and 6(b)), and allocating index space essential for game control operations, such as the frame buffer FB. As explained earlier, the frame buffer FB consists of a first buffer with index number N1 and a second buffer with index number N2.

[0236] The starting address of the shared area allocated in VRAM 53 (used as the AAC area in this embodiment) is set in units of 4k bytes (the lower 15 bits are zero), and the area size is allocated in integer multiples of 4k bytes. In addition, the page area allocated in extended RAM 54 is set in units of 32k bytes (the lower 18 bits are zero), and the area size is allocated in integer multiples of 32k bytes.

[0237] Furthermore, the setting value in the operation control register REG includes operation parameters related to the watchdog timer WDT58, which include an operation start instruction and a counter value. In this embodiment, the WDT58 is configured to downcount from an initial value (counter value), and the WDT58 is prevented from starting by reloading the counter value before an underflow occurs where the count value becomes zero.

[0238] On the other hand, if the count value underflows, a WDT reset request is generated, and the WDT58 starts up, resulting in a software reset state. In standard operation, all internal circuits are initialized, and the values ​​of all registers RGij and REG, except for a predetermined register, return to their initial values ​​(default values), and the WDT58 stops operating. The only register whose value is exceptionally maintained is the register indicating the operating status of the WDT.

[0239] However, in this embodiment, operations other than the standard operation described above are also possible, and (1) whether or not to initialize the internal circuit, and (2) whether or not to initialize the system clock circuit if initialization is performed, can be arbitrarily selected by setting a corresponding value in a predetermined operation control register REG during the initial setup process after a hardware reset.Therefore, in this embodiment, based on the setting value in the predetermined operation control register REG, when a software reset occurs, the game operation is resumed from the process of step ST1 without initializing the internal circuit.

[0240] Thus, unlike the configurations in prior art documents 1 and 2, this embodiment has the advantage that even if the WDT58 underflows, it does not enter a hardware reset state, allowing for a quick resumption of gameplay. Furthermore, since the WDT stops operating after a software reset, there is no risk of the software reset operation being repeatedly triggered.

[0241] Once the initial setup process (ST1), which includes the above processes, is completed, the intermittently executed steady-state processes (ST2~ST10) begin. As shown in step ST2 in Figure 15(a), the steady-state process starts when the interrupt counter VCNT becomes VCNT≧2, so the operating period (operating cycle) δ of the steady-state process is 1 / 30 seconds, corresponding to the operating period of the VBLANK signal (1 / 60 seconds).

[0242] Then, in step ST3, after resetting the interrupt counter VCNT, it is determined whether the conditions for starting steady-state operation are met. Specifically, a predetermined display control register RGij, which indicates the operating state of the drawing circuit 74, is accessed via READ, and it is determined at this timing whether the drawing circuit 74 has finished the drawing operation based on the display list DL of the previous operation cycle. In addition, it is determined whether the memory access period of the drawing circuit 74 in the drawing operation of the previous operation cycle has exceeded the timeout period set in the time setting register TO, by checking the ON / OFF state of a predetermined abnormal flag.

[0243] Then, because the memory access of the drawing circuit 74 took an abnormally long time, if the abnormal flag is ON, even if the drawing circuit 74 has finished its drawing operation, it is determined that the conditions for starting operation have not been met, and the process proceeds to the performance command analysis process in step ST9.

[0244] The reason for skipping steps ST4 to ST8 is that, given the unusually long memory access of the drawing circuit 74, there is a possibility that normal image data is not being generated, including bit corruption in the instruction commands, and this is to avoid an unreasonable screen display.

[0245] In the performance command analysis process (ST9), it is determined whether or not a control command CMD has been received from the main control board 21. If a control command CMD has been received, the control command CMD is analyzed and the necessary processing is executed. The necessary processing includes the preparation process for starting a new variation performance based on a control command CMD that instructs the start of a variation performance, and the start of error notification based on a control command CMD that indicates an error has occurred.

[0246] Next, the watchdog timer WDT58 is prevented from starting by reloading the counter value (ST10). As explained earlier, even in the event of an abnormality where the watchdog timer 58 starts, the composite chip 50 in this embodiment enters a software reset state, which is different from a hardware reset. With this, the operation of this cycle is complete, and the process moves to step ST2, waiting for the next VBLANK interrupt.

[0247] The above describes the case when the conditions for starting operation are not met. Normally, after the determination process in step ST3, the display circuit 71 identifies the image data to be read based on the setting value of a predetermined display register RGij and starts the operation of the display circuit (ST4). As explained earlier, the frame buffer FB has a double buffer structure, and the first buffer and the second buffer are controlled by the setting value of a predetermined display register RGij so that they switch in a toggle manner.

[0248] Specifically, the index numbers N1 / N2 of the first or second buffer, which were identified as the "write area" by the display list DL of the previous operation cycle, are set. When this step ST4 is executed, the "write area" of the previous operation cycle becomes the "read area" of the current operation cycle, so the display circuit 71 outputs the image data completed by the drawing circuit 74 in the previous operation cycle to the display device DS. In other words, the processing of step ST4 also includes an instruction to start the read operation of the display circuit 71.

[0249] Once the processing of step ST4, which has the significance described above, is completed, the performance control CPU 57 then completes the display list DL, which identifies the image data that the display circuit 71 should output to the display device DS in the next operation cycle (ST5). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the built-in RAM 59 is reserved in advance, and the display list DL is completed there (see Figure 8).

[0250] The display list DL is, in principle, created each time with its contents changed for each operation cycle, but the beginning area of ​​the display list DL contains a command that defines the index number of the frame buffer FB. As explained earlier, the frame buffer FB is an index space with a double buffer structure where the index numbers are N1 and N2. And, in order to use the double buffer in a toggle manner, each display list DL alternately specifies the frame buffer FB with index number N1 and the frame buffer FB with index number N2, thereby cycling the "write area".

[0251] The performance control CPU 57 then issues the completed display list DL to the integrated performance circuit 52 (ST6). Next, the performance control CPU 57 updates the performance scenario EN, which centrally manages image performance, sound performance, lamp performance, and motor performance (ST7), and if it is the appropriate performance timing, issues the sound command list VC to the sound processing unit SND to start or advance the sound performance (ST8).

[0252] Regarding motor and lamp effects, when the start time for the effect managed by the effect scenario EN is reached, the timer interrupt processing (Figure 15(b)) executes the motor or lamp effect based on the corresponding motor drive data or lamp drive data. The processing of steps ST9 to ST10 following step ST8 is as described above.

[0253] FIG. 16(a) to FIG. 16(b) are flowcharts showing the specific content of the display list DL issuance process (ST6), and FIG. 16(c) is a schematic diagram showing the operation content of the DL issuance process (ST6). As described with reference to FIG. 9, the display list DL issuance process includes a case where the CPU register port PORT is subjected to Write access in 32-bit units (FIG. 9(a)) and a case where the CPU register port PORT is not used (FIG. 9(b)), and each operation content is shown in FIG. 16.

[0254] First, FIG. 16(a) will be described. The effect control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (data transfer channel CH2), and also sets the total size of the transfer data in a predetermined transfer register RGij (ST30).

[0255] Here, the content of the display list DL differs for each operation cycle, and the display list DL is issued after being terminated by a predetermined end command EODL. In the present embodiment, since the instruction commands used for the display list DL, including the end command EODL, are defined as one word or a plurality of words (=N*32 bits), data amount adjustment processing is not required. That is, the total size of the transfer data set in the transfer register RGij is an arbitrary value that is an integer multiple of 32 bits.

[0256] Next, the effect control CPU 57 sets the number of Write times corresponding to the total size of the transfer data in the management counter CN (ST31), starts the operation of the drawing circuit 74 (ST32), and then starts the operation of the data transfer circuit 70 (ST33). Here, the operation start instruction for the drawing circuit 74 and the data transfer circuit 70 is realized by setting processing to the predetermined drawing register RGij and transfer register RGij, respectively.

[0257] Next, the performance control CPU 57, while confirming that the 130-stage CPU data FIFO circuit is not full, writes the configuration data for the display list DL to the CPU register port PORT in 32-bit units (ST35). Then, it continues the writing operation while decrementing the management counter CN (ST36, ST37).

[0258] As explained earlier, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 are configured to receive data in 1024-bit units. Therefore, in principle, when 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data is transferred to the data relay unit CH2. However, when the value set in the transfer register RGij (total size of the data to be transferred) is reached, the accumulated data in the CPU data FIFO circuit at that point is transferred to the data relay unit CH2.

[0259] The above process completes the DL issuance process (ST6) via the CPU register port PORT. Next, Figure 16(b) shows an embodiment in which the data transfer circuit 70 reads the display list from the list buffer (DL buffer BUF) without going through the CPU register port PORT. In this case, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (ST40), and sets the total size of the data to be transferred and the starting address of the list buffer BUF in a predetermined transfer register RGij (ST41).

[0260] Here, regarding the list buffer BUF set in the built-in RAM 59, its starting address must be set in 8-bit units, so as explained earlier, the starting address of the DL buffer BUF has zeros in the lower 7 bits. Note that this address condition applies not only to the starting address of the list buffer BUF that stores the display list DL, but also to the starting address of the list buffer BUF that stores the voice command list VC.

[0261] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST42), and then starts the operation of the data transfer circuit 70 (ST43). These operation instructions are also realized by setting predetermined drawing registers RGij and transfer registers RGij, respectively. Then, the data transfer process starts with these operation instructions, and the data transfer circuit 70 finishes its operation upon completion of the transfer of a predetermined size of data. Therefore, after the processing in step ST43, the performance control CPU 57 can immediately proceed to another process, which is the display list issuance process (ST6).

[0262] In this case as well, when the amount of data to be transferred reaches the value set in the transfer register RGij (total size of the data to be transferred), the data accumulated in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0263] The process of issuing a display list DL has been explained above based on Figures 16(a) and 16(b). However, when issuing a voice command list VC to the voice processing unit SND, the processing content is essentially the same as in Figures 16(a) and 16(b) (see Figures 9(f) and 9(g)).

[0264] In other words, the voice command list VC, which lists the voice commands, is issued after being terminated with a predetermined termination command EOSC. Since each voice command, including the termination command EOSC, is one or more words (=N*32 bits), no data size adjustment processing is required.

[0265] The above describes the case where the preloader 72 is not used. The main processing when the preloader 72 is used is shown in Figure 17(a). The processing content shown in Figure 17(a) is similar to the processing content shown in Figure 15(a).

[0266] However, as shown in Figure 17(a), this differs from the process in Figure 15(a) in that (a) after creating a display list DL for the next operation cycle (ST5), the display list DL is issued to the preloader 72 instead of the drawing circuit 74 (ST60), and (b) although this display list DL is rewritten by the preloader 72 to become a rewritten list DL', the rewritten list DL' from the previous operation cycle is made to be acquired by the drawing circuit 74 prior to the processing in step ST5 (ST41).

[0267] In the process shown in Figure 17(a), the issuance process (ST60) that issues the display list DL to the preloader 72 is almost the same as in Figures 16(a) and 16(b), except that the destination is the preloader 72. The general operation is as shown in Figures 9(d) and 9(e), where the data relay unit CH2 changes to the data relay unit CH3 (data transfer channel CH3) in response to the change in the destination to the preloader 72, but otherwise it is the same as the operation in Figures 16(a) and 16(b), and the corresponding operations are shown in Figures 17(b) and 17(c).

[0268] On the other hand, the process of causing the drawing circuit 74 to acquire the rewrite list DL' (ST41 in Figure 17) is shown in Figure 17(d). As shown in Figure 9(c), in this embodiment, the rewrite list DL' is stored in the preload buffer of the VRAM 53 (see Figure 6(a)).

[0269] In step ST41 of Figure 17, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (transfer channel CH2) (ST50 in Figure 17(d)). Next, it sets the total size of the rewrite list DL', which is the transfer data, and the starting address of the preload buffer in which the rewrite list DL' is stored to a predetermined transfer register RGij (ST51).

[0270] Since the starting address in VRAM53 must be set in 32-bit units, the starting address of the preload buffer that stores the rewrite list DL' must have its lower 31 bits be zero. In this embodiment, the preload buffer is allocated at a position that satisfies this condition.

[0271] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST52) and the data transfer circuit 70 (ST53). These operation instructions are implemented by setting predetermined drawing registers RGij and transfer registers RGij, respectively. Then, the data transfer process starts with these operation instructions, and upon completion of the data transfer, the data transfer circuit 70 terminates its operation.

[0272] Next, we will explain the effects, which primarily involve displaying images on the display device DS. The effects used in these effects include the display device DS, as well as light-emitting means (illuminated lamps) such as frame-side LED lamps (i.e., on the glass door 6 and front panel 7 side) and board-side LED lamps (i.e., on the game board 5 side), sound output means such as speakers, and movable effects units. These are controlled by the effects control board (effect execution means) 23, thereby executing various effects.

[0273] The display device DS displays various performance images, notification images, etc., and as shown in Figure 18, it consists of a decorative pattern display means 161, a mini pattern display means 162, a hold image display means 163, etc. The decorative pattern display means 161 can display decorative patterns 164, and the mini pattern display means 162 can display mini patterns 165, respectively. In addition, the hold image display means 163 can display various images such as the first and second hold images X1~X4, Y1~Y4, which indicate the number of first and second special hold items.

[0274] The decorative pattern display means 161 is configured to display decorative patterns 164 in a variable manner using the display device DS based on the entry of game balls into the first and second pattern start openings 15a and 15b (fulfillment of predetermined pattern start conditions). The decorative patterns 164 include a left decorative pattern (first decorative pattern) 164a, which is displayed in a variable manner by the special pattern display unit Da (see Figure 2), a right decorative pattern (second decorative pattern) 164b, which is displayed in a variable manner by the special pattern display unit Dc (see Figure 2), and a middle decorative pattern (third decorative pattern) 164c, which is displayed in a variable manner by the special pattern display unit Db (see Figure 2). Each of the decorative patterns 164a to 164c is composed of a pattern row in which multiple patterns are arranged endlessly. Furthermore, each decorative design 164a to 164c has a main body (number section) 166 consisting of numbers such as "1" to "8" and other elements, and a character or other decorative section 167 attached to the main body 166. It is possible to change between multiple display modes, including a non-decorative display mode in which the main body 166 is displayed and the decorative section 167 is not displayed, and a decorative display mode in which both the main body 166 and the decorative section 167 are displayed. It is also possible to enlarge, reduce, and change the display position.

[0275] When a game ball enters the first and second symbol start openings 15a and 15b (when the symbol start condition is met), the decorative symbols 164a to 164c will change and be displayed for a predetermined time according to a predetermined variation pattern. If the jackpot judgment random value included in the first special random number information (random number information) acquired when a game ball enters the first symbol start opening 15a matches a predetermined jackpot judgment value, the symbols will stop in a jackpot performance mode; otherwise, they will stop in a loss performance mode. Similarly, when a game ball enters the second symbol start opening 15b, if the jackpot judgment random value included in the second special random number information (random number information) acquired when a game ball enters the second symbol start opening 15b matches a predetermined jackpot judgment value, the symbols will stop in a jackpot performance mode; otherwise, they will stop in a loss performance mode. In decorative patterns 164a to 164c, combinations where all symbols are the same (predetermined combinations), such as "2-2-2" and "7-7-7", result in a jackpot animation, while all other combinations result in a loss animation.

[0276] In the symbol variation based on the entry of a game ball into the first symbol start opening 15a, if the decorative symbols 164a to 164c result in a jackpot presentation, a special game for the first jackpot is started, and the sliding plate of the first large prize opening 16a is opened. Also, in the symbol variation based on the entry of a game ball into the second symbol start opening 15b, if the decorative symbols 164a to 164c result in a jackpot presentation, a special game for the second jackpot is started, and the opening / closing plate of the second large prize opening 16b is opened. The decorative symbol display means 161 is not limited to arranging the decorative symbols 164a to 164c in the left-right direction and varying them by vertical scrolling, etc., but may also, for example, arrange the decorative symbols 164a to 164c in the up-down direction and vary them by horizontal scrolling, etc.

[0277] The variation patterns of the decorative symbols 164 begin with a normal variation in which each row of symbols 164a to 164c changes. If a reach state such as "2·↓·2" or "7·↓·7" is established during this normal variation, the machine is configured to proceed through one or more stages of reach effects (N reach, S reach, SP reach, etc.) before finally stopping. A reach variation pattern is when the normal variation develops into a reach effect and results in either a jackpot or a loss effect, while a normal variation pattern is when the normal variation does not develop into a reach effect and results in a loss effect.

[0278] The mini-symbol display means 162 is configured to display the mini-symbol 165 in a variable manner via the display device DS in accordance with the variable display of the decorative symbol 164 based on the entry of game balls into the first and second symbol start openings 15a and 15b. The decorative symbol 164 is not always displayed during the symbol variation (hereinafter simply referred to as "during symbol variation") from the time the symbol variation starts based on the entry of game balls into the first and second symbol start openings 15a and 15b until the variation stops, and some or all of it may disappear from the screen depending on the content of the performance such as the reach performance. In contrast, the mini-symbol 165 is always displayed on the display device DS during the symbol variation. It should be noted that the mini-symbol 165 may disappear from the screen for a period of time during the symbol variation. Also, the mini-symbol 165 may become difficult or impossible to see for a period of time when a movable performance body (not shown) is moving.

[0279] Miniature pattern 165 shares the same number of pattern rows (three in this case) and types of patterns that make up each pattern row (number patterns "1" to "8" in this case) as decorative pattern 164. However, it only has a main body consisting of numbers such as "1" to "8" and does not have a decorative part. As shown in Figure 18, it is smaller in size than decorative pattern 164 and is displayed near the periphery of the display screen DSa of the display device DS. Furthermore, the display state of miniature pattern 165 is limited to "stopped fluctuation state" and "high-speed fluctuation state". Unlike decorative pattern 164, there are no speed changes during fluctuation (deceleration, frame-by-frame playback, etc.). When the pattern fluctuation starts, it instantly switches from the stopped fluctuation state based on a predetermined starting pattern, or from the previous stopping pattern to a predetermined starting pattern, and then transitions to a high-speed fluctuation state where each pattern row cyclically fluctuates at a predetermined speed. When the pattern fluctuation stops, it switches from the high-speed fluctuation state to the stopped fluctuation state based on a predetermined stopping pattern. Furthermore, the fluctuation speed of the mini symbol 165 in the high-speed fluctuation state is always constant, and as shown in Figure 19, the high-speed fluctuation display of the mini symbol 165 is performed at a speed at which the symbol sequence completes one cycle every N frames in the display device DS that displays video at a predetermined frame rate (60fps, etc.).

[0280] Furthermore, while the reel stops on the decorative symbol 164 and becomes the starting reel for the next spin, the mini symbol 165 always uses a predetermined starting reel. At the start of a spin, it instantly switches from the reel stops of the previous spin to the predetermined starting reel, and then starts a high-speed spin from that starting reel. This is because if the previous spin was a miss or a big win spin, and the reel stops on that spin and the mini symbol 165 starts spinning with that reel still in place, the left and right symbols or all symbols will remain aligned during the high-speed spin, which could lead players to mistakenly believe that they are about to get another reach or a big win. Therefore, the starting reel for the mini symbol 165 needs to be set to a number unrelated to reaches or big wins, such as "1, 3, 5". Note that the reel stops on the mini symbol 165 and is the same as the reel stops on the decorative symbol 164.

[0281] The reserved image display means 163 performs a reserved display effect that displays a reserved image indicating the number of random number information stored in the reserved storage means. Here, if a game ball enters the first and second symbol start openings 15a and 15b during the special reserved period, including during the symbol variation of the decorative symbol display means 161 and during a big win (special game), the first and second special random number information acquired thereby is reserved and stored in the predetermined reserved storage means, up to a predetermined upper limit of reserved number, for example, 4 each. After the special reserved period ends, the reserved storage is consumed and a new symbol variation by the decorative symbol display means 161 begins. The reserved image display means 163 notifies the number of stored first and second special random number information (first and second special reserved number) by the number of reserved images displayed.

[0282] As shown in Figure 18, the display device DS is configured to display first and second reserved images X1~X4, Y1~Y4, etc., indicating the first and second special reserved numbers, superimposed on the front of a predetermined reserved base image 168. The reserved image display means 163 adds one first and second reserved image X1~, Y1~ to the reserved base image 168 when the number of first and second special reserved numbers increases based on game balls entering the first and second symbol start openings 15a, 15b, and shifts the first and second reserved images X1~, Y1~ one by one toward the front of the queue (for example, the right side of the screen) when the number of first and second special reserved numbers decreases based on the start of a new variation of the decorative symbol 164 by the decorative symbol display means 161. The reserved base image 168 is displayed in the periphery or vicinity of the display screen DSa, and in this embodiment, it is displayed horizontally along the lower edge of the display screen DSa.

[0283] Next, we will explain specific examples of effects during the variation of the decorative pattern 164 (there may be periods during which at least a portion of the decorative pattern 164 is not displayed), focusing on the content of image effects by the display device DS, light effects by light-emitting means (decorative lamps) such as frame-side LED lamps and panel-side LED lamps, and sound output effects by sound output means. In the following explanation, regarding the light-emitting means that perform light effects, the frame-side LED lamp will be referred to as "frame-side lamp La," the panel-side LED lamp as "panel-side lamp Lb," and together they will be referred to as "effect lamp L." In the diagrams used in the following explanation, as shown in Figure 18, the panel-side lamp Lb and frame-side lamp La will be represented by a schematic diagram showing the former arranged on the upper side and left and right sides of the display device DS, and the latter arranged on the left and right sides of those. Of course, the arrangement of these panel-side lamp Lb and frame-side lamp La is not limited to this.

[0284] The following will sequentially explain 12 types of pre-announcement effects that are performed during symbol changes: step-up pre-announcement effect, reach pre-announcement effect, button pre-announcement effect 1, dialogue pre-announcement effect 1, pseudo-consecutive pre-announcement effect, button pre-announcement effect 2, dialogue pre-announcement effect 2, dialogue pre-announcement effect 3, dialogue pre-announcement effect 4, notification pre-announcement effect, and level-up pre-announcement effect. These 12 types of pre-announcement effects are selected and performed based on the setting of the jackpot reliability level as shown in Figure 20. Here, "jackpot reliability level" is an example of the reliability level regarding the appearance of a predetermined event, and in this case it refers to the reliability level that the decorative symbol 164 will result in a jackpot effect. After explaining these 12 types of pre-announcement effects, several examples of various effects (hereinafter referred to as partial effects) that can be adopted in part of these various pre-announcement effects, etc. (reliability suggestion effect, reach title display effect, operation effect, reach development effect) will be explained.

[0285] Further, in each of the following performances, a plurality of variations having reliability suggestion information that suggests the jackpot reliability are prepared, and the jackpot reliability and the like differ for each of the plurality of variations. As the reliability suggestion information, there exist various types such as character information and color information of images. In each of the following various performances, when the color information of an image is adopted as the reliability suggestion information, the jackpot reliability increases in the order of "white", "green", "blue", "red", "gold", "danger color", and "rainbow color", but it is not necessary to adopt all of these colors, and it is sufficient to adopt a plurality of colors among them. Further, these pieces of color information suggest the level relationship of the jackpot reliability among the plurality of variations that can appear in one performance, and between different performances, even for variations using the same color information, the jackpot reliability is naturally not necessarily the same.

[0286] Further, the contents described below for each performance are not limited to each performance, and may be adopted in other performances. For example, the configuration of the high-brightness performance appearing in the step-up notice performance may be adopted in other notice performances such as a ready-to-win notice performance and a dialogue notice performance, or partial performances such as a reliability suggestion performance.

[0287] [Step-up Notice Performance] FIG. 21 to FIG. 26 show an example of the step-up notice performance executed during normal variation in a ready-to-win variation pattern or a normal variation pattern. The step-up notice performance (specific notice performance) is a performance that is executed up to a predetermined stage among a plurality of stages (here, 5 stages) of performance steps according to the jackpot reliability, and is set such that the further the stage of the performance step progresses, the higher the jackpot reliability becomes.

[0288] As shown in Figure 21, this step-up announcement performance is configured such that five types of characters corresponding to the 1st to 5th five-stage performance steps, namely an elephant, a lion, a fox, a squirrel, and a bear, each shoot arrows in sequence aiming at a balloon, and the performance steps proceed until an arrow shot by any of the characters hits and bursts the balloon. First, a step-up introduction performance ST0 indicating that the step-up announcement performance is started is executed (Figure 21(a)). In this step-up introduction performance ST0, the five types of characters each aiming at a balloon appear all at once, thereby suggesting the content of the step-up announcement performance. Of course, each character may appear in the order of elephant → lion → fox → squirrel → bear in accordance with the order of the corresponding performance steps, or may appear in any other arbitrary order.

[0289] Following the step-up introduction performance ST0 (Figure 21(a)), a first step performance ST1 is started as the first stage. The first step performance ST1 is composed of a first half performance ST1A and a second half performance ST1B, and the first half performance ST1A is executed first. In this first half performance ST1A, a scene in which the elephant as the first character shoots an arrow is performed (Figure 21(b1)), and when the arrow hits the balloon (Figure 21(d1)), it is determined that the performance step ends at the first stage, and the second half performance ST1B is executed. The second half performances including this first second half performance ST1B will be described later.

[0290] On the other hand, when the arrow shot by the elephant does not hit the balloon (Fig. 21(c1)), the first-half second presentation ST1B is not executed, and subsequently, as the second stage, the first-half second presentation ST2A of the second step presentation ST2 is started. In this first-half second presentation ST2A, a scene in which the lion as the second character shoots an arrow is performed (Fig. 21(b2)), and when the arrow hits the balloon (Fig. 21(d2)), it is determined that the presentation step ends at the second stage, and the second-half second presentation ST2B is performed. In this way, until the arrow shot by any of the characters hits the balloon, the elephant, lion, fox, squirrel, and bear shoot arrows in sequence (Fig. 21(b1) to (b5)), and when the arrow hits the balloon (Fig. 21(d1) to (d5)), it is determined that the presentation step ends at that stage, and the latter-half presentations ST1B to ST5B corresponding to that stage are executed. Note that, since the step-up notice presentation of the present embodiment only has up to the fifth stage, the arrow shot by the bear at least in the first-half fifth presentation ST5A always hits the balloon (Fig. 21(d5)).

[0291] Further, in the step-up notice presentation of the present embodiment, a plurality of types (here, 5 types each) of the first to fifth latter-half presentations ST1B to ST5B are respectively provided, and any one of the plurality of types is selected in accordance with the reliability relating to the appearance of a predetermined event (here, the jackpot reliability).

[0292] Figure 22 exemplifies five modes (variations) for each of the third latter-half performance ST3B and the fifth latter-half performance ST5B among the first to fifth latter-half performances ST1B to ST5B. Of course, similar variations using respective characters are also prepared for the other first, second, and fourth latter-half performances ST1B, ST2B, and ST4B, but they are omitted here. In the first to fifth latter-half performances ST1B to ST5B, a holding base image 168 is displayed on the lower side of the display screen DSa, and a mini symbol 165 is displayed on the upper side of the display screen DSa, respectively. First and second holding images X1 to X4, Y1 to Y4 and the like are displayed on the front side of the holding base image 168, and a step-up preview performance image 169 is displayed on the rear side of the holding base image 168 and the mini symbol 165. However, the configuration may be such that the holding base image 168 is displayed in the first-half performance, and the holding base image 168 is not displayed during the latter-half performance. Thereby, the display area for the latter-half performance for performing display related to the jackpot reliability can be enlarged, and a more impactful display performance can be executed. In the first to fifth latter-half performances ST1B to ST5B, the decorative symbols 164 during variation are hidden.

[0293] The five types of third latter-half performances ST3Ba to ST3Be shown in Figures 22(a1) to (e1) are common in that the fox, which is the character of the third step performance ST3, appears with respect to the step-up preview performance image 169, and in the basic screen layout centered on the fox and a predetermined character image, but the content of the displayed character image, the display mode of the character image (here, the display color), the display color (base color) of at least a part of the step-up preview performance image 169, and the like are different.

[0294] That is, in the step-up preview effect images 169 of the third latter-half effects ST3Ba to ST3Be shown in Figures 22(a1) to (e1), the fox character image is displayed in a large size in a positional relationship that bisects the background image into a left background image and a right background image, and a character image made up of a predetermined speech character string (which may consist of only a single character) is displayed horizontally in front of and straddling the character image (fox) and its background image, which is a common feature. On the other hand, the content of the speech character string is different across all five types, and the content of the speech character string corresponding to the third latter-half effects ST3Ba to ST3Be is "Something good is likely to happen", "Alright, let's do our best", "Something even better is likely to happen", "It will surely be alright", and "I'm feeling great" respectively. In addition, the display color (display mode) of the speech character string is also different across all five types, and the display color (internal color of the characters) of the speech character string corresponding to the third latter-half effects ST3Ba to ST3Be is "blue", "red", "gold", "danger color", and "rainbow color" respectively. Here, the "danger color" refers to a striped color scheme using a plurality of colors different from the rainbow color, and in this embodiment, it is a diagonal striped color scheme using three colors: yellow, black, and red.

[0295] Further, regarding the step-up advance notification performance image 169 of the third latter-half performances ST3Ba to ST3Bd (Fig.22(a1) to (d1)) other than the third latter-half performance ST3Be (Fig.22(e1)), the base color corresponds to the display color of the dialogue character string, and each of the colors "blue", "red", "gold", and "danger color" corresponding to the respective character colors "blue", "red", "gold", and "danger color" is used in at least a part (such as the right background image) of the step-up advance notification performance image 169. Here, the "danger color" as the base color is the same as the "danger color" as the character color in that it is composed of three colors of yellow, black, and red, but the striped color scheme uses only yellow and black, and differs from the "danger color" as the character color in that character strings of "DANGER" are continuously arranged in red on the black lines, and it is closer to the actual substance to rephrase it as a "danger pattern". Note that for this "danger pattern", each manufacturer uses its own unique pattern, and the pattern used in the present embodiment is merely an example. Of course, the configuration of the danger color is not limited to this, and it is sufficient that it is different from other character colors / base colors.

[0296] In addition, the five types of fifth latter-half performances ST5Ba to ST5Be shown in Fig.22(a2) to (e2) are common in that the bear, which is the character of the fifth step performance ST5, appears regarding the step-up advance notification performance image 169, and in the basic screen layout centered on the bear and a predetermined character image, but the content of the character image displayed on the screen, the display mode of the character image (here, the display color), the display color (base color) of at least a part of the step-up advance notification performance image 169, and the like are different.

[0297] That is, in the step-up preview performance images 169 of the fifth latter-half performances ST5Ba to ST5Be shown in Figs. 22(a2) to (e2), a bear character image is displayed large in a positional relationship that divides the background image into a left background image and a right background image, and in common, a character image composed of a predetermined speech character string (which may be constituted by only one character) is displayed in horizontal writing on the front side thereof so as to straddle the character image (bear) and its background image. On the other hand, the content of the speech character string is different in all five types, and the content of the speech character string corresponding to the fifth latter-half performances ST5Ba to ST5Be is "Might make it", "Almost there", "Feeling great", "Getting excited", and "Fully satisfied!", respectively. In addition, the display color of the speech character string is also different in all five types, and the display color (internal color of characters) of the speech character string corresponding to the fifth latter-half performances ST5Ba to ST5Be is "blue", "red", "gold", "danger color", and "rainbow color", respectively. As described above, although the content of the speech character strings of the fifth latter-half performances ST5Ba to ST5Be are all different from the content of the speech character strings of the third latter-half performances ST3Ba to ST3Be, at least part of the content of the speech character strings may be shared.

[0298] Further, regarding the step-up preview performance images 169 of the fifth latter-half performances ST5Ba to ST5Bd (Figs. 22(a2) to (d2)) other than the fifth latter-half performance ST5Be (Fig. 22(e2)), the base color of the screen corresponds to the display color of the speech character string, and the respective colors of "blue", "red", "gold", and "danger color" corresponding to the respective character colors of "blue", "red", "gold", and "danger color" are used in at least a part of the screen (such as a part of the background image).

[0299] Here, the jackpot reliability is set to gradually increase from the third latter-half performance ST3Ba to ST3Be, and also from the fifth latter-half performance ST5Ba to ST5Be. That is, the relationship between the display color of the dialogue character string and the jackpot reliability is such that the jackpot reliability rises in the order of "blue", "red", "gold", "danger color", and "rainbow color". Note that "rainbow color" indicates a jackpot reliability of 100%, that is, a confirmed jackpot. As described above, since the third latter-half performances ST3Ba to ST3Be and the fifth latter-half performances ST5Ba to ST5Be have different jackpot reliabilities according to the display color of the dialogue character string or the like, the character image (specific character information) or the step-up notice performance image 169 having the character image can be said to be a specific image having reliability information related to the jackpot. The same applies to the other first, second, and fourth latter-half performances.

[0300] As such, for example, the third latter-half performance ST3Ba (FIG.22(a1)) and the fifth latter-half performance ST5Ba (FIG.22(a2)) are examples of the first-party first reliability specific image corresponding to the first-party first reliability, and the third latter-half performance ST3Bb (FIG.22(b1)) and the fifth latter-half performance ST5Bb (FIG.22(b2)) are examples of the first-party second reliability specific image corresponding to the first-party second reliability. In the present embodiment, the five display colors of "blue", "red", "gold", "danger color", and "rainbow color" adopted in this step-up notice performance form the full lineup of the reliability information related to the jackpot (reliability information related to the occurrence of a predetermined event), and are set so that the jackpot reliability increases in that order. However, in other notice performances and the like, it is not necessary to adopt all of these five display colors as the reliability information, and only a part of them such as "red" and "gold" may be adopted. Even in that case, however, the level relationship of the jackpot reliability (for example, "gold" is higher than "red") shall remain unchanged.

[0301] It should be noted that the base color of the step-up advance notification effect image 169 does not need to be completely identical to the character color, and may be a similar color. Also, for the third latter-half effect ST3Be, the fifth latter-half effect ST5Be, etc., where the character color is "rainbow", the base color of the screen may be made to correspond to the character color by setting at least part of the display colors other than the speech character string to "rainbow". In addition, in the present embodiment, regarding display modes other than the display color related to the speech character string, such as the font (typeface) and size of the speech character string, the five types of third latter-half effects ST3Ba to ST3Be, the fifth latter-half effects ST5Ba to ST5Be, etc. are substantially common, but other display modes (font, etc.) may be varied along with the character color, or the character color may be made substantially the same while other specific display modes (font, etc.) are varied, so that the specific display modes may be used as reliability information.

[0302] Next, a specific example of the step-up advance notification effect will be described by taking as an example a case where the effect steps progress up to the third stage and ST3Bc (FIG. 22(c1)) is selected as the third latter-half effect, and the overview will first be described with reference to FIG. 23. When the step-up advance notification effect is started during normal variation in the reach variation pattern, the speaker starts outputting BGM1 related to this step-up advance notification effect as BGM, and on the display screen DSa, the decorative symbols 164 that are under high-speed variation are hidden, with the reserved pedestal image 168 displayed on the lower end side and the mini symbols 165 displayed on the upper end side respectively, the effect image related to the step-up introduction effect ST0 is displayed behind them (FIG. 23(a)).

[0303] In this step-up introduction performance ST0, a step-up advance notice performance image 169 is displayed in which five types of characters corresponding to the five stages of performance steps, namely an elephant, a lion, a fox, a squirrel, and a bear, are all gathered and each is preparing to shoot an arrow toward a balloon. A player who views this can recognize that this is a step-up advance notice performance in which the performance steps progress until one of the characters pops the balloon. Also, in this step-up introduction performance ST0 (Fig. 23(a)), for example, at the start thereof, a predetermined introduction sound is output as a sound effect from a speaker. Further, during this step-up introduction performance ST0 (Fig. 23(a)), at least a part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) emits light in an introduction light emission mode corresponding to this step-up introduction performance ST0, for example, emitting light in orange. Note that "at least a part of the performance lamp L" may be only one of the frame-side lamp La and the board-side lamp Lb, may be both, or may be at least a part of a portion of the frame-side lamp La and a portion of the board-side lamp Lb. This applies to all of the following descriptions.

[0304] Following the step-up introduction performance ST0 (Fig. 23(a)), one or a plurality of stages of step performances from the first stage to a predetermined stage, here a first step performance ST1 to a third step performance ST3, are sequentially executed. That is, first, as the first stage, a first first-half performance ST1A of the first step performance ST1 is started (Fig. 23(b)). In this first first-half performance ST1A, the elephant, which is the first character, shoots an arrow aiming at a balloon, but here the balloon cannot be hit.

[0305] Furthermore, during this first half-performance ST1A (Figure 23(b)), for example, at its start, a predetermined first start sound is output from the speaker as a sound effect, and following that first start sound, a first half-voice such as "Let's go" is output as a line of dialogue. Note that the output of the first half-voice may start after the output of the first start sound has finished, or it may start during the output of the first start sound. Furthermore, during this first half-performance ST1A (Figure 23(b)), at least a portion of the performance lamp L (here, both the frame-side lamp La and the panel-side lamp Lb) emits light in a first half-light emission mode corresponding to the first half-performance (a first light emission mode corresponding to the first half-performance), for example, in green.

[0306] When the arrow shot by the elephant misses the balloon, the first half of the performance ST1A ends, and the second half of the second step performance ST2A begins (Figure 23(c)). In this second half of the performance ST2A, the second character, the lion, shoots an arrow at the balloon, but just like in the first step performance ST1, it is not possible to hit the balloon here.

[0307] Furthermore, during this second first half performance ST2A (Figure 23(c)), for example, at its start, a predetermined second start sound is output from the speaker as a sound effect, and following this second start sound, a second first half voice such as "This time for sure" is output as a line of dialogue. The second start sound may be the same as or different from the first start sound. Also, the output of the second first half voice may start after the output of the second start sound has finished, or it may start during the output of the second start sound. Furthermore, during this second first half performance ST2A (Figure 23(c)), at least a portion of the performance lamp L (here, both the frame-side lamp La and the panel-side lamp Lb) continue to light up in the first half lighting mode corresponding to the first half performance, for example, in green.

[0308] When the arrow shot by the lion misses the balloon, the second first half of the performance ST2A ends, and the third step of the performance ST3, the third first half of the performance ST3A, begins (Figure 23(d)). In this third first half of the performance ST3A, the third character, the fox, shoots an arrow at the balloon, and in the example in Figure 23, the arrow hits the balloon perfectly (Figure 23(d)).

[0309] Furthermore, during this third first half performance ST3A (Figure 23(d)), for example, at its start, a predetermined third start sound is output from the speaker as a sound effect, and following that third start sound, a third first half voice such as "How's that?" is output as a line of dialogue. The third start sound may be the same as or different from the first and second start sounds. Also, the output of the third first half voice may start after the output of the third start sound has finished, or it may start during the output of the third start sound. Furthermore, during this third first half performance ST2A (Figure 23(d)), at least a portion of the performance lamp L (here, both the frame-side lamp La and the panel-side lamp Lb) continues to light up in the first half illumination mode corresponding to the first half performance, for example, in green, until just before the arrow hits the balloon, and then when the arrow hits the balloon or just before, it transitions to the first half ending illumination mode, for example, a short period of blackout.

[0310] Furthermore, the illumination pattern in the first half may differ for each of the first half sequences, ST1A to ST5A. In this case, the illumination pattern may be configured to change when, for example, the second start sound, the third start sound, etc. is triggered. By configuring it in this way, the player can easily perceive the step-up stages. Alternatively, the illumination pattern may be temporarily changed when, for example, the second start sound, the third start sound, etc. is triggered. In this case, the illumination pattern will not change for the first to fifth first half sequences, ST1A to ST5A, but at least before and after the timing when the second start sound, the third start sound, etc. is output, the illumination pattern will be different (e.g., white). By configuring it in this way, the player can easily perceive that the step-up stage has changed.

[0311] When the arrow hits the balloon (Fig. 23(d)), it is determined that the performance step ends at its third stage, and at that timing (first timing), high-luminance performance WO11 (first high-luminance performance A) (Fig. 23(e)) is performed, and during (or after) the execution of the high-luminance performance WO11, any one of a plurality of types (5 types here) of third latter-half performances ST3Ba to ST3Be, here the third latter-half performance ST3Bc, is executed (Fig. 23(f)). That is, the high-luminance performance WO11 is executed at the timing (first timing) when the first scene image related to the first-half performance switches to the second scene image related to the latter-half performance.

[0312] Here, the high-luminance performance refers to a performance that reduces the visibility of the image behind the high-luminance image 170 (here, the step-up advance notice performance image 169) by displaying the high-luminance image 170. All of the high-luminance performances in the present embodiment are so-called white-out that use a white high-luminance image 170, but the color of the high-luminance image may be any color other than white, such as gray, yellow, blue, red, etc., or may be composed of a plurality of colors. In addition, there may be a case where no image is displayed behind the high-luminance image 170.

[0313] In the high-luminance performance WO11, the high-luminance image 170a is displayed on the front side of the step-up advance notice performance image (specific image) 169 and on the rear side of the mini symbols 165, the hold base image 168, and the hold images X1 to X4, Y1 to Y4 on the front side thereof, so that the visibility of the step-up advance notice performance image (specific image) 169 can be changed without changing the visibility of the hold images X1 to X4, Y1 to Y4 and the mini symbols 165. This also applies to other high-luminance performances described later. It should be noted that in the high-luminance performance WO11, the common high-luminance image 170a is displayed regardless of which of the third latter-half performances ST3Ba to ST3Be is selected. The same applies to the other first, second, fourth, and fifth latter-half performances.

[0314] However, the system is not limited to this, and the high-brightness image 170 may be displayed in front of at least one of the mini symbols 165, the hold images X1~, Y1~, and the hold base image 168, thereby reducing their visibility. In this case, the high-brightness image 170 may be displayed in front of the hold base image 168 and behind the hold images X1~, Y1~. This makes it possible to perform a wider-ranging and more impactful high-brightness effect without reducing the visibility of at least the hold images X1~, Y1~. Furthermore, it is desirable that the display area that does not overlap with the high-brightness image 170 be smaller than the area where the high-brightness image 170 is displayed. This makes it possible to create a stronger impression that the image behind the high-brightness image 170 is obscured. Furthermore, it is desirable that the display area that does not overlap with the high-brightness image 170 be an area in the images of the third second half effect ST3B that will be displayed afterward that does not contain information that suggests reliability (text information, character images, and other images displayed in reliability colors). This makes it possible to achieve the occlusion effect of the high-brightness image 170 without obscuring the entire area of ​​the display screen with the high-brightness image 170.

[0315] The high-brightness image 170 is displayed in white within a predetermined area on the screen, and its transmittance is set to an arbitrary level within that area. The transmittance of the high-brightness image 170 may be uniform or non-uniform within its display area. If the transmittance of the high-brightness image 170 is non-uniform, the transmittance and / or rate of change of the transmittance of the high-brightness image 170 may be configured to differ between the area where information suggesting reliability (text information, character images, and other images displayed in reliability colors) is located and the other areas. In this case, it is desirable to configure the area where information suggesting reliability (text information, character images, and other images displayed in reliability colors) is located to have a lower transmittance and / or rate of change of transmittance. Furthermore, the area where particularly important text information and other images displayed in reliability colors are located may have a lower transmittance and / or rate of change of transmittance than the area where character images are located, or vice versa. In this way, by varying the transmittance and the rate of change of transmittance of high-brightness images according to the display position, it is possible to prevent high-brightness effects from becoming monotonous. Furthermore, by determining the level of transmittance and the rate of change of transmittance, it becomes possible to understand the content of the image displayed in, for example, the second half of the third effect ST3B, making high-brightness effects more complex and interesting.

[0316] Furthermore, the size (display range) of the high-brightness image can be changed over time, and the transmittance value and transmittance distribution can also be changed over time. If the transmittance of high-brightness image 170 is 0%, the image behind high-brightness image 170 becomes completely invisible, and if the transmittance of high-brightness image 170 is 100%, high-brightness image 170 itself becomes completely invisible. Therefore, if the transmittance of a predetermined part of high-brightness image 170 is 100%, it can be considered that that predetermined part is not part of high-brightness image 170 in the first place. Also, if the transmittance of a predetermined part of high-brightness image 170 changes from a value of less than 100% to 100%, it can be considered that the predetermined part was removed from the range of high-brightness image 170 at the point when it reached 100%.

[0317] During the high-brightness performance WO11 (Fig. 23(e)), the output of BGM1 related to the step-up advance notification performance is continued. Also, during the high-brightness performance WO11, a predetermined emphasis sound is output as a sound effect, and this predetermined emphasis sound is configured such that one of the first to fifth predetermined emphasis sounds is selected according to the reliability information related to the big win in the latter-half performance (for example, according to which of ST3Ba to ST3Be is selected in the case of the third latter-half performance). That is, when displaying an image (first party first reliability specifying image) related to, for example, the third latter-half performance ST3Ba (Fig. 22(a1)) while the high-brightness image 170a is being displayed, it is possible to output the first predetermined emphasis sound (first sound performance) corresponding to the image (first party first reliability specifying image) related to the third latter-half performance ST3Ba while the high-brightness image 170a is being displayed, and when displaying an image (first party second reliability specifying image) related to, for example, the third latter-half performance ST3Bc (Fig. 22(c1)) while the high-brightness image 170a is being displayed, it is possible to output the third predetermined emphasis sound (second sound performance) corresponding to the image (first party second reliability specifying image) related to the third latter-half performance ST3Bc while the high-brightness image 170a is being displayed. Thereby, during the high-brightness performance WO11 in which the dialogue character string (character information) is not yet visible or is difficult to visually recognize, the reliability information can be notified to the player in advance by sound, which has the advantage of improving the performance effect.

[0318] Further, a configuration may be adopted in which a common predetermined emphasis sound can be output for each big win reliability in the latter-half performance. For example, the common first predetermined emphasis sound is output when displaying the image (first party first reliability specifying image) related to the third latter-half performance ST3Ba (Fig. 22(a1)), when displaying the image (second party first reliability specifying image) related to the third latter-half performance ST3Bb (Fig. 22(b1)), and when displaying the image (second party first reliability specifying image) related to the third latter-half performance ST3Bc (Fig. 22(c1)), and the common second emphasis sound is output when displaying the image (first party first reliability specifying image) related to the third latter-half performance ST3Bd (Fig. 22(d1)) and when displaying the image (second party first reliability specifying image) related to the third latter-half performance ST3Be (Fig. 22(e1)). Thereby, the player can be notified in advance of the expectation level of the reliability information by the content of the predetermined emphasis sound, which brings about the advantage that the performance effect is improved.

[0319] Furthermore, the first to fifth predetermined emphasis sounds may be configured such that the output volume and / or output time increases as the reliability information regarding the jackpot in the second half of the performance increases. In this case, the output volume and / or output time of the third predetermined emphasis sound (first specific sound) output when the high-brightness performance WO11 is executed during the third second half of the performance ST3Bc (Figure 22(c1)) (first high-brightness performance) will be greater than the output volume and / or output time of the first predetermined emphasis sound (second specific sound) output when the high-brightness performance WO11 is executed during the third second half of the performance ST3Ba (Figure 22(a1)) (second high-brightness performance).

[0320] Furthermore, the first to fifth predetermined emphasis sounds may be configured to be accompanied by a vibration effect by activating a vibration mechanism, based on the reliability information regarding the jackpot in the latter half of the performance, with the higher the jackpot reliability. For example, the first to third predetermined emphasis sounds may be configured not to be accompanied by a vibration effect, while the fourth to fifth predetermined emphasis sounds may be configured to be accompanied by a vibration effect. Alternatively, only the fifth predetermined emphasis sound may be configured to be accompanied by a vibration effect. Here, the vibration mechanism can be configured to vibrate a predetermined part such as the chance button 11. Also, when using the two predetermined emphasis sounds described above, the first predetermined emphasis sound and the second predetermined emphasis sound, only the second predetermined emphasis sound may be configured to be accompanied by a vibration effect. Furthermore, it is not always necessary to be accompanied by a vibration effect; there may be cases where a vibration effect is performed along with the execution of the predetermined emphasis sound, and cases where it is not. More preferably, it is desirable to configure the system so that a vibration effect is performed only when the expectation of a jackpot is high.

[0321] Also, during the high-brightness performance WO11 (the first high-brightness performance), at least a part of the performance lamps L (here, both the frame-side lamps La and the board-side lamps Lb) emit light in a first high-brightness middle light emission mode (a first light emission mode corresponding to the high-brightness performance) (a first light emission performance that causes the light emission means to emit light in the first light emission mode, the first light emission performance). In the present embodiment, the first high-brightness middle light emission mode during the high-brightness performance WO11 is a cyclic change mode that cyclically changes to a plurality of colors (for example, three colors of gold, green, and white) including the character color (for example, gold) of the third latter-half performance ST3B. It should be noted that the first high-brightness middle light emission mode only needs to include a color corresponding to the character color (for example, gold) of the third latter-half performance ST3B, and may be a single color such as gold. As a result, during the high-brightness performance WO11 in which the dialogue character string (text information) is not yet visible or is difficult to see, reliability information can be notified to the player in advance by light emission, which has the advantage of improving the performance effect. When the performance lamps L are caused to emit light in a color corresponding to an image, the emitted light color does not have to be exactly the same as the color of the image, and may be a similar color (for example, the emitted light color for a gold image is yellow).

[0322] During the third latter-half performance ST3Bc (Fig. 23(f)) after the end of the high-brightness performance WO11, as described above, as the step-up advance notice performance image 169, a fox character image is displayed in a large size in a positional relationship that divides the background image into a left background image and a right background image, and a dialogue character string with the content "Something even better seems likely" is displayed in "gold" on the front side of the character image (fox) and the background image so as to straddle both of them.

[0323] Further, during this third latter-half performance ST3Bc (Fig. 23(f)), the output of BGM1 related to the step-up advance notice performance continues, and a predetermined third latter-half voice is output as dialogue sound. This third latter-half voice corresponds to the dialogue character string (text information) displayed on the screen, and is output here as "Something even better seems likely". When outputting this dialogue sound, it is desirable to make the character image perform a so-called lip-sync motion (speaking motion).

[0324] Furthermore, during the third second half performance ST3Bc (Figure 23(f)), at least a portion of the performance lamp L (here, both the frame-side lamp La and the panel-side lamp Lb) emits light in a cyclical change pattern that cyclically changes to multiple colors (here, gold, green, and white) including the text color of the third second half performance ST3Bc (here, gold, green, and white), which corresponds to the second half illumination pattern (third illumination pattern corresponding to a specific image) of the third second half performance ST3Bc. Thus, the second half illumination pattern may be the same as or different from the preceding first high-brightness illumination pattern, but it is desirable to configure it to include the text color of the third second half performance ST3Bc (here, gold). This makes it possible to perform an illumination pattern corresponding to the text color (here, gold) indicating the level of expectation even after the display of the image performance of the third second half performance ST3Bc has finished, and to provide notification using the text color (here, gold) indicating the probability of a big win to players who have missed the image performance as much as possible. Furthermore, it is desirable that the light color of this second-half illumination mode does not include the colors corresponding to other second-half effects (in this case, blue, red, danger color, rainbow). Alternatively, the second-half illumination mode may consist only of the light color corresponding to the text color (for example, gold). It may also be configured not to include the text color of the third second-half effect ST3Bc (in this case, gold), which makes it possible to visually perceive that the effect period of the third second-half effect ST3Bc has ended.

[0325] After execution of the third latter-half performance ST3Bc, a high-brightness performance WO12 (first second high-brightness performance) is performed at that timing (the second timing) (Fig. 23(g)), and during the execution of the high-brightness performance WO12, the step-up preview performance image 169 related to the third latter-half performance ST3Bc is switched to the variation screen of the decorative symbols 164 (specific image end performance) (Fig. 23(h)). Here, the high-brightness performance WO12 differs from the high-brightness performance WO11 in the display area of the high-brightness image and the rate of change of transmittance. This makes it possible to clearly express the start and end of the latter-half performance. Note that the high-brightness performance WO12 and the high-brightness performance WO11 have the same minimum value (0%) of the transmittance of the high-brightness image, but this may also be set differently. Further, the high-brightness performance WO12 may have the same display area of the high-brightness image as the high-brightness performance WO11. Further, the (minimum value of) transmittance and / or the rate of change of transmittance may be the same. This makes it possible to give the player a sense of expectation that the latter-half performance may still continue. Further, the high-brightness performance WO12 is desirably displayed such that at least the area where the information suggesting the reliability in the latter-half performance (text information, character images, and other images displayed in reliability colors) is located is concealed by the high-brightness image. This makes it possible to end the latter-half performance without a sense of discomfort and transition to the symbol variation screen. Further, it may be configured such that at least the area where any one of the information suggesting the reliability in the latter-half performance (text information, character images, and other images displayed in reliability colors) is located is concealed by the high-brightness image.

[0326] During the high-brightness effect WO12 (Figure 23(g)), for example, the BGM output is stopped. Also during the high-brightness effect WO12, a specific emphasized sound is output as a sound effect, and this specific emphasized sound is selected from the 1st to 5th specific emphasized sounds depending on the reliability information regarding the jackpot in the second half of the effect (for example, depending on whether ST3Ba to ST3Be is selected in the third second half of the effect). Alternatively, the high-brightness effect WO12 may be configured to output a common specific emphasized sound as a sound effect. That is, it may be configured to output a common specific emphasized sound regardless of the content of the reliability information regarding the jackpot in the second half of the effect. This allows, for example, the high-brightness effect WO11 to output different predetermined emphasized sounds depending on the reliability information regarding the jackpot in the second half of the effect, while the high-brightness effect WO12 can output a common specific emphasized sound regardless of the reliability information regarding the jackpot, making it possible to express different effects in the high-brightness effect WO11 and the high-brightness effect WO12, respectively. Furthermore, the predetermined emphasis sound during the high-brightness effect WO11 may be the same regardless of the reliability information regarding the jackpot, while the specific emphasis sound during the high-brightness effect WO12 may be configured to differ depending on the reliability information regarding the jackpot.

[0327] Furthermore, the first to fifth specific emphasis sounds may be configured such that the output volume and / or output time increases as the reliability information regarding the jackpot in the second half of the performance increases. In this case, the output volume and / or output time of the third specific emphasis sound (first specific sound) output when the high-brightness performance WO12 is executed during the third second half of the performance ST3Bc (Figure 22(c1)) (first high-brightness performance) will be greater than the output volume and / or output time of the first specific emphasis sound (second specific sound) output when the high-brightness performance WO12 is executed during the third second half of the performance ST3Ba (Figure 22(a1)) (second high-brightness performance). Also, the first to fifth specific emphasis sounds in the high-brightness performance WO12 may be different from or the same as the first to fifth predetermined emphasis sounds in the high-brightness performance WO11.

[0328] Furthermore, during the high-brightness effect WO12 (second high-brightness effect), at least a portion of the effect lamp L (here, both the frame-side lamp La and the panel-side lamp Lb) emits light in a cyclical change pattern that cyclically changes to multiple colors (here, gold, green, and white) including the text color (here, gold) of the third second-half effect ST3Bc (a specific light emission effect that causes the light emission means to emit light in a specific light emission pattern corresponding to a specific image). Thus, the second-half light emission pattern may be the same as or different from the first high-brightness medium-brightness light emission pattern and the second-half light emission pattern, but it is desirable to configure it to include the text color (here, gold) of the third second-half effect ST3Bc. Alternatively, the second-half light emission pattern may be configured not to include the text color (here, gold). Furthermore, by configuring the first high-brightness medium-brightness light emission pattern to include the text color and the second-half light emission pattern not to include the text color, it is possible to avoid monotonous effect expression and prevent a decrease in the effect.

[0329] After the high-brightness effect WO12, when the symbol variation screen begins, a symbol stop sound is output as a sound effect in conjunction with the stopping of decorative symbols 164a to 164c.

[0330] Next, regarding the step-up announcement effect shown in FIG. 23 as described above, the effect period centered on the high-brightness effects WO11 and WO12 will be described in more detail. FIGS. 24 to 26 show changes in the display screen and light-emitting means at even smaller time intervals than in FIG. 23 for the period from FIG. 23(e) to (h), that is, the period from the start point of the high-brightness effect WO11 to the end of the high-brightness effect WO12 and the transition to the variation screen of the decorative symbols 164. Note that the 22-frame display images shown in FIGS. 24 to 26 do not represent all the frames in the period of FIGS. 23(e) to (h), but are extracted at a constant pitch from all the frames. Accordingly, in FIGS. 24 to 26, the time intervals between adjacent frames are all the same (here, defined as A milliseconds). As such, in FIGS. 24 to 26, the relationship is such that if the number of frames doubles, the time also doubles. For example, the elapsed time between FIGS. 24(a) to (c) is the same as that between FIGS. 24(d) to (f), and the elapsed time between FIGS. 24(d) to (g) is longer than the elapsed time between FIGS. 24(a) to (c).

[0331] First, the details of the high-brightness effect WO11 will be described. In the high-brightness effect WO11 shown in FIGS. 24(a) to 25(j), at its start, a high-brightness image 170a is displayed on the front side of the step-up announcement effect image (specific image) 169 and on the rear side of the mini symbols 165, the hold base image 168, and the hold images X1 to X4 and Y1 to Y4 on the front side thereof (FIG. 24(a)) (high-brightness image display processing), and the size (range) and transmittance of the high-brightness image 170a gradually change until it finally disappears (FIG. 24(j)).

[0332] Further, the high-brightness image 170a is configured such that its size (range) is the maximum at the start of display (Figure 24(a)), and gradually decreases as time elapses. That is, the high-brightness performance WO11 is composed of an enlargement change performance that changes the size (range) of the high-brightness image 170a in the enlargement direction, and a reduction change performance that similarly changes it in the reduction direction, and the execution time of the latter (Figure 24(a) to Figure 25(j)) is longer than that of the former (Figure 24(a)). In the high-brightness performance WO11, the coverage of the high-brightness image 170a with respect to the entire step-up advance notification performance image 169 is less than 100%, and even when the size (range) of the high-brightness image 170a is the maximum (Figure 24(a)), a part of the step-up advance notification performance image 169 is visible from the front side. Of course, when the size (range) of the high-brightness image 170a is the maximum, the coverage of the high-brightness image 170a with respect to the entire step-up advance notification performance image 169 may be 100%. In addition, it is sufficient that a part of predetermined information (character information, character images, reliability color display images, etc.) in the step-up advance notification performance image is concealed by the high-brightness image 170a, making it difficult to perceive and / or difficult to view, and it is not necessary that all of the predetermined information is concealed.

[0333] Further, the high-brightness image 170a is set such that the transmittance within its range is substantially uniform. In addition, the high-brightness image 170a changes not only in its size (range) but also in transmittance as time elapses (transmittance change processing, transmittance change performance), and is configured such that the transmittance at the start of display (Figure 24(a)) is the minimum (for example, 0%), and gradually increases (rises) at a constant rate of change, for example, as time elapses. That is, the high-brightness performance WO11 is composed of a low transmittance change performance that changes the transmittance of the high-brightness image 170a in the decreasing direction, and a high transmittance change performance that changes the transmittance of the high-brightness image 170a in the increasing direction, and the execution time of the latter (Figure 24(a) to Figure 25(j)) is longer than that of the former (Figure 24(a)).

[0334] Note that the minimum transmittance of the high-brightness image 170a may be greater than 0%. Further, the transmittance of the high-brightness image 170a does not need to have a constant rate of change (amount of change per unit time). Further, the transmittance of the high-brightness image 170a may be non-uniform, and the non-uniform transmittance may be configured to change over time. Further, the size (range) of the high-brightness image 170a may be changed without changing its transmittance, or the transmittance of the high-brightness image 170a may be changed without changing its size (range). However, a reduction in the size (range) of the high-brightness image 170a can be considered as a substantial disappearance of that part due to the transmittance of the partial area of the high-brightness image 170a increasing to 100%, so changing the size (range) of the high-brightness image 170a can also be said to be substantially changing the transmittance of the high-brightness image 170a.

[0335] Further, in the high-brightness performance WO11, for the step-up advance notice performance image 169 displayed on the rear side of the high-brightness image 170a, for example, at the start of display of the high-brightness image 170a (Fig. 24(a)), the image is switched from the image of the preceding third first-half performance ST3A (see Fig. 23(d)) to the image of the third second-half performance ST3Bc (see Fig. 22(c1)). Thereby, after the high-brightness performance WO11 starts, as the size (range) of the high-brightness image 170a gradually decreases and the transmittance thereof also gradually increases, the visibility of the step-up advance notice performance image 169 improves, and when the high-brightness image 170a eventually disappears (Fig. 25(j)), the entire step-up advance notice performance image 169 (excluding the part hidden behind the mini symbols 165 and the like) becomes completely visible.

[0336] Furthermore, during the high-brightness effect WO11, the effect lamp L emits light in a first high-brightness medium emission mode. The first high-brightness medium emission mode is a cyclical change mode that cyclically changes through multiple colors (for example, gold, green, and white) including the text color (for example, gold) of the third second half effect ST3Bc. For example, the emission color changes in the order of green (Figures 24(a)~(c)), white (Figures 24(d)~(f)), and gold (Figures 24(g)~(i)), so that the gold emission corresponding to the text color appears in the latter half or at the end of the high-brightness effect WO11. However, the configuration is not limited to this, and the emission mode of the effect lamp L, for example, the brightness and / or emission color may be changed in accordance with the change in the transmittance of the high-brightness image 170a. This allows for a better correlation between the change in the transmittance of the high-brightness image 170a and the change in the emission mode, thereby enhancing the effect. Furthermore, the lighting mode (e.g., brightness and color) of the lighting lamp L may be configured to change in stages according to the change in transmittance of the high-brightness image 170a. For example, the first lighting mode may be used when the transmittance of the high-brightness image 170a is 0% to 30%, the second lighting mode when it is 31% to 70%, and the third lighting mode when it is 71% to 99%.

[0337] As described above, during the high-brightness effect WO11, the visibility of the subsequent step-up preview effect image 169 changes over time due to changes in the size (range) and / or transmittance of the high-brightness image 170a, and the character information constituting the step-up preview effect image 169 transitions from an invisible (or difficult to see) state to an visible (or easily visible) state at a predetermined point in time (for example, Figure 24(d)). That is, during the high-brightness effect WO11, it is possible to perform a first transmittance change process that changes the transmittance of the high-brightness image 170a while the character information is invisible (or difficult to see), and a second transmittance change process that changes the transmittance of the high-brightness image 170a while all of the character information is visible (or easily visible). The execution time of the former (for example, Figures 24(a) to (d)) and the latter (for example, Figures 24(d) to 25(j)) differs, with the latter taking longer than the former. In this way, by making the execution time of the latter longer than that of the former, the text information that players are most interested in can be revealed to them earlier, and sufficient time can be provided for displaying high-brightness images, thereby enhancing the effect of the high-brightness effects themselves.

[0338] Furthermore, the execution time for the first transparency change process may be longer than that for the second transparency change process, or the execution times for the former and the latter may be made approximately the same. By making the execution time for the first transparency change process longer than that for the second transparency change process, the disclosure of text information can be delayed, thereby heightening the player's sense of anticipation and tension. Also, once the text information has been disclosed, it is desirable to disclose the entire information as soon as possible (to improve visibility in order to make the text information easier to see earlier), so if the execution time for the first transparency change process is set to be longer, it is desirable to make the execution time for the second transparency change process shorter.

[0339] Regarding the boundary between the state where the character information is non-visible (or difficult to visually recognize) and the state where it is visible (or easy to visually recognize), for example, it may be defined that the character information becomes visible (or easy to visually recognize) at the timing when at least part of the character information no longer overlaps with the high-brightness image. Alternatively, it may be defined that the character information becomes visible (or easy to visually recognize) at the timing when all (the entirety of) the character information no longer overlaps with the high-brightness image.

[0340] During the high-brightness performance WO11, it is possible to execute a first range change process that changes the size (range) of the high-brightness image 170a while the character information is in a non-visible (or difficult to visually recognize) state, and a second range change process that changes the size (range) of the high-brightness image 170a while all of the character information is in a visible (or easy to visually recognize) state. The execution time differs between the former (for example, Figures 24(a) to (d)) and the latter (for example, Figures 24(d) to 25(j)), and the execution time of the latter is longer than that of the former. The execution time of the first range change process may be set longer than that of the second range change process, or the execution times of the former and the latter may be made substantially equal.

[0341] When the high-brightness performance WO11 ends and the entire step-up advance notification performance image 169 related to the third latter-half performance ST3Bc becomes visible (Figure 25(j)), the dialogue sound (third latter-half voice) of "It seems something better will happen" corresponding to the dialogue character string (character information) displayed on the screen is output. For the step-up advance notification performance image 169, the following dynamic display is performed in response to the output of the dialogue sound (post-execution dynamic display process, post-execution change process). That is, as shown in Figures 25(j) to (o), while the dialogue sound (third latter-half voice) is being output, the fox character image performs a so-called lip-syncing operation in time with the dialogue sound, and the dialogue character string performs a predetermined operation (here, swinging of each character). In addition, the display color of the character corresponding to the dialogue sound being output changes temporarily (for example, from gold to white). As a result, it is perceived that the white part moves, for example, from left to right over the character string "It seems something better will happen" displayed in gold. Note that the dialogue sound may be output without accompanying the lip-syncing operation of the character.

[0342] When the post-execution dynamic display processing (Fig. 25(j) to (o)) in the third-half effect ST3Bc ends, the high-brightness effect WO12 is subsequently started. In the high-brightness effect WO12 shown in Fig. 25(o) to Fig. 26(v), similar to the high-brightness effect WO11, a high-brightness image 170b appears on the front side of the step-up preview effect image 169 and on the rear side of the mini symbols 165, the hold base image 168, and the hold images X1 to X4 and Y1 to Y4 on the front side thereof, and then disappears after a while. The display pattern of the high-brightness image 170b in this high-brightness effect WO12 (second high-brightness effect) is different from the display pattern of the high-brightness image 170a in the high-brightness effect WO11 (first high-brightness effect), and the length of its execution time is also different. Note that, similarly to the high-brightness effect WO11 (first high-brightness effect), the high-brightness effect WO12 (second high-brightness effect) may also be configured to transition to the symbol variation screen by displaying a high-brightness image with a low transmittance (e.g., 0%) in a short time, and then increasing the transmittance of the high-brightness image over a time longer than that short time.

[0343] That is, the high-brightness image 170b is configured such that its size (range) gradually increases with the lapse of time to reach the maximum at a predetermined time point (Fig. 25(o) to Fig. 26(s)), and then gradually decreases with the lapse of time to finally disappear (Fig. 26(s) to (v)). As described above, the high-brightness effect WO12 includes an enlargement change effect that changes the size (range) of the high-brightness image 170b in the enlargement direction, and a reduction change effect that similarly changes the size in the reduction direction, and the execution time of the latter (Fig. 26(s) to (v)) is shorter than that of the former (Fig. 25(o) to Fig. 26(s)). In the high-brightness effect WO12, the coverage of the high-brightness image 170b with respect to the entire step-up preview effect image 169 is less than 100%, and even when the size (range) of the high-brightness image 170b is maximum (Fig. 26(s)), a part of the step-up preview effect image 169 is outside the range of the high-brightness image 170b. Of course, when the size (range) of the high-brightness image 170b is maximum, the coverage of the high-brightness image 170 with respect to the entire step-up preview effect image 169 may be 100%.

[0344] It should be noted that the high-brightness performance WO12 (the second high-brightness performance) and the high-brightness performance WO11 (the first high-brightness performance) may be configured to have different coverage ratios of the high-brightness image with respect to the entire step-up advance notice performance image. In this case, it is desirable that at least the information suggesting the reliability (text information, character information, display suggesting the reliability color) is covered by the high-brightness image in both the high-brightness performance WO12 (the second high-brightness performance) and the high-brightness performance WO11 (the first high-brightness performance). In addition, at the timing of executing the high-brightness performance WO12 (the second high-brightness performance), since the information suggesting the reliability has already been disclosed, an area / range where such information is not hidden by the high-brightness image may exist.

[0345] Further, the high-brightness image 170b is set such that the transmittance is substantially uniform within its range. The high-brightness image 170b is configured such that not only its size (range) but also its transmittance is variable (transmittance changing process, transmittance changing performance). With the passage of time, the transmittance gradually decreases at a constant rate of change, for example, and reaches the minimum value (here, 0%) at a predetermined point in time (Fig.25(o) to Fig.26(s)), and then gradually increases at a constant rate of change, for example, with the passage of time (Fig.26(s) to (v)). That is, the high-brightness performance WO12 is composed of a low transmittance changing performance that changes the transmittance of the high-brightness image 170b in the decreasing direction, and a high transmittance changing performance that changes the transmittance of the high-brightness image 170b in the increasing direction, and the execution time of the latter (Fig.26(s) to (v)) is shorter than that of the former (Fig.25(o) to Fig.26(s)). Although the minimum transmittance of the high-brightness image 170b is set to 0% (Fig.26(s)), it may be greater than 0%. Of course, the transmittance of the high-brightness image 170b may be non-uniform, and the non-uniform transmittance may be changed with the passage of time. In addition, the execution time of the high transmittance changing performance may be made longer than that of the low transmittance changing performance, or the execution times of both may be made substantially the same.

[0346] Further, the size (range) of the high-brightness image 170b may be changed without changing the transmittance thereof, or the transmittance of the high-brightness image 170b may be changed without changing the size (range) thereof. However, a reduction in the size (range) of the high-brightness image 170b can be considered as a substantial disappearance of a portion of the high-brightness image 170b caused by the transmittance of said portion increasing to 100%, and thus changing the size (range) of the high-brightness image 170b can also be said to substantially change the transmittance of the high-brightness image 170b.

[0347] Further, in the high-brightness performance WO12, the step-up preview performance image 169 displayed on the rear side of the high-brightness image 170b is switched to the variation screen of the decorative patterns 164 (see FIG. 23(h)), for example, at the timing when the size (range) of the high-brightness image 170b is maximum and the transmittance thereof is minimum (FIG. 26(s)), or at a timing in the vicinity thereof. As a result, after the high-brightness performance WO12 is started, as the size (range) of the high-brightness image 170b gradually increases and the transmittance thereof also gradually decreases, the visibility of the step-up preview performance image 169 related to the third latter-half performance ST3B decreases, and the screen is switched to the variation screen of the decorative patterns 164 at the point in time when the visibility of the step-up preview performance image 169 is the lowest (FIG. 26(s)), or at a timing in the vicinity thereof. Thereafter, as the size (range) of the high-brightness image 170b gradually decreases and the transmittance thereof also gradually increases, the visibility of the variation screen of the decorative patterns 164 improves, and when the high-brightness image 170b eventually disappears (FIG. 26(v)), the entire variation screen of the decorative patterns 164 (excluding the portion hidden behind the mini patterns 165 and the like) becomes completely visible. In this manner, during the execution of the high-brightness performance WO12, a specific image end performance for ending the display of the step-up preview performance image (specific image) 169 is executed.

[0348] Note that during the third latter-half performance ST3Bc (during post-execution dynamic display processing) after the high-brightness performance WO11 ends, the performance lamp L emits light in a latter-half light emission mode, and during the subsequent high-brightness performance WO12, the performance lamp L emits light in a second high-brightness-period light emission mode. In the present embodiment, both the latter-half light emission mode and the second high-brightness-period light emission mode are common with the first high-brightness-period light emission mode, forming a cyclic change mode that cyclically changes among a plurality of colors (for example, three colors of gold, green, and white) including the character color (for example, gold) of the third latter-half performance ST3Bc, such that the light emission color changes in the order of green (Fig. 25(j) to (l)), white (Fig. 25(m) to (o)), gold (Fig. 25(p) to (r)), and green (Fig. 26(s) to (u)). Note that at least one of the latter-half light emission mode and the second high-brightness-period light emission mode may be different from the first high-brightness-period light emission mode. However, even in that case, it is desirable that any of the light emission modes include a color corresponding to the character color (for example, gold).

[0349] As described above, the step-up advance notification performance has a first-half performance before displaying the step-up advance notification performance image 169 (specific image) having reliability information related to a jackpot (that is, character information whose display color and content differ according to the jackpot reliability), and a latter-half performance after displaying the step-up advance notification performance image 169 (specific image) having the reliability information related to the jackpot, wherein after the execution of the first-half performance, before or at the start of the latter-half performance, the high-brightness performance WO11 is executed on the front side of the specific image. Further, the performance lamp (light emitting means) L emits light in a first-half light emission mode (first light emission mode) corresponding to the first-half performance during the first-half performance, and emits light in a first high-brightness-period light emission mode (second light emission mode) corresponding to the high-brightness performance WO11 during the high-brightness performance WO11.

[0350] Further, in high-brightness performances WO11 and WO12 of the step-up preview performance, the high-brightness images 170a and 170b are displayed on the front side of the step-up preview performance image 169 (specific image) and on the rear side of the first and second reserved images (reserved images) X1~, Y1~ and the mini symbols 165, so that the visibility of the step-up preview performance image 169 is changed, while the visibility of the first and second reserved images X1~, Y1~ and the mini symbols 165 is not changed. The high-brightness performance WO11 is composed of a low transmittance change performance that changes the transmittance of the high-brightness image 170a in the decreasing direction, and a high transmittance change performance that changes the transmittance of the high-brightness image 170a in the increasing direction, and the execution time of the latter (Fig. 24(a) to Fig. 25(j)) is longer than that of the former (Fig. 24(a)). On the other hand, in the high-brightness performance WO12, the execution time of the high transmittance change performance (Fig. 26(s) to (v)) is shorter than that of the low transmittance change performance (Fig. 25(o) to Fig. 26(s)).

[0351] Further, in the high-brightness performance WO11 of the step-up preview performance, a high-brightness image display process (Fig. 24(a)) for displaying the high-brightness image 170a, and a transmittance change process (Fig. 24(a) to Fig. 25(j)) for changing the transmittance of the high-brightness image 170a displayed by the high-brightness image display process can be executed, and by increasing the transmittance of the high-brightness image 170a through the transmittance change process, the visibility of the step-up preview performance image 169 on the rear side thereof is gradually improved. In addition, the step-up preview performance image 169 includes a character image (specific character information) having reliability information, and during the high-brightness performance WO11, a first transmittance change process that changes the transmittance of the high-brightness image 170a in a state where the character information is not visible (or difficult to see), and a second transmittance change process that changes the transmittance of the high-brightness image 170a in a state where all of the character information is visible (or easy to see) can be executed. The execution time differs between the former (for example, Fig. 24(a) to (d)) and the latter (for example, Fig. 24(d) to Fig. 25(j)), and the execution time of the latter is longer than that of the former.

[0352] Further, in the step-up notice effect, any of a plurality of types of specific images can be displayed, including a step-up notice effect image (a first reliability specifying image having first reliability information corresponding to a first reliability) displayed in a third latter-half effect ST3Ba (FIG. 22(a1)), and a step-up notice effect image (a second reliability specifying image having second reliability information corresponding to a second reliability higher than the first reliability) displayed in a third latter-half effect ST3Bc (FIG. 22(c1)). During the display of a high-brightness image 170a in a high-brightness effect WO11, the high-brightness image 170a is common to the case of the third latter-half effect ST3Ba and the case of a third latter-half effect ST3Bb. In the case of the third latter-half effect ST3Ba, a first predetermined emphasis sound corresponding to the image related to the third latter-half effect ST3Ba (the first reliability specifying image) can be output during the display of the high-brightness image 170a (first sound effect), and in the case of the third latter-half effect ST3Bc, a third predetermined emphasis sound corresponding to the image related to the third latter-half effect ST3Bc (the second reliability specifying image) can be output during the display of the high-brightness image 170a (second sound effect).

[0353] Further, in the step-up notice effect, during execution of a high-brightness effect WO12, the step-up notice effect image 169 related to the third latter-half effect ST3Bc is switched to a variation screen of decorative symbols 164, whereby a specific image end effect for terminating the display of the step-up notice effect image 169 including a character image can be executed. Further, when executing the specific image end effect during execution of the high-brightness effect WO12, an effect lamp (light emitting means) L emits light in a second high-brightness light emission mode including the character color of the latter-half effect (a specific light emission mode corresponding to the specific image) (specific light emission mode).

[0354] Further, in the step-up notice effect, after a step-up notice effect image (specific image) 169 having reliability information related to a big win is displayed during execution of a high-brightness effect WO11 (first high-brightness effect), the display is terminated during execution of a high-brightness effect WO12 (second high-brightness effect) (effect at the end of the specific image). The high-brightness effect WO11 and the high-brightness effect WO12 have different execution durations, and in the examples of FIGS. 24 to 26, the execution duration of the high-brightness effect WO11 is longer than that of the high-brightness effect WO12.

[0355] Further, in the step-up notice performance, a step-up notice performance image 169 having jackpot reliability information is displayed during execution of the high-brightness performance WO11, and after the end of the high-brightness performance WO11, post-execution dynamic display processing for dynamically displaying at least a part of the step-up notice performance image 169, and post-execution change processing (Figs. 25(j) to (o)) for causing a predetermined change (color change) to at least a part of the step-up notice performance image 169, are executed.

[0356] Further, in the step-up notice performance, a high-brightness performance (first high-brightness performance) WO11 for displaying a high-brightness image (first high-brightness image) 170a, and a high-brightness performance (second high-brightness performance) WO12 for displaying a high-brightness image (second high-brightness image) 170b can be executed, the high-brightness performance (first high-brightness performance) WO11 is executed at a first timing at which the first scene image related to the first-half performance switches to the second scene image related to the second-half performance, and the high-brightness performance (second high-brightness performance) WO12 is executed at a subsequent second timing.

[0357] Further, in the step-up notice performance, display of a character image having jackpot reliability information is started during the high-brightness performance WO11, and the high-brightness performance WO12 (performance at the end of the specific image) can be executed when the display of the character image ends. Further, during the high-brightness performance WO11, a first light-emission performance is executed in which a performance lamp (light-emitting means) L is caused to emit light in a first high-brightness middle light-emission mode (first light-emission mode) corresponding to the reliability information (for example, display color) in the character image, and during the high-brightness performance WO12 (performance at the end of the specific image), a second light-emission performance is executed in which the performance lamp (light-emitting means) L is caused to emit light in a second high-brightness middle light-emission mode (second light-emission mode). The second high-brightness middle light-emission mode (second light-emission mode) may be different from the first high-brightness middle light-emission mode (first light-emission mode).

[0358] Further, in the step-up notice effect, the third predetermined emphasis sound (second party first specific sound) output when the high-brightness effect WO11 is executed during the third latter-half effect ST3Bc (FIG. 22(c1)) (second party first high-brightness effect) has a larger output volume and / or longer output time than the first predetermined emphasis sound (second party second specific sound) output when the high-brightness effect WO11 is executed during the third latter-half effect ST3Ba (FIG. 22(a1)) (second party second high-brightness effect). The configuration may be such that a vibration effect is executed substantially simultaneously with the third predetermined emphasis sound. Alternatively, the configuration may be such that a vibration effect is executed in place of the third predetermined emphasis sound.

[0359] The step-up notice effect is an example of a character information display effect for displaying character information, and is capable of executing the high-brightness effect WO11 as a character information display start effect (first specific effect) performed when starting the display of character information, and the high-brightness effect WO12 as a character information display end effect (second specific effect) performed when ending the display of character information. After the execution of the high-brightness effect WO11 (character information display start effect), display mode change processing for changing the display mode of the character information (specific display processing for displaying character information in a specific display mode) (FIG. 25(j) to (o)) is executed, and the configuration is such that the display mode change processing (specific display processing) is not executed while the high-brightness effect WO12 (character information display end effect) is being executed.

[0360] Note that in the step-up preview performance described above, the number of variations of reliability display executable in the first to fifth latter-half performances ST1B to ST5B is uniformly set to 5 types (FIG. 22), but the number of variations of reliability indication executable in the subsequently executed first to fifth latter-half performances ST1B to ST5B may be varied according to the content of the first to fifth former-half performances ST1A to ST5A. Specifically, 3 types of reliability indications from the lower reliability side may be executable for the first to third latter-half performances ST1B to ST3B, and 5 types of reliability indications may be executable for the fourth and fifth latter-half performances ST4B to ST5B. Further, in the case of the fourth and fifth latter-half performances ST4B to ST5B, it is possible to execute reliability indications (two types with high reliability) that are not executed in the first to third latter-half performances ST1B to ST3B. Further, the number of executable reliability indication variations may be varied according to characters or stages, such as 3 types for the first latter-half performance ST1B, 3 types for the second latter-half performance ST2B, 3 types for the third latter-half performance ST3B, 5 types for the fourth latter-half performance ST4B, and 4 types for the fifth latter-half performance ST5B.

[0361] Further, according to the selection rate of each character, the number of reliability indication variations for characters with a high selection rate may be increased, and the number of reliability indication variations for characters with a low selection rate may be decreased. With this configuration, more performance variations can be presented to the player, and a performance configuration that does not bore the player can be achieved. Further, the number of reliability indication variations may be larger for characters with a lower selection rate than for characters with a higher selection rate. Further, in a case where the characters are set in descending order of selection rate as elephant, lion, fox, squirrel, and bear, the number of reliability indication variations for the fox and the squirrel may be larger than that for the elephant and the lion. Further, in this case, the number of reliability indication variations for the bear may be smaller than that for the fox and the squirrel. In this case, it is desirable that the reliability indication variations executed when the bear is selected are configured such that no low-reliability variations are prepared, and only high-reliability variations are prepared.

[0362] The various configurations in the above step-up preview performance are not limited to being adopted in this step-up preview performance, and can be similarly adopted in various other performances (preview performances and partial performances). For example, various configurations such as the high-brightness performances WO11 and WO12 in the step-up preview performance may be adopted in the reach preview performance, the dialogue preview performance, etc., which will be described later.

[0363] [Reach Preview Performance] Figures 27 to 31 show an example of the reach preview performance executed during normal variation in a reach variation pattern or a normal variation pattern. This reach preview performance (specific preview performance) is for giving a preview related to the establishment of a reach state, and is composed of a reach preview first-half performance RC1 and a reach preview second-half performance RC2, and is set such that the performance mode of the reach preview second-half performance RC2 is selected from a plurality of types (here, four types shown in Figure 27) according to the type of the selected variation pattern. Note that the jackpot reliability is set to gradually increase from the first performance mode RC2a (Figure 27(a)) to the fourth performance mode RC2d (Figure 27(d)). In this way, for example, the performance image by the first performance mode RC2a (Figure 27(a)) is an example of a first specific reliability image corresponding to a first reliability, and the performance image by the second performance mode RC2b (Figure 27(b)) is an example of a second specific reliability image corresponding to a second reliability.

[0364] The plurality of (four) performance modes RC2a to RC2d of this reach preview second-half performance RC2 are substantially common in the characters appearing in the performance images and their actions, and differ in the dialogue character string displayed in front of the character image or the like, the dialogue sound output by voice corresponding thereto, and the base color of the performance images. That is, as shown in Figure 27, the same kappa character image is displayed in all of the first to fourth performance modes RC2a to RC2d, but the contents of the dialogue character string displayed in front of the character image and the corresponding dialogue sound are all different among the four types, which are "It's reach!", "It's SP reach!", "Big chance!!", and "Super hot!!" respectively.

[0365] Furthermore, the display color of the speech character string and the base color of the performance image are all different among the four types, and the display color (internal color) and base color of the speech character string corresponding to the first to fourth performance modes RC2a to RC2d are respectively "blue", "red", "gold", and "danger color". The danger color is as described above. As described above, since the first to fourth performance modes RC2a to RC2d have different jackpot reliability according to the display color of the character string or the like, it can be said that the character image (specific character information) or the reach announcement performance image having the character image has reliability information related to the jackpot. A plurality of display modes (here, display colors) may be provided for a common character string. In cases where the character string itself indicates the reliability, such as "super hot", it is desirable to enable performance expression by a plurality of display modes (display colors) with different reliabilities, for example, by configuring the "super hot" in danger color to indicate a higher reliability than the "super hot" in gold. In this case, a plurality of types of display modes other than the display color (character color), such as the size of the character outline, may be provided.

[0366] Next, a specific example of the reach announcement performance will be described taking as an example the case where the first performance mode RC2a (Fig. 27(a)) among the first to fourth performance modes RC2a to RC2d is selected. First, the outline will be described with reference to Fig. 28. When the reach announcement performance is started during the normal variation in the reach variation pattern, the output of BGM2 related to this reach announcement performance is started from the speaker as BGM, and on the display screen DSa, the decorative symbols 164 that are under high-speed variation are hidden, with the reserved pedestal image 168 displayed on the lower end side and the mini symbols 165 displayed on the upper end side, and the reach announcement performance image 171 related to the first half reach announcement performance RC1 is displayed behind them (Fig. 28(a)). The reach announcement performance image 171 related to the first half reach announcement performance RC1 is configured with a scene in which a kappa character flies in the sky.

[0367] Also, during this reach announcement first-half performance RC1 (Fig. 28(a)), at least a part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) emits light in a first-half light emission mode corresponding to the reach announcement first-half performance, for example, in orange. A predetermined start sound may be output as a sound effect at the start of the reach announcement performance.

[0368] Thereafter, the performance shifts from the reach announcement first-half performance RC1 to the reach announcement second-half performance RC2 (here, the first performance mode RC2a), and the reach announcement performance image 171 switches to a scene where the kappa character is shown in an upper body close-up (from Fig. 28(b) onward). Also, at the time of the scene change accompanying the shift from the reach announcement first-half performance RC1 to the reach announcement second-half performance RC2 (switching from the first scene image to the second scene image) (the first timing), a high-brightness performance (first high-brightness performance) WO21 is executed (Fig. 28(b)) that displays the high-brightness image 170c to reduce the visibility of the image behind the high-brightness image 170c (here, the reach announcement performance image 171). In this way, at the first timing when the high-brightness performance WO21 is performed, the speech character string (character image) having reliability information related to the jackpot is not yet displayed on the screen. In this high-brightness performance WO21, the minimum transmittance of the high-brightness image is set to be greater than 0%, but the minimum transmittance of the high-brightness image may be set to 0% so that the character image behind it becomes completely invisible.

[0369] During the high-brightness performance WO21 (Fig. 28(b)), the output of BGM 2 related to the reach announcement performance continues. Also, at the start of the high-brightness performance WO21, a predetermined first emphasis sound is output as a sound effect. During the high-brightness performance WO21, at least a part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) emits light in a high-brightness mid-performance light emission mode. This high-brightness mid-performance light emission mode includes a specific color (for example, blue) corresponding to the character color of the reach announcement second-half performance RC2, and is configured to change, for example, from a predetermined color (here, white) to the specific color (here, blue). This high-brightness mid-performance light emission mode may be configured not to include the specific color corresponding to the character color. This makes it possible to prevent the content of the character information to be displayed later from being leaked in advance.

[0370] When the high-brightness performance WO21 ends and the reach advance notification performance image 171 becomes fully visible (Fig. 28(c)), display of the dialogue character string (text information) "Reach!" is started on the front side of the character image (text information display start performance). At this time, the dialogue character string appears with a first dynamic display performance (Fig. 28(c)→(d)). That is, during the first dynamic display period in which the first dynamic display performance is executed, the text information display start performance (first specific performance) performed when starting display of the text information is executed. In this first dynamic display performance, the dialogue character string moves (here, a movement accompanied by rotation) at a first change speed toward a predetermined display position.

[0371] During the text information display start performance, the output of BGM2 related to the reach preview performance continues. At the start of displaying the dialogue character string (at the start of the text information display start performance), a predetermined character appearance sound is output as a sound effect. During the text information display start performance, at least a part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) emits light in a character appearance light emission mode. This character appearance light emission mode is a cyclic change mode that cyclically changes between a plurality of colors (for example, blue and white) including the character color of the dialogue character string displayed on the screen (here, blue). It is preferable that the light emission colors used for this cyclic change mode do not use colors indicating higher reliability than the character color of the dialogue character string (here, blue) (such as red and gold in this case), and in this case, it is desirable to use a color that indicates lower reliability than the character color of the dialogue character string, or a light emission color that is not used for suggesting reliability (such as white in this case). Alternatively, a light emission mode corresponding only to the character color of the dialogue character string may be adopted, or for example, blinking light emission other than continuous lighting may be used. Alternatively, only a specific light emitting portion may be set to a light emission color corresponding to the character color of the dialogue character string, and the other light emitting portions may be configured to emit light in other light emission modes (for example, white or off). At this time, for the other light emission modes, it is preferable not to use colors indicating higher reliability than the light emission color corresponding to the character color of the dialogue character string (here, blue) (such as red and gold in this case), and it is desirable to use a color that indicates lower reliability than the character color of the dialogue character string, or a light emission color that is not used for suggesting reliability (such as white in this case).

[0372] When the dialogue character string is displayed at a predetermined display position through the first dynamic display performance (at the second timing), by displaying the high-brightness image 170d, the high-brightness performance (first second high-brightness performance) WO22 that reduces the visibility of the image behind the high-brightness image 170d (here, the reach advance announcement performance image 171) is executed (FIG. 28(d)). As such, at the second timing when the high-brightness performance WO22 is performed, the dialogue character string (character image) having the reliability information related to the big win has already been displayed on the screen. During this high-brightness performance WO22, the output of BGM2 related to the reach advance announcement performance continues, and a predetermined second emphasis sound is output as a sound effect. Also, during the high-brightness performance WO22, at least part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) continues to emit light in the character appearance light emission mode.

[0373] When the high-brightness performance WO22 ends and the reach advance announcement performance image 171 including the dialogue character string becomes completely visible (FIG. 28(e)), a predetermined reach advance announcement voice is output as a dialogue sound (dialogue output performance). This reach advance announcement voice corresponds to the dialogue character string displayed on the screen, and here "It's reach" is output. However, the present invention is not limited to this, and the configuration may be such that the dialogue output performance of "It's reach" is executed from during the execution of the high-brightness performance WO22, or the dialogue output performance is executed from the timing when the dialogue character string appears before the execution of the high-brightness performance WO22. Further, during the dialogue output performance, the output of BGM2 related to the reach advance announcement performance continues, and at least part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) emits light in a dialogue output light emission mode (here, blue) corresponding to the character color of the dialogue character string (that is, the reliability information).

[0374] When the speech output performance ends, an end-time performance (specific image end-time performance) for ending the display of the ready-to-win preview performance image 171 related to the ready-to-win preview performance and switching to the symbol variation screen is executed (Fig. 28(f)). During this end-time performance, at least a part of the performance lamp L (here, both the frame-side lamp La and the board-side lamp Lb) emits light in an end-time light emission mode (e.g., orange) different from the previous speech output light emission mode (here, blue) and the character appearance light emission mode (here, the cyclic change mode of blue and white), but this end-time light emission mode may be configured to be the same as either the speech output light emission mode or the character appearance light emission mode. When the symbol variation screen is started after the end-time performance (Fig. 28(g)), a symbol stop sound is output as a sound effect in synchronization with the stop of the decorative symbols 164a to 164c. The reach preview performance shown in Fig. 28 has a different jackpot reliability from the step-up preview performance shown in Fig. 23, and here the latter has a higher jackpot reliability than the former (Fig. 20).

[0375] Furthermore, the high-brightness effect (High-Brightness Effect A, Part 2) WO22 may be configured to have a different execution time than the high-brightness effect (High-Brightness Effect A, Part 1) WO21, or it may be configured to have the same execution time. Also, the transparency of the high-brightness image may be different for the two, or it may be configured to have the same transparency. Also, the display range of the high-brightness image may be different for the two, or it may be the same. In addition, since there is no display of text when the high-brightness effect (High-Brightness Effect A, Part 1) WO21 is running, and there is a display of text when the high-brightness effect (High-Brightness Effect A, Part 2) WO22 is running, it is sufficient for the high-brightness image to be displayed in such a way that the text is at least difficult to see. For example, the transparency of the high-brightness image may be different for the character (kappa) part and the text part. Furthermore, the high-brightness image may be executed so that it does not overlap or only partially overlaps the character (kappa) portion, while it may be executed so that it overlaps the text portion. Also, when the character (kappa) and / or text are displayed dynamically, it is desirable that they are always displayed dynamically within the display range of the high-brightness image. However, this is not limited to this, and the dynamic display of the character (kappa) and / or text may be configured so that there are times when they overlap and times when they do not overlap the display range of the high-brightness image. This makes it possible to change the visibility of the character (kappa) and / or text during dynamic display and improve the effect of the performance. In addition, the dynamic pattern when dynamically displaying the character (kappa) and / or text during the execution of the high-brightness effect may be configured to be different from the dynamic pattern when dynamically displaying the character (kappa) and / or text after the execution of the high-brightness effect has ended.

[0376] Next, with respect to the reach notice performance shown in FIG. 28 as described above, the performance period centered on high-brightness performances WO21 and WO22 will be described in more detail. FIGS. 29 to 31 show changes in the display screen and light-emitting means at even smaller time intervals than in FIG. 28 for the period from FIG. 28(b) to (g), that is, the period from the start time of the high-brightness performance WO21 until the reach notice performance ends and the screen transitions to the variation screen of the decorative symbols 164. The 20-frame display images shown in FIGS. 29 to 31 are extracted at a constant pitch from all frames in the period of FIGS. 28(b) to (g). Accordingly, in FIGS. 29 to 31, the time intervals between adjacent frames are all the same, which is A milliseconds, the same as in FIGS. 24 to 26 in the step-up notice performance.

[0377] First, details of the high-brightness performance WO21 will be described. In the high-brightness performance WO21 shown in FIGS. 29(a) to (f), at the start thereof, a high-brightness image 170c is displayed on the front side of the reach notice performance image 171 and on the rear side of the mini symbols 165, the hold pedestal image 168, and the hold images X1 to X4 and Y1 to Y4 on the front side thereof (FIG. 29(a)), and the transmittance of the high-brightness image 170c gradually changes and finally disappears (FIG. 29(f)).

[0378] Here, the high-brightness image 170c is displayed in a range (size) that covers the entire reach advance notification performance image 171, the transmittance is uniform within the display range, the display range does not change with the passage of time, and the transmittance is configured to change with the passage of time (transmittance change processing, transmittance change performance). The transmittance of the high-brightness image 170c is set to the minimum (25% in this case) at the start of display (Fig. 29(a)), and is configured to gradually increase (rise) at a constant change rate, for example, as time elapses (first display pattern). That is, the high-brightness performance WO21 is composed of a low transmittance change performance that changes the transmittance of the high-brightness image 170c in the decreasing direction, and a high transmittance change performance that changes the transmittance of the high-brightness image 170c in the increasing direction, and the execution time of the latter (Figs. 29(a) to (f)) is longer than that of the former (Fig. 29(a)). Note that in the high-brightness image 170c, the minimum transmittance is greater than 0% (25% in this case), and the reach advance notification performance image 171 is slightly visible even at the start of display (Fig. 29(a)) when the minimum transmittance is reached. The transmittance of the high-brightness image 170c at the start of display may be set to 0%, so that the display content on the rear side at the start of display of the high-brightness image 170c cannot be visually recognized.

[0379] Of course, the high-brightness image 170c may be set to a display range (size) where the coverage of the reach advance notification performance image 171 is less than 100%, or the transmittance within the display range may be non-uniform. Further, the display range (size) may be changed with the passage of time while changing the transmittance or without changing the transmittance. Further, the minimum transmittance of the high-brightness image 170c may be set to 0%. Further, the execution time of the high transmittance change performance may be shorter than that of the low transmittance change performance, or the execution times of the two may be substantially the same.

[0380] Also, at a predetermined time point during the high-brightness performance WO21, for example, at the start thereof (Fig. 29(a)), the performance scenario is switched, whereby the reach advance notice performance image 171 on the rear side of the high-brightness image 170c is switched from the image of the preceding first-half reach advance notice performance RC1 to the image of the subsequent second-half reach advance notice performance RC2. That is, the high-brightness performance WO21 is an example of a high-brightness performance at the time of image change that can be executed when performing an image change process for changing from the first image to the second image, and is an example of a high-brightness performance at the time of scenario switching that is executed at the timing of switching the performance scenario. As a result, after the start of the high-brightness performance WO21, as the transmittance of the high-brightness image 170c gradually increases, the visibility of the reach advance notice performance image 171 improves, and when the high-brightness image 170c eventually disappears (Fig. 29(f)), the entire reach advance notice performance image 171 (excluding the portion hidden behind the mini symbols 165 and the like) becomes completely visible.

[0381] During the execution of the high-brightness performance WO21, the mini symbols 165 have made one full cycle from the position between "3·5·7" and "4·6·8" (Fig. 29(a)) to reach "8·2·4" (Fig. 29(f)). That is, the execution time of the high-brightness performance WO21 (Fig. 29(a) to (f)) is longer than the period in which the mini symbols 165 complete one full cycle.

[0382] Further, during the high-brightness performance WO21, the performance lamp L emits light in a high-brightness mid-performance light emission mode. The high-brightness mid-performance light emission mode is configured such that up to a predetermined time point during the high-brightness performance WO21 (Fig. 29(a) to (b)), the light is of a predetermined color (here, white), and after that (Fig. 29(c) to (e)), the light changes to a specific color (here, blue).

[0383] After the high-brightness performance WO21 ends and the reach preview performance image 171 becomes completely visible (Fig. 29(f)), a text information display start performance (Fig. 29(f) to (h)) is performed at the same time or at a predetermined timing thereafter. In this text information display start performance, the dialogue character string (text information) of "It's reach!" appears in front of the character image or the like with a first dynamic display performance (first dynamic display period). In this first dynamic display performance, the dialogue character string moves toward a predetermined display position at a first change speed (here, a movement accompanied by rotation and reduction change). Through this first dynamic display performance accompanied by rotation and reduction change, the player perceives that the dialogue character string is moving toward the back of the screen while, for example, rotating clockwise. Note that although this dialogue character string of "It's reach!" is displayed in "blue" (Fig. 27(a)), the display mode (display color and shape) of the dialogue character string does not change during the first dynamic display performance (the specific display processing for displaying the text information in a specific display mode is not executed).

[0384] When the dialogue character string reaches the predetermined display position through the first dynamic display performance (Fig. 29(h)), by displaying the high-brightness image 170d, the high-brightness performance WO22 (Fig. 29(h) to Fig. 30(l)) that reduces the visibility of the image behind the high-brightness image 170d (here, the reach preview performance image 171) is executed. Note that unlike the high-brightness performance WO21, this high-brightness performance WO22 is executed when the performance scenario is not switched, that is, at the timing when the reach preview performance image 171 is not changed. As such, the high-brightness performance WO22 is an example of a high-brightness performance at the time of non-image change that can be executed when predetermined image change (image change) is not performed, and is an example of a high-brightness performance at the time of non-scenario switching that is executed at a timing when the performance scenario is not switched.

[0385] In this high-brightness performance WO22, similar to the high-brightness performance WO21, a high-brightness image 170d appears on the front side of the reach advance notice performance image 171 and behind the mini symbols 165, the hold base image 168, and the hold images X1 to X4 and Y1 to Y4 on the front side thereof, and then disappears after a while. The change (display pattern) of the high-brightness image 170d is different from that of the high-brightness image 170b in the high-brightness performance WO21. Note that the configuration may be such that a high-brightness image appears on the front side of the hold base image 168 and the hold images X1 to X4 and Y1 to Y4 on the front side thereof, and this also applies to other performances.

[0386] That is, the high-brightness image 170d is displayed in a range (size) that covers the entire reach advance notice performance image 171, the transmittance is uniform within the display range, the display range does not change over time, and the transmittance changes over time (transmittance change processing, transmittance change performance), which is common to the high-brightness image 170c. However, the transmittance thereof gradually decreases over time to reach the minimum value (40% here) at a predetermined point in time (Fig.29(h) to Fig.30(j)), and then gradually increases over time (Fig.30(j) to (l)), which is different (second display pattern). As described above, the high-brightness performance WO22 includes a low transmittance change performance that changes the transmittance of the high-brightness image 170d in the decreasing direction, and a high transmittance change performance that changes the transmittance of the high-brightness image 170d in the increasing direction, and the execution time of the former (Fig.29(h) to Fig.30(j)) and the latter (Fig.30(j) to (l)) is substantially the same. Of course, the execution time of the high transmittance change performance may be longer than that of the low transmittance change performance, or vice versa. In the high-brightness image 170d, the minimum transmittance is greater than 0% (40% here), and the reach advance notice performance image 171 is visible even at the predetermined point in time (Fig.30(j)) when the minimum transmittance is reached.

[0387] During the execution of the high-brightness effect WO22, the mini symbol 165 cycles from "5-7-1" (Figure 29(h)) to "7-1-3" (Figure 30(l)). In other words, the execution time of the high-brightness effect WO22 (Figure 29(h) to Figure 30(l)) is longer than the time it takes for the mini symbol 165 to cycle. Furthermore, the execution time of the high-transparency change effect may be longer than that of the low-transparency change effect, or vice versa.

[0388] Furthermore, during this high-brightness effect WO22, an arrival emphasis operation is performed to highlight that the dialogue string has reached a predetermined display position; in this case, the dialogue string expands and contracts (enlarges and shrinks) (Figures 29(h) to 30(l)). The type of this arrival emphasis operation is arbitrary and can be anything, such as a bouncing motion of the dialogue string or a deformation operation other than enlargement and shrinking. Also, the high-brightness effect WO22 may be configured to be executed when the arrival emphasis operation of the dialogue string is completed. In other words, the high-brightness effect WO22 may be configured not to perform any deformation operations on the dialogue string. Alternatively, the high-brightness effect WO22 may be configured to perform only minor deformation operations on the dialogue string that are smaller than the arrival emphasis operation performed before the execution of the high-brightness effect WO22.

[0389] Furthermore, during the period from the start of the text information display animation to the high-brightness animation WO22, the animation lamp L illuminates in the text appearance illumination pattern. The text appearance illumination pattern is a cyclical change pattern that changes cyclically through multiple colors (for example, blue and white), including the color of the text string of dialogue displayed on the screen (in this case, blue). The illumination color changes as follows: white (Figure 29(f)~(g)) → blue (Figure 29(h)~(i)) → white (Figure 30(j)~(k)).

[0390] When the high-brightness performance WO22 ends and the entire ready-to-win preview performance image 171 including the dialogue character string becomes visible (FIG. 30(l)), a dialogue output performance is executed, and the dialogue sound "It's a ready-to-win state" (ready-to-win preview voice) corresponding to the dialogue character string (text information) displayed on the screen is output. During this dialogue output performance (the second dynamic display period), a second dynamic display performance is performed on the dialogue character string (FIG. 30(l) to (p)). In this second dynamic display performance, the dialogue character string is, for example, slowly displayed in a reduced size at a second change speed (here, slower than the first change speed) that is different from the change speed at the time of the first dynamic display performance (the first change speed). This reduced display makes the player recognize that the dialogue character string is moving toward the depth of the screen.

[0391] During the second dynamic display period in which the second dynamic display performance is performed on the dialogue character string, the mini symbols 165 have completed one cycle from "7·1·3" (FIG. 30(l)) and reached "1·3·5" (FIG. 30(p)). That is, the second dynamic display period (FIG. 30(l) to (p)) is longer than the period in which the mini symbols 165 complete one cycle, and is also longer than the first dynamic display period (FIG. 29(f) to (h)). In the example of FIG. 29, the first dynamic display period (FIG. 29(f) to (h)) is shorter than the time required for the mini symbols to complete one cycle.

[0392] Furthermore, during this second dynamic display effect (Figures 30(l)~(p)), a display mode change process (a specific display process that displays text information in a specific display mode) is performed to change the display mode (in this case, the display color) of the dialogue string. This display mode change process is performed within the outline of the dialogue string (text information), and for example, the display color of the text corresponding to the dialogue sound being output temporarily changes (for example, from blue to white). As a result, the white portion is perceived as moving, for example, from left to right, over the blue-displayed string "Reach!". When performing a predetermined change effect within the outline of the dialogue string in this way, the dialogue string may be configured to be displayed dynamically, or the effect image may be configured to be displayed while the string is stationary. When outputting this dialogue sound, it is desirable to have the character image perform a so-called lip-syncing action (speaking action). In addition, it is desirable that the display mode change process (a specific display process that displays text information in a specific display mode) that moves the white portion over the dialogue string be performed in response to the output of the dialogue sound. By synchronizing the timing of the dialogue sound output with the change (movement) of the display color on the dialogue string in this way, it becomes possible to more clearly express the relationship between the dialogue sound output and the dialogue text being output, even if there is no lip-syncing action (speech action). The lip-syncing action may be performed while the high-brightness image is being displayed, or it may be configured to be performed after the display of the high-brightness image has finished. When the lip-syncing action is performed while the high-brightness image is being displayed, it is desirable to configure it so that the lip-syncing action is performed at least while the dialogue string is being displayed or after the first dynamic display of the dialogue string has finished, but it is not limited to this, and it may also be configured to perform the lip-syncing action from the first dynamic display.

[0393] Furthermore, during the dialogue output animation, the animation lamp L illuminates in a way that corresponds to the color of the dialogue string (blue in this case), i.e., it illuminates in blue (Figure 30(l)~(p)).

[0394] When the dialogue output performance (Figs. 30(l) to 30(p)) ends (i.e., after the second dynamic display period), an end-time performance (specific image end-time performance, text information display end performance) for terminating the display of the reach preview performance image 171 related to the reach preview performance and switching to the symbol variation screen is performed (Figs. 30(q) to 31(t)). In this end-time performance, a masking image 172 that masks the reach preview performance image 171 is displayed on the front side of the reach preview performance image 171, and the configuration is such that the symbol variation screen appears when the display of the masking image 172 is terminated. In the end-time performance of the present embodiment, the masking image 172 is composed of a draw curtain and a character that pulls the curtain, the character closes the draw curtain to mask the reach preview performance image 171 (Figs. 30(q) to 30(r)), and then the character opens the draw curtain, whereby the variation screen of the decorative symbols 164 (excluding the portions hidden behind the mini symbols 165 and the like) gradually becomes visible (Fig. 30(r) → Fig. 31(t)). During the execution of this end-time performance, the display mode (display color and shape) of the dialogue character string does not change (the specific display processing for displaying the character information in the specific display mode is not executed). Also, although a white image is adopted as the masking image 172 here, the present invention is not limited to this, and for example, a display color suggesting the reliability may be used, or other colors may be used. Further, the transmittance of the masking image 172 may be greater than 0%. When the masking image 172 is set to other colors, it is desirable to adopt an image with a color or pattern that is at least different from the high-brightness image. The masking image 172 may also be configured to be displayed in a region including the front side of the hold base image 168 and the hold images X1 to X4, Y1 to Y4 so as to overlap therewith. The display period of the masking image 172 may be configured to be different from the display period of the high-brightness image, or may be the same period. When the periods are different, the display period of the masking image 172 may be configured to be longer than the display period of the high-brightness image, or conversely, may be configured to be shorter.

[0395] Further, during the end-time performance, the performance lamp L emits light in an end-time light emission mode, for example, in orange (Figs. 30(q) to 31(s)).

[0396] It should be noted that in the reach announcement effect, when comparing the execution times of the high-brightness effects WO21, WO22 and the end-time effect, the high-brightness effect WO21 (Figs. 29(a) to (f)) is about 5A milliseconds, the high-brightness effect WO22 (Figs. 29(h) to 30(l)) is about 4A milliseconds, and the end-time effect is about 4A milliseconds. However, the execution time of the end-time effect may be shorter than the execution time of the high-brightness effect WO22, or conversely, may be longer.

[0397] As described above, in the reach announcement effect, it is possible to execute the high-brightness effect (first high-brightness effect) WO21 that displays the high-brightness image (first high-brightness image) 170c, and the high-brightness effect (second high-brightness effect) WO22 that displays the high-brightness image (second high-brightness image) 170d. The high-brightness effect WO21 is executed at the first timing when the scene change (switching from the first scene image to the second scene image) accompanying the transition from the first-half reach announcement effect RC1 to the second-half reach announcement effect RC2 is performed, and the high-brightness effect WO22 is executed at the subsequent second timing. It should be noted that at the first timing when the high-brightness effect WO21 is performed, the dialogue character string (character image) having reliability information related to the big win is not yet displayed on the screen, and is displayed at the subsequent second timing.

[0398] Further, in the reach announcement effect, the display of the character image having the big win reliability information is started before the high-brightness effect WO22, and when the display of the character image ends, the end-time effect (specific image end-time effect) can be executed (Figs. 30(q) to 31(t)). Also, during the high-brightness effect WO22, the first light emission effect is executed, in which the effect lamp (light emitting means) L is caused to emit light in the character appearance light emission mode (first light emission mode) corresponding to the reliability information (for example, display color) in the character image. During the end-time effect (specific image end-time effect), the second light emission effect is executed, in which the effect lamp (light emitting means) L is caused to emit light in an end-time light emission mode (second light emission mode) different from the character appearance light emission mode (first light emission mode).

[0399] Further, in the reach preview performance, it is possible to execute a high-luminance performance (high-luminance performance upon image change) WO21 that can be executed when an image change process for switching from the image of the first half reach preview performance RC1 (first image) to the image of the second half reach preview performance RC2 (second image) is performed, and a high-luminance performance (high-luminance performance upon no image change) WO22 that can be executed when the image change process is not performed, and the minimum transmittance (transmittance performance) of the high-luminance image is made different between the high-luminance performance WO21 and the high-luminance performance WO22. Note that although the minimum transmittance is made different as an example of the transmittance performance of the high-luminance image here, other transmittance performances, for example, the range (size) of the high-luminance image, the transmittance distribution, and the like may be made different. Further, the image change process is not limited to switching from the image of the first half reach preview performance RC1 (first image) to the image of the second half reach preview performance RC2 (second image), and may be any process that switches from a predetermined first image to a predetermined second image. That is, an image that is displayed before the execution of the high-luminance performance but is not displayed after the execution corresponds to the first image, and an image that is not displayed before the execution of the high-luminance performance but is displayed after the execution corresponds to the second image. In this manner, if there are images (the first image and the second image) whose display is switched before and after the high-luminance performance, it may be determined that the image change process is being executed.

[0400] Additionally, the reach advance notification performance is an example of a character information display performance for displaying (here, dynamically displaying) character information, and is capable of executing a character information display start performance (a first specific performance performed when starting the display of character information) that starts the display of character information, and an end-time performance (a second specific performance performed when ending the display of character information) that ends the display of character information. After execution of the character information display start performance (during the first specific performance), a display mode change process that changes the display mode of the character information (a specific display process that displays the character information in a specific display mode) (Figs. 30(l) to (p)) is executed, and the configuration is such that the display mode change process (specific display process) is not executed during execution of the end-time performance (second specific performance). However, the present invention is not limited to this, and the configuration may be such that the display mode change process (specific display process) is also executed during execution of the end-time performance (second specific performance). In this case, the display mode change performance started after execution of the character information display start performance (during the first specific performance) will be continuously executed even during execution of the end-time performance (second specific performance). Further, the configuration may be such that another display mode change performance different from the display mode change performance started after execution of the character information display start performance (during the first specific performance) is executed during execution of the end-time performance (second specific performance).

[0401] Further, in the ready-for-win notice performance, there are a high-luminance performance executed at the timing of switching the performance scenario (high-luminance performance at scenario switching) WO21, and a high-luminance performance executed at the timing of not switching the performance scenario (high-luminance performance at non-scenario switching) WO22. The high-luminance performance WO21 is configured to display a high-luminance image 170c in a first display pattern, and the high-luminance performance WO22 is configured to display a high-luminance image 170d in a second display pattern different from the first display pattern. The execution time of the high-luminance performance WO21 (Fig. 29(a) to (f)) is longer than that of the high-luminance performance WO22 (Fig. 29(h) to Fig. 30(l)). Further, as described above, the minimum transmittance (transmittance performance) of the high-luminance image differs between the high-luminance performance WO21 and the high-luminance performance WO22, and the minimum transmittance of the high-luminance image 170d of the high-luminance performance WO22 is larger than that of the high-luminance image 170c of the high-luminance performance WO21. The minimum transmittance of the high-luminance image 170d of the high-luminance performance WO22 may be smaller than that of the high-luminance image 170c of the high-luminance performance WO21, or may be substantially the same. Further, other transmittance performances, for example, the maximum range (size) of the high-luminance image, the transmittance distribution, and the like may be made different between the hig...

Claims

[Claim 1] It is possible to perform a specific animation that outputs confidence level suggestion information indicating the likelihood of a predetermined event occurring. The confidence suggestion information comprises textual information and audio information corresponding to the textual information. In gaming machines, The aforementioned specific performance is, A first specific performance includes displaying the aforementioned text information, outputting audio corresponding to the text information, and displaying an image of a speech action corresponding to the audio, A second specific performance includes displaying the aforementioned text information, outputting audio corresponding to the text information, and not displaying an image of a speech action corresponding to the audio, In the first specific performance described above, the audio output period does not exceed the display period of the text information. In the second specific performance described above, it is possible to execute a first pattern in which the audio output period does not extend beyond the display period of the text information, and a second pattern in which the audio output period extends beyond the display period of the text information. The reliability differs between the first pattern and the second pattern. A gaming machine characterized by the following features.

Images