Manufacturing method for packaging substrates

Abstract

To provide a method for manufacturing a packaging substrate that suppresses misalignment of rewiring layers and provides the packaging substrate, etc. with excellent electrical reliability.SOLUTION: A method includes a preparation step for preparing a base substrate including a core layer 10 that includes a top surface and in which a through hole in the thickness direction is formed, a via insulating part formation step for providing a via-plugged substrate by forming the via insulating part 30 in the through hole, and a fabrication step of fabricating a packaging substrate 300 from the via-plugged substrate.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The embodiment relates to a method of manufacturing a packaging substrate.

Background Art

[0002] In manufacturing electronic components, implementing a circuit on a semiconductor wafer is referred to as a front-end (FE) process, and assembling the wafer into a state usable in an actual product is referred to as a back-end (BE) process, and this back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products include semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nanometer line widths, more than ten million cells, high-speed operation, and high heat dissipation, but relatively, the technology to perfectly package these has not been supported. Therefore, the electrical performance of a semiconductor may sometimes be determined by the packaging technology and the electrical connections resulting therefrom, rather than by the performance of the semiconductor technology itself.

[0004] Recently, research on applying ceramic materials to high-end packaging substrates is underway. By forming through holes in a ceramic material substrate and applying a conductive material to these through holes, the wiring length between the element and the motherboard is shortened, and excellent electrical characteristics can be obtained.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] The objective of this embodiment is to provide a packaging substrate with excellent electrical reliability by suppressing misalignment in the redistribution layer. [Means for solving the problem]

[0007] A method for manufacturing a packaging substrate according to one embodiment of this specification includes a preparation step of preparing a base substrate including a core layer having a top surface and through holes formed in the thickness direction; a via-insulating portion forming step of forming via insulating portions in the through holes to provide a via-plugged substrate; and a manufacturing step of manufacturing a packaging substrate from the via-plugged substrate.

[0008] The ratio of the thickness of the core layer to the diameter of the through hole, as observed from the upper surface of the core layer, can be between 4 and 12.

[0009] The core layer may be a glass core.

[0010] The core layer may include two or more of the through holes.

[0011] The diameter of the through-hole may be between 40 μm and 200 μm.

[0012] The pitch of the through holes can be between 50 μm and 1500 μm.

[0013] The via insulation forming step may include a filling step of filling the through-holes with a via insulation manufacturing composition by screen printing, and a curing step of curing the injected via insulation manufacturing composition to form the via insulation.

[0014] The viscosity of the via insulation composition can be 100 dPa*s to 500 dPa*s.

[0015] The via insulation formation step may further include a plasma decamming process of the via-plugged substrate.

[0016] The via insulating part may include one end located on the upper surface side of the core layer.

[0017] The via-plugged substrate may have a trench structure in which one end of the via insulating part is positioned lower than the upper surface of the core layer.

[0018] In the via-plugged substrate, the depth of the trench structure may be 1 μm to 15 μm.

[0019] The packaging substrate may include the core layer in which the through-hole is formed in the thickness direction, and the via insulating part formed in the through-hole.

[0020] The via insulating part may include a filler.

[0021] The average particle diameter of the filler may be 0.1 μm or more and less than 15 μm.

[0022] The elongation percentage of the via insulating part may be 0.1% to 5%.

[0023] The composition for manufacturing a via insulating part may include an epoxy resin, a curing agent and a filler.

[0024] The packaging substrate may include the core layer in which the through-hole is formed in the thickness direction, the via insulating part formed in the through-hole, and a first insulating layer formed such that at least a part thereof is in contact with the upper surface of the core layer.

[0025] The dimple depth of the first insulating layer may be 15 μm or less. Advantageous Effects of the Invention

[0026] The method for manufacturing a packaging substrate according to the embodiment can suppress misalignment of the redistribution layer and provide a packaging substrate with excellent electrical reliability. Brief Description of the Drawings

[0027] [Figure 1A] This is a cross-sectional view illustrating a core layer applied to one embodiment of this specification. [Figure 1B] This is a cross-sectional view illustrating a core layer applicable to other embodiments of this specification. [Figure 2A] This is a cross-sectional view illustrating a filling process applied to one embodiment of this specification. [Figure 2B] This is a cross-sectional view illustrating a filling process applied to one embodiment of this specification. [Figure 3A] This is a conceptual diagram illustrating a via-plugged substrate that has undergone a discam process according to one embodiment of this specification. [Figure 3B] This is a conceptual diagram illustrating a via-plugged substrate that has undergone a descam process according to other embodiments of this specification. [Figure 4] This is a cross-sectional view illustrating a packaging substrate manufactured according to one embodiment of this specification. [Figure 5A] This is a surface profile graph of the through-holes contained in the upper surface of the packaging substrate in the embodiment. [Figure 5B] This is a surface profile graph of the through-holes contained in the upper surface of the packaging substrate in the embodiment. [Figure 5C] This is a surface profile graph of the through-holes contained in the upper surface of the packaging substrate in the embodiment. [Figure 6A] This is a surface profile graph of the through-holes contained in the lower surface of the packaging substrate in the embodiment. [Figure 6B] This is a surface profile graph of the through-holes contained in the lower surface of the packaging substrate in the embodiment. [Figure 6C] This is a surface profile graph of the through-holes contained in the lower surface of the packaging substrate in the embodiment. [Figure 7] This is a TEM (Transmission Electron Microscope) image of a packaging substrate in an embodiment where an insulating layer has been formed. [Best Mode for Carrying Out the Invention]

[0028] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. However, the present invention can be realized in a variety of different forms and is not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0029] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0030] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0031] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0032] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0033] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0034] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0035] In this specification, the form, relative size, angles, etc., of each component in the drawings are illustrative and may be exaggerated for illustrative purposes, and the rights shall not be construed as being limited to the drawings.

[0036] In this specification, "adjacent to A and B" means that A and B are located touching each other, or that A and B are not touching but are located close to each other. In this specification, the expression "adjacent to A and B" is not construed to mean that A and B are located touching each other unless otherwise specified.

[0037] In this specification, unless otherwise specified, a fine line means a line with a width of 5 μm or less, and more specifically, a line with a width of 1 to 4 μm or less.

[0038] To optimize the signal transmission path, a core layer with through-holes formed in the thickness direction can be introduced into the packaging substrate. However, when a redistribution layer is materialized on the core layer, defects may occur during the process in which the insulating resin is embedded in the internal space of the through-holes, which can induce misalignment of the redistribution layer, such as a part of the insulating layer placed on the core layer becoming indented or wrinkled in a wavy pattern.

[0039] The inventors of the embodiment experimentally confirmed that by applying technical features such as forming via insulation in through holes, misalignment of the redistribution layer can be suppressed, and a packaging substrate with excellent electrical reliability can be manufactured, thus completing the embodiment.

[0040] The following are some concrete examples.

[0041] Preparation Steps Figure 1A is a cross-sectional view illustrating a core layer applied to one embodiment of this specification. An example will be described with reference to Figure 1A.

[0042] The manufacturing method for the packaging substrate in the embodiment includes a preparation step of preparing a base substrate 100 which includes a top surface 12 and a core layer 10 in which through holes 11 are formed in the thickness direction.

[0043] The core layer 10 may have the shape of a substrate. The core layer 10 is not limited as long as it is a substrate that can be used as an electronic component.

[0044] The core layer 10 may be any one of the following: a glass core, a ceramic core, a glass fiber reinforced core, or an organic core. In particular, the core layer 10 may be a glass core. A glass core is advantageous in that it can embody fine patterns and reduce the possibility of parasitic elements occurring.

[0045] The glass core may, for example, be alkali borosilicate glass, alkali-free borosilicate glass, or alkali-free alkaline earth borosilicate glass. The glass core can be a glass substrate for electronic devices, and for example, one manufactured by Schott, AGC, Corning, etc. may be used, but is not limited to these.

[0046] The surface of the core layer 10 may include an upper surface 12 and side surfaces connected to the upper surface 12 and formed in the thickness direction of the core layer 10. The surface of the core layer 10 may also include a lower surface facing the upper surface 12.

[0047] The statement that the side surface is formed in the thickness direction of the core layer 10 is interpreted to mean not only that the side surface is perpendicular to the upper surface 12 of the core layer 10, but also that at least a portion of the side surface forms an angle (inclination angle) other than 90° with the upper surface 12.

[0048] The aforementioned side surface may be flat or curved.

[0049] The core layer 10 may have through holes 11 formed in the thickness direction.

[0050] The through-hole 11 may have a substantially uniform inner diameter in the thickness direction of the core layer 10. The through-hole 11 may have an inner diameter that varies in the thickness direction of the core layer 10.

[0051] The cross-section of the through-hole 11 may be rectangular. The cross-section of the through-hole 11 may also be hourglass-shaped, triangular, trapezoidal, or other shapes. The cross-section of the through-hole 11 refers to the cross-section in the thickness direction of the core layer 10.

[0052] In the preparation step, a core layer 10 with through holes 11 can be obtained and prepared, or a core layer 10 can be prepared by forming through holes 11 in a substrate that does not have through holes.

[0053] In particular, the method for preparing the core layer 10 by forming through holes 11 in a glass substrate is as follows.

[0054] Defects can be formed at the locations where through-holes are located on the surface of a glass substrate. Methods such as mechanical etching and laser irradiation may be used to form the defects.

[0055] After the defect is formed, a through-hole 11 can be formed by physical or chemical etching. When chemical etching is applied, wet etching can be performed using an etching solution. The etching solution is not limited as long as it is generally applicable to etching glass substrates. For example, the etching solution may be a sulfuric acid solution, a nitric acid solution, a hydrofluoric acid solution, etc.

[0056] During the etching process, the remaining surface of the glass substrate, excluding the area where the defect is formed, may be masked, or the etching may be performed without masking.

[0057] A core layer 10 can be formed in which a through hole 11 is formed by creating a defect at one point on the upper surface of the glass substrate, creating a defect at another point on the lower surface of the glass substrate opposite to the first point, and then etching in directions opposite to each other.

[0058] The ratio of the thickness of the core layer 10 to the diameter of the through hole 11, as observed from the upper surface 12 of the core layer, can be 4 to 12.

[0059] In the via insulation forming step, the via insulation manufacturing composition can be filled into the through-hole 11 from the upper surface 12 side of the core layer. At this time, the composition may not be filled uniformly throughout the area to be filled in the through-hole 11, and defects such as voids may be formed in the manufactured via insulation.

[0060] In one example, by controlling the ratio of the thickness of the core layer 10 to the diameter of the through hole 11 within a preset range, the via insulation manufacturing composition can be injected into the area to be filled within the through hole 11 with virtually no empty space.

[0061] The ratio of the thickness of the core layer 10 to the diameter of the through hole 11, as observed from the upper surface 12 of the core layer, can be 4 to 12. The ratio may be 5 or more. The ratio may be 7 or more. The ratio may be 11 or less. In such cases, the formation of voids within the via insulation can be substantially suppressed, which can help to realize a packaging substrate with improved integration.

[0062] The core layer 10 may contain two or more through holes 11. In the case of a glass core layer 10 with multiple through holes, the more densely packed the through holes 11 with fine diameters are within the core layer 10, the more susceptible it may be to external impact. When manufacturing a packaging substrate from a core layer 10 having such a structure, physical damage may occur to the core layer 10 due to external forces acting on it during the manufacturing process of the packaging substrate, particularly during the process of injecting the via insulation composition into the through holes 11 via screen printing.

[0063] In practice, the through-holes 11 can be fitted with adjusted diameters and pitches. Through this, wiring penetrating the core layer 10 can be formed on the packaging substrate at a high density, thereby suppressing the occurrence of cracks in the core layer 10 that may occur during the manufacturing process.

[0064] If the through-hole 11 has a diameter that varies in the thickness direction of the core layer 10, the average value of the diameters is taken as the diameter of the through-hole 11.

[0065] The diameter of the through-hole 11 may be 40 μm to 200 μm. The diameter may be 50 μm or more. The diameter may be 70 μm or more. The diameter may be 170 μm or less. The diameter may be 150 μm or less. The diameter may be 130 μm or less.

[0066] The pitch of the through-holes 11 may be 50 μm to 1500 μm. The pitch may be 100 μm or more. The pitch may be 200 μm or more. The pitch may be 300 μm or more. The pitch may be 500 μm or more. The pitch may be 1200 μm or less. The pitch may be 1000 μm or less.

[0067] In such cases, even if a hard material and a complex structure are applied to the core layer 10, the core layer 10 may not be easily damaged during the manufacturing process.

[0068] Figure 1B is a cross-sectional view illustrating a core layer applicable to other embodiments of this specification. Implemented examples will be described with reference to Figure 1B.

[0069] The core layer 10 includes the upper surface 12 and has through holes 11 formed in the thickness direction. The specific configuration of the core layer 10 is the same as that described in Figure 1A above. The differences will be explained below.

[0070] The core layer 10 may include via inner diameter surfaces 13 surrounding the through holes 11. An electrical conductive layer 41 may be formed on the via inner diameter surfaces 13.

[0071] The via inner diameter surface 13 is the surface of the core layer 10 formed on the inside of the core layer 10. The electrical conductive layer 41 may be formed so that at least a portion of it is in contact with the via inner diameter surface 13, or it may be placed on the via inner diameter surface 13 with other components arranged between the electrical conductive layer 41 and the via inner diameter surface 13.

[0072] The electrically conductive layer 41 may include a seed layer (or primer layer) (not shown) disposed on the via inner diameter surface 13, and a conductive layer (not shown) disposed on the seed layer. The seed layer (or primer layer) may help to ensure that the electrically conductive layer 41 can be stably fixed to the via inner diameter surface 13, and may act as a seed in the process of forming the conductive layer via plating.

[0073] The electrical conductive layer 41 may be formed using a dry method or a wet method.

[0074] The dry method is a method in which a seed layer is formed by sputtering in the region where the electrical conductive layer 41 is to be placed, and the electrical conductive layer 41 is formed by plating in the region where the seed layer has been formed. When forming the seed layer, metals such as titanium, chromium, and nickel may be sputtered, or the above metals and copper may be applied together and sputtered. Through sputtering, an anchoring effect occurs in which the surface of the glass core or insulating layer interacts with the metal particles, which can improve the adhesion of the electrical conductive layer 41.

[0075] The wet method is a method in which a primer is applied to the area where the electrical conductive layer 41 needs to be formed, and then metal plating is performed. The primer may include a compound having a functional group such as an amine. Depending on the desired degree of adhesion, the primer may contain both a compound having a functional group such as an amine and a silane coupling agent. When a silane coupling agent is used, the surface to be primed can be pretreated with the silane coupling agent, and then a compound having an amine group can be applied to the pretreated area to form the primer layer.

[0076] After forming a seed layer or primer layer, a conductive layer can be formed via metal plating to provide an electrically conductive layer 41. Copper plating may be applied during the formation of the conductive layer, but is not limited to this. Before metal plating, parts of the seed layer or primer layer where the formation of the electrically conductive layer 41 is unnecessary can be deactivated, or parts where the formation of the electrically conductive layer 41 is necessary can be activated before plating. The activation or deactivation treatment method may include light irradiation treatment using a laser of a specific wavelength, chemical treatment, etc. However, after applying metal plating without applying an activation or deactivation treatment, the electrically conductive layer 41 can be etched and patterned according to a pre-designed shape.

[0077] As the material for the seed layer, the material applied to the conductive layer and a different material can be applied together. For example, when copper is applied to the conductive layer, a metal such as titanium, chromium, or nickel can be applied to the lower part of the seed layer, and copper can be applied to the upper part of the seed layer.

[0078] The material of the conductive layer is not limited as long as it is conductive. The material of the conductive layer may be any one selected from the group consisting of copper, nickel, aluminum, gold, silver, and combinations thereof. The material of the conductive layer may be copper.

[0079] The thickness of the electrical conductive layer 41 placed in the through-hole 11 can be 0.01 μm to 1 μm. The thickness may be 0.05 μm. The thickness may be 0.1 μm or more. The thickness may be 0.3 μm or more. The thickness may be 0.8 μm or less. In such cases, efficient and stable signal transmission is possible through the through-hole 11.

[0080] The core layer 10 may further include a cavity (not shown), which is a space formed by a recess inside.

[0081] The cavity may be formed by a recess in a portion of the upper / lower side of the core layer 10 in the thickness direction of the core layer 10, or it may penetrate through the core layer 10 in the thickness direction.

[0082] The element can be mounted in the cavity, and the packaging substrate and the element can be electrically connected. The element may be not only a semiconductor element such as a CPU, GPU, or memory chip, but also a capacitor element, a transistor element, an impedance element, or other modules. In other words, any semiconductor element that can be mounted in a semiconductor device can be used as the element without limitation.

[0083] Via insulation formation step The manufacturing method for the packaging substrate in the embodiment further includes a via insulation portion forming step, in which via insulation portions are formed in through holes to provide a via plugged substrate.

[0084] The via insulation portion may be substantially void-free and filled in at least a portion of the through-hole. The via insulation portion can prevent the resin constituting the insulating layer from being excessively embedded in the through-hole during the process of forming the insulating layer on top of the core layer. This can help to stably maintain the flatness of the upper surface of the insulating layer. Furthermore, if an electrically conductive layer is formed on the inner diameter surface of the via, it can help to stably protect and fix the electrically conductive layer, thereby maintaining the electrical reliability of the manufactured packaging substrate above a certain level.

[0085] The via insulation forming step may include a filling step of filling the through-holes with a via insulation manufacturing composition by screen printing, and a curing step of curing the injected via insulation manufacturing composition to form the via insulation.

[0086] 1) Filling process Figures 2A and 2B are cross-sectional views illustrating a filling process applied to one embodiment of this specification. An example will be described with reference to Figures 2A and 2B.

[0087] The core layer 10 includes the upper surface 12 and has through holes 11 formed in the thickness direction. The specific configuration of the core layer 10 is the same as that described in Figure 1A above. The differences will be explained below.

[0088] During the filling process, the via insulation manufacturing composition 22 can be filled into the through-holes 11 by screen printing. Specifically, a screen 20 with a pattern corresponding to the position of the through-holes 11 is placed on the core layer 10, and the composition 22 can be squeegeeed with a squeegee 21 in the in-plane direction Dp of the base substrate 100 and filled into the through-holes 11.

[0089] The screen material may, but is not limited to, nylon resin, polyester resin, or stainless steel.

[0090] An example of this is that the viscosity of the via insulation manufacturing composition 22 applied during the filling process can be adjusted. Through this, the composition 22 can be easily and smoothly filled into the through hole 11, and the filled composition 22 can not easily detach from the through hole 11.

[0091] The viscosity of the via insulation composition 22 can be measured using a cone-plate rotational viscometer in accordance with JIS-Z8803:2011. The viscosity is measured at room temperature.

[0092] The viscosity of the via insulation manufacturing composition 22 may be between 100 dPa*s and 500 dPa*s. The viscosity may be 150 dPa*s or higher. The viscosity may be 200 dPa*s or higher. The viscosity may be 450 dPa*s or lower. The viscosity may be 400 dPa*s or lower. In such cases, the via insulation manufacturing composition 22 can be filled even more smoothly into the through-hole 11 through screen printing.

[0093] The via insulation composition 22 may contain an epoxy resin, a curing agent, and a filler.

[0094] The epoxy resin is the main component of the via insulation composition 22, and can provide the via insulation composition 22 with low viscosity characteristics, as well as excellent adhesion and insulation properties.

[0095] The epoxy resin may further contain additional functional groups. For example, the epoxy resin may contain one selected from the group consisting of bisphenol groups, aminophenol groups, naphthalene groups, novolac groups, glycidylamine groups, and combinations thereof.

[0096] The curing agent may help to enable the formation of via insulation from the via insulation manufacturing composition 22 by inducing a crosslinking reaction at high temperatures.

[0097] The curing agent may be any one of the following: a polyamine compound, an imidazole compound, or a combination thereof.

[0098] Examples of polyamine compounds include ethylenediamine, propylenediamine, butylenediamine, pentylenediamine, diethylenetriamine, and modified polyamines of triethylenetetramine.

[0099] Examples of imidazole compounds include methylimidazole, dimethylimidazole, benzylmethylimidazole, benzylphenylimidazole, and cyanoalkylimidazole.

[0100] The filler can adjust the viscosity of the via insulation composition 22 to within the range intended in the embodiment, thereby imparting the adjusted roughness to the via insulation.

[0101] The filler may be an inorganic filler. Examples of fillers that may be used include silica, calcium carbonate, aluminum nitride, boron nitride, alumina, and magnesium oxide.

[0102] The average particle size of the filler may be 0.1 μm or more and less than 15 μm. The average particle size may be 0.5 μm or more. The average particle size may be 1 μm or more. The average particle size may be 3 μm or more. The average particle size may be 5 μm or more. The average particle size may be 12 μm or less. The average particle size may be 10 μm or less. In such cases, the filler may have excellent dispersibility and help the via insulation composition 22 to easily fill through holes 11 having a fine diameter. In addition, the surface of the via insulation may have controlled roughness characteristics, thereby improving the peel strength of the electrical conductive layer against the surface to a certain level or higher.

[0103] The average particle size of the filler is measured in accordance with JIS K 5600-2-5.

[0104] The via insulation composition 22 may contain 4% to 70% by weight of epoxy resin. The via insulation composition 22 may contain 10% or more by weight of epoxy resin. The via insulation composition 22 may contain 20% or more by weight of epoxy resin. The via insulation composition 22 may contain 60% or less by weight of epoxy resin.

[0105] The via insulation manufacturing composition 22 may contain 1 to 30 parts by weight of curing agent per 100 parts by weight of epoxy resin. The via insulation manufacturing composition 22 may contain 3 parts by weight or more of curing agent per 100 parts by weight of epoxy resin. The via insulation manufacturing composition 22 may contain 5 parts by weight or more of curing agent per 100 parts by weight of epoxy resin. The via insulation manufacturing composition 22 may contain 10 parts by weight or more of curing agent per 100 parts by weight of epoxy resin. The via insulation manufacturing composition 22 may contain 25 parts by weight or less of curing agent per 100 parts by weight of epoxy resin. The via insulation manufacturing composition 22 may contain 20 parts by weight or less of curing agent per 100 parts by weight of epoxy resin.

[0106] The via insulation composition 22 may contain 20% to 95% by weight of filler. The via insulation composition 22 may contain 30% or more by weight of filler. The via insulation composition 22 may contain 40% or more by weight of filler. The via insulation composition 22 may contain 80% or less by weight of filler.

[0107] In such cases, it is possible to form a via insulating portion that has excellent filling properties for through holes 11 with a fine diameter, and excellent adhesion and insulation properties to the electrical conductive layer placed in the through holes 11.

[0108] The via insulation composition 22 may further contain other components in addition to those described above. These other components are not limited as long as they are commonly used in the field of curable resin compositions. Examples of substances added to the composition 22 include thickeners, defoamers, adhesion promoters, and leveling agents.

[0109] After injecting the via insulation composition 22 into the through-hole 11, the screen 20 can be removed from the upper surface of the base substrate 100.

[0110] 2)Curing process During the curing process, the via insulation composition injected into the through-holes is cured to form via insulation, and a via-plugged substrate can be provided.

[0111] The curing process can be carried out by placing a base substrate, into which the via insulation manufacturing composition has been injected into the through-holes, into a chamber and leaving it in a high-temperature atmosphere for a predetermined time.

[0112] The ambient temperature during the curing process may be 90°C or higher. The ambient temperature may be 100°C or higher. The ambient temperature may be 110°C or higher. The ambient temperature may be 120°C or higher. The ambient temperature may be 200°C or lower. The ambient temperature may be 170°C or lower.

[0113] The curing process may be carried out for 15 minutes or more. The curing process may be carried out for 20 minutes or more. The curing process may be carried out for 60 minutes or less. The curing process may be carried out for 50 minutes or less.

[0114] In such cases, the via insulation composition 22 embedded in the through hole can harden sufficiently to form a via insulation.

[0115] 3) Deathcam process Figure 3A is a conceptual diagram illustrating a via-plugged substrate after the Descam process according to one embodiment of this specification. The following description will refer to Figure 3A for concrete examples.

[0116] The core layer 10 includes the upper surface 12 and has through holes formed in the thickness direction. The specific configuration of the core layer 10 is the same as that described in Figure 1A above. The differences will be explained below.

[0117] The via insulation formation step may further include a descamming process in which the via-plugged substrate 200 is plasma descammed.

[0118] The via insulation portion 30 formed immediately after the filling and curing processes can have a shape that protrudes from the upper surface 12 of the core layer. In the via insulation portion formation step of the embodiment, by additionally applying a descam process, one end 32 of the via insulation portion located on the upper surface 12 side of the core layer can be positioned at substantially the same height as the upper surface 12 of the core layer. Through this, the redistribution layer formed on the via-plugged substrate 200 can have excellent flatness.

[0119] Simultaneously, organic foreign matter adsorbed onto the substrate surface during the filling and curing processes and not easily removed by the cleaning solution can be effectively removed. In particular, when the core layer 10 is a glass core, efficient removal of organic residue is possible without applying any additional processes and without excessive damage to the core layer 10.

[0120] During the descam process, the via-plugged substrate 200 can be exposed to an O2 plasma atmosphere. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere for 2 to 10 minutes per exposure. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere for 3 minutes or more per exposure. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere for 7 minutes or less per exposure.

[0121] In the descam process, the via-plugged substrate 200 can be exposed to an O2 plasma atmosphere once or more times. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere two or more times. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere five or more times. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere 20 times or less. The via-plugged substrate 200 can be exposed to an O2 plasma atmosphere 10 times or less.

[0122] In such cases, one end 32 of the via insulation portion can be processed to the height desired in the embodiment, and organic particles remaining on the surface of the via-plugged substrate 200 can be effectively removed.

[0123] Figure 3B is a conceptual diagram illustrating a via-plugged substrate after the descam process according to another embodiment of this specification.

[0124] The core layer 10 includes the upper surface 12 and has through holes formed in the thickness direction. The specific configuration of the core layer 10 and the via insulation portion 30 is the same as that described in Figures 1A and 3A above. The differences will be explained below.

[0125] A via-plugged substrate 200 that has undergone the Descam process may have a trench structure 31 in which one end 32 of the via insulation portion is positioned lower than the upper surface 12 of the core layer 10. When an insulating layer (not shown) is formed on the via-plugged substrate 200 having the trench structure 31, an interlocking structure can be formed in which the formed insulating layer and the upper surface of the via-plugged substrate 200 are stably bonded to each other. This further increases the contact area between the insulating layer and the upper surface of the via-plugged substrate 200, thereby improving the bonding strength of the insulating layer to the upper surface 12 of the substrate. At the same time, since deterioration such as wrinkling of the insulating layer does not occur, misalignment of the redistribution layer can be stably suppressed.

[0126] The depth of the trench structure 31 can be measured using a surface roughness meter. If the surface on one end 32 side of the via insulation is not flat, the depth of the trench structure 31 is defined as the difference between the average height of the top surface profile of the via plugged substrate 200 and the height at the point with the deepest depth in the profile of the trench structure 31 being measured.

[0127] The depth of the trench structure 31 can be calculated by measuring the top surface profile of the via-plugged substrate 200 in one of the in-plane directions using a surface roughness meter.

[0128] The depth of the trench structure 31 can be calculated by measuring the top surface profile of the via-plug substrate 200 in the x-axis and y-axis directions within the in-plane direction of the via-plug substrate 200 using a surface roughness meter. In this case, the larger of the calculated trench structure depth values ​​is taken as the depth value of the trench structure 31.

[0129] For example, a surface roughness meter from Veeco can be used.

[0130] The depth of the trench structure 31 can be 1 μm to 15 μm. The depth may be 12 μm or less. The depth may be 10 μm or less. The depth may be 3 μm or more. In such cases, the insulating layer formed on the core layer 10 can have excellent bonding strength to the upper surface 12 side of the core layer and can exhibit a flat upper surface.

[0131] Cleaning step The manufacturing method for the packaging substrate in the embodiment may further include a cleaning step, prior to the manufacturing step, for cleaning the via-plugged substrate provided through the via-insulating portion forming step.

[0132] In the cleaning step, via insulation manufacturing composition, via insulation residue, and other organic particles that remain on the substrate surface without being removed during the descam process can be removed. Through this, bonding or connection failures in the electrical conductive layer caused by particles can be suppressed.

[0133] The cleaning step may include an ultrasonic cleaning process for ultrasonically cleaning the via-plugged substrate.

[0134] In the ultrasonic cleaning process, a via-plugged substrate with residual organic particles can be immersed in a water tank, and ultrasonic vibrations can be applied to the water tank to generate cavitation. Through this, the substrate can be easily removed without excessive damage, and the adsorbed particles can be removed.

[0135] In the cleaning step of the embodiment, the vibration frequency may be 30kHz to 200kHz. The vibration frequency may be 50kHz or higher. The vibration frequency may be 70kHz or higher. The vibration frequency may be 100kHz or higher. The vibration frequency may be 150kHz or lower. In such cases, even if the core layer 10 has a fine and complex pattern structure, it can be effectively cleaned without significant damage.

[0136] Manufacturing steps The manufacturing method for the packaging substrate in the embodiment may further include a manufacturing step of manufacturing the packaging substrate from a via-plugged substrate.

[0137] In the manufacturing step, a redistribution layer can be formed above or below the core layer. The redistribution layer may include an electrical conductive layer and an insulating layer surrounding at least a portion of the electrical conductive layer. In the redistribution layer, the insulating layer and the electrical conductive layer may be arranged in a mixed manner. The redistribution layer may be formed in a manner in which an electrical conductive layer having a predetermined position and shape is embedded within an insulating layer. In the redistribution layer, the electrical conductive layer may be formed as fine wires in at least a portion of it.

[0138] An electrical conductive layer corresponds to a conductor that transmits electrical signals. An electrical conductive layer may contain an electrical conductive material. For example, an electrical conductive layer may contain at least one of copper, nickel, aluminum, gold, and silver. Copper or the like may be used as the material for the electrical conductive layer.

[0139] The electrical conductive layer may be formed using a dry or wet method. A detailed explanation of the dry and wet methods will be omitted as it will overlap with the previous explanation.

[0140] The insulating layer is not limited as long as it can be applied as an insulating layer to semiconductor devices or packaging substrates. For example, the insulating layer may be composed of an epoxy resin containing fillers. For example, the insulating layer may be formed through build-up layer materials such as Ajinomoto's ABF (Ajinomoto Build-up Film), undercoat materials, etc., but is not limited thereto.

[0141] After forming the electrical conductive layer, an insulating layer can be formed surrounding the electrical conductive layer. The insulating layer may be formed by forming and curing a coating layer, or by laminating an uncured or semi-cured insulating film onto the electrical conductive layer and then curing it. When the insulating film is laminated onto the electrical conductive layer through reduced-pressure lamination, the formed insulating layer can surround the electrical conductive layer without voids.

[0142] A multilayer redistribution layer can be formed by repeatedly forming and removing insulating and conductive layers. The multilayer redistribution layer can be formed using a build-up layer method. Specifically, after forming a redistribution layer having one layer, unnecessary portions of the insulating layer within the redistribution layer are removed, a conductive layer is formed by methods such as plating, and the conductive layer is selectively etched and patterned. Subsequently, an insulating layer can be laminated on the patterned conductive layer to form a two-layer redistribution layer. A multilayer redistribution layer can be formed by repeating the above method.

[0143] The redistribution layer may include a first redistribution layer formed on the core layer.

[0144] The first redistribution layer may include two or more conductive layers. The first redistribution layer may include one conductive layer and other conductive layers disposed on the one conductive layer.

[0145] The width of the other electrical conductive layer may be narrower than or the same as the width of the first electrical conductive layer.

[0146] The thickness of the other electrical conductive layer may be thinner than or the same as the thickness of the first electrical conductive layer.

[0147] The pitch of the other electrical conductive layer may be smaller than or the same as the pitch of the first electrical conductive layer.

[0148] In the first redistribution layer of the multilayer structure, electrical conductive layers with progressively smaller widths can be arranged towards the top. Similarly, electrical conductive layers with progressively thinner thicknesses can be arranged towards the top. Through this, the packaging substrate can form a stable electrical connection with semiconductor elements having fine patterns.

[0149] The redistribution layer may include a second redistribution layer located beneath the core layer.

[0150] The second redistribution layer may include an electrical conductive layer and an insulating layer surrounding the electrical conductive layer. The materials and formation methods for the electrical conductive layer and insulating layer of the second redistribution layer may be the same as those for the electrical conductive layer and insulating layer of the first redistribution layer. A description of the electrical conductive layer and insulating layer of the second redistribution layer will be omitted as it will overlap with the content described above.

[0151] The second redistribution layer may include two or more conductive layers. The second redistribution layer may include one conductive layer and other conductive layers positioned below the first conductive layer.

[0152] The width of the other electrical conductive layer may be wider than or the same as the width of the first electrical conductive layer.

[0153] The thickness of the other electrical conductive layer may be greater than or equal to the thickness of the first electrical conductive layer.

[0154] The pitch of the other electrical conductive layer may be greater than or the same as the pitch of the first electrical conductive layer.

[0155] In a multilayer second redistribution layer, wider electrical conductive layers may be arranged towards the bottom. In a multilayer second redistribution layer, thicker electrical conductive layers may be arranged towards the bottom. Through this, the packaging substrate can form a stable electrical connection with the main board on which the wide or thick electrical conductive layers are formed.

[0156] The packaging substrate may further include bumps located beneath the second redistribution layer.

[0157] The bumps can be positioned in a predetermined configuration beneath the redistribution layer. For example, the bumps may be positioned on a portion of the underside of the packaging substrate so as to be in contact with the main board or the like.

[0158] Manufactured packaging substrate Figure 4 is a cross-sectional view illustrating a packaging substrate manufactured according to one embodiment of this specification. An example will be described with reference to Figure 4.

[0159] The core layer 10 includes the top surface and has through holes formed in the thickness direction. Via insulation portions 30 can be formed in these through holes. The specific configurations of the core layer 10 and the via insulation portions 30 are the same as those described in Figures 1A and 3A above. The differences will be explained below.

[0160] A packaging substrate 300 manufactured by the manufacturing method of the example packaging substrate may include a core layer 10 having through holes in the thickness direction and via insulating portions 30 disposed in the through holes. The packaging substrate 300 may include a redistribution layer 40 disposed above and / or below the core layer 10. A description of the core layer 10, the via insulating portions 30 and the redistribution layer 40 will be omitted as it will be redundant with the above description.

[0161] The via insulation portion 30 may contain filler. The average particle size of the filler may be 0.1 μm or more and less than 15 μm. The explanation of the filler is omitted as it overlaps with the above.

[0162] During the process of forming a redistribution layer 40 above or below the core layer 10, or during the operation of the elements, the packaging substrate 300 may be repeatedly exposed to a high-temperature atmosphere. In particular, the core layer 10 and the via insulation portion 30, which are made of different materials within the packaging substrate 300, have different thermal expansion characteristics, so the via insulation portion 30 may stress the core layer 10 in a high-temperature atmosphere. Such stress may induce deterioration of the electrical connections formed in the through holes.

[0163] In practice, by adjusting the mechanical properties of the via insulation portion 30, it is possible to suppress the formation of defects in the packaging substrate 300 when it is repeatedly exposed to a high-temperature atmosphere or when the element is operated for a long period of time. Specifically, it is possible to suppress the formation of mechanical defects in the region near the through-holes in the core layer 10, and if an electrical conductive layer is placed in the through-hole, it is possible to prevent the electrical conductive layer from breaking due to thermal expansion of the via insulation portion 30.

[0164] The Young's modulus of the via insulation portion 30 may be 3,000 MPa or more. The Young's modulus may be 3,500 MPa or more. The Young's modulus may be 4,000 MPa or more. The Young's modulus may be 4,500 MPa or more. The Young's modulus may be 8,000 MPa or less.

[0165] The tensile strength of the via insulation portion 30 may be 5 MPa or more. The tensile strength may be 10 MPa or more. The tensile strength may be 15 MPa or more. The tensile strength may be 50 MPa or less. The tensile strength may be 45 MPa or less.

[0166] The elongation rate of the via insulation portion 30 may be 0.1% to 5%. The elongation rate may be 4% or less. The elongation rate may be 3% or less. The elongation rate may be 2% or less. The elongation rate may be 1% or less.

[0167] In such cases, the packaging substrate 300 can maintain stable electrical reliability and long-term durability even when repeatedly exposed to high-temperature atmospheres.

[0168] The Young's modulus of the via insulation 30 is measured by DMA (Dynamic Mechanical Analysis) at 30°C. The tensile strength and elongation of the via insulation 30 are measured by UTM (Universal Testing Machine) at 30°C.

[0169] The packaging substrate 300 may further include an electrically conductive layer disposed between the via insulating portion 30 and the inner diameter surface of the via. At least a portion of the electrically conductive layer may be disposed in contact with the via insulating portion 30. A description of the electrically conductive layer will be omitted as it will overlap with the content described above.

[0170] In practice, by adjusting the peel strength of the electrical conductive layer on the surface of the via insulation portion 30 to a preset range, the via insulation portion 30 can stably fix and protect the electrical conductive layer, thereby improving the electrical reliability of the packaging substrate 300.

[0171] The peel strength of the electrical conductive layer from the surface of the via insulation portion 30 is measured as follows: After forming a 20 μm thick copper thin film on the surface of the via insulation portion 30, the peel strength of the copper thin film from the surface of the via insulation portion is measured by a 180° peel test.

[0172] The peel strength of the electrical conductive layer on the surface of the via insulation portion 30 may be 4 N / cm or more. The peel strength may be 4.5 N / cm or more. The peel strength may be 5 N / cm or more. The peel strength may be 10 N / cm or less. In such cases, the via insulation portion 30 can contribute to suppressing disconnection of the electrical conductive layer formed in the through hole.

[0173] In one concrete example, by adjusting the difference in the coefficient of thermal expansion between the via insulation portion 30 and the core layer 10, it is possible to suppress the occurrence of physical defects in the core layer or damage to the electrical conductive layer within the through-hole due to repeated thermal expansion of the via insulation portion 30.

[0174] The thermal expansion coefficients of the via insulation 30 and the core layer 10 can be measured using a thermal mechanical analyzer (TMA) with thermomechanical analysis. For example, the thermal expansion coefficient can be measured using a TA Instruments Q400 model TMA.

[0175] The coefficient of thermal expansion is measured in an atmosphere below 150°C.

[0176] The difference between the thermal expansion coefficient of the via insulation and the thermal expansion coefficient of the core layer 10 is the absolute value obtained by subtracting the thermal expansion coefficient of the core layer 10 from the thermal expansion coefficient of the via insulation.

[0177] The difference between the thermal expansion coefficient of the via insulation and the thermal expansion coefficient of the core layer 10 may be 35 ppm / °C or less. The difference may be 32 ppm / °C or less. The difference may be 30 ppm / °C or less. The difference may be 10 ppm / °C or more. In such cases, even if the core layer 10 has a complex structure and high hardness characteristics, damage to the core layer 10 due to thermal expansion of the via insulation may not occur easily. Furthermore, if an electrical conductive layer is placed in the through hole, disconnection of the electrical conductive layer can be suppressed in a high-temperature atmosphere.

[0178] The packaging substrate 300 may further include a first insulating layer 421 formed in contact with at least a portion of the upper surface of the core layer 10. The depth of the dimples in the first insulating layer 421 may be 15 μm or less.

[0179] The first insulating layer 421 is formed by having at least a portion of the insulating layer 42 described above in contact with the upper surface of the core layer 10. In other words, the first insulating layer 421 is a component of the insulating layer 42.

[0180] The explanation of the material and formation method of the first insulating layer 421 will be omitted as it will overlap with the content described above.

[0181] The packaging substrate 300 in the embodiment allows the depth of the dimples in the first insulating layer 421 to be adjusted within a specific range. The first insulating layer 421 having the above characteristics has a flatness suitable for forming the multilayer first redistribution layer 40, which can help the redistribution layer have excellent electrical reliability and reduce the frequency of misalignment in the redistribution layer to below a certain level.

[0182] The depth of the dimples in the first insulating layer 421 can be measured using a TEM (Transmission Electron Microscope).

[0183] The depth of the dimples in the first insulating layer 421 may be 15 μm or less. The depth may be 12 μm or less. The depth may be 10 μm or less. The depth may be 7 μm or less. The depth may be 1 μm or more. In such cases, a first redistribution layer 40 with improved flatness can be formed.

[0184] The packaging substrate 300 may further include a second insulating layer (not shown) formed in contact with at least a portion of the lower surface of the core layer 10. The depth of the dimples in the second insulating layer may be 15 μm or less.

[0185] The second insulating layer is formed such that at least a portion of it is in contact with the upper surface of the core layer 10, as described above. In other words, the second insulating layer is a component of the insulating layer.

[0186] The explanation of the material and formation method of the second insulating layer will be omitted as it will overlap with the content described above.

[0187] The depth of the dimples in the second insulating layer may be 15 μm or less. The depth may be 12 μm or less. The depth may be 10 μm or less. The depth may be 7 μm or less. The depth may be 1 μm or more. In such cases, even if a multilayer redistribution layer is formed, the electrical reliability of the redistribution layer is excellent.

[0188] The following examples will provide a more detailed explanation of the implementation through specific embodiments. These embodiments are merely illustrative to aid in understanding the implementation, and the scope of implementation is not limited to them.

[0189] Manufacturing example: Manufacturing of packaging substrates Example 1: Defects were formed on the surface of a Corning SG7.8 glass plate by laser irradiation, followed by wet etching to create multiple through-holes and provide a core layer. The inner diameter of the through-holes was adjusted to approximately 150 μm.

[0190] A screen targeting the multiple through-holes was placed on the core layer, and THP-100 DX1-450Ps ink from Taiyo Ink Co., Ltd., a via insulation manufacturing composition, was filled into the through-holes using a screen printing method. The average particle size of the filler contained in the via insulation manufacturing composition was set to less than 15 μm. The average particle size of the filler was measured in accordance with JIS K5600-2-5.

[0191] A via-plugged substrate was created by curing the filled ink at 140°C for 30 minutes to form via insulation. The via-plugged substrate was placed in a chamber and subjected to plasma descamming, which involved repeatedly exposing it to an O2 plasma atmosphere for 5 minutes each. After the descamming was performed, the substrate was immersed in a water bath and then ultrasonically cleaned for 300 seconds using an vibration frequency of 100 kHz to complete the packaging substrate.

[0192] Evaluation example: Measurement of the depth of the trench structure in a packaging substrate. Three through-holes located on the upper and lower surfaces of the packaging substrate in the example were identified, and the surface profiles of these through-holes were measured using a surface roughness meter from Veeco. From the measured surface profiles, the average height value of the upper surface of the core layer (referred to as value A) and the height value of the lowest point within the through-hole (referred to as value B) were calculated. The value obtained by subtracting value B from value A was then calculated as the depth value of the trench structure.

[0193] The surface profile for each through-hole was measured once in the x-axis direction and once in the y-axis direction within the in-plane direction of the upper surface of the core layer.

[0194] The profiles of the trench structures for each through-hole located on the upper surface of the packaging substrate in the embodiment are shown in Figures 5A to 5C below, and the depth values ​​of the trench structures are shown in Table 1 below.

[0195] The profiles of the trench structures for each through-hole located on the lower surface of the packaging substrate in the embodiment are shown in Figures 6A to 6C below, and the depth values ​​of the trench structures are shown in Table 2 below.

[0196] Evaluation example: Dimple evaluation An insulating layer was formed on the packaging substrate of the embodiment. Specifically, an insulating layer was formed by laminating ABF (Ajinomoto Build-up Film) onto the upper surface of the core layer using a reduced-pressure lamination method.

[0197] The cross-section of the packaging substrate with the insulating layer formed was imaged using a TEM, and the depth of the dimples was calculated. The TEM image of the packaging substrate with the insulating layer formed is shown in Figure 7 below.

[0198] Evaluation example: Composition for manufacturing via insulation and physical properties of via insulation The viscosity of the via insulation composition used in the manufacturing of the packaging substrate in the example was measured using a cone-plate rotational viscometer in accordance with JIS-Z8803:2011.

[0199] The via insulation composition was applied to a flat plate and cured at 140°C for 30 minutes to form a film-like via insulation. The Young's modulus of the via insulation was measured at 30°C using a DMA. The tensile strength and elongation of the via insulation were also measured using a UTM.

[0200] After forming a 20 μm thick copper thin film on the via insulation portion, the peel strength of the copper thin film from the surface of the via insulation portion was measured by a 180° peel test.

[0201] The measured values ​​for the via insulation composition and the via insulation are shown in Table 3 below.

[0202] [Table 1]

[0203] [Table 2]

[0204] [Table 3]

[0205] In the evaluation of the dimples, the depth of the dimples in the examples was measured to be 10 μm or less. This indicates that the degree to which the insulating layer is embedded in the through-holes can be adjusted, and the upper surface of the insulating layer can have excellent flatness.

[0206] Furthermore, the TEM image shown in Figure 7 revealed that no voids were formed within the through-hole. This means that when an electrical conductive layer is formed on the inner diameter surface of the via, the via insulation can stably fix and protect the electrical conductive layer.

[0207] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements by those skilled in the art, utilizing the basic concepts of the present invention as defined in the appended claims, also fall within the scope of the present invention. [Explanation of Symbols]

[0208] 100 base board 10 core layers 11 Through hole 12 Top surface of the core layer 13 Via inner diameter surface 20 screens 21. Squeegee 22 Composition for manufacturing via insulation 30 Via insulation 31 Trench structure 32 One end of via insulation 40 1st redistribution layer 41 Electrical Conductive Layer 42 Insulating layer 421 First insulating layer 200 via plugged circuit board 300 Packaging substrates Dp base substrate in-plane direction

Claims

1. A preparation step of preparing a base substrate including a core layer having through holes formed in the thickness direction, including the top surface, A via-insulating portion forming step is performed to form a via insulating portion in the through hole and provide a via-plugged substrate. The manufacturing step includes manufacturing a packaging substrate from the via-plug substrate, The via insulation forming step includes a filling step of filling the through-holes with a via insulation manufacturing composition by screen printing, a curing step of curing the filled via insulation manufacturing composition to form the via insulation, and a deathcam step of plasma deathcamming the via-plugged substrate. The ratio of the thickness of the core layer to the diameter of the through hole, as observed from the upper surface of the core layer, is 4 to 12. The viscosity of the via insulation composition is 100 dPa*s to 500 dPa*s. The via insulating portion includes one end located on the upper surface side of the core layer, The via-plugged substrate has a trench structure in which one end of the via insulating portion is located lower than the upper surface of the core layer. A method for manufacturing a packaging substrate, wherein the depth of the trench structure in the via-plugged substrate is 1 μm to 15 μm.

2. The aforementioned core layer is a glass core, The core layer includes two or more of the through holes, The diameter of the through-hole is 40 μm to 200 μm. The method for manufacturing a packaging substrate according to claim 1, wherein the pitch of the through holes is 50 μm to 1500 μm.

3. The packaging substrate includes the core layer in which the through holes are formed in the thickness direction, and via insulating portions formed in the through holes. The via insulating portion includes a filler. The method for manufacturing a packaging substrate according to claim 1, wherein the average particle size of the filler is 0.1 μm or more and less than 15 μm.

4. The method for manufacturing a packaging substrate according to claim 1, wherein the elongation of the via insulating portion, measured by a Universal Testing Machine (UTM) at 30°C, is 0.1% to 5%.

5. The method for manufacturing a packaging substrate according to claim 1, wherein the via insulating composition comprises an epoxy resin, a curing agent, and a filler.

6. The packaging substrate includes a core layer in which the through holes are formed in the thickness direction, via insulating portions formed in the through holes, and a first insulating layer formed so that at least a portion of it is in contact with the upper surface of the core layer. The method for manufacturing a packaging substrate according to claim 1, wherein the depth of the dimples in the first insulating layer is 15 μm or less.

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