Transmitter and receiver

Abstract

The subject matter of the present disclosure provides a transmitter for a master clock of an audio system. The transmitter includes an input configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronizing the audio device, a data stream generator configured to determine a data stream based on the message, a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having a start edge timing based on the clock frequency and an end edge timing earlier or later than a half cycle of the encoded clock signal according to bit values of the data stream, and an output configured to transmit the encoded clock signal to the receiver.

Description

Technical Field

[0001] The subject matter of the present disclosure relates to a transmitter for a master clock of an audio system, and a receiver for an audio device of an audio system. More specifically, the transmitter and the receiver are a transmitter and a receiver capable of transmitting and receiving a clock signal for synchronizing audio devices in an audio system. Background Art

[0002] Audio devices in an audio system need to be synchronized. Synchronization may be achieved using a clock signal. For example, in one approach, a master clock may be employed to synchronize two or more audio devices in the audio system.

[0003] An audio device that receives a clock signal can monitor its pulses to replicate the clock signal. However, additional information is required for the audio device to understand the timing of the pulses. This is because latency across the channel may result in arbitrarily aligning a rising edge to the nearest clock pulse not necessarily matching the exact pulses of the clock signal between the devices being synchronized.

[0004] Prior art methods have been attempted, but they often tie audio devices to using specific data transmission methods, such as the Audio Engineering Society / European Broadcasting Union (AES / EBU) interface or the Sony / Philips Digital Interface Format (SPDIF). Summary of Invention [Problems that the invention aims to solve]

[0005] The aim of this disclosure is to mitigate such problems and improve upon prior art. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a transmitter for a master clock of an audio system is provided. The transmitter comprises an input unit configured to receive a message to be sent to a receiver of an audio device in the audio system, and clock frequency information of a clock signal for synchronizing the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave, having a start edge timing based on the clock frequency and an end edge timing earlier or later than half a cycle of the encoded clock signal depending on the bit values ​​of the data stream; and an output unit configured to transmit the encoded clock signal to a receiver. In this way, the message may be encoded within the encoded clock signal, so that both the clock timing and the message can be transmitted simultaneously without the need for a specific data transmission protocol.

[0007] In one embodiment, the transmitter may further include a pseudorandom number generator configured to generate a pseudorandom number key, and the data stream generator may further be configured to generate a data stream based on the pseudorandom number key.

[0008] In one embodiment, the data stream may include a plurality of bits in the form of a frame, the frame including a synchronization portion, a subsequent trigger portion, and a subsequent message portion, the message portion corresponding to the received message and having a length of m bits, the synchronization portion having a length of n+s bits, where n is the length of a pseudorandom number generator and s is the number of bits for synchronizing the receiver, and the trigger portion having a length of t bits.

[0009] In one embodiment, s may be greater than m.

[0010] In one embodiment, the data stream generator may be configured to generate a data stream based on a payload of 0 and a pseudorandom key during the synchronization portion, based on one or more payloads of 1 and a pseudorandom key during the trigger portion, and based on a payload and a pseudorandom key corresponding to the message during the message portion.

[0011] In one embodiment, the pseudorandom number generator may be a linear feedback shift register.

[0012] In one embodiment, the transmitter may further include a pulse narrower configured to generate a first rectangular wave having a pulse width shorter than half a cycle of the encoded clock signal, and a pulse widener configured to generate a second rectangular wave having a pulse width longer than half a cycle of the encoded clock signal, and the pulse shaper may be configured to select either the first or second rectangular wave depending on the bit values ​​of the data stream.

[0013] In one embodiment, the pulse widener and pulse narrower may be configured to generate a first rectangular wave and a second rectangular wave by combining pulses from a wave having a frequency that is a multiple of the encoded clock signal.

[0014] In one embodiment, the message may include a sample count or a timestamp.

[0015] In one embodiment, the starting edge may be a rising edge, and the ending edge may be a falling edge.

[0016] According to one aspect of this disclosure, a master clock device comprising the above-described transmitter is provided.

[0017] According to one aspect of the present disclosure, a receiver for an audio device of an audio system is provided, the receiver comprising: an input unit configured to receive an encoded clock signal from a transmitter for a master clock of the audio system; a clock signal generator configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal; and a data stream restorer configured to retrieve bit values ​​of a data stream encoded in the encoded clock signal, and to retrieve messages based on the bit values ​​of the data stream, based on whether the end edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal.

[0018] In one embodiment, the receiver may further include a pseudorandom number generator configured to generate a pseudorandom number key, and the data stream restorer may further be configured to retrieve messages based on the bit values ​​of the data stream and the pseudorandom number key.

[0019] In one embodiment, the data stream may include a plurality of bits in the form of a frame, the frame including a synchronization portion, a subsequent trigger portion, and a subsequent message portion, the message portion corresponding to the received message and having a length of m bits, the synchronization portion having a length of n+s bits, where n is the length of a pseudorandom number generator and s is the number of bits for synchronizing the receiver, and the trigger portion having a length of t bits.

[0020] In one embodiment, s may be greater than m.

[0021] In one embodiment, the receiver may further comprise a match counter configured to reset a pseudo-random number generator in response to detecting a trigger portion, and may be configured to output a message in response to counting m bits after the trigger portion.

[0022] In one embodiment, the pseudo-random number generator may be a linear feedback shift register.

[0023] In one embodiment, the receiver may further comprise a pulse width detector configured to determine whether an end edge of an encoded clock signal is earlier or later than a half cycle of the encoded clock signal by sampling the encoded clock signal at a frequency that is a multiple of the frequency of the wave used to generate encoded clock signal pulses.

[0024] In one embodiment, the message may further comprise a sample count or a timestamp.

[0025] In one embodiment, the clock signal generator may be configured to generate a square wave clock signal by dividing the frequency of the encoded clock signal by 2.

[0026] In one embodiment, the start edge may be a rising edge, and the end edge may be a falling edge.

[0027] According to one aspect of the present disclosure, an audio device comprising the above-described receiver is provided.

[0028] According to one aspect of the present disclosure, a system comprising the above-described transmitter and the above-described receiver is provided.

[0029] According to one aspect of the present disclosure, an audio system including the master clock device described above and the audio device described above is provided. According to one aspect of the present disclosure, a method of encoding an encoded clock signal is provided, the method comprising receiving a message to be sent to a receiver of an audio device of the audio system, and clock frequency information of a clock signal for synchronizing the audio device, determining a data stream based on the message, generating the encoded clock signal in the form of a rectangular wave having a start edge timing based on the clock frequency, and an end edge timing that is earlier or later than a half-cycle of the encoded clock signal in accordance with a bit value of the data stream, and transmitting the encoded clock signal to the receiver.

[0030] In one embodiment, the start edge may be a rising edge, and the end edge may be a falling edge.

[0031] According to one aspect of the present disclosure, a method of obtaining a message and a clock signal from an encoded clock signal is provided, the method comprising receiving the encoded clock signal from a transmitter for a master clock of an audio system, generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal, obtaining a bit value of a data stream encoded in the encoded clock signal based on whether an end edge of the encoded clock signal is earlier or later than a half-cycle of the encoded clock signal, and obtaining the message based on the bit value of the data stream.

[0032] In one embodiment, the end edge may be a falling edge.

[0033] According to a further aspect of the present disclosure, a transitory or non-transitory computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform any of the methods described above is provided.

[0034] The subject matter of this disclosure is best described with reference to the accompanying drawings. [Brief explanation of the drawing]

[0035] [Figure 1] This is a block diagram of a system (audio system) according to one or more embodiments. [Figure 2] This is a block diagram of a transmitter from the clock source shown in Figure 1, according to one or more embodiments. [Figure 3] This is a block diagram of a data stream generator from the transmitter shown in Figure 2, according to one embodiment. [Figure 4] This figure shows the encoded clock signal generated by the transmitter (Figure 2) and the restored clock signal generated by the receiver (Figure 6). [Figure 5] This is a block diagram of another transmitter other than the one shown in Figure 2, according to one or more embodiments. [Figure 6] Figure 1 is a block diagram of the receiver from the audio device shown. [Figure 7] Figure 6 is a block diagram of the data stream restorer from the receiver. [Figure 8] This is a flowchart of a method for encoding an encoded clock signal according to one or more embodiments. [Figure 9] This is a flowchart illustrating how to obtain the message and clock signal from the encoded clock signal. [Modes for carrying out the invention]

[0036] While various features are described herein with reference to one or more embodiments, it will be understood that features from different embodiments may be included in other embodiments without constituting the addition of subject matter that goes beyond what is described herein.

[0037] Referring to Figure 1, an audio system 10 is provided. The audio system 10 includes a clock source device 12, also known as a master clock or clock box, and one or more audio devices 14. One or more audio devices may be devices suitable for generating audio. Examples of audio devices include a drive mechanism (e.g., a compact disc reader or MP3 player), a digital-to-analog converter (DAC), an upsampler, a headphone amplifier, and a user interface. One or more sound generating devices, including one or more speakers, headphones, etc., may be connected to one or more audio devices to generate the sound provided by the drive mechanism.

[0038] The clock box 12 may be connected to each audio device using cables.

[0039] The clock box 12 includes a transmitter 18 as shown in Figure 2.

[0040] Referring to Figure 2, the transmitter 18 includes an input unit 19, a clock signal generator 20, a frame counter 22, a data stream generator 24, a pulse widener 26, a pulse narrower 28, a pulse shaper 30, and an output unit 32.

[0041] The input unit 19 is configured to receive a clock signal. The clock signal is a square wave. The input square wave has a frequency f (where f may be used interchangeably with F in this specification to indicate frequency) that is intended to be used to synchronize the audio device 14 (Figure 1). In this way, the input unit is configured to receive clock frequency information of the clock signal for synchronizing the audio device 14, since information related to the clock frequency can be derived from the square wave itself.

[0042] The clock signal generator 20 obtains an input square wave from the input section 19. The clock signal generator 20 is configured to generate a modified square wave based on the input square wave. The clock signal generator 20 may be provided in the form of a phase-locked loop (PLL). The phase-locked loop generates the modified square wave by doubling the frequency of the input square wave. In this way, the modified square wave has a frequency of 2f (or 2F).

[0043] The modified square wave is then used as input to the frame counter 22 (or counter), the data stream generator 24, the pulse widener 26, and the pulse reducer 28.

[0044] The frame counter 22 is aware of the number of bits in a frame. The frame counter 22 may obtain the number of bits in a frame from a clock source memory (not shown). The frame counter 22 counts the number of pulses that make up the modified square wave in a frame and is configured to generate a restart condition when the data stream generator 24 needs to restart generating bits equivalent to another frame.

[0045] A frame is a set of bits required to send a message to an audio device. A frame consists of a synchronization portion, a subsequent trigger portion, and a subsequent message portion, the message portion corresponding to the received message. The message portion may be of length m bits. The synchronization portion is of length n+s bits, where n is the length of the pseudo-random number generator (see below) and s is the number of bits used to synchronize the receiver. The trigger portion is of length t bits.

[0046] Referring to Figure 3, the data stream generator 24 is connected to the input unit 19. The data stream generator 24 is configured to generate a data stream based at least partially on the message. In other words, the data stream generator 24 is configured to generate a data stream that represents the message in binary format.

[0047] To achieve this, the data stream generator 24 includes a payload generator 31, a frame synchronization detector 33, a shift register 34, a switch 36, a pseudo-random number generator 38, and a data stream coupler 40. Note that each of the payload generator 31, frame synchronization detector 33, shift register 34, switch 36, and pseudo-random number generator 38 has a modified square wave 2F as input, and that this is not included in Figure 3 for the sake of brevity and to aid in the clarity of the diagram.

[0048] The input unit 19 also receives messages to be sent to each receiver of the audio device 14. These messages may take the form of sample counts, timestamps, or even auxiliary data. The input unit 19 may be the same as shown in Figure 2, or different input units. The sample count may indicate the sequence order of samples in a data packet containing audio samples. The timestamp may be the time recorded by the clock box 12. In practice, only one or the other of the timestamp and / or sample count may be sent. The sample count and timestamp are used by the audio device, so that the audio device has knowledge of which frame is being received. The auxiliary data may be any other data that the transmitter may have as a message to the audio device. For example, the name of the clock box, its part number or serial number, or technical specifications may be sent. The auxiliary data may be sent alternately with the sample count or timestamp.

[0049] The payload generator 31 is configured to receive a message and generate a payload in response. The payload may contain the message in binary format. As described elsewhere in this disclosure, the payload may also be used to represent all binary values ​​within a frame. In this way, the payload generator 31 may be referred to as a payload message sub-generator.

[0050] The shift register 34 is configured to convert the payload into serial data. In this way, the payload may be a bitstream. The shift register 34 also receives a signal from the frame synchronization detector 33 regarding when to output the bitstream. This signal is sometimes called the load signal. The load signal is sent when the frame synchronization detector 33 has counted several bits of the frame, which signify the end of the message.

[0051] The frame synchronization detector 33 is configured to receive a frame count signal, Frame Count, from the frame counter 22 (Figure 2). The frame count signal indicates to the frame synchronization detector when the frame counter 22 has counted all the bits of the frame, and therefore the frame count signal acts as a reset for the frame synchronization detector 33 to start counting again.

[0052] The frame synchronization detector 33 is also configured to output a synchronization signal Sync to the switch 36. The switch has two inputs. The first input 42 is the output of the shift register 34, i.e., a bitstream representing a message. The second input 44 is also a bitstream, sometimes called a payload. The payload generator 31 may generate this additional bitstream, or this additional bitstream may be generated by a different source. This additional payload may include two subpayloads, namely a synchronization payload and a trigger payload.

[0053] To avoid confusion, the input to switch 36 may be considered as the payload as a whole. The payload may contain multiple parts, each corresponding to a portion of the frame. The payload may also contain a message portion (output from shift register 34) which is input to the first input 42. The message portion may contain m bits of binary value (0 or 1). The number of bits m is chosen so as to be sufficient to define the message using binary notation. The payload may also contain a synchronization portion which is input to the second input 44. The synchronization portion may contain n+s bits of binary value. The binary values ​​of n and s may all be 0. The number of bits n may be the length of the pseudorandom key generated by the pseudorandom number generator 38 (see below). The number of bits s may be greater than the number of bits m. The reason for this is best understood by referring to the receiver (see below). In summary, however, it is theoretically possible for the message payload to have a large section that contains only 0s and no 1s. If the message portion is larger than the synchronization portion, in such cases an incorrect reset of the pseudorandom number generator may occur. The payload may also include a trigger portion having t bits. The trigger portion may be input to a second input 44. The number of bits t may be a single bit in length and may have a value of 1.

[0054] The frame synchronization detector 33 is configured to send a synchronization signal Sync to switch 36 when it receives a frame count signal Frame Count and resets. The synchronization signal Sync is configured to switch the switch to the second input 44. In this way, when the synchronization signal Sync is active, the synchronization portion and trigger portion of the payload are output to the data stream coupler 40. When the frame synchronization detector 33 has counted n+s+t bits, the synchronization signal Sync terminates. Without the synchronization signal Sync, the switch defaults to the first input 42. When the first input 42 is selected, the shift register 34 outputs the message portion of the payload to the data stream coupler 40.

[0055] In some embodiments, n may be 24 bits long, m may be 60 bits long, s may be 61 bits long, and t may be 1 bit long. In this way, the frame may be 146 bits long.

[0056] The pseudorandom number generator 38 is configured to generate a pseudorandom number key (or pseudorandom key). A suitable pseudorandom number generator 38 proceeds sequentially through all n-bit numbers. The numbers are unique in the sense that they are not repeated until all other possible numbers have been exhausted.

[0057] To achieve this, the pseudo-random number generator 38 may include a linear feedback shift register LFSR. The LFSR can acquire a unique set of numbers excluding 0.

[0058] If a sequence of n bits is considered a bitstream (without word boundaries), then an LFSR generates a number that is unique at any point in the bitstream. Other types of pseudorandom number generators 38 may share this property. Therefore, the use of an LFSR is not essential if the pseudorandom number generator 38 can function in this manner. For the purposes of the embodiments described herein, the pseudorandom number generator 38 may be an LFSR for illustrative purposes.

[0059] The LFSR may be 24 bits long. In this way, the pseudorandom key contains 24 bits of 1s and 0s that appear in the random sequence, but their order is determined by the structure of the LFSR.

[0060] Although not shown in Figure 3 for brevity, the synchronization signal Sync is also available for LFSR. In this way, when the trigger portion is sent, the pseudorandom number generator restarts generating pseudorandom keys. Thus, the pseudorandom number generator 38 is configured to generate a 24-bit pseudorandom key once during the first n bits, and then two 24-bit keys during s before resetting between the third key. The end of the third key occurs simultaneously with the trigger bit t. The pseudorandom number generator 38 then generates 2 and 1-bit pseudorandom keys when the load signal Load is active and the synchronization signal Sync is inactive.

[0061] The data stream coupler 40 is configured to couple the payload with a pseudo-random key. For example, the data stream coupler 40 may be an exclusive OR gate (XOR). The output from the data stream coupler 40 may be a data stream. In other words, the data stream generator is configured to generate a data stream based on a pseudo-random key. During the synchronization portion, when the payload is 0, it will be understood that the data stream is the pseudo-random key. During the trigger portion, the data stream is the opposite value of the pseudo-random key. During the message portion, the message appears to be encoded and is extremely unlikely to match the pseudo-random key across all 60 bits. It should also be noted that the message portion is shorter than the synchronization portion and therefore avoids false synchronization. If the message happens to be a group of consecutive 0s or ends therein, synchronization is still detected in the trigger bits.

[0062] In this way, the data stream generator 24 is configured to generate a data stream based on a payload of 0 and a pseudorandom key during the synchronization portion, based on one or more payloads of 1 and a pseudorandom key during the trigger portion, and based on a payload and a pseudorandom key corresponding to the message during the message portion.

[0063] Referring again to Figure 2, the switch uses the data stream as the switching signal.

[0064] The pulse widener 26 and pulse reducer 28 take a modified clock signal, i.e., a modified square wave, as input. Although not shown in Figure 2 for brevity, a further input to the pulse widener 26 and pulse reducer 28 is a high-speed clock. The high-speed clock may have a frequency that is a multiple of the modified clock. For example, a square wave for synchronizing an audio device may have a frequency of 48 kHz. The square wave frequency may correspond to the sample rate of the audio signal. The modified clock signal may have a frequency of 96 kHz. The high clock frequency may have a frequency that is a multiple of the frequency of the modified clock signal, for example, 32 times the frequency. The high clock frequency may be approximately 3.1 MHz (to two significant figures).

[0065] Referring to Figures 2 and 4, the pulse widener 26 may be configured to use pulses from a higher clock frequency to construct the modified clock signal. For example, the frequency may be 2f or 2F if the modified clock signal is a direct double of the clock signal frequency f. Thus, it is possible to construct a narrow pulse using 15 / 32 pulses from a high-speed clock. It is possible to construct a wide pulse using 17 / 32 pulses from a high-speed clock. In this way, the pulse widener 26 and pulse reducer 28 are configured to generate a first rectangular wave and a second rectangular wave by combining pulses from waves having frequencies that are multiples of the encoded clock signal. As a result, the falling edge of the narrow pulse is earlier than half a cycle of the modified clock signal, and the falling edge of the wide pulse is later than half a cycle of the modified clock signal.

[0066] The output from the pulse widener 26 may be a first rectangular wave having a pulse width shorter than half a cycle of the encoded clock signal. The output from the pulse reducer 28 may be a second rectangular wave having a pulse width longer than half a cycle of the encoded clock signal. The pulse shaper 30 is configured to generate an encoded clock signal in the form of a rectangular wave, the timing of which is an initial edge based on clock frequency information and an initial edge earlier or later than half a cycle of the encoded clock signal depending on the bit value of the data stream. The terms “initial edge” and “initial edge” may be more specifically defined in some embodiments as “rising edge” and “falling edge,” respectively. More specifically, the pulse shaper 30 may be configured to select either the first or second rectangular wave depending on the bit value of the data stream. To achieve this, the pulse shaper 30 may take the form of a switch. For example, when the bit value is 1, the pulse shaper 30 may select the output of the pulse widener 26, i.e., the first rectangular wave. When the bit value is 0, the pulse shaper 30 may select the output of the pulse reducer, i.e., the second rectangular wave. In this way, the modified clock signal has a value of 1 or high in half a cycle of the encoded clock signal when the bit value from the data stream is 1. The modified clock signal has a value of 0 or low in half a cycle of the encoded clock signal when the bit value from the data stream is 0.

[0067] The output from the pulse shaper 30 is an encoded clock signal. The output unit 32 is configured to transmit the encoded clock signal to the receiver.

[0068] Referring to Figure 5, a further embodiment of the transmitter 18' is provided. The reference numbers used for this embodiment are the same as those used for the embodiment from Figure 2, with a prime(') appended. The following description explains the differences between the embodiment in Figure 5 and the embodiment in Figure 2. All other features may be considered the same.

[0069] The input section 19' is configured to receive a high-speed clock. The high-speed clock (nf or nF) may have a frequency that is a multiple of the clock signal used to synchronize the audio device. For example, the square wave used to synchronize the audio device may have a frequency of 48 kHz. The modified clock signal may have a frequency of 96 kHz. The higher clock frequency may have a frequency that is a multiple of the frequency of the modified clock signal, for example, 32 times. The higher clock frequency may be approximately 3.1 MHz (to two significant figures). In addition to the high-speed clock, the transmitter 18' may receive the clock frequency of the clock signal used to synchronize the audio device. The clock frequency may be provided in the form of clock frequency information.

[0070] In Figure 5, "n" may be a power of 2 (for example, 2, 4, 8, 16, 32, etc.). "n" may be a variable, but may actually have a fixed value. In other words, the clock frequency information may be stored in a database, may not be a variable, that is, may be predetermined or fixed. Alternatively, the clock frequency information may be implemented in the hardware circuitry.

[0071] The clock signal generator 20' is configured to generate a modified square wave (2F) based on a fast clock (nF). The clock signal generator 20' may include one or more flip-flops. In this way, the modified clock signal has a frequency of 2f (or 2F). The modified clock signal is input to a frame counter 22', a data stream generator 24', a pulse widener 26', and a pulse reducer 28', each of which functions in a manner similar to the embodiment from Figure 2.

[0072] Referring to Figure 6, each audio device 14 (Figure 1) includes a receiver 50.

[0073] The receiver 50 includes an input unit 52, a clock signal generator 54, a pulse width detector 56, a data stream restorer 58, and an output unit 64. The data stream restorer 58 includes frame restorer means 62 and data stream restorer means 60.

[0074] The input unit 52 may be configured to receive an encoded clock signal from the transmitter 18.

[0075] The clock signal generator 54 may take the form of a counter. The counter may be a frequency divider counter. The frequency divider counter may divide an encoded clock signal having a frequency of 2f by 2 in order to generate a clock signal having a frequency of f. Therefore, the clock signal may be a square wave instead of a rectangular wave of the encoded clock signal. The square wave may then be output from the output unit 64 to the processor of the audio device 14 for synchronization with the other audio device 14. In other words, the clock signal generator 54 may be configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal.

[0076] The pulse width detector 56 may be a wide and a narrow detector. The pulse width detector 56 may be configured to determine whether the falling edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal by sampling the encoded clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoded clock signal pulses. For example, a fast clock is used to generate the encoded clock signal pulses by the transmitter. The frequency used to monitor the timing of the falling edge may be a multiple of the fast clock. The frequency used to monitor the timing of the falling edge may be twice the frequency of the fast clock, for example, 6.1 MHz (up to two significant figures). In this way, if the value of the encoded clock signal is high or 1, a wide pulse is detected in 32 / 64 pulses. If the value of the encoded clock signal is low or 0, a narrow pulse is detected in 32 / 64 pulses. The output from the pulse width detector 56 may be a bitstream of 1s and 0s corresponding to the wide pulse and the narrow pulse, respectively. Alternatively, in other embodiments, the same resolution may be used to monitor the timing of the falling edge. For example, if the wide pulse and narrow pulse are 15 and 17 high-speed clock cycles in width, respectively, it is possible to test them over 16 cycles.

[0077] The data stream restorer 58 is configured to receive a bitstream from the pulse width detector 56. The operation of the data stream restorer 58 can be best understood by referring to Figure 7, but in summary, the data stream restorer 58 is configured to retrieve the bit values ​​of the data stream encoded in the encoded clock signal based on whether the falling edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal. In addition, the data stream restorer 58 may be configured to retrieve a message based on the bit values ​​of the data stream.

[0078] Referring to Figure 7, the data stream restorer 58 includes a match counter 70, a pseudo-random number generator 72, a coupler 74, a shift register 76, and a payload latch 78. Roughly speaking, the match counter 70 corresponds to the frame restorer 62 from Figure 6, and the pseudo-random number generator 72, coupler 74, shift register 76, and payload latch 78 correspond to the data stream restorer 60 from Figure 6.

[0079] The match counter 70 (or counter) is configured to count the number of bits in the bitstream. The match counter 70 is configured to count the number of bits in the frame, i.e., 146 bits. The match counter 70 has two inputs, i.e., the bitstream from the pulse width detector, and an output from the pseudorandom number generator 72. The match counter 70 has two outputs, one of which is a reseed signal and the other is a synchronization signal. The match counter 70 is configured to compare the bit values ​​from the bitstream with the bit values ​​from the pseudorandom key. In response to a mismatch, the reseed signal is sent to the pseudorandom number generator. Since 0 is used for the payload for those parts of the frame, it will be understood that for 64 bits, i.e., for message parts n and m, the bitstream matches the pseudorandom key. When the trigger bit t is compared, there is a mismatch because the payload for t is 1. Therefore, the "exclusive OR" combination of the trigger bit (1) and the pseudorandom key value does not have the same value as the pseudorandom key. The reseed signal, Reseed, is then interrupted for 60 bits. The other output, namely the synchronization signal Sync, is output to the payload latch 78 at the last bit of the frame (the 60th bit after the reseed signal has been output).

[0080] Once the entire frame is decoded, encoding restarts with the subsequent frames.

[0081] The pseudorandom number generator 72 receives the bitstream output by the pulse width detector. The first bit of the frame is considered a seed signal Seed. In response to the seed signal Seed, the pseudorandom number generator 72 generates a pseudorandom key. The pseudorandom number generator 72 may include a linear feedback shift register (LFSR). The LFSR may be 24 bits long. The LFSR may be identical to the LFSR in the transmitter. In this way, the pseudorandom number generator 72 generates the same pseudorandom key as in the transmitter. The pseudorandom number generator 72 repeatedly generates a 24-bit pseudorandom key until it receives a reseed signal Reseed, at which point it resets and starts generating the pseudorandom key again from bit 1. In this way, the match counter is configured to reset the pseudorandom number generator in response to the detection of a trigger portion. The pseudorandom key is output to the coupler 74 and the match counter 70.

[0082] The coupler 74 receives two inputs. The first input is a pseudo-random key. The second input is a bitstream output from a pulse width detector. The first and second inputs are coupled by the coupler 74. The coupler 74 may be provided in the form of an exclusive OR gate. The coupled bitstream is output from the coupler 74 to the shift register 76.

[0083] In this way, the data stream restorer is further configured to retrieve messages based on the bit values ​​of the data stream and a pseudo-random key.

[0084] In response to the reception of the synchronization signal Sync, the payload latch 78 is configured to latch the most recent 60 bits in the shift register. The most recent 60 bits correspond to bit m of the frame, which corresponds to the message. In this way, the match counter 70 is configured to output the message in response to the count of m bits after the trigger portion.

[0085] The message may be a timestamp or a sample count. The output from the payload latch 78 may also be a sample count or a timestamp. In this way, the payload latch is sometimes called a message latch.

[0086] Referring to Figure 6, the output unit 64 is configured to output the decoded message (timestamp or sample count) to the processor of the audio device 14 (Figure 1), so that the audio device can synchronize its clock signal with other devices.

[0087] The various features of the transmitter and receiver described in the above embodiments may be embodied as instructions stored on a computer-readable medium. The instructions may be executable by the processor to cause the processor to perform the functions described herein.

[0088] Referring to Figure 8, various features of the transmitter may be understood as method steps. The method may also be a method for encoding an encoded clock signal. In addition to other details included above, the method comprises receiving a message to be sent to a receiver of an audio device in an audio system, and clock frequency information of a clock signal for synchronizing the audio device, in step S100; determining a data stream based on the message in step S102; generating an encoded clock signal in the form of a rectangular wave having a rising edge timing based on the clock frequency and a falling edge timing earlier or later than half a cycle of the encoded clock signal depending on the bit values ​​of the data stream, in step S104; and transmitting the encoded clock signal to the receiver in step S106.

[0089] Referring to Figure 9, various features of the receiver may be understood as method steps. The method may also be a method for obtaining a message and a clock signal from an encoded clock signal. The method comprises receiving an encoded clock signal from a transmitter for the master clock of an audio system in step S200, generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal in step S202, obtaining the bit values ​​of a data stream encoded in the encoded clock signal in step S204 based on whether the falling edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal, and obtaining a message in step S206 based on the bit values ​​of the data stream. [Explanation of Symbols]

[0090] 10 Audio Systems 12 Clock Source Devices 14 Audio Devices 18 Transmitters 19 Input section 20 Clock signal generator 22 Frame Counter 24 Data Stream Generators 26. Pulse widener 28. Pulse Reducer 30 Pulse Shaping Device 31 Payload Generator 32 Output section 33 Frame-synchronous detector 34 Shift Registers 36 switches 38 Pseudorandom number generator 40 Data Stream Couplers 42 First input section 44 Second input section 50 receivers 52 Input section 54 Clock signal generator 56. Pulse width detector 58 Data Stream Restorer 60 Data Stream Restoration Means 62 Frame restoration means 64 Output section 70 Match Counter 72 Pseudorandom number generators 74 Combiner 76 Shift Register 78 Payload Latch

Claims

1. A transmitter for the master clock of an audio system, An input unit configured to receive messages to be sent to the receiver of the audio device of the audio system, and clock frequency information of a clock signal for synchronizing the audio device, A data stream generator configured to determine a data stream based on the aforementioned message, A pulse shaper configured to generate the encoded clock signal in the form of a rectangular wave, having a start signal edge timing based on the clock frequency and an end signal edge timing earlier or later than half a cycle of the encoded clock signal depending on the bit value of the data stream, An output unit configured to transmit the encoded clock signal to the receiver, A pseudorandom number generator configured to generate a pseudorandom number key, wherein the data stream generator is configured to generate the data stream based on the pseudorandom number key, Equipped with, A data stream includes a plurality of bits in the form of a frame, the frame including a synchronization portion, a subsequent trigger portion, and a subsequent message portion, the message portion corresponding to the received message and having a length of m bits, the synchronization portion having a length of n+s bits, where n is the length of the pseudorandom number generator, s is the number of bits for synchronizing the receiver, and the trigger portion having a length of t bits. Transmitter.

2. The transmitter according to claim 1, wherein s is greater than m.

3. The transmitter according to claim 1, wherein the pseudo-random number generator is a linear feedback shift register.

4. The transmitter according to claim 1, further comprising a pulse reducer configured to generate a first rectangular wave having a pulse width shorter than half a cycle of the encoded clock signal, and a pulse widener configured to generate a second rectangular wave having a pulse width longer than half a cycle of the encoded clock signal, wherein the pulse shaper is configured to select the first rectangular wave or the second rectangular wave depending on the bit values ​​of the data stream.

5. The transmitter according to claim 4, wherein the pulse widener and the pulse reducer are configured to generate the first rectangular wave and the second rectangular wave by combining pulses from a wave having a frequency that is a multiple of the encoded clock signal.

6. The transmitter according to claim 1, wherein the message includes a sample count or a timestamp.

7. A receiver for an audio device in an audio system, An input section configured to receive an encoded clock signal from a transmitter for the master clock of the audio system, A clock signal generator configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal, A data stream restorer configured to retrieve the bit values ​​of a data stream encoded within the encoding clock signal, based on whether the termination signal edge of the encoding clock signal is earlier or later than half a cycle of the encoding clock signal, and to retrieve a message based on the bit values ​​of the data stream, A pseudorandom number generator configured to generate a pseudorandom number key, wherein the data stream restorer is further configured to retrieve the message based on the bit values ​​of the data stream and the pseudorandom number key, Equipped with, A data stream includes a plurality of bits in the form of a frame, the frame including a synchronization portion, a subsequent trigger portion, and a subsequent message portion, the message portion corresponding to the received message and having a length of m bits, the synchronization portion having a length of n+s bits, where n is the length of the pseudorandom number generator, s is the number of bits for synchronizing the receiver, and the trigger portion having a length of t bits. Receiver.

8. The receiver according to claim 7, wherein s is greater than m.

9. The receiver according to claim 7, further comprising a match counter configured to reset the pseudorandom number generator in response to detection of the trigger portion, and configured to output the message in response to a count of m bits after the trigger portion.

10. The receiver according to claim 7, wherein the pseudorandom number generator is a linear feedback shift register.

11. The receiver according to claim 7, wherein the message comprises a sample count or a timestamp.

12. The receiver according to claim 7, wherein the clock signal generator is configured to generate the square wave clock signal by dividing the frequency of the encoded clock signal by 2.

13. A method for encoding an encoded clock signal, The steps include receiving a message to be sent to the receiver of an audio device in an audio system, and receiving clock frequency information of a clock signal for synchronizing the audio device, The steps include determining the data stream based on the aforementioned message, The steps of generating an encoded clock signal in the form of a rectangular wave having an initial signal edge timing based on the clock frequency and an ending signal edge timing earlier or later than half a cycle of the encoded clock signal depending on the bit value of the data stream, The steps include generating a pseudorandom key using a pseudorandom number generator, A step of generating a data stream based on the pseudorandom key, wherein the data stream comprises a plurality of bits in the form of a frame, the frame comprising a synchronization portion, a subsequent trigger portion, and a subsequent message portion, the message portion corresponding to the received message and having a length of m bits, the synchronization portion having a length of n+s bits, where n is the length of the pseudorandom generator, s is the number of bits for synchronizing the receiver, and the trigger portion has a length of t bits, The steps include: transmitting the encoded clock signal to the receiver; A method that includes [a certain feature].

14. A method for obtaining a message and a clock signal from an encoded clock signal, The steps include receiving an encoded clock signal from a transmitter for the master clock of the audio system, The steps include generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal, The steps include obtaining the bit values ​​of the data stream encoded within the encoding clock signal based on whether the termination signal edge of the encoding clock signal is earlier or later than half a cycle of the encoding clock signal, The steps include: obtaining a message based on the bit values ​​of the data stream; The steps include generating a pseudorandom key using a pseudorandom number generator, A step of obtaining the message based on the data stream and the bit value of the pseudorandom key, wherein the data stream includes a plurality of bits in the form of a frame, the frame includes a synchronization portion, a trigger portion following it, and a message portion following it, the message portion corresponding to the received message and having a length of m bits, the synchronization portion having a length of n+s bits, where n is the length of the pseudorandom number generator, s is the number of bits for synchronizing the receiver, and the trigger portion has a length of t bits, A method that includes [a certain feature].

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