Systems and methods for testing non-volatile memory

Abstract

According to one embodiment, a method for characterizing a non-volatile memory includes applying a first voltage on a word line conductively coupled to a non-volatile memory cell and measuring a current through the non-volatile memory cell in response to the application of the first voltage, using a sense amplifier to compare the current through the non-volatile memory cell to a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the word line, and determining a measured current based on the comparison.

Description

[Technical Field]

[0001] Cross-reference of related applications This international application claims priority to U.S. Patent Application No. 18 / 069,408, filed on 21 December 2022, which is incorporated herein by reference.

[0002] The present invention generally relates to electronic systems and methods, and in particular embodiments to systems and methods for testing non-volatile memory. [Background technology]

[0003] Programmable non-volatile memory (NVM) is useful in many applications because it retains stored information even when power is removed from the memory. There are many different types of programmable non-volatile memory, including, but not limited to, programmable read-only memory (PROM), electrically erasable ROM (EEPROM), and flash memory. These memory types have several charge storage methods, including, but not limited to, floating gates or silicon-oxide-nitride-oxide-silicon (SONOS) storage materials or nodes. Like other types of memory, programmable NVM is typically constructed as an array of bit cells arranged in rows and columns. Each bit cell may contain one split gate or two transistors (i.e., a 1T, 1.5T, or 2T cell). During programming, charge is injected into one of the storage nodes of the transistors. During normal operation of the NVM, bit cells are read by selecting a row of bit cells via a word line (WL) and measuring the output current of each bit cell via a sense amplifier coupled to the bit line.

[0004] In actual memory applications, the device characteristics of bit cells may vary with respect to semiconductor process parameters and may vary randomly from one another. Therefore, in some applications, the thresholds of each bit cell are measured to determine read parameters, write parameters, and sense amplifier threshold currents. In addition, some bit cells may be defective and require replacement with redundant bit cells. However, given the large size of modern non-volatile memory, measuring and characterizing each cell can be time-consuming, resulting in increased testing costs. [Overview of the Initiative] [Means for solving the problem]

[0005] According to one embodiment, a method for characterizing a non-volatile memory includes the steps of applying a first voltage on a word line conductively coupled to a non-volatile memory cell, and measuring a current flowing through the non-volatile memory cell in response to the application of the first voltage. The step of measuring the current includes using a sense amplifier to compare the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the word line, and determining the measured current based on the comparison.

[0006] According to another embodiment, the memory system includes an integrated circuit having a memory array containing non-volatile memory cells, a plurality of word line drivers coupled to the memory array, a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus, a tunable current source coupled to the plurality of sense amplifiers, a first control circuit, and a second control circuit. The first control circuit is configured to set the tunable current source to a test current and to apply a first address to the memory array to select a row of non-volatile memory cells, and the second control circuit is configured to read the outputs of the sense amplifiers and iteratively update the test current based on the outputs of the sense amplifiers to determine the current flowing through at least one non-volatile memory cell in the row of non-volatile memory cells.

[0007] According to a further embodiment, a method for characterizing a non-volatile memory comprises: performing a test read of the non-volatile memory, the step of operating the non-volatile memory in a test mode comprising: applying a row address to the non-volatile memory to select a row of non-volatile memory cells, grounding a word line coupled to the selected row of non-volatile memory cells, measuring a current of at least one non-volatile memory cell in the row of non-volatile memory cells while the word line is grounded, and incrementing the row address; and repeating the step of performing the test read using the incremented row address.

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] [Figure 1A] 1 is a block diagram of a memory system according to an embodiment. [Figure 1B] FIG. 3 shows a diagram illustrating an exemplary read current distribution for N memory cells. [Figure 2A] 3 is a flowchart of a method according to an embodiment of the present invention. [Figure 2B] 5 is another flowchart of a method according to an embodiment of the present invention. [Figure 3A] 7 is a block diagram illustrating an operation of a sense amplifier according to an embodiment. [Figure 3B] 8 is a schematic diagram of a word line driver according to an embodiment. [Figure 3C] 9 is a schematic diagram of a conventional word line driver. [Figure 3D] 10 is a schematic diagram of a level shifter according to an embodiment. [Figure 3E] 11 is a schematic diagram of a level shifter according to another embodiment. [Figure 3F] 12 is a schematic diagram of a reference current generator according to an embodiment. [Figure 4]FIG. 2 is a timing diagram according to one embodiment. [Figure 5A] FIG. 3 is a diagram illustrating an exemplary memory cell that can be used to implement a non-volatile memory array according to an embodiment of the present invention. [Figure 5B] FIG. 4 is another diagram illustrating an exemplary memory cell that can be used to implement a non-volatile memory array according to an embodiment of the present invention. [Figure 5C] FIG. 5 is still another diagram illustrating an exemplary memory cell that can be used to implement a non-volatile memory array according to an embodiment of the present invention. [Figure 5D] FIG. 6 is a cross-sectional view illustrating one embodiment of an N-type SONOS transistor. [Figure 6] FIG. 7 is a diagram illustrating a processing system that can be used to implement part of a system of an embodiment. [Description of Embodiments]

[0010] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly describe a particular embodiment, characters indicating variations of the same structure, material, or process step may follow a figure number.

[0011] The making and using of the presently preferred embodiments are described in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0012] In one embodiment, the non-volatile memory array is characterized by grounding the word lines of each row of memory cells and measuring the output current of each non-volatile memory cell. The current measurement may be performed by iteratively comparing the output current of each memory cell with an adjustable reference current using a sense amplifier to estimate the output current of the non-volatile memory cell. In some embodiments, these measurements may be performed rapidly row by row using an existing sense amplifier of the non-volatile memory used during normal read operations of the memory, an external data bus, and a sense amplifier current reference circuit.

[0013] Grounding the word lines within the non-volatile memory array during testing enables faster characterization of memory cells compared to conventional systems that measure memory cell thresholds by applying a variable voltage to the word lines. Conventional systems require additional time to charge and discharge the higher voltage applied to the word lines before and after each measurement. The memory system of this embodiment also has a size advantage over conventional systems because the word line driver does not need to include a high-voltage circuit for applying the test voltage to the word lines. Using a smaller word line driver reduces silicon area and lowers costs.

[0014] Figure 1A shows one embodiment of a memory system including an integrated circuit 100 having non-volatile memory. As shown, the integrated circuit 100 includes a memory array 104, a row decoder 102, a word line driver 103, a controller 106, a sense amplifier 112, a column decoder 110, I / O logic 114 coupled to an external data bus, a reference current generator 108, and a test controller 116. The reference current generator 108 may also be called an adjustable current source. In some embodiments, the integrated circuit 100 may be coupled to an external tester 120 while the memory array 104 is being characterized. Instead of, or in addition to, the integrated circuit 100 may also include a built-in self-test (BIST) circuit 118 that performs one or more characterization functions for the memory array 104. The BIST circuit 118 and the tester 120 are shown with dashed lines to indicate that these blocks may or may not be present in some embodiments.

[0015] In various embodiments, the components of the integrated circuit 100 may be arranged on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate, and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0016] As shown in the figure, the memory array 104 includes an array of non-volatile memory cells 105. Each non-volatile memory cell 105 is connected to its respective word line (WL1...WLn) and its respective bit line (BL1...BLm). During normal operation of the memory, the row decoder 102 decodes the row address based on the address data ADDR provided at the input to the I / O logic 114. The decoded row address is used to select one of the word lines (WL1...WLn) via the word line driver 103, which activates the row of memory cell 105 that generates its respective read current on its respective bit line (BL1...BLm). The current on each bit line is compared to a reference current generated by a reference current generator 108 using a sense amplifier 112. The column decoder 110 selects the column of the memory array 104 to be sent to the sense amplifier 112, and its output is sent to the data line DATA via the I / O logic 114. The controller 106 is a memory controller that controls the operation of the memory. In some embodiments, the reference current generator 108 may be implemented using a current digital-to-analog converter (CDAC).

[0017] In various embodiments, the non-volatile memory cells 105 of the memory array 104 are measured to (1) characterize the thresholds of programmed and / or unprogrammed memory cells; (2) determine memory operating parameters such as sense amplifier thresholds and program time; and / or (3) identify non-functional memory cells that should be replaced by redundant memory cells.

[0018] As described above, in various embodiments, the state of each memory is evaluated by determining whether the read current of each memory cell is greater than or less than a threshold current. Figure 1B shows an exemplary distribution of read currents for N memory cells, which may represent, for example, N memory cells 105 in a row of a non-volatile memory array 104.

[0019] As shown in the figure, each memory cell generates a first lower current when the memory cell is written to the "1" state 134, and generates a second higher current when the memory cell is written to the "0" state 132. In an alternative embodiment, the assignment of the binary states "0" and "1" may be reversed. Current I NOM0 represents the average current or nominal current of N memory cells when written to the "0" state, and current I NOM1 represents the average current or nominal current of N memory cells when written to the "1" state. Current I THRESH represents the threshold current used by the sense amplifier 112 during a read operation to determine whether a particular bit is written to the "0" state or the "1" state. For example, during a read operation, the sense amplifier determines that the memory cell 105 is written to the "0" state when the current generated by the memory cell is greater than the threshold current I THRESH , and determines that the memory cell 105 is written to the "1" state when the current generated by the memory cell is less than the threshold current I THRESH .

[0020] In an actual memory system, the actual current I generated by each memory cell NOM0 and I NOM1 may change during operation due to variations in operating memory parameters including, but not limited to, temperature, power supply voltage, aging of the memory cells, and write duration and write voltage. Accordingly, the memory has a nominal "0" write current I NOM0 and a threshold current I THRESH , and between the nominal "1" write current I NOM1 and the threshold current I THRESH is designed to have some current margin I MARG . The current margin I MARG may be selected to ensure sufficient noise margin and accurate operation over a specified temperature range and power supply voltage. This margin may be ensured by selecting the threshold current I THRESH to meet predetermined margin requirements, and in FIG. 1B, for "0" write bits, INOM0 -I THRESH , and for the "1" write bit, I NOM1 +I MARG It is indicated as a dotted line as specified. In various embodiments, I NOM0 -I THRESH The write bit and I generate a measurement current greater than 0. NOM0 +I THRESH A "1" write bit that generates a smaller measured current than is considered to have a sufficient margin. For example, the outlier measurement 136 for a "0" write bit has an associated current of I NOM0 -I THRESH Because it is larger than, the current margin I MARG It is located inside. On the other hand, the outlier measurement of 138 for the "1" write bit indicates that the associated current is I NOM1 +I THRESH Because it is larger, current margin I MARG It's outside.

[0021] In various embodiments, the current measurement of one or more memory cells is determined by iteratively setting the current threshold of the sense amplifier 112 and reading the output of the sense amplifier 112. For example, in one embodiment, the current generated by a reference current generator is set to a first current value for comparison with a specific current threshold. The rows of memory cells are then read using the first current value. The resulting read values ​​provide indication of which memory cells generate currents above and below the first current value. For example, referring to Figure 1B, the first current value is I after the rows of memory cells have been written to have a value of "1". NOM1 +I MARG When set to this value, all measured memory cells will return a value of "1" except for bit 138, which returns a value of "0" indicating that its current is greater than the first current value. This information can be used, for example, to replace bit 138 with a redundant memory cell, or to replace an entire row with a redundant row of memory cells.

[0022] In various embodiments, the memory cells in a row of memory cells may be written to a value of "1", a value of "0", or a combination of "1" and "0" according to a specific pattern. For example, in one embodiment, all memory cells in a particular row are written to have a value of "0". Next, the reference current generated by the reference current generator 108 changes continuously to determine one or more current levels of the written memory cells using a "linear search". For example, referring to Figure 1B, the initial reference current is current I NOM0 It can be made larger than the initial reference current, and as a result, the initial measurement returns a set of measurements indicating that the memory cells in the row have current levels lower than the initial reference current. During each subsequent measurement, the reference current is successively reduced so that the returned measurements indicate a mixture of memory cells having currents above and below the reference current. For example, if the reference current is I NOM0 If it is located in I NOM0 A memory cell with a current exceeding this value returns a value of "0", I NOM1 Memory cells with a current below a certain threshold return a value of "1". The current of a particular memory cell can be estimated to be between a first reference current that returns "0" and a second reference current that returns "1". These measurements may continue until the current of each memory cell is determined. For example, if the reference current falls below the current of the outlier memory cell 136, all memory cells will return a value of "0". In an alternative embodiment, linear search is performed to find lower currents (e.g., I NOM0 -I MARG It starts at less than ( ) and can increase continuously.

[0023] In some embodiments, the current of a subset of memory cells can be estimated. For example, the current threshold can be iteratively adjusted to determine a "worst-case" memory cell (e.g., memory cell 136) that is written as "0", or to determine a predetermined number of "worst-case" memory cells with the minimum current, and then the memory measurement can be terminated.

[0024] In some embodiments of the present invention, different search techniques can be applied in addition to the linear search technique described above. For example, the current of a particular memory cell can be approximated successively using a binary search algorithm. In such embodiments, where the reference current generator 108 is implemented using a CDA, the CDA is initialized to an initial DAC word in which the MSB of the DAC is set to "1" and the remaining least significant bits are set to "0". Consider the case where all bits are written to "0" when the measurement of a particular bit indicates "0", meaning that the reference current is less than the current generated by the particular memory cell, in which case the MSB and the second most significant bit of the CDA are set to "1" for the next measurement. On the other hand, when the measurement of a particular bit indicates "1", meaning that the reference current is greater than the current generated by the particular memory cell, the MSB is set to "0" and the second most significant bit of the CDA is set to "1" for the next measurement. The measurement proceeds bit by bit until all bits of the CDA input word have been used. In some embodiments, the CDA word can be stored and modified using a successive approximation register according to well known successive approximation techniques known in the art. In such an embodiment, the final value stored in the successive approximation register at the end of the measurement represents an estimate of the memory cell.

[0025] In some embodiments, the measurement results of multiple memory cells may be used to determine a reference current when performing a binary search to identify one or more outlier memory cells, and / or to identify and measure the current of a “worst-case” memory cell. In such embodiments, the binary search may be performed to minimize the number of bits that produce a “1” value when the bits are pre-programmed to be in the “0” state. For example, the current used for each successive approximation trial may be determined by comparing the number of “1” values ​​produced between two consecutive cycles so that it converges to a current value where a single memory cell (e.g., outlier 136) returns a “1” value while the remaining memory cells return “0” values. In other words, the system is configured to find the cell (or cells) with the lowest erase current.

[0026] While the current estimation technique described above is relevant to measuring memory cells written to a "0" value, it should be understood that similar measurement techniques can also be used to measure memory cells written to a "1" value. In such embodiments, the polarity of the measurements in the corresponding measurement sequence is reversed and adjusted to correspond to the reversed programmed polarity. For example, instead of determining the current of an outlier cell with the minimum current, the current of one or more outlier cells (e.g., cell 138) with the maximum current is determined.

[0027] Each measurement may be controlled using, for example, BIST118, tester120, controller106, test controller116, or a combination thereof. For example, one of these controllers provides the row address to the row decoder102, analyzes the resulting data output by the sense amplifier112, and determines the next current to be generated by the reference current generator108. In embodiments where the test operation is controlled by an external tester120 during test mode, the row address of the test row may be provided via the address bit ADDR, and the measured bit may be read via the data bus DATA coupled to the I / O logic114. The operation of the reference current generator108 and the test mode of the embodiment may be controlled by the tester120 via the control bus CTL coupled to the I / O logic114. In some embodiments, various test sequences may be partially controlled by the test controller116. For example, when the tester 120 puts the integrated circuit 100 into characterization test mode, the test controller 116 may configure the controller 106 to apply the necessary test control sequence and the reference current generator 108 to adjust its reference current to the requested test current or the series of test currents described above. In some embodiments, the tester 120 may provide only the leading row address for characterization. In such embodiments, the row address may be incremented internally by the test controller 116 and / or BIST 118 after each measurement for each row.

[0028] In some embodiments, the tester 120 may analyze the output of each measurement iteration described above and determine the next current value to be provided by the reference current generator 108. In alternative embodiments, the analysis of each measurement iteration and / or determination of the next current value may be performed internally by the BIST 118. In some embodiments, the entire characterization method may be performed internally by the BIST 118, and the results of the characterization may be made available externally via the I / O logic 114.

[0029] In various embodiments, the characterization results may be presented in a table in various formats. In one embodiment, the characterization results may include a list of memory cell address locations and their associated current thresholds. This list may detail each memory cell in each row or a subset thereof, such as one or more "worst-case" memory cells and their associated current thresholds. These current thresholds may be expressed with respect to a CDAC input word provided to the reference current generator 108 and / or converted to equivalent current thresholds and / or equivalent threshold voltage values ​​based on other physical measurements or characterization data. This conversion may be performed, for example, using a database, a lookup table, or other data conversion methods known in the art.

[0030] The memory systems described herein may be implemented in a variety of semiconductor processes, such as standard CMOS processes and / or CMOS processes modified to accommodate one or more specific types of non-volatile memory. Embodiments of the memory architecture are described herein with respect to silicon-oxide-nitride-oxide-silicon (SONOS) devices developed, for example, according to Infineon's SONOS process technology, but other embodiments of the invention are not limited in this way and may include substantially any type of memory cell developed according to substantially any non-volatile process technology.

[0031] Figures 2A and 2B show flowcharts of methods according to embodiments of the present invention. More specifically, Figure 2A shows method 200 for characterizing a non-volatile memory array in which each memory cell under test is written with "0", and Figure 2B shows method 230 for characterizing a non-volatile memory array in which each memory cell under test is written with "1". In various embodiments, methods 200 and 230 may be performed under the control of a test controller 116, BIST 118 and / or tester 120, depending on the implementation and specifications of a particular system.

[0032] Referring to Figure 2A, method 200 begins in step 202 when it enters a “margin mode” (for example, a mode for characterizing memory cells). This margin mode can be input externally via commands provided to the I / O logic 114 shown in Figure 1A via the control line CTL. Next, in step 204, a first row address is provided to the row decoder 102. As described above, this row address may be provided by the tester 120, BIST 118, and / or test controller 116.

[0033] In step 206, a first initial readout current reference is set, for example, by providing a first CDAC input word to the reference current generator 108. This first initial readout current may correspond, for example, to a first (e.g., MSB) estimate of a binary search successive approximation.

[0034] Once the initial adjustment current is set, the word line of the selected row is set to a reference voltage such as 0V (e.g., ground voltage), and in step 212, the first measurement of the selected row is performed by performing a memory read. The memory output obtained for the selected row (e.g., the output of sense amplifier 112) is analyzed to determine whether the read passed a first set of conditions. In some embodiments, a read pass is defined as a memory read that produces all "0"s for each memory cell in a row of memory cells. If a read pass is encountered in step 214, the reference current generated by the reference current generator 108 is increased in step 210, and step 212 is repeated with the increased reference current. In some embodiments, the reference current is increased by incrementing the digital word provided to the CDAC of the reference current generator 108. On the other hand, if a read pass is not encountered in step 214 (e.g., one or more bits returned by the memory read indicate "1"), the reference current generated by the reference current generator 108 is decreased in step 208, and step 212 is repeated with the decreased reference current. The reference current can be reduced, for example, by decrementing the digital word provided to the CDAC of the reference current generator 108.

[0035] In various embodiments, steps 212, 214, and steps 208 and / or 210 are repeated until the measurement is completed in step 213. In some embodiments, the measurement is completed when all bits controlling the CDA are toggled and the memory cell current is determined (within the precision of the CDA), at which point the method proceeds to step 216, where the row address is incremented. If the measurement is not complete, the method proceeds to step 214 as described above. In embodiments utilizing a column decoder, such as the column decoder 110 shown in Figure 1A, the current column decoder setting may be continuously incremented in step 216 to read an entire row before the row address is incremented.

[0036] During step 218, a determination is made as to whether the incremented row address is greater than a predetermined maximum address. If the incremented row address is not greater than the maximum row address, the method proceeds to step 212, where the row corresponding to the incremented row address is measured. On the other hand, if the incremented row address is greater than the maximum row address, the margin mode is terminated in step 218. The predetermined maximum address may be the maximum address of non-volatile memory, or it may be a different address in embodiments where only a subset of memory rows are measured.

[0037] Method 230, shown in Figure 2B, is similar to Method 200, shown in Figure 2A, except that a memory cell in a particular row is written to have a value of "1". Therefore, steps 212 and 214 are replaced by steps 232 and 234, respectively. In step 234, the word line of the selected row is set to 0V (e.g., ground voltage), and in step 234, the first measurement of the selected row is performed by performing a memory read. The memory output obtained for the selected row (e.g., the output of sense amplifier 112) is analyzed to determine whether the read passed a first set of conditions. In some embodiments, a read pass is defined as a memory read that generates all "1"s for each selected memory cell in the row of accessed memory cells. If a read pass is encountered in step 234, the reference current generated by the reference current generator 108 is reduced in step 208, and step 232 is repeated with the reduced reference current. On the other hand, if no read path is encountered in step 234 (for example, one or more bits returned by the memory read indicate "0"), the reference current generated by the reference current generator 108 is increased in step 210, and step 234 is repeated with the increased reference current. The operation of the remaining steps of method 230 proceeds as described above with respect to method 200 in Figure 2A.

[0038] Figures 3A, 3B, 3D, 3E, and 3F show circuits that may be used to implement a memory system according to an embodiment of the present invention. Figure 3A shows a memory sensing system 300 of an embodiment that includes a memory cell 105 corresponding to a memory cell in the memory array 104 shown in Figure 1A, a sense amplifier 302 corresponding to a sense amplifier included in a plurality of sense amplifiers in the sense amplifier block 112 shown in Figure 1A, and a reference current generator 108 corresponding to the reference current generator in Figure 1A.

[0039] The memory cell 105 may be a floating-gate memory cell or a non-volatile memory cell such as a SONOS memory, configured to generate an output current Icell that depends on the memory state of the memory cell. For example, when the memory cell 105 is in a programmed state (e.g., a "1" state), a lower bit line current Icell is generated. On the other hand, when the memory cell 105 is in an erased state or a "0" state, a higher bit line current Icell is generated. Therefore, the state of the memory cell 105 can be determined by using the sense amplifier 302 and comparing the output current Icell of the memory cell 105 provided to the sense input of the sense amplifier 302 with a reference current Isense generated by a current generator 108 provided to the reference current input of the sense amplifier 302.

[0040] During operation, the sense amplifier 302 generates a first logic state for the output signal Dout when the output current Icell of the memory cell 105 is less than the reference current Isense, and generates a second logic state when the output current Icell is greater than the reference current Isense. The first and second logic states can be referred to as the "low" state and the "high" state, or the "0" state and the "1" state, respectively. In some embodiments, this designation can be reversed so that the first and second logic states are referred to as the "high" state and the "low" state, or the "1" state and the "0" state, respectively.

[0041] The memory cell 105 and sense amplifier 302 may be constructed using memory cell and sense amplifier circuits known in the art. For example, the memory cell 105 can be a SONOS, charge trap memory cell, or floating gate memory cell, and the sense amplifier 302 may be implemented using a cross-coupled CMOS latch circuit. In alternative embodiments, other memory cell and sense amplifier circuits may be used. The reference current generator 108 may be implemented using a CDA such as the CDA360 described later with respect to Figure 3F.

[0042] Figure 3B shows a word line driver circuit 320 of an embodiment that can be used to implement each of the multiple word line driver circuits in the word line driver block 103 shown in Figure 1A. As shown, the word line driver 320 includes a p-channel MOS transistor P1 coupled between a positive bias node (also called a "positive supply node") and a word line drive node WLS, and an n-channel MOS transistor N1 coupled between the word line drive node WLS and a negative bias node (also called a "negative supply node"). The positive bias node and the negative bias node are coupled to positive and negative power supply circuits (e.g., a positive charge pump and a negative charge pump), respectively. In some embodiments, the body connection NWELL of the p-channel MOS transistor P1 may be coupled to the positive bias node, and the body connection PWELL of the n-channel MOS transistor N1 may be coupled to the negative supply node.

[0043] The negative level shifter 322 and the positive level shifter 324 provide gate drive signals to the gates of the p-channel MOS transistor P1 and the n-channel MOS transistor N1, respectively, based on signals received from the low-voltage row control block 326. In one embodiment, the low-voltage row control block 326 represents the output stage of the row decoder 102 shown in Figure 1A. During normal memory read and write operations, the positive and negative bias nodes provide the voltage required for the word line WLS, as described below with respect to Figures 5A, 5B, 5C, and 5D. However, during memory cell characterization operations of the embodiments described herein, the negative bias node is set to ground voltage so that the word line WLS is grounded.

[0044] Device characterization systems and methods of embodiments that enable word line grounding during memory cell characterization are advantageous because they allow the use of a physically compact word line driver. This is in contrast to voltage-mode characterization systems and methods that apply a variable voltage to the word line and require additional circuitry to perform memory cell characterization. A wide range of voltages are applied to the measured memory cell to determine the voltage threshold of the memory cell. In some cases, devices rated to handle higher voltages are used to provide these voltages during characterization. In some embodiments, each of these devices may consist of multiple devices connected to each other, occupying a large amount of silicon area. Figure 3C shows a conventional word line driver that includes transistors P1 and N1 and level shifters 322 and 324, along with additional circuitry to support the application of a wider range of positive voltages to the word line via a p-channel MOS device P3. The additional circuitry further includes a p-channel MOS device P2, an n-channel MOS device N2, and level shifters 333 and 335 that receive input from a low-voltage row-controlled margin mode block 336. The conventional word line driver 330 includes more devices than the word line driver 320 of the embodiment. In various embodiments of the present invention, the word line driver of the embodiment is physically smaller than conventional word line drivers used in voltage-mode device characterization.

[0045] Figures 3D and 3E show level shifter circuits 332 and 334, respectively, which can be used to implement the negative level shifter circuit 322 and the positive level shifter circuit 324 of the word line driver 320 shown in Figure 3B. Figure 3D shows a negative level shifter 332 configured to convert a low-level logic signal (e.g., 0V to 1V) to a high-level logic signal with a signal swing between a negative and a positive power supply (e.g., -3V to 0 / 1V). In various embodiments, the voltage range at the output of the negative level shifter circuit 332 is sufficient to drive the gate of an n-channel MOS transistor N1 (Figure 3B) which functions as a high-side switching transistor. The negative level shifter 332 includes a cross-coupled latch comprising p-channel MOS transistors P4 and P5, n-channel MOS transistors N4 and N5, and input p-channel MOS transistors P6 and P7 which function as input transistors. During operation, a low-level logic input IN LV is applied to the gate of p-channel MOS transistor P6, and an inverting low-level logic input Inb LV is applied to the gate of p-channel MOS transistor P7. The resulting currents from transistors P6 and P7 cause the cross-coupled latch circuit to provide a high-level logic signal at the output node Out HV and an inverting high-level logic signal at OutB HV.

[0046] Referring to Figure 3E, a positive level shifter 334 is shown, configured to convert a low-level logic signal (e.g., 0V to 1V) into a high-level logic signal having a signal swing between a negative and positive power supply (e.g., 0 / 1V to 4V). In various embodiments, the voltage range at the output of the positive level shifter circuit 334 is sufficient to drive the gate of a p-channel MOS transistor P1 (Figure 3B) which functions as a low-side switching transistor. The positive level shifter 334 includes a cross-coupled latch comprising p-channel MOS transistors P4 and P5, n-channel MOS transistors N4 and N5, and input n-channel MOS transistors N8 and N9 which function as input transistors. During operation, a low-level logic input IN LV is applied to the gate of the N-channel MOS transistor N8, and an inverting low-level logic input Inb LV is applied to the gate of the N-channel MOS transistor N9. The resulting currents provided by transistors N8 and N9 cause the cross-coupled latch circuit to provide a high-level logic signal at the output node Out HV and an inverting high-level logic signal at OutB HV.

[0047] It should be understood that the level shifter circuits 332 and 334 shown in Figures 3D and 3E are just two examples of many possible level shifter circuits that can be used to implement the level shifting function of the word line driver 320. In alternative embodiments of the present invention, other level shifting circuits known in the art may be used.

[0048] Figure 3F shows a CDAC circuit 360 that can be used to implement the reference current generator 108 shown in Figure 1A. As shown, the CDAC circuit 360 is configured to provide an output current Iout based on an n-bit digital input word CDAC[n:1]. In one embodiment of the present invention, the CDAC 360 is an 8-bit CDAC. However, in other embodiments, other bit resolutions may be used depending on the particular embodiment and its specifications.

[0049] As shown in the figure, the CDAC circuit 360 is implemented as a binary weighted circuit with n binary weighted output and bias branches. The bias branch includes p-channel MOS transistors 362, 364, and 366, and a resistor RC1. A current source Iin provides a bias voltage P0_BIAS to transistor 366 in the input branch and transistors 372, 378, and 384 in the output branch. The output of resistor RC1 provides a bias voltage P1_BIAS to transistor 364 in the input branch and transistors 370, 376, and 382 in the output branch, and transistor 362 is used to match the on-resistances of the select transistors 368, 374, and 380 in the output branch. As shown in the figure, transistors 362, 364, and 366 each have a relative size of one unit and are configured to receive a DC bias current Iin. The first output branch includes a cascode transistor 372, a current source transistor 370, and a select transistor 368 which is activated when the LSB of the digital input word CDAC[n:1] is asserted. As shown in the figure, transistors 368, 370, and 372 are the same size as transistors 362, 364, and 366 of the bias branch, and the first branch generates a current of 1 × Iin when the branch is active. The second output branch includes a cascode transistor 378, a current source transistor 376, and a select transistor 374 which is activated when the second most significant bit of the digital input word CDAC[n:1] is asserted. As shown in the figure, transistors 374, 376, and 378 are twice the size of transistors 362, 364, and 366 of the bias branch, and the second branch generates a current of 2 × Iin when the branch is active. The nth output branch includes a cascode transistor 384, a current source transistor 382, ​​and a select transistor 380 which is activated when the MSB of the digital input word CDAC[n:1] is asserted. As shown in the figure, transistors 380, 382, ​​and 384 are n times the size of the bias branch transistors 362, 364, and 366, and the nth branch is active when the branch is active. n-1Generates a current of ×Iin. If applicable, 4-2 n-2 Additional binary weighted branches with weightings are not shown for the sake of simplicity. In some embodiments, the CDAC circuit 360 may be implemented using equally weighted segments or a combination of equally weighted segments and binary weighted segments, depending on the specifications of the particular embodiment. In further alternative embodiments, other CDAC circuits and architectures known in the art may also be used.

[0050] Figure 4 shows a timing diagram illustrating the state of the row address line RADDR and data line DATA coupled to the I / O logic 114 in Figure 1A during the memory cell characterization procedure of the embodiment when the memory array 104 is being read. Also shown are the clock signal CLK, which represents the system clock of the memory system, and the signal R_VALID, which is a control signal asserted when the leading row address is written to the test memory system. At time t1, when R_VALID is asserted, the leading row address A1 is written to the row address line RADDR. This results in a first measurement represented by the data word D1 appearing on the data line DATA at time t2, where the length of each word matches the width of the row being measured or the width of the selected column. For example, in an embodiment where 128 sense amplifiers are coupled to a selected column, and / or in an embodiment using 128 sense amplifiers coupled to a row with a width of 128 bits, the widths of the data words D1, D2, D4, and D4 are each 128 bits. After 5 clock cycles, the leading row address A1 is incremented to A2 and given to the row decoder 102, and the corresponding data word D2 appears on the data line DATA at time t3. This process is repeated until the reading from memory 104 is complete. In embodiments using a column decoder such as the column decoder 110 shown in Figure 1A, separate reads are performed for each selected column until the entire row is read before the row address RADDR is incremented.

[0051] The timing scheme shown in Figure 4 is advantageous because it allows for the output of numerous measurements in a small number of clock cycles. This improves the speed of characterization testing and reduces the test cost per device. In contrast, conventional embodiments require significant delays between measurements of each row of the memory array to allow for charging and discharging of word lines by an onboard charge pump. In addition, embodiments that provide measurement data via a wide external data bus are more efficient because they can rapidly clock output the measurement data in a faster parallel manner than using a narrower output bus or a narrower dedicated bus such as a narrow test bus or control bus.

[0052] It should be understood that the timing diagram in Figure 4 is merely one example of possible signal timing relationships in the characterization system of the embodiment. Different timing relationships may be implemented in alternative embodiments. For example, in an alternative embodiment, the data line DATA may be updated every n clock cycles, where n is less than 5 or greater than 5.

[0053] Figures 5A, 5B, and 5C show exemplary memory cells that can be used to implement memory cells 105 of a non-volatile memory array 104 according to embodiments of the present invention. For example, one embodiment of a one-transistor (1T) SONOS memory cell is shown in Figure 5A, which includes an N-type SONOS transistor having a gate terminal, a drain terminal, and a source terminal (see Figure 5C). The gate of the SONOS transistor is coupled to receive the SONOS word line (WLS) voltage, the drain is coupled to receive the bit line (BL) voltage, and the source is coupled to receive the source line (SL) voltage. As shown in the cross section of Figure 5C, the substrate or well of the SONOS transistor is coupled to receive the well bias voltage (P-WELL). Exemplary voltages for reading, erasing, and programming the 1T SONOS memory cell are shown in Figure 5D and will be discussed in more detail below.

[0054] One embodiment of a 2T SONOS memory cell is shown in Figure 5B, which includes an N-type SONOS transistor and an N-type path device (FNPASS) to minimize leakage current during read operations. The SONOS gate is coupled to receive the SONOS word line (WLS) voltage, and the drain is coupled to receive the bit line (BL) voltage. The source of the SONOS transistor is coupled to the drain of the FNPASS device. The gate of the FNPASS device is coupled to receive the word line (WL) voltage, and the source is coupled to receive the source line (SL) voltage. The SONOS and FNPASS devices may share common board connections. Similar to a 1T cell, a well-bias voltage (P-WELL) is supplied to the board of the SONOS and FNPASS devices to facilitate read, erase, and program operations. Exemplary voltages for read, erase, and program the 2T SONOS memory cell are shown in Figure 5D and discussed in more detail below.

[0055] Figure 5C is a cross-sectional view showing one embodiment of an N-type SONOS transistor. While Figures 5A to 5C show N-type devices, the memory architectures described herein are not limited in this way, and other embodiments may include p-type devices. Those skilled in the art will understand how the memory architectures can be modified to accommodate such devices.

[0056] As shown in Figure 5C, the gate of a SONOS transistor is isolated from the channel by a stack of dielectric layers. The dielectric stack (often called the “ONO stack”) may include a thin tunnel layer (typically oxide) above the channel, a charge trap layer (typically nitride) above the tunnel layer, and a blocking layer (typically oxide) between the charge trap layer and the gate. The charge trap layer of a SONOS transistor is the storage node of 1T and 2T memory cells, for example, shown in Figures 5A and 5B. The charge trap layer can be “charged” to change the threshold voltage (Vt) of the SONOS transistor and change the value of a bit stored in the 1T or 2T memory cell (e.g., to “0” or “1”). The threshold voltage (Vt) is defined as the threshold gate-source voltage for which current flows through the SONOS transistor.

[0057] A SONOS memory cell according to an embodiment of the present invention can be programmed or erased by applying a voltage of appropriate polarity, magnitude, and duration between the gate terminal and source / drain / substrate terminals of a SONOS transistor. This voltage is called the gate-channel voltage. For example, a SONOS memory cell can be programmed by increasing the gate-channel voltage of the SONOS transistor to a relatively high positive value (typically 7V to 12V). This causes electrons to tunnel from the channel into the ONO stack, where they are trapped in the charge-trap nitride layer. The trapped charge creates an energy barrier between the drain and source of the transistor, thereby increasing the threshold voltage (Vt) of the SONOS transistor. In one embodiment, a "1" bit can be stored in the memory cell by increasing the threshold voltage of the programmed SONOS transistor to a substantially positive Vt. Electrons trapped in the nitride layer can be removed by applying a negative gate-channel voltage (typically -7V to -12V) to the SONOS transistor, thereby lowering the threshold voltage of the SONOS transistor and erasing the contents of the memory cell. In one embodiment, a "0" bit can be stored in the memory cell using an erased SONOS transistor having substantially negative Vt. Once programmed or erased, the contents of the SONOS memory cell can be read by applying a nominal voltage to a specific combination of word lines, bit lines, and source lines and sensing whether or not current is flowing through the corresponding bit lines.

[0058] Figure 5D shows exemplary bias voltage schemes for reading, erasing, and programming 1T and 2T SONOS memory cells. Some of the bias voltages shown in Figure 5D include two entries separated by a slash ( / ). When two entries are included, the first entry corresponds to the “selection bias” and the second entry corresponds to the “deselection bias”. In some embodiments, the non-volatile memory array 104 may be divided into multiple “blocks” and / or multiple “sectors”.

[0059] When a block or sector architecture is used, the selection and deselection biases shown in Figure 5D may, in one embodiment, be applied to enabled blocks or sectors. In one embodiment, disabled blocks or sectors may also receive a deselection signal (typically 0V), except for WL in a 2T cell block architecture (WL cannot be disabled if it is connected to an accessed memory cell in an enabled block, as WL spans multiple blocks). When the memory array is not divided into blocks or sectors, the selection and deselection biases shown in Figure 5D may be applied to the entire memory array. Some of the bias voltages shown in Figure 5D are indicated by an asterisk (*). These bias voltages are illustrative and may differ in other embodiments of the invention. For example, instead of shorting SL to BL during programming and erasing, SL may be left floating.

[0060] As shown in Figure 5D, 1T and 2T SONOS memory cells can be read by applying a bias (VLIM) to the bit line (BL) while grounding the source line (SL) and SONOS word line (WLS) of the selected memory cell. The word line (WL) of the selected 2T cell can also receive an appropriate voltage bias during the read operation. This allows current to flow (or not flow) along the bit line depending on the threshold voltage (V) of the SONOS device. As will be described in more detail below, the bit line current can be sensed or "read out" by a sense amplifier. In one embodiment, a current value close to zero may indicate the presence of a "1" bit, while a substantially higher current value may indicate the presence of a "0" bit in the selected cell. In alternative embodiments of the present invention, the opposite may be true.

[0061] As shown in Figure 5D, the bias (VLIM) applied to the selected BL during the read operation is limited to avoid interference from other cells on the same BL. In one embodiment, a VLIM of about 1.2V may be provided. As further shown in Figure 5D, a power supply voltage (VPWR) is supplied to the WL of the selected 2T cell to activate the N-channel FNPASS device during the read operation. In one embodiment, a power supply voltage of about 2V may be supplied to the WL of the selected 2T cell. In other embodiments, the read current may be increased by supplying a pump bias above the power supply level to the WL of the selected 2T cell. However, it should be noted that the read bias voltages shown in Figure 5D are illustrative and should not be considered limiting to the invention.

[0062] In some embodiments, a select / deselect bias (e.g., 1.2V / 0V) may be applied to the BL of 1T and 2T memory cells, as well as to the word lines (WL) connected to the pass device (FNPASS) within the 2T cell. Alternatively, a select / deselect bias (e.g., 0V / -2V) may be applied to the WLS line of a 1T cell to select / deselect cells during read operations. The select / deselect bias may be used on the WLS line of a 1T cell, as it does not have a pass device. As shown in Figure 5D, the read bias supplied to the P well may differ between 1T and 2T cells. In one embodiment, 0V may be applied to the substrate of a 2T cell. However, a slightly negative bias (e.g., -2V) may be applied to the substrate of a 1T cell. The negative bias applied to the P well results in a gate-channel voltage of 0V for deselected memory cells. However, it should be noted that the read bias voltages mentioned herein are illustrative and may differ in other embodiments of the invention.

[0063] As shown in Figure 5D, a 1T SONOS memory cell can be erased by applying a negative voltage (VNEG) to the SONOS word line (WLS) and a positive voltage (VPOS) to the bit line (BL), source line (SL), and substrate (P-well) of the target or "selected" memory cell. The SONOS word line (WLS) of unselected memory cells in an enabled block or sector is biased by VPOS to avoid erasing the memory cells in the unselected rows.

[0064] A similar bias scheme for erasing a 2T SONOS memory cell is shown in Figure 5D. However, the 2T scheme differs from the 1T scheme in that it applies a selection / deselection bias to the word lines (WLs) connected to the path device (FNPASS) within the 2T cell. In one embodiment, VPWR may be applied to selected WLs, while 0V is applied to all deselected WLs. The selection / deselection bias applied to the WLs during erasure may be generated, for example, by a word line driver 103.

[0065] As shown in Figure 5D, a 1T SONOS memory cell can be programmed by applying a positive voltage (VPOS) to the SONOS word line (WLS) and a negative voltage (VNEG) to the bit line (BL), source line (SL), and substrate (P-well) of the selected memory cell. The SONOS word line (WLS) of unselected memory cells within an enabled block or sector is biased by VNEG to avoid programming of memory cells on unselected rows.

[0066] In some embodiments, the BL and SL of unselected memory cells may be biased (VBL) to avoid programming of memory cells that are left in an erased state. As described in more detail below, a VBL bias between 0V and VPWR may be used to suppress programming of a particular cell. In one embodiment, a VBL of about 1V may be provided.

[0067] A similar bias scheme for programming 2T SONOS memory cells is shown in Figure 5D. However, the 2T scheme differs from the 1T scheme in that it applies a VWL bias (typically 0V to VNEG) to the word lines (WLs) of all 2T cells to reduce HV damage to the SONOS device during the programming operation.

[0068] As further shown in Figure 5D, SONOS memory cells can be programmed and erased by applying positive (VPOS) and negative (VNEG) voltages to the gate, drain, source, and substrate terminals of the SONOS transistor. In various embodiments, SONOS memory cells can be programmed or erased in the manner described above before applying the characterization method of the embodiment.

[0069] The selection and biasing of memory cells during the characterization operation of the embodiment are the same as those during the read operation. For example, VPWR may be applied to the WL of the selected 2T cell to activate the FNPASS device, while the ground voltage (0V) is applied to the WLS of the selected 2T cell. For 1T cells, the ground voltage (0V) is applied to the WLS of the selected 1T cell.

[0070] Referring here to Figure 6, a block diagram of a processing system 600 according to one embodiment of the present invention is shown. The processing system 600 shows a general-purpose platform as well as common components and functions that can be used to carry out parts of the embodiments described herein, such as the controller 106, test controller 116, BIST 118 and / or tester 120 described with respect to Figure 1A. For example, the processing system 600 can be used to carry out some or all of the processing used to analyze the results of memory cell characterization and to determine the reference current to be applied to the memory array under test. The processing system 600 may also be used to carry out parts of the methods of the embodiments described herein with respect to Figures 2A and 2B.

[0071] The processing system 600 may include, for example, a central processing unit (CPU) 602 and a memory 604 connected to a bus 608, and may be configured to execute the processes described above in accordance with program instructions stored in the memory 604 or other non-temporary computer-readable media. The processing system 600 may further include, optionally, a display adapter 610 providing a connection to a local display 612 and an input / output (I / O) adapter 614 providing an input / output interface for one or more input / output devices 616 such as a mouse, keyboard, or flash drive.

[0072] The processing system 600 may also include a network interface 618, which may be implemented using a network adapter configured to couple to a wired link such as a network cable, a USB interface, and / or a wireless / cellular link for communication with the network 620. The network interface 618 may also include a suitable receiver and transmitter for wireless communication. It should be noted that the processing system 600 may include other components. For example, if the processing system 600 is externally implemented, it may include hardware components such as a power supply, cables, a motherboard, a removable storage medium, a case, etc. These other components are not shown but are considered part of the processing system 600. In some embodiments, the processing system 600 may be implemented on the same monolithic semiconductor integrated circuit as a single monolithic semiconductor integrated circuit and / or other disclosed system components.

[0073] Embodiments of the present invention are summarized herein. Other embodiments can also be understood from the entirety of this specification and the claims filed herein.

[0074] Example 1. A method for characterizing a non-volatile memory, the method comprising: applying a first voltage to a word line conductively coupled to a non-volatile memory cell; measuring a current flowing through the non-volatile memory cell in response to the application of the first voltage, wherein the measuring step includes: using a sense amplifier to compare the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source, applying the same first voltage on the word line; and determining the measured current based on the comparison.

[0075] Example 2. The method according to Example 1, further comprising the step of determining whether the measured current is within a predetermined range.

[0076] Example 3. The method according to Example 1 or 2, further comprising the step of replacing a non-volatile memory cell with a redundant cell when the measured current is not within a predetermined range.

[0077] Example 4. The method according to any one of Examples 1 to 3, further comprising the step of setting memory operating parameters based on a measured current, wherein the memory operating parameters include a write duration or a write voltage.

[0078] Example 5. The method according to any one of Examples 1 to 4, wherein the first voltage is the ground voltage.

[0079] Example 6. The method according to any one of Examples 1 to 5, wherein the step of measuring the current flowing through a non-volatile memory cell includes the step of iteratively adjusting the current generated by an adjustable current source.

[0080] Example 7. The method according to Example 6, wherein the step of iteratively adjusting the current generated by the adjustable current source includes the step of performing a binary search.

[0081] Example 8. The method according to Example 6 or 7, wherein the step of iteratively adjusting the current generated by an adjustable current source includes the steps of increasing the current generated by the adjustable current source when the result of the comparison shows a first comparison result, and decreasing the current generated by the adjustable current source when the result of the comparison shows a second comparison result opposite to the first comparison result.

[0082] Example 9. The method according to any one of Examples 6 to 8, wherein the step of iteratively adjusting an adjustable current source includes the step of iteratively adjusting an input word provided to a current digital-to-analog converter (CDAC).

[0083] Example 10. The method according to any one of Examples 1 to 9, wherein the non-volatile memory includes a plurality of non-volatile memory cells, and the sense amplifier includes a plurality of sense amplifier circuits configured to determine the memory state of the plurality of non-volatile memory cells.

[0084] Example 11. The method according to Example 10, further comprising the step of providing the outputs of a plurality of sense amplifier circuits to an external data bus.

[0085] Example 12. The method according to Example 10 or 11, wherein a plurality of nonvolatile memory cells are arranged in a row in a memory array, and the method further includes the step of measuring the current flowing through at least some of the nonvolatile memory cells in the row of the memory array.

[0086] Example 13. The method according to Example 12, wherein the step of measuring the current flowing through at least some of the nonvolatile memory cells in a row of a memory array includes the step of selecting the nonvolatile memory cells using a column decoder.

[0087] Example 14. A memory system comprising an integrated circuit including a memory array containing non-volatile memory cells, a plurality of word line drivers coupled to the memory array, a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus, a tunable current source coupled to the plurality of sense amplifiers, a first control circuit configured to set the tunable current source to a test current and apply a first address to the memory array to select a row of non-volatile memory cells, and a second control circuit configured to read the outputs of the sense amplifiers and iteratively update the test current based on the outputs of the sense amplifiers to determine the current flowing through at least one non-volatile memory cell in a row of non-volatile memory cells.

[0088] Example 15. The memory system according to Example 14, wherein the second control circuit is located on an integrated circuit.

[0089] Example 16. The memory system according to Example 15, wherein the second control circuit is located outside the integrated circuit.

[0090] Example 17. The memory system according to Example 15 or 16, wherein a second control circuit is configured to read the output of a sense amplifier via an external data bus.

[0091] Example 18. A memory system according to any one of Examples 14 to 17, wherein each word line driver of a plurality of word line drivers includes a first transistor coupled between a word line and a positive supply node, and a second transistor coupled between a word line and a negative supply node, wherein the word line can only be coupled to a positive supply node and a negative supply node via the first and second transistors, respectively.

[0092] Example 19. The memory system according to Example 18, further comprising a first level shifter coupled to a first transistor and a second level shifter coupled to a second transistor, wherein the word line driver does not include any further level shifting circuits other than the first and second level shifters.

[0093] Example 20. A memory system according to any one of Examples 14 to 19, wherein the adjustable current source includes a current DAC.

[0094] Example 21. A memory system according to any one of Examples 14 to 20, wherein the non-volatile memory cell comprises a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

[0095] Example 22. A method for characterizing a non-volatile memory, the method comprising the steps of operating the non-volatile memory in test mode, the steps of performing a test read of the non-volatile memory, the steps of: applying a row address to the non-volatile memory to select a row of non-volatile memory cells; grounding a word line coupled to the selected row of non-volatile memory cells; measuring the current of at least one non-volatile memory cell in the row of non-volatile memory cells with the word line grounded; and incrementing the row address, and repeating the step of performing a test read using the incremented row address.

[0096] Example 23. The method according to Example 22, further comprising the steps of: applying row addresses, then applying column addresses to select a subset of rows of selected nonvolatile memory cells; measuring the current, then incrementing the column addresses before incrementing the row addresses; and repeating the step of performing test reads using the incremented column addresses after incrementing the column addresses, before incrementing the row addresses, while the selected rows of nonvolatile memory cells have not yet been fully read.

[0097] Example 24. The method according to Example 22 or 23, further comprising the steps of determining a non-functional non-volatile memory cell of a non-volatile memory based on a current measurement, or determining an operating memory parameter based on a current measurement.

[0098] Example 25. The method according to any one of Examples 22 to 24, wherein the step of measuring the current of at least one nonvolatile memory cell includes the steps of: applying a reference current to a sense amplifier coupled to at least one nonvolatile memory cell to generate a sense amplifier output; modifying the reference current based on the sense amplifier output; and repeating the steps of applying the reference current and modifying the reference current to estimate the current of at least one nonvolatile memory cell.

[0099] Example 26. The method according to Example 25, wherein the steps of applying a reference current and modifying the reference current are repeated, and are performed according to a linear search or a binary search.

[0100] Example 27. The method according to any one of Examples 22 to 26, wherein at least one nonvolatile memory cell in a row of nonvolatile memory cells comprises a nonvolatile memory cell having a maximum threshold or minimum threshold for nonvolatile memory cells in the row of nonvolatile memory cells.

[0101] While the present invention has been described with reference to exemplary embodiments, this description is not intended to be constrained. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be obvious to those skilled in the art by reference to the description. Accordingly, the appended claims are intended to encompass such modifications or embodiments.

Claims

1. A method for characterizing non-volatile memory, wherein the method is The steps include applying a first voltage to a word line conductively coupled to a non-volatile memory cell, A step of measuring the current flowing through the non-volatile memory cell in response to the application of the first voltage, Includes, The aforementioned measurement step is, The steps include using a sense amplifier to compare the current flowing through the nonvolatile memory cell with a plurality of different first currents generated by an adjustable current source, and applying the same first voltage to the word line, A step of measuring the current flowing through the non-volatile memory cell based on the above comparison, Includes, The step of measuring the current flowing through the nonvolatile memory cell includes the step of iteratively adjusting the current generated by the adjustable current source, The method further includes the step of determining whether the measured current is within a predetermined range. method.

2. The method according to claim 1, further comprising the step of replacing the nonvolatile memory cell with a redundant cell when the measured current is not within the predetermined range.

3. The method according to claim 1, further comprising the step of setting memory operating parameters based on the measured current, wherein the memory operating parameters include write duration or write voltage.

4. The method according to claim 1, wherein the first voltage is the ground voltage.

5. The method according to claim 1, wherein the step of iteratively adjusting the current generated by the adjustable current source includes the step of performing a binary search.

6. The step of iteratively adjusting the current generated by the adjustable current source is: When the result of the comparison indicates a first comparison result, the step of increasing the current generated by the adjustable current source, When the result of the comparison shows a second comparison result opposite to the first comparison result, the step of reducing the current generated by the adjustable current source, including, The method according to claim 1.

7. The method according to claim 1, wherein the step of iteratively adjusting the adjustable current source includes the step of iteratively adjusting the input word provided to a current digital-to-analog converter (CDAC).

8. The non-volatile memory includes a plurality of non-volatile memory cells, The sense amplifier includes a plurality of sense amplifier circuits configured to determine the memory state of the plurality of nonvolatile memory cells. The method according to claim 1.

9. The method according to claim 8, further comprising the step of providing the outputs of the plurality of sense amplifier circuits to an external data bus.

10. The aforementioned plurality of non-volatile memory cells are arranged in a single row within the memory array. The method further includes the step of measuring the current flowing through at least a portion of the nonvolatile memory cells in one row of the memory array, The method according to claim 8.

11. The method according to claim 10, wherein the step of measuring the current flowing through at least a portion of the nonvolatile memory cells in one row of the memory array includes the step of selecting the nonvolatile memory cells using a column decoder.

12. A memory system comprising an integrated circuit, wherein the integrated circuit is A memory array equipped with non-volatile memory cells, Multiple word line drivers coupled to the memory array, Multiple sense amplifiers coupled to the memory array and coupled to an external data bus, An adjustable current source coupled to the plurality of sense amplifiers, The first control circuit and The second control circuit and Equipped with, The first control circuit is, Set the adjustable current source to the test current, To select a row of the non-volatile memory cells, a first address is applied to the memory array. It is configured in such a way, The second control circuit is, Read the output of the sense amplifier, The test current is iteratively updated based on the output of the sense amplifier to measure the current flowing through at least one nonvolatile memory cell in the row of the nonvolatile memory cell. To determine whether the measured current is within a predetermined range, It is configured in such a way. Memory system.

13. The memory system according to claim 12, wherein the second control circuit is arranged on the integrated circuit.

14. The memory system according to claim 13, wherein the second control circuit is located outside the integrated circuit.

15. The memory system according to claim 14, wherein the second control circuit is configured to read the output of the sense amplifier via the external data bus.

16. Each of the aforementioned word line drivers is: A first transistor coupled between the word line and the positive supply node, A second transistor coupled between the word line and the negative supply node, The word line is coupled only to the positive supply node and the negative supply node via the first transistor and the second transistor, respectively. The memory system according to claim 12.

17. The aforementioned memory system A first level shifter coupled to the first transistor, A second level shifter coupled to the second transistor, The word line driver further comprises the first level shifter and the second level shifter, and does not include any further level shifting circuits other than the first level shifter and the second level shifter. The memory system according to claim 16.

18. The memory system according to claim 12, wherein the adjustable current source comprises a current DAC.

19. The memory system according to claim 12, wherein the non-volatile memory cell comprises a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

20. A method for characterizing non-volatile memory, the method comprising the step of operating the non-volatile memory in test mode, The step of operating the non-volatile memory in test mode includes the step of performing a test read of the non-volatile memory, The step of performing a test read of the non-volatile memory is: The steps include applying row addresses to nonvolatile memory to select a row of nonvolatile memory cells, The steps include: grounding the word line connected to the selected row of the non-volatile memory cell; The steps include measuring the current of at least one nonvolatile memory cell in the row of nonvolatile memory cells with the word line grounded, The steps include incrementing the row address, Includes, The step of operating the non-volatile memory in test mode includes repeating the step of performing the test read using the incremented row address, The method further includes the step of determining whether the measured current is within a predetermined range. method.

21. The aforementioned method, The steps include: applying the row address, then applying the column address to select a subset of the rows of the selected nonvolatile memory cells; After measuring the current, the step of incrementing the column address before incrementing the row address, The step of repeating the step of performing the test read using the incremented column address while the selected row of the nonvolatile memory cell has not yet been completely read, after incrementing the column address and before incrementing the row address, Further including, The method according to claim 20.

22. The aforementioned method, A step of determining a non-functional non-volatile memory cell of the non-volatile memory based on the measurement of the current, or The step of determining the operating memory parameters based on the measurement of the current. The method according to claim 20, further comprising:

23. The step of measuring the current of the at least one nonvolatile memory cell is: The steps include applying a reference current to a sense amplifier coupled to at least one non-volatile memory cell in order to generate a sense amplifier output, The steps include: modifying the reference current based on the sense amplifier output; In order to estimate the current of the at least one nonvolatile memory cell, the steps of applying the reference current and modifying the reference current are repeated, The method according to claim 20, including the method described in claim 20.

24. The method according to claim 23, wherein the step of repeating the step of applying the reference current and the step of modifying the reference current is performed according to a linear search or a binary search.

25. The method according to claim 20, wherein the at least one nonvolatile memory cell in the row of the nonvolatile memory cell includes a nonvolatile memory cell having a maximum threshold or minimum threshold for the nonvolatile memory cells in the row of the nonvolatile memory cell.

26. The second control circuit is further configured to set memory operating parameters based on the measured current, The memory operation parameters include the write duration or the write voltage. The memory system according to claim 12.

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