Semiconductor equipment

Abstract

The present invention provides a semiconductor device that is particularly useful as a power device and has reduced element resistance. Provided is a semiconductor device that comprises: an oxide semiconductor layer that includes at least one source region; and a source electrode that is arranged on the source region. The source region comprises at least: an n+ semiconductor layer; and an n++ semiconductor layer that is arranged on the n+ semiconductor layer and has a greater carrier density than the n+ semiconductor layer. The n++ semiconductor layer is an epitaxial layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device useful as a power device or the like. [Background technology]

[0002] Gallium oxide (Ga2O3) is a transparent semiconductor with a broad band gap of 4.8-5.3 eV at room temperature and absorbs almost no visible or ultraviolet light. Therefore, it is a promising material for use in optoelectronic devices and transparent electronics, particularly those operating in the deep ultraviolet region. In recent years, photodetectors, light-emitting diodes (LEDs), and transistors based on gallium oxide (Ga2O3) have been developed (see Non-Patent Document 1). According to Patent Document 4, the band gap of gallium oxide can be controlled by forming a mixed crystal with indium or aluminum, either individually or in combination, forming an extremely attractive material system as an InAlGaO-based semiconductor. Here, an InAlGaO-based semiconductor refers to In X Al Y Ga Z It exhibits the O3 property (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5) and can be viewed as part of the same material system containing gallium oxide.

[0003] Furthermore, gallium oxide (Ga2O3) has five crystal structures: α, β, γ, σ, and ε, and generally the most stable structure is β-Ga2O3. However, since β-Ga2O3 is a β-gallia structure, it differs from the crystal systems generally used in electronic materials, and is not necessarily suitable for use in semiconductor devices. In addition, the growth of β-Ga2O3 thin films requires high substrate temperatures and high vacuum levels, which increases manufacturing costs. Also, as described in Non-Patent Literature 2, β-Ga2O3 is suitable for high concentrations (e.g., 1 × 10⁻⁶). 19 / cm 3 Even the dopants (Si) mentioned above could not be used as donors unless they were annealed at high temperatures of 800°C to 1100°C after ion implantation. On the other hand, α-Ga₂O₃ has the same crystal structure as the widely used sapphire substrate, and thus is suitable for use in optoelectronic devices. Furthermore, since it has a wider band gap than β-Ga₂O₃, it is particularly useful for power devices, and accordingly, semiconductor devices using α-Ga₂O₃ as a semiconductor have been long-awaited.

[0004] Patent Documents 1 and 2 describe a semiconductor device that uses β-Ga₂O₃ as a semiconductor, and employs, as an electrode capable of obtaining ohmic characteristics compatible therewith, a two-layer structure composed of a Ti layer and an Au layer, a three-layer structure composed of a Ti layer, an Al layer and an Au layer, or a four-layer structure composed of a Ti layer, an Al layer, a Ni layer and an Au layer. In addition, Patent Document 3 describes a semiconductor device that uses β-Ga₂O₃ as a semiconductor, and employs, as an electrode capable of obtaining Schottky characteristics compatible therewith, any one of Au, Pt, or a stacked body of Ni and Au. However, when the electrodes described in Patent Documents 1 to 3 are applied to a semiconductor device using α-Ga₂O₃ as a semiconductor, there have been problems such as failure to function as a Schottky electrode or an ohmic electrode, or degradation of semiconductor characteristics due to peeling of the metal electrode from the semiconductor film. Furthermore, when the electrode configurations described in Patent Documents 1 to 3 are applied to, for example, a source electrode of a MOSFET, there has been a problem that the source contact resistance and the source resistance cannot be sufficiently reduced. [Prior Art Documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-260101 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2009-81468 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2013-12760 [Patent Document 4] International Publication No. 2014 / 050793 [Non-Patent Documents]

[0006] [Non-Patent Document 1] Jun Liang Zhao et al, "UV and Visible Electroluminescence From a Sn:Ga2O3 / n+-Si Heterojunction by Metal-Organic Chemical Vapor Deposition",IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.5 MAY 2011 [Non-Patent Document 2] Kohei Sasaki et al, "Si-Ion Implantation Doping in β-Ga2O3 and Its Application to Fabrication of Low-Resistance Ohmic Contacts", Applied Physics Express 6 (2013) 086502 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] An object of the present invention is to provide a semiconductor device with reduced element resistance. [Means for Solving the Problems]

[0008] As a result of intensive studies to achieve the above object, the present inventors have found that a semiconductor device including an oxide semiconductor layer at least including a source region, and a source electrode disposed on the source region, wherein the source region at least includes an n+-type semiconductor layer and an n++-type semiconductor layer disposed on the n+-type semiconductor layer and having a higher carrier density than the n+-type semiconductor layer, has reduced element resistance as compared with the case where the n++-type semiconductor layer is not provided, and have found that the semiconductor device thus obtained can solve the above-mentioned conventional problems. Further, after obtaining the above findings, the present inventors have conducted further studies and have completed the present invention.

[0009] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, wherein the source region at least includes an n+-type semiconductor layer and an n++-type semiconductor layer disposed on the n+-type semiconductor layer and having a carrier density higher than that of the n+-type semiconductor layer. [2] The semiconductor device according to [1], wherein the n+-type semiconductor layer and the n++-type semiconductor layer have the same crystal structure. [3] The semiconductor device according to [1] or [2], wherein the n+-type semiconductor layer and the n++-type semiconductor layer have the same main component. [4] The semiconductor device according to any one of [1] to [3], wherein the n++-type semiconductor layer is an epitaxial layer. [5] The semiconductor device according to [4], wherein the n++-type semiconductor layer is epitaxially doped. [6] The carrier density of the n++-type semiconductor layer is 1.0×10 19 / cm 3 or more, the semiconductor device according to any one of [1] to [5]. [7] The carrier density of the n+-type semiconductor layer is 1.0×10 17 / cm 3 or more and 1.0×10 19 / cm 3 less than, the semiconductor device according to any one of [1] to [6]. [8] The semiconductor device according to any one of [1] to [7], wherein the thickness of the n++-type semiconductor layer is in the range of 1 nm to 1 μm. [9] The semiconductor device according to any one of [1] to [8], wherein the thickness of the n+-type semiconductor layer is larger than the thickness of the n++-type semiconductor layer.

[10] The semiconductor device according to any one of [1] to [9], wherein the mobility of the n+-type semiconductor layer is larger than the mobility of the n++-type semiconductor layer.

[11] The semiconductor device according to any one of [1] to

[10] , wherein the n+-type semiconductor layer is an epitaxial layer.

[12] The semiconductor device according to any one of [1] to

[11] , wherein the oxide semiconductor layer further comprises a channel layer, and a gate electrode is disposed on the channel layer via a gate insulating film.

[13] The semiconductor device according to

[12] , wherein the lower end of the n++ type semiconductor layer is located above the lower end of the gate insulating film.

[14] The semiconductor device according to

[12] or

[13] , wherein the distance from the outer edge of the gate insulating film to the inner edge of the n+ type semiconductor layer is 10 μm or less.

[15] The semiconductor device according to

[12] , wherein the channel layer has a trench and at least a portion of the gate electrode is embedded in the trench.

[16] A semiconductor device according to any of [1] to

[15] above, which is a transistor.

[17] A semiconductor device described in any of [1] to

[16] above, which is a power device.

[18] A power conversion device using a semiconductor device described in any of [1] to

[17] above.

[19] A control system using a semiconductor device described in any of [1] to

[18] above. [Effects of the Invention]

[0010] According to the present invention, a semiconductor device with reduced element resistance can be provided. [Brief explanation of the drawing]

[0011] [Figure 1] This figure schematically shows a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 2] This figure schematically shows a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 3] This figure schematically illustrates a preferred manufacturing process for a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 4]This figure schematically illustrates a preferred manufacturing process for a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 5] This figure shows the results of the IV measurement in the example. [Figure 6] This figure shows the results of the IV measurement in the comparative example. [Figure 7] This is a diagram showing the configuration of a mist CVD apparatus used in this embodiment of the present invention. [Figure 8] This is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 9] This is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 10] This is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 11] This is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 12] This figure shows the simulation results in an embodiment of the present invention. [Figure 13] This figure schematically shows a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 14] This figure schematically shows a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of the present invention. [Modes for carrying out the invention]

[0012] The semiconductor device of the present invention is a semiconductor element comprising an oxide semiconductor layer including at least a source region and a source electrode disposed on the source region, characterized in that the source region includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer and having a carrier density greater than that of the n+ type semiconductor layer.

[0013] The oxide semiconductor layer is not particularly limited as long as it does not hinder the objectives of the present invention. In embodiments of the present invention, it is preferable that the semiconductor layer mainly comprises a crystalline oxide semiconductor. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In embodiments of the present invention, it is preferable that the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium, more preferably contains at least gallium, and most preferably is α-Ga2O3 or a mixed crystal thereof. According to embodiments of the present invention, even when a semiconductor with a large band gap, such as gallium oxide or a mixed crystal thereof, is used, the dielectric strength can be improved while reducing the element resistance, particularly the contact resistance. The crystal structure of the oxide semiconductor layer is also not particularly limited as long as it does not hinder the objectives of the present invention. Examples of the crystalline structure of the oxide semiconductor layer include a corundum structure, a β-gallia structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), a cubic structure, or a tetragonal structure. In embodiments of the present invention, it is preferable that the crystalline oxide semiconductor has a corundum structure, a β-gallia structure, or a hexagonal structure (e.g., an ε-type structure), and it is more preferable that it has a corundum structure. The term "main component" means that the crystalline oxide semiconductor is preferably present in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more, of the total components of the oxide semiconductor layer, and may be 100%. The thickness of the oxide semiconductor layer is not particularly limited and may be 1 μm or less, or 1 μm or more, but in embodiments of the present invention, it is preferably 10 μm or more. The surface area of ​​the semiconductor film is not particularly limited, but may be 1 mm 2 More than that is also fine, or 1mm 2 The following is also acceptable, but 10mm 2 ~300cm 2 Preferably, 100 mm 2 ~100cm 2It is more preferable that this is the case. Furthermore, the semiconductor layer is usually a single crystal, but may be polycrystalline. Also, the oxide semiconductor layer usually contains two or more semiconductor layers. The oxide semiconductor layer includes, for example, an n+ type semiconductor layer, an n- type semiconductor layer (drift layer), a p-type semiconductor layer (current blocking layer), an n- type semiconductor layer (channel layer), and an n+ type semiconductor layer and an n++ type semiconductor layer as source regions. Furthermore, the carrier density of the oxide semiconductor layer can be appropriately set by adjusting the doping amount.

[0014] The oxide semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known dopant. In embodiments of the present invention, particularly when the semiconductor layer mainly consists of a crystalline oxide containing gallium, preferred examples of the dopant include, for example, n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as magnesium, calcium, or zinc. In embodiments of the present invention, the n-type dopant is preferably at least one selected from Sn, Ge, and Si. The dopant content is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.00001 atomic% to 10 atomic% in the composition of the semiconductor layer. More specifically, the dopant concentration is usually about 1 × 10⁻⁶ 16 / cm 3 ~1 × 10 22 / cm 3 Alternatively, the concentration of the dopant may be set to, for example, approximately 1 × 10⁻⁶. 17 / cm 3 The following low concentrations may also be used. Furthermore, according to the present invention, the dopant can be approximately 1 × 10⁻⁶ 20 / cm 3 It may be included at the above high concentration. In this embodiment of the present invention, 1 × 10 17 / cm 3 It is preferable to include the carrier at the above concentrations.

[0015] The source region is not particularly limited as long as it includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer and having a higher carrier density than the n+ type semiconductor layer. The carrier density can be determined using known methods. Examples of methods for determining the carrier density include SIMS (secondary ion mass spectrometry), SCM (scanning capacitance microscopy), SMM (scanning microwave microscopy), and SRA (spread resistance measurement). The main components of the n+ type semiconductor layer and the main components of the n++ type semiconductor layer may be the same or different. In the embodiments of the present invention, it is preferable that the main components of the n+ type semiconductor layer and the main components of the n++ type semiconductor layer are the same. Furthermore, in the embodiments of the present invention, it is preferable that the n+ type semiconductor layer and the n++ type semiconductor layer have the same crystal structure, and it is more preferable that the n+ type semiconductor layer and the n++ type semiconductor layer have a corundum structure. Here, "main component" means, for example, if the main component of the n+ type semiconductor layer is gallium oxide, then it is sufficient if the atomic ratio of gallium among all metal elements in the n+ type semiconductor layer is 50% or more. In the embodiments of the present invention, the atomic ratio of gallium among all metal elements in the n+ type semiconductor layer is preferably 70% or more, more preferably 90% or more, and may be 100%. In the embodiments of the present invention, it is preferable that the n++ type semiconductor layer is an epitaxial layer, and it is more preferable that the n++ type semiconductor layer is epitaxially doped. By using the preferred n++ type semiconductor layer as described above, contact resistance can be reduced more effectively. Here, epitaxial doping refers to doping by epitaxial growth, rather than doping by ion implantation, for example. Examples of n-type dopants included in the n+-type semiconductor layer and / or the n++-type semiconductor layer include at least one n-type dopant selected from tin, germanium, silicon, titanium, zirconium, vanadium, and niobium. In embodiments of the present invention, it is preferable that the n-type dopant is at least one selected from Sn, Ge, and Si.The carrier density of the n++ type semiconductor layer is not particularly limited, as long as it is greater than the carrier density of the n+ type semiconductor layer. In this embodiment of the present invention, the carrier density of the n++ type semiconductor layer is 1.0 × 10⁻¹⁰. 19 / cm 3 Preferably, it is 6.0 × 10 19 / cm 3 It is more preferable that the carrier density of the n++ type semiconductor layer is such a preferred value. By setting the carrier density of the n++ type semiconductor layer to such a preferred value, the contact resistance can be reduced more effectively. Furthermore, the carrier density of the n+ type semiconductor layer is not particularly limited. In this embodiment of the present invention, the carrier density of the n+ type semiconductor layer is 1.0 × 10⁻⁶. 17 / cm 3 The above 1.0 × 10 19 / cm 3 It is preferable that the carrier density of the n+ type semiconductor layer be within the range of less than 1.5. By setting the carrier density of the n+ type semiconductor layer to the preferred range described above, the source resistance can be reduced more effectively. In this embodiment of the present invention, the doping method for the n+ type semiconductor layer is not particularly limited and may be diffusion or ion implantation, or it may be an epitaxial growth method. In this embodiment of the present invention, it is preferable that the mobility of the n+ type semiconductor layer is greater than the mobility of the n++ type semiconductor layer. The thickness of the n++ type semiconductor layer is not particularly limited as long as it does not hinder the objective of the present invention. In this embodiment of the present invention, it is preferable that the thickness of the n++ type semiconductor layer is in the range of 1 nm to 1 μm, and more preferably in the range of 10 nm to 100 nm. In this embodiment of the present invention, it is preferable that the thickness of the n+ type semiconductor layer is greater than the thickness of the n++ type semiconductor layer. By using the above preferred combination of the n+ type semiconductor layer and the n++ type semiconductor layer, the source contact resistance and source resistance of the semiconductor device can be reduced more effectively, thereby realizing a semiconductor device with further reduced element resistance.

[0016] The oxide semiconductor layer may be formed using known means. Examples of means for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, or ALD. In embodiments of the present invention, the means for forming the semiconductor layer is preferably MOCVD, mist CVD, mist epitaxy, or HVPE, and preferably mist CVD or mist epitaxy. In the mist CVD or mist epitaxy method, for example, using the mist CVD apparatus shown in Figure 7, the raw material solution is atomized (atomization step), the droplets are suspended, and after atomization, the obtained atomized droplets are transported to the substrate using a carrier gas (transport step), and then the atomized droplets are subjected to a thermal reaction near the substrate to deposit a semiconductor film mainly composed of a crystalline oxide semiconductor on the substrate (film formation step), thereby forming the semiconductor layer.

[0017] (Atomization process) The atomization step atomizes the raw material solution. The atomization means for the raw material solution is not particularly limited as long as it can atomize the raw material solution, and any known means may be used. However, in the embodiments of the present invention, an atomization means using ultrasound is preferred. The atomized droplets obtained using ultrasound are preferred because they have zero initial velocity and float in the air. For example, they are mist that can be transported as a gas while floating in space, rather than being sprayed like a spray, so there is no damage due to collision energy, making them very suitable. The droplet size is not particularly limited and may be several millimeters in size, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0018] (Raw material solution) The raw material solution is not particularly limited as long as it contains raw materials that can be atomized or dropletized and that can form a semiconductor film, and may be inorganic or organic materials. In embodiments of the present invention, the raw materials are preferably metals or metal compounds, and more preferably contain one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.

[0019] In embodiments of the present invention, the raw material solution can preferably be a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or a salt. Examples of complexes include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of salts include organometallic salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphorylate salts, and metal halide salts (e.g., metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0020] Furthermore, it is preferable to mix additives such as hydrohalic acid and oxidizing agents into the raw material solution. Examples of hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid, but hydrobromic acid or hydroiodic acid are preferred because they can more efficiently suppress the generation of abnormal particles. Examples of oxidizing agents include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, as well as organic peroxides such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozonated water, peracetic acid, and nitrobenzene.

[0021] The raw material solution may contain a dopant. By including a dopant in the raw material solution, doping can be performed effectively. The dopant is not particularly limited as long as it does not hinder the objectives of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The dopant content can be appropriately determined by using a calibration curve that shows the relationship between the concentration of the dopant in the raw material and the desired carrier density.

[0022] The solvent of the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the embodiments of the present invention, it is preferable that the solvent contains water, and more preferably that it is water or a mixed solvent of water and alcohol.

[0023] (Conveying process) In the transport process, the atomized droplets are transported into the film-forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not hinder the objective of the present invention, and suitable examples include inert gases such as oxygen, ozone, nitrogen, and argon, or reducing gases such as hydrogen gas and foaming gas. There may be one type of carrier gas, or there may be two or more types, and a dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) may be used as a second carrier gas. There may also be two or more locations for supplying the carrier gas, not just one. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0024] (Film forming process) In the film formation process, the semiconductor film is formed on the substrate by thermally reacting the atomized droplets near the substrate. The thermal reaction only needs to involve the reaction of the atomized droplets with heat, and the reaction conditions are not particularly limited as long as they do not hinder the objective of the present invention. In this process, the thermal reaction is usually carried out at a temperature above the evaporation temperature of the solvent, but a temperature that is not too high (e.g., 1000°C) or lower is preferred, 650°C or lower is more preferred, and 300°C to 650°C is most preferred. The thermal reaction may be carried out under any of the following conditions, as long as it does not hinder the objective of the present invention: under vacuum, under a non-oxygen atmosphere (e.g., under an inert gas atmosphere), under a reducing gas atmosphere, or under an oxygen atmosphere, but it is preferred to carry it out under an inert gas atmosphere or an oxygen atmosphere. It may also be carried out under any of the following conditions: under atmospheric pressure, under pressurized pressure, or under reduced pressure, but in the embodiments of the present invention, it is preferred to carry it out under atmospheric pressure. The film thickness can be set by adjusting the film formation time.

[0025] (Base) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not hinder the objective of the present invention, and may be a known substrate, an organic compound or an inorganic compound. The shape of the substrate may be any shape and is effective for any shape, such as a plate shape such as a flat plate or disc, a fibrous shape, a rod shape, a cylindrical shape, a prismatic shape, a tubular shape, a spiral shape, a spherical shape, a ring shape, etc., but in the embodiments of the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the embodiments of the present invention.

[0026] The substrate is plate-shaped and is not particularly limited as long as it serves as a support for the semiconductor film. It may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but it is preferable that the substrate is an insulating substrate, and it is also preferable that the substrate has a metal film on its surface. Examples of the substrate include a base substrate mainly composed of a substrate material having a corundum structure, a base substrate mainly composed of a substrate material having a β-gallia structure, and a base substrate mainly composed of a substrate material having a hexagonal crystal structure. Here, "main component" means that the substrate material having the specific crystal structure is preferably present in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the substrate material, and may be 100%.

[0027] The substrate material is not particularly limited and may be a known material, as long as it does not hinder the objectives of the present invention. Examples of substrate materials having the corundum structure include, for example, α-Al2O3 (sapphire substrate) or α-Ga2O3, with a-plane sapphire substrates, m-plane sapphire substrates, r-plane sapphire substrates, c-plane sapphire substrates, and α-type gallium oxide substrates (a-plane, m-plane, or r-plane) being more preferred examples. Examples of underlayment substrates mainly composed of substrate materials having a β-gallia structure include β-Ga2O3 substrates, or mixed crystal substrates containing Ga2O3 and Al2O3, where Al2O3 is more than 0 wt% and 60 wt% or less. Examples of underlayment substrates mainly composed of substrate materials having a hexagonal structure include SiC substrates, ZnO substrates, and GaN substrates.

[0028] In embodiments of the present invention, an annealing treatment may be performed after the film formation step. The annealing treatment temperature is not particularly limited as long as it does not hinder the objective of the present invention, and is usually 300°C to 650°C, preferably 350°C to 550°C. The annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing treatment may be performed under any atmosphere as long as it does not hinder the objective of the present invention. It may be under a non-oxygen atmosphere or an oxygen atmosphere. Examples of non-oxygen atmospheres include an inert gas atmosphere (e.g., a nitrogen atmosphere) or a reducing gas atmosphere, but in embodiments of the present invention, an inert gas atmosphere is preferred, and a nitrogen atmosphere is more preferred.

[0029] Furthermore, in embodiments of the present invention, the semiconductor film may be provided directly on the substrate, or it may be provided via other layers such as a stress relaxation layer (e.g., a buffer layer, an ELO layer, etc.) or a delamination sacrificial layer. The means for forming each layer are not particularly limited and may be known means, but in embodiments of the present invention, the mist CVD method is preferred.

[0030] In embodiments of the present invention, the semiconductor film may be used as the semiconductor layer in a semiconductor device after being peeled off from the substrate or the like by known means, or it may be used as the semiconductor layer in a semiconductor device as is.

[0031] The source electrode is not particularly limited as long as it is conductive and does not hinder the objectives of the present invention. The constituent material of the source electrode may be a conductive inorganic material or a conductive organic material. In embodiments of the present invention, it is preferable that the material of the source electrode is a metal. Suitable metals include, for example, at least one metal selected from groups 4 to 10 of the periodic table. Examples of metals from group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals from group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals from group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals from group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). In embodiments of the present invention, it is preferable that the source electrode contains at least one metal selected from titanium (Ti), tantalum (Ta), and tungsten (W). In embodiments of the present invention, the source electrode may also contain a conductive metal oxide. Examples of conductive metal oxides contained in the source electrode include metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO). The source electrode may consist of a single layer or may contain multiple metal layers. When the source electrode includes multiple metal layers, it is preferable, for example, to use Group 4 metals of the periodic table for the first and third layers, and a Group 13 metal (e.g., Al) for the second layer located between the first and third layers. By using a source electrode with such a preferred configuration, the reliability of the ohmic characteristics between the source electrode and the source region can be further improved.The method for forming the source electrode is not particularly limited. Specific examples of the source electrode formation method include dry methods and wet methods. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating.

[0032] In embodiments of the present invention, it is preferable that the oxide semiconductor layer further includes a channel layer, and that a gate electrode is disposed on the channel layer via the gate insulating film. The constituent material of the channel layer may be the same as the constituent material of the oxide semiconductor layer described above. Furthermore, the conductivity type of the channel layer is not particularly limited and may be n-type or p-type. When the conductivity type of the channel layer is n-type, suitable constituent materials for the channel layer include, for example, α-Ga2O3 or a mixed crystal thereof. When the conductivity type of the channel layer is p-type, suitable constituent materials for the channel layer include, for example, α-Ga2O3 or a mixed crystal containing a p-type dopant, or a metal oxide containing at least one metal selected from Group 9 of the periodic table (e.g., α-Ir2O3, α-Cr2O3, α-Rh2O3). Note that the metal oxide containing at least one metal selected from Group 9 of the periodic table may be a mixed crystal with other metal oxides such as Ga2O3.

[0033] The constituent material of the gate insulating film is not particularly limited and may be a known material. Examples of materials for the gate insulating film include SiO2 film, polysilicon film, phosphorus-doped SiO2 film (PSG film), boron-doped SiO2 film, phosphorus-boron-doped SiO2 film (BPSG film), etc. Examples of methods for forming the gate insulating film include CVD method, atmospheric pressure CVD method, plasma CVD method, mist CVD method, etc. In this embodiment of the present invention, it is preferable that the method for forming the gate insulating film is mist CVD method or atmospheric pressure CVD method. Furthermore, the constituent material of the gate electrode is not particularly limited and may be a known electrode material. Examples of constituent materials for the gate electrode include the constituent materials of the source electrode described above. The method for forming the gate electrode is not particularly limited. Specific examples of methods for forming the gate electrode include dry methods and wet methods. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating. In this embodiment of the present invention, it is preferable that the lower end of the n++ layer is located above the lower end of the gate insulating film, as this allows for a better reduction in the element resistance of the semiconductor device. Furthermore, in this embodiment of the present invention, it is preferable that the distance from the outer end of the gate insulating film to the inner end of the n+ type semiconductor layer is 10 μm or less, and more preferably 5 μm or less. This preferred configuration allows for a further reduction in source resistance.

[0034] The semiconductor device of the present invention is useful for various semiconductor elements, and is particularly useful for power devices. Semiconductor elements can be classified into horizontal elements (horizontal devices) in which electrodes are formed on one side of the semiconductor layer and current flows perpendicular to the thickness direction of the semiconductor layer, and vertical elements (vertical devices) in which electrodes are formed on both the front and back sides of the semiconductor layer and current flows in the thickness direction of the semiconductor layer. In the embodiments of the present invention, the semiconductor element can be suitably used as both a horizontal and a vertical device, but its use as a vertical device is particularly preferred. Examples of the semiconductor element include metal-semiconductor field-effect transistors (MESFETs), high electron-mobility transistors (HEMTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), electrostatic induction transistors (SITs), junction field-effect transistors (JFETs), or insulated-gate bipolar transistors (IGBTs). In the embodiments of the present invention, the semiconductor device is preferably a MOSFET, SIT, JFET, or IGBT, and more preferably a MOSFET or IGBT.

[0035] The following describes preferred examples of the semiconductor device with reference to the drawings, but the present invention is not limited to these embodiments. In the semiconductor device illustrated below, other layers (e.g., insulating layers, semi-insulating layers, conductive layers, semiconductor layers, buffer layers, or other intermediate layers) may be included, as long as they do not hinder the objective of the present invention, and buffer layers may also be omitted as appropriate.

[0036] Figure 1 shows the main part of a metal-oxide-semiconductor field-effect transistor (MOSFET), which is one of the preferred embodiments of the present invention. The MOSFET in Figure 1 comprises a drain electrode 5c, an n+ type semiconductor layer 3, an n- type semiconductor layer 7 as a drift layer, a p- type semiconductor layer 2 as a current-blocking layer, a channel layer 6, an n+ type semiconductor layer and an n++ type semiconductor layer 1b as source regions, a gate insulating film 4, a gate electrode 5a, and a source electrode 5b. The n++ type semiconductor layer 1b is an epitaxial layer and is formed on the n+ type semiconductor layer 1a by epitaxial growth. Here, the n+ type semiconductor layer 3, the n- type semiconductor layer 7, the channel layer 6, the p-type semiconductor layer 2, the n+ type semiconductor layer 1a, and the n++ type semiconductor layer 1b constitute an oxide semiconductor layer 8. The carrier density of the n+ type semiconductor layer 1a is 1.0 × 10⁻¹⁶ 18 / cm 3 The above 1.0 × 10 19 / cm 3 It is within the range of less than 10. Furthermore, the carrier density of the n++ type semiconductor layer 1b is 1.0 × 10 19 / cm 3 The above, preferably 1.0 × 10 19 / cm 3 ~1.0×10 20 / cm 3 It is within the range. Note that the p-type semiconductor layer 2 is a high-resistivity layer (for example, with a resistivity of 1.0 × 10⁻⁶). 10 It may be Ω·cm or more. In this embodiment of the present invention, an epitaxial layer in which an n++ type semiconductor layer 1b is epitaxially doped is used as the source region 1, so a high concentration (for example, 1.0 × 10) 19 / cm 3The n++ type semiconductor layer 1b described above can be realized. Therefore, even when using materials that are difficult to achieve high carrier density by ion implantation, such as gallium oxide (especially α-Ga2O3), the source contact resistance can be reduced. In this embodiment of the present invention, an n+ type semiconductor layer and an n++ type semiconductor layer 1b epitaxially grown on the n+ type semiconductor layer are used as the source region 1. With this configuration, the source resistance of the entire source region can be reduced. In this embodiment of the present invention, it is preferable to make the mobility of the n+ type semiconductor layer greater than the mobility of the n++ type semiconductor layer. With this preferred configuration, the source resistance of the source region can be reduced more effectively. In this embodiment of the present invention, it is preferable that the distance a from the outer end of the gate insulating film 4 to the inner end of the n+ type semiconductor layer 1a is 10 μm or less, and more preferably 5 μm or less. With this preferred configuration, the source resistance can be reduced even further. In addition, as another preferred embodiment, in the semiconductor device shown in Figure 1, at least a portion of the n+ type semiconductor layer 1a and / or the n++ type semiconductor layer 1b may be embedded within the channel layer 6. An example in which the n+ type semiconductor layer 1a and the n++ type semiconductor layer 1b are embedded within the channel layer 6 is shown in Figure 13. According to the structure shown in Figure 13, electric field concentration in the electric field applied to the gate insulating film is less likely to occur, and the reliability of the gate insulating film can be further improved. Furthermore, an example in which the n+ type semiconductor layer 1a is embedded within the channel layer 6 is shown in Figure 14.

[0037] Figure 2 shows the main part of a metal-oxide-semiconductor field-effect transistor (MOSFET), which is one of the preferred embodiments of the present invention. The MOSFET in Figure 2 differs from the MOSFET in Figure 1 in that the channel layer 6 has a trench, and at least a portion of the gate electrode 5a is embedded in the trench. In this embodiment of the present invention, the source region 1 is an epitaxial layer in which the n++ type semiconductor layer 1b is epitaxially doped, thus allowing for higher concentrations (e.g., 1.0 × 10⁻⁶). 19 / cm 3The n++ type semiconductor layer 1b described above can be realized. Therefore, even when using materials that are difficult to achieve high concentrations by ion implantation, such as gallium oxide (especially α-Ga2O3), the source contact resistance can be reduced. Furthermore, in this embodiment of the present invention, an n+ type semiconductor layer and an n++ type semiconductor layer 1b epitaxially grown on the n+ type semiconductor layer are used as the source region 1. With this configuration, the source resistance of the entire source region can be further reduced. In this embodiment of the present invention, it is preferable to make the mobility of the n+ type semiconductor layer greater than the mobility of the n++ type semiconductor layer. With this preferred configuration, the source resistance of the source region can be reduced more effectively.

[0038] The means for forming each layer in Figures 1 and 2 are not particularly limited and may be known means, as long as they do not hinder the objective of the present invention. Examples include methods for forming a film by vacuum deposition, CVD, sputtering, or various coating techniques followed by patterning by photolithography, or methods for directly patterning using printing techniques.

[0039] The present invention will be described in more detail below using a preferred example for manufacturing the semiconductor device shown in Figure 1. Figure 3(a) shows a laminated structure in which an n+ type semiconductor layer 3, an n- type semiconductor layer 7, and a p-type semiconductor layer 2 are stacked in this order on a substrate 9. The p-type semiconductor layer 2 may be a high-resistance layer. The p-type semiconductor layer 2 is patterned using a known patterning technique. The laminate shown in Figure 3(b) is obtained by forming a channel layer 6, an n+ type semiconductor layer 1a as a source region, and an n++ type semiconductor layer 1b on the laminate shown in Figure 3(a). The n+ type semiconductor layer 1a and the n++ type semiconductor layer 1b are patterned by forming them using an epitaxial growth method such as mist CVD, and then etching them using a known etching technique. Next, the laminate shown in Figure 3(c) is obtained by forming a gate insulating film 4 and a gate electrode 5a on the laminate shown in Figure 3(b). The gate insulating film 4 and gate electrode 5a can be formed into the shape shown in Figure 3(c) by first depositing them using a known film deposition method and then etching them using a known etching technique.

[0040] Next, a source electrode 5b is formed on the laminate of Figure 3(c) using a known film deposition method to obtain the laminate of Figure 4(d). The film deposition method for the source electrode 5b includes the dry method or wet method described above. Then, after removing the substrate 9 from the laminate of Figure 4(d), a drain electrode 5c is formed using a known film deposition method to obtain the semiconductor device of Figure 4(d). As described above, the semiconductor device of Figure 4(d) includes an n+ type semiconductor layer 1a and an n++ type semiconductor layer 1b arranged on the n+ type semiconductor layer 1a, and the n++ type semiconductor layer is an epitaxial layer, thus reducing the device resistance (especially the source contact resistance).

[0041] The effects of the semiconductor device according to an embodiment of the present invention were verified using device simulation. The simulated semiconductor device is the one shown in Figure 1. The carrier densities of the n+ type semiconductor layer and the n++ type semiconductor layer were set to 1.0 × 10⁻⁶, respectively. 18 / cm 3and 2.0 × 10 19 / cm 3 The mobility of the n+ type semiconductor layer and the n++ type semiconductor layer were set to 20 cm², respectively. 2 / Vs and 0.0001cm 2 The calculations were performed under the conditions that / Vs, the thickness of the n+ type semiconductor layer, and the n++ type semiconductor layer were 150 nm and 50 nm, respectively. The calculations assumed that both the n+ type and n++ type semiconductor layers were made of gallium oxide. The results are shown in Figure 12. Figure 12(a) shows the current density distribution when the gate voltage is 20 V and the drain voltage is 1 V, and Figure 12(b) shows the current streamlines when the gate voltage is 20 V and the drain voltage is 1 V. As is clear from Figures 12(a) and 12(b), it can be seen that contact resistance can be reduced more effectively when the carrier density of the n++ type semiconductor layer is greater than that of the n+ type semiconductor layer, and when the mobility of the n+ type semiconductor layer is greater than that of the n++ type semiconductor layer.

[0042] In this embodiment, in order to confirm the effect of the n++ layer, a semiconductor device with a structure similar to the semiconductor device shown in Figure 1 was fabricated according to the procedure described above. The configuration of Example 1 is as follows: n-type semiconductor layer 3 is an n-type semiconductor layer made of tin-doped α-Ga2O3, n+-type semiconductor layer 1a is an n+-type semiconductor layer made of tin-doped α-Ga2O3, and n++-type semiconductor layer 1b is an n++-type semiconductor layer made of tin-doped α-Ga2O3 epitaxially grown on the n+-type semiconductor layer (carrier density 1.0 × 10⁻¹⁶). 18 / cm 3The above materials were used. Furthermore, a three-layer electrode with Ti, Al, and Ti layers formed in that order was used as the source electrode. In addition, as Comparative Example 1, a semiconductor device was fabricated in the same manner as in Example 1, except that an n++ type semiconductor layer was not provided. The results of IV measurements of the semiconductor devices fabricated in Example 1 and Comparative Example 1 are shown in Figures 5 and 6. As is clear from Figures 5 and 6, the semiconductor device in the embodiment of the present invention exhibits reduced element resistance (especially source-contact resistance). For reference, the n++ type semiconductor layer in Example 1 showed a greater reduction in contact resistance compared to the case where the n++ layer was formed by ion implantation. This is a new finding obtained for the first time by fabricating a semiconductor device using gallium oxide (especially α-Ga2O3). In particular, when using α-Ga2O3, it is difficult to perform high-temperature activation treatment after ion implantation, so it was found that doping by epitaxial growth resulted in better reduction of source-contact resistance and source resistance than ion implantation.

[0043] The semiconductor device according to the above-described embodiment of the present invention can be applied to power conversion devices such as inverters and converters in order to perform the functions described above. More specifically, it can be applied as a diode built into an inverter or converter, or as a switching element such as a thyristor, power transistor, IGBT (Insulated Gate Bipolar Transistor), or MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Figure 8 is a block diagram showing an example of a control system using the semiconductor device according to the embodiment of the present invention, and Figure 9 is a circuit diagram of the same control system, which is a control system particularly suitable for installation in electric vehicles.

[0044] As shown in Figure 8, the control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506, all of which are mounted in an electric vehicle. The battery 501 is, for example, a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores power through charging at a power supply station or regenerative energy during deceleration, and can output a DC voltage necessary for the operation of the electric vehicle's drive system and electrical system. The boost converter 502 is, for example, a voltage converter equipped with a chopper circuit, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit, and output it to the drive system such as a motor. Similarly, the step-down converter 503 is a voltage conversion device equipped with a chopper circuit, but it can step down a DC voltage of, for example, 200V supplied from the battery 501 to, for example, about 12V, and output it to the electrical system, including power windows, power steering, or on-board electrical equipment.

[0045] The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor that constitutes the traction system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. This rotational driving force is transmitted to the wheels of the electric vehicle via a transmission (not shown) and the like.

[0046] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as wheel rotation speed, torque, and accelerator pedal depression (accelerator amount) from the electric vehicle while it is in motion, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 functions as a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as memory. It generates control signals using the input measurement signals and outputs them as feedback signals to the inverter 504, thereby controlling the switching operation of the switching elements. As a result, the AC voltage supplied by the inverter 504 to the motor 505 is corrected instantaneously, enabling accurate operation control of the electric vehicle and realizing safe and comfortable operation of the electric vehicle. It is also possible to control the output voltage to the inverter 504 by supplying the feedback signal from the drive control unit 506 to the boost converter 502.

[0047] Figure 9 shows the circuit configuration excluding the step-down converter 503 in Figure 8, i.e., the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is used for switching control by being employed, for example, as a Schottky barrier diode in the step-up converter 502 and the inverter 504. In the step-up converter 502, it is incorporated into a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated into a switching circuit including an IGBT to perform switching control. In addition, current stabilization is achieved by interposing an inductor (such as a coil) at the output of the battery 501, and voltage stabilization is achieved by interposing capacitors (such as electrolytic capacitors) between the battery 501, the step-up converter 502, and the inverter 504.

[0048] Furthermore, as shown by the dotted line in Figure 9, the drive control unit 506 is equipped with a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of non-volatile memory. Signals input to the drive control unit 506 are provided to the calculation unit 507, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 508 temporarily holds the calculation results from the calculation unit 507 and stores physical constants and functions necessary for drive control in the form of a table, outputting them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.

[0049] As shown in Figures 8 and 9, in the control system 500, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the switching operation of the boost converter 502, buck converter 503, and inverter 504. By using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements, the switching characteristics are significantly improved. Furthermore, by applying the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be achieved. In other words, the boost converter 502, buck converter 503, and inverter 504 can each be expected to benefit from the effects of the present invention, and the effects of the present invention can be expected in any one of these, any combination of two or more, or in any configuration including the drive control unit 506. Furthermore, the control system 500 described above can be applied not only to the control system of an electric vehicle using the semiconductor device of the present invention, but also to control systems for a wide range of applications, such as boosting or stepping down power from a DC power source, or converting DC to AC power. It is also possible to use a power source such as a solar cell as the battery.

[0050] Figure 10 is a block diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention, and Figure 11 is a circuit diagram of the same control system. This control system is suitable for installation in infrastructure equipment and home appliances that operate on power from an AC power source.

[0051] As shown in Figure 10, the control system 600 receives power supplied from an external source, such as a three-phase AC power supply (power source) 601, and includes an AC / DC converter 602, an inverter 604, a motor (to be driven) 605, and a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power supply 601 is, for example, a power generation facility of a power company (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.), and its output is supplied as AC voltage after being stepped down via a substation. Alternatively, it may be installed in a building or nearby facility in the form of a private generator, for example, and supplied via power cables. The AC / DC converter 602 is a voltage converter that converts AC voltage to DC voltage, converting the 100V or 200V AC voltage supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage conversion converts it to a commonly used desired DC voltage such as 3.3V, 5V, or 12V. If the to be driven is a motor, the conversion to 12V is performed. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, and in that case, a similar system configuration can be achieved by using an AC / DC converter with a single-phase input.

[0052] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The form of the motor 604 varies depending on the controlled object, but if the controlled object is a train, it drives the wheels; if it is factory equipment, it drives pumps and various power sources; and if it is home appliances, it drives compressors, etc. It is a three-phase AC motor that is rotationally driven by the three-phase AC voltage output from the inverter 604 and transmits that rotational driving force to the driven object (not shown).

[0053] In addition, many home appliances, for example, can be driven directly by the DC voltage output from the AC / DC converter 302 (e.g., personal computers, LED lighting equipment, video equipment, audio equipment, etc.). In such cases, the inverter 604 is not required for the control system 600, and the DC voltage is supplied to the driven object from the AC / DC converter 602, as shown in Figure 10. In this case, for example, a 3.3V DC voltage is supplied to personal computers, and a 5V DC voltage is supplied to LED lighting equipment, etc.

[0054] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotational speed and torque of the driven object, as well as the temperature and flow rate of the surrounding environment of the driven object. These measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604, controlling the switching operation of the switching element. This instantly corrects the AC voltage supplied by the inverter 604 to the motor 605, enabling accurate operation control of the driven object and achieving stable operation of the driven object. Furthermore, as described above, if the driven object can be driven with a DC voltage, it is also possible to use feedback control of the AC / DC converter 602 instead of feedback to the inverter.

[0055] Figure 11 shows the circuit configuration of Figure 10. As shown in the figure, the semiconductor device of the present invention is used for switching control by being employed, for example, as a Schottky barrier diode in the AC / DC converter 602 and inverter 604. The AC / DC converter 602 uses, for example, a Schottky barrier diode configured in a bridge circuit, and performs DC conversion by converting the negative voltage component of the input voltage to a positive voltage and rectifying it. The inverter 604 is incorporated into the switching circuit of the IGBT to perform switching control. Voltage stabilization is achieved by interposing a capacitor (such as an electrolytic capacitor) between the AC / DC converter 602 and the inverter 604.

[0056] Furthermore, as shown by the dotted line in Figure 11, the drive control unit 606 is equipped with a calculation unit 607 consisting of a CPU and a storage unit 608 consisting of non-volatile memory. Signals input to the drive control unit 606 are provided to the calculation unit 607, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 608 temporarily holds the calculation results from the calculation unit 607 and stores physical constants and functions necessary for drive control in the form of a table, outputting them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.

[0057] In such a control system 600, as with the control system 500 shown in Figures 8 and 9, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and inverter 604. By using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements, the switching characteristics are improved. Furthermore, by applying the semiconductor film and semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. In other words, the effects of the present invention can be expected in each of the AC / DC converter 602 and inverter 604, and the effects of the present invention can be expected in any one of them, a combination thereof, or in a configuration including the drive control unit 606.

[0058] Although Figures 10 and 11 illustrate the motor 605 as the target to be driven, the target to be driven is not necessarily limited to mechanically operating devices, and can be many devices that require AC voltage. The control system 600 is applicable as long as it drives the target to be driven by inputting power from an AC power source, and can be installed for drive control of infrastructure equipment (e.g., power equipment in buildings and factories, communication equipment, traffic control equipment, water and wastewater treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). [Industrial applicability]

[0059] The semiconductor device of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic equipment, and industrial materials, but is particularly useful as a power device. [Explanation of Symbols]

[0060] 1. Source area 1a n+ type semiconductor layer 1b n++ type semiconductor layer 2 p-type semiconductor layer 3 n-type semiconductor layer 4 gate insulating film 5a Shuttle bus 5b Source electrode 5c drain electrode 6-channel layer 7 n-type semiconductor layer 8. Oxide semiconductor layer 9 circuit boards 21. Film deposition equipment (mist CVD equipment) 22a Carrier gas source 22b Carrier gas (dilution) source 23a Flow control valve 23b Flow control valve 24 Mist Sources 24a Raw material solution 24b Raw material fine particles 25 Container 25a water 26. Ultrasonic transducer 27 Deposition chamber 28 Hot plate 29 Supply pipe 30 circuit boards 500 Control Systems 501 Battery (Power Supply) 502 Boost Converter 503 Step-Down Converter 504 Inverter 505 Motor (Driven object) 506 Drive Control Unit 507 Arithmetic section 508 Storage section 600 Control System 601 Three-phase AC power supply (power supply) 602 AC / DC Converter 604 Inverter 605 Motor (Driven object) 606 Drive Control Unit 607 Arithmetic section 608 Storage section

Claims

1. A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, A semiconductor device characterized in that the source region includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer, the n++ type semiconductor layer having a carrier density greater than that of the n+ type semiconductor layer, and the thickness of the n++ type semiconductor layer is in the range of 1 nm to 1 μm.

2. A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, The semiconductor device is characterized in that the source region includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer, the n++ type semiconductor layer having a carrier density greater than that of the n+ type semiconductor layer, and the thickness of the n+ type semiconductor layer is greater than the thickness of the n++ type semiconductor layer.

3. A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, The semiconductor device is characterized in that the source region includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer, the n++ type semiconductor layer having a carrier density greater than that of the n+ type semiconductor layer, and the mobility of the n+ type semiconductor layer is greater than that of the n++ type semiconductor layer.

4. A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, A semiconductor device characterized in that the source region includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer having a carrier density greater than that of the n+ type semiconductor layer, the oxide semiconductor layer further includes a channel layer, a gate electrode is disposed on the channel layer via a gate insulating film, and the lower end of the n++ type semiconductor layer is located above the lower end of the gate insulating film.

5. A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, A semiconductor device characterized in that the source region includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer having a carrier density greater than that of the n+ type semiconductor layer, the oxide semiconductor layer further includes a channel layer, a gate electrode is disposed on the channel layer via a gate insulating film, and the distance from the outer edge of the gate insulating film to the inner edge of the n+ type semiconductor layer is 10 μm or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein the n+-type semiconductor layer and the n++-type semiconductor layer have the same crystal structure.

7. The semiconductor device according to any one of claims 1 to 6, wherein the main component of the n+ type semiconductor layer and the n++ type semiconductor layer are the same.

8. The semiconductor device according to any one of claims 1 to 7, wherein the n++ type semiconductor layer is an epitaxial layer.

9. The semiconductor device according to claim 8, wherein the n++ type semiconductor layer is epitaxially doped.

10. The carrier density of the n++ type semiconductor layer is 1.0 × 10 １９ / cm ３ The semiconductor device according to any one of claims 1 to 9.

11. The carrier density of the n+ type semiconductor layer is 1.0 × 10 １７ / cm ３ The above 1.0 x 10 １９ / cm ３ A semiconductor device according to any one of claims 1 to 10, which is within the range of less than

12. The semiconductor device according to any one of claims 1 to 11, wherein the n+ type semiconductor layer is an epitaxial layer.

13. The semiconductor device according to any one of claims 1 to 3, wherein the oxide semiconductor layer further includes a channel layer, and a gate electrode is disposed on the channel layer via a gate insulating film.

14. The semiconductor device according to claim 13, wherein the channel layer has a trench, and at least a portion of the gate electrode is embedded in the trench.

15. A semiconductor device according to any one of claims 1 to 14, which is a transistor.

16. A semiconductor device according to any one of claims 1 to 15, which is a power device.

17. A power conversion device using a semiconductor device according to any one of claims 1 to 16.

18. A control system using a semiconductor device according to any one of claims 1 to 17.

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