Semiconductor equipment

Abstract

To provide a semiconductor device having high operation stability, and including laminated structure in which a metal electrode layer is laminated on a semiconductor layer made from Si.SOLUTION: A semiconductor device is provided, including: laminated structure which has rectification and in which a first metal electrode layer is laminated on a p-type semiconductor layer made of a p-type Si; and / or laminated structure which has an ohmic property and in which a second metal electrode layer is laminated on an n-type semiconductor layer made of an n-type Si. A layered chemical compound layer made of a layered chemical compound of Sb and / or Bi, and Te is interposed into between the p-type Si semiconductor layer and the first metal electrode layer and / or the n-type semiconductor layer and the second metal electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si. [Background technology]

[0002] When a silicon (Si) semiconductor layer is brought into contact with a metal layer, it can form either a "diode junction (Schottky junction)" that exhibits rectification, or an "ohmic junction" that does not. This difference depends on the size of the energy barrier between the Si semiconductor layer and the metal layer, as well as whether the Si semiconductor layer is made of p-type or n-type semiconductor, and the type of metal used in combination.

[0003] For example, Patent Document 1 discloses a semiconductor device including an MPS (Merged pin Schottky) structure in which Schottky diodes and pn-type diodes are alternately arranged on one surface of a semiconductor element, and a Schottky junction is provided in the n-type semiconductor region and an ohmic junction in the p-type semiconductor region. Here, it is stated that when SiC is used as the semiconductor substrate and a NiAl alloy is bonded to the n-type semiconductor region for Schottky bonding, the interface is unstable, and it is stated that the Schottky junction layer in the n-type semiconductor region and the ohmic junction layer in the p-type semiconductor region should be formed from different materials. Specifically, the ohmic junction layer is said to be made of an alloy containing aluminum and titanium, and the Schottky junction layer is made of a metal mainly composed of molybdenum. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2010-50267 [Overview of the project] [Problems that the invention aims to solve]

[0005] When a semiconductor layer made of Si is brought into contact with a metal layer, operational stability cannot be obtained unless the contact interface is stable, regardless of whether it is rectifying or ohmic. As mentioned above, it has been confirmed that even when using a high-melting-point metal such as molybdenum, the contact interface becomes wavy and sufficient operational stability cannot be obtained.

[0006] The present invention has been made in view of the circumstances described above, and its objective is to provide a semiconductor device with high operational stability, which includes a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si. [Means for solving the problem]

[0007] The inventors of this application focused on the fact that, for example, even with a high-melting-point metal like W, the interface where it is joined with Si does not become sufficiently flat, and as a result, it lacks operational stability in semiconductor devices, such as rectification and ohmic properties.

[0008] In other words, the semiconductor device according to the present invention is a semiconductor device comprising a laminated structure exhibiting rectification properties, wherein a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and / or a laminated structure exhibiting ohmic properties, wherein a layered compound layer made of a layered compound of Sb and / or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer, and / or between the n-type semiconductor layer and the second metal electrode layer.

[0009] These characteristics allow for the interposition of a layered compound layer that exhibits rectification and ohmic properties with respect to the semiconductor layer, and also possesses high interfacial smoothness, resulting in a semiconductor device with high operational stability.

[0010] In the invention described above, the layered compound layer may be characterized by containing an amorphous phase. With this characteristic, good interfacial smoothness can be obtained, resulting in a semiconductor device with high operational stability.

[0011] In the above-described invention, the layered compound layer may be characterized by having a thickness of 1 to 10 nm. According to this feature, a semiconductor device with high operational stability can be obtained regardless of the metal species of the metal electrode layer.

[0012] In the above-described invention, the layered compound may be (Sb x Bi 1-x )₂Te₃ (where 0<x<1). According to this feature, it is possible to obtain a semiconductor device that exhibits good rectifying properties and ohmic properties, provides good interfacial smoothness, and has high operational stability.

[0013] The p-type Si may be characterized by containing Ge in Si. Further, the n-type Si may be characterized by containing C in Si. According to this feature, a semiconductor device that exhibits good rectifying properties and ohmic properties and has high operational stability can be obtained. [Brief Description of the Drawings]

[0014] [Figure 1] It is a diagram showing a laminated structure in which a metal electrode layer is overlaid on a semiconductor layer according to the present invention. [Figure 2] It is a band diagram when (a) a metal electrode layer and (b) a layered compound layer are respectively connected to an n-type Si semiconductor. [Figure 3] It is a cross-sectional STEM (Scanning Transmission Electron Microscope) image in the vicinity of the connection interface when (a) a metal electrode layer and (b) a layered compound layer are respectively connected to a semiconductor layer. [Figure 4] It is a cross-sectional view showing the junction portion between the semiconductor layer and the layered compound layer according to the present invention. [Figure 5] It is a band diagram of Si semiconductor, Sb₂Te₃ and Bi₂Te₃. [Figure 6] It is a diagram showing the potential barrier height for n-type Si. [Figure 7] It is a graph of the heat treatment temperature and the potential barrier height of the layered compound layer joined to a p-type Si semiconductor (resistivity: 5 Ωcm). [Figure 8]This is a graph of the relationship between applied voltage and current for each of a junction structure of an n-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and a junction structure in which Sb2Te3 is formed therebetween. [Figure 9] This is a graph of the relationship between applied voltage and current for each of a junction structure of a p-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and a junction structure in which Sb2Te3 is formed therebetween. [Figure 10] This is a cross-sectional view showing the manufacturing process of a top-gate transistor that is an embodiment of the present invention. [Figure 11] This is a cross-sectional view showing the manufacturing process of a top-gate transistor that is an embodiment of the present invention. [Figure 12] This is a cross-sectional view showing the manufacturing process of a top-gate transistor that is an embodiment of the present invention. [Figure 13] This is a cross-sectional view showing the manufacturing process of a top-gate transistor that is an embodiment of the present invention. [Mode for Carrying Out the Invention]

[0015] Hereinafter, one mode for carrying out the present invention will be described in detail with reference to the drawings.

[0016] First, a method for manufacturing a semiconductor device and the obtained semiconductor device will be described along FIG. 1.

[0017] As shown in FIG. 1, first, the layered compound layer 4 made of an amorphous film composed of Sb and / or Bi and Te is formed over the semiconductor layer 2. The semiconductor layer 2 is formed of a Si semiconductor. The Si semiconductor is selected from either a p-type semiconductor made of p-type Si or an n-type semiconductor made of n-type Si. It may also be formed of a Si semiconductor containing C or Ge. Then, the metal electrode layer 3 is provided over the layered compound layer 4. As a result, the layered compound layer 4 made of a layered compound composed of Sb and / or Bi and Te is interposed between the semiconductor layer 2 and the metal electrode layer 3.

[0018] There are no particular limitations on the material of the metal electrode layer 3; for example, tungsten (W), cobalt (Co), ruthenium (Ru), etc., can be used.

[0019] The material for the layered compound layer 4 is Sb x Te 1-x , Bi x Te 1-x , (Bi x S 1-x )2Te3 is given as an example. Here 0 <x<1である。

[0020] Next, the amorphous film of the layered compound layer 4 is crystallized by heat treatment. The amorphous film is crystallized by heat treatment at an appropriate temperature to become a layered compound with a crystalline phase. As will be described later, the layered compound layer 4 may contain an amorphous phase and may not be subjected to heat treatment. Alternatively, a crystallized layered compound layer 4 can be obtained by forming the layered compound layer 4 on the semiconductor layer 2 while performing heat treatment.

[0021] The semiconductor device 1 obtained in this way includes a stacked structure of metal electrode layers / semiconductor layers, and the potential barrier height between these layers can be changed compared to the case where the metal electrode layer and the semiconductor layer are directly joined. For example, contact resistance can be reduced, or the on / off ratio of the diode current can be improved.

[0022] Referring to Figure 2(a), generally, when an n-type Si semiconductor (n-Si) is joined to a metal electrode layer 3 (W) as semiconductor layer 2, a diode junction with a high potential barrier height (BH) is formed due to the difference between the work function of the metal and the work function of the semiconductor layer, and the pinning of the Fermi level caused by metal-induced gap states (MIGS). Therefore, when a metal electrode layer 3 is joined to a semiconductor layer 2 made of n-type Si semiconductor, the contact resistance increases.

[0023] In contrast, as shown in Fig. 2(b), according to the structure of the semiconductor device 1 in the present embodiment, when the layered compound layer 4 made of Sb2Te3 is bonded to the semiconductor layer 2, the pinning position of the Fermi level differs, and the potential barrier height (BH) can be reduced. As a result, the contact resistance can be reduced compared to the case where a metal electrode layer is directly bonded to the semiconductor layer, and an ohmic junction exhibiting ohmic properties can be achieved.

[0024] Further, as shown in Fig. 3(a), in general, when the semiconductor layer 2 and the metal electrode layer 3 are bonded to each other, it is difficult to obtain a flat bonding interface. On the other hand, as shown in Fig. 3(b), in the laminated structure of the present embodiment, a bonding interface that is flat at the atomic level can be obtained between the semiconductor layer 2 and the layered compound layer 4. Note that the lower limit of the thickness of the layered compound layer 4 is about 1 nm, which is the thickness of one layer that is the minimum unit of the layered compound. In addition, the thickness of the layered compound layer 4 is preferably set to 10 nm or less so as not to excessively increase the resistance. This upper limit of the thickness is based on the fact that the resistivity of the layered compound layer 4 in the vertical direction is approximately 0.01 Ωcm. For example, as the specific contact resistivity, 10 -8 Ωcm 2 In order to obtain the following, if the resistivity in the vertical direction × film thickness = specific contact resistivity, the film thickness can be calculated to be 10 nm or less. That is, the thickness of the layered compound layer 4 is preferably in the range of 1 to 10 nm.

[0025] Further, as shown in Fig. 4, by obtaining such a flat bonding surface at the atomic level, an ideal defect-free interface can be formed as the bonding surface between the semiconductor layer 2 (Si semiconductor) and the layered compound layer 4 (Te-based layered substance). As a result, a semiconductor device with high operational stability can be obtained.

[0026] Furthermore, as shown in Fig. 5, in Si used for the semiconductor layer 2, the uppermost E of the valence band V , the lowermost E of the conduction band C There is a band gap between them. According to the example in the same figure, for n-type Si, the lowermost E of the conduction band CUsing a layered compound layer 4 with a work function close to that of is advantageous for reducing resistance, and for example, Sb2Te3 is a good choice. Also, in p-type Si, the uppermost E of the valence band V Using a layered compound layer 4 with a work function close to that of the semiconductor is advantageous for reducing resistance, and for example, Bi2Te3 is a good choice. Thus, the layered compound consisting of Sb and / or Bi and Te used in the layered compound layer 4 has a characteristic band alignment with respect to the Si semiconductor.

[0027] In particular, (Bi x S 1-x In a layered compound consisting of (Bi2Te3), when the composition ratio is changed by varying the value of x within the range of 0 to 1, the work function changes between the work function of Sb2Te3 and the work function of Bi2Te3. In other words, (Bi x S 1-x The work function of 2Te3 depends on the composition ratio with respect to the lowest conduction band E of Si, depending on the value of x. C From the vicinity, the uppermost E valence band of Si. V It is adjustable within a nearby range. Therefore, it is possible to adjust not only the electron barrier height due to contact between the semiconductor layer 2 and the metal electrode layer 3, but also in accordance with the change in this work function.

[0028] Furthermore, as shown in Figure 6, with respect to the potential barrier height for n-type Si, no material has been found that approaches the Ec (conduction band) edge, except for rare earth elements such as lanthanides. However, with the layered compound of Sb and Te used in the layered compound layer 4 of this embodiment, the potential barrier height with Si can be made close to the Ec edge, comparable to that of rare earth elements. As a result, the layered compound layer 4 made of SbTe-based compound can reduce the contact resistance between the semiconductor layer 2 made of n-type Si and the metal electrode layer 3.

[0029] As shown in Figure 7, it was found that the potential barrier height (BH) is higher when the metal layer (W) is bonded via a layered compound layer of Sb2Te3 compared to when the metal layer (W) is directly bonded to the semiconductor layer 2, which is made of a p-type Si semiconductor with a resistivity of 5 Ωcm (W / Si). Furthermore, it was confirmed that there was almost no change in the potential barrier height when the layered compound layer was formed as an amorphous film (as-deposited) and when it was heat-treated at four different heat treatment temperatures (Annealing temperature) of 100, 200, 300, and 400°C. In other words, it was found that a potential barrier height equivalent to that of the crystalline phase can be obtained even in the amorphous phase.

[0030] Furthermore, as shown in Figure 8, compared to a conventional Schottky barrier diode using a metal junction with an n-type Si semiconductor having a resistivity of 5 Ωcm, the multilayer structure according to this embodiment, using Sb2Te3 as the layered compound layer, exhibits a larger current when a reverse voltage is applied. There is almost no difference in the current when a forward voltage is applied. Thus, a lower on / off ratio can be obtained compared to conventional metal junctions. In other words, a multilayer structure with an ohmic junction and low contact resistance can be obtained.

[0031] On the other hand, as shown in Figure 9, compared to a conventional Schottky barrier diode using a metal junction with a p-type Si semiconductor having a resistivity of 5 Ωcm, the laminated structure according to this embodiment, which uses Sb2Te3 in the layered compound layer, exhibits a smaller current when a reverse voltage is applied. There is almost no difference in the current when a forward voltage is applied. Thus, a higher on / off ratio can be obtained compared to conventional metal junctions. In other words, a laminated structure with a diode junction that exhibits excellent rectification and low leakage current can be obtained.

[0032] In other words, compared to a conventional junction between a semiconductor layer and a metal electrode layer, the following can be expressed: When an SbTe-based thin film is used for the layered compound layer, contact resistance can be reduced by using an n-type Si semiconductor for the semiconductor layer, and the on / off ratio of the current can be increased by using a p-type Si semiconductor for the semiconductor layer.

[0033] Referring again to Figure 5, it is also clear that, similarly, when compared to a conventional junction between a semiconductor layer and a metal electrode layer, the following is also evident: When a BiTe-based thin film is used as the layered compound layer, contact resistance can be reduced by using a p-type Si semiconductor in the semiconductor layer, and the on / off ratio of the current can be increased by using an n-type Si semiconductor in the semiconductor layer.

[0034] As described above, these embodiments make it possible to change the potential barrier height due to contact between the semiconductor layer and the metal electrode layer.

[0035] Next, we will describe an example of manufacturing a transistor as a semiconductor device 1.

[0036] Figures 10 to 13 show the manufacturing process of a top-gate type field-effect transistor (FET), which is an example of a semiconductor device to which the above-described multilayer structure is applied.

[0037] As shown in Figure 10(a), first, an insulating film 8 is deposited on the semiconductor substrate 6 by atomic layer deposition (ALD). Then, as shown in Figure 10(b), a gate electrode layer 9 is deposited on the insulating film 8. Finally, as shown in Figure 10(c), the gate region is patterned by lithography, and the gate electrode is formed by dry etching of the gate electrode layer 9.

[0038] Subsequently, as shown in Figure 11(a), the insulating film 8 is etched, and as shown in Figure 11(b), a layered compound layer 4, which is an amorphous film made of Sb and / or Bi and Te, is deposited on the semiconductor substrate 6 with a thickness of 10 nm or less, for example by sputtering. Then, as shown in Figure 11(c), the layered compound layer 4 other than the source / drain region is removed by lithography and dry etching.

[0039] Si semiconductor is used as the material for the semiconductor substrate 6.

[0040] The insulating film 8 is made of any material; for example, oxide films such as SiO2, Al2O3, HfO2, ZrO2, Y2O3, and La2O3 can be used.

[0041] There are no particular limitations on the material of the gate electrode layer 9. For example, tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), or alloys or multilayer films containing two or more of these materials can be used.

[0042] Then, as shown in Figure 12(a), the amorphous film of the layered compound layer 4 is crystallized by heat treatment at an appropriate temperature to form a layered compound with a crystalline phase. Subsequently, as shown in Figure 12(b), an interlayer insulating film 10 is formed, and as shown in Figure 12(c), the contact holes 10' are etched.

[0043] Furthermore, as shown in Figure 13(a), a metal electrode layer 3, which will serve as a plug electrode, is formed, and as shown in Figure 13(b), the plug electrode is formed by lithography and dry etching using the metal electrode layer 3. This allows for the creation of a FET as a semiconductor device in which a layered compound layer 4 is interposed between a semiconductor layer 2 (semiconductor substrate 6) made of Si semiconductor and the metal electrode layer 3. This makes it possible to create a top-gate type field-effect transistor with reduced contact resistance. The heat treatment temperature is preferably set in the range of 100°C or higher.

[0044] In this way, by interposing a layered compound layer 4 between the semiconductor layer 2 made of Si semiconductor and the metal electrode layer 3, the contact resistance between the semiconductor layer 2 and the metal electrode layer 3 can be reduced.

[0045] The above-described layered structure can be applied to semiconductor devices such as transistors, Schottky diodes, light-emitting diodes, solar cells, thermoelectric conversion elements, and any other electronic or optical devices that have a junction between a metal electrode layer and a semiconductor layer made of Si semiconductor.

[0046] Although embodiments and modifications based thereon have been described, the present invention is not necessarily limited to these examples. Furthermore, those skilled in the art will be able to find various alternative embodiments and modifications without departing from the spirit of the present invention or the scope of the attached claims. [Explanation of Symbols]

[0047] 1 Semiconductor device 2 Semiconductor layers 3. Metal electrode layer (plug) 4-layer compound layer 6 Semiconductor substrates 8. Insulating film 9 Grid Layer 10 Interlayer insulating film

Claims

1. A semiconductor device comprising a laminated structure exhibiting rectification properties, wherein a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and / or a laminated structure exhibiting ohmic properties, wherein a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si, A semiconductor device characterized in that a layered compound layer made of a layered compound of Sb and / or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer, and / or between the n-type semiconductor layer and the second metal electrode layer.

2. The semiconductor device according to claim 1, characterized in that the layered compound layer includes an amorphous phase.

3. The semiconductor device according to claim 1 or 2, characterized in that the layered compound layer has a thickness of 1 to 10 nm.

4. The layered compound is (Sb ｘ Bi １－ｘ ) ２ Te ３ (However, the semiconductor device according to claim 1 or 2, characterized in that 0 < x < 1.)

5. The semiconductor device according to claim 4, characterized in that the p-type Si contains Ge in Si.

6. The semiconductor device according to claim 4, characterized in that the n-type Si contains C in Si.

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