Semiconductor device manufacturing method

Abstract

The present invention relates to a method for manufacturing a semiconductor device. According to one embodiment, a method for manufacturing a semiconductor device may include forming a thin film structure on a substrate, forming a through hole through the thin film structure, forming a channel layer covering at least a portion of the through hole, performing a high-pressure surface treatment process on the channel layer, and performing an insulating layer formation process on the channel layer. In one embodiment, performing the high-pressure surface treatment process may include performing a high-pressure nitridation (HPN) process.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for manufacturing a semiconductor device. BACKGROUND ART

[0002] A semiconductor device is a component mainly used in electronic circuits and similar apparatuses that utilize the electrical conduction properties of semiconductors. Semiconductors can be classified into memory semiconductors and non-memory semiconductors. Memory semiconductors can be classified into volatile memories such as DRAM and SRAM, and non-volatile memories such as Mask ROM, EP ROM, EEP ROM, and flash memory.

[0003] Figure 1 and Figure 2 illustrate a conventional manufacturing process for a semiconductor device.

[0004] First, referring to Figure 1, an insulating layer 110 and a gate layer 112 are alternately and repeatedly deposited on a substrate 100, whereby a thin film structure (TS) can be formed.

[0005] Next, a through hole (H) that penetrates the thin film structure (TS) to expose the substrate 100 can be formed. The through hole (H) may be two-dimensionally formed on the upper surface of the thin film structure (TS) from a planar perspective.

[0006] Next, a semiconductor pattern (SP) that covers at least a portion of the through hole (H) while exposing the substrate 100 can be formed. The semiconductor pattern (SP) may include a blocking layer 120 that covers at least a portion of the through hole (H), a charge storage layer 130 formed on the blocking layer 120, and a first insulating layer 140 formed on the charge storage layer 130.

[0007] Once the semiconductor pattern (SP) is formed, a channel layer 150 covering the semiconductor pattern (SP) and the substrate 100 may be formed, as shown in Figure 1. The channel layer 150 may be a semiconductor material formed using either atomic layer deposition (ALD) or chemical vapor deposition (CVD) technology. In one example, the channel layer 150 may be a polycrystalline silicon film. In one embodiment, the channel layer 150 is amorphous during deposition but can be crystallized using an annealing process or the like. In the embodiment, the channel layer 150 may be formed in such a way that it exposes the substrate 100.

[0008] Subsequently, by patterning the channel layer 150, a trench pattern (T) can be formed inside the channel layer 150.

[0009] Next, as shown in Figure 2, an insulating layer formation process is performed on the channel layer 150, which can form a second insulating layer 160 inside the trench pattern (T) of the channel layer 150. However, if the second insulating layer 160 is formed without protecting the channel layer 150 during the formation process of the insulating layer 160, a phenomenon occurs where a part of the channel layer 150, i.e., the consumable region 170, is consumed during the formation process of the second insulating layer 160.

[0010] Thus, if the thickness of the channel layer 150 is not formed to a certain level due to the occurrence of a consumable region 170 during the semiconductor device manufacturing process, the electrical characteristics of the semiconductor device (for example, V) will be affected. T Distribution (V T The distribution may become lower.

[0011] Furthermore, if a consumable region 170 is generated during the semiconductor device manufacturing process, the conformality of the channel layer 150 will decrease, affecting the electrical characteristics of the semiconductor device (for example, V T The distribution may become lower. [Overview of the project] [Problems that the invention aims to solve]

[0012] The objective of this specification is to provide a method for manufacturing a semiconductor device that can improve the electrical characteristics of the semiconductor device by reducing the wear area of ​​the channel layer and improving the isometricity of the channel layer during the process of forming the insulating layer after the channel layer has been formed.

[0013] The purposes of this specification are not limited to those mentioned above. Other purposes and advantages of this specification not mentioned can be better understood from the examples described below. Furthermore, the purposes and advantages of this specification can be achieved by the components and combinations thereof described in the claims. [Means for solving the problem]

[0014] A method for manufacturing a semiconductor device according to one embodiment may include the steps of forming a thin film structure on a substrate, forming through holes penetrating the thin film structure, forming a channel layer covering at least a portion of the through holes, performing a high-pressure surface treatment step on the channel layer, and performing an insulating layer formation step on the channel layer.

[0015] In one embodiment, the step of performing the high-pressure surface treatment step may include a step of performing an HPN (High Pressure Nitridation) step or an HPF (High Pressure Fluorination) step.

[0016] In one embodiment, the high-pressure surface treatment step can be carried out in a treatment apparatus in which a reactive gas containing nitrogen or fluorine is injected in an inert gas atmosphere.

[0017] In one embodiment, when the high-pressure surface treatment step is performed, the concentration of the reactive gas in the apparatus may be 1% or more.

[0018] In one embodiment, when the high-pressure surface treatment step is performed, the internal pressure of the processing apparatus can be maintained at 2 to 100 atmospheres.

[0019] In one embodiment, when the high-pressure surface treatment step is performed, the internal temperature of the processing apparatus can be maintained at 200 to 1000°C.

[0020] In one embodiment, a trench pattern may be formed inside the channel layer.

[0021] In one embodiment, the step of forming an insulating layer on the channel layer may form a second insulating layer inside the trench pattern.

[0022] The method for manufacturing a semiconductor device according to one embodiment may further include the step of forming a semiconductor pattern between the through hole and the channel layer.

[0023] In one embodiment, the semiconductor pattern may include a blocking layer covering at least a part of the through hole, a charge storage layer formed on the blocking layer, and a first insulating layer formed on the charge storage layer. [Effects of the Invention]

[0024] According to the method for manufacturing a semiconductor device according to the embodiment, in the manufacturing process of the semiconductor device, after the channel layer is formed and during the process of forming the insulating layer, the consumption region of the channel layer is reduced, and the conformality of the channel layer is improved. Thereby, the electrical characteristics of the semiconductor device can be improved. [Brief Description of the Drawings]

[0025] [Figure 1] It is a diagram showing a normal manufacturing process of a semiconductor device. [Figure 2] It is a diagram showing a normal manufacturing process of a semiconductor device. [Figure 3] It is a diagram showing a manufacturing process of a semiconductor device according to one embodiment. [Figure 4]This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 5] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 6] This graph shows the channel layer thickness of a semiconductor device manufactured according to a conventional semiconductor device manufacturing method, and the channel layer thickness of a semiconductor device manufactured according to one embodiment of the semiconductor device manufacturing method. [Figure 7] These graphs show the isoangularity of the channel layer of a semiconductor device manufactured according to a conventional semiconductor device manufacturing method, and the isoangularity of the channel layer of a semiconductor device manufactured according to one embodiment of the semiconductor device manufacturing method. [Modes for carrying out the invention]

[0026] The aforementioned objectives, features, and advantages will be described in detail below with reference to the accompanying drawings, so that a person with ordinary skill in the art to which this specification belongs can easily implement the embodiments of this specification. In describing this specification, if a specific description of known technology relating to this specification is deemed to obscure the gist of this specification, the detailed description will be omitted. Hereafter, preferred embodiments of this specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0027] Figures 3 to 5 show the manufacturing process of a semiconductor device according to one embodiment.

[0028] For the time being, referring to Figure 3, a thin film structure (TS) can be formed by alternately and repeatedly depositing an insulating layer 210 and a gate layer 212 onto a substrate 200.

[0029] In one embodiment, the substrate 200 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0030] In one embodiment, the insulating layer 210 may be a silicon oxide film formed by a thermal oxidation process or a silicon oxide film formed using vapor deposition technology. In one embodiment, the insulating layer 210 may have the same thickness. In other embodiments, parts of the insulating layer 210 may have different thicknesses.

[0031] In one embodiment, the gate layer 212 is a conductive material and may be a polycrystalline silicon film, but in some embodiments, it may contain a material such as silicide or polycide. In other embodiments, the gate layer 212 may contain a metallic material such as Al, Cu, or W.

[0032] In one embodiment, the insulating layer 210 and the gate layer 212 may be formed using thermal chemical vapor deposition (Thermal CVD), plasma-enhanced chemical vapor deposition (Plasma-enhanced CVD), physical chemical vapor deposition (Physical CVD), or atomic layer deposition (ALD) processes.

[0033] Next, through-holes (H) may be formed that penetrate the thin film structure (TS) to expose the substrate 200. From a planar viewpoint, the through-holes (H) may be formed two-dimensionally on the upper surface of the thin film structure (TS). Forming the through-holes (H) may include forming a first mask pattern (not shown) on the thin film structure (TS) having openings that define the region in which the through-holes (H) are formed, and anisotropically etching the thin film structure (TS) using the first mask pattern as an etching mask. The first mask pattern may be formed of a material that is selective for the insulating layer 210 and the gate layer 212. The etching process may cause the upper surface of the substrate 200 to be over-etched, resulting in a recess of the upper part of the substrate 200.

[0034] Next, a semiconductor pattern (SP) may be formed that exposes the substrate 100 while covering at least a portion of the through-hole (H). The semiconductor pattern (SP) may include a blocking layer 220 that covers at least a portion of the through-hole (H), a charge storage layer 230 formed on the blocking layer 220, and a first insulating layer 240 formed on the charge storage layer 230. The semiconductor pattern (SP) may be deposited using, for example, plasma-enhanced chemical vapor deposition (CVD), physical chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques.

[0035] Once the semiconductor pattern (SP) is formed, a channel layer 250 covering the semiconductor pattern (SP) and the substrate 200 may be formed, as shown in Figure 3. The channel layer 250 may be a semiconductor material formed using either atomic layer deposition (ALD) or chemical vapor deposition (CVD) technology. The channel layer 250 may be, for example, a polycrystalline silicon film. In one embodiment, the channel layer 250 is amorphous during deposition but can be crystallized using an annealing process or the like. In the embodiment, the channel layer 250 may be formed in such a way that it exposes the substrate 200.

[0036] In the embodiment described above, a semiconductor pattern (SP) is formed inside the through hole (H), and then a channel layer 250 is formed on the semiconductor pattern (SP). However, in other embodiments, a semiconductor pattern (SP) may not be formed inside the through hole (H), and only the channel layer 250 may be formed.

[0037] Once the channel layer 250 is formed, a trench pattern (T) may be formed inside the channel layer 250 by patterning.

[0038] Next, as shown in Figure 4, a high-pressure surface treatment process is performed on the channel layer 250, which can form a protective layer 255 inside the trench pattern (T) of the channel layer 250.

[0039] In one embodiment, the high-pressure surface treatment process performed on the channel layer 250 may include an HPN (High Pressure Nitridation) process or an HPF (High Pressure Fluorination) process.

[0040] In one embodiment, the HPN process can be carried out in a processing apparatus (e.g., a chamber or furnace) into which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0041] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0042] Examples of nitrogen-containing reactive gases include NH2 and NH3, but the types of nitrogen-containing reactive gases are not limited to these.

[0043] In one embodiment, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the processing apparatus may be 1% or more. For example, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the processing apparatus may be between 1% and 100%.

[0044] In one embodiment, when the HPN process is performed, the internal pressure of the processing apparatus can be maintained at 2 to 100 atmospheres.

[0045] In one embodiment, when the HPN process is performed, the internal temperature of the processing apparatus can be maintained at 200 to 1000°C.

[0046] In one embodiment, the HPF process can be carried out in a processing apparatus in which a reactive gas containing fluorine is injected in an inert gas atmosphere.

[0047] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0048] Examples of fluorine-containing reactive gases include CF4, C2F6, C3F8, NF3, SF6, WF6, and HF, but the types of fluorine-containing reactive gases are not limited to these.

[0049] In one embodiment, when the HPF process is performed, the concentration of the fluorine-containing reactive gas in the processing apparatus may be 1% or more. For example, when the HPF process is performed, the concentration of the fluorine-containing reactive gas in the processing apparatus may be between 1% and 100%.

[0050] In one embodiment, when the HPF process is performed, the internal pressure of the processing apparatus can be maintained at 2 to 100 atmospheres.

[0051] In one embodiment, when the HPF process is performed, the internal temperature of the processing apparatus can be maintained at 200 to 1000°C.

[0052] Next, as shown in Figure 5, when a protective layer 255 is formed inside the trench pattern (T) of the channel layer 250 by a high-pressure surface treatment process, a second insulating layer 260 can be formed inside the trench pattern (T) of the channel layer 250 by performing an insulating layer formation process on the channel layer 250. Examples of insulating layer formation processes include a vapor deposition process of an insulating material (e.g., SiOx, SiNy, etc.) or an oxidation process on the channel layer 250, but the type of insulating layer formation process is not limited to these.

[0053] During the formation of the second insulating layer 260, a portion of the channel layer 250, i.e., the consumable region 270, is consumed during the formation of the second insulating layer 260. In one embodiment, instead of immediately forming the second insulating layer 260 on top of the channel layer 250 during the formation of the second insulating layer 260, the second insulating layer 260 is formed on top of the protective layer 255. Therefore, the thickness or volume of the consumable region 270 shown in the formation process of the second insulating layer 260 according to one embodiment is less than the thickness or volume of the consumable region 170 in the normal semiconductor manufacturing process shown in Figure 2.

[0054] Furthermore, in the process of forming the second insulating layer 260, instead of immediately forming the second insulating layer 260 on top of the channel layer 250, the second insulating layer 260 is formed on top of the protective layer 255. This can improve the isogonality of the channel layer 250 compared to the normal semiconductor manufacturing process shown in Figure 2.

[0055] Thus, by forming a protective layer 255 on the channel layer 250 and then forming a second insulating layer 260, the thickness of the channel layer 250 can be maintained above a certain level, and the isogonality of the channel layer 250 can be improved compared to conventional methods. This can improve the electrical characteristics of the semiconductor device.

[0056] Figure 6 is a graph showing the channel layer thickness of a semiconductor device manufactured according to a normal semiconductor device manufacturing method, and the channel layer thickness of a semiconductor device manufactured according to one embodiment of the semiconductor device manufacturing method.

[0057] In Figure 6, M1 represents the channel layer thickness of 150 measured before the insulating layer formation process is performed on the channel layer in a conventional semiconductor device manufacturing method or in the semiconductor device manufacturing method according to one embodiment. M2 represents the channel layer thickness of 112 and the wear region thickness of 38 after the direct insulating layer formation process is performed on the channel layer in a conventional semiconductor device manufacturing method, and M3 represents the channel layer thickness of 135 and the wear region thickness of 15 after the high-pressure surface treatment process and the insulating layer formation process are performed sequentially on the channel layer in the semiconductor device manufacturing method according to one embodiment.

[0058] As shown in Figure 6, in a typical semiconductor device manufacturing method, when an insulating layer is formed on the channel layer, the channel layer is excessively worn down, causing the thickness 38 of the worn-down region to increase and the thickness 112 of the channel layer to decrease.

[0059] However, according to one embodiment of the semiconductor device manufacturing method, after a protective layer is formed on the channel layer, an insulating layer formation step is performed on the channel layer. As a result, the channel layer is not directly worn down, so the thickness 15 of the worn region becomes thinner and the thickness 135 of the channel layer becomes thicker compared to a semiconductor device manufactured using a conventional semiconductor device manufacturing method. Therefore, the thickness of the channel layer can be maintained at a constant level, and the electrical characteristics of the semiconductor device can be improved.

[0060] Figure 7 is a graph showing the conformality of the channel layer of a semiconductor device manufactured according to a conventional semiconductor device manufacturing method, and the conformality of the channel layer of a semiconductor device manufactured according to one embodiment of the semiconductor device manufacturing method.

[0061] In Figure 7, N1 represents the isometric curvature of the channel layer, measured before the insulating layer formation step is performed on the channel layer in a conventional semiconductor device manufacturing method or a semiconductor device manufacturing method according to one embodiment.

[0062] Furthermore, N2 indicates an isometric curvature of 87 in the channel layer measured after a direct insulating layer formation process is performed on the channel layer in a typical semiconductor device manufacturing method.

[0063] Furthermore, N3 represents the isoangularity of the channel layer, measured when the internal pressure of the processing apparatus is maintained at 5 atmospheres in the semiconductor device manufacturing method according to one embodiment, and the insulating layer formation process is performed after the high-pressure surface treatment process is carried out on the channel layer.

[0064] Furthermore, N4 indicates an isometric curvature of 93 in the channel layer, measured when the internal pressure of the processing apparatus is maintained at 10 atmospheres, and an insulating layer formation process is performed after a high-pressure surface treatment process is carried out on the channel layer in the semiconductor device manufacturing method according to one embodiment.

[0065] Furthermore, N5 indicates an isometric curvature of 95 for the channel layer, measured when the internal pressure of the processing apparatus is maintained at 20 atmospheres, and an insulating layer formation process is performed after a high-pressure surface treatment process is carried out on the channel layer in the semiconductor device manufacturing method according to one embodiment.

[0066] As shown in Figure 7, the isometric vertices 90, 93, and 95 of the channel layer measured after the high-pressure surface treatment step and subsequent insulating layer formation step according to one embodiment of semiconductor device manufacturing methods are higher than the isometric vertices 87 of the channel layer measured after a direct insulating layer formation step is performed on the channel layer in a normal semiconductor device manufacturing method. In other words, when the insulating layer formation step is performed after the high-pressure surface treatment step on the channel layer, the isometric vertices of the channel layer are improved compared to when the insulating layer formation step is performed directly on the channel layer. This can improve the electrical characteristics of the semiconductor device.

[0067] Furthermore, as shown in Figure 7, when a high-pressure surface treatment process is performed on the channel layer according to the semiconductor device manufacturing method of one embodiment, the isometricity of the channel layer can be improved as the atmospheric pressure inside the processing apparatus increases.

[0068] As described above, this specification has been explained with reference to the illustrative drawings, but the present invention is not limited to the embodiments and drawings disclosed herein, and various modifications can be made by someone of the ordinary skill. In addition, even if the effects of the configuration described herein are not explicitly stated and explained in the embodiments described herein, the effects that can be predicted by such configuration should also be recognized.

Claims

1. The step of forming a thin film structure on a substrate; A step of forming a through-hole that penetrates the thin film structure; A step of forming a channel layer that covers at least a portion of the through hole; A step of performing a high-pressure surface treatment process on the channel layer; and This includes a step of performing an insulating layer formation step on the channel layer, The step of performing the high-pressure surface treatment process is: The process includes a step of performing an HPN (High Pressure Nitride) process or an HPF (High Pressure Fluorination) process in a processing apparatus in which a reactive gas containing nitrogen or fluorine is injected in an inert gas atmosphere, A method for manufacturing a semiconductor device, wherein when the high-pressure surface treatment step is performed, the internal pressure of the apparatus is maintained at 2 to 100 atmospheres.

2. When the high-pressure surface treatment process is performed, the concentration of the reactive gas in the apparatus is 1% or more. A method for manufacturing a semiconductor device according to claim 1.

3. When the high-pressure surface treatment process is performed, the internal temperature of the apparatus is maintained at 200 to 1000°C. A method for manufacturing a semiconductor device according to claim 1.

4. A trench pattern is formed inside the channel layer. The high-pressure surface treatment process forms a protective layer inside the trench pattern. The insulating layer formation step for the channel layer forms a second insulating layer on the protective layer inside the trench pattern. A method for manufacturing a semiconductor device according to claim 1.

5. The process further includes the step of forming a semiconductor pattern between the through-hole and the channel layer, The aforementioned semiconductor pattern is A blocking layer covering at least a portion of the through hole; A charge storage layer formed on the blocking layer; and Including a first insulating layer formed on the charge storage layer, A method for manufacturing a semiconductor device according to claim 1.

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