Semiconductor equipment

Abstract

To reduce the manufacturing cost of a semiconductor device.SOLUTION: A semiconductor device according to the present disclosure includes a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but not including a temperature sensing diode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a manufacturing technology for the semiconductor device, and a technology for providing a chip set, and for example, relates to a technology that is effectively applied to a semiconductor device including a plurality of semiconductor chips each having a power transistor, a manufacturing technology for the semiconductor device, and a technology for providing a chip set.

Background Art

[0002] Japanese Unexamined Patent Application Publication No. 2015-2229 (Patent Document 1) describes a technology related to a semiconductor device including a semiconductor chip that includes a power transistor and a temperature sensing diode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present inventor is engaged in the manufacture and design of semiconductor devices including a plurality of semiconductor chips each including a power transistor and a temperature sensing diode. In recent years, there has been a demand for cost reduction of the above-described semiconductor devices, and in order to meet this demand, the present inventor has continued studies to realize cost reduction of the semiconductor devices. That is, in manufacturing a semiconductor device including a plurality of semiconductor chips each including a power transistor and a temperature sensing diode, a contrivance for realizing cost reduction of the semiconductor device is desired from the viewpoint of responding to market needs.

Means for Solving the Problems

[0005] In one embodiment, the semiconductor device includes a first semiconductor chip that includes a first power transistor and a temperature sensing diode, and a second semiconductor chip that includes a second power transistor but does not include a temperature sensing diode.

[0006] A method for manufacturing a semiconductor device in one embodiment includes the steps of mounting a first semiconductor chip, which includes a first power transistor and a temperature sensing diode, on a first chip mounting section, and mounting a second semiconductor chip, which includes a second power transistor but does not include a temperature sensing diode, on a second chip mounting section.

[0007] One embodiment of the method for providing a chipset comprises the steps of providing a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but not including a temperature sensing diode.

[0008] In the first semiconductor chip, the first pad is exposed within the first opening of the protective film, and the second pad is exposed within the second opening of the protective film. On the other hand, in the second semiconductor chip, the first pad and the second pad are each covered by a protective film so as not to be exposed from the protective film. [Effects of the Invention]

[0009] According to one embodiment, the manufacturing cost of a semiconductor device can be reduced. [Brief explanation of the drawing]

[0010] [Figure 1] (a) is a schematic circuit symbol showing the first power transistor and temperature sensing diode, and (b) is a schematic circuit symbol showing the second power transistor, third power transistor, and fourth power transistor, respectively. [Figure 2] This diagram shows a configuration that applies the basic concept to an improved half-bridge circuit. [Figure 3]Figure 2 is a schematic diagram showing the implementation configuration of a semiconductor device that embodies the improved half-bridge circuit and the basic concept of the half-bridge circuit. [Figure 4] This diagram schematically illustrates the heat flow generated by operating the power transistors located on each of multiple semiconductor chips. [Figure 5] This figure shows the mounting configuration of the semiconductor device in modified example 1. [Figure 6] This figure shows the mounting configuration of the semiconductor device in modified example 2. [Figure 7] This is a diagram showing the manufacturing process of a semiconductor device in an implemented form. [Figure 8] This figure shows the manufacturing process of semiconductor devices, following Figure 7. [Figure 9] This figure shows the manufacturing process of semiconductor devices, following Figure 8. [Figure 10] This figure shows the manufacturing process of semiconductor devices, following Figure 9. [Figure 11] This figure shows the manufacturing process of semiconductor devices, following Figure 10. [Figure 12] This figure shows the manufacturing process of semiconductor devices, following Figure 11. [Figure 13] (a) is a diagram showing the planar layout of the first semiconductor chip, which is an embedded chip, and (b) is a diagram showing the planar layout of the second semiconductor chip, which is a non-embedded chip. [Figure 14] (a) is a cross-sectional view taken along line AA in Figure 13(a), and (b) is a cross-sectional view taken along line BB in Figure 13(b). [Modes for carrying out the invention]

[0011] In all the drawings illustrating the embodiments, the same reference numeral is used for identical components, and repeated explanations of them are omitted. Hatching may be used even in plan views to improve clarity.

[0012] The technical idea in the present embodiment relates to a semiconductor device including a power transistor. In the present embodiment, description is given on the assumption that a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the power transistor, but the technical idea in the present embodiment is not limited thereto, and can also be applied to an aspect in which the power transistor is configured from an IGBT (Insulated Gate Bipolar Transistor).

[0013] <Configuration of General Half-Bridge Circuit> For example, a half-bridge circuit is known as a motor drive circuit for driving a motor. A general half-bridge circuit includes a DC power supply, a high-side transistor, and a low-side transistor. Specifically, the high-side transistor and the low-side transistor are connected in series to the DC power supply, and the motor is connected in parallel with the low-side transistor. In the general half-bridge circuit configured as described above, when the high-side transistor is turned on and the low-side transistor is turned off, a current flows from the power supply potential (positive potential) of the DC power supply to the reference potential (0 V) of the DC power supply via the high-side transistor and the motor. Thereby, the motor can be rotated.

[0014] On the other hand, when the high-side transistor is turned off and the low-side transistor is turned on from this state, the high-side transistor is turned off, so that no current is supplied to the motor. At this time, a back electromotive force is generated in the motor due to the parasitic inductance included in the motor, but since the low-side transistor is on, a regenerative current based on the back electromotive force flows in a loop constituted by the low-side transistor and the motor connected in parallel to each other. As a result, a regenerative brake is generated in the motor, and the motor stops quickly without idling. Note that when both the high-side transistor and the low-side transistor are turned off from a state where the high-side transistor is turned on and the low-side transistor is turned off to cause a current to flow through the motor, the motor idles and stops.

[0015] As described above, a general half-bridge circuit is configured.

[0016] Here, for example, the low-side transistor is composed of a first power transistor formed on a first semiconductor chip. Further, the high-side transistor is composed of a second power transistor formed on a second semiconductor chip separate from the first semiconductor chip.

[0017] At this time, when the power transistor is operated, the semiconductor chip generates heat. As a result, the temperature of the semiconductor chip becomes high, and there is a risk that the power transistor may be broken. For this reason, a temperature sensing diode for detecting the temperature of the semiconductor chip is formed on the semiconductor chip together with the power transistor. Thereby, the temperature of the semiconductor chip can be detected by the temperature sensing diode. Therefore, based on the temperature detected by the temperature sensing diode, the operation of the power transistor can be stopped before the temperature of the semiconductor chip rises to a temperature at which the power transistor is broken. That is, by incorporating the temperature sensing diode in the semiconductor chip on which the power transistor is formed, the semiconductor device constituted by the semiconductor chip having the power transistor can be protected.

[0018] Therefore, for example, in a semiconductor device that is a component of a general half-bridge circuit, a temperature sensing diode is formed on the first semiconductor chip together with the first power transistor, and a temperature sensing diode is formed on the second semiconductor chip together with the second power transistor. However, if the temperature sensing diodes are incorporated in both the first semiconductor chip and the second semiconductor chip included in the semiconductor device, the manufacturing cost of the semiconductor device increases.

[0019] Accordingly, in the present embodiment, a contrivance for reducing the manufacturing cost of the semiconductor device is implemented. Hereinafter, the technical idea of the present embodiment to which this contrivance is applied will be described.

[0020] <Basic Concept in the Embodiment> The basic concept in this embodiment is that the semiconductor device comprises a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but not including a temperature sensing diode. In other words, the basic concept is that in a semiconductor device having a first semiconductor chip and a second semiconductor chip, the temperature sensing diode is not provided on both the first and second semiconductor chips, but only on one of them. To put it another way, the basic concept is that in a semiconductor device comprising multiple semiconductor chips, each having a power transistor, the temperature sensing diode is built into only one semiconductor chip. According to this basic concept, it becomes unnecessary to provide a temperature sensing diode on all of the multiple semiconductor chips that make up the semiconductor device, each having a power transistor, thus reducing the manufacturing cost of the semiconductor device.

[0021] For example, if a semiconductor device having a first semiconductor chip containing a first power transistor and a temperature sensing diode, and a second semiconductor chip containing a second power transistor but not a temperature sensing diode, is a component of a half-bridge circuit, then the first power transistor is one of the high-side transistors and low-side transistors that constitute the half-bridge circuit, and the second power transistor is the other of the high-side transistors and low-side transistors that constitute the half-bridge circuit. In other words, the first semiconductor chip incorporating the temperature sensing diode may be either a low-side transistor or a high-side transistor.

[0022] According to this basic concept, since a temperature sensing diode is provided in only one of the multiple semiconductor chips, the manufacturing cost of the semiconductor devices that make up the half-bridge circuit can be reduced compared to a configuration in which a temperature sensing diode is built into all of the multiple semiconductor chips.

[0023] <Improvements to the Half-Bridge Circuit> In a typical half-bridge circuit, both the low-side and high-side transistors are comprised of a single semiconductor chip.

[0024] In this regard, for example, configuring a low-side transistor using multiple semiconductor chips, and connecting these multiple semiconductor chips (i.e., multiple power transistors formed on each of the multiple semiconductor chips) in parallel, allows for better heat dissipation when the low-side transistor is in operation, compared to configuring it using a single semiconductor chip. Similarly, configuring the high-side transistor using multiple semiconductor chips also allows for better heat dissipation when the high-side transistor is in operation. As a result, the failure of each power transistor can be suppressed, thereby improving the reliability of the semiconductor device.

[0025] <Application of the basic concept to improved half-bridge circuits> The basic concept can also be applied to the improved half-bridge circuit. That is, assuming that both the low-side transistor and the high-side transistor are composed of multiple semiconductor chips (i.e., multiple power transistors formed on multiple semiconductor chips) connected in parallel, instead of providing a temperature sensing diode on all of the multiple semiconductor chips, a temperature sensing diode is provided on only one of the multiple semiconductor chips.

[0026] This eliminates the need to provide temperature sensing diodes on all of the semiconductor chips that make up the semiconductor device, thereby reducing the manufacturing cost of the semiconductor device.

[0027] For example, consider an improved half-bridge circuit in which the low-side transistor is composed of a parallel connection of the first power transistor Q1 and the third power transistor Q3, and the high-side transistor is composed of a parallel connection of the second power transistor Q2 and the fourth power transistor Q4. Apply the basic concept to this example.

[0028] Here, the semiconductor chip on which the first power transistor Q1 is formed is referred to as the first semiconductor chip, the semiconductor chip on which the second power transistor Q2 is formed is referred to as the second semiconductor chip, the semiconductor chip on which the third power transistor Q3 is formed is referred to as the third semiconductor chip, and the semiconductor chip on which the fourth power transistor Q4 is formed is referred to as the fourth semiconductor chip.

[0029] In this case, applying the basic concept, a temperature sensing diode is built into only one of the semiconductor chips (first, second, third, and fourth), while the other three do not have a temperature sensing diode. For example, suppose the first semiconductor chip is provided with a temperature sensing diode, while the second, third, and fourth semiconductor chips are not.

[0030] Figure 1(a) is a schematic circuit symbol for the first power transistor Q1. Figure 1(a) also shows the circuit symbol for the temperature sensing diode, which is provided on the first semiconductor chip together with the first power transistor.

[0031] Here, for example, the first power transistor Q1 is composed of a power MOSFET. In this case, the first power transistor Q1 has a gate, source, and drain, and also includes a parasitic body diode in the device structure. Furthermore, a temperature sensing diode is formed on the first semiconductor chip on which the first power transistor Q1 is formed, and the temperature sensing diode has an anode and a cathode.

[0032] On the other hand, Figure 1(b) shows schematic circuit symbols for the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4. As shown in Figure 1(b), these power transistors do not have a temperature sensing diode mounted together with them, so the circuit symbol for the temperature sensing diode is not shown.

[0033] For example, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 are each composed of a power MOSFET. In this case, each power transistor has a gate, source, and drain, as well as a parasitic body diode present in the device structure.

[0034] Using the circuit symbols shown in Figure 1(a) and Figure 1(b) above, Figure 2 illustrates how the basic concept can be applied to an improved half-bridge circuit.

[0035] Figure 2 shows a configuration in which the basic concept is applied to an improved half-bridge circuit.

[0036] In Figure 2, in the improved half-bridge circuit, the low-side transistor is composed of a parallel connection of the first power transistor Q1 and the third power transistor Q3, while the high-side transistor is composed of a parallel connection of the second power transistor Q2 and the fourth power transistor Q4. Furthermore, since the low-side transistor and the high-side transistor are connected in series, the first power transistor Q1 and the second power transistor Q2 are connected in series, as are the third power transistor Q3 and the fourth power transistor Q4.

[0037] In this way, by applying the basic concept to the improved half-bridge circuit, it is possible to reduce the on-resistance through the improvement of the half-bridge and reduce the manufacturing cost of the semiconductor device through the basic concept. In other words, a semiconductor device having the configuration shown in Figure 2 can improve the performance of the semiconductor device and reduce the manufacturing cost of the semiconductor device.

[0038] The basic concept involves providing a temperature sensing diode on only one of several semiconductor chips. In this case, the placement of the semiconductor chip with the temperature sensing diode is crucial. This is because, if the semiconductor chip with the temperature sensing diode is not placed in an appropriate location, it will be impossible to properly detect the overheating state of the semiconductor device. For example, if the semiconductor chip with the temperature sensing diode can be placed at the hot spot where the temperature is highest, the overheating state of the semiconductor device can be properly detected. In other words, if the semiconductor chip with the temperature sensing diode is not placed at the hot spot, a semiconductor chip without a temperature sensing diode will be placed at the hot spot. As a result, even if this semiconductor chip reaches an overheating state, it will be difficult for the temperature sensing diode of the semiconductor chip with a built-in temperature sensing diode located elsewhere to properly detect the overheating state. Therefore, in realizing the basic concept, it is desirable to appropriately design the placement of the semiconductor chip with the temperature sensing diode. Below, we will explain an embodiment of the basic concept that takes this into consideration, with reference to the drawings.

[0039] <Method of Realization> <<Implementation configuration of semiconductor device>> Figure 3 is a schematic diagram showing the implementation configuration of a semiconductor device 100 that embodies the improved half-bridge circuit shown in Figure 2, applying the basic concept of the half-bridge circuit.

[0040] In Figure 3, the semiconductor device 100 has a chip mounting section DP1 and a chip mounting section DP2. These chip mounting sections DP1 and DP2 are arranged side by side in the X direction (second direction). That is, in a plan view, the chip mounting section DP2 is positioned next to the chip mounting section DP1 so as to be spaced apart from it. Furthermore, each of the chip mounting sections DP1 and DP2 extends in the Y direction (first direction), which intersects the X direction.

[0041] Next, a low-side transistor consisting of a parallel connection of a first power transistor Q1 and a third power transistor Q3, as shown in Figure 2, is mounted on the chip mounting section DP1. Specifically, a first semiconductor chip CHP1, on which the first power transistor Q1 and a temperature sensing diode are formed, and a third semiconductor chip CHP3, on which the third power transistor Q3 is formed but the temperature sensing diode is not, are mounted on the chip mounting section DP1. In particular, as shown in Figure 3, the first semiconductor chip CHP1 and the third semiconductor chip CHP3 are arranged to be spaced apart in the Y direction in a plan view. For example, each of the first semiconductor chip CHP1 and the third semiconductor chip CHP3 is mounted on the chip mounting section DP1 via a conductive adhesive such as solder or silver paste.

[0042] A high-side transistor consisting of a parallel connection of a second power transistor Q2 and a fourth power transistor Q4, as shown in Figure 2, is mounted on the chip mounting section DP2. Specifically, a second semiconductor chip CHP2, in which the second power transistor Q2 is formed but a temperature sensing diode is not formed, and a fourth semiconductor chip CHP4, in which the fourth power transistor Q4 is formed but a temperature sensing diode is not formed, are mounted on the chip mounting section DP2. In particular, as shown in Figure 3, the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4 are arranged to be spaced apart in the Y direction in a plan view. For example, each of the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4 is mounted on the chip mounting section DP2 via a conductive adhesive.

[0043] Next, as shown in Figure 3, the second semiconductor chip CHP2 is electrically connected to the chip mounting section DP1 via a plate-shaped member called a clip CLP1. For example, the clip CLP1 is connected to the first portion P1 of the chip mounting section DP1 via a conductive adhesive.

[0044] Similarly, the fourth semiconductor chip CHP4 is electrically connected to the chip mounting section DP1 via a plate-shaped member, a clip CLP2. For example, the clip CLP2 is connected to the second portion P2 of the chip mounting section DP1 via a conductive adhesive.

[0045] Here, in a plan view, the first semiconductor chip CHP1 is positioned between the first portion P1 of the chip mounting section DP1 to which clip CLP1 is connected and the second portion P2 of the chip mounting section DP1 to which clip CLP2 is connected. On the other hand, in a plan view, the third semiconductor chip CHP3 is positioned such that the second portion P2 of the chip mounting section DP1 is located between the first semiconductor chip CHP1 and the third semiconductor chip CHP3.

[0046] Next, in Figure 3, the semiconductor device 100 further has a conductor pattern portion CP located between the chip mounting portion DP1 and the chip mounting portion DP2 in a plan view. This conductor pattern portion CP has a first extending portion extending in the Y direction and a second extending portion extending in the X direction, and has, for example, an inverted L-shaped planar shape.

[0047] As shown in Figure 3, the first semiconductor chip CHP1 is electrically connected to the conductor pattern portion CP via a plate-shaped member called a clip CLP3. For example, the clip CLP3 is connected to the third portion P3 of the conductor pattern portion CP via a conductive adhesive.

[0048] Similarly, the third semiconductor chip CHP3 is electrically connected to the conductor pattern portion CP via a plate-shaped member, which is a clip CLP4. For example, the clip CLP4 is connected to the fourth portion P4 of the conductor pattern portion CP via a conductive adhesive.

[0049] Here, clip CLP1 straddles the second semiconductor chip CHP2 and the chip mounting area DP1 so as not to physically contact the conductor pattern area CP. Furthermore, clip CLP2 straddles the fourth semiconductor chip CHP4 and the chip mounting area DP1 so as not to physically contact the conductor pattern area CP.

[0050] As shown in Figure 3, clip CLP3 is positioned between clip CLP1 and clip CLP2 in a plan view. Also, clip CLP2 is positioned between clip CLP3 and clip CLP4 in a plan view.

[0051] Next, in Figure 3, the semiconductor device 100 further includes wide leads WLD1 and WLD2 formed integrally with the chip mounting section DP1, wide leads WLD3 and WLD4 formed integrally with the chip mounting section DP2, and a plurality of leads LD arranged to be spaced apart from the chip mounting sections DP1 and DP2, respectively. In this case, wide lead WLD1 is positioned next to the first semiconductor chip CHP1 in the X direction, while wide lead WLD2 is positioned next to the third semiconductor chip CHP3 in the X direction. Furthermore, wide lead WLD3 is positioned next to the second semiconductor chip CHP2 in the X direction, while wide lead WLD4 is positioned next to the fourth semiconductor chip CHP4 in the X direction.

[0052] Here, as shown in Figure 3, the width (width in the Y direction) of each of the wide leads WLD1, WLD2, WLD3, and WLD4 is greater than the width (width in the Y direction) of each of the multiple leads.

[0053] As described above, the semiconductor device 100 in the embodiment is implemented in this manner.

[0054] <<Characteristics of the Embodiment>> Next, I will explain the characteristic features of the embodiment.

[0055] The first characteristic feature of the implemented form is that, based on the fundamental idea of ​​providing a temperature sensing diode on only one of the multiple semiconductor chips equipped with power transistors, the semiconductor chip equipped with both a power transistor and a temperature sensing diode is placed in a location on the semiconductor device where heat generation is high. In other words, the characteristic feature is that the semiconductor chip equipped with a temperature sensing diode is placed in the location where the temperature is most likely to rise among the multiple semiconductor chips mounted.

[0056] According to the key features, even if a temperature sensing diode is provided on only one of several semiconductor chips, the overheating state of the semiconductor device can be appropriately detected by placing the semiconductor chip with the temperature sensing diode at the hot spot where the temperature is highest. As a result, it is possible to prevent the semiconductor chip from becoming too hot and destroying the power transistor. In other words, based on the temperature detected by the temperature sensing diode, the operation of the power transistor can be stopped before the temperature of the semiconductor chip rises to a temperature at which the power transistor would be destroyed. Thus, according to the key features, it is possible to improve the reliability of the semiconductor device while reducing the manufacturing cost of the semiconductor device by adopting this basic concept.

[0057] Thus, the key feature is that a semiconductor chip with a built-in temperature sensing diode is placed at the hotspot where the temperature is highest. Specifically, among the areas where multiple semiconductor chips are mounted, the area that is most likely to become hot is the region where the first semiconductor chip CHP1 is mounted in Figure 3. That is, as shown in Figure 3, in a plan view, it is the region where the first semiconductor chip CHP1 is located between the first part P1 of the chip mounting section DP1 to which clip CLP1 is connected and the second part P2 of the chip mounting section DP1 to which clip CLP2 is connected. In the following, we will explain that in the semiconductor device 100 having the mounting configuration shown in Figure 3, the above-mentioned region is the hotspot that is most likely to become hot.

[0058] Figure 4 schematically illustrates the heat flow generated by operating power transistors on multiple semiconductor chips, for example. In Figure 4, the arrows indicate heat flow, with thicker arrows representing larger heat flows. Considering this, Figure 4 shows that the tips of the arrows are concentrated in the region where the first semiconductor chip CHP1 is mounted, coming from various directions.

[0059] For example, the arrows indicating that heat generated in the second semiconductor chip CHP2 flows through clip CLP1, the arrows indicating that heat generated in the fourth semiconductor chip CHP4 flows through clip CLP2, and the arrows indicating that heat generated in the third semiconductor chip CHP3 travels through chip mounting area DP1 are all concentrated in the region where the first semiconductor chip CHP1 is mounted. Considering that the first semiconductor chip CHP1 itself also generates heat, this means that heat tends to accumulate in the region where the semiconductor chip CHP1 is mounted, and as a result, the first semiconductor chip CHP1 tends to become hot.

[0060] Therefore, in the implemented embodiment, a temperature sensing diode is mounted on the first semiconductor chip CHP1, which is mounted in the region between the first part P1 and the second part P2. In other words, as shown in Figure 4, the region between the first part P1 and the second part P2 is the hot spot where the temperature is highest, and the first semiconductor chip CHP1 with the temperature sensing diode is placed in this hot spot. As a result, according to the implemented embodiment, the hot spot of the semiconductor device 100 can be monitored by the temperature sensing diode. In other words, according to the implemented embodiment, the overheating state of the semiconductor device 100 can be appropriately grasped. As a result, according to the semiconductor device 100 in the implemented embodiment, it is possible to suppress the destruction of the power transistor provided on the first semiconductor chip CHP1 placed in the hot spot.

[0061] Next, a second characteristic feature of the embodiment is that, as shown in Figures 3 and 4, for example, a wide lead is provided next to each of the multiple semiconductor chips in the X direction. In other words, the second characteristic feature is that there is a wide lead corresponding to each of the multiple semiconductor chips, and that each of the multiple semiconductor chips and the wide lead are aligned in a straight line in the X direction. For example, in Figures 3 and 4, a wide lead WLD1 is located next to the first semiconductor chip CHP1, while a wide lead WLD2 is located next to the third semiconductor chip CHP3. Similarly, in Figures 3 and 4, a wide lead WLD3 is located next to the second semiconductor chip CHP2, while a wide lead WLD4 is located next to the fourth semiconductor chip CHP4.

[0062] Here, the width of the wide lead in the Y direction is greater than the width of the lead LD in the Y direction. As a result, according to the second feature point, as shown in Figure 4, the heat generated in each of the multiple semiconductor chips can be efficiently dissipated from the wide lead with a larger Y-direction width that is placed next to it. As a result, depending on the embodiment, the reliability of the semiconductor device 100 can be improved.

[0063] <<Example 1>> Figure 5 shows the mounting configuration of the semiconductor device 100A in this modified example 1.

[0064] As shown in Figure 5, in semiconductor device 100A, the distance between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 mounted on the chip mounting section DP1 is greater than the distance between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 in the embodiment shown in Figure 3. In particular, as shown in Figure 5, in this modified example 1, in a plan view, there is a first part connecting the clip CLP1 and the chip mounting section DP1, and a second part connecting the clip CLP2 and the chip mounting section DP1 between the first semiconductor chip CHP1 and the third semiconductor chip CHP3. In this case, the first semiconductor chip CHP1 is provided with a power transistor and a temperature sensing diode, while the second semiconductor chip CHP2, the third semiconductor chip CHP3, and the fourth semiconductor chip CHP4 are provided with power transistors but not with temperature sensing diodes.

[0065] Thus, the basic concept in this embodiment can be embodied not only as shown in the embodiment shown in Figure 3, but also, for example, as shown in the modified example 1 in Figure 5.

[0066] <<Modification 2>> In the improved half-bridge circuit, the low-side transistor is composed of a parallel connection of power transistors provided on each of the multiple semiconductor chips, and the high-side transistor is composed of a parallel connection of power transistors provided on each of the multiple semiconductor chips. In this embodiment, the above-described example uses two semiconductor chips as the multiple semiconductor chips. Specifically, as shown in Figure 3, the low-side transistor is composed of a parallel connection of power transistors provided on the first semiconductor chip CHP1 and the third semiconductor chip CHP3, and the high-side transistor is composed of a parallel connection of power transistors provided on the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4.

[0067] In this modification, we will describe an example in which three semiconductor chips are used as multiple semiconductor chips. For example, the low-side transistor is composed of a parallel connection of power transistors provided on the first semiconductor chip CHP1, the third semiconductor chip CHP3, and the fifth semiconductor chip CHP5, respectively, and the high-side transistor is composed of a parallel connection of power transistors provided on the second semiconductor chip CHP2, the fourth semiconductor chip CHP4, and the sixth semiconductor chip CHP6, respectively.

[0068] Figure 6 shows the mounting configuration of the semiconductor device 100B in this modified example 2.

[0069] In Figure 6, the chip mounting section DP1 is equipped with three semiconductor chips: the first semiconductor chip CHP1, the third semiconductor chip CHP3, and the fifth semiconductor chip CHP5. On the other hand, the chip mounting section DP2 is equipped with three semiconductor chips: the second semiconductor chip CHP2, the fourth semiconductor chip CHP4, and the sixth semiconductor chip CHP6.

[0070] As shown in Figure 6, in a plan view, the first semiconductor chip CHP1 is provided between a first portion P1 that connects the clip CLP1 and the chip mounting portion DP1, and a second portion P2 that connects the clip CLP2 and the chip mounting portion DP1.

[0071] Similarly, in a plan view, the fifth semiconductor chip CHP5 is located between the fifth portion P5, which connects the clip CLP5 and the chip mounting portion DP1, and the first portion P1, which connects the clip CLP1 and the chip mounting portion DP1.

[0072] Furthermore, as shown in Figure 6, in a plan view, clip CLP6 is provided between clip CLP5 and clip CLP1, connecting the fifth semiconductor chip CHP5 and the sixth portion P6 of the conductor pattern CP. Similarly, in a plan view, clip CLP3 is provided between clip CLP1 and clip CLP2, connecting the first semiconductor chip CHP1 and the third portion P3 of the conductor pattern CP.

[0073] In Figure 6, the first semiconductor chip CHP1 is located between the first part P1 and the second part P2, and the fifth semiconductor chip CHP5 is located between the fifth part P5 and the first part P1. Therefore, not only the first semiconductor chip CHP1 but also the fifth semiconductor chip CHP5 is located in a hot spot where the temperature becomes high.

[0074] Therefore, from the viewpoint of providing temperature sensing diodes on semiconductor chips placed at hot spots, for example, not only may a power transistor and temperature sensing diode be provided on the first semiconductor chip CHP1, but a power transistor and temperature sensing diode may also be provided on the fifth semiconductor chip CHP5. This allows each of the multiple hot spots in the semiconductor device 100B having multiple hot spots to be monitored by a temperature sensing diode, thereby improving the reliability of the semiconductor device 100B.

[0075] Furthermore, in Figure 6, the first semiconductor chip CHP1 is not only located between the first part P1 and the second part P2, but also positioned between the fifth semiconductor chip CHP5 and the third semiconductor chip CHP3. Therefore, the first semiconductor chip CHP1 is affected by both the heat generated by the third semiconductor chip CHP3 and the heat generated by the fifth semiconductor chip CHP5. As a result, the temperature of the first semiconductor chip CHP1 tends to rise.

[0076] Therefore, for example, the distance L2 between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 may be made longer than the distance L1 between the first semiconductor chip CHP1 and the fifth semiconductor chip CHP5. In this case, the thermal influence from the third semiconductor chip CHP3 can be reduced, thereby mitigating the temperature rise of the first semiconductor chip CHP1. Consequently, the reliability of the semiconductor device 100B can be improved.

[0077] <<Manufacturing method for semiconductor device in an embodiment>> Next, we will describe the method for manufacturing a semiconductor device in its embodiment.

[0078] First, as shown in Figure 7, a lead frame LF having a chip mounting section DP1, a chip mounting section DP2, and a conductor pattern section CP is prepared. Then, a conductive adhesive 10, such as solder or silver paste, is applied to a part of the chip mounting section DP1 and a part of the chip mounting section DP2. In addition, a first semiconductor chip CHP1 including a power transistor and a temperature sensing diode, and a second semiconductor chip CHP2, a third semiconductor chip CHP3, and a fourth semiconductor chip CHP4, which include a power transistor but do not include a temperature sensing diode, are prepared. That is, a chipset consisting of the first semiconductor chip CHP1, the second semiconductor chip CHP2, the third semiconductor chip CHP3, and the fourth semiconductor chip CHP4 is prepared.

[0079] Next, as shown in Figure 8, the first semiconductor chip CHP1 and the third semiconductor chip CHP3 are mounted on the chip mounting section DP1 via conductive adhesive 10 using a die bonding apparatus, and the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4 are mounted on the chip mounting section DP2 via conductive adhesive 10.

[0080] Subsequently, as shown in Figure 9, conductive adhesive 20 is applied to a portion of the chip mounting area DP1, a portion of the conductor pattern area CP, the first semiconductor chip CHP1, the second semiconductor chip CHP2, the third semiconductor chip CHP3, and the fourth semiconductor chip CHP4.

[0081] Next, as shown in Figure 10, multiple clips are mounted. Specifically, the second semiconductor chip CHP2 is connected to the first part P1 of the chip mounting section DP1 with clip CLP1, and the fourth semiconductor chip CHP4 is connected to the second part P2 of the chip mounting section DP1 with clip CLP2. Furthermore, the first semiconductor chip CHP1 is connected to the third part P3 of the conductor pattern section CP with clip CLP3, and the third semiconductor chip CHP3 is connected to the fourth part P4 of the conductor pattern section CP with clip CLP4.

[0082] Then, as shown in Figure 11, the first semiconductor chip CHP1 and the lead LD are connected with bonding wire W using a wire bonding apparatus, and the third semiconductor chip CHP3 and the lead LD are connected with bonding wire W. Similarly, the second semiconductor chip CHP2 and the lead LD are connected with bonding wire W, and the fourth semiconductor chip CHP4 and the lead LD are connected with bonding wire W.

[0083] Subsequently, as shown in Figure 12, the sealant MR is formed by resin encapsulation (molding). Next, deburring is performed, and a plating layer is formed on the outer lead portion of the lead LD exposed from the sealant MR as needed. Then, after forming marks on the surface of the sealant MR, the sealant MR is separated from the frame of the lead frame LF by cutting the lead LD at a predetermined position outside the sealant MR. Finally, the outer lead portion of the lead LD protruding from the sealant MR is bent.

[0084] As described above, a semiconductor device in its embodied form can be manufactured.

[0085] <Necessity of feature ingenuity> The semiconductor device manufacturing method described above uses semiconductor chips that include a power transistor and a temperature sensing diode (hereinafter sometimes referred to as an embedded chip) and semiconductor chips that include a power transistor but do not include a temperature sensing diode (sometimes referred to as a non-embedded chip). These embedded and non-embedded chips are provided, for example, from a device manufacturer to an assembly manufacturer as a chipset, and the assembly manufacturer uses the provided chipset to manufacture semiconductor devices. In this case, the chipset includes embedded and non-embedded chips, but if the embedded and non-embedded chips cannot be distinguished by appearance, it is not possible to manufacture a normal semiconductor device. Therefore, in order to realize the basic concept, it is necessary to make it possible to distinguish between embedded and non-embedded chips by appearance. In other words, there is a need for a method to distinguish between embedded and non-embedded chips by appearance.

[0086] The following explains these design features.

[0087] <<Technologies for distinguishing them by appearance>> Figure 13(a) shows the planar layout of the first semiconductor chip CHP1, which is an embedded chip, and Figure 13(b) shows the planar layout of the second semiconductor chip CHP2 (third semiconductor chip CHP3, fourth semiconductor chip CHP4), which are non-embedded chips.

[0088] In Figure 13(a), the first semiconductor chip CHP1 has multiple pads exposed from the polyimide resin film PI. Specifically, the surface of the first semiconductor chip CHP1 is provided with a source pad SP, a Kelvin pad KLP, a gate pad GP, an anode pad AP, and a cathode pad KP, all of which are exposed from the polyimide resin film PI.

[0089] On the other hand, in Figure 13(b), the second semiconductor chip CHP2 has a plurality of pads exposed from the polyimide resin film PI and a plurality of pads covered by the polyimide resin film PI. Specifically, the surface of the second semiconductor chip CHP2 is provided with a source pad SP, a Kelvin pad KLP, and a gate pad GP so as to be exposed from the polyimide resin film PI, while the surface of the second semiconductor chip CHP2 is provided with an anode pad AP and a cathode pad KP so as to be covered by the polyimide resin film PI.

[0090] Thus, in the first semiconductor chip CHP1, which is an embedded chip, the anode pad AP and cathode pad KP are exposed from the polyimide resin film PI. In contrast, in the second semiconductor chip CHP2, which is a non-embedded chip, the anode pad AP and cathode pad KP are covered with the polyimide resin film PI. In this respect, the first semiconductor chip CHP1 and the second semiconductor chip CHP2 have differences in appearance, and thus they can be distinguished from each other by appearance. In other words, in a chipset having embedded and non-embedded chips, embedded and non-embedded chips can be identified by the presence or absence of exposure of the anode pad AP and cathode pad KP. As a result, depending on the embodiment, assembly manufacturers that provide chipsets can suppress misidentification of embedded and non-embedded chips.

[0091] As mentioned above, the built-in first semiconductor chip CHP1 includes a temperature sensing diode and therefore uses an anode pad AP and a cathode pad KP. For this reason, in the first semiconductor chip CHP1, the anode pad AP and cathode pad KP are exposed from the polyimide resin film PI.

[0092] In contrast, the second semiconductor chip CHP2, which is a non-integrated chip, does not include a temperature sensing diode, and therefore does not use an anode pad AP or cathode pad KP. For this reason, in the second semiconductor chip CHP2, the anode pad AP and cathode pad KP are covered with a polyimide resin film PI.

[0093] In the first place, since the second semiconductor chip CHP2 is a non-internal chip, it could be argued that there is no need to form the anode pad AP and cathode pad KP, as they are not used. However, for the reasons shown below, the second semiconductor chip CHP2, which is a non-internal chip without a temperature sensing diode, still includes the unnecessary anode pad AP and cathode pad KP.

[0094] In other words, if an anode pad AP and cathode pad KP are not provided in a non-embedded chip, the device structure of the non-embedded chip will differ from that of an embedded chip that has an anode pad AP and cathode pad KP. For example, in this case, the presence or absence of the anode pad AP and cathode pad KP will result in differences in electric field distribution and parasitic capacitance between the embedded and non-embedded chips, resulting in differences in device characteristics between the embedded and non-embedded chips. That is, since it is desirable for the device characteristics of embedded and non-embedded chips to be equivalent, it is desirable to avoid as much as possible the differences in device characteristics caused by the presence or absence of anode pad AP and cathode pad KP.

[0095] Therefore, in the implemented embodiment, even though anode pads AP and cathode pads KP are unnecessary in non-embedded chips, they are provided in non-embedded chips as well, from the viewpoint of suppressing deviations in device characteristics. In other words, the technical significance of providing unnecessary anode pads AP and cathode pads KP in non-embedded chips is to suppress deviations in device characteristics between embedded chips and non-embedded chips caused by the presence or absence of anode pads AP and cathode pads KP.

[0096] Therefore, in the implemented embodiment, anode pads AP and cathode pads KP are provided not only in the embedded chip but also in the non-embedded chip, while in the non-embedded chip, the anode pads AP and cathode pads KP are covered with a polyimide resin film PI so that they can be visually distinguished from the embedded chip. As a result, according to the implemented embodiment, it is possible to visually distinguish between the embedded chip and the non-embedded chip while suppressing differences in device characteristics between them. For this reason, according to the implemented embodiment, it is possible to provide a chipset including embedded chips and non-embedded chips that are visually distinguishable from each other. In other words, according to the implemented embodiment, it is possible to provide a chipset that can suppress misrecognition of embedded chips and non-embedded chips.

[0097] <<Device Structure>> First, we will explain the device structure of the built-in chip, referring to the diagram.

[0098] Figure 14(a) is a cross-sectional view taken along line AA in Figure 13(a).

[0099] In Figure 14(a), the built-in chip, the first semiconductor chip CHP1, includes, for example, a semiconductor substrate SUB made of a silicon substrate, an insulating film IF1 formed on the semiconductor substrate SUB, and an insulating film IF2 formed on the insulating film IF1. The first semiconductor chip CHP1 also includes an anode pad AP formed on the insulating film IF2, a cathode pad KP formed on the insulating film IF2, and a polyimide resin film PI, which is a protective film formed on the insulating film IF2. The first semiconductor chip CHP1 further includes the following components: the first semiconductor chip CHP1 has a p-type impurity region and an n-type impurity region, is formed on the insulating film IF1 and is a semiconductor layer which is a component of a temperature sensing diode, has a polysilicon film PF which is a semiconductor layer which is a component of a temperature sensing diode, has a p-type impurity region and an n-type impurity region, has a via VA1 which is formed on the insulating film IF2 and electrically connects the anode pad AP and the polysilicon film PF to each other, and has a via VA2 which is formed on the insulating film IF2 and electrically connects the cathode pad KP and the polysilicon film PF to each other.

[0100] In this case, via VA1 is connected to the polysilicon film PF in the p-type impurity region, while via VA2 is connected to the polysilicon film PF in the n-type impurity region. In other words, the polysilicon film PF has a p-type polysilicon film PPF corresponding to the p-type impurity region and an n-type polysilicon film NPF corresponding to the n-type impurity region, with via VA1 being connected to the p-type polysilicon film PPF and via VA2 being connected to the n-type polysilicon film NPF.

[0101] As shown in Figure 14(a), in the first semiconductor chip CHP1, the anode pad AP is exposed within the opening OP1 of the polyimide resin film PI, and the cathode pad KP is exposed within the opening OP2 of the polyimide resin film PI.

[0102] As described above, the device structure of the first semiconductor chip CHP1 is realized.

[0103] Next, we will explain the device structure of the non-internal chip with reference to the diagrams.

[0104] Figure 14(b) is a cross-sectional view taken along line BB in Figure 13(b).

[0105] In Figure 14(b), the second semiconductor chip CHP2, which is a non-integrated chip, includes, for example, a semiconductor substrate SUB made of a silicon substrate, an insulating film IF1 formed on the semiconductor substrate SUB, and an insulating film IF2 formed on the insulating film IF1. The second semiconductor chip CHP2 also includes an anode pad AP formed on the insulating film IF2, a cathode pad KP formed on the insulating film IF2, and a protective polyimide resin film PI formed on the insulating film IF2.

[0106] In this case, as shown in Figure 14(b), in the second semiconductor chip CHP2, the anode pad AP and cathode pad KP are each covered with a polyimide resin film PI so as not to be exposed from the polyimide resin film PI.

[0107] As described above, the device structure of the second semiconductor chip CHP2 is realized.

[0108] In Figure 14(a), the first semiconductor chip CHP1 includes a temperature sensing diode. Therefore, the first semiconductor chip CHP1 has a polysilicon film PF corresponding to the temperature sensing diode, and this polysilicon film PF is composed of a p-type polysilicon film PPF and an n-type polysilicon film NPF. In the first semiconductor chip CHP1, the anode pad AP is connected to the p-type polysilicon film PPF via via VA1, while the cathode pad KP is connected to the n-type polysilicon film NPF via via VA2.

[0109] In contrast, as shown in Figure 14(b), the second semiconductor chip CHP2 does not include a temperature sensing diode. Therefore, the second semiconductor chip CHP2 does not have a polysilicon film PF corresponding to the temperature sensing diode, via VA1 connected to the anode pad AP, and via VA2 connected to the cathode pad KP. In other words, in the second semiconductor chip CHP2, the anode pad AP and cathode pad KP each function as "dummy pads".

[0110] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0111] In the above embodiment, a power MOSFET was used as an example of a power transistor, but the technical concept in the above embodiment is not limited to this and can be broadly applied when using IGBTs. In this case, the following terms will be reinterpreted.

[0112] "Source" → "Emitter" "Source pad" → "Emitter pad" "Drain" → "Collector" [Explanation of Symbols]

[0113] 10 Conductive adhesive 20 Conductive adhesive 100 Semiconductor Equipment 100A Semiconductor Equipment 100B Semiconductor Equipment AP Anode Pad CHP1 First Semiconductor Chip CHP2 Second Semiconductor Chip CHP3 Third Semiconductor Chip CHP4 4th Semiconductor Chip CHP5 Fifth Semiconductor Chip CHP6 6th Semiconductor Chip CLP1 Clip CLP2 Clip CLP3 Clip CLP4 Clip CLP5 Clip CLP6 Clip CP conductor pattern section DP1 chip mounting section DP2 chip mounting section GP Gate Pad IF1 Insulated Film IF2 insulating film KLP Kelvin Pad KP Kelvin Pad LD Lead LF Lead Frame MR sealed body NPF n-type polysilicon film OP1 opening OP2 opening PF polysilicon film PI polyimide resin film PPF p-type polysilicon membrane P1 Part 1 P2 2nd part P3 3rd part P4 Part 4 P5 Part 5 P6 Part 6 Q1 First power transistor Q2 Second power transistor Q3 Third power transistor Q4 4th power transistor SP Source Pad SUB Semiconductor Substrate VA1 Via VA2 Via W bonding wire WLD1 Wide Lead WLD2 Wide Lead WLD3 Wide Lead WLD4 Wide Lead WLD5 Wide Lead WLD6 Wide Lead

Claims

1. A first chip mounting section, In a plan view, a second chip mounting section is located adjacent to the first chip mounting section, separated from the first chip mounting section, A first semiconductor chip mounted on the first chip mounting section, and including a first power transistor and a temperature sensing diode, A second semiconductor chip mounted on the second chip mounting section, which includes a second power transistor but does not include a temperature sensing diode, A third semiconductor chip mounted on the first chip mounting section, which includes a third power transistor but does not include a temperature sensing diode, A fourth semiconductor chip mounted on the second chip mounting section, which includes a fourth power transistor but does not include a temperature sensing diode, A conductor pattern portion is disposed between the first chip mounting portion and the second chip mounting portion, Equipped with, The second semiconductor chip is electrically connected to the first chip mounting portion via the first plate-shaped member. The fourth semiconductor chip is electrically connected to the first chip mounting section via the second plate-shaped member. The first semiconductor chip is electrically connected to the conductor pattern portion via the third plate-shaped member. A semiconductor device in which, in a plan view, the longitudinal axes of the first plate-shaped member, the second plate-shaped member, and the third plate-shaped member are parallel to each other, and the longitudinal axis of the third plate-shaped member is positioned between the longitudinal axis of the first plate-shaped member and the longitudinal axis of the second plate-shaped member.

2. In the semiconductor device described in claim 1, The semiconductor device is a component of a half-bridge circuit, The first power transistor is one of the high-side transistor and the low-side transistor that constitute the half-bridge circuit. The second power transistor is a semiconductor device which is the other of the high-side transistor and the low-side transistor that constitute the half-bridge circuit.

3. In the semiconductor device described in claim 2, Each of the first power transistor and the third power transistor constitutes the low-side transistor of the half-bridge circuit. Each of the second power transistor and the fourth power transistor constitutes the high-side transistor of the half-bridge circuit. The first power transistor is connected in series with the second power transistor, The third power transistor is connected in series with the fourth power transistor. The first power transistor is connected in parallel with the third power transistor, The second power transistor is connected in parallel with the fourth power transistor in a semiconductor device.

4. In the semiconductor device described in claim 3, The first semiconductor chip is a semiconductor device in which, in a plan view, the first semiconductor chip is positioned between a first portion of the first chip mounting area to which the first plate-shaped member is connected and a second portion of the first chip mounting area to which the second plate-shaped member is connected.

5. In the semiconductor device according to claim 4, The third semiconductor chip is electrically connected to the conductor pattern portion via the fourth plate-shaped member. The first plate-shaped member spans the second semiconductor chip and the first chip mounting portion so as not to come into physical contact with the conductor pattern portion. The second plate-shaped member spans the fourth semiconductor chip and the first chip mounting portion so as not to physically contact the conductor pattern portion. The second plate-shaped member is a semiconductor device that, in a plan view, is positioned between the third plate-shaped member and the fourth plate-shaped member.

6. In the semiconductor device described in claim 5, The aforementioned semiconductor device further, A first wide lead is formed integrally with the first chip mounting portion, A second wide lead is formed integrally with the first chip mounting portion, A third wide lead is formed integrally with the second chip mounting portion, A fourth wide lead, integrally formed with the second chip mounting portion, Multiple leads are arranged so as to be spaced apart from the first chip mounting section and the second chip mounting section, It has, Each of the first chip mounting portion and the second chip mounting portion extends in a first direction in a plan view, The second chip mounting portion is positioned next to the first chip mounting portion in a second direction intersecting the first direction. The first wide lead is positioned next to the first semiconductor chip in the second direction. The second wide lead is positioned next to the third semiconductor chip in the second direction. The third wide lead is positioned next to the second semiconductor chip in the second direction. The fourth wide lead is positioned next to the fourth semiconductor chip in the second direction. A semiconductor device in which the width of each of the first wide lead, second wide lead, third wide lead, and fourth wide lead is greater than the width of each of the plurality of leads.

7. In the semiconductor device described in claim 1, Each of the first semiconductor chip and the second semiconductor chip is, Semiconductor substrate and The first insulating film formed on the semiconductor substrate, A second insulating film formed on the first insulating film, A first pad formed on the second insulating film, A second pad formed on the second insulating film, A protective film formed on the second insulating film, It has, The first semiconductor chip further, A semiconductor layer having a first impurity region of a first conductivity type and a second impurity region of a second conductivity type, formed on the first insulating film, and being a component of the temperature sensing diode, A first via is formed in the second insulating film and electrically connects the first pad and the semiconductor layer to each other, A second via is formed in the second insulating film and electrically connects the second pad and the semiconductor layer to each other, It has, The first via is connected to the semiconductor layer in the first impurity region. The second via is connected to the semiconductor layer in the second impurity region. In the first semiconductor chip, the first pad is exposed within the first opening of the protective film, and the second pad is exposed within the second opening of the protective film. A semiconductor device in which, in the second semiconductor chip, each of the first pad and the second pad is covered with the protective film so as not to be exposed from the protective film.

8. In the semiconductor device according to claim 7, The semiconductor layer is a polysilicon film. The first conductivity type is p-type, The semiconductor device wherein the second conductivity type is n-type.

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