How to operate a semiconductor device

Abstract

Provided is a method for operating a semiconductor device that performs data writing and correction processing. The present invention is a method for operating a semiconductor device that includes a control circuit, a first circuit, a second circuit, a wiring, a cell, and a conversion circuit. In this operation method, first, the control circuit transmits, to the first circuit, a first signal corresponding to a value of first data. Next, the first circuit outputs, to the wiring, a first current of a quantity corresponding to the first signal. Also, the cell retains a first potential corresponding to the quantity of the first current. Next, the cell circulates a second current of a quantity corresponding to the first potential from the wiring, and the conversion circuit outputs a second signal corresponding to the quantity of the second current. Next, the second circuit acquires the difference value between the value corresponding to the second signal and the value of the first data. The operation is terminated if the difference value is 0. If the difference value is not 0, then the control circuit generates an update value obtained by adding the difference value to the value corresponding to the first signal that was transmitted the previous time. The first circuit acquires a first signal corresponding to the update value, and outputs the updated first current to the cell.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a method for operating a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, driving methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them. [Background technology]

[0003] Currently, there is a great deal of activity in developing integrated circuits that mimic the structure of the human brain. These integrated circuits incorporate the brain's structure as electronic circuits, possessing circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called, for example, "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, where power consumption increases with increasing processing speed.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that constructs an artificial neural network using SRAM (Static Random Access Memory).

[0005] Furthermore, attempts are being made to use computing devices that constitute artificial neural networks for purposes such as correcting images displayed on display devices. For example, Patent Document 1 discloses a display device that uses a computing circuit that constitutes an artificial neural network to adjust the brightness, color tone, and other properties of a displayed image to suit the viewer's preferences. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-36639 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924. [Overview of the project] [Problems that the invention aims to solve]

[0008] An example of a computational circuit that constitutes an artificial neural network is a circuit that performs a sum-of-products operation by adding up analog currents corresponding to the product of weight coefficients and input data. Because this computational circuit performs calculations using analog currents, its circuit size can be reduced compared to a computational circuit composed of digital circuits, thus reducing the circuit area. Furthermore, by designing this computational circuit to handle small analog currents in its calculations, the power consumption of the computational circuit can be reduced.

[0009] One possible configuration of the calculation circuit is one in which, while holding a potential corresponding to a weight coefficient, a potential corresponding to the input data is input to the calculation circuit, and an analog current corresponding to the product of the weight coefficient and the input data is output. In this case, it is preferable that the potential corresponding to the weight coefficient held by the calculation circuit is correctly written. However, depending on conditions such as the operating environment of the calculation circuit, the potential written to the calculation circuit may deviate from the target potential. In other words, the weight coefficient held by the calculation circuit may deviate from the target weight coefficient that was actually written, so the calculation result in the calculation circuit may deviate from the expected result.

[0010] One aspect of the present invention aims to provide a method for operating a semiconductor device that correctly writes a multiplicand or a multiplier (in this specification, one of the multiplicand and the multiplier may be referred to as the first data and the other as the second data). Alternatively, one aspect of the present invention aims to provide a method for operating a semiconductor device with high calculation accuracy. Alternatively, one aspect of the present invention aims to provide a method for operating a semiconductor device that performs multiplication of a multi-value multiplicand and a multi-value multiplier. Alternatively, one aspect of the present invention aims to provide a novel method for operating a semiconductor device.

[0011] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0012] (1) One aspect of the present invention is a method for operating a semiconductor device, comprising a control circuit, a first circuit, a second circuit, a first wiring, a first cell, and a conversion circuit. The control circuit is electrically connected to the first circuit and the second circuit. The first circuit is electrically connected to the first wiring. The input terminal of the conversion circuit is electrically connected to the first wiring, and the output terminal of the conversion circuit is electrically connected to the second circuit. The first cell is electrically connected to the first wiring and has the function of holding a potential corresponding to the amount of current flowing in from the first wiring, and the function of flowing a current from the first wiring in an amount corresponding to the held potential. The method for operating the semiconductor device also comprises steps 1 to 6. Step 1 involves the control circuit transmitting a first signal corresponding to the value of first data to the first circuit. The second step includes the operation of the first circuit to acquire a first signal, generate a first current in an amount corresponding to the first signal, and output the first current to the first wiring, and the operation of the first cell to maintain a first potential corresponding to the amount of the first current as the first current flows from the first wiring to the first cell. The third step includes the operation of the first cell to flow a second current in an amount corresponding to the first potential from the first wiring, and the operation of the conversion circuit to refer to the second current flowing through the first wiring, which is electrically connected to the input terminal of the conversion circuit, and output a second signal corresponding to the amount of the second current from the output terminal of the conversion circuit. The fourth step includes the operation of the control circuit to transmit a signal corresponding to the value of the first data to the second circuit, the operation of the second circuit to calculate the difference between the value corresponding to the second signal acquired from the conversion circuit and the value of the first data acquired from the control circuit, and transmit the difference value to the control circuit, and the operation of the control path to acquire the difference value, to terminate the operation if the difference value is 0, and to proceed to the fifth step if the difference value is not 0. Step 5 involves the control circuit generating an updated value by adding a difference value to the value of the previously transmitted first signal. Step 6 involves the control circuit transmitting a first signal to the first circuit, which has been changed from the value of the first data to the updated value, and then proceeding to step 2.

[0013] (2) Alternatively, in one aspect of the present invention, the second circuit may be configured to include a subtractor in (1) above.

[0014] (3) Alternatively, one aspect of the present invention is a method of operating a semiconductor device different from (1) above, comprising a control circuit, a first circuit, a second circuit, a first wiring, a first cell, and a conversion circuit. The control circuit is electrically connected to the first circuit and the second circuit. The first circuit is electrically connected to the first wiring. The input terminal of the conversion circuit is electrically connected to the first wiring, and the output terminal of the conversion circuit is electrically connected to the second circuit. The first cell is electrically connected to the first wiring, and the first cell has the function of holding a potential corresponding to the amount of current flowing in from the first wiring, and the function of flowing a current from the first wiring in an amount corresponding to the held potential. The method of operating the semiconductor device comprises a first to third step and a fifth to eighth step. The first step comprises the operation in which the control circuit transmits a first signal corresponding to the value of first data to the first circuit. The second step includes the operation of the first circuit to acquire a first signal, generate a first current in an amount corresponding to the first signal, and output the first current to the first wiring, and the operation of the first cell to maintain a first potential corresponding to the amount of the first current as the first current flows from the first wiring to the first cell. The third step includes the operation of the first cell to flow a second current in an amount corresponding to the first potential from the first wiring, and the operation of the conversion circuit to refer to the second current flowing through the first wiring, which is electrically connected to the input terminal of the conversion circuit, and output a second signal corresponding to the amount of the second current from the output terminal of the conversion circuit. The seventh step includes the operation of the control circuit to transmit a signal corresponding to the value of the first data to the second circuit, and the operation of the second circuit to calculate the difference between the value corresponding to the second signal acquired from the conversion circuit and the value of the first data acquired from the control circuit, and transmit the difference value to the control circuit. Step 8 includes the operation of the second circuit to obtain a reference value from the control circuit, terminate operation if the difference value is smaller than the reference value, and proceed to step 5 if the difference value is larger than the reference value. Step 5 includes the operation of the control circuit to generate an updated value by adding the difference value to the value of the first signal that was transmitted last time. Step 6 includes the operation of the control circuit to transmit a first signal to the first circuit that has been changed from the value of the first data to the updated value, and proceed to step 2.

[0015] (4) Alternatively, in one aspect of the present invention, the second circuit in (3) above may be configured to include a subtractor and a comparator.

[0016] (5) Alternatively, in one aspect of the present invention, in any one of (1) to (4) above, the first cell may have a configuration comprising a first transistor, a second transistor, a third transistor, and a capacitor. Specifically, it is preferable that one of the sources or drains of the first transistor is electrically connected to the gate of the second transistor, one of the sources or drains of the second transistor is electrically connected to one of the sources or drains of the third transistor, and the other of the sources or drains of the first transistor is electrically connected to the other of the sources or drains of the third transistor. Furthermore, it is preferable that the first terminal of the capacitor is electrically connected to one of the sources or drains of the first transistor, and the first wiring is electrically connected to the other of the sources or drains of the first transistor. [Effects of the Invention]

[0017] According to one aspect of the present invention, a method for operating a semiconductor device that correctly writes a multiplicand or multiplier can be provided. Alternatively, according to one aspect of the present invention, a method for operating a semiconductor device with high calculation accuracy can be provided. Alternatively, according to one aspect of the present invention, a method for operating a semiconductor device that performs multiplication of a multi-value multiplicand and a multi-value multiplier can be provided. Alternatively, according to one aspect of the present invention, a novel method for operating a semiconductor device can be provided.

[0018] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0019] Figure 1 is a block diagram showing an example of the configuration of an arithmetic circuit. Figure 2 is a circuit diagram showing an example of the configuration of an arithmetic circuit. Figures 3A to 3C are circuit diagrams showing example configurations of circuits included in the arithmetic circuit. Figures 4A to 4D are circuit diagrams showing example configurations of circuits included in the arithmetic circuit. Figures 5A and 5B are circuit diagrams showing example configurations of circuits included in the arithmetic circuit. Figures 6A to 6C are circuit diagrams showing example configurations of circuits included in the arithmetic circuit. Figure 7 is a flowchart showing an example of the operation of the arithmetic circuit. Figure 8 is a flowchart showing an example of the operation of the arithmetic circuit. Figure 9 is a timing chart showing an example of the operation of the arithmetic circuit. Figure 10 is a circuit diagram showing an example of the configuration of an arithmetic circuit. Figure 11 is a flowchart showing an example of the operation of the arithmetic circuit. Figure 12 is a block diagram showing an example of the configuration of an arithmetic circuit. Figure 13 is a circuit diagram showing an example of the configuration of an arithmetic circuit. Figure 14 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic circuit. Figure 15 is a flowchart showing an example of the operation of the arithmetic circuit. Figure 16 is a timing chart showing an example of the operation of a circuit included in a semiconductor device. Figure 17 is a flowchart showing an example of the operation of the arithmetic circuit. Figure 18A is a perspective view illustrating an example of a semiconductor device configuration. Figure 18B is a block diagram illustrating an example of a semiconductor device configuration. Figure 19A is an enlarged perspective block diagram of a portion of the memory layer. Figure 19B is a plan view of a portion of the memory layer as seen from the Z direction. Figure 20A is a schematic cross-sectional view of a memory cell. Figure 20B is an example of a memory cell circuit configuration. Figure 21 shows an example of a cross-sectional configuration of a memory layer. Figure 22 shows an example of a memory layer circuit configuration. Figures 23A to 23D illustrate examples of semiconductor device configurations. Figure 24 illustrates an example of a semiconductor device configuration. Figures 25A to 25C illustrate an example of the configuration of a semiconductor device. Figures 26A and 26B illustrate an example of the configuration of a semiconductor device. Figures 27A and 27B illustrate an example of the configuration of a semiconductor device. Figures 28A to 28D illustrate examples of semiconductor device configurations. Figure 29 is a diagram illustrating an example of a semiconductor device configuration. Figure 30A is a perspective view showing an example of a semiconductor wafer, Figure 30B is a perspective view showing an example of a chip, and Figures 30C and 30D are perspective views showing examples of electronic components. Figure 31 is a block diagram illustrating the CPU. Figures 32A to 32J are perspective views or schematic diagrams illustrating an example of electronic equipment. Figures 33A to 33D show examples of electronic device configurations. Figures 34A to 34E are perspective views or schematic diagrams illustrating an example of electronic equipment. Figure 35 is a block diagram showing the configuration of the semiconductor device used in the example. Figures 36A and 36B are graphs showing the distribution of current output from the semiconductor device used in the example. Figure 37 is a graph showing the distribution of the current output from the semiconductor device used in the example. Figure 38 is a schematic diagram showing an example of the configuration of the semiconductor device used in the embodiment. Figure 39 is a photograph of the semiconductor device used in the example. Figure 40 is a schematic cross-sectional view of the semiconductor device used in the example. Figure 41 is a cross-sectional STEM image of the semiconductor device used in the example. Figure 42 is a graph showing the relationship between the contact pitch and the number of contacts of the semiconductor device used in the example. Figure 43 is a graph showing the threshold voltage distribution of multiple Si transistors used in the example. Figure 44 is a graph showing the power consumption of the semiconductor device used in the example. Figure 45 is a graph showing the relationship between the number of write cycles and the output current of the semiconductor device used in the example. Figure 46 is a graph showing the data retention time and inference accuracy of the semiconductor device used in the example. Figure 47 is a graph showing the temperature dependence of the off-current of the Si transistor and OS transistor used in the example. Figure 48 is a graph showing the temperature dependence of inference accuracy in the semiconductor device used in the example. Figure 49 is a graph showing the temperature dependence of the output current from the arithmetic cell in the semiconductor device described in the example. Figure 50 is a graph showing the temperature dependence of the conductance of the Si transistor and OS transistor used in the example, as well as the PCM. Figure 51 is a graph showing the benchmarks of the semiconductor device, ASIC, FPGA, and GPU used in the example. [Modes for carrying out the invention]

[0020] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (e.g., transistors, diodes, and photodiodes), and devices having such circuits. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are all examples of semiconductor devices. Additionally, for example, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices or may contain semiconductor devices.

[0021] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).

[0022] One example of a case where X and Y are electrically connected is that one or more elements that enable the electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, and loads) can be connected between X and Y. Note that a switch has the function of being controlled to be on or off. In other words, a switch has the function of being in a conductive state (on state) or a non-conductive state (off state), and controlling whether or not current flows.

[0023] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (e.g., inverters, NAND gates, and NOR gates), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost or buck converters, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplification circuits (e.g., circuits that can increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. Note that, as an example, even if another circuit is placed between X and Y, if a signal output from X is transmitted to Y, X and Y are considered functionally connected.

[0024] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0025] Furthermore, this specification deals with circuit configurations in which multiple elements are electrically connected to wiring (wiring that supplies a constant potential or wiring that transmits a signal). For example, if X and wiring are directly connected, and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0026] Furthermore, for example, it can be expressed as, "X, Y, the source (which may be rephrased as either the first or second terminal) and the drain (which may be rephrased as the other of the first or second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, transistor source, transistor drain, and Y." Or, "The source of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to Y, and X, transistor source, transistor drain, and Y are electrically connected in this order." Or, "X is electrically connected to Y via the source and drain of the transistor, and X, transistor source, transistor drain, and Y are provided in this connection order." By specifying the order of connections in the circuit configuration using similar methods of expression as these examples, the source and drain of the transistor can be distinguished and the technical scope can be determined. Note that these methods of expression are examples and are not limited to these methods of expression. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0027] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0028] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element having a resistance value higher than 0Ω, or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, a transistor, diode, or coil through which current flows between the source and drain. Therefore, the term "resistive element" may be replaced with the terms "resistor," "load," or "region having a resistance value." Conversely, the terms "resistor," "load," or "region having a resistance value" may be replaced with the term "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0029] Furthermore, in this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Also, the terms "capacitive element," "parasitic capacitance," or "gate capacitance" may be replaced with the term "capacitance." Conversely, the term "capacitance" may be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." In addition, "capacitance" (including "capacitance" with three or more terminals) has a configuration that includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" may be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Also, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as the first terminal and the second terminal, respectively. The capacitance value may be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0030] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or sometimes referred to as the first electrode, first terminal, etc.) and "the other of the source or drain" (or sometimes referred to as the second electrode, second terminal, etc.) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as the first gate, and the other of the gate or back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" can sometimes be interchanged. Also, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0031] For example, in this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes during operation in the saturation region. By utilizing this flat voltage-current characteristic, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0032] Furthermore, in this specification, circuit elements such as "light-emitting devices" and "light-receiving devices" may have polarities called "anode" and "cathode." In the case of a "light-emitting device," it may be possible to make the "light-emitting device" emit light by applying a forward bias (applying a positive potential relative to the "cathode" to the "anode"). In the case of a "light-receiving device," it may be possible to generate a current between the "anode" and "cathode" by applying a zero bias or a reverse bias (applying a negative potential relative to the "cathode" to the "anode") and irradiating the "light-receiving device" with light. As described above, the "anode" and "cathode" may be treated as input / output terminals in circuit elements such as "light-emitting devices" and "light-receiving devices." In this specification, the "anode" and "cathode" in circuit elements such as "light-emitting devices" and "light-receiving devices" may be referred to as terminals (first terminal, second terminal, etc.). For example, one of the "anode" or "cathode" may be referred to as the first terminal, and the other as the second terminal.

[0033] Furthermore, even if a single circuit element is depicted in a circuit diagram, that element may actually comprise multiple circuit elements. For example, if one resistor is shown in a circuit diagram, it includes cases where two or more resistors are electrically connected in series. Similarly, if one capacitor is shown in a circuit diagram, it includes cases where two or more capacitors are electrically connected in parallel. Similarly, if one transistor is shown in a circuit diagram, it includes cases where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Likewise, if one switch is shown in a circuit diagram, it includes cases where the switch has two or more transistors, and these two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0034] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration and device structure. Also, terminals, wiring, etc., can be replaced with "node."

[0035] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0036] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0037] Furthermore, "electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Examples of carriers include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, or vacuum). Also, the "direction of current" in wiring, etc., is the direction in which positively charged carriers move and is expressed as a positive current quantity. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, unless otherwise specified regarding the positive or negative (or direction) of the current, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0038] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0039] Furthermore, in this specification, terms indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0040] Furthermore, terms such as "above" or "below" do not limit the positional relationship of the components to being directly above or directly below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, for example, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, for example, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0041] Furthermore, in this specification, terms such as "rows" and "columns" may be used to describe matrix-like arrangements of components and their positional relationships. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terminology used is not limited to that described in the specification and can be appropriately rephrased depending on the situation. For example, the expression "row direction" can sometimes be rephrased as "column direction" by rotating the orientation of the drawing shown by 90 degrees.

[0042] Furthermore, in this specification, the terms "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." Alternatively, depending on the circumstances, the terms "film" and "layer" can be omitted and replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to "insulator."

[0043] Furthermore, in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Also, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected "electrodes," "wiring," and "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, the terms "electrode," "wiring," or "terminal" may be replaced with the term "region" in some cases.

[0044] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to a term such as "power line." The reverse is also true; terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances or situation. Similarly, the term "signal" may be changed to the term "potential."

[0045] Furthermore, this specification may use timing charts to explain the operation of semiconductor devices. The timing charts used in this specification illustrate ideal operating examples, and the periods, magnitudes of signals (e.g., potential or current), and timings shown in the timing charts are not limited unless otherwise specified. Depending on the situation, the magnitudes and timings of the signals (e.g., potential or current) input to each wiring (including nodes) in the timing charts described in this specification may be modified. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may differ. Also, for example, even if one period is shown as longer and the other as shorter, the lengths of the two periods may be equal, or one period may be shorter and the other longer.

[0046] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, if a metal oxide is included in the channel formation region of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute the channel formation region of a transistor having at least one of amplification, rectification, and switching functions, that metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when referring to an OS transistor, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0047] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0048] Furthermore, in this specification, semiconductor impurities refer to elements other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity, or one or both. For example, when the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Also, for example, when the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0049] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) or non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Therefore, a switch may have two or more terminals for conducting current in addition to control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source and drain electrodes. Conversely, the "non-conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] One example of a mechanical switch is a switch that uses MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0052] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less.

[0053] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0054] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0055] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0056] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0057] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0058] Furthermore, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view is, for example, a diagram showing a view of the configuration from a direction perpendicular to the horizontal plane, or a diagram showing a cross-section of the configuration cut horizontally. In addition, hidden lines (e.g., dashed lines) can be included in the plan view to show the positional relationships of multiple elements included in the configuration, or the relationship of overlap between such multiple elements. In this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Also, depending on the situation, a cross-section of the configuration cut in a direction other than the horizontal direction may be referred to as a plan view.

[0059] Furthermore, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a view of a configuration from a direction perpendicular to the horizontal plane, or a view of a configuration cut in a direction perpendicular to the horizontal plane. In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Also, depending on the situation, a cross-sectional view may refer to a view of a configuration cut in a direction other than the vertical direction, rather than a view of a vertical cut.

[0060] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0061] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0062] (Embodiment 1) In this embodiment, an arithmetic circuit, which is a semiconductor device according to one aspect of the present invention, will be described.

[0063] <Example of arithmetic circuit configuration 1> Figure 1 shows an example of a configuration of an arithmetic circuit that performs a sum-of-products operation on a first data point (positive or "0") and a second data point (positive or "0"). The arithmetic circuit MACA0 shown in Figure 1 is a circuit that performs a sum-of-products operation on the first data point corresponding to the potential held in each cell and on multiple input second data points, and then performs a function operation using the result of the sum-of-products operation. This function can be, for example, an activation function when performing calculations in a neural network. The first and second data points can be, for example, analog data (e.g., continuous analog potential) or multi-level data (e.g., discrete analog potential or digital signal). The arithmetic circuit MACA0 also has a function to appropriately correct the potential held in the cells.

[0064] The arithmetic circuit MACA0 includes the control circuit CTR, the circuit WCS, the circuit XCS, the circuit WSD, the circuit ITS, the circuit FB, and the cell array CA.

[0065] The cell array CA has cells IM[1,1] through IM[m,n] (where m is an integer greater than or equal to 1 and n is an integer greater than or equal to 1) and cells IMd[1] through IMd[m]. In Figure 1, cells IM[1,1], IM[m,1], IM[1,n], IM[m,n], IMd[1], and IMd[m] are shown as an excerpt from cells IM[1,1] through IM[m,n] and cells IMd[1] through IMd[m].

[0066] Cells IMd[1] to IMd[m] have the function of supplying potentials to wiring XCL[1] to wiring XCL[m] corresponding to the second data required to perform a sum-of-products operation with the held potential, as an example.

[0067] Note that while the cell array CA in Figure 1 has cells arranged in a matrix of m rows and n+1 columns, any cell array CA can have a configuration in which cells are arranged in a matrix of one or more rows and two or more columns.

[0068] [Example configuration of Cell IM and Cell IMD] Here, we will describe the configuration examples of cells IM[1,1] through IM[m,n] and cells IMd[1] through IMd[m]. The arithmetic circuit MACA1 shown in Figure 2 is an example of the configuration of the arithmetic circuit MACA0 shown in Figure 1, and Figure 2 shows examples of the circuit configurations of cell IM and cell IMd, respectively.

[0069] Note that Figure 2 shows only a selection of cells IM[1,j] (where j is an integer between 1 and n), IM[m,j], IMd[1], and IMd[m] from cells IM[1,1] to IM[m,n] and cells IMd[1] to IMd[m]. Therefore, unless otherwise specified, the examples of the configurations of cells IM[1,1] to IM[m,n] and cells IMd[1] to IMd[m] will be explained by selecting only cells IM[1,j] to IM[m,j] and cells IMd[1] to IMd[m].

[0070] Cells IM[1,j] through IM[m,j] include, for example, transistor F1, transistor F2, transistor F5, and capacitor C5. Similarly, cells IMd[1] through IMd[m] include, for example, transistor F1d, transistor F2d, transistor F5d, and capacitor C5d.

[0071] In particular, it is preferable that the configuration of transistor F1 contained in each of cells IM[1,j] to IM[m,j] (e.g., size such as channel length and channel width) be equal to each other, and that the size of transistor F2 contained in each of cells IM[1,j] to IM[m,j] be equal to each other, and that the size of transistor F5 contained in each of cells IM[1,j] to IM[m,j] be equal to each other. Furthermore, it is preferable that the size of transistor F1d contained in each of cells IMd[1] to IMd[m] be equal to each other, and that the size of transistor F2d contained in each of cells IMd[1] to IMd[m] be equal to each other, and that the size of transistor F5d contained in each of cells IMd[1] to IMd[m] be equal to each other. Furthermore, it is preferable that the sizes of transistor F1 and transistor F1d be equal to each other, and that the sizes of transistor F2 and transistor F2d be equal to each other, and that the sizes of transistor F5 and transistor F5d be equal to each other.

[0072] By making the sizes of transistors equal, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of transistor F1 contained in each of cells IM[1,j] to IM[m,j] equal, the size of transistor F2 contained in each of cells IM[1,j] to IM[m,j] equal, and the size of transistor F5 contained in each of cells IM[1,j] to IM[m,j] equal, each of cells IM[1,j] to IM[m,j] can perform approximately the same operation under identical conditions. Here, identical conditions refer to, for example, the potentials of the source, drain, and gate of transistor F1, the potentials of the source, drain, and gate of transistor F2, the potentials of the source, drain, and gate of transistor F5, and the voltage input to cells IM[1,j] to IM[m,j]. Similarly, by making the size of transistor F1d in each of cells IMd[1] through IMd[m] equal, the size of transistor F2d in each of cells IMd[1] through IMd[m] equal, and the size of transistor F5d in each of cells IMd[1] through IMd[m] equal, each of cells IMd[1] through IMd[m] can perform substantially the same operation under identical conditions. These identical conditions refer, for example, to the potentials of the source, drain, and gate of transistor F1d, the potentials of the source, drain, and gate of transistor F2d, the potentials of the source, drain, and gate of transistor F5d, and the voltages input to cells IMd[1] through IMd[m].

[0073] Unless otherwise specified, transistors F1 and F1d are assumed to operate in the linear region when they are ON. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the range in which they operate in the linear region. However, one aspect of the present invention is not limited thereto. For example, transistors F1 and F1d may operate in the saturation region when they are ON, and they may operate in a mixture of the linear region and the saturation region.

[0074] Furthermore, unless otherwise specified, transistors F2 and F2d include cases where they operate in the subthreshold region (i.e., in transistor F2 or transistor F2d, the gate-source voltage is lower than the threshold voltage, more preferably the drain current increases exponentially with respect to the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above include cases where they are appropriately biased to voltages within the operating range of the subthreshold region. For this reason, transistors F2 and F2d also include cases where they operate such that an off-current flows between the source and drain.

[0075] Furthermore, transistors F5 and F5d function, for example, as clamp transistors (sometimes called clamp FETs). For this reason, it is preferable to apply a constant voltage to the gates of transistors F5 and F5d. Also, as will be described in more detail later, by providing transistor F5 (transistor F5d), drain-induced barrier drop (DIBL) in transistor F2 (transistor F2d) can be prevented.

[0076] On the other hand, if drain-induced barrier drop (DIBL) in transistor F2 (transistor F2d) can be ignored, cell IM (cell IMd) may be configured without transistor F5 (transistor F5d).

[0077] Furthermore, it is preferable that one or both of transistors F1 and F1d are OS transistors, for example. Examples of metal oxides included in the channel formation region of the OS transistor include indium oxide, gallium oxide, and zinc oxide. It is also preferable that the metal oxide contains one or more elements selected from indium, element M, and zinc. Element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, it is preferable that element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0078] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the metal oxide used in the semiconductor layer. Alternatively, it is preferable to use an oxide containing indium, tin, and zinc (also referred to as ITZO®). Alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc. Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO). The OS transistor will be described in detail in Embodiment 4.

[0079] Furthermore, one or both of transistors F1 and F1d can be transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors), other than OS transistors. As silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon can be used.

[0080] By using OS transistors for one or both of transistors F1 and F1d, the leakage current of the selected transistor can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when the selected transistor is in a non-conductive state, the leakage current from the holding node to the write word line can be made very small, thus reducing the refresh operation of the holding node's potential. Furthermore, by reducing the refresh operation, the power consumption of the arithmetic circuit can be reduced. In addition, by making the leakage current from the holding node to the wiring WCL[j] or any of the wirings XCL[1] to XCL[m] described later very small, the cell can hold the potential of the holding node for a long time, thus increasing the calculation accuracy of the arithmetic circuit.

[0081] Furthermore, by using OS transistors for one or both of transistors F2 and F2d, they can be operated within a wide current range in the subthreshold region, thereby reducing current consumption. Also, by using OS transistors for transistors F2 and F2d, they can be fabricated simultaneously with transistors F1 and F1d, which may shorten the fabrication process for the arithmetic circuit. In addition, transistors F2 and F2d can be replaced with Si transistors instead of OS transistors.

[0082] Furthermore, it is even more preferable that transistors F1, F1d, F2, F2d, F5, and F5d have structures such as transistor 300 and transistor 500 as described in Embodiment 4.

[0083] Incidentally, when semiconductor devices are integrated onto a chip with a high degree of integration, heat may be generated on the chip due to the operation of the circuits. This heat can cause the temperature of transistors to rise, which can change the characteristics of those transistors, leading to changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so changes in field-effect mobility due to temperature changes are less likely to occur, and a decrease in operating frequency is also less likely. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, by using OS transistors, calculations and processing can be easily performed even in high-temperature environments. For this reason, when constructing a semiconductor device that is resistant to heat generated by operation, it is preferable to use OS transistors as transistors.

[0084] In cells IM[1,j] through IM[m,j], the first terminal of transistor F1 is electrically connected to the gate of transistor F2. The first terminal of transistor F2 is electrically connected to wiring VE0. The first terminal of capacitor C5 is electrically connected to the gate of transistor F2. The second terminal of transistor F2 is electrically connected to the first terminal of transistor F5. Furthermore, the second terminal of transistor F5 is electrically connected to the second terminal of transistor F1, and the gate of transistor F5 is electrically connected to wiring VE1.

[0085] The second terminal of transistor F2 and the wiring WCL[j] are electrically connected in series via the first and second terminals of transistor F5, thereby preventing the direct application of a high-level potential from the wiring WCL[j] to the second terminal of transistor F2. This prevents a decrease in the drain-induced barrier in transistor F2.

[0086] In the configuration of cells IM[1,j] to IM[m,j], if the second terminal of transistor F2 is directly electrically connected to the wiring WCL[j] (i.e., transistor F5 is not provided), a high-level potential from the wiring WCL[j] is directly applied to the second terminal of transistor F2, which can cause a drain-induced barrier drop in transistor F2. When a drain-induced barrier drop occurs in transistor F2, the threshold voltage of transistor F2 decreases, which can change the voltage range of the subthreshold region of transistor F2. Therefore, when cell IM[1,j] is configured without transistor F5, variations may occur in the current in the subthreshold region flowing through transistor F2.

[0087] In cells IMd[1] through IMd[m], the first terminal of transistor F1d is electrically connected to the gate of transistor F2d. The first terminal of transistor F2d is electrically connected to wiring VE0. The first terminal of capacitor C5d is electrically connected to the gate of transistor F2d. The second terminal of transistor F2d is electrically connected to the first terminal of transistor F5d. Furthermore, the second terminal of transistor F5d is electrically connected to the second terminal of transistor F1d, and the gate of transistor F5d is electrically connected to wiring VE1.

[0088] In cells IMd[1] through IMd[m], transistor F5d, like transistor F5 in cells IM[1,j] through IM[m,j], also plays a role in preventing drain-induced barrier reduction at transistor F2d.

[0089] In Figure 2, back gates are shown for transistors F1, F2, F5, F1d, F2d, and F5d. Although the connection configuration of these back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor with a back gate, the gate and back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and back gate of transistor F1 may be electrically connected, or the gate and back gate of transistor F1d may be electrically connected. Alternatively, for example, in a transistor with a back gate, wiring may be provided to electrically connect the back gate of the transistor to an external circuit, etc., in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, thereby providing a potential to the back gate of the transistor through the external circuit, etc.

[0090] Furthermore, although transistors F1, F2, and F5 shown in Figure 2 have back gates, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, transistors F1, F2, and F5 shown in Figure 2 may be configured without back gates, that is, single-gate transistors. Alternatively, some transistors may have back gates, while others may not.

[0091] Furthermore, although transistors F1, F2, and F5 shown in Figure 2 are n-channel type transistors, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, some or all of transistors F1, F2, and F5 may be replaced with p-channel type transistors.

[0092] Furthermore, the above examples of changes to the structure and polarity of transistors are not limited to transistors F1, F2, and F5. For example, the same applies to transistors F1d, F2d, and F5d, as well as transistors described elsewhere in the specification or illustrated in other drawings.

[0093] Wiring VE0 functions as a wire for conducting current between the first and second terminals of transistor F2 in cells IM[1,j] to IM[m,j]. Wiring VE0 also functions as a wire for conducting current between the first and second terminals of transistor F2d in cells IMd[1] to IMd[m]. As an example, wiring VE0 functions as a wire for supplying a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential.

[0094] Wiring VE1 functions as wiring for applying a potential to the gates of transistors F5 in cells IM[1,j] to IM[m,j] and the gates of transistors F5d in cells IMd[1] to IMd[m]. Preferably, the potential is within the range in which transistors F5 and F5d function as clamp transistors.

[0095] In cell IM[1,j], the second terminals of transistor F1 and transistor F5 are electrically connected to wiring WCL[j], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F5 is electrically connected to wiring WCL[j], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In Figure 2, node N[1,j] is defined as the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,j].

[0096] In cell IM[m,j], the second terminals of transistor F1 and transistor F5 are electrically connected to wiring WCL[j], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F5 is electrically connected to wiring WCL[j], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In Figure 2, node N[m,j] is defined as the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,j].

[0097] In cell IMd[1], the second terminal of transistor F1d and the second terminal of transistor F5d are electrically connected to wiring XCL[1], and the gate of transistor F1d is electrically connected to wiring WSL[1]. The second terminal of transistor F5d is electrically connected to wiring XCL[1], and the second terminal of capacitor C5d is electrically connected to wiring XCL[1]. In Figure 2, node Nd[1] is defined as the connection point between the first terminal of transistor F1d, the gate of transistor F2d, and the first terminal of capacitor C5d in cell IMd[1].

[0098] In cell IMd[m], the second terminal of transistor F1d and the second terminal of transistor F5d are electrically connected to wiring XCL[m], and the gate of transistor F1d is electrically connected to wiring WSL[m]. The second terminal of transistor F5d is electrically connected to wiring XCL[m], and the second terminal of capacitor C5d is electrically connected to wiring XCL[m]. In Figure 2, in cell IMd[m], the connection point between the first terminal of transistor F1d, the gate of transistor F2d, and the first terminal of capacitor C5d is defined as node Nd[m].

[0099] Note that nodes N[1,j], N[m,j], Nd[1], and Nd[m] function as holding nodes for their respective cells.

[0100] In cells IM[1,j] through IM[m,j], for example, when transistors F1 and F5 are ON, transistor F2 is configured to conduct between its gate and second terminal. With the constant voltage supplied by wiring VE0 as the ground potential (GND), when transistor F1 is ON and a current of amount I flows from wiring WCL[j] to the second terminal of transistor F2, the potential of the gate (node ​​N) of transistor F2 is determined according to the current amount I. Since transistor F1 is ON, the potential of the second terminal of transistor F2 is ideally equal to that of the gate (node ​​N) of transistor F2. By turning transistor F1 OFF, the potential of the gate (node ​​N) of transistor F2 is maintained by capacitance C5. As a result, transistor F2 can pass a current of amount I between its source and drain, corresponding to the ground potential of its first terminal and the potential of its gate (node ​​N). In this specification, such operation is referred to as "setting (programming) the amount of current flowing between the source and drain of transistor F2 of cell IM to I."

[0101] Furthermore, in the explanation above, by replacing transistor F1 with transistor F1d, transistor F2 with transistor F2d, and node N with node Nd, the amount of current flowing between the source and drain of transistor F2d can be similarly set in cell IMd[i] (where i is an integer between 1 and m).

[0102] [Circuit WCS] Next, we will describe an example configuration of the WCS circuit, which is equivalent to the peripheral circuitry of the cell array CA.

[0103] Circuit WCS includes, for example, circuit SWS1 and circuit WCSa[j].

[0104] Circuit SWS1 has the function of making the connection between wiring WCL[j] and circuit WCSa[j] conductive or non-conductive.

[0105] Circuit SWS1, for example, includes a switch S3[j].

[0106] Switch S3[j] has as many instances as there are matrix-like columns in which cells IM of the cell array CA are arranged. In other words, in the case of the arithmetic circuit MACA1 shown in Figure 2, the circuit SWS1 has switches S3[1] through S3[n] (a total of n switches).

[0107] The first terminal of switch S3[j] is electrically connected to wiring WCL[j], the second terminal of switch S3[j] is electrically connected to circuit WCSa[j], and the control terminal of switch S3[j] is electrically connected to wiring SWL1.

[0108] An electrical switch, such as an analog switch or a transistor, can be applied to switch S3[j]. In particular, it is preferable that the above-mentioned transistor is used as the electrical switch for switch S3[j], and it is even more preferable that an OS transistor is used. When an electrical switch is used for switch S3[j], a Si transistor, for example, can be used as the electrical switch in addition to an OS transistor. Alternatively, a mechanical switch may be applied to switch S3[j].

[0109] In this specification, the switch S3[j] shown in Figure 2 is assumed to be ON when a high-level potential is applied to the control terminal and OFF when a low-level potential is applied to the control terminal.

[0110] Wiring SWL1 functions, for example, as wiring to switch between the ON and OFF states of switch S3[j]. Therefore, either a high-level potential or a low-level potential is supplied to wiring SWL1.

[0111] As described above, circuit SWS1 functions as a circuit that makes the connection between circuit WCS and wiring WCL[j] either conductive or non-conductive. In other words, circuit SWS1 switches between the conductive and non-conductive states between circuit WCS and wiring WCL[j] using switch S3[j].

[0112] Circuit WCSa[j] has the function of supplying a signal corresponding to the first data to wiring WCL[j]. In other words, when switch S3[j] is ON, circuit WCS supplies the first data to be stored in each cell of cell array CA. In the case of the arithmetic circuit MACA1 in Figure 2, the value of the signal can be expressed as a current.

[0113] For example, circuit WCSa[j] can have the configuration shown in Figure 3A. Figure 3A also shows circuit SWS1, switch S3[j], wiring SWL1, and wiring WCL[j] to illustrate the electrical connections between circuit WCSa and its surrounding circuits.

[0114] Circuit WCSa[j] has as many instances as there are matrix-like columns in which cells IM of cell array CA are arranged. In other words, in the case of the arithmetic circuit MACA1 shown in Figure 2, circuit WCS has circuits WCSa[1] through WCSa[n] (a total of n instances).

[0115] Therefore, the switch S3[j] shown in Figure 3A can be any one of the switches S3[1] to S3[n] included in the arithmetic circuit MACA1 in Figure 2. Similarly, the wiring WCL[j] can be any one of the wiring WCL[1] to WCL[n] included in the arithmetic circuit MACA1 in Figure 2.

[0116] Therefore, circuit WCSa[j] is electrically connected to wiring WCL[j] via switch S3[j].

[0117] The circuit WCSa[j] shown in Figure 3A includes a switch SWW as an example. The first terminal of switch SWW is electrically connected to the second terminal of switch S3[j], and the second terminal of switch SWW is electrically connected to wiring VINIL1. Wiring VINIL1 functions as a wire that provides an initialization potential to wiring WCL, and the initialization potential can be ground potential (GND), low level potential, or high level potential. Note that switch SWW is ON only when providing an initialization potential to wiring WCL, and OFF at all other times.

[0118] The switch SWW can be an electrical switch, such as an analog switch or a transistor. If a transistor is used as the switch SWW, it can be a transistor with the same structure as transistor F1 or transistor F2. In addition to electrical switches, mechanical switches may also be used.

[0119] Furthermore, the circuit WCSa in Figure 3A has multiple current sources CS as an example. Specifically, the circuit WCSa[j] has K bits (2 K It has the function of outputting the first data of value) (K is an integer greater than or equal to 1) as a current quantity, and in this case, the circuit WCSa[j] is 2 K -It has one current source CS. Note that the circuit WCSa[j] has, for example, one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Kth bit as current. K-1 They possess it individually.

[0120] In Figure 3A, each current source CS has terminal T1 and terminal T2. Terminal T1 of each current source CS is electrically connected to the second terminal of switch S3 of circuit SWS1. Also, terminal T2 of one current source CS is electrically connected to wiring DW[1], and each of the terminals T2 of two current sources CS is electrically connected to wiring DW[2], and 2 K-1Each of the terminals T2 of the current sources CS is electrically connected to the wiring DW[K].

[0121] The plurality of current sources CS included in the circuit WCSa[j] each have the same constant current I Wut function of outputting from the terminal T1. Note that in practice, in the manufacturing stage of the arithmetic circuit MACA1, errors may appear due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the error of the constant current I output from each of the terminals T1 of the plurality of current sources CS Wut is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In the present embodiment, description is made on the assumption that there is no error in the constant current I output from the terminals T1 of the plurality of current sources CS included in the circuit WCSa. Wut

[0122] The wirings DW[1] to DW[K] function as wirings for transmitting control signals for outputting the constant current I from the electrically connected current sources CS. Specifically, for example, when a high-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] outputs I as a constant current Wut flows to the second terminal of the switch S3[j], and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] does not output I. Wut flows to the second terminal of the switch S3[j], and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1], I Wut is not output. Further, for example, when a high-level potential is applied to the wiring DW[2], the two current sources CS electrically connected to the wiring DW[2] output a total of 2I Wut constant current flows to the second terminal of the switch S3[j], and when a low-level potential is applied to the wiring DW[2], the current sources CS electrically connected to the wiring DW[2] do not output a total of 2I Wut constant current. Further, for example, when a high-level potential is applied to the wiring DW[K], the 2 electrically connected to the wiring DW[K] K-1 current sources CS have a total of 2 K-1 I Wut ​When a constant current of is applied to the second terminal of switch S3[j] and a low-level potential is applied to wiring DW[K], the current sources CS electrically connected to wiring DW[K] have a total potential of 2 K-1 I Wut It does not output a constant current.

[0123] The current flowing from one current source CS electrically connected to wiring DW[1] corresponds to the value of the first bit, the current flowing from two current sources CS electrically connected to wiring DW[2] corresponds to the value of the second bit, and the current flowing from two current sources CS electrically connected to wiring DW[K] corresponds to the value of the second bit. J-1 The amount of current flowed by each current source CS corresponds to the value of the Kth bit. Now, consider the circuit WCSa when K is 2. For example, when the value of the 1st bit is "1" and the value of the 2nd bit is "0", a high-level potential is applied to wiring DW[1] and a low-level potential is applied to wiring DW[2]. At this time, a constant current I is supplied from circuit WCSa to the second terminal of switch S3[j] of circuit SWS1. Wut A current flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low-level potential is applied to wiring DW[1] and a high-level potential is applied to wiring DW[2]. At this time, a constant current of 2I is supplied from circuit WCSa to the second terminal of switch S3[j] of circuit SWS1. Wut A current flows. Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high-level potential is applied to wiring DW[1] and wiring DW[2]. At this time, a constant current of 3I is supplied from circuit WCSa to the second terminal of switch S3[j] of circuit SWS1. Wut A current flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to wiring DW[1] and wiring DW[2]. At this time, no constant current flows from circuit WCSa to the second terminal of switch S3[j] of circuit SWS1.

[0124] Note that FIG. 3A illustrates the circuit WCSa[j] in the case where K is an integer of 3 or more, but when K is 1, the circuit WCSa in FIG. 3A may be configured without providing the current source CS electrically connected to the wirings DW[2] to DW[K]. When K is 2, the circuit WCSa in FIG. 3A may be configured without providing the current source CS electrically connected to the wirings DW[3] to DW[K].

[0125] Next, a specific configuration example of the current source CS will be described.

[0126] A current source CS1 illustrated in FIG. 4A is a circuit applicable to the current source CS included in the circuit WCSa in FIG. 3A, and the current source CS1 includes a transistor Tr1 and a transistor Tr2.

[0127] A first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and a second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and a first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is electrically connected to the terminal T1, and the gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is electrically connected to the wiring DW.

[0128] The wiring DW is any one of the wirings DW[1] to DW[K] in FIG. 3A.

[0129] The wiring VDDL functions as a wiring that supplies a constant voltage. The constant voltage can be, for example, a high-level potential.

[0130] When the constant voltage supplied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of transistor Tr1. The potential at the second terminal of transistor Tr1 is lower than this high-level potential. In this case, the first terminal of transistor Tr1 functions as the drain, and the second terminal functions as the source. Furthermore, since the gate and the second terminal of transistor Tr1 are electrically connected, the gate-source voltage of transistor Tr1 is 0V. Therefore, if the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) within the subthreshold current range flows between the first and second terminals of transistor Tr1. The amount of this current, for example, 1.0 × 10⁻¹⁰, is an OS transistor. -8 It is preferable that it be less than or equal to A, and also 1.0 × 10 -12 It is more preferable that it be less than or equal to A, and also 1.0 × 10 -15 It is more preferable that the current is less than or equal to A. Furthermore, for example, it is more preferable that the current increases exponentially with respect to the gate-source voltage. In other words, transistor Tr1 functions as a current source for supplying a current within the current range when operating in the subthreshold region. Note that this current is as described above I Wut , or I described later Xut It corresponds to this.

[0131] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain and the second terminal of transistor Tr2 functions as a source. Also, since the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage is 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 will turn on when a high-level potential is input to its gate, and will turn off when a low-level potential is input to its gate. Specifically, when transistor Tr2 is on, a current within the current range of the subthreshold region described above flows from the second terminal of transistor Tr1 to terminal T1, and when transistor Tr2 is off, no current flows from the second terminal of transistor Tr1 to terminal T1.

[0132] Note that the current source CS included in the circuit WCSa[j] in Figure 3A is not limited to the current source CS1 in Figure 4A. For example, in current source CS1, the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, but the back gate of transistor Tr2 may be electrically connected to another wire. An example of such a configuration is shown in Figure 4B. In current source CS2 shown in Figure 4B, the back gate of transistor Tr2 is electrically connected to the wire VTHL. With current source CS2, the wire VTHL is electrically connected to an external circuit, and the external circuit provides a predetermined potential to the wire VTHL, thereby providing the predetermined potential to the back gate of transistor Tr2. This makes it possible to change the threshold voltage of transistor Tr2. In particular, by increasing the threshold voltage of transistor Tr2, the off-current of transistor Tr2 can be reduced.

[0133] Furthermore, for example, current source CS1 is configured such that the back gate of transistor Tr1 is electrically connected to the second terminal of transistor Tr1, but the voltage between the back gate and the second terminal of transistor Tr2 may be maintained by a capacitance. An example of such a configuration is shown in Figure 4C. Current source CS3 shown in Figure 4C has transistor Tr3 and capacitance C6 in addition to transistors Tr1 and Tr2. Current source CS3 differs from current source CS1 in that the second terminal of transistor Tr1 is electrically connected to the back gate of transistor Tr1 via capacitance C6, and the back gate of transistor Tr1 is electrically connected to the first terminal of transistor Tr3. Also, current source CS3 is configured such that the second terminal of transistor Tr3 is electrically connected to wiring VTL, and the gate of transistor Tr3 is electrically connected to wiring VWL. Current source CS3 can create a conductive state between wiring VTL and the back gate of transistor Tr1 by applying a high-level potential to wiring VWL and turning on transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of transistor Tr1. Then, by applying a low-level potential to the wiring VWL and turning off transistor Tr3, the voltage between the second terminal of transistor Tr1 and the back gate of transistor Tr1 can be maintained by capacitor C6. In other words, by determining the voltage that wiring VTL applies to the back gate of transistor Tr1, the threshold voltage of transistor Tr1 can be varied, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0134] Furthermore, for example, the current source CS4 shown in Figure 4D may be applied to the current source CS included in the circuit WCSa[j] in Figure 3A. In the current source CS4, the back gate of transistor Tr2 is electrically connected to the wiring VTHL instead of the second terminal of transistor Tr2, as in the current source CS3 in Figure 4C. In other words, the current source CS4, like the current source CS2 in Figure 4B, can vary the threshold voltage of transistor Tr2 by the potential supplied by the wiring VTHL.

[0135] In the current source CS4, when a large current flows between the first and second terminals of transistor Tr1, it is necessary to increase the on-current of transistor Tr2 in order to allow this current to flow from terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL, lowering the threshold voltage of transistor Tr2 and increasing the on-current of transistor Tr2, thereby allowing the large current flowing between the first and second terminals of transistor Tr1 to flow from terminal T1 to the outside of the current source CS4.

[0136] By applying current sources CS1 to CS4 shown in Figures 4A to 4D as the current source CS included in the circuit WCSa[j] in Figure 3A, the circuit WCSa can output a current corresponding to the first K-bit data. Furthermore, the amount of this current can be, for example, the amount of current flowing between the first and second terminals within the range in which transistor F1 operates in the subthreshold region.

[0137] Alternatively, the circuit WCSa[j] shown in Figure 4A may be used as the circuit WCSa[j] in Figure 3A. The circuit WCSa[j] in Figure 3B is configured such that one current source CS from Figure 4A is connected to each of the wires DW[1] through DW[K]. Furthermore, when the channel width of transistor Tr1[1] is w[1], the channel width of transistor Tr1[2] is w[2], and the channel width of transistor Tr1[K] is w[K], the ratio of their respective channel widths is w[1]:w[2]:w[K]=1:2:2 K-1Therefore, since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCSa shown in Figure 3B can output a current corresponding to the first K-bit data, similar to the circuit WCSa in Figure 3A.

[0138] Furthermore, transistors Tr1 (including transistors Tr1[1] to Tr1[K]), transistors Tr2 (including transistors Tr2[1] to Tr2[K]), and transistors Tr3 can be, for example, transistors applicable to transistor F1 or transistor F2. In particular, it is preferable to use OS transistors for transistors Tr1 (including transistors Tr1[1] to Tr1[K]), transistors Tr2 (including transistors Tr2[1] to Tr2[K]), and transistors Tr3.

[0139] [Circuit XCS] Next, we will describe an example configuration of circuit XCS, which corresponds to the peripheral circuit of the cell array CA.

[0140] Circuit XCS may have, for example, circuits XCSa[1] to XCSa[m] (a total of m circuits).

[0141] In Figure 2, circuit XCSa[1] is electrically connected to wiring XCL[1], for example, and circuit XCSa[m] is electrically connected to wiring XCL[m], for example.

[0142] Each of circuits XCSa[1] through XCSa[m] has the function of supplying signals to wiring XCL[1] through XCL[n] corresponding to the reference data described later, or signals corresponding to the second data. In the case of the arithmetic circuit MACA1 in Figure 2, the values ​​of each of the above signals can be expressed in terms of current.

[0143] Figure 3C is a block diagram showing an example of circuit XCS that can be applied to the arithmetic circuit MACA1 in Figure 2. Note that Figure 3C shows an excerpt of circuit XCSa[i], which corresponds to one of circuits XCSa[1] through XCSa[m]. Figure 3C also shows wiring XCL[i] to illustrate the electrical connections between circuit XCS and surrounding circuits.

[0144] Therefore, circuit XCSa[i] is electrically connected to wiring XCL[i].

[0145] The circuit XCSa[i] shown in Figure 3C includes a switch SWX as an example. The first terminal of switch SWX is electrically connected to wiring XCL[i], and the second terminal of switch SWX is electrically connected to wiring VINIL2. Wiring VINIL2 functions as a wire that provides an initialization potential to wiring XCL[i], and the initialization potential can be ground potential (GND), low level potential, or high level potential. The initialization potential provided by wiring VINIL2 may also be equal to the potential provided by wiring VINIL1. Note that switch SWX[i] is ON only when it provides an initialization potential to wiring XCL[i], and OFF at all other times.

[0146] Switch SWX can be, for example, a switch that can be applied to switch SWW.

[0147] Furthermore, the circuit configuration of circuit XCSa[i] in Figure 3C can be made almost identical to that of circuit WCSa[j] in Figure 3A. Specifically, circuit XCSa[i] has the function of outputting reference data as current quantity, and L bit (2 L It has the function of outputting a second data value (L is an integer greater than or equal to 1) as a current quantity, and in this case, circuit XCSa[i] is 2 LIt has one current source CS. The circuit XCSa[i] has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and 2 current sources CS that output information corresponding to the value of the L-th bit as a current L-1 has.

[0148] By the way, the reference data output by the circuit XCSa[i] as a current can be, for example, information in which the value of the first bit is "1" and the values of the second and subsequent bits are "0".

[0149] In FIG. 3C, the terminal T2 of one current source CS is electrically connected to the wiring DX[1], the respective terminals T2 of two current sources CS are electrically connected to the wiring DX[2], and 2 L-1 respective terminals T2 of the current sources CS are electrically connected to the wiring DX[L].

[0150] The plurality of current sources CS included in the circuit XCSa[i] each have a function of outputting I as the same constant current from the terminal T1. Xut Further, the wirings DX[1] to DX[L] function as wirings for transmitting a control signal for outputting I from the electrically connected current source CS. That is, the circuit XCSa[i] has a function of causing a current amount corresponding to the L-bit information sent from the wirings DX[1] to DX[L] to flow through the wiring XCL. Xut

[0151] Specifically, consider the circuit XCSa[i] in the case where L is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DX[1], and a low-level potential is applied to the wiring DX[2]. At this time, a constant current I flows from the circuit XCSa[i] to the wiring XCL. Xut Further, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low-level potential is applied to the wiring DX[1], and a high-level potential is applied to the wiring DX[2]. At this time, a constant current 2I flows from the circuit XCSa[i] to the wiring XCL[i]. Xut ​A current flows. Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high-level potential is applied to wiring DX[1] and wiring DX[2]. At this time, a constant current of 3I is supplied from circuit XCSa[i] to wiring XCL[i]. Xut A current flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to wiring DX[1] and wiring DX[2]. In this case, no constant current flows from circuit XCSa[i] to wiring XCL[i]. Note that in this specification, etc., it may be rephrased as a current of 0 flowing from circuit XCSa[i] to wiring XCL[i]. Also, the output current of circuit XCSa[i] is 0, I Xut , 2I Xut , 3I Xut These can be used as the second data output by circuit XCSa[i], and in particular, the current quantity I output by circuit XCSa[i] Xut This can be the reference data output by circuit XCSa[i].

[0152] Furthermore, if errors occur in circuit XCSa[i] due to variations in the electrical characteristics of the transistors included in each current source CS, the constant current I output from each of the terminals T1 of the multiple current sources CS will be reduced. Xut The error is preferably within 10%, more preferably within 5%, and most preferably within 1%. In this embodiment, the constant current I output from terminal T1 of the multiple current sources CS included in circuit XCSa Xut We will explain assuming there is no error.

[0153] Furthermore, as the current source CS of circuit XCSa[i], any of the current sources CS1 to CS4 shown in Figures 4A to 4D can be applied, similar to the current source CS of circuit WCSa[j]. In this case, the wiring DW shown in Figures 4A to 4D can be replaced with wiring DX. This allows circuit XCSa[i] to supply current within the subthreshold current range to wiring XCL[i] as reference data or the second data of L bits.

[0154] Furthermore, the same circuit configuration as the circuit WCSa[j] shown in Figure 3B can be applied to the circuit XCSa[i] in Figure 3C. In this case, one should replace the circuit WCSa[j] shown in Figure 3B with the circuit XCSa[i], replace wiring DW[1] with wiring DX[1], replace wiring DW[2] with wiring DX[2], replace wiring DW[K] with wiring DX[L], replace switch SWW with switch SWX, and replace wiring VINIL1 with wiring VINIL2.

[0155] [Circuit WSD] The circuit WSD has the function of selecting the row of the cell array CA to which the first data will be written by supplying a predetermined signal to the wiring WSL[i] when writing the first data to each cell of the cell array CA. For example, in Figure 1, the circuit WSD can supply a high-level potential to wiring WSL[1] and a low-level potential to wiring WSL[2] (not shown) to wiring WSL[m], thereby turning on transistors F1 and F1d, which have gates electrically connected to wiring WSL[1], and turning off transistors F1 and F1d, which have gates electrically connected to wiring WSL[2] to wiring WSL[m].

[0156] [Circuit ITS] Next, we will describe an example configuration of the circuit ITS, which corresponds to the peripheral circuitry of the cell array CA.

[0157] Circuit ITS includes, for example, circuit SWS2 and circuit ITRZ[j].

[0158] Circuit SWS2 has the function of making the connection between wiring WCL[j] and circuit ITRZ[j] conductive or non-conductive.

[0159] Circuit SWS2, for example, includes a switch S4[j]. The first terminal of switch S4[j] is electrically connected to wiring WCL[j], the second terminal of switch S4[j] is electrically connected to the first input terminal of the conversion circuit ITRZ[j] described later, and the control terminal of switch S4[j] is electrically connected to wiring SWL2.

[0160] Wiring SWL2 functions, for example, as wiring to switch between the ON and OFF states of switch S4[j]. Therefore, either a high-level potential or a low-level potential is supplied to wiring SWL2.

[0161] For switch S4[j], for example, a switch applicable to switch S3[j] can be used. In particular, it is preferable to use an OS transistor for switch S4[j]. Alternatively, an electrical switch such as an analog switch or a mechanical switch may be applied to switch S4[j].

[0162] As described above, circuit SWS2 has the function of making the connection between wiring WCL[j] and circuit ITS conductive or non-conductive. In other words, circuit SWS2 can switch between conductive and non-conductive states between circuit ITS and wiring WCL[j] using switch S4[j].

[0163] The conversion circuit ITRZ[j] has, for example, an input terminal and an output terminal. For instance, the input terminal of the conversion circuit ITRZ[j] is electrically connected to the second terminal of switch S4[j], and the output terminal of the conversion circuit ITRZ[j] is electrically connected to wiring OL[j].

[0164] The conversion circuit ITRZ[j], for example, has the function of acquiring the amount of current input from wiring WCL[j] to the input terminal when switch S4[j] is ON, and outputting a signal corresponding to that amount of current. This signal can be either a voltage or a current. The voltage can be, for example, an analog voltage or a digital voltage. The conversion circuit ITRZ[j] may also have a function-based arithmetic circuit. In this case, for example, the converted voltage may be used by the arithmetic circuit to perform a function calculation, and the result of the calculation may be output to wiring OL[j].

[0165] In particular, when performing calculations on hierarchical neural networks, the functions mentioned above can include, for example, the sigmoid function, tanh function, softmax function, ReLU function, or threshold function.

[0166] The conversion circuit ITRZ[j] shown in Figure 5A is an example of a circuit that can be applied to each of the conversion circuits ITRZ[j] in Figure 2. In addition, Figure 5A also shows circuit SWS2, wiring WCL[j], wiring SWL2, switch S4[j], and wiring OL[j] to show the electrical connections with the surrounding circuits of the conversion circuit ITRZ[j]. Wiring WCL[j] is one of the wirings WCL[1] to WCL[n] included in the arithmetic circuit MACA1 in Figure 2, switch S4[j] is one of the switches S4[1] to S4[n] included in the arithmetic circuit MACA1 in Figure 2, and wiring OL[j] is one of the wirings OL[1] to OL[n] included in the arithmetic circuit MACA1 in Figure 2.

[0167] The conversion circuit ITRZ[j] in Figure 5A is electrically connected to the wiring WCL via switch S4[j]. The conversion circuit ITRZ[j] is also electrically connected to the wiring OL[j]. For example, the conversion circuit ITRZ[j] has the function of converting the amount of current flowing from the conversion circuit ITRZ[j] to the wiring WCL[j], or from the wiring WCL[j] to the conversion circuit ITRZ[j], into an analog voltage, and then converting the analog voltage into a digital voltage and then an analog current, and outputting the analog current to the wiring OL[j].

[0168] The conversion circuit ITRZ[j] in Figure 5A includes, as an example, a load LE, an operational amplifier OP1, and an analog-to-digital conversion circuit ADC.

[0169] The inverting input terminal of operational amplifier OP1 is electrically connected to the first terminal of load LE and the second terminal of switch S4[j]. The non-inverting input terminal of operational amplifier OP1 is electrically connected to wiring VRL. The output terminal of operational amplifier OP1 is electrically connected to the second terminal of load LE and the input terminal of analog-to-digital conversion circuit ADC. The output terminal of analog-to-digital conversion circuit ADC is electrically connected to wiring OL[j].

[0170] Wiring VRL functions as wiring that provides a constant voltage. This constant voltage can be, for example, the ground potential (GND) or a low-level potential.

[0171] For the load LE, for example, a resistor, diode, or transistor can be used.

[0172] In the conversion circuit ITRZ[j], the configuration of the operational amplifier OP1 and the load LE allows the current flowing from the wiring WCL to the inverting input terminal of operational amplifier OP1 and the first terminal of the load LE via switch S4[j], or the current flowing from the inverting input terminal of operational amplifier OP1 and the first terminal of the load LE to the wiring WCL[j] via switch S4[j], to be converted into an analog potential. This analog potential is then input to the input terminal of the analog-to-digital conversion circuit ADC.

[0173] In particular, by setting the constant voltage supplied by wiring VRL to ground potential (GND), the inverting input terminal of operational amplifier OP1 becomes a virtual ground, and therefore the analog voltage output to wiring OL[j] can be a voltage referenced to ground potential (GND).

[0174] An analog-to-digital converter (ADC) has the function of outputting a digital voltage corresponding to an analog voltage to wiring OL[j] when an analog voltage is input to the input terminal of the ADC.

[0175] Note that the wiring OL[j] here refers to one or more wirings. The number of wirings OL[j] is determined, for example, by the resolution of the analog-to-digital converter (ADC). For example, if the resolution of the ADC is 1 bit, the number of wirings OL[j] can be 1, and if the resolution of the ADC is 8 bits, the number of wirings OL[j] can be 8.

[0176] Furthermore, the analog-to-digital converter (ADC) can be considered as one of the function-based arithmetic circuits described above. Therefore, if it is desired to use a different function-based arithmetic circuit in the converter circuit ITRZ[j], the analog-to-digital converter (ADC) can be replaced with a circuit that performs the desired function operation. It is preferable that the circuit performing the function operation has an analog voltage as its input and a digital voltage as its output.

[0177] Furthermore, although the conversion circuit ITRZ[j] in Figure 5A is configured to output a digital signal, it is also possible to omit the analog-to-digital conversion circuit ADC in the conversion circuit ITRZ[j] and instead output the analog potential of the output terminal of the operational amplifier OP1 directly to the wiring OL[j]. Specifically, as shown in the conversion circuit ITRZ[j] in Figure 5B, the conversion circuit ITRZ[j] in Figure 5A may be configured without the analog-to-digital conversion circuit ADC.

[0178] [Circuit FB] Circuit FB is, for example, a circuit that performs the calculations necessary to correct the potential corresponding to the first data written to cell IM[1,j] or cell IM[m,j].

[0179] The circuit FB shown in Figure 6A is an example of a circuit that can be applied to the circuit FB shown in Figures 1 and 2 when the conversion circuit ITRZ[j] included in the circuit ITS outputs a digital signal (for example, when the conversion circuit ITRZ[j] shown in Figure 5A is applied to the conversion circuit ITRZ[j] in Figure 2). In addition, the control circuit CTR and wiring OL[j] are also shown in Figure 6A to show the electrical connection with the surrounding circuits of circuit FB. Note that wiring OL[j] is one of the wirings OL[1] to OL[n] included in the arithmetic circuit MACA0 in Figure 1.

[0180] The circuit FB in Figure 6A has, as an example, the circuit SBT[j].

[0181] The circuit SBT[j] shown in Figure 6A has a first input terminal, a second input terminal, and an output terminal. The control circuit CTR here, as an example, has terminal IT and terminal OT1.

[0182] The first input terminal of circuit SBT[j] is electrically connected to wiring OL[j]. The second input terminal of circuit SBT[j] is electrically connected to terminal OT1 of control circuit CTR. The output terminal of circuit SBT[j] is electrically connected to terminal IT of control circuit CTR.

[0183] The wiring OL[j] is supplied with a digital signal output from the conversion circuit ITRZ[j]. Therefore, this digital signal is input to the first input terminal of circuit SBT[j].

[0184] The control circuit CTR in this configuration has the function of outputting comparison data to terminal OT1. The comparison data can be, for example, data used to determine whether the first data read from cell IM[1,j] to cell IM[m,j] is an appropriate value. Therefore, the comparison data can be, for example, the first data transmitted from the control circuit CTR to circuit XCSa when writing to cell IM[1,j] to cell IM[m,j]. In this configuration example, the second input terminal of circuit SBT[j] receives the first data used when writing to cell IM[1,j] to cell IM[m,j]. Note that in Figure 6A, this first data is shown as a digital signal.

[0185] Circuit SBT[j] has the function of calculating the difference between the value of the digital signal from the conversion circuit ITRZ[j] input to the first input terminal and the value of the first data from the control circuit CTR input to the second input terminal, and outputting the calculation result (hereinafter referred to as the difference value) as a digital signal to the output terminal of circuit SBT[j]. In other words, circuit SBT[j] can be a subtractor composed of digital circuits.

[0186] Furthermore, for example, by outputting the value of the first data to be written to cell IM[i,j] as a digital signal from terminal OT1 of the control circuit CTR, and outputting the value read from cell IM[i,j] to which the first data was written as a digital signal from wiring OL[j], circuit SBT[j] can obtain the difference between the first data at the time of writing and the first data at the time of reading. If the difference value in circuit SBT[j] is 0, it can be seen that the first data at the time of writing and the first data at the time of reading are the same. On the other hand, if the difference value in circuit SBT[j] is not 0, it can be seen that the first data at the time of writing and the first data at the time of reading are not the same, and therefore it can be seen that the first data written to cell IM[i,j] is deviating from the value of the first data at the time of writing.

[0187] By the way, if the conversion circuit ITRZ[j] included in circuit ITS outputs an analog potential instead of a digital signal (for example, if the conversion circuit ITRZ[j] shown in Figure 5B is applied to the conversion circuit ITRZ[j] in Figure 2), then circuit FB in Figure 6A can be changed to the circuit configuration of circuit FB shown in Figure 6B.

[0188] The circuit SBT[j] shown in Figure 6B includes, as an example, a digital-to-analog conversion circuit DAC, loads LE1 to LE4, and an operational amplifier OP2.

[0189] The first terminal of load LE1 is electrically connected to the first input terminal of circuit SBT[j], and the second terminal of load LE1 is electrically connected to the first terminal of load LE2 and the inverting input terminal of op-amp OP2. The second terminal of load LE2 is electrically connected to the output terminal of op-amp OP2 and the output terminal of circuit SBT[j]. The input terminal of the digital-to-analog conversion circuit DAC is electrically connected to the second input terminal of circuit SBT[j], and the output terminal of the digital-to-analog conversion circuit DAC is electrically connected to the first terminal of load LE3. The second input terminal of load LE3 is electrically connected to the non-inverting input terminal of op-amp OP2 and the first terminal of load LE4. The second terminal of load LE4 is electrically connected to wiring VGL.

[0190] Wiring VGL functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, the ground potential (GND) or a low-level potential.

[0191] A digital-to-analog converter (DAC) is, for example, a device that, when a digital signal is input to the input terminal of the DAC, outputs an analog potential corresponding to that digital signal to the output terminal of the DAC.

[0192] For loads LE1 to LE4, for example, resistors, diodes, or transistors can be used, similar to load LE.

[0193] The circuit SBT[j] shown in Figure 6B can be used as an analog potential subtractor by making the resistance values ​​of loads LE1 to LE4 equal.

[0194] For example, the value of the first data to be written to cell IM[i,j] is output as a digital signal from terminal OT1 of the control circuit CTR. This digital signal is then converted to an analog potential by the digital-to-analog conversion circuit DAC of circuit SBT[j]. In addition, the value read from cell IM[i,j] on which the first data was written is input as an analog potential to wiring OL[j]. As a result, circuit SBT[j] can take the difference between the analog potential corresponding to the first data at the time of writing and the analog potential corresponding to the first data at the time of reading.

[0195] The control circuit CTR can determine whether the first data at the time of writing and the first data at the time of reading match or not by obtaining the difference value output from the output terminal of circuit SBT[j] via terminal IT. For example, if the difference value in circuit SBT[j] is 0, the control circuit CTR determines that the first data at the time of writing and the first data at the time of reading match. On the other hand, if the difference value in circuit SBT[j] is not 0, the control circuit CTR determines that the first data at the time of writing and the first data at the time of reading do not match, and therefore the control circuit CTR determines that the first data written to cell IM[i,j] is deviating from the value of the first data at the time of writing. This allows the control circuit CTR to determine whether or not correction is necessary for the first data written to cell IM[i,j].

[0196] Furthermore, the circuit FB may not be configured to determine that the first data at the time of writing and the first data at the time of reading match when the difference value output from the circuit SBT[j] is 0, as shown in the configurations of Figures 6A and 6B. Instead, it may be configured to determine that the first data at the time of writing and the first data at the time of reading match when the difference value output from the circuit SBT[j] falls within a predetermined range.

[0197] This circuit configuration is shown in Figure 6C. The circuit FB shown in Figure 6C is configured by adding a comparator circuit CMP[j] to the circuit FB shown in Figure 6A or Figure 6B. Note that each of the multiple wires shown in Figure 6C is supplied with either an analog potential or a digital signal.

[0198] In Figure 6C, the control circuit CTR includes, as an example, terminal IT, terminal OT1, and terminal OT2.

[0199] The comparison circuit CMP[j], for example, has a first input terminal, a second input terminal, and an output terminal.

[0200] The first input terminal of the comparator circuit CMP[j] is electrically connected to the output terminal of circuit SBT[j]. The second input terminal of the comparator circuit CMP[j] is electrically connected to terminal OT2 of the control circuit CTR. Furthermore, the output terminal of the comparator circuit CMP[j] is electrically connected to terminal IT of the control circuit CTR.

[0201] The control circuit CTR here has the function of outputting reference data to terminal OT2. Reference data can be, for example, data (hereinafter referred to as the reference value) used to determine whether the difference between the first data at the time of writing and the first data at the time of reading, transmitted from the output terminal of circuit SBT[j], falls within an acceptable range.

[0202] Therefore, the comparator circuit CMP[j] has the function of comparing, for example, the value input to the first input terminal with the value input to the second input terminal and outputting the result of their greater-than-less-than relationship to the output terminal. Alternatively, the comparator circuit CMP[j] may have the function of obtaining the absolute value of the value input to the first input terminal, comparing that absolute value with the value input to the second input terminal, and outputting the result of their greater-than-less-than relationship to the output terminal. For this reason, the comparator circuit CMP[j] can be referred to as a comparator.

[0203] For example, when δ is input as a reference value from terminal OT2 of control circuit CTR to the second input terminal of comparator circuit CMP[j], comparator circuit CMP[j] outputs the result of the relationship between the difference between the first data at the time of writing and the first data at the time of reading, which is input to the first input terminal, and the reference value δ, from the output terminal of comparator circuit CMP[j].

[0204] The control circuit CTR can determine whether the first data at the time of writing and the first data at the time of reading match or not by acquiring the result output from the output terminal of the comparison circuit CMP[j] via terminal IT. For example, if the difference between the first data at the time of writing and the first data at the time of reading in the comparison circuit CMP[j] is smaller than the reference value δ, the control circuit CTR determines that the first data at the time of writing and the first data at the time of reading match approximately. On the other hand, if the difference between the first data at the time of writing and the first data at the time of reading is larger than the reference value δ, the control circuit CTR determines that the first data at the time of writing and the first data at the time of reading do not match. As a result, the control circuit CTR can determine whether or not correction is necessary for the first data written to cell IM[i,j].

[0205] Note that the difference values ​​mentioned above may be absolute values.

[0206] Furthermore, the aforementioned reference value δ can be determined, for example, according to the distribution width (sometimes referred to as bit precision) of each binary or multi-level potential written to cell IM[i,j].

[0207] [Control circuit CTR] The control circuit CTR, for example, has the function of controlling circuits WCS, SWS1, SWS2, WSD, XCS, and ITS, which correspond to the peripheral circuits of the cell array CA.

[0208] The control circuit CTR has the function of transmitting a signal to circuit WCSa[j] corresponding to the first data to be written to cell IM[1,j] to cell IM[m,j]. This signal can be a digital signal transmitted to wiring DW[1] to wiring DW[K] in circuit WCSa[j].

[0209] Furthermore, the control circuit CTR has the function of transmitting a signal corresponding to the second data to circuits XCSa[1] to XCSa[m], for example. This signal can be a digital signal transmitted to wiring DX[1] to DX[L] in circuit XCSa[j].

[0210] Furthermore, the control circuit CTR has the function of switching the on state and the off state of switch S3[j] included in circuit SWS1, for example. Therefore, the control circuit CTR is electrically connected to wiring SWL1. Similarly, the control circuit CTR has the function of switching the on state and the off state of switch S4[j] included in circuit SWS2, for example. Therefore, the control circuit CTR is electrically connected to wiring SWL2.

[0211] Furthermore, the control circuit CTR has the function of transmitting control signals to the circuit WSD, for example. The control circuit CTR also has the function of transmitting signals to the circuit WSD that include the address of any row from row 1 to row m of the cell array CA to be written for writing the first data.

[0212] The control circuit CTR has, for example, terminal IT and terminal OT. Terminal IT corresponds to terminal IT in Figures 6A to 6C described above. Terminal OT corresponds to terminal OT1 and terminal OT2 in Figures 6A to 6C described above.

[0213] Furthermore, terminals IT and OT of the control circuit CTR are electrically connected to circuit FB.

[0214] The control circuit CTR has the function of transmitting, for example, an analog potential or digital signal corresponding to the value required for the calculation performed by circuit FB to circuit FB via terminal OT. Furthermore, the control circuit CTR has the function of acquiring, for example, the result of the calculation performed by circuit FB via terminal IT.

[0215] By the way, in the arithmetic circuit MACA1 shown in Figure 2, when writing the first data to cell IM[i,j] (not shown), the transistor F1 contained in cell IM[i,j] is turned ON, and the transistors F1 contained in cells IM[1,j] to IM[m,j] other than cell IM[i,j] that are electrically connected to wiring WCL[j] are turned OFF. Next, the switch S3[j] is turned ON, and the switch S4[j] is turned OFF, and a current corresponding to the first data flows from circuit WCSa[j] to cell IM[i,j] via switch S3[j], thereby setting the potential of node N[i,j]. At this time, a current corresponding to the first data flows between the source and drain of transistor F2, so the potential of the gate of transistor F2 (node ​​N[i,j]) is naturally determined. After that, by turning off the transistor F1 of cell IM[i,j], the potential of node N[i,j] can be maintained by capacitor C5.

[0216] At this time, the value of the first data to be written to cell IM[i,j] is determined by the amount of current flowing through cell IM[i,j]. In other words, the node N[i,j] of cell IM[i,j] is determined to have either an analog potential or a multi-level potential depending on the value of the first data.

[0217] When the first data is multi-valued data, if there is a large variation in the potential written to node N[i,j] of cell IM[i,j], the first data written to cell IM[i,j] may deviate from the desired value. For example, variations in the manufacturing of transistors F1, F2, F5, and capacitor C5 in cell IM[i,j] may cause the amount of current flowing to cell IM[i,j] when writing the first data to differ from the amount of current output from cell IM[i,j] during calculation.

[0218] If the amount of current flowing through cell IM[i,j] when the first data is written differs from the amount of current output from cell IM[i,j] during calculation, the first data written to cell IM[i,j] may be read as an incorrect value. For this reason, it is preferable that the amount of current output from cell IM[i,j] during calculation is equal to the amount of current used when the first data is written to cell IM[i,j].

[0219] <<Example 1 of the first data writing operation including correction processing>> Here, we will explain the potential correction process written to node N[i,j] of cell IM[i,j] in the arithmetic circuit MACA1 shown in Figure 2, so that cell IM[i,j] to which the first data is written outputs an appropriate amount of current corresponding to the first data.

[0220] Figure 7 is a flowchart showing an example of a first data writing operation including correction processing. This writing operation has steps S101 to S106. In Figure 7, the start of the writing operation is indicated as "START" and the end of the writing operation is indicated as "END".

[0221] [Step S101] Step S101, as an example, involves the control circuit CTR sending the value of the first data to the circuit WCSa[j] included in the circuit WCS from the control circuit CTR. TRG It has an operation in which a signal equivalent to the above is input.

[0222] In the circuit WCSa[j] in Figure 3, W TRG The corresponding signals can be, for example, digital signals input to each of the wirings DW[1] to DW[K].

[0223] From this point onward, the value of the digital signal input to each of the wirings DW[1] through DW[K] is W WR It is referred to as such. For example, at step S101, W WR =W TRG This is the result.

[0224] [Step S102] Step S102 is, as an example, when circuit WCSa[j] is input to each of the wirings DW[1] through DW[K], the value W of the digital signal. WR Amount I corresponding to WR Generates a current (referred to as the writing current) and I WR The operation involves sending the current to the wiring WCL[j] and sending I to cell IM[i,j]. WR The write current flows through the first terminal (node ​​N[i,j]) of the capacitance C5 of cell IM[i,j], and I WR It has the operation of writing a potential corresponding to the writing current.

[0225] In the circuit WCSa[j] in Figure 3, the quantity I corresponds to the first data. WR This can be generated by one or more current sources CS included in the circuit WCSa[j].

[0226] Furthermore, by inputting a high-level potential to the wiring SWL1 and applying that high-level potential to the control terminal of switch S3[j], switch S3[j] can be turned ON. This allows the I generated in circuit WCSa[j] to be turned ON. WR The current can be passed through the wiring WCL[j].

[0227] Furthermore, among the wirings WSL[1] through WSL[m], a high-level potential is input to wiring WSL[i], and a low-level potential is input to the wirings WSL[1] through WSL[m] other than those in row i. This makes it possible to turn on transistor F1 in cell IM[i,j] and turn off transistor F1 in cells IM[1,j] through IM[m,j] located in column j.

[0228] Furthermore, among cells IMd[1] to IMd[m], cell IMd[i] contains quantity I from circuit XCSa[i]. ref0 (=I Xut ) Assume that a current of ) flows (Note that I ref0 (=I Xut ) is the amount of current corresponding to the second data with a value of "1", and I flows from circuit XCSa[i] ref0 This will be explained in detail in Operation Example 1 of the arithmetic circuit described later). Also, as a result, the potential of wiring XCL[i] becomes V gm It is assumed that the following will occur. Furthermore, each of the cells IMd[1] through IMd[m] other than row i will be supplied with ground potential (GND) from each of the circuits XCSa[1] through XCSa[m]. In other words, the potential of each of the wirings XCL[1] through XCL[m] other than row i will be GND.

[0229] By the way, since the transistors F1 contained in cells IM[1,j] through IM[m,j] located in column j, excluding row i, are in the off state, the nodes N[1,j] through N[m,j], excluding row i, are in the floating state. At this time, the potential of each of the wirings XCL[1] through XCL[m], excluding row i, becomes GND, and the potential of each of the nodes N[1,j] through N[m,j], excluding row i, also changes. At this time, the transistors F2 contained in each of the cells IM[1,j] through IM[m,j] located in column j, excluding row i, are assumed to be in the off state.

[0230] Furthermore, by inputting a low-level potential to the wiring SWL2 and applying that low-level potential to the control terminal of switch S4[j], switch S4[j] can be turned off.

[0231] As described above, switch S3[j] is ON, switch S4[j] is OFF, and transistors F1 and F2 of cells IM[1,j] to IM[m,j] located in column j other than row i are OFF, therefore the I generated by circuit WCSa[j] WR The current flows only through cell IM[i,j]. Also, at this time, in cell IM[i,j], I WR As the write current flows, the potential of the gate of transistor F2 (node ​​N[i,j]) is automatically determined. Subsequently, by inputting a low-level potential to wiring WSL[i] and turning off transistor F1 of cell IM[i,j], the potential of node N[i,j] can be maintained by capacitor C5. In other words, the first data can be written to cell IM[i,j].

[0232] [Step S103] Step S103, as an example, involves reading the first data written to cell IM[i,j]. In other words, step S103 involves cell IM[i,j] outputting a read current corresponding to the potential of capacitor C5 (node ​​N[i,j]), and the read current being input to the conversion circuit ITRZ[j], causing the conversion circuit ITRZ[j] to output a value corresponding to the read current to wiring OL[j].

[0233] Specifically, for example, by inputting a low-level potential into wiring SWL1 and applying that low-level potential to the control terminal of switch S3[j], switch S3[j] is turned off. Also, by inputting a high-level potential into wiring SWL2 and applying that high-level potential to the control terminal of switch S4[j], switch S4[j] is turned on.

[0234] Furthermore, a low-level potential is continuously applied to each of the wirings WSL[1] through WSL[m] to maintain the off state of transistor F1 in each of the cells IM[1,j] through IM[m,j] located in the j-th column.

[0235] Also, from step S102, the potential of wiring XCL[i] is V gm This maintains the potential of each wiring XCL[1] through XCL[m] other than row i to GND. This keeps the transistor F2 contained in each of cells IM[1,j] through IM[m,j] located in column j other than row i in the off state.

[0236] In cell IM[i,j], the potential written in step S102 is held at node N[i,j]. Here, assuming the potential supplied by wiring VE0 is the ground potential, the source-drain current of transistor F2 in cell IM[i,j] is determined according to the gate potential of transistor F2. Furthermore, the source-drain current of transistor F2 is assumed to flow from wiring WCL[j] to cell IM[i,j] as the read current in step S103. Here, the amount of the source-drain current (read current) of transistor F2 in cell IM[i,j] is I RD Let's assume that the potential of node N[i,j] in cell IM[i,j] is appropriate, then the amount of writing current I WR And the amount of read current I RD and are equal to each other.

[0237] As described above, switch S3[j] is in the off state, switch S4[j] is in the on state, and transistors F1 and F2 of cells IM[1,j] to IM[m,j] located in column j other than row i are in the off state, therefore the setting I in cell IM[i,j] RD The current is output from the conversion circuit ITRZ[j] of circuit ITS via switch S4[j].

[0238] The current I is transmitted from the conversion circuit ITRZ[j] through switch S4[j] to the wiring WCL[j].RD As the current flows, the conversion circuit ITRZ[j] receives the current I RD It outputs a potential corresponding to the value W read from cell IM[i,j]. RD It is then sent to circuit FB.

[0239] Specifically, the conversion circuit ITRZ[j] converts the current I through the current-voltage conversion circuit (operational amplifier OP1 and load LE). RD The voltage is converted to an analog potential. The conversion circuit ITRZ[j] then reads the value W from cell IM[i,j] from the analog potential. RD The signal containing this is sent to circuit FB. For example, if the conversion circuit ITRZ[j] in Figure 5B is applied as the conversion circuit ITRZ[j], the value W RD A signal containing this can be output as an analog potential.

[0240] Furthermore, the conversion circuit ITRZ[j] converts the analog potential into a digital signal using an analog-to-digital conversion circuit, and reads the value W from the cell IM[i,j] of the digital signal. RD The signal containing the following may be transmitted to circuit FB. In this case, for example, if the conversion circuit ITRZ[j] shown in Figure 5A is applied as the conversion circuit ITRZ[j], the value W RD A signal containing this can be output as a digital signal.

[0241] [Step S104] Step S104, as an example, shows that the circuit FB has a value W as the first data. TRG And the value W read from cell IM[i,j] RD It has the operation of comparing and .

[0242] Specifically, step S104 is W TRG and W RD If they are equal, the operation to terminate the write operation including the correction process and W TRG and W RD If they are not equal, the operation proceeds to step S105.

[0243] In step S104, a signal containing the value W from the wiring OL[j] is input to the first input terminal of the circuit SBT[j] included in the circuit FB RD . Further, a signal containing the value W from the control circuit CTR is input to the second input terminal of the circuit SBT[j] TRG . Thereby, a signal containing the value W is output from the output terminal of the circuit SBT[j] RD and the value W TRG , as a difference value W TRG -W RD (=ΔW1).

[0244] [Step S105] As an example, step S105 includes an operation in which the control circuit CTR generates corrected first data for rewriting to the cell IM[i,j].

[0245] Specifically, step S105 includes an operation in which the control circuit CTR acquires ΔW1 from the circuit SBT[j] included in the circuit FB, and generates W as the corrected first data WR +ΔW1 (hereinafter referred to as an updated value).

[0246] Note that the updated value may be set as W using a desired coefficient s WR +s·ΔW1. By setting the updated value to W WR +s·ΔW1, the number of loops from step S102 to step S106 may be reduced in some cases.

[0247] [Step S106] As an example, step S106 includes an operation in which a signal corresponding to the updated value W+ΔW is input from the control circuit CTR to the circuit WCSa[j] included in the circuit WCS WR , and an operation of shifting to step S102.

[0248] That is, in the circuit WCSa[j] of FIG. 3, the value of the digital signal input to each of the wirings DW[1] to DW[K] is a value obtained by further adding ΔW to the value of W previously input to the circuit WCSa[j] WR .

[0249] Therefore, after the transition from step S106 to step S102, W described in steps S102 to S106 described above WR can be described as being replaced with the updated value W WR +ΔW.

[0250] Thereafter, by repeating steps S102 to S106 until W in step S104 TRG and W RD are equal (the difference between the write current and the read current becomes 0), a potential corresponding to the first data can be appropriately written into the cell IM[i,j].

[0251] As described above, by performing steps S101 to S106, variations at the time of writing the first data to the cell IM[i,j] can be suppressed.

[0252] <<Example 2 of First Data Write Operation Including Correction Processing>> Note that the first data write operation including the correction processing of the semiconductor device of one embodiment of the present invention is not limited to the flowchart shown in FIG. 7. The flowchart shown in FIG. 7 may be modified as appropriate.

[0253] For example, in the flowchart of FIG. 7, the write operation of the first data including the correction processing is terminated when the value W as the first data TRG and the value W read from the cell IM[i,j] RD are equal, but the flowchart may be configured such that the write operation of the first data including the correction processing is terminated when the difference between W TRG and W RD is within a predetermined range.

[0254] The flowchart in Figure 8 is a modified version of the flowchart in Figure 7, differing from the flowchart in Figure 7 in that it includes steps S107 and S108 instead of step S104. In Figure 8, the start of the write operation is indicated as "START," and the end of the write operation is indicated as "END."

[0255] [Step S107] Step S107, as an example, shows that the circuit FB has a value W as the first data. TRG And the value W read from cell IM[i,j] RD It has the operation of obtaining the difference between and .

[0256] In step S107, the first input terminal of circuit SBT[j] included in circuit FB receives the value W from wiring OL[j]. RD A signal corresponding to this is input. In addition, the value W from the control circuit CTR is input to the second input terminal of circuit SBT[j]. TRG A signal corresponding to this is input. As a result, the output terminal of circuit SBT[j] receives the value W. RD and value W TRG W as the difference value TRG -W RD A signal corresponding to (=ΔW1) is output.

[0257] [Step S108] Step S108, as an example, involves the control circuit CTR determining whether the absolute value of ΔW1 (hereinafter referred to as |ΔW1|) is smaller than the reference value δ.

[0258] Specifically, step S108 includes an operation to terminate the writing operation, including the correction process, if |ΔW1| is smaller than the reference value δ, and an operation to proceed to step S105 if |ΔW1| is larger than the reference value δ.

[0259] If |ΔW1| is equal to the reference value δ, the system may choose to either terminate the writing operation including the correction process, or proceed to step S105.

[0260] The control circuit CTR obtains ΔW1 from the output terminal of circuit SBT[j] included in circuit FB, and compares |ΔW1| with the reference value δ.

[0261] Therefore, it is preferable that the control circuit CTR is equipped with a comparator that compares |ΔW1| with a reference value δ. Alternatively, instead of the control circuit CTR, a comparator circuit CMP[j] may be provided in the circuit SBT[j] included in the circuit FB, as shown in Figure 6C, which functions as a comparator.

[0262] The value of the reference value δ can be determined according to the distribution width (sometimes called bit precision) of each binary or multi-level potential written to cell IM[i,j]. Specifically, for example, if the bit precision is low, such as with binary potentials, the reference value δ should be increased, and if the bit precision is high, such as with three or more levels, the reference value δ should be decreased.

[0263] [Step S105 and later] From step S105 onward, as in the flowchart in Figure 7, the control circuit CTR receives the corrected first data (updated value) as W WR You just need to generate +ΔW1 and write it back to cell IM[i,j].

[0264] In the flowchart of Figure 8, step S108 does not necessarily have an operation to determine whether |ΔW1| is smaller than the reference value δ and terminate the operation if it is smaller than the reference value δ. Instead, it may have an operation to terminate the operation when the processes from step S105 to step S106 have been performed a predetermined number of times.

[0265] For example, the value read from cell IM[i,j] in step S103 is W RD =(1+σ)W WR It may be written as follows. Note that σ is W WR From W RD This value represents the change to as a percentage. For example, W WR W decreased by 10% RDIn this case, σ = -0.1.

[0266] In step S103, the value read from cell IM[i,j] is W RD =(1+σ)W WR When it can be written as such, by repeatedly performing the processes from step S105 to step S106, W RD to W WR It may be possible to converge to this.

[0267] Here, for example, step S108 has the function of terminating when the process from step S105 to step S106 has been performed N times (where N is an integer of 1 or more).

[0268] When the processing from step S105 to step S106 is performed for the first time, W TRG =W WR , W RD =(1+σ)W WR Therefore, ΔW1 = W TRG -W RD =W TRG -(1+σ)W TRG =-σW TRG This is the result.

[0269] The process from step S105 to step S106 for the Nth time is performed, and the value read from cell IM[i,j] is W RD =W TRG {1+(-1) N-1 σ N It can be written as}. Note that the difference value in this case is ΔW1=W TRG (-σ) N This is the result.

[0270] In other words, by knowing σ, W RD The number of processing steps N required for convergence can be estimated.

[0271] As stated above, W RDIf the number of processing steps N required for convergence can be estimated, it becomes unnecessary to compare the difference value ΔW1 with the reference value δ each time steps S105 to S106 are repeated. Therefore, instead of step S108 having an operation that determines whether |ΔW1| is smaller than the reference value δ and terminates the operation when it is smaller than the reference value δ, having an operation that terminates the operation when the processing from steps S105 to S106 has been performed a predetermined number of times makes it possible to speed up the writing operation of the first data, including the correction processing.

[0272] <Example of arithmetic circuit configuration 2> Furthermore, the semiconductor device according to one embodiment of the present invention is not limited to the arithmetic circuit MACA1 shown in Figure 2. The arithmetic circuit MACA1 shown in Figure 2 may be modified depending on the circumstances.

[0273] The arithmetic circuit MACA2 shown in Figure 10 is a modified version of the arithmetic circuit MACA1 shown in Figure 2, and differs from the arithmetic circuit MACA1 in that it does not have a circuit FB.

[0274] In the arithmetic circuit MACA2, the conversion circuit ITRZ[j] included in the circuit ITS is assumed to be the conversion circuit ITRZ[j] shown in Figure 5A or Figure 5B.

[0275] The MACA2 arithmetic circuit shown in Figure 10 is configured such that the signal output from the ITRZ[j] conversion circuit is input to the CTR control circuit.

[0276] <<Example 3 of the first data writing operation including correction processing>> Next, we will explain the potential correction process written to node N[i,j] of cell IM[i,j] in the MACA2 arithmetic circuit shown in Figure 10, so that cell IM[i,j] on which the first data is written outputs a current of an appropriate amount corresponding to the first data.

[0277] Figure 11 is a flowchart showing an example of a first data writing operation including correction processing. This writing operation has steps S101, S102, S103A, S104A, and S106.

[0278] Note that the flowchart in Figure 11 is a modified version of the flowchart in Figure 7, and differs from the flowchart in Figure 7 in that step S103A is performed instead of step S103, step S104A is performed instead of step S104, and step S105A is performed instead of step S105. Also, in the operation method of the flowchart in Figure 11, explanations may be omitted for parts that are the same as the operation method of the flowchart in Figure 7.

[0279] [Step S101] Step S101 in the flowchart of Figure 11 performs the same operation as step S101 in the flowchart of Figure 7.

[0280] [Step S102] Step S102 in the flowchart of Figure 11 performs the same operation as step S102 in the flowchart of Figure 7.

[0281] [Step S103A] Step S103A is, as an example, the I generated in step S102. WR The operation includes sending the write current to the wiring WCL[j], outputting a read current corresponding to the first data written to cell IM[i,j], and inputting the difference current between the write current and the read current to the conversion circuit ITRZ[j], causing the conversion circuit ITRZ[j] to output a value corresponding to the difference current to the wiring OL[j].

[0282] Specifically, for example, by inputting a high-level potential into wiring SWL1 and applying that high-level potential to the control terminal of switch S3[j], switch S3[j] is turned ON. Similarly, by inputting a high-level potential into wiring SWL2 and applying that high-level potential to the control terminal of switch S4[j], switch S4[j] is turned ON.

[0283] Furthermore, a low-level potential is continuously applied to each of the wirings WSL[1] through WSL[m] to maintain the off state of transistor F1 in each of the cells IM[1,j] through IM[m,j] located in the j-th column.

[0284] Also, from step S102, the potential of wiring XCL[i] is V gm This maintains the potential of each wiring XCL[1] through XCL[m] other than row i to GND. This keeps the transistor F2 contained in each of cells IM[1,j] through IM[m,j] located in column j other than row i in the off state.

[0285] In cell IM[i,j], the potential written in step S102 is held at node N[i,j]. Here, assuming the potential supplied by wiring VE0 is the ground potential, the source-drain current of transistor F2 in cell IM[i,j] is determined according to the gate potential of transistor F2. Furthermore, the source-drain current of transistor F2 is assumed to flow from wiring WCL[j] to cell IM[i,j] as the read current in step S103A. Here, the amount of the source-drain current (read current) of transistor F2 in cell IM[i,j] is I RD Let's assume that the potential of node N[i,j] in cell IM[i,j] is appropriate, then the amount of writing current I WR And the amount of read current I RD and are equal to each other.

[0286] As described above, switch S3[j] is ON, switch S4[j] is ON, and transistors F1 and F2 of cells IM[1,j] to IM[m,j] located in column j other than row i are OFF. Therefore, the I flow from circuit WCSa[j] through wiring WCL[j] WR The current and the I set in cell IM[i,j] RD Because the sum of the currents and flows, as a result, I WR and I RD The difference current (I WR -I RD The signal is input to the conversion circuit ITRZ[j] of circuit ITS via switch S4[j].

[0287] Wiring WCL[j] to switch S4[j] and then to conversion circuit ITRZ[j] WR -I RD When the difference current is input, the conversion circuit ITRZ[j] receives the current I WR -I RD It outputs a potential corresponding to the current. Furthermore, this potential is the difference between the write current and the read current, W. WR -W RD (Assuming this is ΔW2), it is transmitted to the control circuit CTR.

[0288] Specifically, the conversion circuit ITRZ[j] converts the current I through the current-voltage conversion circuit (operational amplifier OP1 and load LE). WR -I RD The voltage is converted to an analog potential. The conversion circuit ITRZ[j] then transmits the analog potential to the control circuit CTR via the wiring OL[j] as a signal including the difference value ΔW2.

[0289] Alternatively, the conversion circuit ITRZ[j] may convert the analog potential into a digital signal using an analog-to-digital conversion circuit, and transmit the digital signal, which includes the difference value ΔW2, to the control circuit CTR via wiring OL[j].

[0290] [Step S104A] Step S104A, as an example, involves the control circuit CTR acquiring the difference value ΔW2 and determining whether or not correction is necessary for the potential corresponding to the first data written to cell IM[i,j].

[0291] Specifically, step S104A is when the control circuit CTR determines that the difference value ΔW2 is 0 (W WR and W RD If (and are equal), the write operation including the correction process is terminated, and if the control circuit CTR determines that the difference value ΔW2 is not 0 (W WR and W RD If (and ) are not equal, the operation proceeds to step S106.

[0292] W WR and W RD If they are equal, the amount of writing current I WR And the amount of read current I RD This corresponds to the case where and are equal. In other words, W TRG and W RD If these conditions are equal, it can be determined that the first data has been written to cell IM[i,j] correctly.

[0293] [Step S105A] Step S105A, as an example, involves the control circuit CTR generating corrected first data to be written again to cell IM[i,j].

[0294] Specifically, in step S105, the control circuit CTR obtains ΔW2 from the circuit ITRZ[j] included in the circuit ITS, and as corrected first data, W WR It has the operation of generating +ΔW2 (hereinafter referred to as the updated value).

[0295] [Step S106] Step S106, as an example, is similar to step S106 in the flowchart of Figure 7, where the control circuit CTR updates the circuit WCSa[j] included in the circuit WCS as the update value W WRThe process involves inputting a signal equivalent to +ΔW2 and then proceeding to step S102.

[0296] In other words, in the circuit WCSa[j] in Figure 3, the value of the digital signal input to each of the wires DW[1] through DW[K] is the same as the value of the W input to the circuit WCSa[j] last time. WR The value is obtained by adding ΔW2 to the original value.

[0297] Therefore, after transitioning from step S106 to step S102, W described in steps S102 to S106 above WR is, W WR This can be explained by substituting it with +ΔW2.

[0298] Subsequently, in step S104A, W TRG and W RD By repeatedly performing steps S102, S103A, S104A, and S106 until the values ​​become equal (the difference between the write current and the read current becomes 0), the appropriate potential corresponding to the first data can be written to cell IM[i,j].

[0299] As described above, by performing steps S101, S102, S103A, S104A, S105, and S106 in the arithmetic circuit MACA2, variations in the writing of the first data to cell IM[i,j] can be suppressed.

[0300] In the above-described first data writing operations 1 to 3, which include correction processing, examples were shown in which the first data was written to cell IM[i,j]. However, these writing operations may be performed row by row in the cell array CA, rather than one cell IM at a time. In other words, the first data writing operation including correction processing may be performed sequentially on each cell IM in each row of the cell array CA, for example, by performing the first data writing operation including correction processing on each cell IM[1,1] to IM[1,n] located in the first row of the cell array CA all at once, and then, after the writing operations for all cells IM[1,1] to IM[1,n] are completed, performing the first data writing operation including correction processing on each cell IM[2,1] to IM[2,n] located in the second row all at once.

[0301] <Example of operation of the arithmetic circuit 1> Next, we will describe an example of the operation of the arithmetic circuit MACA1 shown in Figure 2, which is an example of the arithmetic circuit MACA0.

[0302] Figure 9 shows a timing chart of an example of the operation of the MACA0 arithmetic circuit in Figure 1. The timing chart in Figure 9 shows the potential fluctuations of wires SWL1, SWL2, WSL[i] (where i is an integer between 1 and m-1), WSL[i+1], XCL[i], XCL[i+1], node N[i,j] (where j is an integer between 1 and n-1), node N[i+1,j], node Nd[i], and node Nd[i+1] between time T11 and time T23, and in the vicinity of these times. Furthermore, the timing chart in Figure 9 also shows the current I flowing between the first and second terminals of transistor F2 contained in cell IM[i,j]. F2 [i,j] and the current I flowing between the first and second terminals of transistor F2d contained in cell IMd[i]. F2d The variations of [i] and each of them are also shown.

[0303] Furthermore, the circuit WCS[j] shown in Figure 3A shall be applied as the circuit WCS of the arithmetic circuit MACA0, and the circuit XCS[i] shown in Figure 3C shall be applied as the circuit XCS of the arithmetic circuit MACA0.

[0304] In this example, the potential of wiring VE1 is set to ground potential GND. Also, before time T11, the initial settings assume that the potentials of nodes N[i,j], N[i+1,j], Nd[i], and Nd[i+1] are set to ground potential GND. Specifically, for example, by setting the initialization potential of wiring VINIL1 in Figure 3A to ground potential GND, and turning on switches SWW, S3[j], and transistors F1 contained in cells IM[i,j] and IM[i+1,j], the potentials of nodes N[i,j] and N[i+1,j] can be set to ground potential GND. Similarly, for example, by setting the initialization potential of wiring VINIL2 in Figure 3C to ground potential GND, and turning on switches SWX and transistors F1d contained in cells IMd[i] and IMd[i+1], the potentials of nodes Nd[i] and Nd[i+1] can be set to ground potential GND.

[0305] [From time T11 to time T12] Between time T11 and time T12, a high-level potential (labeled "High" in Figure 9) is applied to wiring SWL1, and a low-level potential (labeled "Low" in Figure 9) is applied to wiring SWL2. As a result, a high-level potential is applied to the control terminals of switches S3[1] through S3[n], causing each of switches S3[1] through S3[n] to turn on, and a low-level potential is applied to the gates of switches S4[1] through S4[n], causing each of switches S4[1] through S4[n] to turn off.

[0306] Furthermore, between time T11 and time T12, a low-level potential is applied to wiring WSL[i] and wiring WSL[i+1]. As a result, a low-level potential is applied to the gates of transistors F1 contained in cells IM[i,1] through IM[i,n] in the i-th row of cell array CA, and to the gate of transistor F1d contained in cell IMd[i], causing transistors F1 and F1d to turn off. Additionally, a low-level potential is applied to the gates of transistors F1 contained in cells IM[i+1,1] through IM[i+1,n] in the i+1-th row of cell array CA, and to the gate of transistor F1d contained in cell IMd[i+1], causing transistors F1 and F1d to turn off.

[0307] Furthermore, between time T11 and time T12, the ground potential GND is applied to wiring XCL[i] and wiring XCL[i+1]. Specifically, for example, if the wiring XCL shown in Figure 3C is wiring XCL[i] and wiring XCL[i+1] respectively, the potential of wiring XCL[i] and wiring XCL[i+1] can be set to the ground potential GND by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX.

[0308] Furthermore, between time T11 and time T12, in each of the circuits WCSa[j] in Figure 3A, which are electrically connected to wiring WCL[1] to wiring WCL[n] via separate switches S3, no first data is input to wiring DW[1] to wiring DW[K]. In this case, it is assumed that a low-level potential is input to each of the wirings DW[1] to wiring DW[K] in the circuit WCSa[j] in Figure 3A. Also, between time T11 and time T12, in each of the circuits XCSa in Figure 4C, which are electrically connected to wiring XCL[1] to wiring XCL[m], no second data is input to wiring DX[1] to wiring DX[L]. In this case, it is assumed that a low-level potential is input to each of the wirings DX[1] to wiring DX[L] in the circuit XCSa[i] in Figure 4C.

[0309] Furthermore, between time T11 and time T12, no current flows through wiring WCL[j], wiring XCL[i], and wiring XCL[i+1]. Therefore, I F2 [i,j], I F2d [i]I F2 [i+1,j], I F2d [i+1] is 0.

[0310] [From time T12 to time T13] Between time T12 and time T13, a high-level potential is applied to wiring WSL[i]. This applies a high-level potential to the gates of transistors F1 in cells IM[i,1] through IM[i,n] of row i of cell array CA, and to the gates of transistors F1d in cell IMd[i], causing transistors F1 and F1d to turn ON. Also, between time T12 and time T13, a low-level potential is applied to wirings WSL[1] through WSL[m] other than wiring WSL[i], and transistors F1 in cells IM[1,1] through IM[m,n] other than row i of cell array CA, and transistors F1d in cells IMd[1] through IMd[m] other than row i are assumed to be in the OFF state.

[0311] Furthermore, the ground potential GND has been continuously applied to wiring XCL[1] through wiring XCL[m] since before time T12.

[0312] [From time T13 to time T14] Between time T13 and time T14, a current of amount I0[i,j] flows from circuit WCSa[j] to wiring WCL[j] via switch S3[j] as the first data. Specifically, when wiring WCL shown in Figure 3A is wiring WCL[j], a signal corresponding to the first data is input to each of wirings DW[1] to DW[K], causing a current of I0[i,j] to flow from circuit WCSa[j] to the second terminal of switch S3[j]. In other words, the value of the K-bit signal input as the first data is α[i,j] (α[i,j] is between 0 and 2). K When I0[i,j] = α[i,j] × I (i,j) is an integer less than or equal to -1, then I0[i,j] = α[i,j] × I Wut This is the result.

[0313] Note that when α[i,j] is 0, I0[i,j]=0, so strictly speaking, no current flows from circuit WCSa[j] to cell array CA via switch S3[j]. However, in this specification and other documents, it may be stated that "a current of I0[i,j]=0 flows."

[0314] Between time T13 and time T14, the first terminal of transistor F1 in cell IM[i,j] of row i of cell array CA and the wiring WCL[j] are conductive, and the first terminals of transistor F1 in cells IM[1,j] through IM[m,j] other than row i of cell array CA and the wiring WCL[j] are not conductive. Therefore, a current of I0[i,j] flows from the wiring WCL[j] to cell IM[i,j].

[0315] By the way, when transistor F1 in cell IM[i,j] is turned ON, transistor F2 in cell IM[i,j] becomes a diode connection. Therefore, when current flows from wiring WCL[j] to cell IM[i,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i,j] and the potential of the first terminal of transistor F2 (here, GND), etc. In this example of operation, when a current of amount I0[i,j] flows from wiring WCL[j] to cell IM[i,j], the potential of the gate of transistor F2 (node ​​N[i,j]) becomes V g Let [i,j] be the case. That is, in transistor F2, the gate-source voltage is V g [i,j]-GND is established, and the current I0[i,j] is set as the current flowing between the first and second terminals of transistor F2.

[0316] Here, the threshold voltage of transistor F2 is V th When [i,j] is denoted as such, the current I0[i,j] when transistor F2 operates in the subthreshold region can be described by the following equation.

[0317]

number

[0318] Note I a is V g [i,j] is V th The drain current when [i,j], where J is a correction factor determined by temperature, device structure, etc.

[0319] Furthermore, between time T13 and time T14, current I is transmitted from circuit XCS to wiring XCL[i] as reference data. ref0A current flows. Specifically, a high-level potential is input to wiring DX[1] and a low-level potential is input to each of wirings DX[2] through DX[K], causing a current I to flow from circuit XCSa[i] to wiring XCL[i]. ref0 It flows. In other words, I ref0 =I Xut This is the result.

[0320] Between time T13 and time T14, the first terminal of transistor F1d in cell IMd[i] and the wiring XCL[i] are in a conductive state, so a current I is supplied from wiring XCL[i] to cell IMd[i]. ref0 An electric current flows.

[0321] Similar to cell IM[i,j], when transistor F1d in cell IMd[i] is turned on, transistor F2d in cell IMd[i] becomes a diode-connected device. Therefore, when current flows from wiring XCL[i] to cell IMd[i], the potentials of the gate of transistor F2d and the second terminal of transistor F2d become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i] to cell IMd[i] and the potential of the first terminal of transistor F2d (GND in this case). In this example of operation, the amount of current I flows from wiring XCL[i] to cell IMd[i]. ref0 As the current flows, the potential at the gate (node ​​Nd[i]) of transistor F2 is V gm [i] is assumed to be the case, and the potential of the wiring XCL[i] at this time is also V gm Let [i]. That is, in transistor F2d, the gate-source voltage is V gm [i]-GND, and the current I is the current flowing between the first and second terminals of transistor F2d. ref0 This will be set.

[0322] Here, the threshold voltage of transistor F2d is V thm [i] When transistor F2d operates in the subthreshold region, the current I ref0 This can be written as follows:

[0323]

number

[0324] The correction coefficient J is assumed to be the same as that of transistor F2 included in cell IM[i,j]. For example, the device structure and size (channel length, channel width) of the transistors are assumed to be the same. Although the correction coefficient J of each transistor will vary due to manufacturing variations, it is assumed that the variations are suppressed to a degree that allows the discussion described later to hold true with sufficient accuracy for practical purposes.

[0325] Here, the first data point, the weight coefficient w[i,j], is defined as follows.

[0326]

number

[0327] Therefore, equations (1.2), (1.3), and I0[i,j]=α[i,j]×I Wut , and I ref0 =I Xut Using this, equation (1.1) can be rewritten as follows:

[0328]

number

[0329] Furthermore, the current I output by the current source CS of the circuit WCSa[j] Wut And the current I output by the current source CS of the circuit XCSa[i] Xut If and are equal, then w[i,j]=α[i,j]. That is, I Wut And, I Xut If and are equal, then α[i,j] corresponds to the value of the first data, so I Wut And, I Xut It is preferable that and are equal to each other.

[0330] [From time T14 to time T15] Between time T14 and time T15, a low-level potential is applied to wiring WSL[i]. This applies a low-level potential to the gates of transistors F1 in cells IM[i,1] through IM[i,n] of row i of cell array CA, and to the gate of transistor F1d in cell IMd[i], causing transistors F1 and F1d to turn off.

[0331] When transistor F1 in cell IM[i,j] turns off, capacitance C5 receives the difference between the potential of the gate of transistor F2 (node ​​N[i,j]) and the potential of wiring XCL[i], which is V. g [i,j]-V gm [i] is maintained. Also, when transistor F1 contained in cell IMd[i] turns off, capacitance C5d maintains 0, which is the difference between the potential of the gate (node ​​Nd[i]) of transistor F2d and the potential of wiring XCL[i]. Note that the voltage held by capacitance C5d is a non-zero voltage (here, for example, V) depending on the transistor characteristics of one or both of transistors F1d and F2d during the operation from time T13 to time T14. ds In some cases, this may be the case. In this case, the potential of node Nd[i] is V ds It can be considered as the potential with added voltage.

[0332] By performing operations between time T12 and time T15, the potential corresponding to the first data can be written to cell IM[i,j]. During this time, the first data writing operation, including the correction process described above, may also be performed to correct the potential corresponding to the first data held in cell IM[i,j].

[0333] [From time T15 to time T16] Between time T15 and time T16, GND is applied to wiring XCL[i]. Specifically, by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX, the potential of wiring XCL[i] can be set to the ground potential GND.

[0334] Therefore, the potential of nodes N[i,1] through N[i,n] changes due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i,1] through IM[i,n] in row i, and the potential of node Nd[i] changes due to capacitive coupling by the capacitance C5d contained in cell IMd[i].

[0335] The change in potential at nodes N[i,1] through N[i,n] is the potential obtained by multiplying the change in potential at wiring XCL[i] by the capacitive coupling coefficient determined by the configuration of each cell IM[i,1] through IM[i,n] contained in cell array CA. This capacitive coupling coefficient is calculated, for example, by the capacitance of capacitor C5, the gate capacitance of transistor F2, and the parasitic capacitance. When the capacitive coupling coefficient due to capacitor C5 is P for each of cells IM[i,1] through IM[i,n], the potential at node N[i,j] of cell IM[i,j] is calculated by P(V) from the potential at the time between time T14 and time T15. gm [i]-GND) decreases

[0336] Similarly, a change in the potential of wiring XCL[i] causes a change in the potential of node Nd[i] due to capacitive coupling by capacitance C5d contained in cell IMd[i]. When the capacitive coupling coefficient by capacitance C5d is denoted as P, the same as for capacitance C5, the potential of node Nd[i] of cell IMd[i] is calculated from the potential between time T14 and time T15 as P(V). gm [i]-GND) decreases

[0337] Note that in the timing chart of Figure 9, P=1 is used as an example. Therefore, the potential of node Nd[i] between time T15 and time T16 is GND.

[0338] As a result, the potential of node N[i,j] in cell IM[i,j] decreases, causing transistor F2 to turn off, and similarly, the potential of node Nd[i] in cell IMd[i] decreases, causing transistor F2d to turn off as well. Therefore, between time T15 and time T16, I F2 [i,j], I F2d Each of [i] is 0.

[0339] [From time T16 to time T17] Between time T16 and time T17, a high-level potential is applied to wiring WSL[i+1]. This applies a high-level potential to the gates of transistors F1 in cells IM[i+1,1] through IM[i+1,n] in the i+1th row of cell array CA, and to the gates of transistors F1d in cell IMd[i+1], causing transistors F1 and F1d to turn ON. Also, between time T16 and time T17, a low-level potential is applied to wirings WSL[1] through WSL[m] other than wiring WSL[i+1], and transistors F1 in cells IM[1,1] through IM[m,n] other than the i+1th row of cell array CA, and transistors F1d in cells IMd[1] through IMd[m] other than the i+1th row, are assumed to be in the OFF state.

[0340] Furthermore, the ground potential GND has been continuously applied to wiring XCL[1] through wiring XCL[m] since before time T16.

[0341] [From time T17 to time T18] Between time T17 and time T18, a current of amount I0[i+1,j] flows from circuit WCS to cell array CA via switch S3[j] as the first data. Specifically, in circuit WCSa[j] shown in Figure 3A, a signal corresponding to the first data is input to each of the wires DW[1] to DW[K], causing a current of amount I0[i+1,j] to flow from circuit WCSa[j] to the second terminal of switch S3[j]. In other words, the value of the K-bit signal input as the first data is α[i+1,j] (α[i+1,j] is between 0 and 2). K Let I0[i+1,j] = α[i+1,j] × I Wut This is the result.

[0342] Note that when α[i+1,j] is 0, I0[i+1,j]=0, so strictly speaking, no current flows from circuit WCSa to cell array CA via switch S3[j]. However, in this specification and other documents, it is sometimes written as "a current of I0[i+1,j]=0 flows," similar to the case where I0[i,j]=0.

[0343] At this time, there is a conductive state between the first terminal of transistor F1 in cell IM[i+1,j] in the i+1 row of cell array CA and the wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 in cells IM[1,j] through IM[m,j] other than the i+1 row of cell array CA and the wiring WCL[j]. Therefore, a current of I0[i+1,j] flows from the wiring WCL[j] to cell IM[i+1,j].

[0344] By the way, when transistor F1 in cell IM[i+1,j] is turned on, transistor F2 in cell IM[i+1,j] becomes a diode connection. Therefore, when current flows from wiring WCL[j] to cell IM[i+1,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i+1,j] and the potential of the first terminal of transistor F2 (here, GND), etc. In this example of operation, when a current of amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j], the potential of the gate of transistor F2 (node ​​N[i+1,j]) becomes V g Assume that the range is [i+1, j]. In other words, in transistor F2, the gate-source voltage is V g [i+1,j]-GND is set, and the current I0[i+1,j] is defined as the current flowing between the first and second terminals of transistor F2.

[0345] Here, the threshold voltage of transistor F2 is V th When [i+1,j] is defined as such, the current I0[i+1,j] when transistor F2 operates in the subthreshold region can be described by the following equation.

[0346]

number

[0347] The correction factor is set to J, the same value as transistor F2 contained in cell IM[i,j] and transistor F2d contained in cell IMd[i].

[0348] Furthermore, between time T17 and time T18, the current quantity I is transmitted as reference data from circuit XCS[i+1] to wiring XCL[i+1]. ref0A current flows. Specifically, as between time T13 and time T14, when circuit XCS[i] shown in Figure 3C is circuit XCS[i+1], a high-level potential is input to wiring DX[1] and a low-level potential is input to each of wirings DX[2] through DX[K], causing a current I to flow from circuit XCSa[i+1] to wiring XCL[i+1]. ref0 =I Xut It plays.

[0349] Between time T17 and time T18, the first terminal of transistor F1d contained in cell IMd[i+1] and the wiring XCL[i+1] become conductive, and a current I is drawn from the wiring XCL[i+1] to cell IMd[i+1]. ref0 An electric current flows.

[0350] Similar to cell IM[i+1,j], when transistor F1d in cell IMd[i+1] is turned ON, transistor F2d in cell IMd[i+1,j] becomes a diode-connected configuration. Therefore, when current flows from wiring XCL[i+1] to cell IMd[i+1], the potentials of the gate of transistor F2d and the second terminal of transistor F2d become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i+1] to cell IMd[i+1] and the potential of the first terminal of transistor F2d (GND in this case). In this example of operation, the amount of current I flows from wiring XCL[i+1] to cell IMd[i+1] ref0 As the current flows, the gate (node ​​Nd[i+1]) of transistor F2d becomes V gm It is assumed that the potential becomes [i+1], and the potential of the wiring XCL[i+1] at this time is also V gm Let [i+1]. That is, in transistor F2d, the gate-source voltage is V gm [i+1]-GND, and the current I is the current flowing between the first and second terminals of transistor F2d. ref0 This will be set.

[0351] Here, the threshold voltage of transistor F2d is V thmWhen [i+1,j], the current I when transistor F2d operates in the subthreshold region is [i+1,j]. ref0 This can be written as follows:

[0352]

number

[0353] The correction coefficient J is assumed to be the same as that of transistor F2 included in cell IM[i+1,j].

[0354] Here, we define the first data point, the weight coefficient w[i+1,j], as follows.

[0355]

number

[0356] Therefore, equations (1.6), (1.7), and I0[i+1,j]=α[i+1,j]×I Wut , and I ref0 =I Xut Using this, equation (1.5) can be rewritten as follows:

[0357]

number

[0358] Note that the current I output by the current source CS of circuit WCSa[j] Wut And the current I output by the current source CS of circuit XCSa[i+1] Xut If and are equal, then w[i+1,j]=α[i+1,j]. That is, I Wut And, I Xut If and are equal, then α[i+1,j] corresponds to the value of the first data, so I Wut And, I Xut It is preferable that and are equal to each other.

[0359] [From time T18 to time T19] Between time T18 and time T19, a low-level potential is applied to wiring WSL[i+1]. This applies a low-level potential to the gates of transistors F1 in cells IM[i+1,1] through IM[i+1,n] in the i+1 row of cell array CA, and to the gate of transistor F1d in cell IMd[i+1], causing transistors F1 and F1d to turn off.

[0360] When transistor F1 in cell IM[i+1,j] turns off, capacitance C5 receives the difference between the potential of the gate of transistor F2 (node ​​N[i+1,j]) and the potential of wiring XCL[i+1], which is V. g [i+1,j]-V gm [i+1] is maintained. Also, when transistor F1 contained in cell IMd[i+1] turns off, capacitance C5d maintains 0, which is the difference between the potential of the gate of transistor F2d (node ​​Nd[i+1]) and the potential of wiring XCL[i+1]. Note that the voltage held by capacitance C5d is a non-zero voltage (here, for example, V) depending on the transistor characteristics of one or both transistors F1d and F2d during operation from time T18 to time T19. ds In some cases, this may be the case. In this case, the potential of node Nd[i+1] is V ds It can be considered as the potential with added voltage.

[0361] [From time T19 to time T20] Between time T19 and time T20, the ground potential GND is applied to wiring XCL[i+1]. Specifically, for example, if circuit XCSs[i] shown in Figure 3A is circuit XCSs[i+1], the potential of wiring XCL[i+1] can be set to the ground potential GND by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX.

[0362] Therefore, the potential of nodes N[i,1] through N[i+1,n] changes due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i+1,1] through IM[i+1,n] in the i+1 row, and the potential of node Nd[i+1] changes due to capacitive coupling by the capacitance C5d contained in cell IMd[i+1].

[0363] The change in potential at nodes N[i+1,1] through N[i+1,n] is the potential obtained by multiplying the change in potential at wiring XCL[i+1] by the capacitive coupling coefficient determined by the configuration of each cell IM[i+1,1] through IM[i+1,n] contained in cell array CA. This capacitive coupling coefficient is calculated using the capacitance of capacitor C5, the gate capacitance of transistor F2, parasitic capacitance, etc. When the capacitive coupling coefficient due to capacitor C5 in each of cells IM[i+1,1] through IM[i+1,n] is set to P, the same as the capacitive coupling coefficient due to capacitor C5 in each of cells IM[i,1] through IM[i,n], the potential at node N[i+1,j] of cell IM[i+1,j] is calculated by taking the potential at the time between time T18 and time T19 and calculating P(V gm [i+1]-GND) decreases.

[0364] Similarly, a change in the potential of wiring XCL[i+1] causes a change in the potential of node Nd[i+1] due to capacitive coupling by capacitance C5d contained in cell IMd[i+1]. When the capacitive coupling coefficient of capacitance C5d is denoted as P, the same as for capacitance C5, the potential of node Nd[i+1] of cell IMd[i+1] is calculated as P(V) from the potential at the time between time T18 and time T19. gm [i+1]-GND) decreases.

[0365] Note that in the timing chart in Figure 9, P=1 is used as an example. Therefore, the potential of node Nd[i+1] between time T20 and time T21 is GND.

[0366] As a result, the potential at node N[i+1,j] of cell IM[i+1,j] decreases, causing transistor F2 to turn off. Similarly, the potential at node Nd[i+1] of cell IMd[i+1] decreases, causing transistor F2d to turn off. Therefore, between time T19 and time T20, I F2 [i+1,j], I F2d Each of [i+1] is 0.

[0367] By performing operations between time T16 and time T20, the potential corresponding to the first data can be written to cell IM[i+1,j]. During this time, the first data writing operation, including the correction process described above, may also be performed to correct the potential corresponding to the first data held in cell IM[i+1,j].

[0368] [From time T20 to time T21] Between time T20 and time T21, a low-level potential is applied to wiring SWL1. As a result, a low-level potential is applied to the control terminals of switches S3[1] through S3[n], causing each of switches S3[1] through S3[n] to turn off.

[0369] [From time T21 to time T22] Between time T21 and time T22, a high-level potential is applied to the wiring SWL2. As a result, a high-level potential is applied to the control terminals of switches S4[1] through S4[n], causing each of switches S4[1] through S4[n] to turn on.

[0370] [From time T22 to time T23] Between time T22 and time T23, the current quantity I is transferred from circuit XCS to wiring XCL[i] as the second data. ref0 x[i]I is x[i] times the original. ref0A current of x[i]I flows. Specifically, for example, in the circuit XCSa[i] shown in Figure 3C, a high-level potential or a low-level potential is input to each of the wires DX[1] to DX[K] according to the value of x[i], and the current x[i]I flows from circuit XCSa to wire XCL[i]. ref0 =x[i]I Xut The current flows. In this example, x[i] corresponds to the value of the second data. At this time, the potential of wiring XCL[i] is from 0 to V gm Let it change to [i] + ΔV[i].

[0371] A change in the potential of wiring XCL[i] causes a change in the potential of nodes N[i,1] through N[i,n] due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i,1] through IM[i,n] in row i of cell array CA. Therefore, the potential of node N[i,j] of cell IM[i,j] is V g [i,j]+PΔV[i]

[0372] Similarly, a change in the potential of wiring XCL[i] causes a change in the potential of node Nd[i] due to capacitive coupling by capacitance C5d contained in cell IMd[i]. Therefore, the potential of node Nd[i] of cell IMd[i] is V gm [i] + PΔV[i]

[0373] As a result, the current I1[i,j] flowing between the first and second terminals of transistor F2 and the current I ref1 [i,j] can be written as follows:

[0374]

number

[0375]

number

[0376] Note that x[i] is defined as follows:

[0377]

number

[0378] Therefore, equation (1.9) can be rewritten using equations (1.4) and (1.11) as follows:

[0379]

number

[0380] In other words, the amount of current flowing between the first and second terminals of transistor F2 contained in cell IM[i,j] is proportional to the product of the first data w[i,j] and the second data x[i].

[0381] Furthermore, between time T22 and time T23, the current quantity I is transferred from circuit XCS to wiring XCL[i+1] as the second data. ref0 x[i+1]I is x[i+1] times the original. ref0 A current of x[i+1]I flows. Specifically, for example, when circuit XCSa[i] shown in Figure 3C is circuit XCSa[i+1], a high-level potential or a low-level potential is input to each of the wires DX[1] to DX[K] according to the value of x[i+1], and a current of x[i+1]I flows from circuit XCSa[i+1] to wire XCL[i+1]. ref0 =x[i+1]I Xut The current flows. In this example, x[i+1] corresponds to the value of the second data. At this time, the potential of wiring XCL[i+1] is from 0 to V gm Let it change to [i+1] + ΔV[i+1].

[0382] A change in the potential of wiring XCL[i+1] causes a change in the potential of nodes N[i+1,1] through N[i+1,n] due to capacitive coupling by the capacitance C5 contained in each of the cells IM[i+1,1] through IM[i+1,n] in the i+1 row of cell array CA. Therefore, the potential of node N[i+1,j] of cell IM[i+1,j] is V g The result is [i+1,j]+PΔV[i+1].

[0383] Similarly, a change in the potential of wiring XCL[i+1] causes a change in the potential of node Nd[i+1] due to capacitive coupling by capacitance C5d contained in cell IMd[i+1]. Therefore, the potential of node Nd[i+1] of cell IMd[i+1] is V gm The result is [i+1] + PΔV[i+1].

[0384] As a result, the current flowing between the first and second terminals of transistor F2, I1[i+1,j], and the current flowing between the first and second terminals of transistor F2d, I, are determined between time T22 and time T23. ref1 [i+1,j] can be written as follows:

[0385]

number

[0386]

number

[0387] Note that x[i+1] is defined as follows:

[0388]

number

[0389] Therefore, equation (1.13) can be rewritten using equations (1.8) and (1.15) as follows:

[0390]

number

[0391] In other words, the amount of current flowing between the first and second terminals of transistor F2 contained in cell IM[i+1,j] is proportional to the product of the first data, w[i+1,j], and the second data, x[i+1].

[0392] Here, we consider the sum of the currents flowing from the conversion circuit ITRZ[j] through the switch S4[j] and the wiring WCL[j] to cells IM[i,j] and IM[i+1,j]. The sum of these currents is I S If we set it to [j], then I S [j] can be expressed by the following equation, derived from equations (1.12) and (1.16).

[0393]

number

[0394] Therefore, the amount of current output from the conversion circuit ITRZ[j] is proportional to the sum of the products of the first data, which are the weight coefficients w[i,j] and w[i+1,j], and the second data, which are the neuron signal values ​​x[i] and x[i+1].

[0395] In the above example, we dealt with the sum of the currents flowing through cell IM[i,j] and cell IM[i+1,j], but we may also deal with the sum of the currents flowing through each of the cells IM[1,j] through IM[m,j]. In this case, equation (1.17) can be rewritten as the following equation.

[0396]

number

[0397] Therefore, even in the case of an arithmetic circuit MACA1 having a cell array CA with three or more rows and multiple columns, the sum-of-accumulate operation can be performed as described above. In this case, the arithmetic circuit MACA1 uses one of the multiple columns as the current quantity I ref0 , and xI ref0 By using cells that hold this information, it becomes possible to simultaneously perform multiply-accumulate operations for the number of remaining columns among multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that achieves high-speed multiply-accumulate operations.

[0398] In this embodiment, each of the arithmetic circuits MACA0, MACA1, and MACA2 is configured to hold first data in cell IM in order to perform a multiply-accumulate operation. For this reason, each of the arithmetic circuits MACA0, MACA1, and MACA2 may be treated as a memory device. Furthermore, when reading the first data from cell IM[i,j] in arithmetic circuits MACA0, MACA1, or MACA2, the first data held in cell IM[i,j] can be read by, for example, flowing a current corresponding to "1" as the value of the second data from circuit XCS to wiring XCL[i], and flowing a current corresponding to "0" as the value of the second data from circuit XCS to wiring XCL[1] to wiring XCL[m] other than row i.

[0399] As described above, the arithmetic circuits MACA0, MACA1, and MACA2 described in this embodiment may be referred to as memory devices in other embodiments.

[0400] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0401] (Embodiment 2) Embodiment 1 described an arithmetic circuit that performs a sum-of-products operation on a first data set that is positive or "0" and a second data set that is positive or "0". This embodiment describes an arithmetic circuit that performs a sum-of-products operation on a first data set that is positive, negative, or "0" and a second data set that is positive or "0".

[0402] <Example of arithmetic circuit configuration 1> Figure 12 shows an example of a configuration for an arithmetic circuit that performs a sum-of-products operation on a first data point (positive, negative, or "0") and a second data point (positive, or "0"). The arithmetic circuit MACB0 shown in Figure 12 is a circuit that performs a sum-of-products operation on the first data point corresponding to the potential held in each cell and on multiple input second data points, and then performs a function operation using the result of the sum-of-products operation. This function can be, for example, an activation function when performing calculations in a neural network. The first and second data points can be, for example, analog data (e.g., continuous analog potential) or multi-level data (discrete analog potential or digital signal).

[0403] The MACB0 arithmetic circuit includes the CTR control circuit, the WCS circuit, the XCS circuit, the WSD circuit, the ITS circuit, the FB circuit, and the CA cell array.

[0404] The cell array CA has cells IM[1,1] to IM[m,n] (where m is an integer greater than or equal to 1 and n is an integer greater than or equal to 1), cells IMr[1,1] to IMr[m,n], and cells IMd[1] to IMd[m]. In Figure 12, cells IM[1,1] to IM[m,n], IMr[1,1] to IMr[m,n], and cells IMd[1] to IMd[m] are shown as an excerpt, specifically cells IM[1,1], IM[m,1], IM[1,n], IM[m,n], IMr[1,1], IMr[m,1], IMr[1,n], IMr[m,n], IMd[1], and IMd[m].

[0405] Furthermore, in Figure 12, cells IM and IMr located at the same address are collectively shown as circuit CES. In addition, in the arithmetic circuit MACB0, circuit CES has the function of holding the first data, with cells IM and IMr located at the same address as a pair. Specifically, each of cells IM[1,1] to IM[m,n] and cells IMr[1,1] to IMr[m,n] has the function of holding a potential corresponding to the amount of current corresponding to the first data, for example.

[0406] Note that while the cell array CA in Figure 12 has cells arranged in a matrix of m rows and 2 × n+1 columns, any cell array CA can have a configuration in which cells are arranged in a matrix of one or more rows and three or more columns.

[0407] <<Example configuration of Cell IM, Cell IMR, and Cell IMD>> The arithmetic circuit MACB1 shown in Figure 13 is an example configuration of the arithmetic circuit MACB0 shown in Figure 12, and Figure 13 shows example circuit configurations for cell IM, cell IMr, and cell IMd.

[0408] As shown in Figure 13, the configurations of cells IM[1,1] to IM[m,n] and cells IMd[1] to IMd[m] are the same as those of cells IM[1,1] to IM[m,n] and cells IMd[1] to IMd[m] in the arithmetic circuit MACA1 shown in Figure 2. Therefore, for each of cells IM[1,1] to IM[m,n] and cells IMd[1] to IMd[m] in the arithmetic circuit MACB0 in Figure 13, refer to the explanation of cells IM[1,1] to IM[m,n] and cells IMd[1] to IMd[m] described in Embodiment 1.

[0409] Furthermore, cell IMr[i,j] (where i is an integer between 1 and m, and j is an integer between 1 and n) can have the same configuration as cell IM[i,j]. Cell IMr[i,j] in Figure 13 is illustrated as an example with the same configuration as cell IM[i,j]. In addition, to distinguish between the transistors, capacitances, etc. contained in cell IM[i,j] and cell IMr[i,j], the sign "r" is added to indicate the transistors and capacitances contained in cell IMr[i,j].

[0410] Furthermore, since cell IMr[i,j] can have the same configuration as cell IM[i,j], transistor F1r can be a transistor applicable to transistor F1. Similarly, transistor F2r can be a transistor applicable to transistor F2, and transistor F5r can be a transistor applicable to transistor F5.

[0411] Furthermore, since cell IMr[i,j] can have the same configuration as cell IM[i,j], it is preferable that the size of transistor F1r included in cell IMr[i,j] is equal to the size of transistor F1 included in cell IM[i,j]. Also, it is preferable that the size of transistor F2r included in cell IMr[i,j] is equal to the size of transistor F2 included in cell IM[i,j]. Furthermore, it is preferable that the size of transistor F5r included in cell IMr[i,j] is equal to the size of transistor F5 included in cell IM[i,j].

[0412] Unless otherwise specified, transistor F1r, like transistors F1 and F1d, includes cases where it ultimately operates in the linear region when on. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above include cases where they are appropriately biased to voltages within the range of operation in the linear region. However, one aspect of the present invention is not limited thereto. For example, transistor F1r may operate in the saturation region when on, or it may operate in a mixture of the linear region and the saturation region.

[0413] Furthermore, unless otherwise specified, transistor F2r, like transistors F2 and F2d, includes cases where it operates in the subthreshold region (i.e., in transistor F2r, the gate-source voltage is lower than the threshold voltage, more preferably the drain current increases exponentially with respect to the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above include cases where they are appropriately biased to voltages within the operating range of the subthreshold region. For this reason, transistor F2r also includes cases where it operates such that an off-current flows between the source and drain.

[0414] Furthermore, transistor F5r functions as a clamp transistor, similar to transistors F5 and F5d, for example. Therefore, it is preferable to apply a constant voltage to the gate of transistor F5r. This prevents drain-induced barrier drop (DIBL) in transistor F2r.

[0415] In cell IMr[i,j], the first terminal of transistor F1r is electrically connected to the gate of transistor F2r. The first terminal of transistor F2r is electrically connected to wiring VE0. The first terminal of capacitor C5r is electrically connected to the gate of transistor F2r. The second terminal of transistor F2r is electrically connected to the first terminal of transistor F5r. Furthermore, the second terminal of transistor F5r is electrically connected to the second terminal of transistor F1r, and the gate of transistor F5r is electrically connected to wiring VE1.

[0416] Wiring VE0 functions as a wire for supplying current between the first and second terminals of transistor F2 in cell IM[i,j], between the first and second terminals of transistor F2d in cell IMd[i,j], and between the first and second terminals of transistor F2r in cell IMr[i,j]. For example, wiring VE0 functions as a wire for supplying a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential.

[0417] Wiring VE1 functions as wiring for applying potential to the gates of transistor F5 in cell IM[i,j], transistor F5r in cell IMr[i,j], and transistor F5d in cell IMd[i]. Preferably, the potential is within the range in which transistors F5, F5r, and F5d function as clamp transistors.

[0418] In cell IMr[i,j], the second terminals of transistor F1r and transistor F5r are electrically connected to wiring WCLr[j], and the gate of transistor F1r is electrically connected to wiring WSL[i]. The second terminal of transistor F2r is electrically connected to wiring WCLr[j], and the second terminal of capacitor C5r is electrically connected to wiring XCL[i]. In Figure 13, the connection point between the first terminal of transistor F1r, the gate of transistor F2r, and the first terminal of capacitor C5r in cell IMr[i,j] is defined as node Nr[i,j].

[0419] Note that node Nr[i,j] functions as a cell holding node, similar to nodes N[i,j] and Nd[i].

[0420] <<Circuit WCS>> Circuit WCS includes, for example, circuit SWS1, circuit WCSa[j], and circuit WCSar[j].

[0421] Circuit SWS1, for example, includes switches S3[j] and S3r[j].

[0422] Switch S3[j] has a number equal to the number of matrix columns in which cells IM of the cell array CA are arranged. Similarly, switch S3r[j] has a number equal to the number of matrix columns in which cells IMr of the cell array CA are arranged. In other words, in the case of the arithmetic circuit MACB1 shown in Figure 13, circuit SWS1 has switches S3[1] to S3[n] (total of n) and switches S3r[1] to S3r[n] (total of n).

[0423] The first terminal of switch S3[j] is electrically connected to wiring WCL[j], the second terminal of switch S3[j] is electrically connected to circuit WCSa[j] included in circuit WCS, and the control terminal of switch S3[j] is electrically connected to wiring SWL1. In addition, the first terminal of switch S3r[j] is electrically connected to wiring WCLr[j], the second terminal of switch S3r[j] is electrically connected to circuit WCSar[j] included in circuit WCS, and the control terminal of switch S3r[j] is electrically connected to wiring SWL1.

[0424] For each of switches S3[j] and S3r[j], a switch applicable to switch S3[j] from circuit SWS1 included in circuit WCS described in Embodiment 1 can be used. In particular, it is preferable to use OS transistors for each of switches S3[j] and S3r[j].

[0425] In this specification, it is assumed that the switches S3[j] and S3r[j] shown in Figure 13 are in the ON state when a high-level potential is applied to the control terminal and in the OFF state when a low-level potential is applied to the control terminal.

[0426] Wiring SWL1 functions, for example, as wiring to switch between the ON and OFF states of switches S3[j] and S3r[j], respectively. Therefore, either a high-level potential or a low-level potential is supplied to wiring SWL1.

[0427] Based on the above, circuit SWS1 functions as a circuit that makes the connection between circuit WCSa[j] and wiring WCL[j], and between circuit WCSar[j] and wiring WCLr[j], either conductive or nonconductive.

[0428] Circuit WCSa[j] is described with reference to the description of circuit WCSa[j] included in circuit WCS of the arithmetic circuit MACA1 described in Embodiment 1. Circuit WCSar[j] is described as having a similar configuration to circuit WCSa[j].

[0429] In other words, circuit WCSa[j] has the function of supplying an amount of current to wiring WCL[j] corresponding to the first data, similar to circuit WCSa[j] included in circuit WCS of arithmetic circuit MACA1. Also, circuit WCSar[j] has the function of supplying an amount of current to wiring WCLr[j] corresponding to the first data.

[0430] <<Circuit XCS>> Regarding circuit XCS, please refer to the description of circuit XCS of the arithmetic circuit MACA1 described in Embodiment 1.

[0431] <<Circuit WSD>> For the WSD circuit, please refer to the description of the WSD circuit of the MACA1 arithmetic circuit described in Embodiment 1.

[0432] In the MACB1 arithmetic circuit, the WSD circuit supplies a high-level potential to wiring WSL[1] and a low-level potential to wiring WSL[2] (not shown) through wiring WSL[m], thereby turning on transistors F1, F1r, and F1d, which have gates electrically connected to wiring WSL[1], and turning off transistors F1, F1r, and F1d, which have gates electrically connected to wiring WSL[2] through wiring WSL[m], respectively.

[0433] <<Circuit ITS>> Circuit ITS comprises circuit SWS2 and conversion circuit ITRZD[j].

[0434] Circuit SWS2, for example, includes switches S4[j] and S4r[j].

[0435] Switch S4[j] has a number equal to the number of matrix columns in which cells IM of the cell array CA are arranged. Similarly, switch S4r[j] has a number equal to the number of matrix columns in which cells IMr of the cell array CA are arranged. In other words, in the case of the arithmetic circuit MACB1 shown in Figure 13, the circuit SWS2 has switches S4[1] through S4[n] (total of n) and switches S4r[1] through S4r[n] (total of n).

[0436] The first terminal of switch S4[j] is electrically connected to wiring WCL[j], the second terminal of switch S4[j] is electrically connected to the first input terminal of conversion circuit ITRZD[j] included in circuit ITS, and the control terminal of switch S4[j] is electrically connected to wiring SWL2. Furthermore, the first terminal of switch S4r[j] is electrically connected to wiring WCLr[j], the second terminal of switch S4r[j] is electrically connected to the second terminal of circuit ITRZD[j] included in circuit ITS, and the control terminal of switch S4r[j] is electrically connected to wiring SWL2. Circuit ITRZD[j] will be described later.

[0437] For each of switches S4[j] and S4r[j], a switch applicable to switch S4[j] from circuit SWS2 included in circuit ITS described in Embodiment 1 can be used. In particular, it is preferable to use OS transistors for each of switches S4[j] and S4r[j].

[0438] In this specification, it is assumed that the switches S4[j] and S4r[j] shown in Figure 13 are in the ON state when a high-level potential is applied to the control terminal and in the OFF state when a low-level potential is applied to the control terminal.

[0439] Wiring SWL2 functions, for example, as wiring to switch between the ON and OFF states of switches S4[j] and S4r[j], respectively. Therefore, either a high-level potential or a low-level potential is supplied to wiring SWL2.

[0440] Based on the above, circuit SWS2 has the function of making the connection between wiring WCL[j] and the first terminal of circuit ITRZD[j], and between wiring WCLr[j] and the second terminal of circuit ITRZD[j], either conductive or nonconductive.

[0441] Each of the conversion circuits ITRZD[j] has, for example, a first input terminal, a second input terminal, and an output terminal.

[0442] As mentioned above, the first input terminal of the conversion circuit ITRZD[j] is electrically connected to the second terminal of switch S4[j], and the second input terminal of the conversion circuit ITRZD[j] is electrically connected to the second terminal of switch S4r[j]. In addition, the output terminal of the conversion circuit ITRZD[j] is electrically connected to wiring OL[j].

[0443] The conversion circuit ITRZD[j], for example, has the function of acquiring the difference in current amounts input to the input terminals from wiring WCL[j] and wiring WCLr[j], converting that difference into a voltage, and outputting that voltage from the output terminal. This voltage can be, for example, an analog voltage or a digital voltage. The conversion circuit ITRZD[j] may also have a function-based arithmetic circuit. In this case, for example, the arithmetic circuit may perform a function calculation using the converted voltage and output the result of the calculation to wiring OL[j].

[0444] In particular, when performing calculations on hierarchical neural networks, the functions mentioned above can include, for example, the sigmoid function, tanh function, softmax function, ReLU function, or threshold function.

[0445] Here, the specific circuit configuration of the conversion circuit ITRZD[j] will be described. Figure 14 shows a block diagram of the conversion circuit ITRZD[j] that can be applied to the conversion circuit ITRZD[j] included in the circuit ITS of the arithmetic circuit MACB1 in Figure 13. The conversion circuit ITRZD[j] comprises a comparator CP, a control unit CNR, a digital-to-analog conversion circuit IDCa, and a digital-to-analog conversion circuit IDCb. Wiring ILa is electrically connected to the input terminal CPTa of the comparator CP, and wiring ILb is electrically connected to the input terminal CPTb of the comparator CP. The conversion circuit ITRZD[j] here has the function of performing AD (analog-to-digital) conversion.

[0446] Wiring ILa is electrically connected, for example, to the first input terminal of the conversion circuit ITRZD[j]. In other words, wiring ILa is electrically connected to wiring WCL[j] in the arithmetic circuit MACB1 shown in Figure 13. Similarly, wiring ILb is electrically connected, for example, to the second input terminal of the conversion circuit ITRZD[j]. In other words, wiring ILb is electrically connected to wiring WCLr[j] in the arithmetic circuit MACB1 shown in Figure 13.

[0447] The comparison unit CP compares the value of the current flowing through input terminal CPTa with the value of the current flowing through input terminal CPTb and supplies one of the two potentials to output terminal D. For example, consider the case where a current of amount Ia flows through input terminal CPTa via wiring ILa, and a current of amount Ib flows through input terminal CPTb via wiring ILb. If the current amount Ia exceeds the current amount Ib, the comparison unit CP supplies a high-level potential (hereinafter referred to as potential H) to output terminal D as its output. If the current amount Ia is less than or equal to the current amount Ib, the comparison unit CP supplies a low-level potential (hereinafter referred to as potential L) to output terminal D as its output. The output of the comparison unit CP is input to the control unit CNR via output terminal D.

[0448] The control unit CNR comprises a code generation unit CNR-FS and a digital signal generation unit CNR-SG. The code generation unit CNR-FS has the function of generating a code bit according to the output of the comparison unit CP. For example, if the output of the comparison unit CP is at a high potential, it generates a code bit of "0". If the output of the comparison unit CP is at a low potential, it generates a code bit of "1". The code bit may also be "1" when the output of the comparison unit CP is at a high potential and "0" when it is at a low potential.

[0449] The digital signal generator CNR-SG has the function of generating digital signals with a resolution of, for example, 8 bits or more and 16 bits or less. Lower resolution results in lower AD conversion accuracy, but allows for faster AD conversion speed. Higher resolution results in higher AD conversion accuracy, but slower AD conversion speed. Note that the resolution of the digital signal generator CNR-SG is not limited to 8 bits or more and 16 bits or less. The resolution of the digital value output by the digital signal generator CNR-SG may be 7 bits or less, or 17 bits or more. The resolution should be determined appropriately according to the purpose and application.

[0450] In this embodiment, the digital signal generation unit CNR-SG generates a digital signal with a resolution of 8 bits. Note that in this specification and elsewhere, each digit of a digital signal represented in binary is sometimes referred to as a "bit".

[0451] The control unit CNR has the function of supplying the digital signal generated by the digital signal generation unit CNR-SG to the digital-to-analog conversion circuit IDC (either or both of the digital-to-analog conversion circuit IDCa and the digital-to-analog conversion circuit IDCb). The control unit CNR also has the function of outputting (OUT) a signal to the outside, with a sign bit added to the digital signal. If the resolution of the digital signal is 8 bits, a 9-bit signed digital signal (with an additional sign bit) can be output externally. Furthermore, the control unit CNR functions as a successive approximation register (SAR).

[0452] The digital-to-analog conversion circuit (IDC) functions as a current-output type DAC (Digital to Analog Converter). That is, the digital-to-analog conversion circuit (IDC) has the function of outputting a current of a value corresponding to the digital signal supplied from the control unit (CNR) to the output terminal C (either or both of output terminals Ca and Cb). In addition, the digital-to-analog conversion circuit (IDC) may be configured in the same way as the circuit WCSa[j] shown in Figures 3A and 3B.

[0453] In Figure 14, the output terminal Ca of the digital-to-analog conversion circuit IDCa is electrically connected to the input terminal CPTa of the comparator CP via node NDa. Therefore, the output current of the digital-to-analog conversion circuit IDCa is input to the input terminal CPTa of the comparator CP. That is, the input terminal CPTa receives current I A The current I and the output current of the digital-to-analog conversion circuit IDCa flow. In other words, the amount of current I A The current obtained by adding the output current of the digital-to-analog conversion circuit IDCa to the current from the input terminal CPTa flows through the input terminal CPTa.

[0454] Furthermore, in Figure 14, the output terminal Cb of the digital-to-analog conversion circuit IDCb is electrically connected to the input terminal CPTb of the comparator CP via node NDb. Therefore, the output current of the digital-to-analog conversion circuit IDCb is added to the input terminal CPTb of the comparator CP. In other words, the input terminal CPTb receives a current quantity I B The current and the output current of the digital-to-analog conversion circuit IDCb flow. In other words, the amount of current I B The current obtained by adding the output current of the digital-to-analog conversion circuit IDCb to the input current flows through the input terminal CPTb.

[0455] Node NDA is the node where the output terminal of the digital-to-analog conversion circuit IDCa, the wiring ILa, and the input terminal CPTa are electrically connected. Similarly, node NDb is the node where the output terminal of the digital-to-analog conversion circuit IDCb, the wiring ILb, and the input terminal CPTb are electrically connected.

[0456] <<Example of operation of the conversion circuit ITRZD[j]>> Figure 15 is a flowchart illustrating an example of the operation of the conversion circuit ITRZD[j]. In this embodiment, the resolution of the digital signal generated by the digital signal generation unit CNR-SG is set to 8 bits, and the step size of the output current of the digital-to-analog conversion circuit IDC is set to 1 nA. Here, the current quantity I A and current I B This section explains the process of converting the difference value (also called "difference current") into a signed digital signal.

[0457] [Step S201] The control unit CNR is reset. Specifically, the 8-bit digital signal is set to (00000000)2. This digital signal is then supplied to the digital-to-analog conversion circuit IDCa and the digital-to-analog conversion circuit IDCb. As a result, the outputs of the digital-to-analog conversion circuits IDCa and IDCb are stopped.

[0458] [Step S202] Current amount I A and current IB The current values ​​are compared by the comparison unit CP. In this embodiment, the current quantity I A Current I B If it is greater than, the comparison unit CP supplies potential H to the output terminal D. Also, the current I A Current I B If the following conditions are met, the comparison unit CP supplies potential L to the output terminal D.

[0459] [Step S203a] If the comparison unit CP outputs a potential H in step S202, the sign bit is set to "0".

[0460] [Step S204a] If the sign bit is "0", successive comparison (SA) is performed using the digital-to-analog converter IDCb. During the SA, the digital-to-analog converter IDCa is continuously supplied with the digital signal (00000000)2. Alternatively, power to the digital-to-analog converter IDCa may be stopped. By stopping power to the digital-to-analog converter IDCa, power consumption can be reduced. The operation of SA will be explained later.

[0461] [Step S203b] If the comparison unit CP outputs a potential L in step S202, the sign bit is set to "1".

[0462] [Step S204b] If the sign bit is "1", SA is performed using the digital-to-analog converter circuit IDCa. During SA, the digital-to-analog converter circuit IDCb is continuously supplied with the digital signal (00000000)2. Alternatively, power supply to the digital-to-analog converter circuit IDCb may be stopped. By stopping power supply to the digital-to-analog converter circuit IDCb, power consumption can be reduced.

[0463] [Step S205] After step S204a or step S204b is completed, the obtained digital signal and the sign bit are combined to generate a signed digital signal. The sign bit may be the most significant bit or the least significant bit of the signed digital signal.

[0464] For example, if the sign bit is "1" and the digital signal obtained by SA is (01001011)2, the sign bit may be used as the most significant bit (MSB) to represent the signed digital signal as (101001011)2. Alternatively, the sign bit may be used as the least significant bit (LSB) to represent the signed digital signal as (010010111)2.

[0465] [Step S206] The generated signed digital signal is output externally. When the sign bit "0" is considered positive and the sign bit "1" is considered negative, the conversion circuit ITRZD[j] can output a positive digital signal and a negative digital signal. Alternatively, the conversion circuit ITRZD[j] according to one aspect of the present invention outputs a current quantity I A and current I B The relative magnitudes of the two and the difference in current between them can be output as digital signals.

[0466] <<Example of sequential comparison operation>> The sequential comparison operation corresponding to step S204b will be explained using Figure 16. In Figure 16, the current quantity I in periods TM1 to TM8 A , current amount I B This shows the output terminal D and the state of each digit (bit Q0 to bit Q7) of the digital signal. As mentioned above, the resolution of the digital signal generated by the digital signal generation unit CNR-SG is set to 8 bits, and the step size of the output current of the digital-to-analog conversion circuit IDC is set to 1 nA. Here, the current quantity I A The current is 75nA, and the current is I B Let's explain the case where the current is 150nA. Note that the potential of output terminal D before successive approximation operation (initial state) is potential L. Also, the digital signal in the initial state is (00000000)2.

[0467] [Period TM1] During period TM1, the Q7 bit, which is the MSB of the digital signal, is set to "1". That is, the digital signal (10000000)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, and 128nA is output from the digital-to-analog conversion circuit IDCa. This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 203nA (75 + 128nA) flows through the input terminal CPTa. Since 150nA flows through the input terminal CPTb, the potential of the output terminal D becomes potential H.

[0468] If the potential of output terminal D changes from its initial state during period TM1, the Q7 bit is set to "0" from period TM1 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q7 bit is set to "1" from period TM1 onward until the control unit CNR is reset. In this embodiment, the Q7 bit is "0" from period TM1 onward.

[0469] [Period TM2] During period TM2, bit Q6, which is one bit below the MSB of the digital signal, is set to "1". That is, the digital signal (01000000)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, and 64nA is output from the digital-to-analog conversion circuit IDCa. This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 139nA (75+64nA) flows through the input terminal CPTa, and the potential of the output terminal D is the same potential L as in the initial state.

[0470] If the potential of output terminal D changes from its initial state during period TM2, the Q6 bit is set to "0" from period TM2 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q6 bit is set to "1" from period TM2 onward until the control unit CNR is reset. In this embodiment, the Q6 bit is "1" from period TM2 onward.

[0471] [Period TM3] During period TM3, bit Q5, which is two bits below the MSB of the digital signal, is set to "1". That is, the digital signal (01100000)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, and 96nA (64+32nA) is output from the digital-to-analog conversion circuit IDCa. This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 171nA (75+64+32nA) flows through the input terminal CPTa, and the potential of the output terminal D becomes potential H.

[0472] If the potential of output terminal D changes from its initial state during period TM3, the Q5 bit is set to "0" from period TM3 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q5 bit is set to "1" from period TM3 onward until the control unit CNR is reset. In this embodiment, the Q5 bit is "0" from period TM3 onward.

[0473] [Period TM4] During period TM4, bit Q4, which is 3 bits below the MSB of the digital signal, is set to "1". That is, the digital signal (01010000)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, which outputs 80nA (64+16nA). This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 155nA (75+64+16nA) flows through the input terminal CPTa, and the potential of the output terminal D becomes potential H.

[0474] If the potential of output terminal D changes from its initial state during period TM4, the Q4 bit is set to "0" from period TM4 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q4 bit is set to "1" from period TM4 onward until the control unit CNR is reset. In this embodiment, the Q4 bit is "0" from period TM4 onward.

[0475] [Period TM5] During period TM5, bit Q3, which is 4 bits below the MSB of the digital signal, is set to "1". That is, the digital signal (01001000)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, and 72nA (64+8nA) is output from the digital-to-analog conversion circuit IDCa. This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 147nA (75+64+8nA) flows through the input terminal CPTa, and the potential of the output terminal D becomes potential L.

[0476] If the potential of output terminal D changes from its initial state during period TM5, the Q3 bit is set to "0" from period TM5 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q3 bit is set to "1" from period TM5 onward until the control unit CNR is reset. In this embodiment, the Q3 bit is "1" from period TM5 onward.

[0477] [Period TM6] During period TM6, the Q2 bit, which is 5 bits below the MSB of the digital signal, is set to "1". That is, the digital signal (01001100)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, which outputs 76nA (64+8+4nA). This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 151nA (75+64+8+4nA) flows through the input terminal CPTa, and the potential of the output terminal D becomes potential H.

[0478] If the potential of output terminal D changes from its initial state during period TM6, the Q2 bit is set to "0" from period TM6 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q2 bit is set to "1" from period TM6 onward until the control unit CNR is reset. In this embodiment, the Q2 bit is "0" from period TM6 onward.

[0479] [Period TM7] During period TM7, bit Q1, which is 6 bits below the MSB of the digital signal, is set to "1". That is, the digital signal (01001010)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, which outputs 74nA (64+8+2nA). This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 149nA (75+64+8+2nA) flows through the input terminal CPTa, and the potential of the output terminal D becomes potential L.

[0480] If the potential of output terminal D changes from its initial state during period TM7, the Q1 bit is set to "0" from period TM7 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q1 bit is set to "1" from period TM7 onward until the control unit CNR is reset. In this embodiment, the Q1 bit is "1" from period TM7 onward.

[0481] [Period TM8] During period TM8, the Q0 bit, which is the LSB of the digital signal, is set to "1". That is, the digital signal (01001011)2 is generated. This digital signal is input to the digital-to-analog conversion circuit IDCa, and 75nA (64+8+2+1nA) is output from the digital-to-analog conversion circuit IDCa. This output is supplied to the input terminal CPTa via node NDa. Therefore, a current of 150nA (75+64+8+2+1nA) flows through the input terminal CPTa, and the potential of the output terminal D becomes potential L.

[0482] If the potential of output terminal D changes from its initial state during period TM8, the Q0 bit is set to "0" from period TM8 onward until the control unit CNR is reset. If the potential of output terminal D does not change from its initial state, the Q0 bit is set to "1" from period TM8 onward until the control unit CNR is reset. In this embodiment, the Q0 bit is "1" from period TM8 onward.

[0483] In this way, by comparing the current quantity I sequentially from MSB to LSB, A and current I B The difference current of 75nA can be converted into a digital signal (01001011)2.

[0484] The successive approximation operation corresponding to step S204b can be understood by replacing the potential H with the potential L and the digital-to-analog conversion circuit IDCa with the digital-to-analog conversion circuit IDCb in the above explanation.

[0485] Furthermore, in this embodiment, since the step size of the output current of the digital-to-analog conversion circuit (IDC) is set to 1nA, differential currents up to a maximum of 255nA can be converted into digital signals. By increasing the step size of the output current of the digital-to-analog conversion circuit (IDC), larger differential currents can be handled. For example, by setting the step size of the output current of the digital-to-analog conversion circuit (IDC) to 2nA, differential currents up to a maximum of 510nA can be converted into digital signals.

[0486] <<Circuit FB>> Regarding circuit feedback (FB), as an example, please refer to the explanation of circuit feedback of the arithmetic circuit MACA1 described in Embodiment 1.

[0487] <<Control circuit CTR>> For the control circuit CTR, as an example, please refer to the explanation of the control circuit CTR of the arithmetic circuit MACA1 described in Embodiment 1.

[0488] <Example of operation of the arithmetic circuit 1> This section describes an example of the operation of the MACB1 arithmetic circuit shown in Figure 13.

[0489] First, we will explain the differences between the arithmetic circuit MACB1 and the arithmetic circuit MACA1 described in Embodiment 1.

[0490] The MACA1 arithmetic circuit is configured to perform a sum-of-products operation on a first data point that is positive or "0" and a second data point that is positive or "0". On the other hand, the MACB1 arithmetic circuit is configured to perform a sum-of-products operation on a first data point that is positive, negative, or "0" and a second data point that is positive or "0". Therefore, unlike the arithmetic cells in the MACA1 arithmetic circuit, the MACB1 arithmetic cells are configured to hold a first data point that is positive, negative, or "0". The CES[i,j] circuit in the MACB1 arithmetic circuit functions as an arithmetic cell that can hold a first data point that is positive, negative, or "0".

[0491] As explained in the configuration examples of cell IM and cell IMr, the circuit CES[i,j] has the function of holding the first data, with cell IM[i,j] and cell IMr[i,j] located at the same address as a pair. In this circuit configuration example, the amount of current flowing between the source and drain of transistor F2 contained in cell IM and the amount of current flowing between the source and drain of transistor F2r contained in cell IMr are set in the circuit CES[i,j] according to the first data. The relationship between the first data, which is positive, negative, or zero, and the amount of current flowing between the source and drain of transistor F2 and the amount of current flowing between the source and drain of transistor F2r, which are set according to the first data, is defined as follows.

[0492] When α[i,j] is written to circuit CES[i,j] as the value of the first positive data, the amount of current flowing between the source and drain of transistor F2 of cell IM[i,j] contained in circuit CES[i,j] is |α[i,j]| × I Wut It shall be set to the following, and the amount of current flowing between the source and drain of transistor F2r of cell IMr[i,j] shall be set to 0. Wut This is defined as the amount of current flowing when the absolute value of the first data point (in this case, α[i,j]) is 1.

[0493] Furthermore, if α[i,j] is written to circuit CES[i,j] as the negative first data value, the amount of current flowing between the source and drain of transistor F2 of cell IM[i,j] included in circuit CES[i,j] will be set to 0, and the amount of current flowing between the source and drain of transistor F2r of cell IMr[i,j] will be |α[i,j]| × I Wut It shall be set to [this value].

[0494] Furthermore, when the first data value of 0 is written to circuit CES[i,j], the amount of current flowing between the source and drain of transistor F2 of cell IM[i,j] included in circuit CES[i,j] shall be set to 0, and the amount of current flowing between the source and drain of transistor F2r of cell IMr[i,j] shall be set to 0.

[0495] Note that if one or both of the current flowing between the source and drain of transistor F2 in cell IM[i,j] and the current flowing between the source and drain of transistor F2r in cell IMr[i,j] are set to 0, no current will flow between the source and drain of one or both of transistors F2 and F2r. However, in this specification, etc., it may be stated that a current of 0 flows between the source and drain of one or both of transistors F2 and F2r.

[0496] Based on the above, each of the cells IM[i,j] and IMr[i,j] included in the circuit CES[i,j] will have two currents set according to one first data.

[0497] Here, the current set in cell IM[i,j] is assumed to be expressed in the same way as in equation (1.5) of Embodiment 1. Also, the current set in cell IMr[i,j] is w r Using [i,j], it can be expressed by the following equation, similar to equation (1.5) in Embodiment 1.

[0498]

number

[0499] Note: r [i,j] is a value corresponding to the first data (weighting coefficient), similar to w[i,j] in equation (1.5) of Embodiment 1. In this embodiment, when the first data is positive, w[i,j] is set to a positive value, w r When [i,j] is 0 and the first data is negative, set w[i,j] to 0, w r Let [i,j] be a positive value, and when the first data is 0, w[i,j] and w r Define [i] and [j] as 0.

[0500] For example, when the first data is -2, -1, 0, 1, and 2, the amount of current set in cell IM[i,j] and cell IMr[i,j] will be as shown in the table below.

[0501] [Table 1]

[0502] By writing the first data (w[1,j] to w[m,j]) to each of the cells IM[1,j] to IM[m,j] located in the j-th column of the cell array CA, and by flowing the second data to each of the wirings XCL[1] to XCL[m], the sum of the currents output from cells IM[1,j] to IM[m,j] can be described below, based on the operation example of the calculation circuit of Embodiment 1.

[0503]

number

[0504] Furthermore, in equation (2.2), when the first data α[i,j] is negative, we set w[i,j]=0, and when the first data α[i,j] is 0, we set w[i,j]=0, thereby determining the current I S It can represent [j].

[0505] Furthermore, each of the cells IMr[1,j] to IMr[m,j] located in the j-th column of the cell array CA contains the first data (w r [1,j]~w r By writing [m,j]) and sending the second data through each of the wires XCL[1] to XCL[m], the sum of the currents output from cells IMr[1,j] to IMr[m,j] can be expressed as follows, similar to equation (2.2).

[0506]

number

[0507] Note that in equation (2.3), when the first data α[i,j] is positive, w r Let [i,j]=0, and when the first data α[i,j] is 0, w r By setting [i,j]=0, the current I Sr It can represent [j].

[0508] Here, using the conversion circuit ITRZD[j], the difference current between the current in equation (2.2) and the current in equation (2.3) can be obtained. This difference current can be written as follows.

[0509]

number

[0510] In other words, the amount of differential current expressed by equation (2.4) is a value corresponding to the sum of the products of the first data (positive, negative, or "0") and the second data (positive, or "0"). Therefore, the result of the sum of the products of the first data and the second data can be obtained from this differential current.

[0511] Therefore, even in the case of an arithmetic circuit MACB1 having a cell array CA with 3 or more rows and 2 or more columns, the sum-of-accumulate operation can be performed as described above. In this case, the arithmetic circuit MACB1 uses one of the multiple columns (let's call it the i-th column) as the current quantity I ref0 [i], and x[i]×Iref0 By using a cell that holds [i], it is possible to simultaneously perform multiply-accumulate operations for the number of remaining columns among multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that can perform high-speed multiply-accumulate operations.

[0512] <<Example 1 of the first data writing operation including correction processing>> In the MACB1 arithmetic circuit shown in Figure 13, the correction process for the potential written to node N[i,j] of cell IM[i,j], which is used to write the first data, will be explained so that the cell IM[i,j] to which the first data is written outputs an appropriate amount of current corresponding to the first data.

[0513] Figure 17 is a flowchart showing an example of a first data writing operation including correction processing. This writing operation has steps S301 to S306.

[0514] Note that the flowchart in Figure 17 is a modified version of the flowchart in Figure 7, which was described in Embodiment 1. Therefore, explanations of the operations in the flowchart in Figure 17 that overlap with the operations and content of the flowchart in Figure 7 may be omitted.

[0515] [Step S301] Step S301, as an example, is similar to step S101, in the control circuit CTR, the value of the first data is W for the circuit WCSa[j] included in the circuit WCS. TRG The operation involves inputting a signal corresponding to the above. Furthermore, step S301 involves inputting a signal corresponding to a value of 0 from the control circuit CTR to the circuit WCSar[j] included in the circuit WCS.

[0516] In circuit WCSa[j], W TRG The corresponding signals can be, for example, the digital signals input to each of the wires DW[1] to DW[K] in the circuit WCSa shown in Figure 3.

[0517] Subsequently, the value of the digital signal input to each of the wirings DW[1] through DW[K] of wiring WCSa[j] is W WR It is referred to as such. For example, at step S301, W WR =W TRG This is the result.

[0518] Furthermore, in circuit WCSar[j], the signal corresponding to a value of 0 can be, for example, a low-level potential input to each of the wires DW[1] to DW[K] in circuit WCSa in Figure 3.

[0519] [Step S302] Step S302, as an example, is similar to step S102, where circuit WCSa[j] is input to each of the wirings DW[1] through DW[K], and the value W of the digital signal is input to each of them. WR Amount I corresponding to WR Generates a current (referred to as the writing current) and I WR The operation involves sending the current to the wiring WCL[j] and sending I to cell IM[i,j]. WR The write current flows through the first terminal (node ​​N[i,j]) of the capacitance C5 of cell IM[i,j], and I WR It has the operation of writing a potential corresponding to the writing current.

[0520] For details on the operation in step S302, please refer to the explanation of the operation in step S102.

[0521] Furthermore, step S302, as an example, involves the circuit WCSar[j] providing ground potential (GND) to the wiring WCLr[j].

[0522] For example, when the circuit WCSa in Figure 3 is applied to the circuit WCSar[j] in Figure 13, the potential supplied to wiring VINIL1 is used as the ground potential (GND), and switch SWW is turned ON. Then, a high-level potential is input to wiring SWL1, and by applying this high-level potential to the control terminal of switch S3r[j], switch S3r[j] is turned ON, thereby inputting the ground potential supplied to wiring VINIL1 to wiring WCLr[j].

[0523] Furthermore, when the current to cell IM[i,j] is set, a high-level potential is input to wiring WSL[i] among wiring WSL[1] to WSL[m], while a low-level potential is input to wiring WSL[1] to WSL[m] other than row i. As a result, among the cells IMr[1,j] to IMr[m,j] located in column j, transistor F1r of cell IMr[i,j] is turned on, and the respective transistors F1 of cells IM[1,j] to IM[m,j] other than row i are turned off.

[0524] At this time, the ground potential from wiring WCLr[j] is input to node Nr[i] (the first terminal of capacitor C5r) of cell IM[i,j] and the second terminal of transistor F2r. When the potential supplied by wiring VE0 is the ground potential, the gate-source voltage of transistor F2r becomes 0V, and if the threshold voltage of transistor F2r is appropriate, transistor F2r will be in the off state.

[0525] Furthermore, when the current is set for cell IM[i,j], the transistors F1r contained in cells IMr[1,j] to IMr[m,j] located in column j (excluding row i) are also in the off state, so nodes Nr[1,j] to Nr[m,j] (excluding row i) are in a floating state. At this time, the potential of each of the wirings XCL[1] to XCL[m] (excluding row i) becomes GND, which changes the potential of each of the nodes Nr[1,j] to Nr[m,j] (excluding row i). At this time, the transistors F2 contained in each of the cells IMr[1,j] to IMr[m,j] located in column j (excluding row i) are assumed to be in the off state.

[0526] Furthermore, since a low-level potential is input to the wiring SWL2 at this time, this low-level potential is applied to the control terminal of switch S4r[j]. As a result, switch S4r[j] is turned off.

[0527] As described above, with switch S3r[j] ON and switch S4r[j] OFF, and transistors F1r and F2r in cells IMr[1,j] to IMr[m,j] located in column j other than row i, the ground potential output from circuit WCSar[j] is input only to cell IMr[i,j]. Also, at this time, the gate-source voltage of transistor F2r in cell IMr[i,j] is 0V. By inputting a low-level potential to wiring WSL[i] and turning off transistor F1r in cell IMr[i,j], the potential of node Nr[i,j] can be maintained by capacitance C5. In other words, the gate-source voltage of transistor F2r in cell IMr[i,j] can be maintained at 0V.

[0528] [Step S303] Step S303, as an example, involves reading the first data written to cell IM[i,j], similar to step S103. In other words, step S303 involves cell IM[i,j] outputting a read current corresponding to the potential of capacitor C5 (node ​​N[i,j]), and the read current being input to the conversion circuit ITRZD[j], causing the conversion circuit ITRZD[j] to output a value corresponding to the read current to wiring OL[j].

[0529] Specifically, for example, by inputting a low-level potential into wiring SWL1 and applying that low-level potential to the control terminal of switch S3[j], switch S3[j] is turned off. Also, by inputting a high-level potential into wiring SWL2 and applying that high-level potential to the control terminal of switch S4[j], switch S4[j] is turned on.

[0530] Furthermore, a low-level potential is continuously applied to each of the wirings WSL[1] through WSL[m] to maintain the off state of transistor F1 in each of the cells IM[1,j] through IM[m,j] located in the j-th column.

[0531] Also, from step S102, the potential of wiring XCL[i] is V gm This maintains the potential of each wiring XCL[1] through XCL[m] other than row i to GND. This keeps the transistor F2 contained in each of cells IM[1,j] through IM[m,j] located in column j other than row i in the off state.

[0532] In cell IM[i,j], node N[i,j] holds the potential written in step S302. Here, since the potential supplied by wiring VE0 is the ground potential, the source-drain current of transistor F2 in cell IM[i,j] is determined according to the gate potential of transistor F2. Furthermore, the source-drain current of transistor F2 is assumed to flow from wiring WCL[j] to cell IM[i,j] as the first read current in step S303. Here, the amount of the source-drain current (read current) of transistor F2 in cell IM[i,j] is I RD Let's assume that the potential of node N[i,j] in cell IM[i,j] is appropriate, then the amount of writing current I WR And the amount of read current I RD and are equal to each other.

[0533] Furthermore, in cell IMr[i,j], node Nr[i,j] holds the ground potential written in step S302. Since the potential supplied by wiring VE0 is the ground potential, transistor F1r in cell IMr[i,j] is in the off state. Therefore, the source-drain current of transistor F2 (referred to as the read current for convenience) becomes 0. For this reason, as the second read current in step S303, a current of 0 flows from wiring WCLr[j] to cell IMr[i,j].

[0534] As described above, switch S3[j] is in the off state, switch S4[j] is in the on state, and transistors F1 and F2 of cells IM[1,j] to IM[m,j] located in column j other than row i are in the off state, therefore the setting I in cell IM[i,j] RD The current is output from the conversion circuit ITRZ[j] of circuit ITS via switch S4[j].

[0535] The current I is transmitted from the conversion circuit ITRZD[j] through switch S4[j] to the wiring WCL[j]. RDA current of 0 flows through the conversion circuit ITRZD[j], and a current of 0 flows from the conversion circuit ITRZD[j] through the switch S4r[j] to the wiring WCLr[j], so the conversion circuit ITRZD[j] receives a current of 1. RD The difference between this and a current of 0 (i.e., current I RD It outputs a potential corresponding to ). Furthermore, this potential is the value W read from cell IM[i,j]. RD It is then sent to circuit FB.

[0536] Specifically, as explained in Figures 14 and 15, the conversion circuit ITRZD[j] converts the difference in the amount of current flowing through wiring WCL and wiring WCLr into a digital signal. Then, the conversion circuit ITRZD[j] reads the value W from cell IM[i,j] using this digital signal. RD It is then sent to circuit FB.

[0537] Furthermore, the conversion circuit ITRZD[j] is not a digital signal, but rather a digital-to-analog conversion circuit that converts it to an analog potential, and the value W is read from the cell IM[i,j] of that analog potential. RD The signal containing this may be transmitted to circuit FB. In this case, for example, the circuit configuration may be such that a digital-to-analog conversion circuit is added to the conversion circuit ITRZD[j].

[0538] [Step S304] Step S304, as an example, is similar to step S104, where the circuit FB is set to the value W as the first data. TRG And the value W read from cell IM[i,j] RD It has the operation of comparing and .

[0539] Specifically, step S304 is W TRG and W RD If they are equal, the operation to terminate the write operation including the correction process and W TRG and W RD If they are not equal, the operation proceeds to step S305.

[0540] Note that Step S304 W TRG and WRD For the comparison operation, please refer to the explanation of step S104 in the flowchart in Figure 7.

[0541] [Step S305] Step S305, as an example, involves generating corrected first data (updated value) for the control circuit CTR to write again to cell IM[i,j], similar to step S105. Therefore, for the specific operation of step S305, please refer to the explanation of step S105 in the flowchart of Figure 7.

[0542] [Step S306] Step S306, as an example, similar to step S105, updates the circuit WCSa[j] included in the circuit WCS from the control circuit CTR as the update value W WR The process involves inputting a signal equivalent to +ΔW and then proceeding to step S302.

[0543] In other words, when the circuit WCSa[j] in Figure 3 is applied to the circuit WCSa[j] of the arithmetic circuit MACB1 in Figure 13, the value of the digital signal input to each of the wires DW[1] to DW[K] is the same as the value of the W input to the circuit WCSa[j] last time. WR The value is obtained by adding ΔW to the original value.

[0544] Therefore, after transitioning from step S306 to step S302, W described in steps S302 to S306 above WR is, W WR This can be explained by substituting +ΔW.

[0545] Furthermore, step S306, as an example, has the operation of the circuit WCSar[j] providing ground potential (GND) to the wiring WCLr[j], similar to step S301.

[0546] Subsequently, in step S304, W TRG and W RDBy repeatedly performing steps S302 to S306 until the values ​​become equal (the difference between the write current and the read current becomes 0), the potential corresponding to the first data can be appropriately written to cell IM[i,j].

[0547] As described above, by performing steps S301 to S306, variations in the writing of the first data to cell IM[i,j] can be suppressed.

[0548] Note that the flowchart in Figure 17 shows, as an example, the operation of writing a first data with a positive value, including the correction process. For example, in the above operation, the first data is W. TRG When the value is negative, the first data, including the correction process, can be written by changing the writing destination from cell IM[i,j] to cell IMr[i,j].

[0549] Furthermore, the first data writing operation, including the correction process, in the MACB1 arithmetic circuit of Figure 16 is not limited to the operation method shown in the flowchart of Figure 17. For example, the operation method shown in the flowchart of Figure 8 may be applied as appropriate to the MACB1 arithmetic circuit of Figure 16.

[0550] In the MACB1 arithmetic circuit of Figure 16, when applying the operation method of the flowchart in Figure 8 to appropriately correct the potential written to cell IM[i,j], it is preferable that the node Nr[i,j] of cell IMr[i,j] is supplied with a ground potential from wiring VINIL1 so that the transistor F2r of cell IMr[i,j] is turned off, similar to the flowchart in Figure 17. This makes it possible to set the amount of current flowing from wiring WCLr[j] to cell IMr[i,j] to 0, so that the MACB1 arithmetic circuit of Figure 16 can perform the first data writing operation, including the correction process, taking into consideration the operation method of the flowchart in Figure 8.

[0551] Furthermore, similar to Embodiment 1, the arithmetic circuits MACB0 and MACB1 described in this embodiment can each be treated as a memory device. Also, when reading the first data from circuit CES[i,j] in arithmetic circuit MACB0 or ​​arithmetic circuit MACB1, for example, the first data held in circuit CES[i,j] can be read by flowing a current corresponding to "1" as the value of the second data from circuit XCS to wiring XCL[i], and flowing a current corresponding to "0" as the value of the second data from circuit XCS to wiring XCL[1] to wiring XCL[m] other than row i. In this case, the conversion circuit ITRZ[j] included in circuit ITS is treated as a readout circuit that converts the amount of current into an analog potential or a digital signal. Furthermore, since circuit CES[i,j] uses cells IM[i,j] and IMr[i,j] as a single memory element, it can take on more threshold voltages as a multi-level memory than arithmetic circuits MACA0, MACA1, and MACA2, which use cell IM[i,j] as a single memory element. For this reason, arithmetic circuits MACB0 and MACB1 may also be referred to as memory devices in other embodiments.

[0552] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0553] (Embodiment 3) This embodiment describes an example of the configuration of the arithmetic circuit described in the above embodiment.

[0554] Furthermore, since the arithmetic circuit described in the above embodiment has the function of holding the first data, in this embodiment, the arithmetic circuit may be referred to as a memory device.

[0555] Figure 18A shows a schematic perspective view illustrating an example configuration of the storage device 100. Figure 18B shows a block diagram illustrating an example configuration of the storage device 100. The storage device 100 includes a drive circuit layer 50 and an N-layer (where N is an integer of 1 or more) storage layer 60.

[0556] The N-layer storage layer 60 is provided on the drive circuit layer 50. By providing the N-layer storage layer 60 on the drive circuit layer 50, the occupied area of ​​the storage device 100 can be reduced. In addition, the storage capacity per unit area can be increased.

[0557] In this embodiment, the first storage layer 60 is referred to as storage layer 60_1, the second storage layer 60 as storage layer 60_2, and the third storage layer 60 as storage layer 60_3. Furthermore, the kth storage layer 60 (where k is an integer between 1 and N) is referred to as storage layer 60_k, and the nth storage layer 60 as storage layer 60_N. In this embodiment, when describing matters relating to the entire N-layer storage 60, or when referring to matters common to each layer of the N-layer storage 60, the term "storage layer 60" may be used.

[0558] <Example of configuration of the drive circuit layer 50> The drive circuit layer 50 includes a PSW22 (power switch), a PSW23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0559] In the storage device 100, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0560] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 32.

[0561] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 100. For example, the control circuit 32 performs logical operations on signals CE, GW, and BW to determine the operating mode of the memory device 100 (e.g., write operation and read operation). The control circuit 32 also generates control signals for the peripheral circuit 41 so that this operating mode is executed.

[0562] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0563] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48.

[0564] The row decoder 42 and column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to access, and the column decoder 44 is a circuit for specifying the column to access.

[0565] The row driver 43 has the function of selecting the wiring WWL (write word line) or wiring RWL (read word line) specified by the row decoder 42. The row driver 43 can be, for example, one or both of the circuits WSD and XCS described in the above embodiment.

[0566] The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data. The column driver 45 also has the function of selecting the wiring BL (write and read bit lines) specified by the column decoder 44. The column driver 45 can be, for example, one or both of the circuit WCS and circuit ITS described in the above embodiment.

[0567] The input circuit 47 has the function of holding the signal WDA. The data held by the input circuit 47 (referred to as the first data in the above embodiment) is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory cell 10. The data (Dout) read by the column driver 45 from the memory cell 10 is output to the output circuit 48. In the above embodiment, the read data (Dout) is treated as the calculation result data. The output circuit 48 has the function of holding Dout. The output circuit 48 also has the function of outputting Dout to the outside of the storage device 100. The data output from the output circuit 48 is the signal RDA.

[0568] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. Signal PON1 switches PSW22 between the on and off states, and signal PON2 switches PSW23 between the on and off states. In Figure 1B, the number of power supply domains to which VDD is supplied in the peripheral circuit 31 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0569] <Example configuration of memory layer 60> An example configuration of an N-layer memory layer 60 is described below. Each of the N-layer memory layers 60 has a memory array 15. The memory array 15 also has multiple memory cells 10. Figures 18A and 18B show an example in which the memory array 15 has multiple memory cells 10 arranged in a matrix of p rows and q columns (where p and q are integers of 2 or more). The memory cells 10 may be replaced with the term memory element in other explanations, for example.

[0570] The memory cell 10 corresponds, for example, to the cell IM in Embodiment 1.

[0571] Note that rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction is defined as "rows" and the Y direction as "columns," but the X direction may be defined as "columns" and the Y direction as "rows."

[0572] In Figure 18B, the memory cell 10 located in the 1st row and 1st column is shown as memory cell 10[1,1], and the memory cell 10 located in the pth row and qth column is shown as memory cell 10[p,q]. Furthermore, the memory cell 10 located in the ith row and jth column (where i is an integer between 1 and p, and j is an integer between 1 and q) is shown as memory cell 10[i,j].

[0573] Figure 19A is an enlarged perspective block diagram of a portion of the memory layer 60_k. Figure 19B is a plan view of the area corresponding to Figure 19A, viewed from the Z direction. Each layer of the memory layer 60 has q wirings WDL extending in the Y direction (column direction), q wirings XCL extending in the Y direction (column direction), and q wirings VE1 extending in the Y direction (column direction). In Figures 19A and 19B, the wiring WDL located in the j-th column is shown as wiring WDL[j], the wiring XCL located in the j-th column is shown as wiring XCL[j], and the wiring VE1 located in the j-th column is shown as wiring VE1[j]. Wirings WDL[j], XCL[j], and VE1[j] are electrically connected to the memory cell 10 located in the j-th row.

[0574] In this embodiment, the wiring WDL shown in Figures 19A and 19B functions as the first write word line. Furthermore, the wiring WDL shown in Figures 19A and 19B corresponds to the wiring WDL[1] to wiring WDL[m] extending to the cell array CA in Embodiment 1.

[0575] Furthermore, in this embodiment, the wiring XCL shown in Figures 19A and 19B functions as the first read word line. Also, in Embodiments 1 and 2, the wiring XCL shown in Figures 19A and 19B corresponds to the wiring XCL[1] to wiring XCL[m] extending to the cell array CA in Embodiment 1.

[0576] Furthermore, in this embodiment, the wiring VE1 shown in Figures 19A and 19B functions as wiring that provides a constant potential. Also, the wiring VE1 shown in Figures 19A and 19B corresponds to the wiring VE1 that extends to the cell array CA in Embodiment 1. Note that the wiring VE1 shown in Figures 19A and 19B may be wiring that provides a high-level potential or a low-level potential instead of a constant potential. In this case, the wiring VE1 functions as a first write word line or a first read word line.

[0577] Furthermore, the memory layer 60 has wiring WCL and wiring VE0. Wiring WCL and wiring VE0 extend in the Z direction (vertical direction) and are arranged in a matrix of p rows and R columns (R is an integer depending on q, which will be described in detail later) in the plan view. In Figures 19A and 19B, wiring WCL and wiring VE0 located in the i-th row and s-th column (s is an integer between 1 and R) are shown as wiring WCL[i,s] and wiring VE0[i,s], respectively.

[0578] Furthermore, in this embodiment, the wiring WCLs shown in Figures 19A and 19B function as write and read bit lines. Also, the wiring WCLs shown in Figures 19A and 19B correspond to the wiring WCL[1] to wiring WCL[n] extending to the cell array CA in Embodiment 1.

[0579] Furthermore, in this embodiment, the wiring VE0 shown in Figures 19A and 19B functions as wiring that provides a constant potential. Also, the wiring VE0 shown in Figures 19A and 19B corresponds to the wiring VE0 that extends to the cell array CA in Embodiment 1.

[0580] In the memory layer 60_k, one wiring WCL is electrically connected to two memory cells 10. One wiring VE0 is electrically connected to two memory cells 10. By sharing one wiring WCL and one wiring VE0 between two adjacent memory cells 10, the occupied area of ​​the memory array 15 can be reduced. In addition, the integration density of the memory cells 10 can be improved, and the storage capacity of the storage device 100 can be increased.

[0581] In Figures 19A and 19B, wiring WCL[i,s] is electrically connected to memory cell 10[i,j] and memory cell 10[i,j+1]. Specifically, wiring WCL[i,s] is electrically connected to memory cell 10[i,2×s-1]_k and memory cell 10[i,2×s]_k.

[0582] Furthermore, in Figures 19A and 19B, wiring VE0[i,s+1] is electrically connected to memory cells 10[i,j+1] and 10[i,j+2]. Memory cell [i,j] is electrically connected to wiring VE0[i,s], and memory cell [i,j+3] is electrically connected to wiring VE0[i,s+2].

[0583] The relationship between R, which indicates the position of a column, and q can be expressed as follows (3.1) or (3.2) when q is odd.

[0584]

number

[0585]

number

[0586] The relationship between R, which indicates the position of a column, and q can be expressed as (3.3) or (3.4) below when q is an even number.

[0587]

number

[0588]

number

[0589] The column positions s and j can be expressed as follows (3.5) or (3.6) if j is an odd number.

[0590]

number

[0591]

number

[0592] The column positions s and j can be expressed as (3.7) or (3.8) below if j is an even number.

[0593]

number

[0594]

number

[0595] Figure 20A shows a schematic cross-sectional view of memory cells 10[i,j] and 10[i,j+1] of the memory layer 60_k. Figure 20B shows an example of the circuit configuration of Figure 20A. Note that Figure 20A shows an enlarged view of a portion of the schematic cross-sectional view.

[0596] Memory cell 10[i,j] has transistors F1, F2, F5, and capacitance C5, similar to cell IM described in Embodiment 1 above. A memory cell composed of three transistors and one capacitance is also called a 3Tr1C type memory cell. Therefore, memory cell 10 shown in this embodiment is a 3Tr1C type memory cell.

[0597] In memory cell 10[i,j], the gate of transistor F1 is electrically connected to wiring WDL[j], and the first terminal of transistor F1 is electrically connected to wiring WCL[i,s]. Figure 20A shows an example configuration where a portion of wiring WDL[j] functions as the gate of transistor F1. The gate of transistor F2 is electrically connected to the first terminal of capacitor C5, the first terminal of transistor F2 is electrically connected to the first terminal of transistor F5, and the second terminal of transistor F2 is electrically connected to wiring VE0[i,s]. The first terminal of transistor F5 is also electrically connected to wiring WCL[i,s]. The second terminal of capacitor C5 is also electrically connected to wiring XCL[j]. Figure 20A and others show an example configuration where a portion of wiring XCL[j] functions as the second terminal of capacitor C5. The gate of transistor F5 is also electrically connected to wiring VE1[j]. Note that Figure 20A and others show an example configuration where a portion of the wiring VE1[j] functions as the gate of transistor F5.

[0598] In memory cell 10[i,j+1], the gate of transistor F1 is electrically connected to wiring WDL[j+1], and the first terminal of transistor F1 is electrically connected to wiring WCL[i,s]. Figure 20A shows an example configuration where a portion of wiring WDL[j+1] functions as the gate of transistor F1. The gate of transistor F2 is electrically connected to the first terminal of capacitor C5, the first terminal of transistor F2 is electrically connected to the first terminal of transistor F5, and the second terminal of transistor F2 is electrically connected to wiring VE0[i,s+1]. The first terminal of transistor F5 is also electrically connected to wiring WCL[i,s]. The second terminal of capacitor C5 is also electrically connected to wiring XCL[j+1]. Figure 20A and others show an example configuration where a portion of wiring XCL[j+1] functions as the second terminal of capacitor C5. The gate of transistor F5 is also electrically connected to wiring VE1[j+1]. Note that Figure 20A and others show an example configuration where a portion of the wiring VE1[j+1] functions as the gate of transistor F5.

[0599] In memory cell 10[i,j] and memory cell 10[i,j+1], the region where the first terminal of capacitor C5, the first terminal of transistor F1, and the gate of transistor F2 are electrically connected and always at the same potential is called "node N".

[0600] Furthermore, as shown in Figures 20A and 20B, transistors with back gates may be used as transistors F1, F2, and F5. The gate and back gate are arranged so as to sandwich the semiconductor channel formation region between them. The gate and back gate are formed of a conductor. The back gate can be made to function in the same way as the gate. Also, the threshold voltage of the transistor can be changed by changing the potential of the back gate. The potential of the back gate may be the same as the gate potential, or it may be the ground potential or any other potential.

[0601] Furthermore, since the gate and back gate are made of a conductor, they also have the function of preventing electric fields generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly an electrostatic shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of external electric fields such as static electricity. In addition, by providing a back gate, the change in the threshold voltage of the transistor before and after bias thermal stress testing (sometimes called BT testing) can be reduced.

[0602] For example, by using a transistor with a back gate in transistor F1, the influence of external electric fields is reduced, and the off state can be stably maintained. Therefore, the data written to node N can be stably retained. By providing a back gate, the operation of the memory cell 10 is stabilized, and the reliability of the memory device including the memory cell 10 can be improved.

[0603] The semiconductor layer on which the channels of transistors F1, F2, and F5 are formed can be a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, either individually or in combination. As the semiconductor material, for example, as described in Embodiment 1, silicon, germanium, etc., can be used. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0604] Furthermore, it is preferable that the transistors F1, F2, and F5 are OS transistors (OS transistors) in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channels are formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the storage device 100 including the memory cell 10 can be reduced.

[0605] Furthermore, a memory cell containing an OS transistor can be called an "OS memory." Similarly, a storage device 100 containing such memory cells can also be called an "OS memory."

[0606] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, the on-current does not decrease significantly even in high-temperature environments. Therefore, OS memory operates stably even in high-temperature environments, resulting in high reliability.

[0607] Furthermore, in the example cross-sectional configuration shown in Figure 20A, the conductor 242a (conductors 242a1 and 242a2), which includes a region that functions as either the source or drain electrode of transistor F1, extends beyond the oxide 230 (oxides 230a and 230b), which functions as a semiconductor layer. Therefore, the conductor 242 also functions as wiring. In Figure 20A, parts of the top, side, and bottom surfaces of the conductor 242a are electrically in contact with the wiring WCL[i,s] extending in the Z direction.

[0608] Since the wiring WCL[i,s] directly contacts one or more selected surfaces from the top, side, and bottom of the conductor 242a, there is no need to provide separate connection electrodes, thus reducing the occupied area of ​​the memory array 15. In addition, the integration density of the memory cells 10 is improved, and the storage capacity of the storage device 100 can be increased. Preferably, the wiring WCL[i,s] contacts two or more surfaces from the top, side, and bottom of the conductor 242a. By having the wiring WCL[i,s] contact multiple surfaces of the conductor 242a, the contact resistance between the wiring WCL[i,s] and the conductor 242a can be reduced.

[0609] Furthermore, the conductor 242b (conductors 242b1 and 242b2), which includes a region functioning as the second terminal of transistor F1, extends beyond the oxide 230 (oxides 230a and 230b), which functions as a semiconductor layer. In the example cross-sectional configuration shown in Figure 20A, a conductor 366 is provided in contact with the lower surface of the conductor 242b. Also, the conductor 242b and the gate of transistor F2 are electrically connected via the conductor 366.

[0610] By providing a conductor 366 in the region overlapping with the conductor 242b and electrically connecting it to the lower conductor, the connection distance between the two can be shortened. Furthermore, the number of wires required for the configuration of the memory cell 10 can be reduced. Therefore, the occupied area of ​​the memory cell 10 can be reduced. Consequently, the storage capacity and storage density of the memory device can be increased.

[0611] Furthermore, the second terminal of transistor F5 is electrically connected to the wiring WCL[i,s] in a configuration similar to that of the second terminal of transistor F1. Specifically, it is electrically connected to the wiring WCL[i,s] via a conductor that includes a region functioning as the second terminal of transistor F5. Also, similar to transistor F1, it is preferable that one or more portions selected from the top, side, and bottom surfaces of the conductor are in contact with the wiring WCL[i,s].

[0612] Furthermore, the second terminal of transistor F2 may be electrically connected to the wiring VE0[i,s] in the same configuration as the first terminal of transistor F1. Specifically, it may be electrically connected to the wiring VE0[i,s] via a conductor that includes a region functioning as the second terminal of transistor F2. It is also preferable that one or more parts selected from the top, side, and bottom surfaces of the conductor are in contact with the wiring VE0[i,s].

[0613] Figure 21 shows an example of a cross-sectional configuration in which memory layers 60_1 to 60_5 are stacked. Figure 22 shows an example of the circuit configuration of Figure 21. In Figures 21 and 22, the memory cells 10[i,j] of memory layers 60_1 to 60_5 are shown as memory cells 10[i,j]_1 to 10[i,j]_5. Also, the wiring WDL[j] of memory layer 60_5 is shown as wiring WDL[j]_5, the wiring XCL[j] of memory layer 60_5 is shown as wiring XCL[j]_5, and the wiring VE0[j] of memory layer 60_5 is shown as wiring VE0[j]_5. Furthermore, the wiring WDL[j+1] of the memory layer 60_5 is denoted as wiring WDL[j+1]_5, the wiring XCL[j+1] of the memory layer 60_5 is denoted as wiring XCL[j+1]_5, and the wiring VE0[j+1] of the memory layer 60_5 is denoted as wiring VE0[j+1]_5.

[0614] Figures 21 and 22 show an example configuration in which five memory layers 60 are stacked, but the number of stacked memory layers 60 is not limited to five. By increasing the number of stacked memory layers 60, the storage capacity of the storage device 100 can be increased without increasing the occupied area of ​​the memory cell 10. Therefore, the occupied area per bit is reduced, and a compact storage device with a large storage capacity can be realized.

[0615] Furthermore, when the memory device 100 is used as the arithmetic circuit described in Embodiment 1, the sum of products can be calculated using the circuit configuration shown in Figure 22. Specifically, in Figure 22, by configuring memory cells 10[i,j]_1 to 10[i,j]_5 and memory cells 10[i,j+1]_1 to 10[i,j+1]_5 to each be used as arithmetic cells, and by flowing an amount of current corresponding to the sum of products through the wiring WCL[i,s], the memory device 100 can be used as an arithmetic circuit in the same way as the arithmetic circuit described in Embodiment 1.

[0616] Next, examples of the configuration of transistors and capacitances included in the memory cell 10 will be described in detail in other embodiments.

[0617] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0618] (Embodiment 4) In this embodiment, an example of the configuration of a semiconductor device applicable to a memory cell 10 according to one aspect of the present invention will be described with reference to the drawings. The semiconductor device shown in this embodiment has a transistor and a capacitive element.

[0619] <Example of semiconductor device configuration> An example of the configuration of a semiconductor device having transistors and capacitive elements will be explained using Figure 23. Figures 23A to 23D are top views and cross-sectional views of a semiconductor device having transistors 200a, 200b, capacitive element 150a, and capacitive element 150b.

[0620] Transistor 200a or transistor 200b can be used in transistors F1 and F2 as shown in the above embodiment. Capacitive elements 150a and 150b can be used in capacitor C5 as shown in the above embodiment.

[0621] Figure 23A is a plan view of the semiconductor device. Figures 23B to 23D are cross-sectional views of the same semiconductor device. Here, Figure 23B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 23A, and is a cross-sectional view of transistors 200a and 200b in the channel length direction, and is also a cross-sectional view of capacitive elements 150a and 150b. Figure 23C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 23A, and is a cross-sectional view of transistor 200a in the channel width direction. Figure 23D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 23A, and is a cross-sectional view of transistor 200a and capacitive element 150a in the channel width direction. Note that in the plan view of Figure 23A, some components have been omitted for clarity.

[0622] Furthermore, the X direction shown in Figure 23A is parallel to the channel length direction of transistor 200a and the channel length direction of transistor 200b.

[0623] A semiconductor device according to one aspect of the present invention includes an insulator 214 on a substrate (not shown), transistors 200a, 200b, capacitive elements 150a, and 150b on the insulator 214, an insulator 280 on an insulator 275 provided on transistors 200a and 200b, an insulator 282 on the capacitive elements 150a, on the capacitive elements 150b, and on the insulator 280, an insulator 285 on the insulator 282, and a conductor 240 (conductor 240a and conductor 240b). The insulators 214, 280, 282, and 285 function as interlayer films. As shown in Figure 23B, each of the transistors 200a, 200b, 150a, and 150b is arranged with at least a portion embedded in the insulator 280.

[0624] Here, transistors 200a and 200b each have an oxide 230 that functions as a semiconductor layer, a conductor 260 that functions as a first gate (also called a top gate) electrode, a conductor 205 that functions as a second gate (also called a back gate) electrode, a conductor 242a that functions as either a source electrode or a drain electrode, and a conductor 242b that functions as the other of the source electrode or a drain electrode. They also have insulators 253 and 254 that function as first gate insulators, and insulators 222 and 224 that function as second gate insulators. Note that gate insulators are sometimes also called gate insulating layers or gate insulating films.

[0625] Since transistors 200a and 200b have the same configuration, in the following explanations, when describing matters common to both transistors 200a and 200b, the symbol attached to the reference numeral may be omitted, and they may be referred to simply as transistor 200.

[0626] The first gate electrode and the first gate insulating film are placed within the opening 258 formed in the insulators 280 and 275. That is, the conductor 260, insulator 254, and insulator 253 are placed within the opening 258.

[0627] Each capacitive element 150a and each capacitive element 150b has a conductor 242b that functions as a lower electrode, an insulator 275, an insulator 153, and an insulator 154 that functions as a dielectric, and a conductor 160 that functions as an upper electrode. In other words, each capacitive element 150a and each capacitive element 150b constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0628] Since capacitive elements 150a and 150b have the same configuration, in the following explanations, when describing matters common to capacitive elements 150a and 150b, the symbols attached to the reference numerals may be omitted, and they may be referred to simply as capacitive element 150.

[0629] The upper electrode and a portion of the dielectric of the capacitive element 150 are placed within an opening 158 formed in the insulator 280. That is, the conductor 160, insulator 154, and insulator 153 are placed within the opening 158.

[0630] Furthermore, a semiconductor device according to one aspect of the present invention includes a conductor 240 (conductor 240a and conductor 240b) which is electrically connected to the transistor 200 and functions as a plug. Conductor 240 has a region that is in contact with conductor 242a.

[0631] Furthermore, a semiconductor device according to one aspect of the present invention has an insulator 210 and a conductor 209 between a substrate (not shown) and an insulator 214. The conductor 209 is arranged so as to be embedded in the insulator 210. The conductor 209 has a region that is in contact with the conductor 240.

[0632] Furthermore, a semiconductor device according to one aspect of the present invention may have an insulator 212 between the insulator 210 and the conductor 209 and the insulator 214.

[0633] The semiconductor device having a transistor 200 and a capacitive element 150 as shown in this embodiment can be used as a memory cell of a storage device. In this case, the conductor 240 may be electrically connected to a sense amplifier. Here, as shown in Figure 23A, the capacitive element 150 is provided such that at least a part of it overlaps with the oxide 230 of the transistor 200. Therefore, the capacitive element 150 can be provided without significantly increasing the occupied area in the plan view, and thus the semiconductor device according to this embodiment can be miniaturized or highly integrated.

[0634] Furthermore, the semiconductor device shown in this embodiment has a line-symmetric configuration with respect to the dashed line A7-A8 shown in Figure 23A as the axis of symmetry. The conductor 242a serves as both the source electrode or drain electrode of transistor 200a and the source electrode or drain electrode of transistor 200b. By connecting the two transistors, the two capacitive elements, and the plug in the above configuration, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0635] [Transistor 200] As shown in Figures 23A to 23D, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and a conductor 242a (conductors 242a1 and 205b) on the oxide 230b. The device comprises a body 242a2) and a conductor 242b (conductors 242b1 and 242b2), an insulator 253 on oxide 230b, an insulator 254 on insulator 253, a conductor 260 (conductors 260a and 260b) located on insulator 254 and overlapping with a portion of oxide 230b, and an insulator 275 arranged on insulator 222, insulator 224, oxide 230a, oxide 230b, conductor 242a, and conductor 242b.

[0636] In this specification, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242.

[0637] Insulators 280 and 275 are provided with an opening 258 that reaches the oxide 230b. In other words, the opening 258 has a region that overlaps with the oxide 230b. Also, insulator 275 has an opening that overlaps with the opening of insulator 280. Insulators 253, 254, and conductor 260 are arranged within the opening 258. In other words, conductor 260 has a region that overlaps with the oxide 230b via insulators 253 and 254. Furthermore, in the channel length direction of transistor 200, conductor 260, insulator 253, and insulator 254 are provided between conductor 242a and conductor 242b. Insulator 254 has a region that is in contact with the side surface of conductor 260 and a region that is in contact with the bottom surface of conductor 260. As shown in Figure 23C, in the region of the opening 258 that does not overlap with the oxide 230, the upper surface of the insulator 222 is exposed.

[0638] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0639] Although the transistor 200 shows a configuration in which the oxide 230 consists of two layers, oxide 230a and oxide 230b, the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0640] Conductor 260 functions as a first gate electrode, and conductor 205 functions as a second gate electrode. Insulators 253 and 254 function as first gate insulators, and insulators 222 and 224 function as second gate insulators. Conductor 242a functions as either a source electrode or a drain electrode, and conductor 242b functions as the other source electrode or drain electrode. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0641] Here, an enlarged view of the vicinity of the channel formation region in Figure 23B is shown in Figure 25A. As shown in Figure 25A, in the cross-sectional view of the transistor 200 in the channel length direction, it is preferable that the distance L2 between the conductor 242a and the conductor 242b is smaller than the width of the opening 258. Here, the width of the opening 258 corresponds to the distance L1 between the interface of the insulator 280 and the insulator 253 on the conductor 242a side and the interface of the insulator 280 and the insulator 253 on the conductor 242b side, as shown in Figure 25A. As will be described in detail later, in this embodiment, channel etching of the conductor 242a and the conductor 242b is performed after the formation of the opening 258. With this configuration, the distance L2 between the conductor 242a and the conductor 242b can be made relatively easily into a very fine structure (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). Furthermore, since the conductor 260 has a region at a distance L1 that is greater than the distance L2, it suppresses the decrease in conductivity of the conductor 260 located in the region at distance L1, allowing the conductor 260 to function as wiring.

[0642] The opening 258 can also be considered as having a shape in which a part of the structure containing insulator 224, oxide 230, conductor 242, and insulator 275 protrudes into an opening with insulator 222 as the bottom surface and insulator 280 as the side surface. Furthermore, in the structure containing insulator 224, oxide 230, conductor 242, and insulator 275, the region of oxide 230 sandwiched between conductor 242a and conductor 242b can be considered as being exposed.

[0643] As shown in Figures 25A and 23C, an insulator 253 is provided in contact with the bottom surface and inner wall of the opening 258. Thus, the insulator 253 is in contact with at least a portion of the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductors 242a and 242b, the side surface of the insulator 275, the side surface of the insulator 280, and the bottom surface of the insulator 254. Furthermore, the insulator 254 and the conductor 260 are laminated on the insulator 253. For this reason, the insulator 253, insulator 254, and conductor 260 are provided to cover the conductor 242 and insulator 275 which partially protrude into the opening 258.

[0644] A channel formation region is formed in the oxide 230b at a distance L2. Therefore, the channel formation region of transistor 200 has a very fine structure. This increases the on-current of transistor 200, improving its frequency characteristics.

[0645] Note that the shape of the opening 258 is not limited to the shape shown in Figure 25A. As shown in Figure 25B, the opening 258 may have a shape in which distance L1 and distance L2 are equal. In this case, as shown in Figure 25B, the side surface of the conductor 242a and the side surface of the insulator 275 roughly coincide with the side surface of the insulator 280. Also, the side surface of the conductor 242b and the side surface of the insulator 275 roughly coincide with the side surface of the insulator 280. By adopting this configuration, the manufacturing process of the semiconductor device can be simplified and productivity can be improved. Furthermore, when providing multiple transistors 200, it becomes possible to reduce the area and increase the density.

[0646] Figure 25B shows a configuration in which the side wall of the opening 258 is approximately perpendicular to the upper surface of the insulator 222, but the present invention is not limited to this. As shown in Figure 25C, the side wall of the opening 258 may be tapered. By making the side wall of the opening 258 tapered, the covering of the insulator 253 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0647] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. For example, it is preferable that there is a region in which the angle between the inclined side surface of the structure and the substrate surface (bottom surface) (hereinafter sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface (bottom surface) do not necessarily have to be perfectly flat, and may be substantially planar with a fine curvature, or substantially planar with fine irregularities.

[0648] As shown in Figure 25A, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich region 230bc and function as a source region or drain region. At least a portion of region 230bc is superimposed on the conductor 260. In other words, region 230bc is provided in the region between conductors 242a and 242b. Region 230ba is provided superimposed on conductor 242a, and region 230bb is provided superimposed on conductor 242b.

[0649] Region 230bc, which functions as a channel-forming region, has fewer oxygen vacancies or lower impurity concentrations than regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. Thus, region 230bc can be said to be type i (intrinsic) or substantially type i.

[0650] Furthermore, regions 230ba and 230bb, which function as source or drain regions, are regions with high oxygen deficiencies or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, resulting in increased carrier concentration and low resistance. In other words, regions 230ba and 230bb are n-type regions with higher carrier concentration and lower resistance compared to region 230bc.

[0651] Here, as shown in Figure 25A, it is preferable that the opposing sides of conductor 242a and conductor 242b are approximately perpendicular to the upper surface of oxide 230b. This configuration prevents the side edge of region 230ba formed beneath conductor 242a on the region 230bc side from receding excessively from the side edge of conductor 242a on the region 230bc side. Similarly, it prevents the side edge of region 230bb formed beneath conductor 242b on the region 230bc side from receding excessively from the side edge of conductor 242b on the region 230bc side. This reduces the formation of so-called Loff regions between region 230ba and region 230bc, and between region 230bb and region 230bc. Here, when we say that the side edge of region 230ba on the region 230bc side is receding, it means that the side edge of region 230ba is located closer to conductor 240 than the side surface of conductor 242a on the region 230bc side. Furthermore, when we say that the side edge of region 230bb on the region 230bc side is recessed, it means that the side edge of region 230bb is located closer to the conductor 160 than the side surface of the conductor 242b on the region 230bc side.

[0652] As a result, the frequency characteristics of the transistor 200 can be improved, and the operating speed of the semiconductor device according to one aspect of the present invention can be improved. For example, when the semiconductor device according to one aspect of the present invention is used as a memory cell in a storage device, the writing speed and reading speed can be improved.

[0653] Furthermore, the carrier concentration in region 230bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3It is even more preferable that it be less than . Furthermore, there is no particular limit to the lower limit of the carrier concentration in region 230bc which functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0654] Furthermore, a region may be formed between region 230bc and region 230ba, or between region 230bc and region 230bb, where the carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba, or between region 230bc and region 230bb. In this junction region, the hydrogen concentration may be equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. Also, in this junction region, the oxygen deficiency may be equal to or less than that of region 230ba and region 230bb, and equal to or greater than that of region 230bc.

[0655] Although Figure 25A shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0656] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentration of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0657] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0658] Furthermore, the band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0659] As oxide 230, it is preferable to use a metal oxide such as indium oxide, gallium oxide, and zinc oxide. Alternatively, as oxide 230, it is preferable to use a metal oxide having one or more elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin. A metal oxide having indium, element M, and zinc may be referred to as In-M-Zn oxide.

[0660] The oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. This configuration suppresses the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b.

[0661] Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. With this configuration, transistor 200 can obtain a large on-current and high frequency characteristics.

[0662] Furthermore, because oxides 230a and 230b share a common element other than oxygen as a main component, the defect level density at the interface between oxides 230a and 230b can be reduced. As a result, the influence of interfacial scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0663] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, In:M:Zn = 1:1:1.2 [atomic ratio] or close to it, In:M:Zn = 1:1:2 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M. Also, when a single layer of oxide 230b is provided as oxide 230, a metal oxide that can be used for oxide 230a may be applied as oxide 230b.

[0664] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0665] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0666] CAAC-OS is a metal oxide with a highly crystalline, dense structure and low levels of impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0667] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0668] Furthermore, by using a crystalline oxide such as CAAC-OS as oxide 230b, the extraction of oxygen from oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 230b is reduced, making the transistor 200 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0669] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). OOxygen vacancies (sometimes called H) can form and generate electron carriers. Therefore, if the region where channels are formed in an oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which channels exist and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the region where channels are formed in an oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsic) or substantially type i.

[0670] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device having the transistor. In addition, if the oxygen supplied from the insulator to the oxide semiconductor diffuses into conductors such as the gate electrode, source electrode, and drain electrode, these conductors may oxidize, impairing their conductivity and potentially adversely affecting the electrical characteristics and reliability of the transistor.

[0671] Therefore, in an oxide semiconductor, it is preferable that the region 230bc, which functions as a channel-forming region, has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H. Also, ensure that an excessive amount of oxygen is not supplied to regions 230ba and 230bb, and that the V between regions 230ba and 230bb is reduced.O It is preferable to prevent an excessive reduction in the amount of H. It is also preferable to have a configuration that suppresses a decrease in the conductivity of conductor 260, conductor 242a, and conductor 242b. For example, it is preferable to have a configuration that suppresses oxidation of conductor 260, conductor 242a, and conductor 242b. Note that hydrogen in oxide semiconductors is V O Since H can be formed, V O To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0672] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in region 230bc, suppress oxidation of conductors 242a, 242b, and 260, and suppress the reduction of hydrogen concentration in regions 230ba and 230bb.

[0673] To reduce the hydrogen concentration in region 230bc, it is preferable that the insulator 253 has the function of capturing and fixing hydrogen. As shown in Figure 23C, the insulator 253 has a region that is in contact with region 230bc of oxide 230b. With this configuration, the hydrogen concentration in region 230bc of oxide 230b can be reduced. Therefore, the hydrogen concentration in region 230bc O By reducing H, region 230bc can be made i-type or substantially i-type.

[0674] Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. For example, it is preferable to use metal oxides such as magnesium oxide, or oxides containing one or both of aluminum and hafnium. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, amorphous metal oxides can be said to have a high ability to capture or fix hydrogen.

[0675] The insulator 253 and the insulator 153 of the capacitive element 150 are formed using the same insulating film. In other words, the insulator 253 and the insulator 153 have the same material. Furthermore, the insulator 153 functions as a dielectric of the capacitive element 150. Therefore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 153. In this case, the insulator 253 includes a high-k material. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulator 253, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. It also becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0676] Based on the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 253, and it is more preferable to use an oxide containing one or both of aluminum and hafnium having an amorphous structure, and it is even more preferable to use hafnium oxide having an amorphous structure. In this embodiment, hafnium oxide is used as the insulator 253. In this case, the insulator 253 is an insulator having at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 253 has an amorphous structure.

[0677] To suppress oxidation of conductors 242a, 242b, and 260, it is preferable to provide oxygen barrier insulators near each of conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, insulator 253, insulator 254, and insulator 275.

[0678] In this specification, a barrier insulator refers to an insulator that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0679] Examples of oxygen barrier insulators include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, insulators 253, 254, and 275 can each be made of the above oxygen barrier insulators in a single layer or a multi-layer structure.

[0680] The insulator 253 preferably has barrier properties against oxygen. The insulator 253 only needs to be less permeable to oxygen than the insulator 280. The insulator 253 has regions that are in contact with the side surfaces of the conductor 242a and the conductor 242b. The oxygen barrier properties of the insulator 253 suppress oxidation of the side surfaces of the conductors 242a and 242b, preventing the formation of an oxide film on these surfaces. This suppresses a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0681] Furthermore, the insulator 253 is provided in contact with the upper and side surfaces of oxide 230b, the side surfaces of oxide 230a, the side surfaces of insulator 224, and the upper surface of insulator 222. Because the insulator 253 has an oxygen barrier property, it can suppress the detachment of oxygen from the oxide 230b region 230bc when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in oxide 230a and oxide 230b can be reduced.

[0682] Conversely, even if the insulator 280 contains an excess amount of oxygen, it is possible to suppress the excessive supply of that oxygen to oxides 230a and 230b. Therefore, it is possible to suppress excessive oxidation of regions 230ba and 230bb, which would cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility.

[0683] Oxides containing either or both aluminum and hafnium have barrier properties against oxygen and can therefore be suitably used as insulator 253.

[0684] The insulator 254 preferably has barrier properties against oxygen. The insulator 254 is provided between the oxide region 230bc and the conductor 260, and between the insulator 280 and the conductor 260. This configuration suppresses the diffusion of oxygen contained in the oxide region 230bc into the conductor 260, preventing the formation of oxygen vacancies in the oxide region 230bc. It also suppresses the diffusion of oxygen contained in the oxide 230 and the oxygen contained in the insulator 280 into the conductor 260, preventing the oxidation of the conductor 260. The insulator 254 only needs to be less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0685] The insulator 275 preferably has barrier properties against oxygen. The insulator 275 is provided between the insulator 280 and the conductors 242a and 242b. This configuration suppresses the diffusion of oxygen contained in the insulator 280 to the conductors 242a and 242b. Therefore, it is possible to suppress the oxidation of the conductors 242a and 242b by the oxygen contained in the insulator 280, which increases their resistivity and reduces the on-current. The insulator 275 only needs to be less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 will be an insulator containing at least nitrogen and silicon.

[0686] To suppress the reduction of hydrogen concentration in regions 230ba and 230bb, it is preferable to provide hydrogen barrier insulators near regions 230ba and 230bb, respectively. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is, for example, insulator 275.

[0687] Examples of hydrogen barrier insulators include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 may be made of the above hydrogen barrier insulator in a single layer or a multi-layer structure.

[0688] It is preferable that the insulator 275 has barrier properties against hydrogen. The insulator 275 is arranged in contact with the side surfaces of the oxide 230b region 230ba and the oxide 230b region 230bb, respectively. The in...

Claims

1. It comprises a control circuit, a first circuit, a second circuit, a first wiring, a first cell, and a conversion circuit. The control circuit is electrically connected to the first circuit and the second circuit. The first circuit is electrically connected to the first wiring, The input terminal of the conversion circuit is electrically connected to the first wiring, The output terminal of the conversion circuit is electrically connected to the second circuit. The first cell is electrically connected to the first wiring, and the method of operating a semiconductor device is as follows: The process comprises steps 1 through 6, The first step includes the operation of the control circuit transmitting a first signal to the first circuit corresponding to the value of the first data, The second step described above is: The first circuit acquires the first signal, generates a first current in an amount corresponding to the first signal, and outputs the first current to the first wiring; The first current flows from the first wiring to the first cell, causing the first cell to maintain a first potential corresponding to the amount of the first current. The previous third step is, The first cell performs the operation of supplying a second current from the first wiring in an amount corresponding to the first potential, The conversion circuit has the operation of referring to the second current flowing through the first wiring, which is electrically connected to the input terminal of the conversion circuit, and outputting a second signal from the output terminal of the conversion circuit corresponding to the amount of the second current, The fourth step is, The control circuit performs the operation of transmitting a signal to the second circuit corresponding to the value of the first data, The second circuit performs the operation of calculating the difference between the value corresponding to the second signal obtained from the conversion circuit and the value of the first data obtained from the control circuit, and transmitting the difference value to the control circuit. The control circuit has the operation of obtaining the difference value, terminating the operation if the difference value is 0, and proceeding to the fifth step if the difference value is not 0. The fifth step involves the control circuit generating an updated value by adding the difference value to the value of the first signal transmitted previously. The sixth step described above is: The control circuit performs the operation of transmitting the first signal to the first circuit, which has been changed from the value of the first data to the updated value, The operation includes, The operation method of a semiconductor device.

2. In claim 1, The second circuit has a subtractor, The operation method of a semiconductor device.

3. It comprises a control circuit, a first circuit, a second circuit, a first wiring, a first cell, and a conversion circuit. The control circuit is electrically connected to the first circuit and the second circuit. The first circuit is electrically connected to the first wiring, The input terminal of the conversion circuit is electrically connected to the first wiring, The output terminal of the conversion circuit is electrically connected to the second circuit. The first cell is electrically connected to the first wiring, A method for operating a semiconductor device, wherein the first cell has the function of maintaining a potential corresponding to the amount of current flowing in from the first wiring, and the function of flowing a current from the first wiring in an amount corresponding to the maintained potential, It comprises the first to third steps and the fifth to eighth steps, The first step includes the operation of the control circuit transmitting a first signal to the first circuit corresponding to the value of the first data, The second step described above is: The first circuit acquires the first signal, generates a first current in an amount corresponding to the first signal, and outputs the first current to the first wiring; The first current flows from the first wiring to the first cell, causing the first cell to maintain a first potential corresponding to the amount of the first current. The previous third step is, The first cell performs the operation of supplying a second current from the first wiring in an amount corresponding to the first potential, The conversion circuit has the operation of referring to the second current flowing through the first wiring, which is electrically connected to the input terminal of the conversion circuit, and outputting a second signal from the output terminal of the conversion circuit corresponding to the amount of the second current, The seventh step is, The control circuit performs the operation of transmitting a signal to the second circuit corresponding to the value of the first data, The second circuit includes the operation of calculating the difference between a value corresponding to the second signal obtained from the conversion circuit and the value of the first data obtained from the control circuit, and transmitting the difference value to the control circuit. The eighth step described above is: The second circuit has the operation of obtaining a reference value from the control circuit, terminating the operation if the difference value is smaller than the reference value, and proceeding to the fifth step if the difference value is larger than the reference value. The fifth step involves the control circuit generating an updated value by adding the difference value to the value of the first signal transmitted previously. The sixth step described above is: The control circuit performs the operation of transmitting the first signal to the first circuit, which has been changed from the value of the first data to the updated value, The operation includes, The operation method of a semiconductor device.

4. In claim 3, The second circuit includes a subtractor and a comparator. The operation method of a semiconductor device.

5. In any one of claims 1 to 4, The first cell comprises a first transistor, a second transistor, a third transistor, and a capacitor. Either the source or drain of the first transistor is electrically connected to the gate of the second transistor. Either the source or drain of the second transistor is electrically connected to either the source or drain of the third transistor. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The first terminal of the capacitance is electrically connected to either the source or the drain of the first transistor. The first wiring is electrically connected to the other of the source or drain of the first transistor. The operation method of a semiconductor device.

Images