Memory and electronic devices

Abstract

The present invention relates to a memory and electronic device, the memory comprising a plurality of bit line function groups located on a substrate, a plurality of memory cells, a first staircase structure, and a second staircase structure, wherein the plurality of bit line function groups are spaced apart along a first direction perpendicular to the substrate, and each bit line function group includes a first bit line, a second bit line coupled to the first bit line, and a third bit line coupled to the first bit line, the first bit line extending along a second direction parallel to the substrate, the second bit line and the third bit line extending along a third direction parallel to the substrate, the second direction intersects the third direction, the second bit line and the plurality of memory cells are located on one side of the first bit line in the third direction, the third bit line, the first staircase structure, and the second staircase structure are located on the other side of the first bit line in the third direction, and the first staircase structure and the second staircase structure are located on opposite sides of the third bit line in the second direction. The stacked structure within the memory is compact and advantageous for increasing the number of dies that can be cut from a wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular, to a memory and an electronic apparatus. BACKGROUND ART

[0002] With the development of semiconductor technology, processes are shifting from two-dimensional to three-dimensional to further miniaturize the device structure in memories. That is, arranging each memory cell and associated signal lines in a memory in a three-dimensional space has become the main development direction of current memory structure research.

[0003] For example, in some three-dimensional memories, the stacked structure includes vertically stacked memory cells, vertically extending word lines, and horizontally extending and vertically stacked bit lines, and the bit lines are connected to the outside via a stepped structure provided at an end of the stacked structure. For example, conductive steps are provided hierarchically, so that the bit lines can be electrically connected to a circuit structure (for example, a sense amplifier) provided outside the stacked structure via the corresponding conductive steps and contact plugs disposed thereon.

[0004] However, as the storage density increases, it is necessary to continuously increase the number of layers in the stacked structure, which poses a challenge to the arrangement of the stepped structure. SUMMARY OF THE INVENTION

[0005] In a first embodiment according to the embodiments of the present disclosure, a memory is provided, the memory comprising a plurality of bit line function groups located on a substrate, a plurality of memory cells, a first staircase structure, and a second staircase structure. The plurality of bit line function groups are spaced apart along a first direction perpendicular to the substrate, and each bit line function group within the plurality of bit line function groups includes a first bit line, a second bit line coupled to the first bit line, and a third bit line coupled to the first bit line, the first bit line extending along a second direction parallel to the substrate, the second bit line and the third bit line extending along a third direction parallel to the substrate, the second direction intersects the third direction, and the second bit line and the plurality of memory cells extend along the third direction In the first bit line, the third bit line, the first stair structure, and the second stair structure are located on one side of the first bit line in the third direction, and the first and second stair structures are located on opposite sides of the third bit line in the second direction, and the plurality of memory cells are each coupled to the corresponding second bit line, and each stair structure in the first and second stair structures includes a plurality of conductive steps extending along the second direction, each of which conductive steps is coupled to the corresponding third bit line.

[0006] In some embodiments, the first bit line, the second bit line, and the third bit line are each ring-shaped.

[0007] In some embodiments, the first bit line, the second bit line, and the third bit line have the same material composition.

[0008] In some embodiments, the memory further comprises a first isolation column, a second isolation column, and a third isolation column located on the substrate, wherein the first bit line surrounds the first isolation column in a circumferential direction, the second bit line surrounds the second isolation column in a circumferential direction, and the third bit line surrounds the third isolation column in a circumferential direction.

[0009] In some embodiments, the first isolation column, the second isolation column, and the third isolation column have the same material composition.

[0010] In some embodiments, each step structure within the first step structure and the second step structure includes a plurality of conductive step groups, each conductive step group includes at least two conductive steps spaced apart along a first direction perpendicular to the substrate and having different extension lengths, wherein in each conductive step group, the conductive steps with shorter extension lengths are further from the substrate than the conductive steps with longer extension lengths.

[0011] In some embodiments, each step structure within the first step structure and the second step structure includes a first conductive step and a second conductive step, the first conductive step and the second conductive step having substantially the same extending length, the first conductive step being closer to the center of the third bit line than the second conductive step, and the first conductive step being closer to the substrate than the second conductive step.

[0012] In some embodiments, the first stepped structure includes a third conductive step, the second stepped structure includes a fourth conductive step, the orthographic projections of the third and fourth conductive steps onto the substrate are arranged along the second direction, the third and fourth conductive steps have substantially the same extending length, and the third conductive step is further away from the substrate than the fourth conductive step.

[0013] In some embodiments, each conductive step in the first stepped structure is further from the substrate than any conductive step in the second stepped structure.

[0014] In some embodiments, the memory further comprises a plurality of contact plugs positioned one-to-one in correspondence on the conductive step, each of which contact plugs is integrally formed with the corresponding conductive step.

[0015] In some embodiments, the memory cells coupled to each of the second bit lines are provided on opposite sides of each of the second bit lines in the second direction.

[0016] In some embodiments, each memory cell comprises an access transistor and a capacitor, wherein the access transistor is coupled to the corresponding second bit line, and the capacitor is coupled to the access transistor.

[0017] In some embodiments, the access transistor comprises a first gate, a first active layer surrounding the first gate, and a first gate dielectric layer located between the first gate and the first active layer, wherein the first gates facing each other along the first direction are connected to form a word line, the first gate dielectric layers facing each other along the first direction are connected to form a single structure, and the first active layers facing each other along the first direction are spaced apart from each other and each is coupled to the corresponding second bit line.

[0018] In some embodiments, the capacitor comprises a first electrode, a second electrode surrounding the first electrode, and a capacitive dielectric layer located between the first electrode and the second electrode, wherein the first electrodes facing each other along the first direction are connected to form an integral structure, the capacitive dielectric layers facing each other along the first direction are connected to form an integral structure, and the second electrodes facing each other along the first direction are spaced apart from each other and each is coupled to a corresponding access transistor.

[0019] In some embodiments, multiple second bit lines are provided.

[0020] In some embodiments, the memory further comprises a plurality of selection transistors, and in each bit line function group, each of the second bit lines is coupled to the first bit line via one corresponding selection transistor.

[0021] In some embodiments, the selection transistor comprises a second gate, a second active layer surrounding the second gate, and a second gate dielectric layer located between the second gate and the second active layer, wherein the second gates facing each other along the first direction are connected to form a selection control line, the second gate dielectric layers facing each other along the first direction are connected to form a single structure, and the second active layers facing each other along the first direction are spaced apart from each other and coupled to the corresponding first bit line and the corresponding second bit line, respectively.

[0022] A second embodiment according to an embodiment of the present disclosure provides an electronic device comprising a processor and a memory provided in any embodiment of the present disclosure, which is coupled to the processor.

[0023] In the memory provided in the embodiments of this disclosure, the extension length of the second bit line can be set according to the number of memory cells coupled to it, the extension length of the first bit line can be set according to the number of second bit lines coupled to it, and the extension length of the third bit line can be set according to the arrangement of the stepped structure coupled to it. This makes the stacked structure within the memory more compact (i.e., its planar shape has a smaller area rectangular outline), and further improves the yield of memory chips on each wafer (i.e., the number of dies that can be cut from the wafer, DPW: Die Per Wafer). [Brief explanation of the drawing]

[0024] [Figure 1A] This is a schematic diagram showing a partial planar structure of a three-dimensional memory. [Figure 1B] This is a schematic diagram of a cross-section obtained by cutting along the line K1-K2 in Figure 1A. [Figure 2A] This is a schematic diagram showing a partial planar structure of a memory according to some embodiments of the present disclosure. [Figure 2B] This is a schematic diagram of a cross-section obtained by cutting along the line A1-A2 in Figure 2A. [Figure 2C]This is a schematic diagram of a cross-section taken along line B1-B2 of FIG. 2A. [Figure 2D] This is a schematic diagram of a cross-section taken along line C1-C2 of FIG. 2A. [Figure 3] This is a schematic diagram showing the structure of a memory cell according to some embodiments of the present disclosure. [Figure 4] This is a schematic diagram showing a partial planar structure of another memory according to some embodiments of the present disclosure. [Figure 5A] This is a schematic diagram showing partial cross-sectional structures of several stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 5B] This is a schematic diagram showing partial cross-sectional structures of several stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 5C] This is a schematic diagram showing partial cross-sectional structures of several stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 6A] This is a schematic diagram showing partial cross-sectional structures of several other stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 6B] This is a schematic diagram showing partial cross-sectional structures of several other stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 6C] This is a schematic diagram showing partial cross-sectional structures of several other stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 6D] This is a schematic diagram showing partial cross-sectional structures of several other stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 6E] This is a schematic diagram showing partial cross-sectional structures of several other stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 6F] This is a schematic diagram showing partial cross-sectional structures of several other stages in a memory manufacturing process according to some embodiments of the present disclosure. [Figure 7]This block diagram shows the configuration of an electronic device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0025] The technical solutions of this disclosure will be described in more detail below with reference to the drawings and embodiments. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in a variety of ways and should not be limited to the embodiments described herein. Rather, these embodiments are provided to allow for a more complete understanding of this disclosure and to fully convey its scope to those skilled in the art.

[0026] The following paragraphs will provide a more detailed explanation of this disclosure with reference to the drawings. The advantages and features of this disclosure will become clearer based on the following description and claims. It should be noted that the drawings are in a highly simplified form and are not to an exact scale, but are used solely to facilitate a simple and clear explanation of the embodiments of this disclosure.

[0027] For the purposes of understanding, the meanings of "on," "above," and "above" in this disclosure should be interpreted in the broadest possible sense, and the meaning of "on" not only means "on top of" something and without any intervening features or layers (i.e., directly on top of something), but also means "on top of" something and with intervening features or layers.

[0028] In the embodiments of this disclosure, terms such as "first," "second," and "third" are not intended to limit a specific order or sequence, but rather to distinguish similar objects.

[0029] In the embodiments of this disclosure, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend over the entirety of a lower or upper structure, or it may have a smaller extent than the extent of the lower or upper structure. Alternatively, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or it may be positioned between any pair of horizontal planes of the top and bottom surfaces of a continuous structure. A layer may extend along horizontal, vertical, and / or inclined planes. A layer may include multiple sublayers.

[0030] In the embodiments of this disclosure, the term “coupled” means that two (or more) conductive structures are operably connected to one another, and may include, but are not limited to, the following, as practically required: 1) the two conductive structures are directly electrically connected; 2) the two conductive structures are indirectly electrically connected (through another conductive structure); and 3) the two conductive structures are not electrically connected to one another (e.g., an insulating layer is provided between them), but one of the two conductive structures can respond to an electrical signal to control the electrical properties of the other, for example, a gate (or word line) is connected to an active region (or channel region).

[0031] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined in any way without contradiction.

[0032] Figure 1A is a schematic diagram showing the planar structure of a three-dimensional memory, and Figure 1B is a schematic diagram of a cross-section taken along the line K1-K2 in Figure 1A. As shown in Figures 1A and 1B, the three-dimensional memory includes a plurality of layers sequentially stacked along the vertical direction Z, and each layer includes a bit line BL extending along the horizontal direction X and a plurality of memory cells MC coupled to the bit line BL. For example, each memory cell may include a transistor coupled to the bit line BL and a capacitor coupled to the transistor.

[0033] As shown in Figures 1A and 1B, the three-dimensional memory further comprises a plurality of word lines WL extending along the vertical direction Z, each word line WL being coupled to a plurality of vertically stacked memory cells MC. Specifically, each word line WL is coupled to a transistor within the plurality of vertically stacked memory cells MC. As shown in Figures 1A and 1B, the word lines WL and memory cells MC are located on one side (the same side) of the bit line BL in the horizontal direction Y.

[0034] As shown in Figures 1A and 1B, the three-dimensional memory further comprises a staircase structure located on the other side of the bit line BL in the horizontal direction Y, and the staircase structure comprises multiple bit lines of different layers. BL The three-dimensional memory includes a plurality of conductive steps 210 coupled in a one-to-one correspondence. For example, as shown in Figures 1A and 1B, the plurality of conductive steps 210 form two rising steps (the distance from the conductive step 210 to the substrate 100 gradually increases from the edge of the stepped structure toward the center). As shown in Figures 1A and 1B, the three-dimensional memory further includes contact plugs 220 located on each conductive step 210, thereby electrically connecting the bit line BL to a circuit structure (e.g., a sense amplifier) ​​located outside the stacked structure via the conductive steps 210 and the contact plugs 220.

[0035] Figure 1B illustrates the substrate 100, etching stop layer 105, first dielectric layer 110, second dielectric layer 120, and planarization layer 150, and these structures / layers can be found in the relevant descriptions of the embodiments described later.

[0036] In the three-dimensional memory shown in Figures 1A and 1B, considering the limitations of the circuit structure's driving capability, the extension length of the bit line BL is typically set according to the number of memory cells MC coupled to it. On the other hand, since the contact plug 220 is located on the conductive step 210, the area of ​​the conductive step 210 cannot be reduced indefinitely. In other words, once the extension length of the bit line BL is determined, the number of conductive steps 210 in the above-mentioned stepped structure is limited, and the increase in the number of layers of the stacked structure is also limited.

[0037] At least some embodiments of the present disclosure provide a memory comprising a plurality of bit line function groups located on a substrate, a plurality of memory cells, a first stage structure, and a second stage structure. The plurality of bit line function groups are spaced apart along a first direction perpendicular to the substrate, and each bit line function group within the plurality of bit line function groups includes a first bit line, a second bit line coupled to the first bit line, and a third bit line coupled to the first bit line, wherein the first bit line extends along a second direction parallel to the substrate, the second bit line and the third bit line extend along a third direction parallel to the substrate, the second direction intersects the third direction, and the second bit line and the plurality of memory cells extend along the third direction In the first bit line, the third bit line, the first stair structure, and the second stair structure are located on one side of the first bit line in the third direction, and the first and second stair structures are located on opposite sides of the third bit line in the second direction, and the plurality of memory cells are each coupled to the corresponding second bit line, and each stair structure in the first and second stair structures includes a plurality of conductive steps extending along the second direction, each of which conductive steps is coupled to the corresponding third bit line.

[0038] In the memory provided in the embodiments of this disclosure, the extension length of the second bit line can be set according to the number of memory cells coupled to it, the extension length of the first bit line can be set according to the number of second bit lines coupled to it, and the extension length of the third bit line can be set according to the arrangement of the stepped structure coupled to it. This makes the stacked structure within the memory more compact (i.e., its planar shape has a smaller area rectangular outline), and further improves the yield of memory chips on each wafer (i.e., the number of dies that can be cut from the wafer, DPW: Die Per Wafer).

[0039] Figure 2A is a schematic diagram showing a partial planar structure of a memory according to some embodiments of the present disclosure; Figure 2B is a schematic diagram of a cross-section taken along line A1-A2 in Figure 2A; Figure 2C is a schematic diagram of a cross-section taken along line B1-B2 in Figure 2A; and Figure 2D is a schematic diagram of a cross-section taken along line C1-C2 in Figure 2A. For the sake of clarity and brevity, some of the insulating and / or dielectric layers within the memory are omitted in Figure 2A.

[0040] As shown in Figures 2A to 2D, the memory comprises a plurality of bit line function groups BLG located on the substrate 100, a plurality of memory cells MC, a first stage structure SCa, and a second stage structure SCb. The plurality of bit line function groups BLG are spaced apart along a first direction Z perpendicular to the substrate 100, and each bit line function group BLG includes a first bit line BLa, a second bit line BLb coupled to the first bit line BLa, and a third bit line BLc coupled to the first bit line BLa. The first bit line BLa, the second bit line BLb, and the third bit line BLc within each bit line function group BLG are located at the same hierarchical level. The first bit line BLa extends along a second direction X parallel to the substrate 100, and the second bit line BLb and the third bit line BLc extend along a third direction Y parallel to the substrate 100. Both the second direction X and the third direction Y are perpendicular to the first direction Z, and the second direction X intersects the third direction Y. For example, the second direction X is perpendicular to the third direction Y. For example, the orthographic projections of the first bit line BLa in a different bit line function group BLG onto the substrate 100 basically overlap, the orthographic projections of the second bit line BLb in a different bit line function group BLG onto the substrate 100 basically overlap, and the orthographic projections of the third bit line BLc in a different bit line function group BLG onto the substrate 100 basically overlap.

[0041] As shown in Figures 2A to 2D, the second bit line BLb and the multiple memory cells MC are located on one side of the first bit line BLa in the third direction Y, the third bit line BLc, the first step structure SCa, and the second step structure SCb are located on the other side of the first bit line BLa in the third direction Y, and the first step structure SCa and the second step structure SCb are located on both sides of the third bit line BLc in the second direction X.

[0042] As shown in Figures 2A to 2D, multiple memory cells MC are each coupled to their corresponding second bit line BLb, and each step structure within the first step structure SCa and the second step structure SCb includes multiple conductive steps ST extending along the second direction X, with each conductive step ST being coupled to the corresponding third bit line BLc.

[0043] Exemplary, in the embodiments shown in Figures 2A to 2D, the memory comprises a stacked structure having 16 layers (T1 to T16). Understandably, the stacked structure within the memory may have more or fewer layers. For example, the number of layers in the stacked structure within the memory may include, but is not limited to, 32, 64, 128, 256, etc. The arrangement of the conductive steps ST in Figures 2A to 2D will be described below in conjunction with Table 1.

[0044] [Table 1]

[0045] For example, referring to Table 1 and Figures 2A-2D, the first step structure SCa includes a conductive step ST located in the T1-T8 hierarchy, and the second step structure SCb includes a conductive step ST located in the T9-T16 hierarchy. In the table, the natural number i represents a conductive step ST located in the Ti hierarchy, which is coupled to the third bit line BLc located in the same hierarchy (i.e., the Ti hierarchy).

[0046] Table 2 shows alternative arrangements of the conductive step ST in Figures 2A to 2D. The contents of Table 2 can be understood in conjunction with the related explanations in Table 1, and therefore will not be repeated here. It should be understood that, in the embodiments shown in Figures 2A to 2D, the arrangement of the conductive step ST is not limited to those shown in Tables 1 and 2, and may include other suitable arrangements as long as they are easy to manufacture.

[0047] [Table 2]

[0048] [Table 3]

[0049] [Table 4]

[0050] It is understandable that, if the number of layers in the stacked structure within the memory is a different value, the arrangement of conductive steps ST can be set by referring to the arrangement methods in Table 1 or Table 2. Tables 3 and 4 each show 32 arrangement methods for conductive steps. The contents of Tables 3 and 4 can be understood in conjunction with the related explanation in Table 1, and will not be explained again here.

[0051] For example, in some embodiments, the second bit line BLb may be set to multiple values, as shown in Figure 2A. It should be noted that the number of second bit lines BLb and memory cells MC shown in Figure 2A are illustrative and should not be considered as limiting the present disclosure.

[0052] For example, in some embodiments, as shown in Figure 2A, the first bit line BLa, the second bit line BLb, and the third bit line BLc are each ring-shaped. For example, the first bit line BLa may be a closed ring. For example, the second bit line BLb may be a closed ring or an open ring. For example, if the second bit line BLb is an open ring, the opening of the open ring is located at one end of the second bit line BLb away from the first bit line BLa. For example, the third bit line BLc may be a closed ring or an open ring. For example, Third bit line BLc If the ring is not closed, the open ring-shaped opening is located at one end of the third bit line BLc away from the first bit line BLa.

[0053] For example, in some embodiments, the first bit line BLa, the second bit line BLb, and the third bit line BLc have the same material composition. For example, the materials of the first bit line BLa, the second bit line BLb, and the third bit line BLc may include, but are not limited to, titanium nitride and / or tungsten. For example, the first bit line BLa, the second bit line BLb, and the third bit line BLc may be formed simultaneously.

[0054] For example, in some embodiments, as shown in Figures 2A to 2D, the memory further comprises a first isolation column 132, a second isolation column 134, and a third isolation column 136 located on a substrate 100, wherein a first bit line BL surrounds the first isolation column 132 in the circumferential direction, a second bit line BLb surrounds the second isolation column 134 in the circumferential direction, and a third bit line BLc surrounds the third isolation column 136 in the circumferential direction.

[0055] For example, in some embodiments, the first isolation column 132, the second isolation column 134, and the third isolation column 136 have the same material composition. For example, the material of the first isolation column 132, the second isolation column 134, and the third isolation column 136 may include, but are not limited to, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or aluminum oxide. For example, the first isolation column 132, the second isolation column 134, and the third isolation column 136 may be formed simultaneously.

[0056] For example, in some embodiments, each step structure within the first step structure SCa and the second step structure SCb includes a plurality of conductive step groups, each conductive step group is spaced apart along a first direction Z perpendicular to the substrate 100 and includes at least two conductive steps ST having different extension lengths (conductive steps located in the same row in the "First Step Structure SCa" or "Second Step Structure SCb" column in Tables 1 to 4), and in each conductive step group, the conductive step ST with a smaller extension length is further from the substrate 100 than the conductive step ST with a larger extension length. This makes it possible to provide contact plugs CT on both the conductive step ST with a smaller extension length and the conductive step ST with a larger extension length. For example, referring to Figures 2B and 2C, a conductive step ST with a small extension length located at the T1 level and a conductive step ST with a large extension length located at the T2 level constitute one conductive step group, with the former being further from the substrate 100 than the latter. A conductive step ST with a small extension length located at the T3 level and a conductive step ST with a large extension length located at the T4 level also constitute one conductive step group, with the former being further from the substrate 100 than the latter. A conductive step ST with a small extension length located at the T5 level and a conductive step ST located at the T6 level A conductive step ST with a long extension length constitutes a single conductive step group, with the former being further from the substrate 100 than the latter. A conductive step ST with a short extension length located at the T7 layer and a conductive step ST with a long extension length located at the T8 layer constitute a single conductive step group, with the former being further from the substrate 100 than the latter. A conductive step ST with a short extension length located at the T9 layer and a conductive step ST with a long extension length located at the T10 layer constitute a single conductive step group, with the former being further from the substrate 100 than the latter.

[0057] For example, in some embodiments, each step structure within the first step structure SCa and the second step structure SCb includes a first conductive step and a second conductive step, the first and second conductive steps having approximately the same extension length, the first conductive step being closer to the center of the third bit line BLc than the second conductive step, and the first conductive step being closer to the substrate 100 than the second conductive step. Illustratively, referring to Table 1, Figures 2A and 2B, the conductive step ST located in the T5 layer and the conductive step ST located in the T1 layer may be the first conductive step and the second conductive step, respectively, both having approximately the same extension length, the former being closer to the center of the third bit line BLc than the latter, and the former being closer to the substrate 100 than the latter. Alternatively, the conductive step ST located at the T7 level and the conductive step ST located at the T3 level may be designated as the first conductive step and the second conductive step, respectively; or the conductive step ST located at the T6 level and the conductive step ST located at the T2 level may be designated as the first conductive step and the second conductive step, respectively; or the conductive step ST located at the T8 level and the conductive step ST located at the T4 level may be designated as the first conductive step and the second conductive step, respectively.

[0058] For example, in some embodiments, the first step structure SCa includes a third conductive step, the second step structure SCb includes a fourth conductive step, the orthographic projections of the third and fourth conductive steps onto the substrate 100 are aligned along a second direction X, the third and fourth conductive steps have approximately the same extension length, and the third conductive step is further from the substrate than the fourth conductive step. Illustratively, referring to Table 1, Figures 2A and 2C, conductive steps ST located at the T1 level and conductive steps ST located at the T9 level may be the third and fourth conductive steps, respectively, the orthographic projections of the former and latter onto the substrate 100 are aligned along a second direction X, the former and latter have approximately the same extension length, and the former is further from the substrate 100 than the latter, or conductive steps ST located at the T2 level and conductive steps ST located at the T10 level may be the third and fourth conductive steps, respectively.

[0059] For example, in some embodiments, referring to Table 1 (or Tables 2 to 4), Figures 2A and 2C, each conductive step ST in the first step structure SCa is further from the substrate 100 than any conductive step ST in the second step structure SCb.

[0060] Understandably, the first stair structure SCa and the second stair structure SCb are interchangeable.

[0061] For example, in some embodiments, as shown in Figures 2A-2C, the memory further comprises a plurality of contact plugs CT, the plurality of contact plugs CT positioned one-to-one on each conductive step ST. For example, each contact plug CT is integrally formed with the corresponding conductive step ST. For example, the contact plugs CT have the same material composition as the conductive step ST. For example, the contact plugs CT and conductive step ST may contain, but are not limited to, titanium nitride and / or tungsten.

[0062] For example, in some embodiments, as shown in Figures 2A and 2D, memory cells MC coupled to each second bit line BLb are provided on opposite sides of each second bit line BLb in the second direction X. For example, each memory cell MC comprises an access transistor TR and a capacitor CAP, where the access transistor TR is coupled to the corresponding second bit line BLb and the capacitor CAP is coupled to the access transistor TR. It should be noted that the memory cell MC may include, but is not limited to, a DRAM (Dynamic Random Access Memory) memory cell. For example, the memory cell MC may be an FeRAM (Ferroelectric Random Access Memory) memory cell, a PCM (Phase Change Memory) memory cell, an MRAM (Magnetic Random Access Memory) memory cell, etc. In other words, the memory according to the embodiments of this disclosure may be DRAM, FeRAM, PCM, MRAM, etc.

[0063] For example, in some embodiments, as shown in Figures 2A and 2D, the access transistor TR comprises a first gate 143, a first active layer 141 surrounding the first gate 143, and a first gate dielectric layer 142 located between the first gate and the first active layer 141. That is, the access transistor TR may also be a CAA (Channel-All-Around) transistor, where the first gates 143 facing each other along the first direction Z are connected to form an integrated structure (i.e., word line 143), the first gate dielectric layers 142 facing each other along the first direction Z are connected to form an integrated structure, and the first active layers 141 facing each other along the first direction Z are spaced apart from each other and each is coupled to the corresponding second bit line BLb. For example, the material of the first active layer 141 may include, but is not limited to, polysilicon or a metal oxide, for example, the metal oxide may be IGZO (indium gallium zinc oxide). For example, the first gate Dielectric layer The material of 142 may include, but is not limited to, silicon oxide (SiO2) and / or a high-K dielectric. For example, the material of word wire 143 may include, but is not limited to, titanium nitride and / or tungsten.

[0064] For example, in some embodiments, as shown in Figures 2A and 2D, the capacitor CAP comprises a first electrode 147, a second electrode 145 surrounding the first electrode 147, and a capacitive dielectric layer 146 located between the first electrode 147 and the second electrode 145, wherein the first electrode 147, facing each other along the first direction Z, is connected to form an integrated structure (i.e., a common electrode 147), the capacitive dielectric layers 146, facing each other along the first direction Z, are connected to form an integrated structure, and the second electrode 145, facing each other along the first direction Z, are spaced apart from each other and each is coupled to a corresponding access transistor TR. For example, the material of the second electrode 145 may include, but is not limited to, titanium nitride and / or tungsten. For example, the material of the capacitive dielectric layer 146 may include, but is not limited to, silicon oxide (SiO2) and / or a high-K dielectric. For example, the material of the first electrode 147 may include, but is not limited to, titanium nitride and / or tungsten.

[0065] It should be noted that the structures of the memory cell MC (i.e., the access transistor TR and capacitor CAP) shown in Figure 2D are all illustrative. Figure 3 is a schematic diagram showing the structure of a memory cell (including the access transistor and capacitor) according to some embodiments of the present disclosure. For example, as shown in Figure 3, in some embodiments, in the memory transistor TR of the memory cell MC, the partial cross-sectional shape of the first active layer 141 is "C" shaped, the first gate dielectric layer 142 covers the first active layer 141 according to its shape, and the word line 143 includes a branch extending laterally within the "C" shaped opening of the first active layer 141. For example, as shown in Figure 3, in some embodiments, in the capacitor CAP of the memory cell MC, the partial cross-sectional shape of the second electrode 145 is "C" shaped, the capacitive dielectric layer 146 covers the second electrode 145 according to its shape, and the common electrode 147 includes a branch extending laterally within the "C" shaped opening of the second electrode 145.

[0066] Figure 4 is a schematic diagram showing a partial planar structure of another memory according to some embodiments of the present disclosure. For example, in some embodiments, based on the memory shown in Figure 2, the memory shown in Figure 4 may further comprise a plurality of selection transistors T0, and in each bit line function group BLG, each second bit line BLb is coupled to a first bit line BLa via one corresponding selection transistor T0.

[0067] For example, in some embodiments, the structure and material composition of the selection transistor T0 may be the same as that of the access transistor TR. For example, the selection transistor T0 comprises a second gate (see the first gate 143 described above), a second active layer surrounding the second gate (see the first active layer 141 described above), and a second gate dielectric layer located between the second gate and the second active layer (see the first gate dielectric layer 142 described above). That is, the selection transistor T0 may be a CAA (Channel-All-Around) transistor, where the opposing second gates along the first direction Z are connected to form an integrated structure (i.e., a selection control line), the opposing second gate dielectric layers along the first direction Z are connected to form an integrated structure, and the opposing second active layers along the first direction Z are spaced apart from each other and coupled to the corresponding first bit line BLa and the corresponding second bit line BLb, respectively. For example, the selection transistor T0 and the access transistor TR may be formed simultaneously.

[0068] Figures 5A to 5C are schematic diagrams showing partial cross-sectional structures of several stages in the memory manufacturing process according to some embodiments of this disclosure. Below, the manufacturing processes of the bit line function group (BLG) and memory cell (MC) will be briefly described in conjunction with Figures 5A to 5C.

[0069] For example, in some embodiments, the manufacturing process for a bit line functional group BLG may include the following steps: Referring to Figure 5A, an etching stop layer 105, alternately stacked first dielectric layers 110 and second dielectric layers 120, and a mask layer 125 are sequentially formed on a substrate 100, with adjacent first dielectric layers 110 and second dielectric layers 120 forming one layer; then, referring to Figure 5B, an opening pattern is formed on the mask layer 125, and the alternately stacked first dielectric layers 110 and second dielectric layers 120 are etched to form a vertical opening VP, the vertical opening VP exposing the upper surface of the etching stop layer 105; then, referring to Figure 5C, a horizontal opening HP is formed by etching laterally from the vertical opening VP to remove a portion of the second dielectric layer 120 in each layer; and then, referring to the first bit line BLa and first isolation column 132 in Figure 2B, the first bit line BLa is formed within the horizontal opening HP, and the first isolation column 132 fills the vertical opening VP. It is understandable that the formation process of the second bit line BLb and the second isolation pillar 134 is the same as the formation process of the first bit line BLa and the first isolation pillar 132, and the formation process of the third bit line BLc and the third isolation pillar 136 is also the same as the formation process of the first bit line BLa and the first isolation pillar 132, and will not be explained again here. Furthermore, it is understandable that in the process of forming the first bit line BLa, the second bit line BLb, and the third bit line BLc, the three must satisfy corresponding coupling relationships.

[0070] For example, in some embodiments, the manufacturing process for an access transistor TR within a memory cell MC may include the following steps: Referring to Figure 5B, an opening pattern is formed on a mask layer 125; alternating stacked first dielectric layers 110 and second dielectric layers 120 are etched to form a vertical opening VP, the vertical opening VP exposing the upper surface of an etching stop layer 105; then, referring to Figure 5C, a horizontal opening HP is formed by laterally etching from the vertical opening VP to remove a portion of the second dielectric layer 120 of each layer; then, referring to the first active layer 141, first gate dielectric layer 142, and word line WL in Figure 2D or 3, the first active layer 141 is formed within the horizontal opening HP; the first gate dielectric layer 142 covers the first active layer 141 according to its shape; and a word line 143 fills the vertical opening VP. Understandably, if the second bit line BLb is formed before the first active layer 141, the horizontal opening on one side housing the first active layer 141 should expose the sidewall of the second bit line BLb, thereby allowing the later-formed first active layer 141 to couple with the earlier-formed second bit line BLb. Similarly, if the second electrode 145 of the capacitor CAP is formed before the first active layer 141, the horizontal opening on the other side housing the first active layer 141 should expose the sidewall of the second electrode 145, thereby allowing the later-formed first active layer 141 to couple with the earlier-formed second electrode 145. Furthermore, understandably, the formation process of the selection transistor T0 may be the same as the formation process of the access transistor TR, and will not be described again here.

[0071] For example, in some embodiments, the manufacturing process for a capacitor CAP in a memory cell MC may include the following steps: Referring to Figure 5B, an opening pattern is formed on a mask layer 125, and alternating stacked first dielectric layers 110 and second dielectric layers 120 are etched to form a vertical opening VP, the vertical opening VP exposing the upper surface of an etching stop layer 105; then, referring to Figure 5C, a horizontal opening HP is formed by etching laterally from the vertical opening VP to remove a portion of the second dielectric layer 120 of each layer; then, referring to the first active layer 141, the first gate dielectric layer 142, and the word line WL in Figure 2D or 3, a second electrode 145 is formed within the horizontal opening HP, a capacitive dielectric layer 146 is formed to cover the second electrode 145 according to its shape, and a common electrode 147 is formed to fill the vertical opening VP. Understandably, if the first active layer 141 is formed before the second electrode 145, the horizontal opening on one side that accommodates the second electrode 145 should expose the side wall of the first active layer 141, so that the later-formed second electrode 145 can be coupled to the earlier-formed first active layer 141.

[0072] Figures 6A to 6F are schematic diagrams showing partial cross-sectional structures of several other stages in the memory manufacturing process according to some embodiments of this disclosure. Below, the manufacturing processes for the first stage structure SCa and the second stage structure SCb will be briefly described in conjunction with Figures 6A to 6F.

[0073] For example, in some embodiments, the manufacturing process for the first step structure SCa and the second step structure SCb may include the following steps: Referring to Figures 6A and 6B, the alternating stacked first dielectric layers 110 and second dielectric layers 120 are etched to form the first initial step structure and the second initial step structure (the mask layer 125 can then be removed); then, referring to Figures 6C and 6D, a planarization layer 150 is formed to cover the first initial step structure and the second initial step structure, vertical openings VO are formed within the planarization layer 150, the vertical openings VO expose the second dielectric layer 120 at the top of each initial step, then, referring to Figures 6E and 6F, the second dielectric layer 120 at the top of each initial step is etched from the vertical openings VO to form horizontal openings HO, the horizontal openings HO expose the sidewalls of the third bit line BLc, and then, referring to Figures 2 and 2C, a conductive step ST is formed within the horizontal opening HO and a contact plug CT is formed within the vertical opening VO to obtain the first step structure SCa and the second step structure SCb. For example, by depositing a conductive material, a conductive step ST and a contact plug CT can be formed simultaneously.

[0074] For example, in the embodiments of this disclosure, the substrate 100 may include, but is not limited to, a silicon substrate, a silicon-on-insulator substrate, etc. For example, the material of the etching stop layer 105 may include, but is not limited to, silicon carbide (SiC), silicon-carbon-oxygen (SiCO), or silicon-carbon-nitrogen (SiCN), etc. For example, the material of the first dielectric layer 110 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), etc. For example, the material of the second dielectric layer 120 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), etc. For example, the material of the mask layer 125 may include, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), or silicon-carbon-nitrogen (SiCN), etc. For example, the material of the planarization layer 150 may be the same as the material of the first dielectric layer 110, but is not limited to that.

[0075] Understandably, the materials of the etching stop layer 105, the first dielectric layer 110, and the second dielectric layer 120 are usually different from each other, and they typically have a constant etching selectivity ratio. Similarly, the first dielectric layer 110, the second dielectric layer 120, and the mask layer 125 are usually different from each other, and they typically have a constant etching selectivity ratio.

[0076] In the memory provided in the embodiments of this disclosure, the extension length of the second bit line BLb can be set according to the number of memory cells MC coupled to it, the extension length of the first bit line BLa can be set according to the number of second bit lines BLb coupled to it, and the extension length of the third bit line BLc can be set according to the arrangement of the stepped structures SCa and SCb coupled to it. This makes the stacked structure within the memory more compact (i.e., its planar shape has a smaller area rectangular outline), and further improves the yield of memory chips on each wafer (i.e., the number of dies that can be cut from the wafer, DPW: Die Per Wafer).

[0077] At least some embodiments of the present disclosure further provide electronic devices. Figure 7 is a block diagram showing the configuration of an electronic device according to some embodiments of the present disclosure. As shown in Figure 7, the electronic device 1 comprises a coupled processor 20 and memory 10, where the memory 10 is the memory provided in any of the embodiments described above.

[0078] For example, the processor 20 may include, but is not limited to, a central processing unit (CPU) or a graphics processing unit (GPU). The memory 10 may be configured to store data processed by the processor 20 and / or data processed by the processor.

[0079] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart handling devices, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0080] The above describes only embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art could easily conceive of within the technical scope disclosed herein should be included within the scope of protection of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be subject to the scope of protection of the claims.

Claims

1. A memory comprising a plurality of bit line function groups (BLGs) located on a substrate (100), a plurality of memory cells (MCs), a first stage structure (SCa), and a second stage structure (SCb), The plurality of bit line function groups are spaced apart along a first direction (Z) perpendicular to the substrate, and each bit line function group within the plurality of bit line function groups includes a first bit line (BLa), a second bit line (BLb) coupled to the first bit line, and a third bit line (BLc) coupled to the first bit line, the first bit line extending along a second direction (X) parallel to the substrate, the second bit line and the third bit line extending along a third direction (Y) parallel to the substrate, the second direction intersecting the third direction, The second bit line and the plurality of memory cells are located on one side of the first bit line in the third direction, the third bit line, the first stair structure, and the second stair structure are located on the other side of the first bit line in the third direction, and the first stair structure and the second stair structure are located on opposite sides of the third bit line in the second direction. Each of the plurality of memory cells is coupled to the corresponding second bit line, and each of the first and second step structures includes a plurality of conductive steps (STs) extending along the second direction, each of the conductive steps is coupled to the corresponding third bit line. Each of the first bit line, the second bit line, and the third bit line is ring-shaped, The memory further comprises a first isolation column (132), a second isolation column (134), and a third isolation column (136) located on the substrate. The first bit line surrounds the first isolation pillar in the circumferential direction, the second bit line surrounds the second isolation pillar in the circumferential direction, and the third bit line surrounds the third isolation pillar in the circumferential direction. Memory.

2. Each step structure within the first step structure and the second step structure includes a plurality of conductive step groups, each conductive step group includes at least two conductive steps spaced apart along a first direction perpendicular to the substrate and having different extending lengths. In each group of conductive steps, the conductive steps with a smaller extension length are further from the substrate than the conductive steps with a larger extension length. The memory according to claim 1.

3. Each step structure within the first step structure and the second step structure includes a first conductive step and a second conductive step, the first conductive step and the second conductive step having substantially the same extending length, the first conductive step being closer to the center of the third bit line than the second conductive step, and the first conductive step being closer to the substrate than the second conductive step. The memory according to claim 2.

4. The first step structure includes a third conductive step, the second step structure includes a fourth conductive step, the orthographic projections of the third and fourth conductive steps onto the substrate are arranged along the second direction, the third and fourth conductive steps have substantially the same extension length, and the third conductive step is further away from the substrate than the fourth conductive step. The memory according to claim 3.

5. Each conductive step in the first staircase structure is further from the substrate than any conductive step in the second staircase structure. The memory according to claim 4.

6. The aforementioned memory is The system further comprises a plurality of contact plugs (CTs) positioned one-to-one in correspondence on the conductive step, each of which contact plugs is integrally formed with the corresponding conductive step. The memory according to any one of claims 1 to 5.

7. The memory cells coupled to each of the second bit lines are provided on both sides of each of the second bit lines facing each other in the second direction, Each memory cell comprises an access transistor (TR) and a capacitor (CAP), wherein the access transistor is coupled to the corresponding second bit line, and the capacitor is coupled to the access transistor. The access transistor comprises a first gate (143), a first active layer (141) surrounding the first gate, and a first gate dielectric layer (142) located between the first gate and the first active layer. The first gates facing each other along the first direction are connected to form a word line (143), the first gate dielectric layers facing each other along the first direction are connected to form an integral structure, and the first active layers facing each other along the first direction are spaced apart from each other and each is coupled to the corresponding second bit line. The capacitor comprises a first electrode (147), a second electrode (145) surrounding the first electrode, and a capacitive dielectric layer (146) located between the first electrode and the second electrode. The first electrodes, facing each other along the first direction, are connected to form an integrated structure; the capacitive dielectric layers, facing each other along the first direction, are connected to form an integrated structure; and the second electrodes, facing each other along the first direction, are spaced apart from each other and coupled to their respective access transistors. The memory according to claim 6.

8. Multiple second bit lines are provided, The memory further comprises a plurality of selection transistors (T0), and in each bit line function group, each second bit line is coupled to the first bit line via one corresponding selection transistor. The selected transistor comprises a second gate, a second active layer surrounding the second gate, and a second gate dielectric layer located between the second gate and the second active layer. The second gates facing each other along the first direction are connected to form a selection control line, the second gate dielectric layers facing each other along the first direction are connected to form an integrated structure, and the second active layers facing each other along the first direction are spaced apart from each other and coupled to the corresponding first bit line and the corresponding second bit line, The memory according to claim 6.

9. Processor (20) and An electronic device comprising a memory (10) according to any one of claims 1 to 5, wherein the memory (10) is coupled to the processor.

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