Semiconductor device and electronic apparatus

Abstract

Provided is a novel semiconductor device. The semiconductor device comprises an imaging unit and a display unit, wherein the semiconductor device is provided with: a first layer; a second layer disposed on the first layer; and a third layer disposed on the second layer. The first layer comprises a plurality of photoelectric conversion elements. The second layer comprises a plurality of display pixel circuits. The third layer comprises a plurality of display elements. The imaging unit contains the plurality of photoelectric conversion elements. The display unit contains the plurality of display pixel circuits and the plurality of display elements. One of the plurality of display pixel circuits is electrically connected to one of the plurality of display elements.

Description

Semiconductor devices and electronic devices

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0004] In recent years, there has been a demand for higher definition display devices. Devices requiring high-definition display devices include, for example, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR), and these devices have been actively developed in recent years. Display devices used in these devices are required to be compact as well as high-definition.

[0005] Representative examples of the display device include a liquid crystal display device, an organic EL (Electro Luminescence) element, a light-emitting device equipped with a light-emitting element such as a light-emitting diode (LED: Light Emitting Diode), and electronic paper that displays using an electrophoresis method.

[0006] For example, the basic structure of an organic EL element is a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be emitted from the light-emitting organic compound. A display device using such an organic EL element does not require a backlight, which is necessary in liquid crystal display devices and the like, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0007] JP 2002-324673 A

[0008] Small, high-resolution display devices are also used in electronic viewfinders (EVFs) of mirrorless cameras, etc. Mirrorless cameras equipped with EVFs have the advantages of matching the image projected on the imaging unit (image sensor) with the image that is actually captured, and of being able to display necessary information on the display device.

[0009] On the other hand, mirrorless cameras equipped with EVFs generally have the problem that the captured image is displayed on the EVF after the signal is read from the image sensor, which can easily cause a time lag between capture and display (signal delay).In particular, when photographing a moving subject, the timing of the capture can easily be off, making it difficult to achieve an accurate framework.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device or a display device with a small time lag between capturing an image of a subject and displaying the image.An object of one embodiment of the present invention is to provide a miniaturized semiconductor device or a display device.Another object of one embodiment of the present invention is to provide a semiconductor device or a display device with high color reproducibility.Another object of one embodiment of the present invention is to provide a high-definition semiconductor device or a display device.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device or a display device.Another object of one embodiment of the present invention is to provide a semiconductor device or a display device with reduced power consumption.Another object of one embodiment of the present invention is to provide a novel semiconductor device or a display device.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including an imaging unit and a display unit, in which the imaging unit includes a plurality of photoelectric conversion elements arranged in a matrix, the display unit includes a plurality of display pixel circuits arranged in a matrix and a plurality of display elements arranged in a matrix, the plurality of photoelectric conversion elements are provided in a first layer, the plurality of display pixel circuits are provided in a second layer above the first layer, the plurality of display elements are provided in a third layer above the second layer, and one of the plurality of display pixel circuits is electrically connected to one of the plurality of display elements.

[0013] The semiconductor device may have a function of acquiring imaging data using a plurality of photoelectric conversion elements, a function of supplying imaging data of all columns for each row to a display unit, and a function of adjusting a voltage of the imaging data and supplying the adjusted voltage to the display unit.

[0014] The display pixel circuit has a function of controlling the luminance of the display element, for example. Various elements can be used as the display element. For example, an organic EL element can be used as the display element.

[0015] The display pixel circuit may include a transistor having an oxide semiconductor. The first layer and the second layer may be connected via, for example, an adhesive layer and a bump.

[0016] Another aspect of the present invention is an electronic device including the semiconductor device and at least one of an antenna, a battery, and a microphone. Another aspect of the present invention is an electronic device including the semiconductor device and at least one of a mounting portion, a lens, a main body, and a cable, and having a function of acquiring user information through the lens.

[0017] According to one embodiment of the present invention, a semiconductor device or display device with a short time lag between capturing an image of a subject and displaying it can be provided. Alternatively, a miniaturized semiconductor device or display device can be provided. Alternatively, a semiconductor device or display device with high color reproducibility can be provided. Alternatively, a high-definition semiconductor device or display device can be provided. Alternatively, a highly reliable semiconductor device or display device can be provided. Alternatively, one embodiment of the present invention can provide a semiconductor device or display device with reduced power consumption. Alternatively, a novel semiconductor device or display device can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0019] FIGS. 1A and 1B are perspective views of a semiconductor device. FIG. 2 is a perspective view of the semiconductor device. FIG. 3 is a block diagram of the semiconductor device. FIGS. 4A and 4B are diagrams illustrating an example of a circuit configuration of an imaging pixel 12. FIGS. 5A and 5B1 to 5B7 are diagrams illustrating an example of a configuration of a layer 20. FIGS. 6A to 6D are diagrams illustrating an example of a circuit configuration of a display pixel 230. FIGS. 7A to 7D are diagrams illustrating an example of a configuration of a light-emitting element. FIGS. 8A to 8D are diagrams illustrating an example of a configuration of a display device. FIGS. 9A to 9D are diagrams illustrating an example of a configuration of a display device. FIG. 10 is a cross-sectional view illustrating an example of a configuration of a semiconductor device. FIGS. 11A and 11B are diagrams illustrating an example of use of the semiconductor device. FIGS. 12A and 12B are perspective views of the semiconductor device. FIG. 13 is a perspective view of the semiconductor device. FIG. 14 is a cross-sectional view illustrating an example of a configuration of the semiconductor device. FIGS. 15A and 15B are perspective views of the semiconductor device. FIG. 16 is a perspective view of the semiconductor device. FIG. 17A is a diagram illustrating an example of a circuit configuration of a display pixel. FIG. 17B is a diagram illustrating a configuration example of a semiconductor device. FIG. 18 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 19 is a perspective view of a semiconductor device. FIG. 20 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 21 is a perspective view of a semiconductor device. FIG. 22 is a perspective view illustrating a configuration example of a semiconductor device. FIG. 23 is a diagram illustrating a configuration example of a semiconductor device. FIG. 24 is a perspective view illustrating a configuration example of a semiconductor device. FIG. 25 is a diagram illustrating a configuration example of a semiconductor device. FIG. 26 is a diagram illustrating a configuration example of a semiconductor device. FIG. 27 is a perspective view illustrating a configuration example of a semiconductor device. FIG. 28 is a diagram illustrating a configuration example of a semiconductor device. FIG. 29 is a perspective view illustrating a configuration example of a semiconductor device. FIG. 30 is a diagram illustrating a configuration example of a semiconductor device. FIG. 31 is a perspective view illustrating a configuration example of a semiconductor device. FIG. 32 is a diagram illustrating a configuration example of a semiconductor device. FIG. 33 is a diagram illustrating a configuration example of a semiconductor device. FIG. 34 is a diagram illustrating a configuration example of a semiconductor device. FIG. 35 is a diagram illustrating a configuration example of a semiconductor device. FIG. 36A is a top view illustrating a configuration example of a transistor. FIGS. 36B and 36C are cross-sectional views illustrating configuration examples of transistors.Fig. 37A is a diagram explaining classification of IGZO crystal structure. Fig. 37B is a diagram explaining an XRD spectrum of a CAAC-IGZO film. Fig. 37C is a diagram explaining a microelectron beam diffraction pattern of a CAAC-IGZO film. Figs. 38A to 38F are diagrams explaining an example of an electronic device. Figs. 39A to 39F are diagrams explaining an example of an electronic device.

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0021] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0022] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The on and off states of the switch are controlled. In other words, the switch has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.

[0023] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0024] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0025] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0027] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance occurring between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," and the like. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0028] Furthermore, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the transistor structure, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification.

[0029] Furthermore, in this specification and the like, the term "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Furthermore, the term "node" can be rephrased as a terminal, wiring, etc.

[0030] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification, etc. may be omitted in another embodiment, in the claims, etc.

[0031] Furthermore, in this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0032] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] Furthermore, in this specification and the like, the term "overlap" does not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0034] Furthermore, in this specification and the like, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0035] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, depending on the situation, terms such as "film" and "layer" may be replaced with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0036] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0037] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0038] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0040] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0041] In addition, in the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations, etc. may be included.

[0042] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and no distinction is made between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0043] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0044] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described. Note that the semiconductor device according to one embodiment of the present invention has a function of operating as an imaging device and a function of operating as a display device.

[0045] 1 and 2 are perspective views of a semiconductor device 100A according to one embodiment of the present invention. Fig. 1A is a perspective view of the front side of the semiconductor device 100A, and Fig. 1B is a perspective view of the back side of the semiconductor device 100A. In Fig. 2, layers 10 and 20 are shown separated from each other to make the configuration of the semiconductor device 100A easier to understand.

[0046] The semiconductor device 100A includes a layer 10 and a layer 20. The layer 10 and the layer 20 are provided to overlap each other. In FIG. 1 and other figures, the direction in which the layer 10 and the layer 20 overlap is defined as the Z direction.

[0047] The layer 10 includes an imaging section 11, a first driving circuit section 13, a second driving circuit section 14, a readout circuit section 15, and a control circuit section 16. The layer 10 also includes a microlens array including a plurality of microlenses 19, overlapping the imaging section 11. The microlenses 19 are provided on the opposite side of the layer 20 with the layer 10 interposed therebetween. The imaging section 11 also includes a plurality of imaging pixels 12 arranged in a matrix.

[0048] The layer 20 includes a display section 21, a first drive circuit section 231, a second drive circuit section 232, and an input / output terminal section 29. The display section 21 also includes a plurality of display pixels 230 arranged in a matrix. The layer 60 is also provided overlying a plurality of display pixel circuits 431 arranged in a matrix. The layer 60 includes a plurality of display elements 432 arranged in a matrix.

[0049] One display pixel 230 is made up of one display pixel circuit 431 and one display element 432. Therefore, the display unit 21 includes a plurality of display pixels 230 arranged in a matrix.

[0050] Examples of the display element 432 include EL elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), micro LEDs, QLEDs (Quantum-dot Light Emitting Diodes), transistors (transistors that emit light in response to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma display panels (PDPs), display elements using MEMS (microelectromechanical systems), digital micromirror devices (DMDs), DMS (digital micro shutters), IMOD (interferometric modulation) elements, shutter-type MEMS display elements, optical interference-type MEMS display elements, electrowetting elements, piezoelectric ceramic displays, display elements using carbon nanotubes, and the like, which have a display medium whose contrast, brightness, reflectance, transmittance, etc. change due to electrical or magnetic action.

[0051] Layer 10 has a function of converting the subject image projected onto imaging unit 11 into an electrical signal. Layer 20 has a function of displaying an image corresponding to the input electrical signal on display unit 21. In semiconductor device 100A according to one aspect of the present invention, layer 10 and layer 20 are provided overlapping each other, so that the subject image captured by layer 10 can be immediately displayed on display unit 21 provided on layer 20. In other words, the time lag between capturing the subject and displaying the image can be reduced. One aspect of the present invention is particularly effective when capturing a moving subject.

[0052] Furthermore, the semiconductor device 100A is supplied with power, signals required for operation of the imaging unit 11, signals required for operation of the display unit 21, and the like via the input / output terminal unit 29. The semiconductor device 100A can output imaging data (also referred to as "image data") captured on the layer 10 to the outside via the input / output terminal unit 29. The semiconductor device 100A can also display an image on the display unit 21 in accordance with a video signal supplied via the input / output terminal unit 29.

[0053] At least a part of the circuits and the like included in the layer 10 may be provided in the layer 20. At least a part of the circuits and the like included in the layer 20 may be provided in the layer 10.

[0054] 3 shows a block diagram for explaining the configuration of the layer 10. As described above, the layer 10 includes an imaging section 11, a first driving circuit section 13, a second driving circuit section 14, a readout circuit section 15, and a control circuit section 16. The first driving circuit section 13, the second driving circuit section 14, the readout circuit section 15, and the control circuit section 16 may be collectively referred to as a "functional circuit." The functional circuit may be a variety of circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit.

[0055] The transistors used in the imaging unit 11 and functional circuits included in the layer 10 may be n-channel transistors or p-channel transistors. Both n-channel transistors and p-channel transistors may be used. The imaging unit 11 and functional circuits may have a CMOS structure that combines n-channel transistors and p-channel transistors.

[0056] The imaging unit 11 includes imaging pixels 12 arranged in a matrix of m rows and n columns (m and n are each an integer of 1 or greater). The imaging unit 11 is electrically connected to the first drive circuit unit 13 via a plurality of wirings 131. The imaging unit 11 is also electrically connected to the readout circuit unit 15 via a plurality of wirings 132. The readout circuit unit 15 is electrically connected to the second drive circuit unit 14 via a plurality of wirings 133. For example, an imaging pixel 12 arranged in the i-th row (i is any number and is an integer of 1 to m inclusive in the present embodiment) is electrically connected to the first drive circuit unit 13 via the i-th wiring 131. An imaging pixel 12 arranged in the j-th column (j is any number and is an integer of 1 to n inclusive in the present embodiment) is electrically connected to the readout circuit unit 15 via the j-th wiring 132.

[0057] 3, the imaging pixel 12 arranged in the first row and first column is indicated as imaging pixel 12[1,1], the imaging pixel 12 arranged in the mth row and nth column is indicated as imaging pixel 12[m,n], and the imaging pixel 12 arranged in the ith row and jth column is indicated as imaging pixel 12[i,j].

[0058] Note that the wirings connected to one imaging pixel 12 are not limited to the wirings 131 and 132. Wires other than the wirings 131 and 132 may be connected to the imaging pixel 12.

[0059] The pixel density (also referred to as "resolution") of the imaging unit 11 is preferably 100 ppi to 10,000 ppi, and more preferably 1,000 ppi to 10,000 ppi. For example, it may be 2,000 ppi to 6,000 ppi, or 3,000 ppi to 5,000 ppi.

[0060] There is no particular limitation on the aspect ratio of the imaging unit 11. The imaging unit 11 of the semiconductor device 100A can accommodate various aspect ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0061] The diagonal size of the imaging unit 11 may be 0.1 inches or more and 100 inches or less, and may be 100 inches or more.

[0062] The control circuit unit 16 has a function of controlling the operation of the circuits included in the layer 10. The first drive circuit unit 13 has a function of selecting the imaging pixels 12 for each row. The imaging pixels 12 in the row selected by the first drive circuit unit 13 output imaging data to the readout circuit unit 15 via wiring 132.

[0063] The readout circuit unit 15 holds the imaging data supplied from the imaging pixels 12 for each column and performs noise removal processing, etc. As the noise removal processing, for example, CDS (Correlated Double Sampling) processing, etc. The readout circuit unit 15 may also have a function of amplifying the imaging data, an AD conversion function for the imaging data, etc.

[0064] The second drive circuit 14 has a function of sequentially selecting the imaging data held in the readout circuit 15 and outputting the imaging data from the output terminal OUT to the outside.

[0065] 4A is a circuit diagram illustrating an example of the circuit configuration of the imaging pixel 12. The imaging pixel 12 includes a photoelectric conversion device 101 (also referred to as a "photoelectric conversion element" or an "imaging element"), a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 108. Note that the capacitor 108 may not be provided. Note that in this specification and the like, at least one of the above elements excluding the photoelectric conversion device 101 may be referred to as an "imaging pixel circuit."

[0066] One electrode (cathode) of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103. One of the source or drain of the transistor 103 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105.

[0067] Here, a wiring that connects the other of the source and the drain of the transistor 102, one of the source and the drain of the transistor 103, one electrode of the capacitor 108, and the gate of the transistor 104 is referred to as a node FD. The node FD can function as a charge detection portion.

[0068] The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to a wiring 121. The gate of the transistor 102 is electrically connected to a wiring 127. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 104 is electrically connected to a wiring 123. The gate of the transistor 103 is electrically connected to a wiring 126. The gate of the transistor 105 is electrically connected to a wiring 128. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 352.

[0069] The wirings 127, 126, and 128 function as signal lines for controlling the on / off state of each transistor. The wiring 352 functions as an output line.

[0070] 4A, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, and a high potential is supplied to the node FD during reset. Therefore, the wiring 122 has a high potential (a higher potential than the wiring 121).

[0071] 4A shows a configuration in which the cathode of the photoelectric conversion device 101 is electrically connected to the node FD, a configuration in which the anode of the photoelectric conversion device 101 is electrically connected to one of the source and the drain of the transistor 102 may be used. In this case, a low potential is supplied to the node FD during resetting, and therefore the wiring 122 may be set to a low potential (a potential lower than that of the wiring 121).

[0072] The transistor 102 has a function of controlling the potential of the node FD. The transistor 102 is also referred to as a "transfer transistor." The transistor 103 has a function of resetting the potential of the node FD. The transistor 103 is also referred to as a "reset transistor." The transistor 104 functions as a source follower circuit and can output the potential of the node FD to the wiring 352 as image data. The transistor 105 has a function of selecting a pixel from which image data is output. The transistor 104 is also referred to as an "amplification transistor." The transistor 105 is also referred to as a "selection transistor."

[0073] 4B , a plurality of pairs of a photoelectric conversion device 101 and a transistor 102 may be connected to the node FD. The circuit configuration shown in FIG. 4B can reduce the area occupied by each imaging pixel 12. Therefore, the packaging density of the imaging pixels 12 can be increased.

[0074] 4B , a first pair of a photoelectric conversion device 101 and a transistor 102 are shown as a photoelectric conversion device 101_1 and a transistor 102_1. The gate of the transistor 102_1 is electrically connected to a wiring 127_1. A second pair of a photoelectric conversion device 101 and a transistor 102 are shown as a photoelectric conversion device 101_2 and a transistor 102_2. The gate of the transistor 102_2 is electrically connected to a wiring 127_2. A kth pair (k is an integer of 1 or more) of a photoelectric conversion device 101 and a transistor 102 are shown as a photoelectric conversion device 101_k and a transistor 102_k. The gate of the transistor 102_k is electrically connected to a wiring 127_k.

[0075] All of the transistors included in layer 10 can be fabricated in the same process.

[0076] The functional circuits included in the layer 10 do not necessarily have to have all of the configurations shown in the present embodiment, and may have configurations other than these.

[0077] 5A shows a block diagram for explaining the configuration of the layer 20. As described above, the layer 20 includes the display unit 21, the first drive circuit unit 231, and the second drive circuit unit 232.

[0078] As with the layer 10, the first drive circuit section 231, the second drive circuit section 232, etc. provided in the layer 20 may also be collectively referred to as a "functional circuit."

[0079] The circuit included in the first drive circuit unit 231 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 21. Note that some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 21. Note that the circuits included in the first drive circuit unit 231 and the second drive circuit unit 232 may be collectively referred to as a "peripheral drive circuit."

[0080] The peripheral driver circuit can include various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit. The peripheral driver circuit can include a transistor, a capacitor, and the like. The transistors included in the peripheral driver circuit can be formed in the same process as the transistors included in the display pixel 230.

[0081] The transistors used in the display unit 21 and peripheral drive circuits included in the layer 20 may be n-channel transistors or p-channel transistors. Both n-channel and p-channel transistors may be used. The display unit 21 and peripheral drive circuits may have a CMOS structure that combines n-channel and p-channel transistors.

[0082] The layer 20 also includes p (p is an integer greater than or equal to 1) wires 236 that are arranged approximately parallel to one another and whose potential is controlled by a circuit included in the first drive circuit section 231, and q (q is an integer greater than or equal to 1) wires 237 that are arranged approximately parallel to one another and whose potential is controlled by a circuit included in the second drive circuit section 232.

[0083] 5A shows an example in which the wiring 236 and the wiring 237 are connected to the display pixel 230. However, the wiring 236 and the wiring 237 are just an example, and the wirings connected to the display pixel 230 are not limited to the wiring 236 and the wiring 237.

[0084] The display unit 21 includes a plurality of display pixels 230 arranged in a matrix of p rows and q columns. For example, the display pixel 230 arranged in the rth row (r is any number and is an integer of 1 to p in this embodiment and the like) is electrically connected to the first drive circuit unit 231 via the rth wiring 236. The imaging pixel 12 arranged in the sth column (s is any number and is an integer of 1 to q in this embodiment and the like) is electrically connected to the second drive circuit unit 232 via the sth wiring 237.

[0085] 5A, the display pixel 230 arranged in the first row and q column is indicated as display pixel 230[1,q], the display pixel 230 arranged in the pth row and qth column is indicated as display pixel 230[p,q], and the display pixel 230 arranged in the rth row and sth column is indicated as display pixel 230[r,s].

[0086] For example, a transistor having a metal oxide in a channel formation region (hereinafter also referred to as an "OS transistor") may be used as a transistor constituting the display pixel 230, and a transistor having silicon in a channel formation region (hereinafter also referred to as an "Si transistor") may be used as a transistor constituting the peripheral driver circuit. OS transistors have a small source-drain leakage current (also referred to as an "off-state current") in an off state, which allows for reduced power consumption. Furthermore, Si transistors have a higher operating speed than OS transistors, making them suitable for use in the peripheral driver circuit. Note that OS transistors may be used as both the transistors constituting the display pixel 230 and the transistors constituting the peripheral driver circuit. Alternatively, Si transistors may be used as both the transistors constituting the display pixel 230 and the transistors constituting the peripheral driver circuit. Furthermore, Si transistors may be used as the transistors constituting the display pixel 230, and OS transistors may be used as the transistors constituting the peripheral driver circuit.

[0087] Both Si transistors and OS transistors may be used as transistors forming the display pixel 230. Both Si transistors and OS transistors may be used as transistors forming the peripheral driver circuits.

[0088] Examples of materials used for Si transistors include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor having low temperature polysilicon (LTPS) in a semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. An LTPS transistor has high field-effect mobility and favorable frequency characteristics.

[0089] By using Si transistors such as LTPS transistors, circuits that need to be driven at high frequencies (such as source driver circuits) can be built on the same substrate as the display unit, which simplifies the external circuits mounted on the semiconductor device and reduces component and mounting costs.

[0090] An OS transistor has much higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the OS transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0091] The off-state current of the OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ Note that the off-state current of a Si transistor per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) More than 1pA (1×10 −１２ Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0092] A display pixel 230 that controls red light, a display pixel 230 that controls green light, and a display pixel 230 that controls blue light are collectively configured to function as a single pixel 240, and the light emission amount (light emission brightness) of each display pixel 230 is controlled, thereby achieving a full-color display. Thus, each of the three display pixels 230 functions as a subpixel. That is, each of the three subpixels controls the light emission amount of red light, green light, or blue light (see FIG. 5B1). The light colors controlled by each of the three subpixels are not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), and yellow (Y) (see FIG. 5B2).

[0093] Furthermore, the three display pixels 230 constituting one pixel 240 may be arranged in a delta arrangement (see FIG. 5B3). Specifically, the three display pixels 230 constituting one pixel 240 may be arranged so that the lines connecting the center points of each of the three display pixels 230 form a triangle.

[0094] Furthermore, the areas of the three sub-pixels (display pixels 230) do not have to be the same. If the light-emitting efficiency and reliability differ depending on the emitted color, the area of ​​the sub-pixels may be changed for each emitted color (see FIG. 5B4). The sub-pixel arrangement shown in FIG. 5B4 may be referred to as an "S-stripe arrangement."

[0095] Alternatively, four subpixels may be combined to function as one pixel. For example, a subpixel that controls white light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 5B5). Adding a subpixel that controls white light can increase the brightness of the display area. Alternatively, a subpixel that controls yellow light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 5B6). Alternatively, a subpixel that controls white light may be added to three subpixels that control cyan, magenta, and yellow light, respectively (see FIG. 5B7).

[0096] By increasing the number of sub-pixels that function as one pixel and by appropriately combining sub-pixels that control red, green, blue, cyan, magenta, and yellow light, it is possible to improve the reproducibility of intermediate tones, and thus the display quality.

[0097] Furthermore, the semiconductor device of one embodiment of the present invention can reproduce color gamuts of various standards, such as the Phase Alternating Line (PAL) standard and the National Television System Committee (NTSC) standard used in television broadcasting, the standard RGB (sRGB) standard and the Adobe RGB standard widely used in display devices used in electronic devices such as personal computers, digital cameras, and printers, and the ITU-R BT.21 standard used in high definition television (HDTV). It is possible to reproduce the color gamut of standards such as the International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) standard, the Digital Cinema Initiatives P3 (DCI-P3) standard used in digital cinema projection, and the ITU-R BT. 2020 (REC. 2020 (Recommendation 2020)) standard used in UHDTV (Ultra High Definition Television, also known as Super Hi-Vision).

[0098] Furthermore, by arranging the pixels 240 in a 1920 x 1080 matrix, it is possible to realize a display unit 21 capable of full-color display at a resolution of so-called full high-definition (also referred to as "2K resolution," "2K1K," or "2K"). Furthermore, by arranging the pixels 240 in a 3840 x 2160 matrix, it is possible to realize a display unit 21 capable of full-color display at a resolution of so-called ultra high-definition (also referred to as "4K resolution," "4K2K," or "4K"). Furthermore, by arranging the pixels 240 in a 7680 x 4320 matrix, it is possible to realize a display unit 21 capable of full-color display at a resolution of so-called super high-definition (also referred to as "8K resolution," "8K4K," or "8K"). By increasing the number of pixels 240, it is also possible to realize a display unit 21 capable of full-color display at a resolution of 16K or 32K.

[0099] The pixel density of the display unit 21 is preferably 100 ppi to 10,000 ppi, and more preferably 1,000 ppi to 10,000 ppi. For example, it may be 2,000 ppi to 6,000 ppi, or 3,000 ppi to 5,000 ppi. The pixel density of the display unit 21 may be the same as or different from the pixel density of the imaging unit 11.

[0100] There is no particular limitation on the aspect ratio of the display unit 21. The display unit 21 of the semiconductor device 100A can accommodate various aspect ratios, such as 1:1 (square), 4:3, 16:9, and 16:10. The aspect ratio of the display unit 21 may be the same as or different from the aspect ratio of the imaging unit 11.

[0101] The diagonal size of the display unit 21 may be 0.1 inches or more and 100 inches or less, and may be 100 inches or more. The diagonal size of the display unit 21 may be the same as or different from the diagonal size of the imaging unit 11.

[0102] When the semiconductor device 100A is used as an xR display device, the diagonal size of the display unit 21 can be set to 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display unit 21 may be set to 1.5 inches or close to 1.5 inches. Setting the diagonal size of the display unit 21 to 2.0 inches or less, preferably close to 1.5 inches, enables the exposure process to be performed in an exposure device (typically a scanner device) to be completed in one step, thereby improving the productivity of the manufacturing process.

[0103] Furthermore, the semiconductor device of one embodiment of the present invention can vary the refresh rate of the display portion 21. For example, the refresh rate can be adjusted (for example, adjusted within a range of 0.01 Hz to 240 Hz) depending on content displayed on the display portion 21 to reduce power consumption. Furthermore, driving that reduces the power consumption of the display portion 21 by lowering the refresh rate may be referred to as idling stop (IDS) driving.

[0104] The display unit 21 may also be provided with a touch sensor or a near-touch sensor. The drive frequency of the touch sensor or the near-touch sensor may be changed depending on the refresh rate. For example, if the refresh rate of the display unit 21 is 120 Hz, the drive frequency of the touch sensor or the near-touch sensor may be configured to be higher than 120 Hz (typically 240 Hz). This configuration enables low power consumption and an increased response speed of the touch sensor or the near-touch sensor.

[0105] Here, a touch sensor or non-contact sensor is a sensor that has the function of detecting the proximity or contact of an object (such as a finger, hand, or pen). A touch sensor can detect an object when the object directly contacts the sensor. A non-contact sensor can detect an object even if the object does not directly contact the sensor. For example, a configuration in which the sensor can detect an object when the distance between the semiconductor device (or display unit 21) and the object is in the range of 0.1 mm to 300 mm, preferably 3 mm to 50 mm. This configuration enables the semiconductor device to be operated without the object directly touching it, in other words, the semiconductor device can be operated in a non-contact (touchless) manner. This configuration reduces the risk of the semiconductor device being soiled or scratched, or enables the semiconductor device to be operated without the object directly touching the semiconductor device with dirt (e.g., dust, viruses, etc.) attached thereto.

[0106] The non-contact sensor function can also be called a hover sensor function, a hover-touch sensor function, a near-touch sensor function, a touchless sensor function, etc. The touch sensor function can also be called a direct touch sensor function, etc.

[0107] 6A is a diagram showing an example of a circuit configuration of the display pixel 230. The display pixel 230 includes a display pixel circuit 431 and a display element 432.

[0108] Therefore, each wiring 236 is electrically connected to q display pixel circuits 431 arranged in any row among the display pixel circuits 431 arranged in p rows and q columns in the display unit 21. Furthermore, each wiring 237 is electrically connected to p display pixel circuits 431 arranged in any column among the display pixel circuits 431 arranged in p rows and q columns.

[0109] The display pixel circuit 431 includes a transistor 436, a capacitor 433, a transistor 251, and a transistor 434. The display pixel circuit 431 is electrically connected to a display element 432.

[0110] One of the source electrode and the drain electrode of the transistor 436 is electrically connected to a wiring (hereinafter referred to as a signal line DL) to which a data signal (also referred to as a "video signal") is applied. Furthermore, a gate electrode of the transistor 436 is electrically connected to a wiring (hereinafter referred to as a scan line GL) to which a gate signal is applied. The signal line DL and the scan line GL correspond to the wiring 237 and the wiring 236, respectively. The transistor 436 has a function of controlling writing of the data signal to the node 435.

[0111] One of a pair of electrodes of the capacitor 433 is electrically connected to a node 435, and the other is electrically connected to a node 437. The other of the source electrode and the drain electrode of the transistor 436 is electrically connected to the node 435.

[0112] The capacitor 433 functions as a storage capacitor for holding a data signal written to the node 435 .

[0113] One of a source electrode and a drain electrode of the transistor 251 is electrically connected to the potential supply line VL_a, and the other is electrically connected to a node 437. Furthermore, a gate electrode of the transistor 251 is electrically connected to a node 435.

[0114] One of a source electrode and a drain electrode of the transistor 434 is electrically connected to the potential supply line V0, and the other is electrically connected to a node 437. Furthermore, a gate electrode of the transistor 434 is electrically connected to the scan line GL.

[0115] One of the anode and the cathode of the display element 432 is electrically connected to the potential supply line VL_b, and the other is electrically connected to a node 437 .

[0116] As the display element 432, for example, a light-emitting element (also called a "light-emitting device") such as an organic electroluminescence element (also called an "organic EL element") can be used. However, the display element 432 is not limited to this, and for example, an inorganic EL element made of an inorganic material may also be used. Note that "organic EL elements" and "inorganic EL elements" may be collectively referred to as "EL elements."

[0117] The luminescent color of the EL element can be white, red, green, blue, cyan, magenta, yellow, or the like, depending on the material that constitutes the EL element.

[0118] There are two methods for achieving color display: one is to combine a display element 432 that emits white light with a colored layer, and the other is to provide a display element 432 that emits a different light color for each pixel. The former method has higher productivity than the latter method. On the other hand, the latter method requires the production of a separate display element 432 for each pixel, making it less productive than the former method. However, the latter method can produce an emitted light color with higher color purity than the former method. In addition to the latter method, the color purity can be further improved by providing a microcavity structure to the display element 432.

[0119] Either a low molecular weight compound or a high molecular weight compound, or an inorganic compound, can be used for the display element 432. The layers constituting the display element 432 can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

[0120] The display element 432 may include an inorganic compound such as quantum dots. For example, quantum dots can be used in a light-emitting layer to function as a light-emitting material.

[0121] Note that, for example, a relatively high potential or a relatively low potential can be used as the power supply potential. The high potential side power supply potential is called a high power supply potential (also called "VDD"), and the low potential side power supply potential is called a low power supply potential (also called "VSS"). Also, the ground potential can be used as the high power supply potential or the low power supply potential. For example, when the high power supply potential is the ground potential, the low power supply potential is a potential lower than the ground potential, and when the low power supply potential is the ground potential, the high power supply potential is a potential higher than the ground potential.

[0122] For example, a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other.

[0123] In the layer 20 having the display pixel circuits 431 , the display pixel circuits 431 in each row are sequentially selected by a circuit included in the peripheral driver circuit, and the transistors 436 and 434 are turned on to write a data signal to the node 435 .

[0124] The display pixel circuit 431, to which a data signal is written to the node 435, is put into a holding state by turning off the transistor 436 and the transistor 434. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 251 is controlled in accordance with the potential of the data signal written to the node 435, and the display element 432 emits light with a luminance corresponding to the amount of current. By performing this process sequentially for each row, an image can be displayed. The transistor 251 is also called a "driving transistor."

[0125] Furthermore, to increase the light emission luminance of the light-emitting device included in the display pixel 230, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the driving transistor included in the display pixel circuit 431. Since an OS transistor has a higher source-drain withstand voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as the driving transistor included in the display pixel circuit 431, it is possible to increase the amount of current flowing through the light-emitting device and increase the light emission luminance of the light-emitting device.

[0126] Furthermore, when the transistor operates in the saturation region, the change in source-drain current of an OS transistor is smaller than that of a Si transistor in response to a change in gate-source voltage. Therefore, by using an OS transistor as the driving transistor included in the display pixel circuit 431, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the display pixel 230.

[0127] Furthermore, in terms of the saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, for example, even when the current-voltage characteristics of a light-emitting device containing an EL material vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0128] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0129] Fig. 6B shows a modified circuit configuration of the display pixel 230 shown in Fig. 6A. In the circuit configuration shown in Fig. 6B, the gate electrode of the transistor 436 is electrically connected to a line (hereinafter referred to as a scanning line GL1) to which a first scanning signal is applied, and the gate electrode of the transistor 434 is electrically connected to a line (hereinafter referred to as a scanning line GL2) to which a second scanning signal is applied.

[0130] 6B includes a transistor 438 in addition to the circuit configuration shown in Fig. 6A. One of a source electrode and a drain electrode of the transistor 438 is electrically connected to a potential supply line V0, and the other is electrically connected to a node 435. Furthermore, a gate electrode of the transistor 438 is electrically connected to a line to which a third scan signal is supplied (hereinafter referred to as a scan line GL3).

[0131] The scanning line GL1 corresponds to the wiring 236 shown in Fig. 5A. Although wiring corresponding to the scanning line GL2 and the scanning line GL3 is not shown in Fig. 5A, the scanning line GL2 and the scanning line GL3 are electrically connected to the first drive circuit unit 231.

[0132] For example, when the display pixel 230 is to be displayed in black, both the transistor 434 and the transistor 438 are turned on. Then, the potentials of the source electrode and gate electrode of the transistor 251 become equal. Therefore, the gate voltage of the transistor 251 becomes 0 V, and the current flowing to the display element 432 can be cut off.

[0133] Some or all of the transistors included in the display pixel circuit 431 may be transistors having back gates. In the circuit configuration shown in FIG. 6B , transistors having back gates are used. For example, the gate and back gate of each of the transistors 434, 436, and 438 are electrically connected to each other. In addition, the back gate of the transistor 251 shown in FIG. 6B is electrically connected to the node 437.

[0134] Figure 6C shows a modified example of the circuit configuration of the display pixel 230 shown in Figure 6A. The circuit configuration shown in Figure 6C has a configuration in which the transistor 434 and the potential supply line V0 are removed from the circuit configuration shown in Figure 6A. The other components can be understood by referring to the description of the circuit configuration shown in Figure 6A. Therefore, in order to reduce repetition of the description, a detailed description of the circuit configuration shown in Figure 6C will be omitted.

[0135] As described above, some or all of the transistors included in the display pixel circuit 431 may be transistors having back gates. For example, as shown in FIG. 6D , a transistor having a back gate may be used as the transistor 436, and the back gate and the gate may be electrically connected. Alternatively, as shown in FIG. 6D , a transistor having a back gate may be used as the transistor 251, and the back gate may be electrically connected to either the source or the drain.

[0136] <Structure Example of Light-Emitting Element> A light-emitting element that can be used for a semiconductor device according to one embodiment of the present invention will be described. The light-emitting element can be used for the display element 432.

[0137] 7A , the light-emitting element 61 includes an EL layer 172 between a pair of electrodes (conductive layers 171 and 173). The EL layer 172 can be formed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0138] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 7A is referred to as a single structure in this specification and the like.

[0139] 7B shows a modified example of the EL layer 172 included in the light-emitting element 61 shown in Fig. 7A. Specifically, the light-emitting element 61 shown in Fig. 7B includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 173 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 173 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductive layer 171 is a cathode and the conductive layer 173 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. With such a layer structure, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0140] Note that a structure in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 7C is also an example of a single structure.

[0141] 7D , a configuration in which a plurality of light-emitting units (EL layers 172 a and 172 b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure or a stack structure in this specification and elsewhere. Note that the tandem structure makes it possible to realize a light-emitting element capable of emitting light with high brightness.

[0142] Furthermore, when the light-emitting element 61 has a tandem structure as shown in FIG. 7D , the EL layer 172 a and the EL layer 172 b may emit the same light. For example, the EL layer 172 a and the EL layer 172 b may both emit green light. When the display unit 21 includes three subpixels, R, G, and B, each of which has a light-emitting element, the light-emitting elements of the subpixels may be arranged in a tandem structure. Specifically, the EL layer 172 a and the EL layer 172 b of the R subpixel each contain a material capable of emitting red light, the EL layer 172 a and the EL layer 172 b of the G subpixel each contain a material capable of emitting green light, and the EL layer 172 a and the EL layer 172 b of the B subpixel each contain a material capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of the same material. By making the EL layers 172a and 172b emit light of the same color, the current density per unit of emitted light luminance can be reduced, thereby improving the reliability of the light-emitting element 61.

[0143] The light-emitting color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 172. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0144] The light-emitting layer may contain two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. It is preferable that a light-emitting element that emits white light has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. When white light is obtained using two types of light-emitting materials, light-emitting materials may be selected such that the emission colors of the respective light-emitting materials are in a complementary color relationship. Furthermore, for example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary colors, a light-emitting element that emits white light as a whole can be obtained. The same applies to a light-emitting element that has three or more light-emitting layers.

[0145] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0146] Examples of the light-emitting substance include a fluorescent substance (fluorescent material), a phosphorescent substance (phosphorescent material), an inorganic compound (such as a quantum dot material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). Note that, as the TADF material, a material that is in thermal equilibrium between a singlet excited state and a triplet excited state may be used. TADF materials have a long emission lifetime (excitation lifetime), and therefore can suppress a decrease in efficiency in a high-brightness region of a light-emitting element.

[0147] <Method for Forming Light-Emitting Element> A method for forming a light-emitting element 61 that can be used as the display element 432 will be described below.

[0148] FIG. 8A shows a schematic top view of a light-emitting element 61. In FIG. 8A and other figures, the light-emitting element 61 that exhibits red is designated as light-emitting element 61R, the light-emitting element 61 that exhibits green is designated as light-emitting element 61G, and the light-emitting element 61 that exhibits blue is designated as light-emitting element 61B. In FIG. 8A , the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to simplify the distinction between the light-emitting elements. The configuration of the light-emitting element 61 shown in FIG. 8A may be referred to as an SBS (Side By Side) structure. Furthermore, the configuration shown in FIG. 8A illustrates a configuration having three colors, red (R), green (G), and blue (B), but is not limited thereto. For example, a configuration having four or more colors may also be used.

[0149] The light-emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 8A shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement of the light-emitting elements is not limited to this, and arrangements such as a delta arrangement or a zigzag arrangement may also be used, or a pentile arrangement may also be used.

[0150] As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, it is preferable to use an organic EL device such as an OLED (organic light-emitting diode) or a QOLED (quantum-dot organic light-emitting diode). Examples of the light-emitting material contained in the light-emitting element include a fluorescent material, a phosphorescent material, an inorganic compound (such as a quantum dot material), and a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material).

[0151] 8B is a schematic cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 8A . FIG. 8B shows cross sections of the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulating layer 363 and include a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The insulating layer 363 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulating layer 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0152] The light-emitting element 61R has an EL layer 172R between a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having an intensity at least in the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having an intensity at least in the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having an intensity at least in the blue wavelength range.

[0153] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0154] The conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element. The conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-reflective, a bottom-emission display device can be obtained. Conversely, by making the conductive layer 171 functioning as a pixel electrode reflective and the conductive layer 173 functioning as a common electrode light-transmitting, a top-emission display device can be obtained. Note that by making both the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0155] An insulating layer 272 is provided to cover an end portion of the conductive layer 171 functioning as a pixel electrode. The end portion of the insulating layer 272 preferably has a tapered shape. The insulating layer 272 can be formed using a material similar to that of the insulating layer 363.

[0156] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the top surface of the conductive layer 171 that functions as a pixel electrode, and a region in contact with the surface of the insulating layer 272. Ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulating layer 272.

[0157] As shown in Figure 8B, a gap is provided between the EL layers of the light-emitting elements that emit two different colors. In this manner, it is preferable that the EL layers 172R, 172G, and 172B are not in contact with each other. This can effectively prevent current from flowing through two adjacent EL layers, which can cause unintended light emission (also known as crosstalk). This can improve contrast and realize a display device with high display quality.

[0158] The EL layer 172R, the EL layer 172G, and the EL layer 172B can be separately formed by a vacuum deposition method using a shadow mask such as a metal mask. Alternatively, they may be separately formed by a photolithography method. By using the photolithography method, it is possible to realize a high-definition display device that is difficult to achieve when using a metal mask.

[0159] In this specification and the like, a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification and the like, a device fabricated using an FMM may be referred to as a device with an FMM structure. In this specification and the like, a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because a display device with an MML structure is fabricated without using a metal mask, it has a higher degree of design freedom in terms of pixel arrangement, pixel shape, and the like than a display device with an FMM structure or an MM structure.

[0160] In the manufacturing method of a display device with an MML structure, the island-shaped EL layer is not formed by a metal mask pattern, but is formed by forming the EL layer on the entire surface and then processing it. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the EL layer can be made separately for each color, it is possible to realize a display device with extremely vivid images, high contrast, and high display quality. Furthermore, by providing a sacrificial layer on the EL layer, damage to the EL layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting device.

[0161] When a display device has a fine metal mask (FMM) structure, there may be limitations on the pixel arrangement, etc. The FMM structure will now be described.

[0162] To fabricate an FMM structure, a metal mask (also referred to as an FMM) with openings is set opposite the substrate so that the EL material can be deposited in the desired area during EL deposition. Then, EL deposition is performed through the FMM, depositing the EL material in the desired area. As the substrate size increases during EL deposition, the FMM size and weight also increase. Furthermore, heat and other factors may be applied to the FMM during EL deposition, which may cause deformation of the FMM. Alternatively, a method may be used in which a certain tension is applied to the FMM during EL deposition, so the weight and strength of the FMM are important parameters.

[0163] Therefore, when designing the pixel arrangement of a device with an FMM structure, the above parameters must be taken into consideration and certain limitations must be considered. On the other hand, in a display device according to one embodiment of the present invention, since it is manufactured using an MML structure, it has an excellent effect of providing a higher degree of freedom in the pixel arrangement configuration compared to an FMM structure. Note that this configuration is highly compatible with, for example, flexible devices, and various circuit arrangements can be used for either or both of the pixels and the drive circuit.

[0164] In addition, a protective layer 271 is provided on the conductive layer 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0165] The protective layer 271 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide or nitride films such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used for the protective layer 271. The protective layer 271 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or sputtering. While the protective layer 271 includes an inorganic insulating film, the present invention is not limited to this. For example, the protective layer 271 may have a stacked structure of an inorganic insulating film and an organic insulating film.

[0166] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0167] When indium gallium zinc oxide is used as the protective layer 271, it can be processed by wet etching or dry etching. For example, when IGZO is used as the protective layer 271, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as a mixed acid aluminum etching solution)) can be used. Note that the mixed acid aluminum etching solution can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water of approximately 53.3:6.7:3.3:36.7.

[0168] 8C shows a different example from the above. Specifically, Fig. 8C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.

[0169] The EL layer 172W may be configured, for example, by stacking two light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between the light-emitting layers. Alternatively, the EL layer 172W may have three or more light-emitting layers.

[0170] 8C shows three light-emitting elements 61W lined up. A colored layer 264R is provided on the top of the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.

[0171] Here, the EL layer 172W and the conductive layer 173 functioning as a common electrode are separated between two adjacent light-emitting elements 61W. This prevents unintended light emission due to current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer in which a charge generation layer is provided between two light-emitting layers is used as the EL layer 172W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0172] The EL layer 172W and the conductive layer 173 functioning as a common electrode are preferably separated by photolithography, which allows the distance between light-emitting elements to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0173] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductive layer 171 functioning as a pixel electrode and the insulating layer 363 .

[0174] FIG. 8D illustrates an example different from the above. Specifically, FIG. 8D illustrates a structure in which an insulating layer 272 covering an edge of the conductive layer 171 is not provided between the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. In other words, no insulator is provided between the conductive layer 171 and the EL layer 172. With this structure, light from the EL layer can be efficiently extracted, thereby significantly reducing viewing angle dependency. For example, in the display device of one embodiment of the present invention, the viewing angle (the maximum angle at which a certain contrast ratio is maintained when the screen is viewed from an oblique direction) can be set to 100° or more and less than 180°, preferably 150° or more and 170° or less. Note that the above viewing angle can be applied to both the vertical and horizontal directions. The display device of one embodiment of the present invention reduces viewing angle dependency and improves image visibility.

[0175] Furthermore, by not providing the insulating layer 272, a display device with a high aperture ratio can be obtained. Furthermore, the protective layer 271 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. This configuration can suppress impurities (typically, water) that may enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. Furthermore, in the configuration shown in FIG. 8D , the top surfaces of the conductive layer 171, the EL layer 172R, and the conductive layer 173 generally coincide with each other. This structure can be formed simultaneously using a resist mask or the like after the conductive layer 171, the EL layer 172R, and the conductive layer 173 are formed. This process can also be called self-aligned patterning, since the EL layer 172R and the conductive layer 173 are processed using the conductive layer 173 as a mask. While the EL layer 172R has been described here, the EL layer 172G and the EL layer 172B can also be similarly configured.

[0176] 8D shows a structure in which a protective layer 273 is further provided on the protective layer 271. For example, the protective layer 271 may be formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 273 may be formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 271, thereby providing a region 275 between the protective layer 271 and the protective layer 273. In other words, the region 275 is located between the EL layer 172R and the EL layer 172G, and between the EL layer 172G and the EL layer 172B.

[0177] The region 275 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The region 275 may also contain, for example, a gas used when forming the protective layer 273. For example, when the protective layer 273 is formed by sputtering, the region 275 may contain one or more of the above Group 18 elements. When the region 275 contains a gas, the gas can be identified by gas chromatography or the like. When the protective layer 273 is formed by sputtering, the gas used during sputtering may also be contained in the protective layer 273. In this case, elements such as argon may be detected when the protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like.

[0178] Furthermore, if the refractive index of region 275 is lower than the refractive index of protective layer 271, light emitted from EL layer 172R, EL layer 172G, or EL layer 172B is reflected at the interface between protective layer 271 and region 275. This may prevent light emitted from EL layer 172R, EL layer 172G, or EL layer 172B from entering adjacent pixels. This prevents light of different colors from being mixed in with neighboring pixels, thereby improving the display quality of the display device.

[0179] 8D , the area between light-emitting element 61R and light-emitting element 61G or the area between light-emitting element 61G and light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of EL layer 172R and the side surface of EL layer 172G or the distance between the side surface of EL layer 172G and the side surface of EL layer 172B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0180] Furthermore, for example, when the region 275 contains gas, it is possible to isolate the light emitting elements while suppressing color mixing or crosstalk of light from each light emitting element.

[0181] Alternatively, the region 275 may be filled with a filler. Examples of the filler include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Alternatively, a photosensitive resin (e.g., a resist material) may be used as the filler. The photosensitive resin used as the filler may be either positive or negative.

[0182] By using a photosensitive resin as the filler, the region 275 can be filled simply by the steps of exposure and development. Alternatively, the region 275 may be filled using a negative photosensitive resin. It is also preferable to use a material that absorbs visible light as the filler. Filling the region 275 with a material that absorbs visible light allows the region 275 to absorb light emitted from the EL layer, thereby suppressing light (stray light) that may leak into an adjacent EL layer. Therefore, a display device with high display quality can be provided.

[0183] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0184] FIG. 9A shows a different example from the above. Specifically, the configuration shown in FIG. 9A differs from the configuration shown in FIG. 8D in the configuration of the insulating layer 363. The insulating layer 363 has a recess formed by partially removing a portion of its upper surface during processing of the light-emitting elements 61R, 61G, and 61B. A protective layer 271 is formed in the recess. In other words, the insulating layer 363 has a region where the lower surface of the protective layer 271 is located lower than the lower surface of the conductive layer 171 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the light-emitting elements 61R, 61G, and 61B from below can be suitably suppressed. The recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 61R, 61G, and 61B are removed by wet etching or the like during processing. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 271, thereby achieving a highly reliable display device.

[0185] FIG. 9B also shows a different example. Specifically, the configuration shown in FIG. 9B includes an insulating layer 276 and a microlens array 277 in addition to the configuration shown in FIG. 9A . The insulating layer 276 functions as an adhesive layer. When the refractive index of the insulating layer 276 is lower than that of the microlens array 277, the microlens array 277 can focus the light emitted from the light-emitting elements 61R, 61G, and 61B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a bright image to be viewed when the user views the display surface from directly in front of the display surface. The insulating layer 276 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0186] FIG. 9C also shows an example different from the above. Specifically, the configuration shown in FIG. 9C has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 9A. An insulating layer 276 is provided above the three light-emitting elements 61W, and coloring layers 264R, 264G, and 264B are provided above the insulating layer 276. Specifically, a coloring layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a coloring layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a coloring layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the display device to display a color image. The configuration shown in FIG. 9C is also a modified example of the configuration shown in FIG. 8C. Note that the coloring layers are sometimes called "color filters."

[0187] 9C can be configured as a single structure or a tandem structure capable of emitting white light, as described above. The tandem structure is preferable because it can provide high-luminance light emission.

[0188] Furthermore, by combining the above-mentioned structure capable of emitting white light (either a single structure or a tandem structure, or both), a color filter, and the MML structure of one embodiment of the present invention, a display device having a high contrast ratio can be obtained.

[0189] 9D shows an example different from the above. Specifically, in the configuration shown in FIG. 9D, a protective layer 271 is provided adjacent to the side surfaces of the conductive layer 171 and the EL layer 172. The conductive layer 173 is provided as a continuous layer common to each light-emitting element. In the configuration shown in FIG. 9D, it is preferable that the region 275 is filled with a filler material.

[0190] The color purity of the emitted color can be increased by providing a micro-optical resonator (microcavity) structure to the light-emitting element 61. To provide the light-emitting element 61 with a microcavity structure, the product (optical path length) of the distance d between the conductive layer 171 and the conductive layer 173 and the refractive index n of the EL layer 172 should be configured to be m times half the wavelength λ (m is an integer of 1 or greater). The distance d can be calculated using Equation 1.

[0191] d = m × λ / (2 × n)... Equation 1.

[0192] According to Equation 1, the distance d of the light-emitting element 61 having the microcavity structure is determined according to the wavelength (emission color) of the emitted light. The distance d corresponds to the thickness of the EL layer 172. Therefore, the EL layer 172G may be provided thicker than the EL layer 172B, and the EL layer 172R may be provided thicker than the EL layer 172G.

[0193] Strictly speaking, the distance d is the distance from the reflective region of the conductive layer 171, which functions as a reflective electrode, to the reflective region of the conductive layer 173, which functions as a semi-transmissive and semi-reflective electrode. For example, if the conductive layer 171 is a laminate of silver and ITO, which is a transparent conductive film, and the ITO is on the EL layer 172 side, the distance d can be set according to the emitted color by adjusting the film thickness of the ITO. In other words, even if the thicknesses of the EL layers 172R, 172G, and 172B are the same, the distance d appropriate for the emitted color can be obtained by changing the thickness of the ITO.

[0194] However, it may be difficult to precisely determine the positions of the reflective regions in the conductive layers 171 and 173. In this case, it is assumed that the microcavity effect can be fully obtained by assuming that any position on the conductive layers 171 and 173 is the reflective region.

[0195] The light-emitting element 61 is composed of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. In order to increase the light extraction efficiency in the microcavity structure, it is preferable to set the optical distance from the conductive layer 171, which functions as a reflective electrode, to the light-emitting layer to an odd multiple of λ / 4. To achieve this optical distance, it is preferable to appropriately adjust the thickness of each layer that constitutes the light-emitting element 61.

[0196] Furthermore, when light is emitted from the conductive layer 173 side, it is preferable that the reflectance of the conductive layer 173 is higher than the transmittance. The light transmittance of the conductive layer 173 is preferably 2% to 50%, more preferably 2% to 30%, and even more preferably 2% to 10%. By reducing the transmittance of the conductive layer 173 (increasing the reflectance), the effect of the microcavity can be enhanced.

[0197] <Example of Stacked Structure> Next, an example of the stacked structure of the semiconductor device 100A will be described with reference to a cross-sectional view.

[0198] 10 is a cross-sectional view of a portion of the semiconductor device 100A. The semiconductor device 100A has a bonding surface between the layer 10 and the layer 20. The layer 10 includes a light-shielding layer 252, an optical conversion layer 250 (color filter), a microlens 19, a photoelectric conversion device 101, an insulating layer 241, an insulating layer 242, an insulating layer 245, an insulating layer 246, an insulating layer 247, and an insulating layer 249. A conductive layer 248 is embedded in the insulating layer 249. The height of the top surface of the conductive layer 248 and the height of the top surface of the insulating layer 249 can be made approximately the same.

[0199] The photoelectric conversion device 101 is a pn junction photodiode formed on a silicon substrate, and has a p-type region 243 and an n-type region 244. The photoelectric conversion device 101 is a buried photodiode, and the thin p-type region 243 provided on the surface side (current extraction side) of the n-type region 244 can suppress dark current and reduce noise.

[0200] The insulating layer 241 functions as a blocking layer, the insulating layer 242 functions as an element isolation layer, and the insulating layer 245 functions to suppress the outflow of carriers.

[0201] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 245 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 245, it is possible to prevent carriers generated in the photoelectric conversion device 101 from flowing into adjacent pixels. The insulating layer 245 also has the function of suppressing the intrusion of stray light. Therefore, the insulating layer 245 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 245.

[0202] The element isolation layer can be formed using a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic resin can be used as the insulating layer 245. The insulating layer 245 may have a multi-layer structure.

[0203] The layer 10 also includes a transistor 102. The transistor 102 is a Si transistor. One of the source or the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source or the drain functions as a node FD.

[0204] The transistor 102 is provided on a silicon substrate included in the layer 10. The transistor 102 is one of the transistors that make up the imaging pixel 12. The other transistors that make up the imaging pixel 12, as well as the transistors that make up the first drive circuit unit 13, the second drive circuit unit 14, the readout circuit unit 15, and the control circuit unit 16, are also provided on the silicon substrate.

[0205] The first drive circuit unit 13, the second drive circuit unit 14, the readout circuit unit 15, and the control circuit unit 16 may be implemented by various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit.

[0206] The n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 in the layer 10 via a thin p-type region. The p-type region 243 (anode) is electrically connected to a wiring (not shown) that functions as a power supply line.

[0207] The light-shielding layer 252 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 252. The metal layer may also be stacked with a dielectric film that functions as an anti-reflection film.

[0208] A color filter can be used for the optical conversion layer 250. A color image can be obtained by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel.

[0209] Furthermore, if a wavelength cut filter is used in the optical conversion layer 250, a semiconductor device can be obtained that can obtain images in various wavelength regions.

[0210] For example, if a filter that blocks light with wavelengths equal to or shorter than visible light is used in the optical conversion layer 250, it can be used as an infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or shorter than near-infrared light is used in the optical conversion layer 250, it can be used as a far-infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or longer than visible light is used in the optical conversion layer 250, it can be used as an ultraviolet imaging device.

[0211] Furthermore, if a scintillator is used for the optical conversion layer 250, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light and / or ultraviolet light by the photoluminescence phenomenon. Then, imaging data is obtained by detecting this light with the photoelectric conversion device 101. An imaging device having this configuration may also be used for a radiation detector, etc.

[0212] A scintillator includes a material that absorbs the energy of radiation such as X-rays and / or gamma rays and emits visible and / or ultraviolet light when irradiated with the radiation. For example, Gd ２ O ２ S: Tb, Gd ２ O ２ S: Pr, Gd ２ O ２ S: Eu, BaFCl: Eu, NaI, CsI, CaF ２ , BaF ２ , CeF ３ , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0213] A microlens 19 is provided overlapping the photoelectric conversion device 101. Light 260 incident from the outside passes through the microlens 19 and the optical conversion layer 250 and is irradiated onto the photoelectric conversion device 101. By providing the microlens 19, the light 260 is condensed and incident on the photoelectric conversion device 101, thereby enabling efficient photoelectric conversion. The microlens 19 is preferably formed from a resin or glass that is highly translucent to visible light.

[0214] The layer 20 includes a substrate 701, and a transistor 251 is provided on the substrate 701. The transistor 251 is a transistor included in the display pixel circuit 431, for example.

[0215] The substrate 701 can be, for example, a single-crystal semiconductor substrate such as a single-crystal silicon substrate. Note that a semiconductor substrate other than a single-crystal semiconductor substrate may also be used as the substrate 701. For example, an insulating substrate or a semiconductor substrate can be used as the substrate 701. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Note that there is no limitation on the crystallinity of the semiconductor substrate. The semiconductor substrate used as the substrate 701 may be a single-crystal semiconductor substrate, a polycrystalline semiconductor substrate, or an amorphous semiconductor substrate. Furthermore, the substrate 701 may be a printed wiring board (PWB).

[0216] When a silicon substrate is used as the substrate 701, the transistor 251 is a Si transistor.

[0217] The transistor 251 is electrically isolated from other transistors by an element isolation layer 403. Fig. 10 shows a case where the transistor 251 is electrically isolated from other transistors by the element isolation layer 403. The element isolation layer 403 can be formed by a LOCOS method, an STI method, or the like.

[0218] Here, the transistor 251 has a semiconductor region 447 that has a convex shape. A conductive layer 443 is provided to cover the side surface and the top surface of the semiconductor region 447 with an insulating layer 445 interposed therebetween. Note that the conductive layer 443 covering the side surface of the semiconductor region 447 is not illustrated in FIG. The conductive layer 443 can be formed using a material that adjusts the work function.

[0219] A transistor having a convex semiconductor region such as the transistor 251 can be called a fin transistor because it utilizes the convex portion of a semiconductor substrate. Note that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Although FIG. 10 shows a structure in which the convex portion is formed by processing a part of the substrate 701, a semiconductor having a convex portion may be formed by processing an SOI substrate.

[0220] 10 is merely an example, and the present invention is not limited to this configuration, and an appropriate configuration may be used depending on the circuit configuration, the operation method of the circuit, etc. For example, the transistor 251 may be a planar transistor.

[0221] In addition to the element isolation layer 403 and the transistor 251, insulating layers 405, 407, 409, 361, and 363 are provided on the substrate 701. A conductive layer 451 is embedded in the insulating layer 409. Here, the height of the top surface of the conductive layer 451 and the height of the top surface of the insulating layer 409 can be made approximately the same.

[0222] Furthermore, a conductive layer 453 is embedded in the insulating layer 407, the insulating layer 405, the element isolation layer 403, and the substrate 701. The conductive layer 453 functions as a through silicon electrode (TSV: Through Silicon Via).

[0223] The conductive layers 311, 313, 331, and the capacitor 433 are embedded in the insulating layer 361. The conductive layers 311 and 313 function as wirings. The conductive layers 311 and 331 are electrically connected to the transistor 251.

[0224] Although FIG. 10 shows an example in which the capacitor 433 is provided over the insulating layer 409 , the capacitor 433 may be provided over an insulator different from the insulating layer 409 .

[0225] The conductive layer 341 and the conductive layer 351 are buried in the insulating layer 363. Here, the height of the upper surface of the conductive layer 351 and the height of the upper surface of the insulating layer 363 can be made to be approximately the same.

[0226] The insulating layers 405, 407, 409, 361, and 363 each function as an interlayer film and may also function as a planarizing film that covers uneven shapes below the insulating layer 405, 407, 409, 361, and 363. For example, the top surface of the insulating layer 363 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0227] Furthermore, the layer 10 and the layer 20 are connected by an adhesive layer 459. Specifically, the adhesive layer 459 is provided between the insulating layer 249 and the substrate 701. Furthermore, a bump 458 is embedded in the adhesive layer 459. The bump 458 is conductive. A portion of the bump 458 is electrically connected to the conductive layer 248, and another portion is electrically connected to the conductive layer 453. Thus, the layer 10 and the layer 20 are electrically connected via the bump 458.

[0228] In this specification and the like, the configuration or process of bonding two layers together using a silicon through electrode may be referred to as a “TSV connection” or “TSV bonding.” In this embodiment, layer 10 and layer 20 are bonded together using a TSV bond, but they may also be bonded together using a Cu-Cu bond, which will be described later.

[0229] Furthermore, the bonding of the layers 10 and 20 may be not only bonding the flat surfaces of the layers 10 and 20 together, but also bonding one flat surface to the side surface of the other. Alternatively, bonding of both side surfaces may also be possible. Furthermore, the layers 10 and 20 do not have to be bonded together, if necessary.

[0230] The layer 60 is provided on the layer 20. The layer 60 includes a light-emitting element 61. The light-emitting element 61 includes a conductive layer 171, an EL layer 172, and a conductive layer 173. The EL layer 172 includes an organic compound or an inorganic compound such as quantum dots.

[0231] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, while materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0232] The conductive layer 171 is electrically connected to one of the source and the drain of the transistor 251 through the conductive layer 351, the conductive layer 341, and the conductive layer 311. The conductive layer 171 is formed over the insulating layer 363 and functions as a pixel electrode.

[0233] A material that is transparent to visible light or a material that is reflective to visible light can be used for the conductive layer 171. Examples of light-transmitting materials include an oxide material containing indium and zinc, an oxide material containing indium, gallium, and zinc (also referred to as "IGZO"), an oxide material containing indium and tin (also referred to as "ITO"), or an oxide material containing indium, tin, and silicon (also referred to as "ITSO"). Examples of reflective materials include a material containing aluminum, silver, or the like.

[0234] For example, when light 175 emitted from light-emitting element 61 is emitted from the conductive layer 173 side, conductive layer 171 preferably contains a reflective material. Conductive layer 171 may have a single-layer structure or a multi-layer laminate structure. For example, when conductive layer 171 is used as an anode, it may have a three-layer structure in which silver is sandwiched between two ITO layers.

[0235] When the surface to be formed that contacts the conductive layer 171 contains silicon nitride, the conductive layer 171 may have a three-layer structure in which aluminum, titanium oxide, and ITO (or ITSO) are stacked in this order from the surface to be formed. When the surface to be formed that contacts the conductive layer 171 contains silicon nitride, the conductive layer 171 may have a two-layer structure in which aluminum and IGZO are stacked in this order from the surface to be formed.

[0236] In addition to the microlenses 19, the semiconductor device 100A may be provided with optical members such as a polarizing member, a phase difference member, and an anti-reflection member.

[0237] The light-emitting element 61 shown in Figure 10 can be made into a light-emitting element with a top emission structure in which light 175 is emitted from the conductive layer 173 side by using a reflective material for the conductive layer 171 and a light-transmitting material for the conductive layer 173.

[0238] 10 includes a filling layer 732 and a sealing substrate 40 overlapping the light-emitting element 61. In this embodiment, a solid sealing structure is shown in which the filling layer 732 is provided between the light-emitting element 61 and the sealing substrate 40, but a hollow sealing structure without the filling layer 732 may also be used. When the semiconductor device 100A has a hollow sealing structure, an inert gas containing a Group 18 element (a rare gas (noble gas)) and / or nitrogen may be sealed in the portion corresponding to the filling layer 732. When light emitted by the light-emitting element 61 is emitted toward the sealing substrate 40, it is preferable to use a light-transmitting material for the filling layer 732.

[0239] Note that a transistor including various semiconductors can be used as a transistor included in a semiconductor device according to one embodiment of the present invention. For example, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used. Furthermore, the semiconductor is not limited to a single element semiconductor whose main component is a single element, and a compound semiconductor (e.g., SiGe, GaAs, or the like) or an oxide semiconductor can also be used.

[0240] Furthermore, as a transistor included in a semiconductor device according to one embodiment of the present invention, transistors with various structures can be used. For example, transistors with various structures such as planar type, FIN type, TRI-GATE type, top-gate type, bottom-gate type, and double-gate type (gates are arranged above and below the channel) can be used. Furthermore, as a transistor included in a semiconductor device according to one embodiment of the present invention, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used.

[0241] <Application Example> A semiconductor device according to one embodiment of the present invention can reduce the time required from capturing an image of a subject to displaying the image. An application example of the semiconductor device according to one embodiment of the present invention is shown in Fig. 11. Fig. 11A and Fig. 11B show an example in which a subject 190 is captured using the semiconductor device 100A.

[0242] The subject image is projected onto the imaging unit 11 provided in the layer 10 of the semiconductor device 100A via an optical element 180 including a lens 181 (see FIG. 11A ). The optical element 180 may be a lens, a prism, a total reflection mirror, a semi-transparent mirror (half mirror), a polarizing element, a phase difference element, an anti-reflection element, and / or a shutter.

[0243] The subject image projected onto the imaging unit 11 is converted into an electrical signal by the imaging unit 11. The electrical signal is transmitted to a layer 20 including a display unit 21. The electrical signal transmitted to the layer 20 is reconstructed as an image and displayed on the display unit 21 (see FIG. 11B).

[0244] In the semiconductor device 100A according to one embodiment of the present invention, the layer 10 and the layer 20 are stacked on top of each other, so that an image of a subject captured by the layer 10 can be immediately displayed on the display unit 21 included in the layer 20. In other words, the time lag between capturing an image of a subject and displaying the image can be reduced. This embodiment of the present invention is particularly effective when capturing an image of a moving subject.

[0245] Note that the semiconductor device 100A according to one embodiment of the present invention can operate the imaging unit 11 and the display unit 21 independently. For example, the semiconductor device 100A according to one embodiment of the present invention can operate only the display unit 21 without operating the imaging unit 11. The semiconductor device 100A according to one embodiment of the present invention can also operate only the imaging unit 11 without operating the display unit 21. The semiconductor device 100A according to one embodiment of the present invention can also perform imaging using the imaging unit 11 and display an image on the display unit 21 that is different from the image obtained by the imaging.

[0246] Furthermore, the resolution, pixel density, diagonal size, and the like of the imaging unit 11 and the display unit 21 do not necessarily have to be the same between the imaging unit 11 and the display unit 21. Furthermore, when viewed in the Z direction, the semiconductor device 100A may or may not have an area where the imaging unit 11 and the display unit 21 overlap each other.

[0247] In this embodiment, the case where the semiconductor device 100A includes the layer 10, the layer 20, and the layer 60 has been described. However, the semiconductor device 100A according to one embodiment of the present invention is not limited to this. The semiconductor device 100A may have a configuration in which at least one of the layer 10, the layer 20, and the layer 60 included therein is not provided. Furthermore, in addition to the layer 10, the layer 20, and the layer 60, other layers including functional circuits such as memory circuits may be provided.

[0248] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0249] Second Embodiment In this embodiment, a semiconductor device 100B, which is a modification of the semiconductor device 100A, will be described. The semiconductor device 100B differs from the semiconductor device 100A in the configuration of the layer 10. FIGS. 12 and 13 are perspective views illustrating the configuration of the semiconductor device 100B. FIG. 12A is a perspective view of the front side of the semiconductor device 100B, and FIG. 12B is a perspective view of the back side of the semiconductor device 100B. In FIG. 13, layers 10 and 20 are shown separated to make the configuration of the semiconductor device 100B easier to understand.

[0250] In order to reduce repetition of explanation, the present embodiment will mainly describe the configuration of the semiconductor device 100B that is different from the semiconductor device 100A. For explanations not included in the present embodiment, please refer to the explanations in other embodiments.

[0251] The layer 10 of the semiconductor device 100B includes a layer 10a and a layer 10b. The layers 10a and 10b are stacked one on top of the other. The layer 10a includes an imaging unit 11, and the layer 10b includes a first driving circuit unit 13, a second driving circuit unit 14, a readout circuit unit 15, and a control circuit unit 16. By providing the functional circuits provided on the same layer as the imaging unit 11 in the semiconductor device 100A on a different layer, the semiconductor device can be made smaller.

[0252] Furthermore, stacking the imaging unit 11 and the functional circuitry allows the area occupied by the imaging unit 11 to be increased. This allows the resolution of the imaging unit 11 to be increased. Alternatively, the area occupied per pixel can be increased. This allows the light receiving sensitivity of the imaging unit 11 to be increased. Furthermore, the imaging quality of the semiconductor device 100B can be improved.

[0253] Furthermore, by providing the functional circuits on a different layer from the imaging unit 11, the area occupied by the functional circuits is freed up, making it possible to mount other functional circuits. Fig. 13 shows an example in which a DSP circuit unit 17 (DSP: Digital Signal Processor) and a memory circuit unit 18 are provided on the layer 10b. The DSP circuit unit 17 can perform various processes on the imaging data acquired by the imaging unit 11. The memory circuit unit 18 has a function of temporarily storing the imaging data acquired by the imaging unit 11 and the imaging data processed by the DSP circuit unit 17.

[0254] Storage devices of various storage methods can be used as the storage circuit unit 18. For example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase-change memory (PCM), a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), an antiferroelectric memory, or the like may be used.

[0255] A flash memory may be used as the memory circuit unit 18. A nonvolatile oxide semiconductor random access memory (NOSRAM) or a dynamic oxide semiconductor random access memory (DOSRAM) may be used as the memory circuit unit 18. NOSRAM and DOSRAM are types of memory devices that use OS transistors.

[0256] The memory circuit unit 18 may include multiple types of memory devices. For example, it may include a non-volatile memory device and a volatile memory device. The memory circuit unit 18 has a function of storing various programs used in the semiconductor device 100B, as well as data necessary for the operation of the semiconductor device 100B.

[0257] The functional circuits included in layer 10b do not necessarily have to have all of the configurations shown in the present embodiment, etc., and may have configurations other than these. Also, part of the functional circuits may be provided in layer 10a.

[0258] Furthermore, by stacking the imaging unit 11 and the first drive circuit unit 13, etc., the wiring electrically connecting them can be shortened. This reduces wiring resistance and parasitic capacitance, allowing the operating speed of the semiconductor device 100B to be increased. Furthermore, because the wiring resistance and parasitic capacitance are reduced, the power consumption of the semiconductor device 100B is reduced.

[0259] <Stacked Structure Example> A stacked structure example of the semiconductor device 100B will be described with reference to a cross-sectional view.

[0260] 14 is a cross-sectional view of a portion of the semiconductor device 100B. The semiconductor device 100B has a bonding surface between the layer 10a and the layer 20, and a bonding surface between the layer 10a and the layer 10b. The bonding surface between the layer 10a and the layer 20 is similar to the bonding surface between the layer 10 and the layer 20 in the semiconductor device 100A.

[0261] The layer 10 a includes an insulating layer 423 superimposed on the insulating layer 249 of the layer 10 , and a conductive layer 455 embedded in the insulating layer 423 .

[0262] The layer 10b can have a structure similar to that of the layer 20. FIG. 14 shows an example in which a substrate 701_2, an element isolation layer 403_2, an insulating layer 405_2, an insulating layer 407_2, an insulating layer 409_2, and a conductive layer 453_2 are included. The layer 10b also includes a transistor 104. The transistor 104 can have a structure similar to that of the transistor 251. The layer 10b can also include other transistors, a capacitor, and the like.

[0263] The substrate 701_2 corresponds to the substrate 701, and the element isolation layer 403_2 corresponds to the element isolation layer 403. The same applies to the insulating layer 405_2, the insulating layer 407_2, the insulating layer 409_2, and the conductive layer 453_2.

[0264] The layer 10b includes an insulating layer 424 overlapping the insulating layer 409_2, and a conductive layer 456 embedded in the insulating layer 424.

[0265] [Laminating] Next, laminating the layer 10a and the layer 10b will be described.

[0266] The surfaces of the insulating layer 423 and the conductive layer 455 are planarized to be at the same height, and the surfaces of the insulating layer 424 and the conductive layer 456 are planarized to be at the same height.

[0267] Here, the conductive layers 455 and 456 preferably contain the same metal element as a main component, and the insulating layers 423 and 424 preferably contain the same component.

[0268] For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 455 and 456. Cu, Al, W, or Au is preferable because of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 423 and 424.

[0269] That is, the same metal material as described above is preferably used for the conductive layer 455 and the conductive layer 456. The same insulating material as described above is preferably used for the insulating layer 423 and the insulating layer 424. With this structure, the layer 10a and the layer 10b can be bonded together at the boundary between them.

[0270] The conductive layers 455 and 456 may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 423 and 424 may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0271] By this bonding, electrical connection can be obtained between the conductive layer 455 and the conductive layer 456. Furthermore, connection between the insulating layer 423 and the insulating layer 424 can be obtained with sufficient mechanical strength.

[0272] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0273] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0274] When the layer 10a and the layer 10b are bonded to each other, an insulating layer and a metal layer are mixed on each bonding surface, so that the bonding may be performed by, for example, a combination of a surface activated bonding method and a hydrophilic bonding method.

[0275] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0276] By the above-mentioned bonding, the imaging section 11 of the layer 10a can be electrically connected to the first driving circuit section 13, the second driving circuit section 14, the readout circuit section 15, etc. of the layer 10b.

[0277] In this way, when two layers are bonded together with their metal layers facing each other, Cu is often used for the metal layers. Therefore, in this specification and elsewhere, the configuration or process of bonding two layers together with their respective metal layers facing each other may be referred to as "Cu-Cu connection" or "Cu-Cu bonding." Even if the metal layers do not contain Cu, the term "Cu-Cu connection" or "Cu-Cu bonding" may be used.

[0278] The layer 10b and the layer 20 may be bonded together by Cu-Cu bonding, and the layer 10a and the layer 10b may be bonded together by TSV bonding.

[0279] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0280] Third Embodiment In this embodiment, a semiconductor device 100C, which is a modification of the semiconductor device 100B, will be described. The semiconductor device 100C differs from the semiconductor device 100B in the configuration of the layer 20. Figures 15 and 16 are perspective views illustrating the configuration of the semiconductor device 100C. In Figure 16, layers 10 and 20 are shown separated from each other to make the configuration of the semiconductor device 100C easier to understand.

[0281] To reduce repetition of explanation, the present embodiment will mainly describe the configuration of the semiconductor device 100C that is different from the semiconductor device 100A and the semiconductor device 100B. For explanations not included in the present embodiment, please refer to the explanations in other embodiments.

[0282] Layer 20 of semiconductor device 100C includes layer 20a and layer 20b. Layer 20a and layer 20b are provided one on top of the other. Layer 20a includes a first drive circuit unit 231 and a second drive circuit unit 232, while layer 20b includes a display unit 21 and an input / output terminal unit 29. By providing first drive circuit unit 231 and second drive circuit unit 232 on a different layer from the display unit 21, it is possible to reduce the size of the semiconductor device.

[0283] Furthermore, the width of the frame around the display section 21 can be made extremely narrow, thereby increasing the area occupied by the display section 21. This improves the display quality of the semiconductor device 100C.

[0284] For example, the occupied area per pixel can be increased. Therefore, the luminance of the display unit 21 can be increased. Furthermore, the aperture ratio of the pixel can be increased. For example, the aperture ratio of the pixel can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, by increasing the occupied area per pixel, the current density supplied to the pixel can be reduced. Therefore, the load on the pixel is reduced, and the reliability of the semiconductor device 100C can be improved.

[0285] Furthermore, by stacking the display unit 21 and the peripheral driving circuits, etc., it is possible to shorten the wiring that electrically connects them, thereby reducing the wiring resistance and parasitic capacitance, and increasing the operating speed of the semiconductor device 100C. Furthermore, the power consumption of the semiconductor device 100C is reduced.

[0286] The layer 20 a also includes a CPU (Central Processing Unit) 23 , a GPU (Graphics Processing Unit) 24 , and a memory circuit section 25 in addition to the peripheral drive circuits.

[0287] The CPU 23 has a function of controlling the operation of the GPU 24 and the circuits provided in the layer 20a in accordance with a program stored in the memory circuit unit 25. The GPU 24 has a function of performing arithmetic processing to generate a video signal. Furthermore, the GPU 24 can perform many matrix operations (product-sum operations) in parallel, allowing it to perform arithmetic processing using, for example, a neural network at high speed. The GPU 24 has a function of correcting the video signal, for example, using correction data stored in the memory circuit unit 25. For example, the GPU 24 has a function of generating a video signal with corrections made to brightness, hue, and / or contrast.

[0288] The GPU 24 may be used to upconvert or downconvert the video signal. A super-resolution circuit may also be provided in the layer 20a. The super-resolution circuit has a function of determining the potential of any pixel in the display unit 21 by multiplying and adding the potentials and weights of the pixels surrounding the pixel. The super-resolution circuit has a function of upconverting a video signal having a lower resolution than the display unit 21. The super-resolution circuit also has a function of downconverting a video signal having a higher resolution than the display unit 21.

[0289] By providing a super-resolution circuit, the load on the GPU 24 can be reduced. For example, the GPU 24 processes up to 2K resolution (or 4K resolution), and the super-resolution circuit upconverts to 4K resolution (or 8K resolution), thereby reducing the load on the GPU 24. Furthermore, the processing speed of the semiconductor device 100C can be increased. Downconversion can be performed in the same manner.

[0290] The functional circuits included in the layer 20a may not necessarily include all of these components, or may include other components, such as a potential generating circuit that generates a plurality of different potentials and / or a power management circuit that controls the supply and stop of power to each circuit included in the semiconductor device 100C.

[0291] The supply and stopping of power may be performed for each circuit constituting the CPU 23. For example, power supply to a circuit constituting the CPU 23 that is determined not to be used for a while may be stopped, and power supply may be resumed when necessary, thereby reducing power consumption. Data required when power supply is resumed may be stored in a memory circuit within the CPU 23 or in the memory circuit unit 25 before the circuit is stopped. Storing data required when the circuit is restored enables the stopped circuit to be restored quickly. Note that circuit operation may be stopped by stopping the supply of a clock signal.

[0292] Furthermore, the functional circuits may include a DSP circuit, a sensor circuit, a communication circuit, and / or an FPGA (Field Programmable Gate Array) (not shown).

[0293] The sensor circuit has a function of acquiring information from one or more of human vision, hearing, touch, taste, and smell. More specifically, the sensor circuit has at least one of a function of detecting or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, gradient, vibration, odor, and infrared light. The sensor circuit may also have a function other than detecting or measuring these.

[0294] The communication circuit has a function of communicating wirelessly or via a wire, and a function of communicating wirelessly is particularly preferable because it can reduce the number of components such as cables for connection.

[0295] If the communication circuit has a function of wireless communication, the communication circuit can perform communication via an antenna. Furthermore, as a communication protocol or communication technology, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark), can be used.

[0296] The communication circuit can connect the semiconductor device 100C to other devices and input and output information via computer networks such as the Internet, an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), and a GAN (Global Area Network), which are the foundations of the World Wide Web (WWW).

[0297] In the semiconductor device 100C, an OS transistor is used as the transistor included in the layer 20b. An OS transistor has an extremely low off-state current. Therefore, the retention time of a video signal or the like can be extended, thereby reducing the frequency of refresh operations. Therefore, the power consumption of the semiconductor device 100C can be reduced.

[0298] Fig. 17A shows an example of the circuit configuration of a display pixel 230. The display pixel 230 includes a display pixel circuit 431 and a light-emitting element 61. Fig. 17B is a diagram schematically showing the hierarchical relationship between a layer 20a including a peripheral driver circuit, a layer 20b including the display pixel circuit 431, and a layer 60 including the light-emitting element 61.

[0299] 17A and 17B includes a transistor 436, a transistor 251, a transistor 434, and a capacitor 433. The transistors 436, 251, and 434 can be OS transistors. Each of the OS transistors 436, 251, and 434 preferably includes a back gate electrode. In this case, the back gate electrode can be supplied with the same signal as that of the gate electrode, or can be supplied with a signal different from that of the gate electrode.

[0300] The transistor 251 includes a gate electrode electrically connected to the transistor 436, a first terminal electrically connected to the light-emitting element 61, and a second terminal electrically connected to a potential supply line VL_a. The potential supply line VL_a is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0301] The transistor 436 has a first terminal electrically connected to the gate electrode of the transistor 251, a second terminal electrically connected to the wiring SL that functions as a source line, and a gate electrode that has a function of controlling the conductive state or non-conductive state based on the potential of the wiring GL1 that functions as a gate line.

[0302] The transistor 434 includes a first terminal electrically connected to a wiring V0, a ​​second terminal electrically connected to the light-emitting element 61, and a gate electrode having a function of controlling a conductive state or a non-conductive state based on the potential of a wiring GL2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the display pixel circuit 431 to a peripheral driver circuit.

[0303] The capacitor 433 includes a conductive film electrically connected to the gate electrode of the transistor 251 and a conductive film electrically connected to the second terminal of the transistor 434 .

[0304] The light-emitting element 61 includes a first electrode electrically connected to a first terminal of the transistor 251 and a second electrode electrically connected to a potential supply line VL_b. The potential supply line VL_b is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0305] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with a video signal applied to the gate electrode of the transistor 251. Furthermore, the reference potential of the wiring V0 applied via the transistor 434 can suppress variations in the gate-source potential of the transistor 251.

[0306] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 251 or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 may be converted into a voltage by a source follower circuit or the like.

[0307] In the configuration example shown in FIG. 17B , the wiring electrically connecting the display pixel circuit 431 and the peripheral driver circuit can be shortened, thereby reducing the wiring resistance of the wiring. Furthermore, the parasitic capacitance of the wiring can be reduced. Therefore, data can be written at high speed, allowing the display unit 21 to be driven at high speed. This allows a sufficient frame period to be ensured even with a large number of display pixel circuits 431, thereby increasing the pixel density of the display unit 21. Furthermore, increasing the pixel density of the display unit 21 can increase the resolution of images displayed on the display unit 21. For example, the pixel density of the display unit 21 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the semiconductor device 100A can be used, for example, in a display device for xR (xR) such as AR or VR. The semiconductor device 100A according to one embodiment of the present invention can be suitably applied to electronic devices, such as HMDs, in which the display unit is close to the user.

[0308] <Stacked Structure Example> A stacked structure example of the semiconductor device 100C will be described with reference to a cross-sectional view.

[0309] 18 is a cross-sectional view of a portion of the semiconductor device 100C. The layer 20a includes a substrate 701, and a transistor 251 is provided on the substrate 701. The layer 20a also includes an element isolation layer 403, an insulating layer 405, an insulating layer 407, an insulating layer 409, and a conductive layer 453.

[0310] The layer 20b includes an insulating layer 213 and an insulating layer 214, and a transistor 436 is provided over the insulating layer 214. The transistor 436 is, for example, a transistor included in the display pixel circuit 431. An OS transistor can be preferably used as the transistor 436. An OS transistor has an extremely low off-state current. Therefore, the retention time of a video signal or the like can be extended, thereby reducing the frequency of a refresh operation. Therefore, the power consumption of the semiconductor device 100C can be reduced.

[0311] The layer 20b includes an insulating layer 216, an insulating layer 222, an insulating layer 224, an insulating layer 254, an insulating layer 280, an insulating layer 274, an insulating layer 281, an insulating layer 361, and an insulating layer 363. A conductive layer 301 is embedded in the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281. The conductive layer 301 is electrically connected to one of the source and the drain of the transistor 436. Here, the height of the top surface of the conductive layer 301 and the height of the top surface of the insulating layer 281 can be made approximately the same.

[0312] A conductive layer 311 and a conductive layer 313 are buried in an insulating layer 361. The conductive layer 311 is electrically connected to one of the source and the drain of the transistor 251. The conductive layer 313 is electrically connected to the transistor 436 through the conductive layer 301. The conductive layer 313 functions as a wiring.

[0313] The insulating layers 213, 214, 216, 280, 274, and 281 each function as an interlayer film and may also function as a planarizing film that covers the uneven shapes below them. For example, the top surface of the insulating layer 281 may be planarized by a planarization treatment using a CMP method or the like to improve the planarity.

[0314] The semiconductor device 100C shown in FIG. 18 includes an OS transistor and a light-emitting device with a metal maskless (MML) structure. This configuration significantly reduces leakage current that may flow through the transistor and leakage current that may flow between adjacent light-emitting elements (also referred to as lateral leakage current or side leakage current). Furthermore, with this configuration, when an image is displayed on the display unit 21, a viewer can observe one or more of image clarity, image sharpness, high saturation, and a high contrast ratio. By significantly reducing leakage current that may flow through the transistor and lateral leakage current between light-emitting elements, a display with extremely reduced light leakage (so-called white floating) that may occur during black display (also referred to as true black display) can be achieved.

[0315] In particular, among light-emitting devices with an MML structure, by applying the SBS structure described above, the layer provided between the light-emitting elements (for example, an organic layer used in common between the light-emitting elements, also called a common layer) is configured to be separated, thereby making it possible to achieve a display with no side leakage or extremely little side leakage.

[0316] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0317] Fourth Embodiment In this embodiment, a semiconductor device 100D, which is a modification of the semiconductor device 100C, will be described. The semiconductor device 100D includes a layer 30 that integrates the functions of the layers 10b and 20a shown in the semiconductor device 100C. Figure 19 is a perspective view illustrating the configuration of the semiconductor device 100D. In Figure 19, the layers 10a and 30 are shown separated from each other to make the configuration of the semiconductor device 100D easier to understand.

[0318] In order to reduce repetition of explanation, the present embodiment will mainly describe the configuration of the semiconductor device 100D that is different from the semiconductor device 100C. For explanations not included in the present embodiment, please refer to the explanations in other embodiments.

[0319] The layer 30 included in the semiconductor device 100D is provided between the layer 10a and the layer 20b. The layer 30 shown in FIG. 19 includes a first drive circuit unit 13, a second drive circuit unit 14, a readout circuit unit 15, a control circuit unit 16, a DSP circuit unit 17, a memory circuit unit 18, a first drive circuit unit 231, a second drive circuit unit 232, a CPU 23, a GPU 24, and a memory circuit unit 25. Note that the layer 30 does not necessarily include all of these functional circuits. Furthermore, circuits other than these may be provided in the layer 30. Furthermore, some of these functional circuits may be provided in the layer 10a and / or the layer 20b.

[0320] By integrating the layers 10b and 20a into the layer 30, the number of components of the semiconductor device 100D can be reduced, thereby increasing the productivity of the semiconductor device 100D. Furthermore, by reducing the number of components, the number of connections between the components can be reduced, thereby improving the reliability of the semiconductor device.

[0321] <Stacked Structure Example> A stacked structure example of the semiconductor device 100D will be described with reference to a cross-sectional view.

[0322] 20 is a cross-sectional view of a portion of the semiconductor device 100D. The layer 30 has a similar configuration to the layer 20a. The layer 30 and the layer 10a are electrically connected by a TSV junction. Alternatively, the layer 30 and the layer 10a may be electrically connected by a Cu-Cu junction.

[0323] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0324] Fifth Embodiment In this embodiment, a semiconductor device 100E, which is a modification of the semiconductor device 100B, will be described. The semiconductor device 100E has a layer 20 that has the function of the layer 10b shown in the semiconductor device 100B. Figure 21 is a perspective view illustrating the configuration of the semiconductor device 100E. In Figure 21, layers 10a and 20 are shown separated from each other to make the configuration of the semiconductor device 100E easier to understand.

[0325] Although FIG. 21 does not show the control circuit section 16, the DSP circuit section 17, and the memory circuit section 18 in the layer 20, the semiconductor device 100E may include some or all of these functional circuits and other functional circuits.

[0326] <Stacked Structure Example> The stacked structure of the semiconductor device 100E is similar to the cross-sectional configuration example of the semiconductor device 100A shown in Fig. 10, and therefore detailed description thereof will be omitted. In the stacked structure example of the semiconductor device 100E, the layer 10a shown in Fig. 10 can be read as the layer 10.

[0327] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0328] Sixth Embodiment In this embodiment, an example of a connection configuration between the imaging unit 11 and the display unit 21 will be described.

[0329] As described in the above embodiment, the semiconductor device 100 according to one aspect of the present invention (semiconductor devices 100A to 100E) has a function of reading an image of a subject projected onto the imaging unit 11 and displaying the read image of the subject on the display unit 21. The imaging unit 11 and the display unit 21 have an overlapping area in the Z direction.

[0330] FIG. 22 is a perspective view showing how the imaging unit 11 and the display unit 21 overlap. FIG. 23 shows the imaging unit 11 and the display unit 21 shown in FIG. 22 in a separated state. FIGS. 22 and 23 correspond to, for example, a configuration example of a semiconductor device 100A. In this embodiment, to make it easier to understand how the imaging unit 11 and the display unit 21 overlap, a mark 99a is added to a corner of the imaging unit 11, and a mark 99b is added to a corner of the display unit 21. As shown in FIG. 22 , the imaging unit 11 and the display unit 21 overlap such that when the mark 99a is located at the bottom left of the imaging unit 11, the mark 99b is also located at the bottom left of the display unit 21. In other words, the imaging unit 11 and the display unit 21 overlap such that the mark 99a and the mark 99b coincide or approximately coincide.

[0331] In addition, in the drawings used in this embodiment, peripheral drive circuits and functional circuits are omitted in order to make it easier to understand the connection configuration between the imaging unit 11 and the display unit 21.

[0332] 22 and 23 show examples of a connection configuration in which the imaging unit 11 and the display unit 21 have the same resolution. That is, the imaging unit 11 includes imaging pixels 12 arranged in a matrix of m rows and n columns, and the display unit 21 includes display pixels 230 arranged in a matrix of m rows and n columns.

[0333] 22 and 23 , the imaging unit 11 and the display unit 21 are electrically connected via n wirings 134. Specifically, the imaging pixels 12 in the first column are electrically connected to the display pixels 230 in the first column via the first wiring 134 (wiring 134[1]). Similarly, the imaging pixels 12 in the nth column are electrically connected to the display pixels 230 in the nth column via the nth wiring 134 (wiring 134[n]). Note that the wirings 134 may be formed in the same manner as the conductive layers 248 and 453 described in the above embodiment. For example, the wirings 134 may be formed using TSVs, Cu-Cu bonding, or the like. Alternatively, the wirings 134 may be formed using a wire bonding method or the like.

[0334] By electrically connecting the imaging pixels 12 and the display pixels 230 via wiring 134 for each column, the imaging data obtained by the imaging unit 11 can be supplied to the display unit 21 as a video signal as imaging data for all columns for each row.

[0335] Specifically, the imaging data of the n imaging pixels 12 (imaging pixel 12[1,1] to imaging pixel 12[1,n]) in the first row can be supplied directly as a video signal to each of the n display pixels 230 (display pixel 230[1,1] to display pixel 230[1,n]) in the first row.

[0336] 22 and 23, the subject image captured by the imaging unit 11 can be immediately displayed on the display unit 21, reducing the time lag between capturing and displaying. This reduces the deviation in the timing of capturing. Furthermore, an accurate framework can be realized.

[0337] <Modification 1> Modifications of the configurations shown in Fig. 22 and Fig. 23 are shown in Fig. 24 and Fig. 25. Fig. 24 is a perspective view showing the imaging unit 11 and the display unit 21 overlapping each other. Fig. 25 shows the imaging unit 11 and the display unit 21 shown in Fig. 24 separated from each other.

[0338] 24 and 25 show a configuration example in which an analog potential control circuit 26, which is a type of functional circuit, is provided between the imaging unit 11 and the display unit 21. Each of the n wirings 134 is electrically connected to the analog potential control circuit 26. The analog potential control circuit 26 is also electrically connected to each column of a plurality of display pixels 230 provided in the display unit 21 via n wirings 135.

[0339] The analog potential control circuit 26 has the function of adjusting the voltage, converting the polarity, and amplifying the power of the imaging data supplied from the imaging unit 11. Therefore, it can also be said that the analog potential control circuit 26 has the function of converting the imaging data into a video signal.

[0340] Of the imaging data obtained by the imaging unit 11, imaging data for all columns is supplied row by row to the analog potential control circuit 26. The analog potential control circuit 26 converts the imaging data input via the wiring 134 into a video signal and supplies it to the display unit 21 via the wiring 135. Specifically, the imaging data supplied to the analog potential control circuit 26 via the wiring 134[1] is converted into a video signal by the analog potential control circuit 26 and supplied to the display unit 21 via the wiring 135[1]. Similarly, the imaging data supplied to the analog potential control circuit 26 via the wiring 134[n] is converted into a video signal by the analog potential control circuit 26 and supplied to the display unit 21 via the wiring 135[n].

[0341] According to one embodiment of the present invention, imaging data acquired by the imaging unit 11 can be converted into a video signal more suitable for display on the display unit 21 using the analog potential control circuit 26. For example, a semiconductor device that is less susceptible to noise and has high display quality can be realized.

[0342] Although this embodiment shows an example in which the analog potential control circuit 26 is provided in the layer 20, the analog potential control circuit 26 may be provided in the layer 10 (see FIG. 26 ). The wiring 135 may be formed in the same manner as the conductive layer 248 and the conductive layer 453 shown in the above embodiment. For example, the wiring 135 may be formed using a TSV and Cu-Cu bonding. Alternatively, the wiring 135 may be formed using a wire bonding method. Furthermore, for example, the analog potential control circuit 26 may be provided in the layer 30 of the semiconductor device 100D shown in the above embodiment.

[0343] <Modification 2> Furthermore, when the resolutions of the imaging unit 11 and the display unit 21 are different, the number of video signals output by the analog potential control circuit 26 may be adjusted. Figures 27 and 28 show an example in which the imaging unit 11 includes imaging pixels 12 arranged in a matrix of m rows and n columns, and the display unit 21 includes display pixels 230 arranged in a matrix of p rows and q columns. Although Figures 27 and 28 show a case in which p is less than m and q is less than n, the magnitude relationship may be reversed, or p and m may be equal.

[0344] 27 and 28 show an example of a configuration in which imaging data is supplied to the analog potential control circuit 26 via n wires 134 and a video signal is supplied to the display unit 21 via q wires 135.

[0345] When q is less than n, the imaging data of the corresponding column may be deleted at regular intervals, or when q is greater than n, the video signal of the added column may be calculated by using the average or weighted average of the video signals of the columns adjacent to the added column.

[0346] If p is smaller than m, the imaging data of the corresponding row may be deleted at regular intervals, and if p is larger than m, the video signal of the added row may be calculated by using the average or weighted average of the video signals of the rows adjacent to the added row.

[0347] Furthermore, as explained in the above embodiment, up-conversion or down-conversion of video signals may be performed using a GPU or a super-resolution circuit.

[0348] 29 and 30 , each column of the imaging unit 11 may be provided with an analog-to-digital converter (ADC) 51. Various ADCs, such as successive approximation, delta-sigma, or pipeline ADCs, may be used as the ADC 51. Furthermore, each column of the display unit 21 may be provided with a digital-to-analog converter (DAC) 52. Various DACs, such as segment, switched capacitor, or delta-sigma, may be used as the DAC 52.

[0349] In Figures 29 and 30, the ADC 51 provided between the imaging pixel 12 in the first column and the first wiring 134 is shown as ADC 51[1], and the ADC 51 provided between the imaging pixel 12 in the nth column and the nth wiring 134 is shown as ADC 51[n].

[0350] Also, in Figures 29 and 30, the DAC 52 provided between the display pixel 230 in the first column and the first wiring 134 is shown as DAC 52[1], and the DAC 52 provided between the display pixel 230 in the nth column and the nth wiring 134 is shown as DAC 52[n].

[0351] The imaging data of the imaging pixels 12 is an analog signal. The imaging data is converted into a digital signal by the ADC 51 and input to the DAC 52 via the wiring 134. The DAC 52 converts the digital imaging data into an analog signal. The converted analog imaging data is supplied to the display pixels 230 as a video signal.

[0352] Digital signals have higher noise resistance than analog signals, and can achieve stable data transfer. While Fig. 30 shows an example in which the ADC 51 is provided in layer 10 and the DAC 52 is provided in layer 20, for example, one or both of the ADC 51 and the DAC 52 may be provided in layer 30 of the semiconductor device 100D shown in the above embodiment.

[0353] <Modification 4> Furthermore, converting analog signals into digital signals facilitates arithmetic processing of captured image data (image processing), enabling various types of image processing to be performed, such as adjusting contrast, brightness, and saturation, as well as data compression / expansion and product-sum operations.

[0354] When performing arithmetic processing on imaging data, it is necessary to first output the imaging data converted into a digital signal to an arithmetic processing device (image processing device) or a storage device. Therefore, as shown in Figures 31 and 32, an output control circuit 53 may be provided on the output side of an ADC 51, and an input control circuit 54 may be provided on the input side of a DAC 52.

[0355] The output control circuit 53 has a function of selecting whether to output the imaging data supplied from the ADC 51 to the display unit 21 side or to the outside from the output terminal OUT. It is also possible to output the data to both the outside and the display unit 21 side.

[0356] The imaging data output to the outside is supplied to a storage device 610 (see FIGS. 34 and 35 ). Examples of the storage device 610 include not only the storage circuit unit 18 described in the above embodiment but also a hard disk drive (HDD), a solid state drive (SSD), a floppy disk (FD), a magneto-optical disk (MO), a USB memory, an SD memory card, a compact disc (CD), a digital versatile disc (DVD), and a Blu-ray disc (BD (registered trademark)).

[0357] The storage device 610 also functions as a temporary storage device for image processing of the captured image data. The image processing device for performing arithmetic processing of the captured image data may be, for example, one or more selected from the CPU, GPU, DSP, and super-resolution circuit described in the above embodiments.

[0358] The input control circuit 54 has a function of selecting either the imaging data supplied from the imaging unit 11 side via the ADC 51 or the digital signal supplied from the outside via the input terminal IN and supplying the selected signal to the DAC 52. It also has a function of supplying to the DAC 52 a signal that combines the imaging data supplied from the imaging unit 11 side via the ADC 51 and the digital signal input (IN) from the outside.

[0359] By providing the output control circuit 53 and the input control circuit 54, it is possible to supply externally processed image data to the display unit 21. Therefore, it is possible to realize a semiconductor device with good display quality.

[0360] 32 illustrates an example in which the ADC 51 and the output control circuit 53 are provided in the layer 10 and the DAC 52 and the input control circuit 54 are provided in the layer 20, but one embodiment of the present invention is not limited to this. For example, at least one of the ADC 51, the output control circuit 53, the DAC 52, and the input control circuit 54 may be provided in the layer 30 of the semiconductor device 100D described in the above embodiment.

[0361] Also, for example, the layer 10b of the semiconductor device 100C shown in the above embodiment may be provided with the ADC 51 and the output control circuit 53, and the layer 20a may be provided with the DAC 52 and the input control circuit 54 (see FIG. 33).

[0362] 34 and 35 show an example of a semiconductor device 100 including the layer 10 and the layer 20 shown in Fig. 32, and an example of an external device electrically connected to the semiconductor device 100. In Fig. 34 and 35, a control device 600, a memory device 610, an image processing device 620, a power control device 630, a timing controller 640, an input / output device 650, and a communication device 660 are shown as examples of the external device.

[0363] 34 and 35 , a control device 600, a storage device 610, an image processing device 620, a power control device 630, a timing controller 640, an input / output device 650, and a communication device 660 are electrically connected via a bus line 601. The image processing device 620 may also be electrically connected to the storage device 610 without using the bus line 601.

[0364] The control device 600 has a function of controlling the operation of each device connected via the bus line 601 .

[0365] The image processing device 620 has a function of performing arithmetic processing of the image data stored in the storage device 610. For example, it has a function of performing contrast adjustment and gamma correction of the image data.

[0366] The power control device 630 has a function of supplying the necessary power to layer 10 and a function of supplying the necessary power to layer 20. The power control device 630 may supply the same power to layer 10 and layer 20, or may supply different powers to each of them. Furthermore, as shown in Fig. 35, the power control device 630 may be divided into a power control device 630a having the function of supplying power to layer 10 and a power control device 630b having the function of supplying power to layer 20.

[0367] The timing controller 640 has a function of synchronizing the operation of the circuit included in layer 10 with the operation of the circuit included in layer 20. For example, the timing controller 640 has a function of supplying clock signals, start signals, etc. of the same frequency to each of layer 10 and layer 20. Furthermore, as shown in Figure 35, the timing controller 640 may be divided into a timing controller 640a having a function of supplying clock signals, start signals, etc. to layer 10, and a timing controller 640b having a function of supplying clock signals, start signals, etc. to layer 20.

[0368] The input / output device 650 has a function of inputting and outputting data to and from the outside. The input / output device 650 also has a function of supplying data held in the storage device 610 to the layer 20. Data input via the input / output device 650 may be stored in the storage device 610. The input / output device 650 also has a function of supplying data processed by the image processing device 620 to the layer 20.

[0369] The communication device 660 can communicate using the same communication protocol or communication technology as the communication circuit described above.

[0370] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0371] Embodiment 7 In this embodiment, a transistor that can be used for a semiconductor device according to one embodiment of the present invention will be described.

[0372] 36A, 36B, and 36C are a top view and a cross-sectional view of a transistor 500 that can be used for a semiconductor device according to one embodiment of the present invention. The transistor 500 can be applied to a semiconductor device according to one embodiment of the present invention. For example, the transistor 500 can be used as a transistor included in the layer 20.

[0373] FIG. 36A is a top view of the transistor 500. Also, FIGS. 36B and 36C are cross-sectional views of the transistor 500. Here, FIG. 36B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 36A and is also a cross-sectional view of the transistor 500 in the channel length direction. Also, FIG. 36C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 36A and is also a cross-sectional view of the transistor 500 in the channel width direction. Note that some elements are omitted from the top view in FIG. 36A for clarity.

[0374] As shown in FIG. 36 , the transistor 500 has a metal oxide 531 a arranged on a substrate (not shown), a metal oxide 531 b arranged on the metal oxide 531 a, conductors 542 a and 542 b arranged spaced apart from each other on the metal oxide 531 b, an insulator 580 arranged on the conductors 542 a and 542 b and having an opening formed between the conductors 542 a and 542 b, a conductor 560 arranged in the opening, an insulator 550 arranged among the metal oxide 531 b, the conductors 542 a, the conductors 542 b, and the insulator 580, and the conductor 560, and a metal oxide 531 c arranged among the metal oxide 531 b, the conductors 542 a, the conductors 542 b, the insulator 580, and the insulator 550. 36B and 36C , it is preferable that the top surface of conductor 560 substantially coincides with the top surfaces of insulators 550, 554, metal oxide 531c, and insulator 580. Note that, hereinafter, metal oxides 531a, 531b, and 531c may be collectively referred to as metal oxide 531. Furthermore, conductors 542a and 542b may be collectively referred to as conductor 542.

[0375] 36 , the side surfaces of the conductors 542a and 542b facing the conductor 560 have a substantially vertical shape. Note that the transistor 500 shown in FIG. 36 is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 542a and 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductors 542a and 542b may have multiple surfaces.

[0376] 36 , it is preferable that an insulator 554 be disposed between the insulator 524, the metal oxide 531a, the metal oxide 531b, the conductor 542a, the conductor 542b, and the metal oxide 531c and the insulator 580. Here, it is preferable that the insulator 554 be in contact with the side surface of the metal oxide 531c, the top and side surfaces of the conductor 542a, the top and side surfaces of the conductor 542b, the side surfaces of the metal oxide 531a and the metal oxide 531b, and the top surface of the insulator 524, as shown in FIGS.

[0377] Although the transistor 500 has a three-layer structure including a metal oxide 531a, a metal oxide 531b, and a metal oxide 531c in a region where a channel is formed (hereinafter also referred to as a channel formation region) and in the vicinity thereof, the present invention is not limited to this structure. For example, a two-layer structure including the metal oxide 531b and the metal oxide 531c or a stacked structure of four or more layers may be provided. Although the transistor 500 has a two-layer structure including the conductor 560, the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 531a, the metal oxide 531b, and the metal oxide 531c may have a stacked structure of two or more layers.

[0378] For example, when the metal oxide 531c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the metal oxide 531b, and the second metal oxide has a composition similar to that of the metal oxide 531a.

[0379] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. Here, the arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This allows for a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0380] As shown in FIG. 36, the conductor 560 preferably has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a.

[0381] The transistor 500 preferably includes an insulator 514 disposed on a substrate (not shown), an insulator 516 disposed on the insulator 514, a conductor 505 disposed so as to be embedded in the insulator 516, an insulator 522 disposed on the insulator 516 and the conductor 505, and an insulator 524 disposed on the insulator 522. A metal oxide 531a is preferably disposed on the insulator 524.

[0382] An insulator 574 functioning as an interlayer film and an insulator 581 are preferably provided over the transistor 500. Here, the insulator 574 is preferably provided in contact with top surfaces of the conductor 560, the insulator 550, the insulator 554, the metal oxide 531c, and the insulator 580.

[0383] The insulators 522, 554, and 574 preferably have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, the insulators 522, 554, and 574 preferably have lower hydrogen permeability than the insulators 524, 550, and 580. The insulators 522 and 554 preferably have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulators 522 and 554 preferably have lower oxygen permeability than the insulators 524, 550, and 580.

[0384] Here, the insulator 524, the metal oxide 531, and the insulator 550 are separated by the insulators 580 and 581, and the insulators 554 and 574. This prevents impurities such as hydrogen and excess oxygen contained in the insulators 580 and 581 from being mixed into the insulators 524, the metal oxide 531, and the insulator 550.

[0385] A conductor 545 (conductor 545a and conductor 545b) that is electrically connected to the transistor 500 and functions as a plug is preferably provided. Note that the insulator 541 (insulator 541a and insulator 541b) is provided in contact with the side surface of the conductor 545 that functions as a plug. That is, the insulator 541 is provided in contact with the inner walls of the openings of the insulators 554, 580, 574, and 581. Alternatively, a first conductor of the conductor 545 may be provided in contact with the side surface of the insulator 541, and a second conductor of the conductor 545 may be provided further inward. Here, the height of the top surface of the conductor 545 and the height of the insulator 581 can be made approximately the same. Note that the transistor 500 illustrates a structure in which the first conductor of the conductor 545 and the second conductor of the conductor 545 are stacked, but the present invention is not limited to this. For example, the conductor 545 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the layers may be distinguished by adding an ordinal number to indicate the order of formation.

[0386] In the transistor 500, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 531 (the metal oxide 531a, the metal oxide 531b, and the metal oxide 531c) including the channel formation region. For example, the metal oxide that serves as the channel formation region of the metal oxide 531 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0387] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). Furthermore, it is preferable that it contains an element M in addition to these. The element M can be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that the element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is even more preferable that the element M contains either or both of gallium (Ga) and tin (Sn).

[0388] 36B , the thickness of the metal oxide 531b in a region that does not overlap with the conductor 542 may be thinner than the thickness of the region that overlaps with the conductor 542. This is formed by removing a portion of the upper surface of the metal oxide 531b when forming the conductors 542a and 542b. When a conductive film that will become the conductor 542 is formed on the upper surface of the metal oxide 531b, a low-resistance region may be formed near the interface with the conductive film. In this way, removing the low-resistance region located between the conductors 542a and 542b on the upper surface of the metal oxide 531b can prevent a channel from being formed in that region.

[0389] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0390] A detailed structure of a transistor 500 that can be used in a display device according to one embodiment of the present invention will be described.

[0391] The conductor 505 is arranged to have a region overlapping with the metal oxide 531 and the conductor 560. The conductor 505 is preferably embedded in the insulator 516.

[0392] The conductor 505 includes a conductor 505a, a conductor 505b, and a conductor 505c. The conductor 505a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 516. The conductor 505b is provided so as to be embedded in a recess formed in the conductor 505a. Here, the top surface of the conductor 505b is lower than the top surface of the conductor 505a and the top surface of the insulator 516. The conductor 505c is provided in contact with the top surface of the conductor 505b and the side surface of the conductor 505a. Here, the height of the top surface of the conductor 505c is approximately the same as the height of the top surface of the conductor 505a and the height of the top surface of the insulator 516. In other words, the conductor 505b is configured to be enclosed by the conductors 505a and 505c.

[0393] The conductor 505a and the conductor 505c are made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0394] By using a conductive material that can reduce hydrogen diffusion for the conductors 505a and 505c, it is possible to prevent impurities such as hydrogen contained in the conductor 505b from diffusing into the metal oxide 531 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductors 505a and 505c, it is possible to prevent the conductor 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 505a may be formed as a single layer or a multilayer structure using the above conductive materials. For example, the conductor 505a may be made of titanium nitride.

[0395] The conductor 505b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0396] Here, the conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 505 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 505 may be changed independently of the potential applied to the conductor 560, thereby controlling the V ｔｈ In particular, applying a negative potential to the conductor 505 can control the V ｔｈ Therefore, when a negative potential is applied to the conductor 505, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when no negative potential is applied.

[0397] The conductor 505 is preferably larger than the channel formation region of the metal oxide 531. In particular, as shown in Fig. 36C, the conductor 505 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 531. In other words, the conductor 505 and the conductor 560 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 531 in the channel width direction.

[0398] With the above structure, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560 that functions as a first gate electrode and the electric field of the conductor 505 that functions as a second gate electrode.

[0399] 36C, the conductor 505 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 505.

[0400] The insulator 514 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. Therefore, the insulator 514 prevents hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., copper atoms are less likely to penetrate the impurities), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less likely to penetrate the insulating material).

[0401] For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 514 to the transistor 500 side. Alternatively, it can prevent oxygen contained in the insulator 524 or the like from diffusing to the substrate side of the insulator 514.

[0402] The insulators 516, 580, and 581, which function as interlayer films, preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 516, 580, and 581 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like as appropriate.

[0403] The insulators 522 and 524 function as gate insulators.

[0404] Here, the insulator 524 in contact with the metal oxide 531 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 524 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be reduced, and the reliability of the transistor 500 can be improved.

[0405] Specifically, an oxide material from which some oxygen is released by heating is preferably used as the insulator 524. The oxide from which oxygen is released by heating is an oxide having an oxygen atom content of 1.0×10 or more as determined by thermal desorption spectroscopy (TDS). １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0406] 36C , the thickness of the insulator 524 in a region that does not overlap with the insulator 554 and the metal oxide 531b may be thinner than the thickness of the other regions. The thickness of the insulator 524 in a region that does not overlap with the insulator 554 and the metal oxide 531b is preferably a thickness that allows sufficient diffusion of the oxygen.

[0407] Like the insulator 514 and the like, the insulator 522 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. For example, the insulator 522 preferably has lower hydrogen permeability than the insulator 524. By surrounding the insulator 524, the metal oxide 531, the insulator 550, and the like with the insulators 522, 554, and 574, impurities such as water or hydrogen can be prevented from entering the transistor 500 from the outside.

[0408] Furthermore, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, the insulator 522 preferably has lower oxygen permeability than the insulator 524. The insulator 522 preferably has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the metal oxide 531 toward the substrate side. Furthermore, the conductor 505 can be prevented from reacting with oxygen contained in the insulator 524 and the metal oxide 531.

[0409] The insulator 522 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the metal oxide 531 and the intrusion of impurities such as hydrogen into the metal oxide 531 from the periphery of the transistor 500.

[0410] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0411] The insulator 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ Insulators containing so-called high-k materials such as BST may be used in a single layer or a multilayer configuration. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0412] The insulator 522 and the insulator 524 may have a stacked structure of two or more layers. In this case, the insulators are not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. For example, an insulator similar to the insulator 524 may be provided under the insulator 522.

[0413] The metal oxide 531 includes a metal oxide 531a, a metal oxide 531b on the metal oxide 531a, and a metal oxide 531c on the metal oxide 531b. Having the metal oxide 531a below the metal oxide 531b can suppress the diffusion of impurities from structures formed below the metal oxide 531a to the metal oxide 531b. Having the metal oxide 531c on the metal oxide 531b can suppress the diffusion of impurities from structures formed above the metal oxide 531c to the metal oxide 531b.

[0414] Note that the metal oxide 531 preferably has a stacked structure of multiple oxide layers with different atomic ratios of the metal atoms. For example, when the metal oxide 531 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 531a to the number of atoms of all elements constituting the metal oxide 531a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 531b to the number of atoms of all elements constituting the metal oxide 531b. Furthermore, the atomic ratio of the element M contained in the metal oxide 531a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 531b to In. Here, the metal oxide 531c can be the same as the metal oxide 531a or the metal oxide 531b.

[0415] The energy of the conduction band minimum of the metal oxide 531a and the metal oxide 531c is preferably higher than the energy of the conduction band minimum of the metal oxide 531b. In other words, the electron affinity of the metal oxide 531a and the metal oxide 531c is preferably lower than the electron affinity of the metal oxide 531b. In this case, the metal oxide 531c is preferably a metal oxide that can be used for the metal oxide 531a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 531c to the number of atoms of all elements constituting the metal oxide 531c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 531b to the number of atoms of all elements constituting the metal oxide 531b. Furthermore, the atomic ratio of the element M contained in the metal oxide 531c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 531b to In.

[0416] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxides 531a, 531b, and 531c. In other words, the energy level of the conduction band minimum at the junction between the metal oxides 531a, 531b, and 531c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interface between the metal oxides 531a and 531b and at the interface between the metal oxides 531b and 531c.

[0417] Specifically, the metal oxide 531a and the metal oxide 531b, and the metal oxide 531b and the metal oxide 531c, have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low density of defect levels. For example, when the metal oxide 531b is an In—Ga—Zn oxide, the metal oxide 531a and the metal oxide 531c may be made of an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like. The metal oxide 531c may also have a stacked structure. For example, a stacked structure of an In—Ga—Zn oxide and a Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of an In—Ga—Zn oxide and a gallium oxide on the In—Ga—Zn oxide, may be used. In other words, a stacked structure of an In—Ga—Zn oxide and an oxide not containing In may be used as the metal oxide 531c.

[0418] Specifically, the metal oxide 531a may have an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The metal oxide 531b may have an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. The metal oxide 531c may have an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the metal oxide 531c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0419] In this case, the main carrier path is the metal oxide 531b. The above-described configuration of the metal oxide 531a and the metal oxide 531c can reduce the defect state density at the interface between the metal oxide 531a and the metal oxide 531b and at the interface between the metal oxide 531b and the metal oxide 531c. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 500 to achieve a high on-state current and high frequency characteristics. Note that when the metal oxide 531c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 531b and the metal oxide 531c, it is expected that the diffusion of constituent elements of the metal oxide 531c toward the insulator 550 can be suppressed. More specifically, the metal oxide 531c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, thereby suppressing In that may diffuse toward the insulator 550. The insulator 550 functions as a gate insulator, and diffusion of In causes poor transistor characteristics. Therefore, by using the metal oxide 531c in a stacked structure, a highly reliable display device can be provided.

[0420] Conductors 542 (conductors 542a and 542b) functioning as a source electrode and a drain electrode are provided on the metal oxide 531b. The conductor 542 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0421] By providing the conductor 542 so as to be in contact with the metal oxide 531, the oxygen concentration may be reduced in the vicinity of the conductor 542 of the metal oxide 531. Furthermore, a metal compound layer containing the metal contained in the conductor 542 and components of the metal oxide 531 may be formed in the vicinity of the conductor 542 of the metal oxide 531. In such a case, the carrier concentration increases in the region of the metal oxide 531 in the vicinity of the conductor 542, and the region becomes a low-resistance region.

[0422] Here, the region between the conductor 542a and the conductor 542b is formed to overlap the opening of the insulator 580. This allows the conductor 560 to be arranged in a self-aligned manner between the conductor 542a and the conductor 542b.

[0423] The insulator 550 functions as a gate insulator. The insulator 550 is preferably disposed in contact with the top surface of the metal oxide 531c. The insulator 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

[0424] The insulator 550 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 524. The thickness of the insulator 550 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

[0425] A metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. This can suppress oxidation of the conductor 560 due to oxygen in the insulator 550.

[0426] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 550 and the metal oxide, a stacked structure that is stable against heat and has a high dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0427] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0428] Although the conductor 560 is shown as having a two-layer structure in FIG. 36, it may have a single-layer structure or a laminated structure of three or more layers.

[0429] The conductor 560a is a material containing the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductor that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0430] The conductor 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductor 560b caused by oxygen contained in the insulator 550. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0431] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0432] 36A and 36C , in a region of the metal oxide 531b that does not overlap with the conductor 542, in other words, in the channel formation region of the metal oxide 531, the side surface of the metal oxide 531 is arranged to be covered with the conductor 560. This makes it easier for the electric field of the conductor 560, which functions as the first gate electrode, to act on the side surface of the metal oxide 531. This increases the on-state current of the transistor 500 and improves its frequency characteristics.

[0433] Like the insulator 514, the insulator 554 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the insulator 580 side. For example, the insulator 554 preferably has lower hydrogen permeability than the insulator 524. Furthermore, as shown in FIGS. 36B and 36C , the insulator 554 preferably contacts the side surface of the metal oxide 531c, the top and side surfaces of the conductor 542a, the top and side surfaces of the conductor 542b, the side surfaces of the metal oxide 531a and the metal oxide 531b, and the top surface of the insulator 524. This structure can prevent hydrogen contained in the insulator 580 from entering the metal oxide 531 from the top or side surfaces of the conductor 542a, the conductor 542b, the metal oxide 531a, the metal oxide 531b, and the insulator 524.

[0434] Furthermore, the insulator 554 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate through the insulator 554). For example, the insulator 554 preferably has lower oxygen permeability than the insulator 580 or the insulator 524.

[0435] The insulator 554 is preferably formed by a sputtering method. By forming the insulator 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 524 near a region in contact with the insulator 554. This allows oxygen to be supplied from the region to the metal oxide 531 through the insulator 524. The insulator 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 531 to the insulator 580. The insulator 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 531 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the metal oxide 531. This reduces oxygen vacancies in the metal oxide 531, and suppresses the transistor from becoming normally on.

[0436] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 554. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

[0437] The insulator 524, the insulator 550, and the metal oxide 531 are covered with the insulator 554 having a barrier property against hydrogen, and thus the insulator 580 is separated from the insulator 524, the metal oxide 531, and the insulator 550 by the insulator 554. This can prevent impurities such as hydrogen from penetrating from the outside of the transistor 500, thereby providing the transistor 500 with good electrical characteristics and reliability.

[0438] The insulator 580 is provided over the insulator 524, the metal oxide 531, and the conductor 542 with the insulator 554 interposed therebetween. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0439] The concentration of impurities such as water or hydrogen is preferably reduced in the insulator 580. The top surface of the insulator 580 may be planarized.

[0440] Like the insulator 514, the insulator 574 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 580 from above. As the insulator 574, for example, any of the insulators that can be used for the insulator 514, the insulator 554, and the like can be used.

[0441] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0442] The conductor 545a and the conductor 545b are arranged in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 554. The conductor 545a and the conductor 545b are provided opposite each other with the conductor 560 interposed therebetween. Note that the height of the top surfaces of the conductor 545a and the conductor 545b may be flush with the top surface of the insulator 581.

[0443] Note that insulator 541a is provided in contact with the inner walls of the openings of insulators 581, 574, 580, and 554, and a first conductor of conductor 545a is formed in contact with the side surface of insulator 541a. Conductor 542a is located on at least a portion of the bottom of the opening, and conductor 545a is in contact with conductor 542a. Similarly, insulator 541b is provided in contact with the inner walls of the openings of insulators 581, 574, 580, and 554, and a first conductor of conductor 545b is formed in contact with the side surface of insulator 541b. Conductor 542b is located on at least a portion of the bottom of the opening, and conductor 545b is in contact with conductor 542b.

[0444] The conductors 545a and 545b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 545a and 545b may have a layered structure.

[0445] When the conductor 545 has a layered structure, the conductors in contact with the metal oxide 531a, the metal oxide 531b, the conductor 542, the insulator 554, the insulator 580, the insulator 574, and the insulator 581 preferably have the above-described function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, a conductive material that suppresses the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. The use of such a conductive material can suppress the absorption of oxygen added to the insulator 580 by the conductors 545a and 545b. Furthermore, impurities such as water or hydrogen from layers above the insulator 581 can be prevented from entering the metal oxide 531 through the conductors 545a and 545b.

[0446] The insulators 541a and 541b may be, for example, an insulator that can be used for the insulator 554. The insulators 541a and 541b are provided in contact with the insulator 554, and thus can prevent impurities such as water or hydrogen from the insulator 580 or the like from being mixed into the metal oxide 531 through the conductors 545a and 545b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 545a and 545b.

[0447] Although not shown, a conductor functioning as a wiring may be disposed in contact with the top surface of the conductor 545a and the top surface of the conductor 545b. The conductor functioning as a wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0448] <Constituent Materials of Transistor> Constituent materials that can be used for the transistor will be described.

[0449] [Substrate] The substrate on which the transistor 500 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0450] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0451] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0452] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0453] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0454] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as the insulator 514, the insulator 522, the insulator 554, and the insulator 574) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, a single-layer or stacked insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0455] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be compensated for.

[0456] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0457] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0458] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0459] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0460] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0461] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0462] Embodiment 8 In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0463] <Classification of Crystal Structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 37A. Fig. 37A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0464] As shown in FIG. 37A , oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." Furthermore, "amorphous" includes completely amorphous. Furthermore, "crystalline" includes c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). The "Crystalline" category excludes single crystal, poly crystal, and completely amorphous. The "Crystal" category includes single crystal and poly crystal.

[0465] The structure within the bold frame shown in Figure 37A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from "Crystal" or the energetically unstable "Amorphous."

[0466] The crystalline structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 37B shows an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also called the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in FIG. 37B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 37B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 37B is 500 nm.

[0467] As shown in Figure 37B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 37B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0468] The crystalline structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 37C. FIG. 37C is a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 37C is near In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron beam diffraction is performed using a probe diameter of 1 nm.

[0469] As shown in FIG. 37C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0470] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 37A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0471] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0472] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0473] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nanometers.

[0474] In an In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0475] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0476] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0477] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0478] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0479] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities and / or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0480] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0481] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.

[0482] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0483] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0484] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0485] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0486] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0487] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0488] For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0489] When a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0490] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0491] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0492] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0493] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0494] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and therefore may also have a low density of trap states.

[0495] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0496] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0497] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0498] When an oxide semiconductor contains silicon and / or carbon, which are elements of Group 14, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those in the vicinity of the interface with the oxide semiconductor (concentrations obtained by SIMS) are calculated to be 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0499] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0500] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0501] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ less than 1×10１９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0502] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0503] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0504] Embodiment 9 In this embodiment, electronic devices to which a semiconductor device according to one embodiment of the present invention can be applied will be described.

[0505] The semiconductor device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, an electronic device with high display quality, extremely high resolution, or high reliability can be realized.

[0506] Examples of electronic devices using a semiconductor device or the like according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Examples of such equipment include image playback devices that play back still images or videos stored on recording media such as a CD (disc), portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable game machines, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, air conditioning equipment such as electric rice cookers, electric washing machines, electric vacuum cleaners, hot water heaters, electric fans, hair dryers, air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, and tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Mobile bodies propelled by fuel-powered engines or electric motors powered by power from power storage devices may also be included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs) equipped with both internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0507] An electronic device according to one embodiment of the present invention may include a secondary battery (battery), and it is preferable that the secondary battery can be charged using contactless power transmission.

[0508] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0509] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0510] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0511] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0512] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on one part of the display units and mainly displaying text information on another part, or a function of displaying a stereoscopic image by displaying an image taking into account parallax on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing a still image or a video, a function of automatically or manually correcting the captured image, a function of storing the captured image in a recording medium (external or built in the electronic device), a function of displaying the captured image on the display unit, etc. Note that the functions of the electronic device of one embodiment of the present invention are not limited to these, and can have various functions.

[0513] The semiconductor device according to one embodiment of the present invention can display high-resolution images. Therefore, the semiconductor device can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, and the like. For example, the semiconductor device can be suitably used in xR devices such as VR devices and AR devices.

[0514] FIG. 38A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0515] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000. Note that the lens 8006 and the housing of the camera 8000 may be integrated together.

[0516] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display portion 8002 that functions as a touch panel.

[0517] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0518] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0519] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display portion 8102.

[0520] The button 8103 has a function as a power button or the like.

[0521] The semiconductor device according to one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the finder 8100 may be built in the camera 8000.

[0522] FIG. 38B is a diagram showing the appearance of the head-mounted display 8200.

[0523] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. A battery 8206 is built into the mounting portion 8201. Note that the battery 8206 need not be built into the head-mounted display 8200, but may be externally attached.

[0524] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on the display portion 8204. The main body 8203 also includes a camera and can use information on the movement of the user's eyeball or eyelid via the lens 8202 as an input means. Note that the semiconductor device of one embodiment of the present invention may be applied to the camera. That is, one embodiment of the present invention is an electronic device that includes at least one of an attachment portion, a lens, a main body, and a cable and has a function of acquiring information from the user via the lens 8202.

[0525] The wearing unit 8201 may have a plurality of electrodes at positions that come into contact with the user, capable of detecting a current that flows in accordance with the movement of the user's eyeballs, and may have a function of recognizing the line of sight. The wearing unit 8201 may also have a function of monitoring the user's pulse based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying biometric information of the user on the display unit 8204 and a function of changing an image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0526] The semiconductor device according to one embodiment of the present invention can be applied to the display portion 8204 .

[0527] 38C to 38E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0528] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to curve the display portion 8302 because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, three-dimensional display using parallax can be performed. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion provided for each eye of the user.

[0529] A semiconductor device according to one embodiment of the present invention can be applied to the display portion 8302. The semiconductor device according to one embodiment of the present invention can also achieve extremely high definition. For example, even when a display is enlarged and viewed using a lens 8305 as shown in FIG. 38E , pixels are difficult for a user to view. That is, a highly realistic image can be viewed by the display portion 8302.

[0530] 38F is a diagram showing the appearance of a goggle-type head-mounted display 8400. The head-mounted display 8400 includes a pair of housings 8401, an attachment portion 8402, and a cushioning member 8403. A display portion 8404 and a lens 8405 are provided in each of the pair of housings 8401. By displaying different images on the pair of display portions 8404, three-dimensional display using parallax can be performed.

[0531] A user can view the display portion 8404 through the lens 8405. The lens 8405 has a focus adjustment mechanism, and its position can be adjusted according to the user's eyesight. The display portion 8404 is preferably a square or a horizontally long rectangle. This can enhance the sense of realism.

[0532] The attachment portion 8402 preferably has plasticity and elasticity so that it can be adjusted according to the size of the user's face and does not slip off. Furthermore, a portion of the attachment portion 8402 preferably has a vibration mechanism that functions as a bone conduction earphone. This allows the user to enjoy video and audio simply by wearing the device, without the need for separate audio equipment such as earphones or speakers. The housing 8401 may also have a function for outputting audio data via wireless communication.

[0533] The mounting portion 8402 and the buffer member 8403 are portions that come into contact with the user's face (forehead, cheeks, etc.). The close contact of the buffer member 8403 with the user's face can prevent light leakage and enhance the sense of immersion. The buffer member 8403 is preferably made of a soft material so that it can be in close contact with the user's face when the user wears the head-mounted display 8400. For example, materials such as rubber, silicone rubber, urethane, and sponge can be used. Furthermore, using a sponge or the like with its surface covered with cloth, leather (natural leather or synthetic leather), or the like can prevent gaps from forming between the user's face and the buffer member 8403, thereby effectively preventing light leakage. Furthermore, using such a material is preferable because it feels pleasant to the touch and prevents the user from feeling cold when worn in cold seasons. It is preferable that the buffer member 8403 or the mounting portion 8402, or other components that come into contact with the user's skin, are removable for easy cleaning or replacement.

[0534] 39A shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0535] The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000 .

[0536] 39A can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0537] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0538] 39B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The housing 7211 includes a display portion 7000.

[0539] The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000 .

[0540] 39C and 39D show an example of digital signage.

[0541] 39C includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0542] 39D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0543] 39C and 39D, the semiconductor device of one embodiment of the present invention can be applied to the display portion 7000.

[0544] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0545] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0546] 39C and 39D , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0547] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0548] 39E includes a housing 7551, a display portion 7552, a microphone 7557, a speaker portion 7554, a camera 7553, an operation switch 7555, and the like. The semiconductor device according to one embodiment of the present invention can be applied to the display portion 7552. The display portion 7552 has a touch panel function. The information terminal 7550 includes an antenna, a battery, and the like inside the housing 7551. The information terminal 7550 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an e-book reader, or the like.

[0549] 39F shows an example of a wristwatch-type information terminal. The information terminal 7660 includes a housing 7661, a display portion 7662, a band 7663, a buckle 7664, operation switches 7665, an input / output terminal 7666, and the like. The information terminal 7660 also includes an antenna, a battery, and the like inside the housing 7661. The information terminal 7660 can execute various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games.

[0550] The display portion 7662 is also equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. For example, an application can be started by touching an icon 7667 displayed on the display portion 7662. The operation switch 7665 can have various functions, such as time setting, power on / off operation, wireless communication on / off operation, silent mode activation / deactivation, and power saving mode activation / deactivation. For example, the functions of the operation switch 7665 can be set by an operating system incorporated in the information terminal 7660.

[0551] The information terminal 7660 can also perform short-range wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wirelessly enabled headset. The information terminal 7660 also includes an input / output terminal 7666, and can transmit and receive data to and from other information terminals via the input / output terminal 7666. Charging can also be performed via the input / output terminal 7666. Note that charging may be performed by wireless power supply without using the input / output terminal 7666.

[0552] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0553] 10: Layer, 11: Imaging section, 12: Imaging pixel, 13: Drive circuit section, 14: Drive circuit section, 15: Circuit section, 16: Control circuit section, 17: DSP circuit section, 18: Memory circuit section, 19: Microlens, 20: Layer, 21: Display section, 23: CPU, 24: GPU, 25: Memory circuit section, 29: Input / output terminal section, 30: Layer, 40: Sealing substrate, 60: Layer, 61: Light-emitting element

Claims

1. A semiconductor device including an imaging unit and a display unit, The imaging unit includes: A plurality of photoelectric conversion elements arranged in a matrix form are provided, The display unit is A substrate; a plurality of display pixel circuits arranged in a matrix; A plurality of display elements arranged in a matrix, The plurality of photoelectric conversion elements are provided in a first layer, the plurality of display pixel circuits are provided in a second layer on the first layer; the plurality of display elements are provided on a third layer on the second layer; the first layer includes a first insulating layer above the plurality of photoelectric conversion elements and a first conductive layer embedded in the first insulating layer; the second layer has an element isolation layer on the substrate, a second insulating layer on the element isolation layer, and a third insulating layer on the second insulating layer, and has a second conductive layer embedded in the substrate, the element isolation layer, the second insulating layer, and the third insulating layer; one of the plurality of display pixel circuits is electrically connected to one of the plurality of display elements; an adhesive layer having bumps embedded therein between the first layer and the second layer; The first conductive layer is electrically connected to the second conductive layer via the bump.

2. In claim 1, A function of acquiring imaging data using the plurality of photoelectric conversion elements; and supplying the imaging data of all columns, row by row, to the display unit.

3. In claim 2, The semiconductor device has a function of adjusting a voltage of the imaging data and supplying the adjusted voltage to the display unit.

4. In any one of claims 1 to 3, The display pixel circuit is a semiconductor device having a function of controlling the light emission luminance of the display element.

5. In any one of claims 1 to 4, The display element is an organic electroluminescence (EL) element.

6. In any one of claims 1 to 5, The display pixel circuit is a semiconductor device including a transistor having an oxide semiconductor.

7. In claim 6, The transistor is electrically connected to the first conductive layer via a second conductive layer and the bump.

8. A semiconductor device according to any one of claims 1 to 7, at least one of an antenna, a battery, or a microphone; An electronic device comprising:

9. A semiconductor device according to any one of claims 1 to 7, The optical fiber has at least one of a mounting portion, a lens, a body, or a cable; An electronic device having a function of acquiring information about a user through the lens.