Display device

Abstract

Provided is a display device having a high display quality. Provided is a highly reliable display device. Provided is a display device having a low power consumption. In the display device, a light-emitting element is electrically connected to one of the source and drain of a first transistor, the other of the source and drain of the first transistor is electrically connected to one of the source and drain of a second transistor, the gate electrode of the second transistor is electrically connected to one of the source and drain of a third transistor, each of a semiconductor layer of the second transistor and a semiconductor layer of the third transistor contains indium, zinc and a third metal, the semiconductor layer of the second transistor has the ratio of the number of indium atoms to the total sum of the numbers of atoms of indium, zinc, and the third metal being 30 atom%-100 atom% inclusive, and the second transistor has a function of controlling the light emission amount of the light-emitting element.

Description

display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device. Another embodiment of the present invention relates to a method for driving a display device. Another embodiment of the present invention relates to a semiconductor device. Another embodiment of the present invention relates to a method for driving a semiconductor device. Another embodiment of the present invention relates to a method for driving a circuit.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, pixels, pixel circuits, circuits, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, there has been a demand for higher definition display panels. Devices requiring high-definition display panels include, for example, smartphones, tablet terminals, and notebook computers. Furthermore, stationary display devices such as televisions and monitors are also required to have higher definitions in line with the trend toward higher resolutions. Furthermore, devices requiring the highest definition include, for example, devices for virtual reality (VR) or augmented reality (AR).

[0004] Representative examples of display devices that can be used in the display panel include liquid crystal display devices, organic EL (Electro Luminescence) elements, light-emitting devices equipped with light-emitting elements such as light-emitting diodes (LEDs), and electronic paper that displays images using an electrophoresis method.

[0005] For example, the basic structure of an organic EL element is a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be emitted from the light-emitting organic compound. A display device using such an organic EL element does not require a backlight, which is necessary in liquid crystal display devices and the like, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0006] Patent Document 2 discloses a display device for VR that uses an organic EL device.

[0007] Non-Patent Document 1 describes a pixel circuit having a thin film transistor using polycrystalline silicon and a thin film transistor using oxide, and Non-Patent Document 2 describes driving of a pixel circuit at various refresh rates of a display.

[0008] Patent Document 1: JP 2002-324673 A, International Publication No. 2018 / 087625

[0009] Ting-Kuo Chang et al. ,”LTPO TFT Technology for AMOLEDs,”SID Symp. Dig. Tech. Pap. , pp. 545-548 (2019). Ryo Yonebayashi et al. , “High refresh rate and low power consumption AMOLED panel using top-gate n-oxide and p-LTPS TFTs,” J. Soc. Inf. Disp. , 28, 4, pp. 350-359 (2020).

[0010] An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a display device with high reliability.An object of one embodiment of the present invention is to provide a display device with low power consumption.An object of one embodiment of the present invention is to provide a novel display device.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device including different transistors over the same substrate.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a display device including a first transistor, a second transistor, a third transistor, and a light-emitting element. the semiconductor layer of the third transistor contains indium, zinc, and the element M, and the ratio of the number of indium atoms to the total number of atoms of indium, zinc, and the element M in the semiconductor layer of the second transistor is 30 atomic % or more and 100 atomic % or less; and the second transistor is a display device having a function of controlling the amount of light emitted by the light-emitting element.

[0014] In the above configuration, it is preferable that the other of the source and drain of the third transistor is electrically connected to the other of the source and drain of the second transistor, and that the semiconductor layer of the second transistor has a higher ratio of the number of indium atoms to the total number of atoms of indium, zinc, and element M than the semiconductor layer of the third transistor.

[0015] In the above structure, the semiconductor layer of the third transistor preferably has a higher ratio of the number of atoms of the element M to the total number of atoms of indium, zinc, and the element M than the semiconductor layer of the second transistor.

[0016] In the above structure, it is preferable that the semiconductor layer of the third transistor has a ratio of the number of atoms of the element M to the number of atoms of the contained metal element of 20 atomic % to 60 atomic %.

[0017] Furthermore, in the above configuration, it is preferable that the semiconductor device has a fourth transistor, a fifth transistor, a first wiring, a capacitor, and a drive circuit, wherein one of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the second transistor, one of the source and drain of the fifth transistor is electrically connected to the other of the source and drain of the second transistor, the other of the source and drain of the fourth transistor is electrically connected to the first wiring, a first electrode of the capacitor is electrically connected to one of the source and drain of the first transistor, a second electrode of the capacitor is electrically connected to the gate of the second transistor, and the first wiring has a function of supplying a video signal output from the drive circuit to the other of the source and drain of the fourth transistor.

[0018] In addition, in the above configuration, it is preferable that the second transistor, the third transistor, and the fourth transistor are turned on and the first transistor and the fifth transistor are turned off, thereby having a function of writing a potential to the gate of the second transistor, and that the third transistor and the fourth transistor are turned off after the potential has been written, thereby having a function of retaining the written potential.

[0019] Furthermore, in the above configuration, it is preferable that the semiconductor device has a function of writing a potential to the gate of the second transistor by turning on the second transistor, the third transistor, and the fourth transistor and turning off the first transistor and the fifth transistor, a function of holding the written potential by turning off the third transistor and the fourth transistor after the potential has been written, and a function of passing a current through the light-emitting element and controlling the amount of light emitted by the light-emitting element by turning on the first transistor, the second transistor, and the fifth transistor after the potential has been held.

[0020] According to one embodiment of the present invention, a display device with high display quality can be provided. Further, according to one embodiment of the present invention, a display device with high reliability can be provided. Further, according to one embodiment of the present invention, a display device with low power consumption can be provided. Further, according to one embodiment of the present invention, a novel display device can be provided.

[0021] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with stable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device including different transistors over the same substrate can be provided. According to another embodiment of the present invention, a novel semiconductor device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A and 1B are diagrams showing an example of the configuration of a pixel. FIG. 2 is a diagram showing an example of the configuration of a pixel. FIG. 3A is a timing chart illustrating an example of the operation of a pixel. FIG. 3B is a diagram showing an example of the configuration of a pixel. FIG. 4A is a diagram showing an example of the configuration of a pixel. FIG. 4B is a diagram showing an example of the configuration of a pixel. FIGS. 5A and 5B are diagrams showing an example of the configuration of a pixel. FIG. 6 is a diagram showing an example of the configuration of a display device. FIGS. 7A and 7B are diagrams showing an example of the configuration of a display device. FIGS. 8A to 8E are diagrams showing an example of an array of pixels. FIG. 9A is a top view showing an example of a display device. FIG. 9B is a cross-sectional view showing an example of a display device. FIGS. 10A to 10C are cross-sectional views showing an example of a display device. FIGS. 11A and 11B are cross-sectional views showing an example of a display device. FIGS. 12A to 12C are cross-sectional views showing an example of a display device. FIGS. 13A to 13F are cross-sectional views showing an example of a display device. FIG. 14 is a perspective view showing an example of a display device. FIG. 15A is a cross-sectional view showing an example of a display device. FIG. 15B is a cross-sectional view showing an example of a transistor. FIG. 16 is a cross-sectional view showing an example of a display device. Fig. 17 is a cross-sectional view showing an example of a display device. Figs. 18A to 18F are diagrams showing configuration examples of a light-emitting device. Figs. 19A and 19B are diagrams showing an example of an electronic device. Figs. 20A to 20D are diagrams showing an example of an electronic device. Figs. 21A to 21F are diagrams showing an example of an electronic device. Figs. 22A and 22B show Id-Vg characteristics of a transistor. Figs. 23A and 23B show Id-Vg characteristics of a transistor.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0026] In each figure described in this specification, the size of each component, the thickness of a layer, or the area may be exaggerated for clarity, and therefore, is not necessarily limited to that scale.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] The functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0030] In this specification, either the source or the drain of a transistor may be referred to as a "first electrode," and the other of the source or the drain may be referred to as a "second electrode." The gate may also be referred to as a "gate" or a "gate electrode." In addition, in this specification, the first terminal and the second terminal of a transistor refer to, for example, one of the source and the drain of the transistor and the other of the source and the drain, respectively.

[0031] In this specification, "electrically connected" includes a connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0032] In this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0033] In this specification, the EL layer refers to a layer (also referred to as a light-emitting layer) that is provided between a pair of electrodes of a light-emitting device (also referred to as a light-emitting element) and contains at least a light-emitting substance, or a stack including a light-emitting layer.

[0034] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface, and therefore the display panel is one aspect of an output device.

[0035] In this specification and the like, a display panel having a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) attached to its substrate, or a substrate having an IC mounted on it using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, a display module, or simply a display panel.

[0036] A display device according to one embodiment of the present invention can suppress current variations in pixel circuits included in each pixel and achieve excellent display quality. Furthermore, the display device according to one embodiment of the present invention can reduce power consumption and achieve excellent display quality, particularly when an image is displayed on a display unit at a low frame frequency.

[0037] A low frame frequency is, for example, 3 Hz or less, preferably 1 Hz or less, more preferably 0.1 Hz or less, and even more preferably 0.01 Hz or less. A high frame frequency is, for example, 30 Hz or more.

[0038] When a transistor including an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) is used as a transistor included in a pixel circuit, charge written to each node can be retained for a long period of time. When a still image that does not require rewriting for each frame is displayed at a high frequency, the frame frequency can be lowered, and the operation of the peripheral driver circuit can be stopped after a signal corresponding to image data is written to the pixel circuit. Such a driving method of stopping the operation of the peripheral driver circuit while a still image is displayed is also called "idling stop driving." By performing idling stop driving, the power consumption of the display device can be reduced.

[0039] Furthermore, the display device of one embodiment of the present invention can have a variable refresh rate. For example, the refresh rate can be adjusted (for example, within a range of 0.01 Hz to 240 Hz) depending on the content displayed on the display device, thereby reducing power consumption. Furthermore, driving that reduces the power consumption of the display device by driving it at a reduced refresh rate may be called idling stop (IDS) driving.

[0040] The drive frequency of the touch sensor or near-touch sensor may be changed depending on the refresh rate. For example, if the refresh rate of the display device is 120 Hz, the drive frequency of the touch sensor or near-touch sensor may be set to a frequency higher than 120 Hz (typically 240 Hz). This configuration enables low power consumption and an increased response speed of the touch sensor or near-touch sensor.

[0041] Furthermore, to increase the emission luminance of a light-emitting device included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain withstand voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0042] Furthermore, when the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing through the light-emitting device. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0043] Furthermore, in terms of the saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, for example, even when the current-voltage characteristics of a light-emitting device containing an EL material vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0044] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0045] [Pixel Structure Example] FIG. 1A illustrates an example of a pixel Px of one embodiment of the present invention.

[0046] The pixel Px includes a pixel circuit 51 and a light-emitting element EL1. The pixel circuit 51 includes transistors Tr1 to Tr6 and a capacitor C1. The pixel Px is electrically connected to wirings Vdata, Vdd, Vss, Vini, Vscan1, Vscan2, Vem1, and Vem2.

[0047] The transistors Tr1 to Tr6 are preferably n-channel field-effect transistors, and each of the transistors Tr1 to Tr6 is preferably an enhancement (normally-off) n-channel field-effect transistor. Therefore, the threshold voltage (also referred to as "Vth") of each of the transistors Tr1 to Tr6 is preferably greater than 0 V.

[0048] The light-emitting element EL1 includes a first electrode electrically connected to the wiring Vss and a second electrode electrically connected to the transistor Tr5.

[0049] The transistor Tr5 has a first terminal electrically connected to the light-emitting element EL1, a second terminal electrically connected to the transistors Tr2 and Tr1, and a gate electrode electrically connected to the wiring Vem1. Here, the first terminal and the second terminal of the transistor refer to, for example, one of the source and the drain of the transistor, respectively.

[0050] The transistor Tr5 functions as a switch that controls whether or not a current flows through the light-emitting element EL1.

[0051] The transistor Tr6 includes a first terminal electrically connected to the light-emitting element EL1, a second terminal electrically connected to the wiring Vini, and a gate electrode electrically connected to the wiring Vscan1.

[0052] The capacitor C1 has a first electrode electrically connected to the light-emitting element EL1 and a second electrode electrically connected to the gate of the transistor Tr2.

[0053] The node ND1 is a junction that electrically connects the second electrode of the light-emitting element EL1, the first terminal of the transistor Tr5, the first terminal of the transistor Tr6, and the first electrode of the capacitor C1.

[0054] The transistor Tr2 has a first terminal electrically connected to the transistor Tr5, a second terminal electrically connected to the transistor Tr3 and the transistor Tr4, and a gate electrode electrically connected to the capacitor C1.

[0055] The transistor Tr1 includes a first terminal electrically connected to the transistors Tr2 and Tr5, a second terminal electrically connected to the wiring Vdata, and a gate electrode electrically connected to the wiring Vscan2.

[0056] The node ND3 is a node electrically connecting the second terminal of the transistor Tr5, the first terminal of the transistor Tr2, and the second terminal of the transistor Tr1.

[0057] The transistor Tr3 has a first terminal, a second terminal, and a gate electrode. The gate electrode of the transistor Tr3 is electrically connected to the wiring Vscan1. The first terminal of the transistor Tr3 is electrically connected to the gate electrode of the transistor Tr2, and the second terminal of the transistor Tr3 is electrically connected to the second terminal of the transistor Tr2. Therefore, when the transistor Tr3 is turned on, the gate electrode of the transistor Tr2 and the second terminal can be electrically connected.

[0058] The node ND2 is a node electrically connecting the gate electrode of the transistor Tr2, the second electrode of the capacitor C1, and the first terminal of the transistor Tr3.

[0059] The transistor Tr4 has a first terminal electrically connected to the transistors Tr2 and Tr3, a second terminal electrically connected to the wiring Vdd, and a gate electrode electrically connected to the wiring Vem2.

[0060] The second terminal of the transistor Tr2, the second terminal of the transistor Tr3, and the first terminal of the transistor Tr4 are electrically connected.

[0061] The transistor Tr2 functions as a current control transistor for the light-emitting element EL1, that is, the transistor Tr2 functions to control the amount of light emitted by the light-emitting element EL1, and is therefore sometimes called a drive transistor.

[0062] In the pixel circuit 51 of one embodiment of the present invention, by using a transistor with extremely small hysteresis as the transistor Tr2, the display quality of a display device can be improved even at a low frame frequency.

[0063] In a transistor having a significantly large hysteresis, the threshold voltage of the transistor changes due to voltage stress between the gate and source of the transistor.

[0064] If the transistor Tr2 has a hysteresis characteristic, there is a concern that the threshold value of the transistor Tr2 may fluctuate during the period in which a current flows through the light-emitting element EL1. In particular, when the frame frequency of the image display in the display unit is low, the period from when image data is written to the pixel until the next frame is long, and therefore, the change in the luminance of the light-emitting element EL1 due to the fluctuation in the threshold value of the transistor Tr2 is easily visible to a user of the display device.

[0065] An OS transistor has extremely small hysteresis. Therefore, by using an OS transistor as a driving transistor in the pixel circuit of one embodiment of the present invention, a change in luminance of the light-emitting element EL1 can be suppressed. By using an OS transistor as a driving transistor in the pixel circuit of one embodiment of the present invention, variation in the value of current flowing through the light-emitting element EL1 can be suppressed, and the display quality of the display device can be improved even at a low frame frequency.

[0066] In the Id-Vg measurement of a transistor included in a pixel circuit of one embodiment of the present invention, for example, hysteresis is preferably 0.1 V or less, more preferably 0.05 V or less, when reciprocating scanning is performed in a Vg range of −15 V to +20 V. Furthermore, Vd in the Id-Vg measurement is, for example, 0.01 V to 10 V. The Vg measurement interval may be, for example, in increments of 0.1 V. A hold period of, for example, 1 second or less may be provided at each Vg measurement point. Here, Id is the source-drain current, Vd is the source-drain voltage, and Vg is the source-gate voltage. The transistor used for the measurement has a channel length of, for example, 100 μm or less, or 10 μm or less. The transistor used for the measurement has a channel width of, for example, 100 μm or less, or 10 μm or less.

[0067] In addition, an OS transistor has a high withstand voltage between its source and drain. By using an OS transistor as a transistor constituting the pixel circuit 51, operation is stable even when a large potential difference is applied to the wiring Vdd and the wiring Vss of the light-emitting element EL1, and a highly reliable display device can be realized. Using an OS transistor with a high withstand voltage between its source and drain as the transistor Tr2 is preferable because it enables accurate control of the current of the light-emitting element EL1 even when the display device is used for a long period of time.

[0068] The wiring Vdata has a function of supplying a signal Vdata_1 corresponding to a video signal to the transistor Tr1. The wiring Vdata is sometimes called a source line. The pixel circuit 51 has a function of supplying a signal obtained by performing a correction process on the signal Vdata_1 to the node ND2 by turning on each of the transistors Tr1, Tr2, and Tr3. This correction process can suppress the influence of threshold voltage variations of the transistor Tr2 on the current flowing through the light-emitting element EL1. The pixel circuit 51 can sometimes be expressed as having a function of supplying a potential to the node ND2 in which the influence of threshold voltage variations of the transistor Tr2 has been canceled out.

[0069] Here, the threshold voltage variation of the transistor Tr2 refers to, for example, the variation in the threshold voltage of the transistor Tr2 of each pixel circuit 51 among a plurality of pixel circuits.

[0070] The pixel circuit 51 has a function of turning off the transistor Tr3 and holding the potential applied to the node ND2. The oxide semiconductor used for the channel formation region of the OS transistor has a band gap of 2 eV or more, and therefore the off-state current is extremely small. By using an OS transistor as the transistor Tr3, leakage current in the off state can be kept extremely low, and therefore fluctuation in the potential of the signal applied to the node ND2 can be made extremely small.

[0071] When the frame frequency of the image display on the display unit is low, the period from when image data is written to the pixel circuit until the next frame is long, and therefore the fluctuation in the potential of the node ND2 due to the off-leak current of the transistor Tr3 becomes large. Therefore, when the frame frequency is low, it is particularly preferable to use a transistor with a small off-leak current as the transistor Tr3.

[0072] For example, after a signal is written from the wiring Vdata in the pixel circuit 51, the transistor Tr1 can be turned off until the next frame. By turning off the transistor Tr1, the current flowing through the wiring Vdata in the pixel circuit 51 can be cut off, thereby reducing the power consumption of the pixel circuit 51 and the power consumption of a circuit that supplies a signal to the wiring Vdata.

[0073] In the pixel circuit 51, for example, after a potential corresponding to a signal from the wiring Vini is written to the node ND1 via the transistor Tr6, the transistor Tr6 can be turned off until the next frame. By turning off the transistor Tr6, the current flowing through the wiring Vini can be cut off, thereby reducing the power consumption of the pixel circuit 51 and the power consumption of a circuit that supplies a signal to the wiring Vini.

[0074] Each transistor included in the pixel circuit 51 may have a back gate. In particular, an OS transistor preferably has a back gate. FIG. 1B shows an example of a transistor having a back gate. The same signal as that applied to the gate can be applied to the back gate. Alternatively, the same signal as that applied to the source or drain can be applied to the back gate. Applying a signal to the back gate can control, for example, the threshold voltage of the transistor.

[0075] Alternatively, the back gate of a transistor may be electrically connected to the source or drain of the transistor. In the pixel circuit 51 shown in FIG. 2 , the back gates of the transistors Tr4 and Tr5 are electrically connected to one of the source and drain of the transistor. By electrically connecting the back gates of the transistors to the source or drain of the transistors, for example, the transistors can be made more resistant to application of a gate electric field, thereby improving reliability.

[0076] Note that an OS transistor has significantly higher field-effect mobility than an amorphous silicon transistor. Furthermore, an OS transistor has a significantly smaller source-drain leakage current in an off state (hereinafter also referred to as an off-state current), and can hold charge accumulated in a capacitor connected in series with the OS transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a display device.

[0077] The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor), the off-state current per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) More than 1pA (1×10 −１２ Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0078] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A display device including an OS transistor operates stably and has high reliability even in a high-temperature environment.

[0079] The silicon contained in the Si transistor includes amorphous silicon and crystalline silicon (for example, polycrystalline silicon and single crystal silicon).

[0080] The light-emitting element EL1 preferably uses an EL device such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that the EL device may have include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). The TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in a high-brightness region of the light-emitting device. The light-emitting element EL1 is not limited to this, and may be an inorganic EL element containing an inorganic material, a light-emitting diode, etc. An LED such as a micro LED (Light Emitting Diode) may also be used as the light-emitting device.

[0081] 3A, 3B, 4A, and 4B, an example of the operation of the pixel Px shown in FIG. 1A will be described. In the following operation example, the potentials of the nodes ND1, ND2, and ND3 are respectively represented by potentials V ＮＤ１ , potential V ＮＤ２ , and potential V ＮＤ３ It may be indicated as follows.

[0082] 3A is a timing chart showing an example of the operation of pixel Px. Note that, although the following description will be given assuming that all transistors constituting the pixel are n-channel transistors, the following description can also be applied to cases where some or all of the transistors are p-channel transistors by, for example, switching between high potential and low potential as necessary.

[0083] <Initialization Operation> First, at time t1, a high potential signal H is applied to the wiring Vscan1 and the wiring Vem2, and a low potential signal L is applied to the wiring Vscan2 and the wiring Vem1.

[0084] The transistors Tr1 and Tr5 are in the off state.

[0085] The transistor Tr6 is turned on, and the potential Vi_1 is applied to the node ND1 from the wiring Vini (FIG. 3B).

[0086] The transistors Tr3 and Tr4 are turned on, and the potential Vd_1 is applied to the node ND2 from the wiring Vdd (FIG. 3B).

[0087] <Threshold Voltage Compensation Operation> Next, at time t2, a high potential signal is applied to the wirings Vscan1 and Vscan2, and a low potential signal L is applied to the wirings Vem1 and Vem2.

[0088] The transistor Tr4 is turned off, and the transistor Tr5 continues to be turned off.

[0089] The transistor Tr6 continues to be on, and the potential Vi_1 is held at the node ND1 (FIG. 4A).

[0090] The transistor Tr1 is turned on, and the potential Va_1 is applied to the node ND3 from the wiring Vdata through the transistor Tr1 (FIG. 4A).

[0091] The transistor Tr3 continues to be on. In addition, since the potential Vd_1 is applied to the node ND2, the transistor Tr2 also remains on.

[0092] The potential of node ND2 changes as the potential of node ND3 changes, and node ND2 is given the sum (potential (Va_1+Vt)) of the potential of node ND3 (potential Va_1) and the threshold value of transistor Tr2 (potential Vt) (Figure 4A).

[0093] In each of the multiple pixels in the display unit, the threshold value of the transistor Tr2 is acquired and a potential corresponding to the threshold value of the transistor Tr2 is applied between the gate and source of the transistor Tr2, thereby correcting the variation in the threshold value of the transistor for each pixel. Note that the operation of acquiring the threshold value of the transistor Tr2 is sometimes referred to as a "threshold compensation operation."

[0094] <Light Emitting Operation> Next, at time t3, a high potential signal is applied to the wirings Vem1 and Vem2, and a low potential signal L is applied to the wirings Vscan1 and Vscan2.

[0095] The transistor Tr1 is turned off, and the node ND3 is electrically disconnected from the wiring Vdata. The transistor Tr6 is turned off, and the node ND1 is electrically disconnected from the wiring Vini.

[0096] The transistor Tr3 is turned off, and the potential of the node ND2 is maintained.

[0097] The transistors Tr4, Tr2, and Tr5 are turned on, and a current flows through the light-emitting element EL1 ( FIG. 4B ). The channel lengths, channel widths, materials and thicknesses of the gate insulating films, materials used for the channel formation regions, and the like of the transistors Tr2, Tr4, and Tr5 may be determined so that the current flowing through the light-emitting element EL1 is controlled mainly in accordance with the current driving capability of the transistor Tr2.

[0098] In the display device of one embodiment of the present invention, the variation in threshold voltage of the transistor Tr2 is corrected in each of a plurality of pixels included in the display portion, so that the variation in luminance due to the variation in transistor characteristics can be suppressed, and excellent display quality can be achieved.

[0099] <Light-Quenching Operation> The light-emitting element EL1 can continue to emit light during one frame period. This driving method is also called a "hold type" or "hold-type driving." By using the hold-type driving method for the display device, it is possible to reduce flicker on the display screen. On the other hand, hold-type driving is prone to causing afterimages and blurred images when displaying moving images. The resolution perceived by humans when displaying moving images is also called "moving image resolution." In other words, hold-type driving is prone to reducing moving image resolution.

[0100] Also known is "black insertion driving," which reduces the afterimage and blurred images in moving image displays. "Black insertion driving" is also called "pseudo-impulse type" or "pseudo-impulse type driving." Black insertion driving is a driving method in which black is inserted every other frame, or black is displayed for a certain period of time within one frame.

[0101] The transistor Tr5 can be turned off by applying a low potential signal to the wiring Vem1 electrically connected to the gate electrode of the transistor Tr5, which stops the current flowing through the light-emitting element EL1 and allows black insertion.

[0102] Furthermore, even when the frame frequency is reduced to display a still image, only transistor Tr5 may be controlled at high speed to periodically cut off the current flowing through light-emitting element EL1 at a high frequency, thereby performing black insertion driving.

[0103] Here, the case where the frame frequency is 1 Hz will be described, for example. By applying a high-potential signal and a low-potential signal at a frequency higher than 1 Hz, for example, 60 Hz, to the wiring Vem1 electrically connected to the gate electrode of the transistor Tr5, it is possible to insert black display at a cycle of 60 Hz within one frame period. By performing black insertion driving at a high frequency, it is possible to make changes in luminance within one frame period less visible, even when the frame frequency is low and one frame period is long.

[0104] Note that when an OS transistor is used as the transistor Tr2, the hysteresis of the transistor Tr2 is extremely small, and therefore, when the frame frequency is low, such as when a still image is displayed, a change in luminance can be kept small. Therefore, excellent display quality may be achieved without high-speed black insertion driving using the transistor Tr5. Therefore, during the period when a still image is displayed, the circuit unit that supplies a signal to the wiring Vem1 electrically connected to the gate electrode of the transistor Tr5 can be stopped, thereby further reducing the power consumption of the driver circuit.

[0105] [Transistor] An oxide semiconductor that can be used for an OS transistor will be described below. The following metal oxides or the like can be used as an oxide semiconductor for an OS transistor.

[0106] The metal oxide used in the OS transistor preferably contains at least indium or zinc. The metal oxide more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, an element M (M is one or more elements selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. The element M is preferably one or more elements selected from gallium, aluminum, yttrium, and tin, and more preferably gallium.

[0107] The composition of the metal oxide significantly affects the electrical characteristics and reliability of the transistor. For example, increasing the indium content of the metal oxide may result in a transistor with a high on-state current, which is preferable.

[0108] Furthermore, for example, by increasing the content of element M in the metal oxide, the band gap of the metal oxide becomes larger, which may lead to realization of a transistor with even lower off-leakage current, which is preferable.

[0109] An OS transistor can be preferably used as the transistor Tr2, particularly an OS transistor containing a high content of indium in metal oxide.

[0110] The transistor Tr2 has a function of controlling the drive current of the light-emitting element EL1. By using an OS transistor with a high content of indium, which is a metal oxide, as the transistor Tr2, the current drive capability of the transistor Tr2 can be improved, and the luminance of the light-emitting element EL1 can be sufficiently increased.

[0111] OS transistors can be preferably used as the transistors Tr3, Tr6, and Tr1. In particular, OS transistors containing a high content of the element M of metal oxide can be preferably used as the transistors Tr3, Tr6, and Tr1.

[0112] When the transistor Tr3 is in an off state, the transistor Tr3 has a function of holding the potential applied to the gate electrode of the transistor Tr2. If the off-leak current of the transistor Tr3 is high, for example, the potential of the gate electrode of the transistor Tr2 may decrease due to the leakage current, which may result in a decrease in the luminance of the light-emitting element EL1. Therefore, it is preferable to use a transistor with a low off-leak current as the transistor Tr3.

[0113] The transistors Tr6 and Tr1 are electrically connected to the wiring Vini and the wiring Vdata, respectively. Therefore, if the off-leak currents of the transistors Tr6 and Tr1 are high, for example, a portion of the current flowing through the light-emitting element EL1 may leak to the wiring Vini and the wiring Vdata, which may cause fluctuations in luminance. Therefore, it is preferable to use transistors with low off-leak currents as the transistors Tr6 and Tr1.

[0114] Moreover, Si transistors may be used as the transistors Tr3, Tr6, and Tr1.

[0115] The transistors Tr4 and Tr5 can be preferably Si transistors, particularly transistors having crystalline silicon in their channel formation regions, or OS transistors, particularly OS transistors having a high indium content in metal oxide.

[0116] It is preferable that the transistors Tr4 and Tr5 have sufficient current driving capability so as not to limit the amount of current through the transistor Tr2. Therefore, transistors having crystalline silicon (e.g., polycrystalline silicon and single crystal silicon) in their channel formation regions can be preferably used as the transistors Tr4 and Tr5. For example, a transistor having low temperature polysilicon (LTPS) can be used as a transistor having polycrystalline silicon.

[0117] When OS transistors are used as the transistors Tr4 and Tr5, the indium content of the metal oxide is preferably increased to increase the current driving capability of the OS transistors.

[0118] The metal oxide that can be used in an OS transistor will be described in detail later.

[0119] [Pixel Configuration Example 2] Fig. 5A shows a pixel configuration example. The pixel Px shown in Fig. 5A has a pixel circuit 51 and a light-emitting element EL1. The pixel circuit 51 has transistors Tr1, Tr2, Tr6 and a capacitor C1.

[0120] 5A, a first terminal of the transistor Tr2 is electrically connected to the light-emitting element EL1, a second terminal of the transistor Tr2 is electrically connected to the wiring Vdd, a first terminal of the transistor Tr1 is electrically connected to the wiring Vdata, and a second terminal of the transistor Tr2 is electrically connected to the gate of the transistor Tr2.

[0121] An OS transistor can be preferably used as the transistor Tr2, particularly an OS transistor containing a high content of indium in metal oxide.

[0122] OS transistors having a high content of the element M of metal oxide can be preferably used as the transistors Tr6 and Tr1.

[0123] Alternatively, an OS transistor having a high content of indium in metal oxide can be preferably used as the transistor Tr6. By using an OS transistor having a high content of indium in metal oxide as the transistor Tr6, a display device with high display quality can be realized even when displaying at a high frequency.

[0124] The pixel configuration example shown in FIG. 5B differs from that shown in FIG. 5A in that it includes a transistor Tr7.

[0125] The transistor Tr7 has a gate electrode electrically connected to the wiring Vscan3, a first terminal electrically connected to the wiring Vini, and a second terminal electrically connected to the gate of the transistor Tr2 and the second electrode of the capacitor C1. An OS transistor having a high content of a metal oxide element M can be preferably used as the transistor Tr7. Alternatively, an OS transistor having a high content of indium in the metal oxide can be preferably used as the transistor Tr7.

[0126] [Display Device] A structural example of a display device using a pixel according to one embodiment of the present invention will be described.

[0127] 6 shows a block diagram of the display device 10. The display device 10 has a display unit 11, a first drive circuit 12, and a second drive circuit 13.

[0128] A plurality of pixels Px are arranged in a matrix in the display section 11. Each pixel includes at least one display element and one transistor. The display element may typically be an organic EL element or a liquid crystal element.

[0129] The first driver circuit 12 includes a circuit that functions as a source driver. The first driver circuit 12 has a function of generating a gray scale signal based on a video signal input from the outside and supplying the gray scale signal to the pixels of the display unit 11.

[0130] The second driver circuit 13 includes a circuit that functions as a gate driver. The second driver circuit 13 has a function of generating a selection signal based on a signal input from the outside and supplying the selection signal to the pixels of the display unit 11.

[0131] It is preferable to apply the above-described pixels Px as the pixels Px of the display unit 11 .

[0132] An OS transistor or the like can be used for the first driver circuit 12. Since a source driver or a demultiplexer circuit requires high-speed switching operation, it is preferable to use an OS transistor in which a metal oxide with a high indium content is used for a semiconductor layer as the OS transistor used for the second driver circuit 13.

[0133] A transistor having silicon in a channel formation region can be used for the first driver circuit 12. The first driver circuit 12 may include both OS transistors and Si transistors.

[0134] An OS transistor or the like can be used for the second driver circuit 13. Compared to a source driver circuit, a demultiplexer circuit, or the like, a gate driver does not require a switching operation with a high response speed. Therefore, a stable transistor with a low off-state current may be used as the OS transistor, and for example, an OS transistor in which a metal oxide with a high content of element M is used for a semiconductor layer can be used for the second driver circuit 13.

[0135] A transistor having silicon in a channel formation region can be used for the second driver circuit 13. The second driver circuit 13 may include both OS transistors and Si transistors.

[0136] If necessary, an OS transistor in which a metal oxide having a high content of indium is applied to a semiconductor layer may be used for the second driver circuit 13, or an OS transistor in which a metal oxide having a high content of element M is applied to a semiconductor layer may be used for the first driver circuit 12.

[0137] The display portion 11 is provided with a plurality of wirings Vdata connected to the first driver circuit 12 and a plurality of wirings GL connected to the second driver circuit 13. The wirings Vdata function as, for example, source lines, and the wirings GL function as, for example, gate lines.

[0138] <Configuration Example of First Drive Circuit> A more specific configuration example of the first drive circuit 12 included in the display device 10 will be described below.

[0139] The first drive circuit 12 includes a shift register circuit 31, a latch circuit section 41, a level shifter circuit section 42, a DA conversion section 43, an analog buffer circuit section 44, and the like.

[0140] The latch circuit section 41 has a plurality of latch circuits 32 and a plurality of latch circuits 33. The level shifter circuit section 42 has a plurality of level shifter circuits 34. The D-A conversion section 43 has a plurality of DAC circuits 35. The analog buffer circuit section 44 has a plurality of analog buffer circuits 36.

[0141] A clock signal CLK and a start pulse signal SP are input to the shift register circuit 31. The shift register circuit 31 generates a timing signal for sequentially shifting pulses in accordance with the clock signal CLK and the start pulse signal SP, and outputs the timing signal to each latch circuit 32 of the latch circuit unit 41.

[0142] The latch circuit section 41 receives the video signal S ０ , and a latch signal LAT are input.

[0143] When a timing signal is input to the latch circuit 32, the video signal S ０ is sampled and written in turn to each latch circuit 32. At this time, the video signal S ０ The period until the writing of all the data is completed can be called a line period.

[0144] When one line period is completed, the video signals held in each latch circuit 32 are simultaneously written into and held in each latch circuit 33 in accordance with the pulse of the latch signal LAT input to each latch circuit 33. After sending out the video signal to the latch circuit 33, the latch circuit 32 sequentially writes the next video signal in accordance with the timing signal from the shift register circuit 31. During this second one line period, the video signals written into and held in the latch circuit 33 are output to each level shifter circuit 34 of the level shifter circuit section 42.

[0145] The video signals input to each level shifter circuit 34 in the level shifter circuit section 42 have their voltage amplitude increased by the level shifter circuit 34, and are then sent to each DAC circuit 35 in the D-A conversion section 43. The video signals input to the group of DAC circuits 35 are converted to analog and output as a single analog signal to the analog buffer circuit section 44. The video signals input to the analog buffer circuit section 44 are output to each wiring Vdata via each analog buffer circuit 36.

[0146] On the other hand, the second driver circuit 13 sequentially selects each wiring GL. A video signal input from the first driver circuit 12 to the display unit 11 via the wiring Vdata is input to each pixel Px connected to the wiring GL selected by the second driver circuit 13.

[0147] Instead of the shift register circuit 31, other circuits capable of outputting signals in which pulses are shifted sequentially may be used.

[0148] <Modification of First Drive Circuit> The first drive circuit 12 illustrated in FIG. 6 is configured to convert a digital signal into an analog signal and output the signal to the display unit 11. However, by using an analog signal as the input signal, the configuration of the first drive circuit 12 can be further simplified.

[0149] 7A includes a shift register circuit 31, a latch circuit section 41, and a source follower circuit section 45. The source follower circuit section 45 includes a plurality of source follower circuits 37.

[0150] The latch circuit 32 outputs the analog video signal S in accordance with the timing signal from the shift register circuit 31. ０ The latch circuits 32 simultaneously output the video signals held in the latch circuits 33 in accordance with the latch signal LAT.

[0151] The video signal held in the latch circuit 33 is output to one wiring Vdata via a source follower circuit 37. Note that the source follower circuit 37 may be replaced by the analog buffer circuit described above.

[0152] The first drive circuit 12b shown in FIG. 7B includes a shift register circuit 31 and a demultiplexer circuit 46.

[0153] The demultiplexer circuit 46 has a plurality of sampling circuits 38. Each sampling circuit 38 receives a plurality of analog video signals S from a plurality of wires. ０ is input, and video signals are simultaneously output to a plurality of wirings Vdata in accordance with a timing signal input from the shift register circuit 31. The shift register circuit 31 outputs a timing signal so as to sequentially select a plurality of sampling circuits 38.

[0154] For example, the number of wirings Vdata connected to the display unit 11 is 2160, and the number of wirings S ０ When the number of wirings through which Vdata is supplied is 54, by providing 40 sampling circuits 38 in the demultiplexer circuit 46, one line period can be divided into 40 parts, and video signals can be output simultaneously to 54 wirings Vdata within each period.

[0155] Here, OS transistors may be used for the demultiplexer circuit 46, and Si transistors may be used for the shift register circuit 31. For example, consider a case where transistors having single crystal silicon are used for the shift register circuit 31, and OS transistors are used for the demultiplexer circuit 46 and the display unit 11. The OS transistors can be stacked over transistors having single crystal silicon, for example.

[0156] This is preferable because it allows reducing the number of wirings from the layer where the Si transistors that make up the shift register circuit 31 are provided to the layer where the OS transistors that make up the demultiplexer circuit 46 and the display unit 11 are provided.

[0157] The above is the description of the first drive circuit unit.

[0158] [Metal Oxide] The composition of a metal oxide that can be used for a semiconductor layer included in a transistor of one embodiment of the present invention will be described. Note that the composition of a metal oxide may be expressed by replacing it with the composition of a semiconductor layer.

[0159] The metal oxide preferably contains at least indium or zinc. The metal oxide more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, an element M (wherein M is one or more elements selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc.

[0160] Examples of metal oxides that can be used include indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, indium tin oxide containing silicon can be used.

[0161] The element M is preferably one or more elements selected from gallium, aluminum, yttrium, and tin, and more preferably gallium. Note that in this specification and the like, a metal oxide having indium, the element M, and zinc may be referred to as an In-M-Zn oxide.

[0162] The composition of the semiconductor layer significantly affects the electrical characteristics and reliability of the transistor.

[0163] <Indium Content> By increasing the indium content in the semiconductor layer, a transistor with a large on-state current can be realized.

[0164] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0165] By increasing the content of indium in the semiconductor layer, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a high on-state current, a display device with excellent electrical characteristics can be provided.

[0166] When an In-Zn oxide is used for the semiconductor layer, the indium content can be increased by using a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or any of these approximate values, can be used.

[0167] When an In-Sn oxide is used for the semiconductor layer, the indium content can be increased by using a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or any of these approximate values, can be used.

[0168] When an In-Sn-Zn oxide is used for the semiconductor layer, the indium content can be increased by using a metal oxide in which the atomic ratio of indium is higher than that of tin. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of tin. For example, the atomic ratios of metal elements are In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In :Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn=10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10, or metal oxides thereof having a ratio close to these can be used.

[0169] When an In-Al-Zn oxide is used for the semiconductor layer, the indium content can be increased by using a metal oxide in which the atomic ratio of indium is higher than that of aluminum. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, In In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10, or metal oxides thereof having a similar ratio can be used.

[0170] When an In-Ga-Zn oxide is used for the semiconductor layer, the indium content can be increased by using a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium.Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium.For example, the semiconductor layer may have atomic ratios of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1:6. , In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides in the vicinity of these can be used.

[0171] When an In-M-Zn oxide is used for the semiconductor layer, the indium content can be increased by using a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, the semiconductor layer may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, or In:M:Zn=6:1:6. , In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides in the vicinity of these can be used.

[0172] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0173] The indium content can be increased by using a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the contained metal elements is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-Ga-Zn oxide is used for the semiconductor layer, the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is preferably in the above-mentioned range.

[0174] <Transistor Reliability> One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature Stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0175] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0176] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0177] <Regarding the Content of Element M (1)> By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0178] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0179] The following is a possible reason why the use of a metal oxide containing no gallium or with a low gallium content in the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the semiconductor layer has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium bonds with excess oxygen in the gate insulating layer at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage. Note that by including gallium in the semiconductor layer, oxygen deficiency (V Ｏ) is less likely to occur.

[0180] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer, the gallium content can be reduced by applying a metal oxide in which the atomic ratio of indium is higher than that of gallium to the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratios of metal elements satisfy In > Ga and Zn > Ga to the semiconductor layer.

[0181] For example, the semiconductor layer may have an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn= The gallium content can be reduced by using metal oxides having a composition ratio of In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or a metal oxide having a composition ratio close to these.

[0182] The gallium content of the semiconductor layer can be reduced by using a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %.

[0183] A metal oxide that does not contain gallium may be used for the semiconductor layer. For example, In—Zn oxide may be used for the semiconductor layer. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide results in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Furthermore, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer. By using a metal oxide that does not contain gallium, fluctuations in threshold voltage, particularly in a PBTS test, can be made extremely small.

[0184] For example, the semiconductor layer can be made of an oxide containing indium and zinc, in which the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these values.

[0185] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where element M is used instead of gallium. For the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0186] By reducing the content of the element M in the semiconductor layer, a transistor having high reliability against application of a positive bias can be obtained. By applying the transistor to a transistor that is required to have high reliability against application of a positive bias, a display device having high reliability can be obtained.

[0187] <Regarding the Content of Element M (2)> Increasing the content of element M in the semiconductor layer can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be obtained. Specifically, a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. Furthermore, a larger band gap can sometimes further reduce the off-state current of the transistor. The band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, even more preferably 3.2 eV or more, even more preferably 3.3 eV or more, even more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0188] For example, the content of element M can be increased by using a metal oxide in which the atomic ratio of metal elements in the semiconductor layer is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a ratio close to these.

[0189] In particular, the semiconductor layer can increase the content of element M by suitably using a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0190] When an In—Ga—Zn oxide is used for the semiconductor layer, a metal oxide can be used in which the atomic ratio of indium to the atomic number of the metal element is equal to or less than the atomic ratio of gallium. For example, by using a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these, the content of element M can be increased.

[0191] In particular, the semiconductor layer can increase the content of element M by using a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0192] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0193] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is more than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is more than 0.1 and 2 or less, and the atomic ratio of zinc is more than 0.1 and 2 or less.

[0194] When a metal oxide is formed by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.

[0195] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0196] Second Embodiment A specific example of the configuration of a display device will be described below.

[0197] When a pixel of a display device has three types of subpixels that exhibit different colors, the three subpixels include, for example, subpixels of three colors: red (R), green (G), and blue (B), and subpixels of three colors: yellow (Y), cyan (C), and magenta (M). When a pixel of a display device has four subpixels, the four subpixels include, for example, subpixels of four colors: red (R), green (G), blue (B), and white (W), and subpixels of four colors: red (R), green (G), blue (B), and yellow (Y). Each subpixel has a light-emitting device.

[0198] The layout of pixels in a display device will now be described. The arrangement of sub-pixels in a pixel is not particularly limited, and various methods can be applied. Examples of sub-pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0199] Examples of the top surface shape of the subpixel include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon or a hexagon, a polygon with rounded corners, an ellipse, or a circle. Here, the top surface shape of the subpixel corresponds to the top surface shape of the light-emitting region of the light-emitting device.

[0200] The pixel 310 shown in FIG. 8A has a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). The pixel 310 shown in FIG. 8A is arranged in a stripe pattern. The arrangement order of the sub-pixels is not limited to the configuration shown in FIG. 8A. Although FIG. 8A shows a configuration in which the sub-pixels have the same area, the sub-pixels may have different areas. Here, the area of ​​the sub-pixel corresponds to the area of ​​the light-emitting region of the light-emitting device. In FIG. 8A, the symbols R, G, and B are assigned within the area of ​​each sub-pixel light-emitting element to easily distinguish between the sub-pixels.

[0201] The pixel 310 shown in Fig. 8B has a configuration in which an S-stripe arrangement is applied. The pixel 310 shown in Fig. 8B is configured with two rows and two columns, with two subpixels (subpixel (R) and subpixel (G)) in the left column (first column) and one subpixel (subpixel (B)) in the right column (second column). In other words, the pixel 310 has two subpixels (subpixel (R) and subpixel (B)) in the top row (first row) and two subpixels (subpixel (G) and subpixel (B)) in the bottom row (second row), with the subpixel (B) spanning these two rows.

[0202] 8B shows an example in which the area of ​​the subpixel (B) is larger than the areas of the subpixels (R) and (G). This configuration is suitable for use when the life of the light-emitting device emitting blue light is shorter than the life of the light-emitting device emitting red light and the light-emitting device emitting green light. In the subpixel (B) with a larger light-emitting area, the current density applied to the light-emitting device emitting blue light is lower, and therefore the life of the light-emitting device can be extended. In other words, a highly reliable display device can be obtained.

[0203] 8B shows a configuration in which the area of ​​the subpixel (B) is larger than the areas of the subpixels (R) and (G), but one embodiment of the present invention is not limited to this. The area of ​​a subpixel can be determined depending on the lifetime of a light-emitting device included in the subpixel. It is preferable to make the area of ​​a subpixel having a light-emitting device with a short lifetime larger than the areas of the other subpixels.

[0204] 8C shows two pixels in which subpixels of each color are arranged in a zigzag pattern. Specifically, in each column, subpixels of different colors are arranged in odd-numbered rows and even-numbered rows.

[0205] FIG. 8D shows a pixel to which a Pentile arrangement is applied. The pixel shown in FIG. 8D has two pixels, pixel 310A and pixel 310B, each having three subpixels: a red subpixel (R), a green subpixel (G), and a blue subpixel (B). The two pixels, pixel 310A and pixel 310B, each have one subpixel (R), two subpixels (G), and one subpixel (B). This configuration allows the area of ​​the subpixels to be increased while maintaining a pseudo-high resolution, thereby reducing the required processing accuracy. In other words, compared with the same processing accuracy, it is possible to manufacture a display device with higher resolution. Furthermore, the number of transistors per area can be reduced, thereby improving productivity. Therefore, a pseudo-high-resolution display device can be manufactured with high productivity.

[0206] The pixel 310 also includes a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), as well as an infrared sub-pixel (IR) and a light-detecting pixel (PS) (see FIG. 8E). The pixel PS includes a light-receiving element.

[0207] The sub-pixel (IR) that emits infrared light can be used as a light source, and the infrared light emitted by the sub-pixel can be detected by the light-detecting pixel (PS).

[0208] 8E shows an example in which the aperture ratio of the light-detecting pixel (PS) is the lowest among the red sub-pixel (R), the green sub-pixel (G) and the blue sub-pixel (B), the infrared sub-pixel (IR), and the light-detecting pixel (PS). A narrow light-receiving area of ​​the light-detecting pixel (PS) narrows the imaging range, thereby reducing blurring in the imaging result and improving resolution. This is preferable because it enables high-definition or high-resolution imaging. The aperture ratios of the red sub-pixel (R), the green sub-pixel (G) and the blue sub-pixel (B), the infrared sub-pixel (IR), and the light-detecting pixel (PS) can each be determined appropriately.

[0209] 8E includes a pixel 310 including a light-emitting element (also referred to as a light-emitting device) and a light-receiving element (also referred to as a light-receiving device). In the display device of one embodiment of the present invention, the pixel has a light-receiving function, and thus it is possible to detect contact or proximity of an object while displaying an image. Furthermore, the display device of one embodiment of the present invention includes subpixels that emit infrared light, and thus it is possible to display an image while emitting infrared light as a light source using the subpixels included in the display device. In other words, the display device of one embodiment of the present invention has a high affinity with functions other than the display function (here, the light-receiving function).

[0210] The light receiving element included in the pixel 310 shown in FIG. 8E may be used as a touch sensor or a non-contact sensor.

[0211] Here, a touch sensor or non-contact sensor can detect the proximity or contact of an object (such as a finger, hand, or pen). A touch sensor can detect an object when the electronic device and the object are in direct contact with each other. A non-contact sensor can detect an object even if the object does not come into contact with the electronic device. For example, a configuration is preferred in which the display device (or electronic device) can detect the object when the distance between the display device (or electronic device) and the object is between 0.1 mm and 300 mm, preferably between 3 mm and 50 mm. This configuration enables the electronic device to be operated without the object directly touching it, in other words, the display device can be operated in a non-contact (touchless) manner. This configuration reduces the risk of the electronic device becoming dirty or scratched, or enables the electronic device to be operated without the object directly touching dirt (e.g., dust, viruses, etc.) attached to the electronic device.

[0212] The non-contact sensor function can also be called a hover sensor function, a hover-touch sensor function, a near-touch sensor function, a touchless sensor function, etc. The touch sensor function can also be called a direct touch sensor function, etc.

[0213] 9A and 9B illustrate a display device according to one embodiment of the present invention.

[0214] 9A shows a top view of a display device 300. The display device 300 has a display section in which a plurality of pixels 310 are arranged in a matrix, and a connection section 340 on the outside of the display section. One pixel 310 is composed of three subpixels: subpixel 310a, subpixel 310b, and subpixel 310c. Note that the pixel is not limited to the configuration shown in FIG. 9A.

[0215] 9A shows an example in which the connection portion 340 is located below the display portion when viewed from above, but this is not particularly limited. The connection portion 340 may be provided in at least one location on the upper, right, left, or lower side of the display portion when viewed from above, and may be provided so as to surround all four sides of the display portion. The connection portion 340 may be singular or plural.

[0216] Fig. 9B shows a cross-sectional view taken along dashed lines X1-X2 and Y1-Y2 in Fig. 9A. As modified examples, Figs. 10A to 10C, 11A and 11B, and 12A to 12C show cross-sectional views taken along dashed lines X1-X2 and Y1-Y2 in Fig. 9A.

[0217] 9B , in display device 300, light-emitting devices 330a, 330b, and 330c are provided on transistor-containing layer 301, and protective layer 331 is provided to cover these light-emitting devices. Substrate 320 is bonded to protective layer 331 with resin layer 322. In addition, insulating layer 325 and insulating layer 327 on insulating layer 325 are provided in the region between two adjacent light-emitting devices.

[0218] The display device of one embodiment of the present invention may be any of a top emission type that emits light in a direction opposite to a substrate on which a light-emitting device is formed, a bottom emission type that emits light toward a substrate on which a light-emitting device is formed, and a dual emission type that emits light from both sides.

[0219] The layer 301 including transistors can have, for example, a stacked structure in which a plurality of transistors are provided on a substrate and an insulating layer is provided to cover these transistors. The layer 301 including transistors may have a recess between two adjacent devices. For example, a recess may be provided in an insulating layer located on the top surface of the layer 301 including transistors. The transistor described in Embodiment 1 can be used as the transistor.

[0220] A light-emitting device has an EL layer between a pair of electrodes, one of which may be referred to as a pixel electrode and the other as a common electrode in this specification and the like.

[0221] A light-emitting device has a pair of electrodes, one of which functions as an anode and the other as a cathode. In the following, an example will be described in which the pixel electrode functions as the anode and the common electrode functions as the cathode.

[0222] The light-emitting device 330a includes a conductive layer 311a on the layer 301 including the transistor, a first layer 313a on the conductive layer 311a, a fourth layer 314 on the first layer 313a, and a common electrode 315 on the fourth layer 314. The conductive layer 311a functions as a pixel electrode. In the light-emitting device 330a, the first layer 313a and the fourth layer 314 can be collectively referred to as an EL layer.

[0223] The first layer 313a may include, for example, a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer, or may include, for example, a first light-emitting unit, a charge generation layer, and a second light-emitting unit.

[0224] The fourth layer 314 may include, for example, an electron injection layer, or may include a stack of an electron transport layer and an electron injection layer.

[0225] The light-emitting device 330b includes a conductive layer 311b on the layer 301 including the transistor, an island-shaped second layer 313b on the conductive layer 311b, a fourth layer 314 on the island-shaped second layer 313b, and a common electrode 315 on the fourth layer 314. The conductive layer 311b functions as a pixel electrode. In the light-emitting device 330b, the second layer 313b and the fourth layer 314 can be collectively referred to as an EL layer.

[0226] The light-emitting device 330c includes a conductive layer 311c on the layer 301 including the transistor, an island-shaped third layer 313c on the conductive layer 311c, a fourth layer 314 on the island-shaped third layer 313c, and a common electrode 315 on the fourth layer 314. The conductive layer 311c functions as a pixel electrode. In the light-emitting device 330c, the third layer 313c and the fourth layer 314 can be collectively referred to as an EL layer.

[0227] The fourth layer 314 is a layer shared by all the light-emitting devices. As described above, the fourth layer 314 includes, for example, an electron injection layer. Alternatively, the fourth layer 314 may include a stack of an electron transport layer and an electron injection layer.

[0228] The common electrode 315 is electrically connected to the conductive layer 323 provided in the connection portion 340. As a result, the same potential is supplied to the common electrode 315 of each light-emitting device. Note that FIG. 9B shows an example in which a fourth layer 314 is provided on the conductive layer 323, and the conductive layer 323 and the common electrode 315 are electrically connected via the fourth layer 314. The fourth layer 314 does not have to be provided in the connection portion 340. For example, FIG. 10C shows an example in which the fourth layer 314 is not provided on the conductive layer 323, and the conductive layer 323 and the common electrode 315 are directly connected.

[0229] For example, by using a mask for defining a deposition area (also called an area mask or a rough metal mask), the regions where the fourth layer 314 and the common electrode 315 are deposited can be changed.

[0230] The side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c are covered with the insulating layer 325 and the insulating layer 327. This prevents the fourth layer 314 (or the common electrode 315) from contacting any of the side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c, thereby preventing short circuits in the light-emitting device. This improves the reliability of the light-emitting device.

[0231] The insulating layer 325 preferably covers at least the side surfaces of the conductive layers 311a to 311c. Furthermore, the insulating layer 325 preferably covers the side surfaces of the first layer 313a, the second layer 313b, and the third layer 313c. The insulating layer 325 can be in contact with the side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c.

[0232] The insulating layer 327 is provided over the insulating layer 325 so as to fill recesses formed in the insulating layer 325. The insulating layer 327 can overlap with side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c with the insulating layer 325 interposed therebetween.

[0233] By providing the insulating layers 325 and 327, the gap between adjacent island-shaped layers can be filled, which reduces the unevenness of the surface on which a layer (such as a common electrode) is formed on the island-shaped layer, making the surface flatter. Therefore, coverage of the common electrode can be improved, and discontinuity of the common electrode can be prevented.

[0234] The insulating layer 325 or the insulating layer 327 can be provided so as to be in contact with the island-shaped layer. This can prevent the island-shaped layer from peeling off. The insulating layer and the island-shaped layer are in close contact with each other, which has the effect of fixing or bonding the adjacent island-shaped layers together.

[0235] An organic resin film is suitable for the insulating layer 327. If the side surface of the EL layer and the photosensitive organic resin film are in direct contact with each other, organic solvents that may be contained in the photosensitive organic resin film may damage the EL layer. By using an aluminum oxide film formed by atomic layer deposition (ALD) for the insulating layer 325, it is possible to prevent the photosensitive organic resin film used for the insulating layer 327 from being in direct contact with the side surface of the EL layer. This makes it possible to prevent the EL layer from being dissolved by an organic solvent.

[0236] Note that either the insulating layer 325 or the insulating layer 327 does not necessarily have to be provided. For example, by forming the insulating layer 325 to have a single-layer structure using an inorganic material, the insulating layer 325 can be used as a protective insulating layer for the EL layer. This can improve the reliability of the display device. Furthermore, by forming the insulating layer 327 to have a single-layer structure using an organic material, for example, the insulating layer 327 can fill the gap between adjacent EL layers and achieve planarization. This can improve the coverage of a common electrode (upper electrode) formed over the EL layer and the insulating layer 327.

[0237] The fourth layer 314 and the common electrode 315 are provided over the first layer 313a, the second layer 313b, the third layer 313c, the insulating layer 325, and the insulating layer 327. Before the insulating layer 325 and the insulating layer 327 are provided, a step is generated between a region where the pixel electrode and the EL layer are provided and a region where the pixel electrode and the EL layer are not provided (a region between light-emitting devices). In the display device of one embodiment of the present invention, the insulating layer 325 and the insulating layer 327 can flatten the step, thereby improving the coverage of the fourth layer 314 and the common electrode 315. Therefore, poor connection due to a step can be suppressed. Alternatively, an increase in electrical resistance caused by a local thinning of the common electrode 315 due to the step can be suppressed.

[0238] In order to improve the flatness of the surfaces on which the fourth layer 314 and the common electrode 315 are formed, it is preferable that the height of the upper surface of the insulating layer 325 and the upper surface of the insulating layer 327 be equal to or approximately equal to the height of the upper surface of at least one of the first layer 313a, the second layer 313b, and the third layer 313c. The upper surface of the insulating layer 327 preferably has a flat shape, and may have a convex portion, a convex curved surface, a concave curved surface, or a concave portion.

[0239] The insulating layer 325 has regions in contact with side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c, and functions as a protective insulating layer for the first layer 313 a, the second layer 313 b, and the third layer 313 c. By providing the insulating layer 325, impurities (oxygen, moisture, and the like) can be prevented from entering the inside from the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c, thereby providing a highly reliable display device.

[0240] If the width (thickness) of the insulating layer 325 in the region in contact with the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c is large in a cross-sectional view, the distance between the first layer 313 a, the second layer 313 b, and the third layer 313 c increases, which may result in a low aperture ratio. Also, if the width (thickness) of the insulating layer 325 is small, the effect of suppressing impurities from penetrating into the interior from the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c may be reduced. The width (thickness) of the insulating layer 325 in the region in contact with the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c is preferably 3 nm to 200 nm, more preferably 3 nm to 150 nm, further preferably 5 nm to 150 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, and further preferably 10 nm to 50 nm. By setting the width (thickness) of the insulating layer 325 in the above range, a display device having a high aperture ratio and high reliability can be obtained.

[0241] The insulating layer 325 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 325. The insulating layer 325 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, aluminum oxide is preferable because it has a high etching selectivity with respect to the EL layer and functions to protect the EL layer in the formation of the insulating layer 327 described below. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 325, it is possible to form an insulating layer 325 with few pinholes and excellent protection of the EL layer. The insulating layer 325 may also have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 325 may have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0242] The insulating layer 325 can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, an ALD method, or the like. The insulating layer 325 is preferably formed by an ALD method, which has good coverage.

[0243] The insulating layer 327 provided on the insulating layer 325 has the function of planarizing recesses formed in the insulating layer 325 between adjacent light-emitting devices. In other words, the insulating layer 327 has the effect of improving the flatness of the surface on which the common electrode 315 is formed. An insulating layer containing an organic material can be suitably used for the insulating layer 327. For example, the insulating layer 327 can be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. Alternatively, the insulating layer 327 can be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Alternatively, the insulating layer 327 can be made of a photosensitive resin. The photosensitive resin can be a photoresist. The photosensitive resin can be a positive-type material or a negative-type material.

[0244] The difference in height between the top surface of the insulating layer 327 and the top surface of any of the first layer 313a, the second layer 313b, and the third layer 313c is, for example, preferably 0.5 times or less, more preferably 0.3 times or less, the thickness of the insulating layer 327. For example, the insulating layer 327 may be provided so that the top surface of any of the first layer 313a, the second layer 313b, and the third layer 313c is higher than the top surface of the insulating layer 327. For example, the insulating layer 327 may be provided so that the top surface of the insulating layer 327 is higher than the top surface of the light-emitting layer included in the first layer 313a, the second layer 313b, or the third layer 313c.

[0245] 10A shows an example in which the insulating layer 325 is not provided. In the case where the insulating layer 325 is not provided, the insulating layer 327 can be in contact with the side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c. The insulating layer 327 can be provided to fill the spaces between the EL layers of the light-emitting devices.

[0246] In this case, it is preferable to use an organic material that causes less damage to the first layer 313 a, the second layer 313 b, and the third layer 313 c for the insulating layer 327. For example, it is preferable to use an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin for the insulating layer 327.

[0247] FIG. 10B shows an example in which the insulating layer 327 is not provided.

[0248] It is preferable to provide a protective layer 331 on the light emitting devices 330a, 330b, and 330c. By providing the protective layer 331, the reliability of the light emitting devices can be improved.

[0249] There is no restriction on the conductivity of the protective layer 331. The protective layer 331 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0250] By having the protective layer 331 be an inorganic film, it is possible to prevent oxidation of the common electrode 315 and to prevent impurities (moisture, oxygen, etc.) from entering the light-emitting devices 330a, 330b, and 330c, thereby suppressing deterioration of the light-emitting devices and improving the reliability of the display device.

[0251] The protective layer 331 can be made of an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film. Examples of the insulating oxide film include a silicon oxide film, an aluminum oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.

[0252] The protective layer 331 preferably includes an insulating nitride film or an insulating nitride oxide film, and more preferably includes an insulating nitride film.

[0253] An inorganic film containing In—Sn oxide (also referred to as ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), or the like can also be used for the protective layer 331. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0254] When light emitted from the light-emitting device is extracted through the protective layer 331, it is preferable that the protective layer 331 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0255] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 331. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0256] Furthermore, the protective layer 331 may include an organic film. For example, the protective layer 331 may include both an organic film and an inorganic film.

[0257] Since the upper end portions of the conductive layers 311 a to 311 c are not covered with an insulating layer, the distance between adjacent light-emitting devices can be made extremely narrow, thereby enabling a high-definition or high-resolution display device.

[0258] As shown in FIGS. 11A and 11B, the end portions of the conductive layers 311a to 311c may be covered with an insulating layer 321.

[0259] The insulating layer 321 can have a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating film and an organic insulating film.

[0260] Examples of organic insulating materials that can be used for the insulating layer 321 include acrylic resins, epoxy resins, polyimide resins, polyamide resins, polyimideamide resins, polysiloxane resins, benzocyclobutene-based resins, and phenolic resins. In addition, as an inorganic insulating film that can be used for the insulating layer 321, an inorganic insulating film that can be used for the protective layer 331 can be used.

[0261] When an inorganic insulating film is used as the insulating layer 321 covering the edge of the pixel electrode, impurities are less likely to enter the light-emitting device than when an organic insulating film is used, thereby improving the reliability of the light-emitting device. When an organic insulating film is used as the insulating layer 321 covering the edge of the pixel electrode, step coverage is higher and the insulating layer is less affected by the shape of the pixel electrode than when an inorganic insulating film is used. Therefore, short circuits in the light-emitting device can be prevented. Specifically, when an organic insulating film is used as the insulating layer 321, the insulating layer 321 can be processed into a tapered shape or the like. Note that, in this specification, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined with respect to the substrate surface. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0262] Note that the insulating layer 321 does not necessarily have to be provided. By not providing the insulating layer 321, the aperture ratio of the sub-pixels can be increased in some cases. Alternatively, the distance between the sub-pixels can be narrowed, and the definition or resolution of the display device can be improved in some cases.

[0263] Although FIG. 11A shows an example in which the fourth layer 314 penetrates into the region between the first layer 313a and the second layer 313b, a void 334 may be formed in the region as shown in FIG. 11B.

[0264] The void 334 contains, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and a Group 18 element (typically, helium, neon, argon, xenon, krypton, etc.). Alternatively, a resin or the like may be embedded in the void 334.

[0265] 9A and the like show an example in which the end portion of the conductive layer 311a and the end portion of the first layer 313a are aligned or substantially aligned. In other words, the top surface shapes of the conductive layer 311a and the first layer 313a are aligned or substantially aligned.

[0266] There is no particular limitation on the size relationship between the conductive layer 311a and the first layer 313a, the conductive layer 311b and the second layer 313b, the conductive layer 311c and the third layer 313c, etc. Fig. 12A shows an example in which the end of the first layer 313a is located inside the end of the conductive layer 311a. In Fig. 12A, the end of the first layer 313a is located on the conductive layer 311a. Fig. 12B shows an example in which the end of the first layer 313a is located outside the end of the conductive layer 311a. In Fig. 12B, the first layer 313a is provided so as to cover the end of the conductive layer 311a.

[0267] In addition, when the edges are aligned or approximately aligned, and when the top surface shapes are the same or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, it is also said that the edges are approximately aligned, or the top surface shapes are approximately aligned.

[0268] 12C shows a modified example of insulating layer 327. In Fig. 12C, the upper surface of insulating layer 327 has a shape that gradually bulges toward the center, i.e., a convex curved surface, in a cross-sectional view, and a shape that is recessed at the center and its vicinity, i.e., a concave curved surface.

[0269] 13A to 13F show the cross-sectional structure of a region 139 including the insulating layer 327 and its surroundings.

[0270] 13A shows an example in which the first layer 313a and the second layer 313b have different thicknesses. The height of the top surface of the insulating layer 325 on the first layer 313a side is the same as or approximately the same as the top surface of the first layer 313a, and the height of the top surface of the second layer 313b on the second layer 313b side is the same as or approximately the same as the top surface of the second layer 313b. The top surface of the insulating layer 327 has a gentle slope, with the first layer 313a side being higher and the second layer 313b side being lower. In this way, the heights of the insulating layers 325 and 327 are preferably aligned with the top surfaces of the adjacent EL layers. Alternatively, the heights may be aligned with the top surface of one of the adjacent EL layers, resulting in a flat portion.

[0271] 13B, the upper surface of insulating layer 327 has a region that is higher than the upper surface of first layer 313a and the upper surface of second layer 313b. As shown in Fig. 13B, the upper surface of insulating layer 327 can be configured such that the center and its vicinity bulge in cross section, that is, have a shape with a convex curve.

[0272] 13C , the upper surface of insulating layer 327 has a shape that gradually bulges toward the center, i.e., a convex curved surface, and a shape that is recessed in the center and its vicinity, i.e., a concave curved surface, in a cross-sectional view. Insulating layer 327 has a region that is higher than the upper surface of first layer 313a and the upper surface of second layer 313b. In region 139, the display device also has at least one of sacrificial layer 318a and sacrificial layer 319a, and has a first region where insulating layer 327 is higher than the upper surfaces of first layer 313a and second layer 313b and located outside insulating layer 325, and the first region is located on at least one of sacrificial layer 318a and sacrificial layer 319a. In addition, in region 139, the display device has at least one of sacrificial layer 318b and sacrificial layer 319b, and has a second region in which insulating layer 327 is higher than the top surface of the first layer 313a and the top surface of the second layer 313b and is located outside insulating layer 325, and the second region is located on at least one of sacrificial layer 318b and sacrificial layer 319b.

[0273] 13D , the upper surface of insulating layer 327 has an area that is lower than the upper surfaces of first layer 313 a and second layer 313 b. In addition, the upper surface of insulating layer 327 has a recessed shape in the center and its vicinity, i.e., a shape having a concave curved surface, in a cross-sectional view.

[0274] 13E, the upper surface of the insulating layer 325 has a region higher than the upper surface of the first layer 313a and the upper surface of the second layer 313b. That is, the insulating layer 325 protrudes from the surface on which the fourth layer 314 is to be formed, forming a convex portion.

[0275] When forming the insulating layer 325, for example, if the insulating layer 325 is formed so that its height is aligned or approximately aligned with that of the sacrificial layer, the insulating layer 325 may be formed in a protruding shape as shown in FIG. 13E.

[0276] 13F, the upper surface of the insulating layer 325 has an area lower than the upper surfaces of the first layer 313a and the second layer 313b. That is, the insulating layer 325 forms a recess on the surface where the fourth layer 314 is to be formed.

[0277] In this way, the insulating layer 325 and the insulating layer 327 can be applied to various shapes.

[0278] The sacrificial layer may be, for example, a metal film, an alloy film, a metal oxide film, a semiconductor film, or an inorganic film such as an inorganic insulating film.

[0279] The sacrificial layer can be made of a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or an alloy material containing such a metal material.

[0280] The sacrificial layer can be made of a metal oxide such as In—Ga—Zn oxide. For example, an In—Ga—Zn oxide film can be formed as the sacrificial layer by sputtering. Furthermore, indium oxide, In—Zn oxide, In—Sn oxide, indium titanium oxide (In—Ti oxide), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), etc. can also be used. Alternatively, indium tin oxide containing silicon can also be used.

[0281] Instead of the gallium, an element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used. In particular, it is preferable that M is one or more elements selected from gallium, aluminum, and yttrium.

[0282] The sacrificial layer can be made of any of various inorganic insulating films that can be used for the protective layer 331. In particular, an oxide insulating film is preferable because it has higher adhesion to the EL layer than a nitride insulating film. For example, an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide can be used for the sacrificial layer. For example, an aluminum oxide film can be formed as the sacrificial layer by using the ALD method. The ALD method is preferable because it can reduce damage to the base (particularly the EL layer, etc.). For example, a silicon nitride film can be formed as the sacrificial layer by using the sputtering method.

[0283] For example, the sacrificial layer may be a stacked structure of an inorganic insulating film (e.g., an aluminum oxide film) formed by ALD and an In—Ga—Zn oxide film formed by sputtering, or a stacked structure of an inorganic insulating film (e.g., an aluminum oxide film) formed by ALD and an aluminum film, a tungsten film, or an inorganic insulating film (e.g., a silicon nitride film) formed by sputtering.

[0284] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0285] In this specification and the like, a structure in which different light-emitting layers are fabricated or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the freedom of material and configuration selection and facilitating improvements in brightness and reliability.

[0286] In this specification and the like, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. Note that a white light-emitting device can be combined with a colored layer (for example, a color filter) to realize a full-color display device.

[0287] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light, the light-emitting layers may be selected so that the light emitted by each of the two light-emitting layers has a complementary color relationship. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration in which the light-emitting device as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light, the light-emitting device as a whole may be configured so that the light-emitting colors of the three or more light-emitting layers are combined to emit white light.

[0288] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0289] Furthermore, by combining a white light-emitting device (either a single structure or a tandem structure, or both), a color filter, and the MML structure of one embodiment of the present invention, a display device having a high contrast ratio can be obtained.

[0290] When the above-described white light-emitting device (single structure or tandem structure) is compared with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. When it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0291] In particular, by applying the SBS structure to a light-emitting device with an MML structure, the layer provided between the light-emitting elements (for example, an organic layer used in common between the light-emitting elements, also called a common layer) is configured to be separated, thereby enabling a display with no side leakage or extremely little side leakage.

[0292] The display device of this embodiment can reduce the distance between light-emitting devices. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of the first layer 313 a and the side surface of the second layer 313 b or the distance between the side surface of the second layer 313 b and the side surface of the third layer 313 c has a region of 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100 nm or less.

[0293] A light-shielding layer may be provided on the surface of substrate 320 facing resin layer 322. Various optical components may be disposed on the outside of substrate 320. Examples of optical components include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. The outside of substrate 320 may also be provided with an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses scratches during use, an impact absorbing layer, and the like.

[0294] The substrate 320 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. Using a flexible material for the substrate 320 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used as the substrate 320.

[0295] The substrate 320 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. The substrate 320 can also be made of glass having a thickness sufficient to provide flexibility.

[0296] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0297] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0298] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0299] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display panel. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0300] The resin layer 322 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Adhesive sheets or the like may also be used.

[0301] Materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0302] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These materials can also be used for conductive layers such as various wirings and electrodes constituting display devices, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in light-emitting devices.

[0303] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0304] Next, materials that can be used in light-emitting devices will be described.

[0305] A conductive film that transmits visible light and infrared light is used for the electrode from which light is extracted, and a conductive film that reflects visible light and infrared light is preferably used for the electrode from which light is not extracted.

[0306] The light-emitting device preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes of the light-emitting device preferably has a transmissive and reflective electrode for visible light, and the other preferably has a reflective electrode for visible light. By having the light-emitting device have a microcavity structure, light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting device.

[0307] The semi-transmitting / semi-reflective electrode can have a laminated structure of an electrode that is reflective to visible light and an electrode that is transparent to visible light (also referred to as a transparent electrode).

[0308] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for a light-emitting device. The visible light reflectance of the semi-transparent / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 −２ The transmittance or reflectance of these electrodes for near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less) preferably satisfies the above-mentioned range, similar to the transmittance or reflectance for visible light.

[0309] The first layer 313 a, the second layer 313 b, and the third layer 313 c each have a light-emitting layer. It is preferable that the first layer 313 a, the second layer 313 b, and the third layer 313 c each have a light-emitting layer that emits light of a different color.

[0310] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0311] The first layer 313 a, the second layer 313 b, and the third layer 313 c may further include a layer containing a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, a substance with high electron-injection properties, an electron-blocking material, or a bipolar substance (a substance with high electron-transport properties and high hole-transport properties), as a layer other than the light-emitting layer.

[0312] The light-emitting device can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting device can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0313] For example, the first layer 313 a, the second layer 313 b, and the third layer 313 c may each include one or more of a hole-injection layer, a hole-transport layer, a hole-blocking layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer. The first layer 313 a, the second layer 313 b, and the third layer 313 c may each include a charge-generation layer (also referred to as an intermediate layer).

[0314] The fourth layer 314 may include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer. For example, when the conductive layers 311 a to 311 c function as anodes and the common electrode 315 functions as a cathode, the fourth layer 314 preferably includes an electron injection layer.

[0315] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0316] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting display devices can be formed using a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0317] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the display device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0318] In particular, vacuum processes such as vapor deposition and solution processes such as spin coating and inkjet printing can be used to fabricate light-emitting devices. Vapor deposition methods include physical vapor deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical vapor deposition (CVD). In particular, functional layers included in the EL layer (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer, etc.) can be formed by vapor deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet printing, screen (stencil printing), offset (lithographic printing), flexography (relief printing), gravure, microcontact printing, etc.), etc.

[0319] When processing the thin film that constitutes the display device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0320] As described above, in the display device of this embodiment, the island-shaped EL layer is not formed by a metal mask pattern but is formed by forming the EL layer on the entire surface and then processing it, so that the island-shaped EL layer can be formed with a uniform thickness. Furthermore, a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now, can be realized. Furthermore, since the EL layer can be made separately for each color, a display device with extremely vivid, high contrast, and high display quality can be realized. Furthermore, by providing a sacrificial layer on the EL layer, damage to the EL layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting device can be improved.

[0321] A display device according to one embodiment of the present invention includes an OS transistor and a light-emitting device with an MML (metal maskless) structure. This structure can significantly reduce leakage current that may flow through the transistor and leakage current that may flow between adjacent light-emitting elements (also referred to as lateral leakage current or side leakage current). Furthermore, when an image is displayed on the display device, the viewer can observe one or more of image clarity, image sharpness, high saturation, and a high contrast ratio. The extremely low leakage current that may flow through the transistor and lateral leakage current between light-emitting elements can minimize light leakage (so-called white floating) that may occur during black display (also referred to as true black display).

[0322] Furthermore, the display device of one embodiment of the present invention can have a structure in which an insulator covering an edge of a pixel electrode is not provided. In other words, the display device of one embodiment of the present invention has a structure in which an insulator is not provided between the pixel electrode and the EL layer. With this structure, light emitted from the EL layer can be efficiently extracted, thereby significantly reducing viewing angle dependency. For example, in the display device of one embodiment of the present invention, the viewing angle (the maximum angle at which a certain contrast ratio is maintained when the screen is viewed from an oblique direction) can be set to a range of 100° to less than 180°, preferably 150° to 170°. Note that the above viewing angle can be applied to both the vertical and horizontal directions. The display device of one embodiment of the present invention can improve viewing angle dependency and image visibility.

[0323] When a display device is formed using a fine metal mask (FMM) structure, there are cases where restrictions are imposed on the pixel arrangement configuration, etc. Here, the FMM structure will be described below.

[0324] In the FMM structure, a metal mask (also referred to as FMM) with openings is set opposite the substrate so that EL is deposited in the desired area during EL deposition. EL deposition is then performed through the FMM, resulting in EL deposition in the desired area. As the substrate size increases during EL deposition, the FMM also increases in size and weight. Furthermore, heat and other factors are applied to the FMM during EL deposition, which can cause deformation of the FMM. Alternatively, a method of applying a certain tension to the FMM during EL deposition is also available, so the weight and strength of the FMM are important parameters.

[0325] Therefore, when designing a pixel arrangement configuration using FMM, the above parameters and the like must be taken into consideration, and consideration must be given under certain limitations. On the other hand, in a display device according to one embodiment of the present invention, since it is manufactured using an MML structure, it has an excellent effect of providing a higher degree of freedom in the pixel arrangement configuration and the like compared to an FMM structure. Note that this configuration is highly compatible with, for example, flexible devices, and various circuit configurations can be used for either or both of the pixels and the driving circuits.

[0326] The first, second, and third layers constituting the light-emitting device of each color are formed in separate processes. Therefore, each EL layer can be fabricated with a configuration (material, film thickness, etc.) suitable for the light-emitting device of each color. This allows the fabrication of light-emitting devices with excellent characteristics.

[0327] This embodiment mode can be combined with other embodiment modes as appropriate.

[0328] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 14, 15A, and 15B.

[0329] The display device of the present embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of the present embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0330] [Display Device] FIG. 14 shows a perspective view of the display device 300A, and FIG. 15A shows a cross-sectional view of the display device 300A.

[0331] The display device 300A has a configuration in which a substrate 352 and a substrate 351 are bonded together. In Fig. 14, the substrate 352 is clearly indicated by a dashed line.

[0332] The display device 300A includes a display portion 362, a connection portion 340, a circuit 364, wiring 365, and the like. Fig. 14 shows an example in which an IC 373 and an FPC 372 are mounted on the display device 300A. Therefore, the configuration shown in Fig. 14 can also be said to be a display module including the display device 300A, an IC (integrated circuit), and an FPC.

[0333] The connection portion 340 is provided on the outside of the display portion 362. The connection portion 340 can be provided along one side or multiple sides of the display portion 362. The connection portion 340 may be single or multiple. Fig. 14 shows an example in which the connection portion 340 is provided so as to surround the four sides of the display portion. The connection portion 340 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode.

[0334] The circuit 364 can be, for example, a scanning line driver circuit.

[0335] The wiring 365 has a function of supplying signals and power to the display portion 362 and the circuit 364. The signals and power are input to the wiring 365 from the outside via the FPC 372 or from the IC 373.

[0336] 14 shows an example in which an IC 373 is provided on a substrate 351 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 373 may be, for example, an IC having a scanning line driver circuit or a signal line driver circuit. The display device 300A and the display module may not necessarily include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0337] Figure 15A shows an example of a cross section of the display device 300A, where a portion of the area including the FPC 372, a portion of the circuit 364, a portion of the display unit 362, a portion of the connection portion 340, and a portion of the area including the end portion are cut away.

[0338] The display device 300A shown in Figure 15A has, between a substrate 351 and a substrate 352, a transistor 201, a transistor 205, a light-emitting device 330a that emits red light, a light-emitting device 330b that emits green light, and a light-emitting device 330c that emits blue light.

[0339] The light-emitting device 330a includes a conductive layer 311a, a conductive layer 312a on the conductive layer 311a, and a conductive layer 326a on the conductive layer 312a. All or some of the conductive layers 311a, 312a, and 326a may be called pixel electrodes.

[0340] The conductive layer 311a is connected to the conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 324. The end of the conductive layer 312a is located outside the end of the conductive layer 311a. The end of the conductive layer 312a and the end of the conductive layer 326a are aligned or approximately aligned. For example, a conductive layer functioning as a reflective electrode can be used for the conductive layer 311a and the conductive layer 312a, and a conductive layer functioning as a transparent electrode can be used for the conductive layer 326a.

[0341] The light-emitting device 330b includes a conductive layer 311b, a conductive layer 312b on the conductive layer 311b, and a conductive layer 326b on the conductive layer 312b.

[0342] The light-emitting device 330c includes a conductive layer 311c, a conductive layer 312c on the conductive layer 311c, and a conductive layer 326c on the conductive layer 312c.

[0343] The conductive layer 311b, the conductive layer 312b, and the conductive layer 326b in the light-emitting device 330b, and the conductive layer 311c, the conductive layer 312c, and the conductive layer 326c in the light-emitting device 330c are similar to the conductive layer 311a, the conductive layer 312a, and the conductive layer 326a in the light-emitting device 330a, and therefore detailed description thereof will be omitted.

[0344] The conductive layers 311a, 311b, and 311c have recesses formed therein so as to cover openings formed in the insulating layer 324. A layer 328 is buried in the recesses.

[0345] The layer 328 has a function of planarizing recesses of the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c. The conductive layers 312a, 312b, and 312c, which are electrically connected to the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c, are provided over the conductive layers 311a, 311b, 311c, and the layer 328. Therefore, regions overlapping with the recesses of the conductive layers 311a, 311b, and 311c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0346] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 328. In particular, the layer 328 is preferably formed using an insulating material.

[0347] An insulating layer containing an organic material can be suitably used for the layer 328. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, or the like can be used for the layer 328. Alternatively, a photosensitive resin can be used for the layer 328. The photosensitive resin can be a positive material or a negative material.

[0348] By using a photosensitive resin, the layer 328 can be formed only through exposure and development steps, and the influence of dry etching, wet etching, etc. on the surfaces of the conductive layers 311 a, 311 b, and 311 c can be reduced. Furthermore, by forming the layer 328 using a negative photosensitive resin, the layer 328 can be formed using the same photomask (exposure mask) as that used to form the openings in the insulating layer 324 in some cases.

[0349] The top and side surfaces of the conductive layer 312a and the conductive layer 326a are covered with the first layer 313a. The top and side surfaces of the conductive layer 312b and the conductive layer 326b are covered with the second layer 313b. The top and side surfaces of the conductive layer 312c and the conductive layer 326c are covered with the third layer 313c. Therefore, the entire region where the conductive layer 312a, the conductive layer 312b, or the conductive layer 312c is provided can be used as the light-emitting region of the light-emitting device 330a, the light-emitting device 330b, or the light-emitting device 330c, thereby increasing the aperture ratio of the pixel.

[0350] The side surfaces of the first layer 313a, the second layer 313b, and the third layer 313c are covered with an insulating layer 325 and an insulating layer 327, respectively. A sacrificial layer 318a is located between the first layer 313a and the insulating layer 325, a sacrificial layer 318b is located between the second layer 313b and the insulating layer 325, and a sacrificial layer 318c is located between the third layer 313c and the insulating layer 325. A fourth layer 314 is provided on the first layer 313a, the second layer 313b, the third layer 313c, the insulating layer 325, and the insulating layer 327, and a common electrode 315 is provided on the fourth layer 314. The fourth layer 314 and the common electrode 315 are continuous films provided in common to the light-receiving device and the light-emitting device, respectively. In addition, a protective layer 331 is provided on the light emitting device 330a, the light emitting device 330b, and the light emitting device 330c.

[0351] The protective layer 331 and the substrate 352 are bonded via an adhesive layer 342. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device. In FIG. 15A , the space between the substrates 352 and 351 is filled with the adhesive layer 342, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 342 may be provided so as not to overlap with the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 342.

[0352] In the connection portion 340, a conductive layer 323 is provided over the insulating layer 324. The conductive layer 323 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive film as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive film as the conductive layers 326a, 326b, and 326c. Ends of the conductive layer 323 are covered with a sacrificial layer, an insulating layer 325, and an insulating layer 327. A fourth layer 314 is provided over the conductive layer 323, and a common electrode 315 is provided over the fourth layer 314. The conductive layer 323 and the common electrode 315 are electrically connected via the fourth layer 314. The fourth layer 314 does not necessarily have to be formed in the connection portion 340. In this case, the conductive layer 323 and the common electrode 315 are in direct contact with each other and electrically connected.

[0353] The display device 300A is a top-emission type. Light emitted by the light-emitting device is emitted toward the substrate 352. The substrate 352 is preferably made of a material that is highly transparent to visible light. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 315) contains a material that transmits visible light.

[0354] The insulating layer 215 is provided to cover the transistor. The insulating layer 324 is provided to cover the transistor and functions as a planarization layer. Note that the number of insulating layers covering the transistor is not limited, and each insulating layer may be a single layer or two or more layers.

[0355] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0356] The insulating layer 215 is preferably an inorganic insulating film. Examples of inorganic insulating films that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may be used. Two or more of the above insulating films may be stacked.

[0357] The insulating layer 324, which functions as a planarization layer, can be preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 324 may also have a stacked structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 324 preferably functions as an etching protection film. This can prevent recesses from being formed in the insulating layer 324 during processing of the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like. Alternatively, recesses may be formed in the insulating layer 324 during processing of the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like.

[0358] A connection portion 204 is provided in a region of the substrate 351 where the substrate 352 does not overlap. In the connection portion 204, a wiring 365 is electrically connected to the FPC 372 via a conductive layer 366 and a connection layer 203. The conductive layer 366 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive film as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive film as the conductive layers 326a, 326b, and 326c. The conductive layer 366 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 372 to be electrically connected via the connection layer 203.

[0359] A light-shielding layer 317 is preferably provided on the surface of the substrate 352 facing the substrate 351. The light-shielding layer 317 can be provided between adjacent light-emitting devices, on the connecting portion 340, on the circuit 364, and so on. Various optical members can be disposed on the outside of the substrate 352. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. The outside of the substrate 352 may also be provided with an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, and so on.

[0360] By providing the protective layer 331 that covers the light emitting device and the light receiving device, it is possible to prevent impurities such as water from entering the light emitting device and the light receiving device, thereby improving the reliability of the light emitting device and the light receiving device.

[0361] The substrate 351 and the substrate 352 can each be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. Using a flexible material for the substrate 351 and the substrate 352 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used for the substrate 351 or the substrate 352.

[0362] Substrate 351 and substrate 352 can each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 351 and 352 may be made of glass having a thickness sufficient to provide flexibility.

[0363] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0364] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0365] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0366] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display panel. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0367] The adhesive layer 342 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0368] The connection layer 203 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0369] Materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0370] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These materials can also be used for conductive layers such as various wirings and electrodes constituting display devices, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in light-emitting devices.

[0371] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0372] <Transistor> FIG. 15B is an enlarged view of a cross section including the transistor 201 and the transistor 205. As shown in FIG.

[0373] The transistor 205 includes a semiconductor layer 108, an insulating layer 117, an insulating layer 110, and a conductive layer 112 stacked in this order. Parts of the insulating layer 117 and the insulating layer 110 function as gate insulating layers of the transistor 201. The conductive layer 112 functions as a gate electrode of the transistor 201. The transistor 201 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108.

[0374] The transistor 201 includes a semiconductor layer 208, an insulating layer 110, and a conductive layer 212 stacked in this order. Part of the insulating layer 110 functions as a gate insulating layer of the transistor 205. The conductive layer 212 functions as a gate electrode of the transistor 205. The transistor 205 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 208. The transistor 205 differs from the transistor 201 in the surface where the semiconductor layer is formed. Furthermore, the transistor 205 differs from the transistor 201 in the configuration of the gate insulating layer.

[0375] The components of the transistor 201 and the transistor 205 other than the semiconductor layers can be formed in the same process, which can prevent an increase in the number of processes even when two types of transistors are mixed.

[0376] 15B includes a conductive layer 106 that functions as a back gate. The transistor 201 in FIG. 15B includes a conductive layer 206 that functions as a back gate.

[0377] 15B , a conductive layer 106 is provided on and in contact with a substrate 351. An insulating layer 103 is provided on and in contact with the conductive layer 106 and the substrate 351. A semiconductor layer 108 is provided on and in contact with the insulating layer 103. An insulating layer 117 is provided on and in contact with the top surface of the insulating layer 103, the top surface of the substrate 351, and the top surface and side surfaces of the semiconductor layer 108. A semiconductor layer 208 is provided on and in contact with the insulating layer 117. That is, the semiconductor layer 208 is provided on a surface different from that of the semiconductor layer 108. The insulating layer 117 functions as a base film in the transistor 201. An insulating layer 110 is provided on and in contact with the top surface of the insulating layer 117 and the top surface and side surfaces of the semiconductor layer 208. A conductive layer 112 and a conductive layer 212 are provided on and in contact with the insulating layer 110. The conductive layer 112 has a region overlapping with the semiconductor layer 108 with the insulating layer 117 and the insulating layer 110 interposed therebetween. The conductive layer 212 has a region overlapping with the semiconductor layer 208 with the insulating layer 110 interposed therebetween.

[0378] 15B , the transistor 201 and the transistor 205 preferably further include an insulating layer 118. The insulating layer 118 is provided to cover the insulating layer 110, the conductive layer 112, and the conductive layer 212 and functions as a protective layer to protect the transistor 201 and the transistor 205.

[0379] The transistor 205 may include a conductive layer 222a and a conductive layer 222b over the insulating layer 118. The conductive layer 222a functions as one of a source electrode and a drain electrode of the transistor 205, and the conductive layer 222b functions as the other of the source electrode and the drain electrode of the transistor 205. The conductive layer 222a and the conductive layer 222b are electrically connected to the low-resistance region 108N of the semiconductor layer 108 through openings provided in the insulating layer 118, the insulating layer 110, and the insulating layer 117, respectively.

[0380] The transistor 201 may include a conductive layer 365a and a conductive layer 365b over the insulating layer 118. The conductive layer 365a functions as one of a source electrode and a drain electrode of the transistor 201, and the conductive layer 365b functions as the other of the source electrode and the drain electrode of the transistor 201. The conductive layer 365a and the conductive layer 365b are electrically connected to the low-resistance region 208N of the semiconductor layer 208 through openings provided in the insulating layer 118 and the insulating layer 110, respectively.

[0381] Here, the semiconductor layer 108 and the semiconductor layer 208 preferably contain metal oxides having different compositions. The semiconductor layer 108 and the semiconductor layer 208 can be formed by processing metal oxide films having different compositions. A display device which is one embodiment of the present invention includes a plurality of transistors having semiconductor layers with different compositions over the same substrate, and components other than the semiconductor layers can be formed in the same process.

[0382] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be obtained.

[0383] The following describes an example in which the transistor 201 is used as a transistor that requires a large on-state current. For example, when In—Ga—Zn oxide is used for both the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the metal elements contained therein is higher than that of the semiconductor layer 108. Alternatively, the semiconductor layer 108 can be made of a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the metal elements contained therein is higher than that of the semiconductor layer 208.

[0384] Similarly, when an In—Ga—Zn oxide is used for the semiconductor layer 108 and a metal oxide containing indium other than an In—Ga—Zn oxide is used for the semiconductor layer 208, a metal oxide having a higher ratio of the number of indium atoms to the number of atoms of the metal element compared to the semiconductor layer 108 can be used for the semiconductor layer 208.

[0385] A metal oxide containing indium other than In—Ga—Zn oxide can also be used for the semiconductor layer 108. In this case, similarly, the semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of indium atoms to the number of metal element atoms is higher than that of the semiconductor layer 108.

[0386] Alternatively, the semiconductor layer 108 may be formed using a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the metal element contained therein is higher than that of the semiconductor layer 208 .

[0387] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108N sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 205. The pair of low-resistance regions 108N function as a source region and a drain region of the transistor 205. Similarly, the semiconductor layer 208 has a channel formation region overlapping with the conductive layer 212 and a pair of low-resistance regions 208N sandwiching the channel formation region.

[0388] In the transistor 205, the low-resistance region 108N can also be referred to as a region having lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region than the channel formation region of the transistor 205. Similarly, in the transistor 201, the low-resistance region 208N can also be referred to as a region having lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region than the channel formation region of the transistor 201.

[0389] The low-resistance region 108N and the low-resistance region 208N are regions containing impurity elements. Examples of such impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. The low-resistance region 108N and the low-resistance region 208N preferably contain boron or phosphorus. The low-resistance region 108N and the low-resistance region 208N may contain two or more of the above elements. The low-resistance region 108N and the low-resistance region 208N may contain different impurity elements.

[0390] The low resistance region 108N and the low resistance region 208N can be formed by adding impurities through the insulating layer 110 using the conductive layer 112 or the conductive layer 212 as a mask, for example.

[0391] Note that the plurality of transistors included in the circuit 364 may all have the same structure or may have two or more types. Similarly, the plurality of transistors included in the display portion 362 may all have the same structure or may have two or more types.

[0392] Further, the circuit 364 and the display portion 362 may include transistors having the same structure.

[0393] For example, the transistor 205 may be used in the circuit 364 .

[0394] 16 illustrates an example in which the transistor 201 and the transistor 205 are used as transistors included in the display portion 362. The pixel circuit of the display portion 362 includes the transistor 201 and the transistor 205, so that a display device with high display quality and excellent reliability can be realized. Furthermore, the manufacturing process of the display device can be simplified compared to that of FIG. 17 described later.

[0395] Note that although the display device 300B illustrated in FIG. 16 uses the transistor 201 as a transistor included in the circuit 364, the transistor 205 may also be used.

[0396] 17 illustrates an example in which the transistors 201, 205, and 202 are used as transistors constituting the display portion 362, and the transistor 202 is used as a transistor constituting the circuit 364. When the pixel circuit included in the display portion 362 includes the transistors 201, 202, and 205, a display device with high display quality and excellent reliability can be realized.

[0397] The transistor 202 includes a semiconductor layer 411, an insulating layer 412, a conductive layer 413, and the like. The semiconductor layer 411 includes a channel formation region 411i and a low-resistance region 411n. The semiconductor layer 411 includes silicon. The semiconductor layer 411 preferably includes polycrystalline silicon. For example, LTPS can be used as the polycrystalline silicon. A part of the insulating layer 412 functions as a gate insulating layer. A part of the conductive layer 413 functions as a gate electrode.

[0398] The low-resistance region 411n is a region containing an impurity element. For example, when the transistor 202 is an n-channel transistor, phosphorus, arsenic, or the like may be added to the low-resistance region 411n. On the other hand, when the transistor 202 is a p-channel transistor, boron, aluminum, or the like may be added to the low-resistance region 411n. Furthermore, in order to control the threshold voltage of the transistor 202, the above-mentioned impurities may be added to the channel formation region 411i.

[0399] The circuit 364 may be configured using both n-channel transistors and p-channel transistors, or may be configured using only n-channel transistors or only p-channel transistors.

[0400] The transistor 202 may include a conductive layer 421a and a conductive layer 421b over the insulating layer 118. The conductive layer 421a functions as one of a source electrode and a drain electrode of the transistor 202, and the conductive layer 421b functions as the other of the source electrode and the drain electrode of the transistor 202. The conductive layer 421a and the conductive layer 421b are electrically connected to the low-resistance region 411n through openings provided in the insulating layer 118, the insulating layer 110, the insulating layer 117, and the insulating layer 412, respectively.

[0401] Here, the conductive layers 421a and 421b electrically connected to the transistor 202 are preferably formed by processing the same conductive film as the conductive layers 222a, 222b, 365a, and 365b, which can simplify the manufacturing process.

[0402] The conductive layer 413 functioning as the gate electrode of the transistor 202, the conductive layer 206 functioning as the second gate electrode of the transistor 201, and the conductive layer 106 functioning as the second gate of the transistor 205 are preferably formed by processing the same conductive film, which is preferable because the manufacturing process can be simplified.

[0403] Note that the transistor 202 may have a second gate electrode. In the case where the transistor 202 has the second gate electrode, for example, a conductive layer functioning as the second gate electrode may be provided over the substrate 351, an insulating layer may be provided so as to be in contact with the conductive layer and top surfaces of the substrate 351, and the semiconductor layer 411 may be provided over the insulating layer. Furthermore, the conductive layer 413 and the conductive layer functioning as the second gate electrode preferably have regions overlapping each other.

[0404] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0405] Embodiment 4 In this embodiment, a light-emitting device that can be used for a display device according to one embodiment of the present invention will be described.

[0406] 18A , the light-emitting device has an EL layer 786 between a pair of electrodes (a lower electrode 772 and an upper electrode 788). The EL layer 786 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron-injection properties (electron-injection layer) and a layer containing a substance with high electron-transport properties (electron-transport layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole-injection properties (hole-injection layer) and a layer containing a substance with high hole-transport properties (hole-transport layer).

[0407] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 18A is referred to as a single structure in this specification.

[0408] Fig. 18B shows a modified example of the EL layer 786 included in the light-emitting device shown in Fig. 18A. Specifically, the light-emitting device shown in Fig. 18B includes a layer 4431 on a lower electrode 772, a layer 4432 on the layer 4431, a light-emitting layer 4411 on the layer 4432, a layer 4421 on the light-emitting layer 4411, a layer 4422 on the layer 4421, and an upper electrode 788 on the layer 4422. For example, when the lower electrode 772 is an anode and the upper electrode 788 is a cathode, the layer 4431 functions as a hole injection layer, the layer 4432 functions as a hole transport layer, the layer 4421 functions as an electron transport layer, and the layer 4422 functions as an electron injection layer. Alternatively, when the lower electrode 772 is a cathode and the upper electrode 788 is an anode, the layer 4431 functions as an electron injection layer, the layer 4432 functions as an electron transport layer, the layer 4421 functions as a hole transport layer, and the layer 4422 functions as a hole injection layer. With such a layer structure, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0409] As shown in FIGS. 18C and 18D, a configuration in which a plurality of light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between the layer 4420 and the layer 4430 is also a variation of the single structure.

[0410] 18E and 18F , a configuration in which a plurality of light-emitting units (EL layer 786 a, EL layer 786 b) are connected in series via charge generation layer 4440 is referred to as a tandem structure in this specification. The tandem structure may also be referred to as a stack structure. The tandem structure makes it possible to obtain a light-emitting device capable of emitting light with high brightness.

[0411] 18C and 18D , light-emitting materials that emit light of the same color, or even the same light-emitting material, may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413. For example, a light-emitting material that emits blue light may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413. A color conversion layer may be provided as the layer 785 shown in FIG.

[0412] The light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413 may each be made of a light-emitting material that emits light of a different color. When the light emitted from the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413 has a complementary color relationship, white light can be obtained. A color filter (also referred to as a coloring layer) may be provided as the layer 785 shown in FIG. 18D. When white light passes through the color filter, light of a desired color can be obtained.

[0413] 18E and 18F , the light-emitting layer 4411 and the light-emitting layer 4412 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. Alternatively, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of light-emitting materials that emit light of different colors. When the light emitted by the light-emitting layer 4411 and the light emitted by the light-emitting layer 4412 are complementary colors, white light emission is obtained. FIG. 18F shows an example in which a layer 785 is further provided. The layer 785 can be one or both of a color conversion layer and a color filter (coloring layer).

[0414] 18C, 18D, 18E, and 18F, the layer 4420 and the layer 4430 may have a laminated structure consisting of two or more layers, as shown in FIG. 18B.

[0415] A structure that produces different luminescent colors (for example, blue (B), green (G), and red (R)) for each light-emitting device is sometimes called an SBS (Side By Side) structure.

[0416] The light-emitting device can emit light of red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 786. Furthermore, the color purity can be further improved by providing the light-emitting device with a microcavity structure.

[0417] A light-emitting device that emits white light preferably has a configuration in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, light-emitting materials can be selected so that the light emitted from each of the two or more light-emitting materials has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a light-emitting device that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0418] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0419] This embodiment mode can be combined with other embodiment modes as appropriate.

[0420] Embodiment 5 In this embodiment, a metal oxide (also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0421] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0422] The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, or an atomic layer deposition (ALD) method.

[0423] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0424] The crystalline structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by a GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method.

[0425] For example, in the case of a quartz glass substrate, the shape of the peak in the XRD spectrum is almost symmetrical. On the other hand, in the case of an IGZO film having a crystalline structure, the shape of the peak in the XRD spectrum is asymmetrical. The asymmetrical shape of the peak in the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the shape of the peak in the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0426] The crystalline structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an IGZO film formed at room temperature, rather than a halo. For this reason, it is estimated that the IGZO film formed at room temperature is neither crystalline nor amorphous, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0427] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0428] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0429] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0430] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nanometers.

[0431] In an In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, silicon, boron, copper, vanadium, beryllium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in, for example, a high-resolution TEM (Transmission Electron Microscope) image.

[0432] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0433] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0434] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0435] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0436] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of a CAAC-OS in an OS transistor can increase the flexibility of the manufacturing process.

[0437] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0438] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.

[0439] <<Structure of Oxide Semiconductor>> Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0440] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0441] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0442] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0443] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0444] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0445] CAC-OS in In—Ga—Zn oxide refers to a mosaic structure in which some regions mainly composed of Ga and other regions mainly composed of In are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0446] The CAC-OS can be formed by sputtering without heating the substrate. When the CAC-OS is formed by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0447] For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as the main component (first region) and a region containing Ga as the main component (second region) are unevenly distributed and mixed.

[0448] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0449] On the other hand, the second region has higher insulating properties than the first region, that is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0450] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby imparting a switching function (on / off function) to the CAC-OS. In other words, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the entire material functions as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a large on-state current, high field-effect mobility, and favorable switching operation can be achieved.

[0451] A transistor using the CAC-OS has high reliability and is therefore ideal for a variety of display devices including display devices.

[0452] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0453] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0454] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0455] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10 １０ cm−３ is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0456] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0457] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0458] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0459] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0460] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0461] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0462] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0463] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0464] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0465] This embodiment mode can be combined with other embodiment modes as appropriate.

[0466] Embodiment 6 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0467] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0468] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0469] The display device of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices (e.g., head-mounted displays), AR glasses-type devices, and MR devices.

[0470] The display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth in electronic devices for personal use, such as portable or home use. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0471] The electronic device of this embodiment may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0472] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0473] The electronic device 6500 shown in FIG. 19A is a portable information terminal that can be used as a smartphone.

[0474] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0475] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0476] FIG. 19B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0477] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0478] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0479] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0480] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion, an electronic device with a narrow frame can be realized.

[0481] 20A shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0482] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0483] 20A can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0484] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0485] 20B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The housing 7211 includes a display portion 7000.

[0486] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0487] 20C and 20D show an example of digital signage.

[0488] 20C includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0489] 20D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0490] 20C and 20D, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0491] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0492] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0493] 20C and 20D , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411, such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0494] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0495] Note that the display portion of the electronic device of one embodiment of the present invention preferably includes a light-receiving device as a sensor device. The display portion includes both a light-emitting device and a light-receiving device, which enables the number of components to be reduced. In other words, since the electronic device of one embodiment of the present invention includes both a light-emitting device and a sensor device, it is not necessary to separately provide a fingerprint authentication device or a capacitive touch panel device for scrolling or the like. Therefore, one embodiment of the present invention can provide an electronic device with reduced manufacturing costs.

[0496] The electronic device shown in Figures 21A to 21F has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0497] The electronic devices shown in Figures 21A to 21F have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0498] The electronic device shown in FIGS. 21A to 21F will be described in detail below.

[0499] FIG. 21A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 21A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0500] 21B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0501] FIG. 21C is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0502] 21D to 21F are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 21D is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 21F is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 21E is a perspective view of a state in the process of changing from one of FIG. 21D and FIG. 21F to the other. The mobile information terminal 9201 has excellent portability in a folded state, and excellent display visibility due to a seamless, wide display area in an unfolded state. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0503] This embodiment mode can be combined with other embodiment modes as appropriate.

[0504] In this example, characteristics of an OS transistor of one embodiment of the present invention and a transistor using LTPS will be described.

[0505] <Fabrication of Transistor 1> As Transistor 1, an OS transistor was fabricated.

[0506] First, a 100-nm-thick tungsten film was formed on a substrate by sputtering, and then processed to form a first conductive layer. Next, a first insulating layer was formed on the substrate and the first conductive layer by plasma CVD. The first insulating layer had a stacked structure of a 120-nm-thick silicon nitride film and a 150-nm-thick silicon oxynitride film.

[0507] Next, a heat treatment was carried out at 350° C. for 10 minutes.

[0508] Next, a 25 nm thick metal oxide film was formed on the first insulating layer and processed to obtain a semiconductor layer. The metal oxide film was formed by sputtering, and a metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 was used.

[0509] Next, a heat treatment was carried out at 340° C. for 2 hours.

[0510] Next, a silicon oxynitride film was formed to a thickness of 140 nm as a second insulating layer over the semiconductor layer by a plasma CVD method.

[0511] Next, a heat treatment was carried out at 340° C. for 1 hour.

[0512] Next, a second conductive layer was formed over the second insulating layer, having a stacked structure of a 50-nm-thick titanium layer, a 200-nm-thick aluminum layer, and a 50-nm-thick titanium layer.

[0513] Next, a third insulating layer was formed on the second conductive layer, openings were formed in the third insulating layer that reached the semiconductor layer, and conductive layers that functioned as source and drain electrodes were formed so as to fill the openings.

[0514] Through the above steps, an OS transistor formed over a glass substrate was obtained.

[0515] <Fabrication of Transistor 2 and Transistor 3> Transistors 2 and 3 were fabricated using LTPS. The thickness of the LTPS was 50 nm. Silicon oxynitride was used as a gate insulating layer with a thickness of 110 nm. The transistors had a top-gate structure and a back gate. Silicon nitride oxide with a thickness of 140 nm was provided on the back gate, silicon oxynitride with a thickness of 100 nm was provided on the silicon nitride oxide, and LTPS was provided on the silicon oxynitride. Transistor 2 was an n-channel transistor, and transistor 3 was a p-channel transistor.

[0516] <Id-Vg Characteristics> Next, the Id-Vg characteristics of the transistors of the samples fabricated above were measured.

[0517] The Id-Vg characteristics of the transistor were measured by applying a voltage to the gate electrode (hereinafter also referred to as gate voltage (Vg)) from −15 V to +20 V in 0.1 V increments (denoted as Pscan in the figure), and then measuring the voltage from +20 V to −15 V in 0.1 V increments (denoted as Mscan in the figure). The voltage applied to the source electrode (hereinafter also referred to as source voltage (Vs)) was set to 0 V (comm), and the voltage applied to the drain electrode (hereinafter also referred to as drain voltage (Vd)) was set to 0.1 V and 10 V. The drain current (Id) was measured at 1×10 −３A was set as the upper limit.

[0518] Here, the Id-Vg characteristics were measured when the same gate voltage was applied to the second gate electrode and the first gate electrode.

[0519] The measurement was performed using a transistor with a designed channel length of 10 μm and a designed channel width of 6 μm. An OS transistor with a designed channel length of 6 μm and a designed channel width of 6 μm was also used.

[0520] The Id-Vg characteristics of each transistor are shown in Figures 22A, 22B, 23A, and 23B. Each graph shows gate voltage (Vg) on ​​the horizontal axis and drain current (Id) on the vertical axis. The graphs also show two Id-Vg characteristics when the drain voltage is 0.1 V and 10 V.

[0521] 22A shows the Id-Vg characteristics of an n-channel OS transistor with a channel length of 10 μm and a channel width of 6 μm, FIG. 22B shows the Id-Vg characteristics of an n-channel OS transistor with a channel length of 6 μm and a channel width of 6 μm, FIG. 23A shows the Id-Vg characteristics of an n-channel LTPS transistor with a channel length of 10 μm and a channel width of 6 μm, and FIG. 22B shows the Id-Vg characteristics of a p-channel LTPS transistor with a channel length of 10 μm and a channel width of 6 μm.

[0522] As shown in Figures 22A and 22B, when an OS transistor is used, the difference between the Id-Vg curve (Pscan) obtained by sweeping the gate voltage in the positive direction and the Id-Vg curve (Mscan) obtained by sweeping the gate voltage in the negative direction is extremely small, indicating that hysteresis can be kept small.

[0523] C1: capacitance, GL: wiring, EL1: light-emitting element, ND1: node, ND2: node, ND3: node, PS: pixel, Px: pixel, t1: time, t2: time, t3: time, Tr1: transistor, Tr2: transistor, Tr3: transistor, Tr4: transistor, Tr5: transistor, Tr6: transistor, Tr7: transistor, Va_1: potential, Vd_1: potential, Vdata: wiring, Vdata_1: signal, Vdd: wiring, Vem1: wiring, Vem2: wiring, Vi_1: potential, Vini: wiring, Vscan1: wiring, Vscan2: wiring, Vss: wiring, 10: display device, 11: display unit, 12: drive circuit, 12a: drive circuit, 12b: drive circuit, 13: drive circuit, 31: shift register circuit, 32: latch circuit, 33: latch circuit, 34: level shifter circuit, 35: DAC circuit, 36: analog buffer circuit, 37: source follower circuit, 38: sampling circuit, 41: latch circuit unit, 42: level shifter circuit unit, 43: D-A conversion unit, 44: analog buffer circuit unit, 45: source follower circuit unit, 46: demultiplexer circuit, 51: pixel circuit, 103: insulating layer, 106: conductive layer, 1 08: semiconductor layer, 108N: low resistance region, 110: insulating layer, 112: conductive layer, 117: insulating layer, 118: insulating layer, 139: region, 201: transistor, 202: transistor, 203: connection layer, 204: connection portion, 205: transistor, 206: conductive layer, 208: semiconductor layer, 208N: low resistance region, 212: conductive layer, 215: insulating layer, 222a: conductive layer, 222b: conductive layer, 300: display device, 300A: display device, 300B: display device, 300C: display device, 301: layer, 310: pixel, 310a: sub-pixel, 310A: pixel, 310b: sub-pixel, 310B: pixel, 310c: sub-pixel, 311a: conductive layer, 311b: conductive layer, 311c: conductive layer, 312a: conductive layer, 312b: conductive layer, 312c: conductive layer, 313a: layer, 313b: layer, 313c: layer, 314: layer, 315: common electrode, 317: light-shielding layer, 318a: sacrificial layer, 318b: sacrificial layer, 318c: sacrificial layer, 319a: sacrificial layer, 319b: sacrificial layer, 320: substrate, 321: insulating layer, 322: resin layer, 323: conductive layer, 324: insulating layer, 325: insulating layer, 326a: conductive layer, 326b: conductive layer, 326c: conductive layer, 327: insulating layer, 328: layer,330a: light-emitting device, 330b: light-emitting device, 330c: light-emitting device, 331: protective layer, 334: gap, 340: connection portion, 342: adhesive layer, 351: substrate, 352: substrate, 362: display portion, 364: circuit, 365: wiring, 365a: conductive layer, 365b: conductive layer, 366: conductive layer, 372: FPC, 373: IC, 411: semiconductor layer, 411i: channel formation region, 411n: low resistance region, 412: insulating layer, 413: conductive layer, 421a: conductive layer, 421b: conductive layer, 772: lower electrode Electrode, 785: layer, 786: EL layer, 786a: EL layer, 786b: EL layer, 788: upper electrode, 4411: light-emitting layer, 4412: light-emitting layer, 4413: light-emitting layer, 4420: layer, 4421: layer, 4422: layer, 4430: layer, 4431: layer, 4432: layer, 4440: charge generation layer, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511 : Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television device, 7101: Housing, 7103: Stand, 7111: Remote control device, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 73 03: speaker, 7311: information terminal, 7400: digital signage, 7401: pillar, 7411: information terminal, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: mobile information terminal, 9102: mobile information terminal, 9200: mobile information terminal, 9201: mobile information terminal,

Claims

1. A first transistor, a second transistor, a third transistor, and a light emitting element, the light-emitting element is electrically connected to one of the source and the drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; a gate electrode of the second transistor is electrically connected to one of a source and a drain of the third transistor; the semiconductor layer of the second transistor comprises indium, zinc and an element M; The element M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt; the semiconductor layer of the third transistor comprises indium, zinc and the element M; In the semiconductor layer of the second transistor, the ratio of the number of indium atoms to the total number of indium atoms, zinc atoms, and the element M is 30 atomic % or more and 100 atomic % or less; a ratio of the number of atoms of the element M to the total number of atoms of indium, zinc, and the element M in the semiconductor layer of the third transistor is higher than that in the semiconductor layer of the second transistor; The second transistor has a function of controlling an amount of light emitted by the light-emitting element.

2. In claim 1, the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor; A display device, wherein the semiconductor layer of the second transistor has a higher ratio of the number of indium atoms to the total number of indium, zinc and the element M atoms than the semiconductor layer of the third transistor.

3. In claim 1 or 2, The semiconductor layer of the third transistor has a ratio of the number of atoms of the element M to the number of atoms of the metal element contained therein of 20 atomic % or more and 60 atomic % or less.

4. In any one of claims 1 to 3, a fourth transistor, a fifth transistor, a first wiring, a capacitance, and a drive circuit; one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor; one of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor; the other of the source and the drain of the fourth transistor is electrically connected to the first wiring; a first electrode of the capacitor is electrically connected to one of the source and the drain of the first transistor; a second electrode of the capacitor electrically connected to a gate of the second transistor; The first wiring has a function of supplying a video signal output from the drive circuit to the other of the source and drain of the fourth transistor.

5. In claim 4, a function of writing a potential to a gate of the second transistor by turning on the second transistor, the third transistor, and the fourth transistor and turning off the first transistor and the fifth transistor; The display device has a function of holding the written potential by turning off the third transistor and the fourth transistor after the potential is written.

6. In claim 4, a function of writing a potential to a gate of the second transistor by turning on the second transistor, the third transistor, and the fourth transistor and turning off the first transistor and the fifth transistor; After the potential is written, the third transistor and the fourth transistor are turned off to hold the written potential; A display device having a function of controlling the amount of light emitted by the light-emitting element by turning on the first transistor, the second transistor, and the fifth transistor after the potential is maintained.