Display device

Abstract

Provided is a high-definition display device. Provided is a low-power-consumption display device. This display device comprises a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring stretches out in the first direction, and has a gate signal applied. The second wiring stretches out in the second direction intersecting with the first direction, and has a source signal applied. The first transistor has a gate electrically connected to the first wiring, either one of a source or drain electrically connected to the second wiring, and the other of the source or drain electrically connected to each of the plurality of second transistors. The plurality of second transistors are connected in series or in parallel. The first transistor has a first semiconductor layer where a current flows in the first direction or in the second direction. The plurality of second transistors each have a second semiconductor layer where a current flows in the first direction or in the second direction.

Description

display device

[0001] 1. Field of the Invention One aspect of the present invention relates to a display device. 2. Field of the Invention One aspect of the present invention relates to an electronic device including a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, display panels have become increasingly higher in definition. Devices requiring high-definition display panels, such as devices for virtual reality (VR) or augmented reality (AR), have been actively developed in recent years.

[0004] Representative examples of display devices applicable to the display panel include organic EL (Electro Luminescence) elements, light-emitting devices equipped with light-emitting elements such as light-emitting diodes (LEDs), liquid crystal display devices, and electronic paper that displays using an electrophoresis method or the like.

[0005] The basic structure of an organic EL element is a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be emitted from the light-emitting organic compound. A display device using such an organic EL element does not require a backlight, which is necessary in liquid crystal display devices and the like, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0006] JP 2002-324673 A

[0007] In the wearable devices for VR or AR described above, the distance between the eyes and the display panel is short, so a focus adjustment lens must be provided between them. Since the lens magnifies part of the screen, if the resolution of the display panel is low, the sense of realism and immersion may be diminished.

[0008] In addition, in the case of battery-powered devices, it is necessary to reduce the power consumption of the display panel in order to extend the time that it can be used continuously.In particular, in devices for AR, high brightness is required to display images superimposed on external light.

[0009] An object of one embodiment of the present invention is to provide a display device with high definition.An object of one embodiment of the present invention is to provide a display device with low power consumption.An object of one embodiment of the present invention is to provide a display device with high luminance.An object of one embodiment of the present invention is to provide a display device with a high aperture ratio.An object of one embodiment of the present invention is to provide a display device with high reliability.

[0010] An object of one embodiment of the present invention is to provide a novel display device, display module, or electronic device. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing the above-described display device with high yield. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a display device including a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. The first transistor has a gate electrically connected to the first wiring, one of a source and a drain electrically connected to a second wiring, and the other of the source and the drain electrically connected to gates of the plurality of second transistors. The plurality of second transistors are connected in series. The first transistor has a first semiconductor layer through which a current flows in a first direction or a second direction. The plurality of second transistors each have a second semiconductor layer through which a current flows in the first direction or a second direction.

[0013] Another embodiment of the present invention is a display device including a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. The first transistor has a gate electrically connected to the first wiring, one of a source and a drain electrically connected to a second wiring, and the other of the source and drain electrically connected to each gate of the plurality of second transistors. The plurality of second transistors each have one of a source and a drain electrically connected and the other of a source and a drain electrically connected. The first transistor has a first semiconductor layer through which a current flows in a first direction or a second direction. The plurality of second transistors each have a second semiconductor layer through which a current flows in the first direction or a second direction.

[0014] In any of the above, it is preferable that a light-emitting element having an anode and a cathode is provided, and one of the source and drain of one of the second transistors is preferably electrically connected to the anode or the cathode.

[0015] In any of the above, it is preferable that the plurality of second transistors have approximately the same channel length and approximately the same channel width.

[0016] In any of the above, it is preferable that the first transistor and the plurality of second transistors have approximately the same channel length and approximately the same channel width.

[0017] In any of the above, it is preferable that two adjacent second transistors among the plurality of second transistors each have a channel formation region in one island-shaped second semiconductor layer.

[0018] In any of the above, it is preferable that each of the second transistors has a second semiconductor layer, and the second semiconductor layers are arranged at equal intervals in the first direction or the second direction.

[0019] In any of the above, the second semiconductor layer preferably contains a metal oxide containing one or both of indium and zinc, and the first semiconductor layer preferably contains the same metal oxide as the second semiconductor layer.

[0020] In any of the above, it is preferable that the semiconductor device further includes a third transistor. The third transistor includes a third semiconductor layer. The third semiconductor layer preferably includes the same semiconductor material as the first semiconductor layer and has a portion having substantially the same top surface shape as the first semiconductor layer. In addition, it is preferable that at least one of the gate, source, and drain of the third transistor is electrically floating.

[0021] According to one embodiment of the present invention, a display device with high definition, low power consumption, high luminance, a high aperture ratio, or a high reliability can be provided.

[0022] According to one aspect of the present invention, a novel display device, a display module, or an electronic device can be provided. Alternatively, a method for manufacturing the above-described display device with high yield can be provided. Alternatively, at least one of the problems of the prior art can be alleviated.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0024] FIGS. 1A to 1C are diagrams showing an example of a configuration of a pixel circuit. FIGS. 2A to 2E are diagrams showing an example of a configuration of a pixel circuit. FIGS. 3A to 3D are diagrams showing an example of a configuration of a pixel circuit. FIG. 4 is a timing chart showing an example of a method for driving a display device. FIG. 5 is a diagram showing an example of a configuration of a transistor. FIGS. 6A to 6E are diagrams showing an example of a configuration of a transistor. FIGS. 7A to 7E are diagrams showing an example of a configuration of a transistor. FIGS. 8A and 8B are diagrams showing an example of a configuration of a transistor. FIG. 9 is a diagram showing an example of a configuration of a display device. FIGS. 10A to 10E are diagrams showing an example of a configuration of a display device. FIG. 11 is a diagram showing an example of a configuration of a display device. FIGS. 12A to 12E are diagrams showing an example of a configuration of a display device. FIG. 13 is a diagram showing an example of a configuration of a display device. FIG. 14 is a diagram showing an example of a configuration of a display device. FIG. 15 is a diagram showing an example of a configuration of a display device. FIG. 16 is a diagram showing an example of a configuration of a display device. FIGS. 17A to 17F are diagrams showing an example of a configuration of a light-emitting device. FIGS. 18A and 18B are diagrams showing examples of configurations of electronic devices. 19A and 19B are diagrams showing configuration examples of electronic devices. FIGS. 20A and 20B show electrical characteristics of a transistor according to an example. FIG. 21 is a photograph of the display state of a display panel according to an example. FIGS. 22A and 22B show measurement results of the viewing angle dependency of a display panel according to an example. FIG. 23 is a block diagram of a drive circuit for a display panel according to an example. FIG. 24 shows measurement results of the luminance during duty driving of a display panel according to an example.

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0027] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0029] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0030] In the following description, expressions indicating directions such as "up" and "down" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided in the drawing (such as the surface to be formed, the supporting surface, the adhesive surface, or the flat surface) is located above the laminate, the direction toward the surface may be expressed as "down" and the opposite direction as "up."

[0031] In this specification, the EL layer refers to a layer provided between a pair of electrodes of a light-emitting element and containing at least a light-emitting substance (also referred to as a light-emitting layer), or a stack including a light-emitting layer.

[0032] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface, and therefore the display panel is one aspect of an output device.

[0033] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) attached to the substrate, or a display panel having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, a display module, or simply a display panel.

[0034] Embodiment 1 In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0035] One embodiment of the present invention is a display device having a plurality of pixels arranged in a matrix. The display device includes a plurality of gate lines (first wirings) to which gate signals (also referred to as scan signals, scanning signals, or the like) are supplied and a plurality of source lines (second wirings) to which source signals (also referred to as video signals, data signals, or the like) are supplied. The gate lines are provided to extend in a first direction, and the source lines are provided to extend in a second direction intersecting the first direction.

[0036] A pixel is provided at an intersection of one source line and one gate line, and includes one or more display elements and two or more transistors. The pixel also includes a pixel electrode that functions as an electrode of the display element.

[0037] The pixel includes a first transistor and a second transistor. In this case, the second transistor is preferably composed of a plurality of transistors (also referred to as sub-transistors) sharing a gate. For example, the second transistor is composed of a plurality of sub-transistors connected in series. Alternatively, the second transistor is composed of a plurality of sub-transistors connected in parallel. Alternatively, the second transistor is composed of a group of a plurality of parallel-connected sub-transistors connected in series (hereinafter also referred to as series-parallel connection).

[0038] Here, a sub-transistor refers to one of a group of multiple transistors that share a gate and are connected in series or parallel. When multiple sub-transistors are connected in parallel, the gate, source, and drain are common to each sub-transistor. When multiple sub-transistors are connected in series, the gate is common to each sub-transistor, and two adjacent sub-transistors are connected so that one source and the other drain are common. Note that hereinafter, a sub-transistor may also be simply referred to as a transistor.

[0039] Furthermore, it is preferable that each of the plurality of sub-transistors constituting the second transistor has approximately the same channel length and channel width. That is, it is preferable that the second transistor is configured by connecting a plurality of sub-transistors having the same design size in series, parallel, or series-parallel. This reduces the variation in the electrical characteristics of the second transistor between pixels compared to when the second transistor is configured with a single transistor.

[0040] Furthermore, it is preferable that the channel length directions of all the sub-transistors constituting the second transistor are the same. For example, it is preferable that the sub-transistors are arranged so that the channel length directions of all the transistors are parallel to the first direction or the second direction. In this case, it is also preferable that the channel width directions of all the sub-transistors are the same.

[0041] Furthermore, the channel formation regions of the plurality of sub-transistors are preferably arranged at equal intervals. Note that the channel formation region here refers to a part of the semiconductor layer of the transistor that overlaps with the gate in a plan view.

[0042] Furthermore, it is preferable that the first transistor and one of the sub-transistors have approximately the same channel length and channel width. Furthermore, it is preferable that they are equal in the channel length direction and the channel width direction. In particular, it is preferable that all of the multiple transistors constituting a pixel are composed of sub-transistors designed to be the same size.

[0043] Furthermore, the channel length direction of the first transistor is preferably parallel to the first direction or the second direction. In this case, the channel length direction of the sub-transistor is preferably parallel to the channel length direction of the first transistor. In this way, aligning the current flow directions of the multiple transistors constituting a pixel is preferable because it simplifies the design.

[0044] A more specific example will be described below with reference to the drawings.

[0045] [Configuration Example] FIGS. 1A, 1B, and 1C illustrate examples of pixel circuits in a display device of one embodiment of the present invention.

[0046] 1A, 1B, and 1C includes a transistor M1, a transistor M2, a capacitor C1, and a light-emitting element EL. In addition, the pixel circuit is electrically connected to a wiring GL, a wiring SL, a wiring AL, and a wiring CL.

[0047] A gate signal is applied to the wiring GL. A source signal is applied to the wiring SL. A constant potential is applied to the wirings AL and CL. The anode side of the light-emitting element EL can be set to a high potential, and the cathode side can be set to a lower potential than the anode side.

[0048] The transistor M1, which can also be called a selection transistor, functions as a switch for controlling pixel selection / non-selection. The transistor M1 has a gate electrically connected to a wiring GL, one of a source and a drain electrically connected to a wiring SL, and the other electrically connected to one electrode of a capacitor C1 and the transistor M2.

[0049] The capacitor C1 functions as a storage capacitor. The other electrode of the capacitor C1 is electrically connected to one electrode of the light-emitting element EL. The capacitor C1 does not have to be provided if it is not necessary.

[0050] The transistor M2 can also be called a drive transistor, and has a function of controlling the current flowing through the light-emitting element EL.

[0051] The transistor M2 is composed of a plurality of transistors (sub-transistors).

[0052] In FIG. 1A, the transistor M2 is a transistor m ｉ (i is an integer between 1 and p) ｉ The gates of the transistors are electrically connected (also referred to as having a common gate).

[0053] Transistor m １ to transistor m ｐ Among them, transistor m １ One of the source and drain is electrically connected to the wiring AL, and the other is connected to the transistor m ２ The transistor m is electrically connected to one of the source and drain of the transistor m. ｐ is the source and drain of transistor m ｐ−１ The other of the source and drain of the transistor m is electrically connected to one electrode of the light-emitting element EL and the other electrode of the capacitor C1. １ , transistor m ｐ Transistors other than m ｉ (Transistor m ２ to transistor m ｐ−１ ) is the transistor m ｉ−１The other of the source and drain of the transistor m ｉ＋１ The transistor is electrically connected to one of the source and drain of the transistor.

[0054] FIG. 1B shows a transistor M2 connected in parallel to q (q is an integer of 2 or more) transistors m ｊ (j is an integer of 1 or more and q or less). ｊ have a common gate, source, and drain.

[0055] Transistor m １ to transistor m ｑ The gates of the transistors M1 and M2 are electrically connected to the other of the source and drain of the transistor M1. １ to transistor m ｑ In each of the light-emitting elements, one of a source and a drain is electrically connected to a wiring AL, and the other is electrically connected to one electrode of the light-emitting element EL.

[0056] FIG. 1C shows that transistor M2 is connected to p×q transistors m ｉｊ Specifically, q units each having p transistors connected in series are connected in parallel.

[0057] In the configurations shown in FIGS. 1A, 1B, and 1C, the transistor m constituting the transistor M2 ｉ , transistor m ｊ or transistor m ｉｊ (Hereinafter, when there is no need to distinguish between them, they will be referred to as transistor m) preferably have the same transistor structure and approximately the same channel length and channel width.

[0058] For example, let the channel length of transistor m be L and the channel width be W. In this case, transistor M2 in FIG. 1A can be treated as a single transistor with a channel length of p×L and a channel width of W. Transistor M2 in FIG. 1B can be treated as a single transistor with a channel length of L and a channel width of q×W. Transistor M2 in FIG. 1C can be treated as a single transistor with a channel length of p×L and a channel width of q×W.

[0059] Next, an example of a pixel circuit different from the above will be described. Note that, although the following illustrates and describes a case where the transistor M2 is configured by connecting multiple transistors in series as illustrated in Fig. 1A, the transistor M2 illustrated in Fig. 1B and Fig. 1C can also be applied.

[0060] The pixel circuit shown in Fig. 2A has a configuration in which a transistor M3 is added to the configuration in Fig. 1A. A wiring V0 is also electrically connected to the pixel circuit in Fig. 2A.

[0061] The transistor M3 has a gate electrically connected to the wiring GL, one of a source and a drain electrically connected to the anode of the light-emitting element EL, and the other electrically connected to the wiring V0.

[0062] A constant potential is applied to the wiring V0 when data is written to the pixel circuit, thereby suppressing variations in the gate-source voltage of the transistor M2.

[0063] The pixel circuit shown in FIG. 2B has the transistors M1 and M2 of the pixel circuit shown in FIG. 1A. ｉ This is an example in which a transistor having a pair of gates is applied to the above.

[0064] The transistor M1 has a pair of gates electrically connected to each other, which increases the current that the transistor can pass. １ to transistor m ｎ is the back gate of transistor m ｎFor example, when a potential higher than that of the wiring CL is applied to the wiring AL, the transistor m ｎ The source of the transistor M2 is electrically connected to the back gate of each transistor, thereby stabilizing the electrical characteristics of the transistor M2 and improving its reliability.

[0065] FIG. 2C shows an example in which a transistor having a pair of gates is applied to each transistor of the pixel circuit in FIG. 2A.

[0066] 2D and 2E show different examples of the transistor M2. As shown in FIG. １ to transistor m ｎ The back gates of the transistors m may be electrically connected to their respective sources. １ to transistor m ｎ The back gate and the gate of each of the transistors may be electrically connected to each other.

[0067] 3A shows a configuration in which a transistor M4 is added to the configuration shown in FIG. 3A. In addition, in FIG. 3A, three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines are electrically connected.

[0068] The gate of the transistor M4 is electrically connected to a wiring GL3, one of the source and drain of the transistor M4 is electrically connected to the gate of the transistor M2, and the other is electrically connected to a wiring V0. The gate of the transistor M1 is electrically connected to a wiring GL1, and the gate of the transistor M3 is electrically connected to a wiring GL2.

[0069] By turning on transistors M3 and M4 for the same period, the source and gate of transistor M2 have the same potential, making it possible to turn off transistor M2. This makes it possible to forcibly cut off the current flowing through the light-emitting element EL. This pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0070] The pixel circuit shown in Fig. 3B is an example in which a capacitor C2 is added to the circuit shown in Fig. 3A. The capacitor C2 functions as a storage capacitor.

[0071] 3C and 3D are examples of pixel circuits in which transistors each having a pair of gates are applied to the circuit in FIG. 3A or 3B, respectively. Transistors M1, M3, and M4 are transistors in which a pair of gates are electrically connected, and transistor M2 is a transistor in which one gate is electrically connected to its source.

[0072] [Driving Method Example] An example of a driving method for a display device to which the pixel circuit illustrated in Fig. 3A is applied will be described below. Note that the same driving method can also be applied to Figs. 3B, 3C, and 3D.

[0073] 4 is a timing chart illustrating a driving method of a display device. The timing chart illustrates transitions in potentials of the wirings GL1[k], GL2[k], and GL3[k], which are gate lines in the kth row, and the wirings GL1[k+1], GL2[k+1], and GL3[k+1], which are gate lines in the k+1th row. The timing chart also illustrates timings of signals applied to the wirings SL, which function as source lines.

[0074] Here, an example of a driving method is shown in which one horizontal period is divided into a light-on period and a light-off period. The horizontal period for the kth row and the horizontal period for the k+1th row are shifted by the selection period of the gate line.

[0075] During the lighting period of the kth row, a high-level potential is first applied to the wiring GL1[k] and the wiring GL2[k], and a source signal is applied to the wiring SL. This brings the transistors M1 and M3 into conduction, and a potential corresponding to the source signal is written from the wiring SL to the gate of the transistor M2. After that, a low-level potential is applied to the wiring GL1[k] and the wiring GL2[k], bringing the transistors M1 and M3 into non-conduction, and the gate potential of the transistor M2 is maintained.

[0076] Subsequently, the lighting period of the k+1th row begins, and data is written in the same manner as above.

[0077] Next, the off period will be described. During the off period of the kth row, a high-level potential is applied to the wiring GL2[k] and the wiring GL3[k]. As a result, the transistors M3 and M4 are turned on, and the same potential is applied to the source and gate of the transistor M2, so that almost no current flows through the transistor M2. This turns off the light-emitting element EL. All subpixels located in the kth row are turned off. The subpixels in the kth row remain off until the next light-on period.

[0078] Next, the process transitions to the off period of the k+1th row, and all the sub-pixels of the k+1th row are in the off state in the same manner as above.

[0079] This driving method, in which the display is not always on throughout one horizontal period but has an off period during one horizontal period, can also be called duty driving. Duty driving can reduce the afterimage phenomenon when displaying moving images, thereby realizing a display device with high moving image display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0080] In duty driving, the ratio of the on period to one horizontal period can be called the duty ratio. For example, a duty ratio of 50% means that the on period and the off period are the same length. The duty ratio can be freely set and can be adjusted as appropriate within a range of, for example, more than 0% and less than 100%.

[0081] The above is a description of an example of a driving method.

[0082] [Structure Example of Transistor] Next, a structure example of a transistor that can be used for a pixel of a display device of one embodiment of the present invention will be described.

[0083] 5A and 5B are a schematic top view and a schematic cross-sectional view of the transistor 10. The transistor 10 includes a semiconductor layer 31, a conductive layer 21, a conductive layer 22, an insulating layer 51, an insulating layer 52, and the like.

[0084] The semiconductor layer 31 has a region 31i that functions as a channel formation region and a pair of regions 31n that sandwich the region 31i and function as low-resistance regions. One of the pair of regions 31n functions as a source, and the other functions as a drain. An insulating layer 51 is provided to cover the semiconductor layer 31, and a portion of it functions as a gate insulating layer. A conductive layer 22 is provided on the insulating layer 51, and a portion of it functions as a gate electrode. The conductive layer 22 has a portion that overlaps with the region 31i of the semiconductor layer 31. The insulating layer 52 functions as an interlayer insulating layer and is provided to cover the insulating layer 51 and the conductive layer 22. The pair of conductive layers 21 are each provided on the insulating layer 52. The conductive layer 21 is electrically connected to the region 31i at the contact portion 41 through openings provided in the insulating layer 52 and the insulating layer 51. A portion of the conductive layer 21 functions as a source electrode or a drain electrode.

[0085] The semiconductor layer 31 preferably contains a metal oxide (oxide semiconductor) having a band gap wider than that of silicon. This allows a transistor with low off-state current to be realized. In particular, the semiconductor layer 31 preferably contains a metal oxide containing one or both of indium and zinc.

[0086] Alternatively, the semiconductor layer 31 may contain silicon, such as amorphous silicon or crystalline silicon (such as low-temperature polysilicon or single-crystal silicon).

[0087] 5 illustrates a so-called top-gate transistor in which a gate electrode is located above the semiconductor layer 31 as the transistor 10, but the structure of the transistor is not limited thereto and various structures can be used. For example, a bottom-gate transistor or a dual-gate transistor can be applied to the display device.

[0088] 5 is used as a basic structure, and examples of transistors and pixel circuits manufactured by combining these structures will be described below. Note that, unless otherwise specified, the same reference numerals will be used to denote components formed on the same surface in the same process. For example, a conductive layer, part of which functions as a gate electrode, and a conductive layer formed in the same process as the conductive layer and functioning as a wiring will be described with the same reference numerals.

[0089] 6A shows a circuit diagram of a transistor 10a and a transistor 10b described below. The transistor 10a and the transistor 10b are configured by four transistors 10 connected in series and sharing a gate. Each transistor 10 has a channel formation region in an island-shaped semiconductor layer 31.

[0090] Fig. 6B shows an example of a schematic top view of the transistor 10a. Fig. 6C shows a schematic cross-sectional view taken along the line A1-A2 in Fig. 6A. The transistor 10a has four conductive layers 22 functioning as gate electrodes provided at equal intervals on an island-shaped semiconductor layer 31 with an insulating layer 51 interposed therebetween.

[0091] The four conductive layers 22 are electrically connected via the conductive layer 21. The conductive layers 22 and 21 are electrically connected by the contact portions 42. This forms four transistors connected in series. Note that although an example in which the four conductive layers 22 are connected by the conductive layer 21 has been shown here, a single conductive layer 22 having a comb-like upper surface shape may also be used.

[0092] A pair of conductive layers 21 electrically connected to the region 31n are provided at both longitudinal ends of the semiconductor layer 31. Note that a conductive layer 21 may also be provided in the region between two adjacent conductive layers 22.

[0093] Figure 6D shows a schematic top view of transistor 10b. Figure 6E shows a schematic cross-sectional view taken along line A3-A4 in Figure 6D. Transistor 10b has a configuration in which two semiconductor layers 31 are arranged symmetrically (here, vertically symmetrically) with a gap between them, and are connected by a conductive layer 21. Furthermore, two conductive layers 22 are arranged symmetrically (here, horizontally symmetrically) with a gap between them, and are arranged so as to intersect with the two semiconductor layers 31. This configuration can reduce the area occupied.

[0094] 7A shows a circuit diagram of the transistor 10c, which is composed of four transistors 10 connected in parallel and sharing the gate, source, and drain.

[0095] Fig. 7B shows an example of a schematic top view of the transistor 10c. Fig. 7C shows a schematic cross-sectional view taken along the line A5-A6 in Fig. 7B. The transistor 10c has four equally spaced island-shaped semiconductor layers 31 on which one conductive layer 22 intersects. The conductive layers 21 are connected to both ends of the four island-shaped semiconductor layers 31.

[0096] 7D shows a circuit diagram of the transistor 10d. The transistor 10d has four transistors with a common gate, and two of the four transistors are connected in series.

[0097] 7E shows an example of a schematic top view of a transistor 10d. The transistor 10d has a similar configuration to that shown in FIG. 6D except for the shape of the conductive layer 21. A pair of conductive layers 21 is provided to connect the two semiconductor layers 31 to both ends of the two semiconductor layers 31. Each of the pair of conductive layers 21 electrically connects the two semiconductor layers.

[0098] Although the transistors 10a to 10d each include four transistors 10, the present invention is not limited thereto, and the number of transistors 10 may be two, three, five or more.

[0099] [Example of Layout Method] Hereinafter, an example of layout will be described in the case where transistors having approximately the same channel length and channel width are combined.

[0100] The basic configuration is shown in Fig. 8A. In Fig. 8A, a plurality of semiconductor layers 31 whose longitudinal direction is parallel to the X direction are arranged at equal intervals in the Y direction. Furthermore, a plurality of conductive layers 22 whose longitudinal direction is parallel to the Y direction are arranged at equal intervals in the X direction. The intersections between the conductive layers 22 and the semiconductor layers 31 form the channel formation regions (regions 31i) of the transistors.

[0101] Here, the arrangement interval of the semiconductor layers 31 in the Y direction is defined as Py, and the arrangement interval of the conductive layers 22 in the X direction is defined as Px.

[0102] 8A , the semiconductor layer 31 is preferably processed so that the width in the Y direction of a region located between two conductive layers 22 is larger than the width of a region overlapping with the conductive layer 22. This increases the area of ​​the contact portion 41 between the semiconductor layer 31 and the conductive layer 21, thereby reducing the resistance therebetween (also referred to as contact resistance or contact resistance).

[0103] Using the layout shown in FIG. 8A as a basic configuration, by dividing the semiconductor layer 31 extending in the X direction, dividing the conductive layer 22 extending in the Y direction, and connecting the semiconductor layers 31 to each other, the conductive layers 22 to each other, or the semiconductor layer 31 and the conductive layer 22 with the conductive layer 21, etc., it is possible to configure transistors of various sizes or various circuits by combining transistors 10 having approximately the same channel length and channel width.

[0104] Figure 8B shows an application example of the layout of Figure 8A, which shows transistors 10e, 10f, 10g, and 10h.

[0105] The transistor 10e is a single transistor. The transistors 10f and 10g each have a configuration in which two transistors are connected in series. The transistor 10h, like the transistor 10e shown in FIG. 7E, has a configuration in which two transistors are connected in parallel and two in series, four transistors.

[0106] 8B shows a plurality of conductive layers 21. As shown in FIG. 8B, it is preferable to arrange the conductive layers 21 as equally spaced as possible. This reduces variations in the processed shape of the conductive layers 21. FIG. 8B shows an example in which the arrangement interval of the conductive layers 21 is set to Px, which is the same as the arrangement interval of the conductive layers 22.

[0107] Furthermore, dummy layers may be disposed in areas where no transistors are disposed. For example, electrically floating semiconductor layers 31, conductive layers 22, or conductive layers 21 may be disposed in the empty spaces. Note that a dummy layer is a layer disposed in the empty spaces for the purpose of stabilizing the manufacturing process, reducing processing variations, etc., and is basically not considered as a component that constitutes a circuit. For this reason, the dummy layer is either electrically floating or has a constant voltage applied to it. Note that it is also preferable to provide dummy layers in layers other than semiconductor layers.

[0108] 8B, a plurality of dummy transistors 11 may be arranged. A dummy transistor has a stacked structure that functions as a transistor, and one or more of the gate, drain, and source are electrically floating.

[0109] In this way, by arranging the dummy transistor 11 in an area where no transistor is provided, it is possible to reduce variations in the processed shapes of the semiconductor layer 31, the conductive layer 22, etc., and to reduce variations in the electrical characteristics of the transistors.

[0110] [Pixel Configuration Example] A specific pixel configuration example will be described below.

[0111] 9 shows a schematic top view of a pixel 20 included in a display device. The pixel 20 includes sub-pixels 20R, 20G, and 20B. The display device includes a plurality of pixels 20, which are periodically arranged in the X and Y directions.

[0112] The sub-pixel 20R has a light-emitting element 12R that emits red light, the sub-pixel 20G has a light-emitting element 12G that emits green light, and the sub-pixel 20B has a light-emitting element 12B that emits blue light.

[0113] The light-emitting elements 12R, 12G, and 12B may each be configured to contain a different light-emitting material, or may each be configured to combine a white-emitting light-emitting element with a color filter, or may each be configured to combine a blue or purple light-emitting element with a color conversion material (such as quantum dots).

[0114] 10A to 10E each show a schematic top view of one subpixel 20X included in the pixel 20 shown in Fig. 9. The subpixel 20X can be applied to the subpixels 20R, 20G, and 20B. Note that light-emitting elements are omitted here.

[0115] 10B, only the outline of the pixel electrode 24 shown in FIG. 10A is clearly indicated by a broken line, and an example of the top surface shape of the conductive layer 23 is shown.

[0116] The wiring formed by the conductive layer 23 functions as a power supply line to the light emitting element 12R etc., and is given a constant potential. When the pixel electrode 24 functions as an anode, a high power supply potential is given to the wiring, and when it functions as a cathode, a low power supply potential is given to the wiring.

[0117] 10B, it is preferable that the conductive layer 23 functioning as wiring has not only a portion extending in the Y direction but also a portion extending in the X direction. This allows the conductive layer 23 to have a lattice-like upper surface shape, which can suppress the effect of voltage drop compared to when the conductive layer 23 has a striped upper surface shape.

[0118] In Fig. 10C, the conductive layer 23 in Fig. 10B is shown by a dashed line, while in Fig. 10D, the conductive layer 21 in Fig. 10C is shown by a dashed line, and in Fig. 10E, the conductive layer 22 in Fig. 10D is shown by a dashed line.

[0119] 10C and 10D show transistors 30a and 30b. Also, FIG. 10D shows a semiconductor layer 31a included in the transistor 30a and a semiconductor layer 31b included in the transistor 30b. The transistor 30a functions as a selection transistor that controls the selection and non-selection of a subpixel. The transistor 30b functions as a drive transistor that controls the current flowing through a light-emitting element.

[0120] The transistor 30a has a conductive layer 22 functioning as a gate line, which forms part of the gate, one of the source and drain electrically connected to the conductive layer 21 functioning as a source line, and the other electrically connected to the gate of the transistor 30b. The transistor 30b has a source and drain electrically connected to the conductive layer 23, and the other electrically connected to the pixel electrode 24.

[0121] Here, the transistor 30b is composed of four transistors connected in series and sharing a gate. The channel length of the transistor 30b is four times that of the transistor 30a, and the channel width of the transistor 30b is equal to that of the transistor 30a, so the transistor 30b can be treated as a single transistor. The transistor 30b has four channel formation regions in one island-shaped semiconductor layer 31b.

[0122] Here, an example is shown in which the top surface shape of each of the semiconductor layers 31a and 31b has a pair of thick portions where contact portions are arranged and a thin portion formed as a channel.

[0123] In the subpixel 20X, the semiconductor layer 31a of the transistor 30a and the semiconductor layer 31b of the transistor 30b are arranged so that current flows in the Y direction, that is, in a direction parallel to the extension direction of the conductive layer 21 that functions as a source line. In other words, the transistors 30a and 30b are arranged so that their channel length directions are parallel to the Y direction and their channel width directions are parallel to the X direction. In this way, aligning the current flow directions for the multiple transistors that make up a pixel is preferable because it simplifies the design.

[0124] 10D and other figures, it is preferable to provide a plurality of dummy layers 32. The dummy layers 32 are formed by processing the same film as the semiconductor layers 31 a and 31 b, and can be films having the same composition as the semiconductor layers 31 a and 31 b. In addition, in Figures 10A to 10E, the semiconductor layers 31 a and 31 b are shown with different hatching patterns to distinguish them from the dummy layers 32.

[0125] The top surface shape of the dummy layer 32 is preferably the same as the top surface shape of the semiconductor layer 31a and the semiconductor layer 31b, or a shape that is a periodic combination of these. In the subpixel 20X, each dummy layer 32 has a top surface shape that has two or more thick portions and a thin portion connecting the two thick portions in the Y direction. Each dummy layer 32 is arranged so that its longitudinal direction is parallel to the Y direction. Furthermore, one dummy layer 32 is arranged across multiple pixels arranged in the Y direction.

[0126] In this way, by placing the dummy layer 32 in the area where the semiconductor layer 31a and the semiconductor layer 31b are not provided, the variation in the processed shape of the semiconductor layer 31a and the semiconductor layer 31b can be reduced, and the variation in the electrical characteristics of the transistor 30a and the transistor 30b can be reduced.

[0127] The dummy layer 32 is preferably arranged as closely as possible to the area where the semiconductor layer 31 a and the semiconductor layer 31 b are not provided. In the subpixel 20X, an example is shown in which the dummy layer 32 is arranged so as to avoid the area where the conductive layer 21 is provided, but the dummy layer 32 may be arranged so as to overlap the conductive layer 21.

[0128] Although an example in which two transistors are arranged in one subpixel has been shown here, the present invention is not limited to this, and a configuration in which three or more transistors are arranged may also be used. In this case, it is preferable that the semiconductor layers of all the transistors provided in the subpixel have the same pattern and that the direction of current flowing through the semiconductor layers is the same.

[0129] [Configuration Example 2] Below, a configuration example that differs in part from the above will be described with reference to the drawings. Note that the following description may omit parts that overlap with the above. Furthermore, in the drawings shown below, components having the same functions are given the same hatching patterns and symbols, and descriptions thereof may be omitted.

[0130] Fig. 11 shows a schematic top view of a display device exemplified below. In the display device shown in Fig. 11, wiring such as source lines and power supply lines extending in the Y direction is formed of a conductive layer 23, and wiring such as gate lines extending in the X direction is formed of a conductive layer 21.

[0131] 12A to 12E are schematic top views of the subpixel 20X. The display devices exemplified below differ from the display device exemplified in Configuration Example 1 above in that the orientation of the semiconductor layers is different and that four transistors are provided. The subpixel 20X shown in Fig. 11 and Fig. 12A to 12E corresponds to, for example, the pixel circuit exemplified in Fig. 3A.

[0132] 12C and 12D , the subpixel 20X includes transistors 30a, 30b, 30c, and 30d. Each of the transistors 30a, 30c, and 30d is formed by a single transistor. The transistor 30b includes six transistors connected in series. The transistor 30b includes two channel formation regions in each of three semiconductor layers 31b arranged at equal intervals in the Y direction.

[0133] The dummy layer 32 is disposed so that its longitudinal direction is parallel to the X direction. The dummy layer 32 is disposed across a plurality of pixels arranged in the X direction.

[0134] In addition, in Figure 12D etc., the dummy layer 29, which is formed in the same process as the conductive layer 22 and is electrically floating, is shown with a different hatching pattern to distinguish it from the conductive layer 22 which functions as a gate electrode, wiring, etc.

[0135] The sub-pixel 20X has a plurality of dummy transistors 11 each configured by a dummy layer 32 and a dummy layer 29 .

[0136] The above is a description of an example of the pixel configuration.

[0137] [Cross-Sectional Structure Example] Next, a cross-sectional structure example of a display device according to one embodiment of the present invention will be described.

[0138] 13 is a schematic cross-sectional view of a display device 200 A. The display device 200 A has, between a substrate 201 and a substrate 202, a light-emitting element 250 R, a light-emitting element 250 G, a transistor 210 , a transistor 220 , a capacitor 240 , and the like.

[0139] The transistor 210 is a transistor in which a channel formation region is formed in a substrate 201. The substrate 201 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 210 includes a part of the substrate 201, a conductive layer 211, a low-resistance region 212, an insulating layer 213, an insulating layer 214, and the like. The conductive layer 211 functions as a gate electrode. The insulating layer 213 is located between the substrate 201 and the conductive layer 211 and functions as a gate insulating layer. The low-resistance region 212 is a region in which the substrate 201 is doped with impurities and functions as one of a source and a drain. The insulating layer 214 is provided to cover a side surface of the conductive layer 211.

[0140] Furthermore, an element isolation layer 215 is provided between two adjacent transistors 210 so as to be embedded in the substrate 201 .

[0141] A wiring layer 203 is provided between the transistor 210 and the transistor 220. The wiring layer 203 has a structure in which layers each having one or more wirings are stacked. Each layer has a conductive layer 271, and an interlayer insulating layer 273 is provided between two layers. Furthermore, the conductive layers 271 of different layers are electrically connected to each other by plugs 272 provided in the interlayer insulating layer 273.

[0142] A transistor 220 is provided over the wiring layer 203. The transistor 220 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0143] The transistor 220 includes a semiconductor layer 221, an insulating layer 223, a conductive layer 224, a pair of conductive layers 225, an insulating layer 226, a conductive layer 227, and the like.

[0144] An insulating layer 231 is provided over the wiring layer 203. The insulating layer 231 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the wiring layer 203 side to the transistor 220 and prevents oxygen from being released from the semiconductor layer 221 to the wiring layer 203 side. As the insulating layer 231, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0145] A conductive layer 227 is provided over the insulating layer 231, and an insulating layer 226 is provided to cover the conductive layer 227. The conductive layer 227 functions as a first gate electrode of the transistor 220, and part of the insulating layer 226 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 226 that is in contact with the semiconductor layer 221.

[0146] The semiconductor layer 221 is provided over the insulating layer 226. The semiconductor layer 221 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics.

[0147] When the semiconductor layer 221 is an In-M-Zn oxide, the atomic ratio of metal elements in a sputtering target used to form the In-M-Zn oxide is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2. :1, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, I Examples include n:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and the like.

[0148] Furthermore, it is preferable to use a target containing a polycrystalline oxide as the sputtering target, since this facilitates the formation of a crystalline semiconductor layer 221. The atomic ratio of the semiconductor layer 221 to be formed varies within a range of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 221 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 221 to be formed may be close to In:Ga:Zn = 4:2:3 [atomic ratio].

[0149] When the atomic ratio is described as In:Ga:Zn = 4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When the atomic ratio is described as In:Ga:Zn = 5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. When the atomic ratio is described as In:Ga:Zn = 1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0150] The energy gap of the semiconductor layer 221 is 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

[0151] The semiconductor layer 221 preferably has a non-single-crystal structure. Examples of the non-single-crystal structure include a CAAC structure, a polycrystalline structure, a microcrystalline structure, and an amorphous structure, which will be described later. Among the non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0152] Below, we will explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0153] The CAAC structure is a crystalline structure such as a thin film having a plurality of nanocrystals (crystalline regions with a maximum diameter of less than 10 nm), in which the c-axis of each nanocrystal is oriented in a specific direction, and the a-axis and b-axis are not oriented, and the nanocrystals are continuously connected without forming grain boundaries. In particular, a thin film having a CAAC structure is characterized in that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the surface of the thin film.

[0154] CAAC-OS (oxide semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries are observed in CAAC-OS, it can be said that a decrease in electron mobility due to the crystal grain boundaries is unlikely to occur. Furthermore, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities, the generation of defects, or the like, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having CAAC-OS is heat-resistant and highly reliable.

[0155] In crystallography, it is common to take a unit cell with a specific axis as the c-axis among the three axes (crystal axes) of the a-axis, b-axis, and c-axis that make up the unit cell. In particular, in crystals with a layered structure, it is common to take the two axes parallel to the plane direction of the layer as the a-axis and b-axis, and the axis intersecting the layer as the c-axis. A typical example of a crystal with such a layered structure is graphite, which is classified as a hexagonal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, YbFe, which has a layered structure, ２ O ４ InGaZnO with a type crystal structure ４ The crystals can be classified as hexagonal, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layers, and the c-axis is perpendicular to the layers (i.e., the a-axis and b-axis).

[0156] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly visible in a TEM image. The crystal parts included in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals with a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an nc-OS film, for example, crystal grain boundaries may not be clearly visible in a TEM image.

[0157] The nc-OS film has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS film does not exhibit regularity in the crystal orientation between different crystalline parts. Therefore, the entire film does not exhibit orientation. Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus using X-rays with a diameter larger than that of the crystalline parts, no peaks indicating crystal planes are detected by the out-of-plane analysis. Furthermore, when the nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of the crystalline parts (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to or smaller than the size of the crystalline portion, a circular (ring-shaped) region of high brightness is observed, and multiple spots may be observed within the ring-shaped region.

[0158] The nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film lacks regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier density and electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit high field-effect mobility.

[0159] The nc-OS film can be formed by lowering the oxygen flow rate during film formation compared to the CAAC-OS film. The nc-OS film can also be formed by lowering the substrate temperature during film formation compared to the CAAC-OS film. For example, the nc-OS film can be formed at a relatively low substrate temperature (for example, 130° C. or lower) or without heating the substrate. Therefore, the nc-OS film is suitable for use on a large glass substrate, a resin substrate, or the like, and can increase productivity.

[0160] An example of the crystal structure of a metal oxide will be described. A metal oxide formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) at a substrate temperature of 100°C or higher and 130°C or lower tends to have either an nc (nanocrystal) structure or a CAAC structure, or a mixed structure of these. On the other hand, a metal oxide formed at a substrate temperature of room temperature (RT) tends to have an nc crystal structure. Note that room temperature (RT) here includes a temperature when the substrate is not intentionally heated.

[0161] The pair of conductive layers 225 is provided over and in contact with the semiconductor layer 221 and functions as a source electrode and a drain electrode.

[0162] An insulating layer 232 is provided to cover top surfaces and side surfaces of the pair of conductive layers 225 and side surfaces of the semiconductor layer 221, and an insulating layer 261 is provided over the insulating layer 232. The insulating layer 232 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from an interlayer insulating layer or the like into the semiconductor layer 221 and prevents oxygen from being released from the semiconductor layer 221. The insulating layer 232 can be an insulating film similar to the insulating layer 231.

[0163] An opening reaching the semiconductor layer 221 is provided in the insulating layer 232 and the insulating layer 261. Inside the opening, an insulating layer 223 in contact with side surfaces of the insulating layer 261, the insulating layer 232, and the conductive layer 225 and an upper surface of the semiconductor layer 221, and a conductive layer 224 on the insulating layer 223 are buried. The conductive layer 224 functions as a second gate electrode, and the insulating layer 223 functions as a second gate insulating layer.

[0164] The top surface of the conductive layer 224, the top surface of the insulating layer 223, and the top surface of the insulating layer 261 are planarized so that they are approximately the same height, and an insulating layer 233 is provided to cover them. An opening is provided in the stacked structure between the insulating layer 233 and the insulating layer 231, and part of the insulating layer 233 is provided in contact with the insulating layer 231 in the opening. The insulating layer 261 functions as an interlayer insulating layer. The insulating layer 233 also functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from above. The insulating layer 233 can be an insulating film similar to the insulating layer 231.

[0165] A capacitor 240 is provided over the insulating layer 233 .

[0166] The capacitor 240 includes a conductive layer 241, a conductive layer 242, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 242 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0167] An insulating layer 234 is provided to cover the capacitor element 240. The insulating layer 234 can be formed using an insulating film similar to that of the insulating layer 231. An insulating layer 262 is provided over the insulating layer 231 with an interlayer insulating layer and wiring interposed therebetween, and the light-emitting element 250R and the light-emitting element 250G are provided over the insulating layer 262.

[0168] The light-emitting element 250R includes a conductive layer 251, a conductive layer 252R, an EL layer 253W, a conductive layer 254, and the like.

[0169] The conductive layer 251 is reflective to visible light, and the conductive layer 252R is transparent to visible light. The conductive layer 254 is reflective and transparent to visible light. The conductive layer 252R functions as an optical adjustment layer for adjusting the optical distance between the conductive layer 251 and the conductive layer 254. The optical adjustment layer can have different thicknesses for light-emitting elements that emit different colors of light. The conductive layer 252R of the light-emitting element 250R and the conductive layer 252G of the light-emitting element 250G have different thicknesses.

[0170] An insulating layer 256 is provided to cover the end of the conductive layer 252R and the end of the conductive layer 252G.

[0171] The EL layer 253W and the conductive layer 254 are provided in common across a plurality of pixels. The EL layer 253W has a light-emitting layer that emits white light.

[0172] An insulating layer 235 is provided to cover the light emitting elements 250R, 250G, etc. The insulating layer 235 functions as a barrier film that prevents impurities such as water from diffusing into the light emitting elements 250R, 250G, etc. The insulating layer 235 can be a film similar to the insulating layer 231.

[0173] A lens array 257 is provided on the light emitting element 250R and the light emitting element 250G via an adhesive layer 263. Light emitted from the light emitting element 250R is collected by the lens array 257, colored by the colored layer 255R, and emitted to the outside. The lens array 257 does not have to be provided if it is not necessary.

[0174] Furthermore, colored layers 255R, 255G, and 255B are provided on the lens array 257 via an insulating layer 264. The colored layer 255R is provided on the light-emitting element 250R via the lens array 257. The colored layer 255G is provided on the light-emitting element 250G. Also, part of the colored layer 255B is shown in FIG. 13 .

[0175] For example, the colored layer 255R transmits red light, the colored layer 255G transmits green light, and the colored layer 255B transmits blue light, thereby improving the color purity of the light from each light-emitting element and realizing a display device with higher display quality.

[0176] The display device 200A has a substrate 202 on the viewing side. The substrate 202 is bonded to the substrate 201. The substrate 202 can be a light-transmitting substrate such as a glass substrate, a quartz substrate, a sapphire substrate, or a plastic substrate.

[0177] The colored layers 255R, 255G, and 255B are formed on the surface of the substrate 202 facing the substrate 201. An insulating layer 264 is provided to cover the colored layers 255R and the like, and a lens array 257 is provided on the surface of the insulating layer 264 facing the substrate 201. The substrate 202 on which the colored layers 255R, 255G, 255B, and lens array 257 are provided is bonded to the substrate 201 by an adhesive layer 263. By forming the colored layers 255R, 255G, 255B, and lens array 257 on the substrate 202 side in this manner, the temperature of the heat treatment in the formation process can be increased.

[0178] Although the colored layers 255R, 255G, and 255B, and the lens array 257 are formed on the substrate 202 side here, the colored layers and the lens array 257 may be formed on the insulating layer 235. In this case, the alignment accuracy between each light-emitting element and each colored layer can be improved compared to when the colored layers are formed on the substrate 202 side and then the substrates 201 and 202 are bonded together.

[0179] With this configuration, a display device with extremely high definition and high display quality can be realized.

[0180] [Cross-Sectional Configuration Example 2] FIG. 14 shows a schematic cross-sectional view of a display device 200B that is partially different in configuration from the display device 200A.

[0181] In the display device 200B, the EL layer 253W is divided on the insulating layer 256 located between two light-emitting elements. By dividing the EL layer 253W, it is possible to prevent leakage current from occurring between the light-emitting elements via the EL layer 253W. This is preferable because it prevents unintended light emission and improves contrast and color reproducibility.

[0182] The EL layer 253W may be divided by a vapor deposition method using a fine metal mask, but is preferably finely processed by a photolithography method.

[0183] Cross-Sectional Configuration Example 3 FIG. 15 is a schematic cross-sectional view of a display device 200C.

[0184] The light emitting element 250R has an EL layer 253R that emits red light, and the light emitting element 250G has an EL layer 253G that emits green light.

[0185] In addition, here, an example is shown in which the display device 200C does not have a colored layer.

[0186] Furthermore, the EL layer 253R and the EL layer 253G are processed so as not to contact each other between two adjacent light-emitting elements. In other words, between two adjacent light-emitting elements, an end of the EL layer 253R and an end of the EL layer 253G are provided facing each other on the insulating layer 256. The EL layer 253R and the EL layer 253G may be separately formed by a vapor deposition method using a fine metal mask, but it is preferable that they are each finely processed by a photolithography method.

[0187] Furthermore, an insulating layer 258 is provided between the light-emitting element 250R and the light-emitting element 250G in contact with the side surface of the EL layer 253R, the side surface of the conductive layer 252R, the side surfaces of the pair of conductive layers 251, the top surface of the insulating layer 262, the side surface of the conductive layer 252G, and the side surface of the EL layer 253G. The insulating layer 258 can be made of a material with low water permeability, and can be made of an insulating film similar to the insulating layer 231. In particular, it is preferable to use an inorganic insulating film formed by the ALD method. It is more preferable to use an aluminum oxide film formed by the ALD method.

[0188] In addition, a resin layer 259 is provided on the insulating layer 258 so as to fill recesses located between adjacent pixels. The resin layer 259 functions as a planarizing film and has the function of improving the coverage of a film (e.g., the conductive layer 254) formed thereon.

[0189] Although the conductive layers 252R and 252G functioning as optical adjustment layers have different thicknesses in this example, the optical adjustment layers of each light-emitting element may have the same thickness. In this case, it is preferable to use a portion of the EL layer as the optical adjustment layer and control the optical path length by its thickness. Furthermore, the conductive layers 252R and 252G may not be provided.

[0190] 16 is a schematic cross-sectional view of a display device 200D. The display device 200D differs from the display device 200C mainly in that the transistor 210 is not included.

[0191] An insulating layer 231 is provided over the substrate 201, and the transistor 220 is provided over the insulating layer 231. Note that if there is no risk of impurities or the like diffusing from the substrate 201, the insulating layer 231 is not necessarily provided.

[0192] It is preferable to use a substrate with a low thermal expansion coefficient as the substrate 201. For example, it is preferable to use a single crystal semiconductor substrate such as single crystal silicon or silicon carbide, or a high melting point insulating substrate such as sapphire or quartz.

[0193] The above is a description of the cross-sectional configuration example.

[0194] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0195] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0196] Embodiment 2 In this embodiment, a light-emitting element (also referred to as a light-emitting device) and a light-receiving element (also referred to as a light-receiving device) that can be used for a light-emitting and receiving device that is one embodiment of the present invention will be described.

[0197] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0198] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (for example, a color filter) to form a full-color display device.

[0199] [Light-Emitting Device] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission with a single structure, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0200] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, with each light-emitting unit preferably including one or more light-emitting layers. By using light-emitting layers that emit light of the same color in each light-emitting unit, the luminance per given current can be increased, and the device can be made more reliable than a single-structure light-emitting device. To obtain white light emission in a tandem structure, the device can be configured to combine light from the light-emitting layers of multiple light-emitting units to obtain white light. The combination of light-emitting colors that can produce white light is the same as in the single-structure configuration. In a tandem-structure device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0201] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0202] 17A , the light-emitting device has an EL layer 790 between a pair of electrodes (a lower electrode 791 and an upper electrode 792). The EL layer 790 can be composed of multiple layers, such as a layer 720, a light-emitting layer 711, and a layer 730. The layer 720 can have, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 711 contains, for example, a light-emitting compound. The layer 730 can have, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0203] A structure having the layer 720, the light-emitting layer 711, and the layer 730 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 17A is referred to as a single structure in this specification.

[0204] 17B shows a modified example of the EL layer 790 included in the light-emitting device shown in Fig. 17A. Specifically, the light-emitting device shown in Fig. 17B has a layer 730-1 on a lower electrode 791, a layer 730-2 on the layer 730-1, a light-emitting layer 711 on the layer 730-2, a layer 720-1 on the light-emitting layer 711, a layer 720-2 on the layer 720-1, and an upper electrode 792 on the layer 720-2. For example, when the lower electrode 791 is an anode and the upper electrode 792 is a cathode, the layer 730-1 functions as a hole injection layer, the layer 730-2 functions as a hole transport layer, the layer 720-1 functions as an electron transport layer, and the layer 720-2 functions as an electron injection layer. Alternatively, when the lower electrode 791 is used as a cathode and the upper electrode 792 is used as an anode, the layer 730-1 functions as an electron injection layer, the layer 730-2 functions as an electron transport layer, the layer 720-1 functions as a hole transport layer, and the layer 720-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 711 and increase the efficiency of carrier recombination in the light-emitting layer 711.

[0205] As shown in FIGS. 17C and 17D, a configuration in which a plurality of light-emitting layers (light-emitting layers 711, 712, and 713) are provided between the layer 720 and the layer 730 is also a variation of the single structure.

[0206] 17E and 17F, a configuration in which a plurality of light-emitting units (EL layer 790a, EL layer 790b) are connected in series via an intermediate layer (charge generating layer) 740 is referred to as a tandem structure in this specification. Note that, although the configuration shown in FIGS. 17E and 17F is referred to as a tandem structure in this specification and the like, this is not limiting, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting device capable of emitting light with high brightness can be obtained.

[0207] In FIG. 17C, the light-emitting layer 711, the light-emitting layer 712, and the light-emitting layer 713 may be made of the same light-emitting material.

[0208] Furthermore, different light-emitting materials may be used for the light-emitting layer 711, the light-emitting layer 712, and the light-emitting layer 713. When the light emitted from the light-emitting layer 711, the light-emitting layer 712, and the light-emitting layer 713 has a complementary color relationship, white light can be obtained. Fig. 17D shows an example in which a colored layer 795 that functions as a color filter is provided. When white light passes through the color filter, light of a desired color can be obtained.

[0209] 17E, the same light-emitting material may be used for the light-emitting layer 711 and the light-emitting layer 712. Alternatively, light-emitting materials that emit different light may be used for the light-emitting layer 711 and the light-emitting layer 712. When the light emitted by the light-emitting layer 711 and the light emitted by the light-emitting layer 712 are complementary colors, white light is obtained. FIG. 17F shows an example in which a colored layer 795 is further provided.

[0210] 17C, 17D, 17E, and 17F, the layer 720 and the layer 730 may have a laminated structure consisting of two or more layers, as shown in FIG. 17B.

[0211] 17D, the same light-emitting material may be used for the light-emitting layers 711, 712, and 713. Similarly, in FIG. 17F, the same light-emitting material may be used for the light-emitting layers 711 and 712. In this case, by applying a color conversion layer instead of the colored layer 795, light of a desired color different from the light-emitting material can be obtained. For example, by using a blue light-emitting material for each light-emitting layer and transmitting blue light through the color conversion layer, light with a longer wavelength than blue (e.g., red, green, or other light) can be obtained. For the color conversion layer, a fluorescent material, a phosphorescent material, or quantum dots can be used.

[0212] The light-emitting device can emit light of red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 790. Furthermore, the color purity can be further improved by providing the light-emitting device with a microcavity structure.

[0213] A light-emitting device that emits white light preferably has a configuration in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, light-emitting materials can be selected such that the respective emissions of the two or more light-emitting materials have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a light-emitting device that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0214] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0215] [Light-Emitting Device] Here, a specific example of the configuration of the light-emitting device will be described.

[0216] The light-emitting device has at least a light-emitting layer. The light-emitting device may further have, as a layer other than the light-emitting layer, a layer containing a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, an electron-blocking material, a substance with high electron-injection properties, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties), or the like.

[0217] The light-emitting device can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting device can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0218] For example, the light-emitting device may have, in addition to the light-emitting layer, one or more of a hole-injection layer, a hole-transport layer, a hole-blocking layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer.

[0219] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0220] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 −６ cm ２ A substance having a hole mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0221] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a molecular weight of 1×10 −６ cm ２ A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0222] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0223] The electron injection layer may be formed of, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ２ ), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), lithium oxide (LiO ｘ ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used. The electron injection layer may have a stacked structure of two or more layers. For example, the stacked structure may have a structure in which lithium fluoride is used in the first layer and ytterbium is used in the second layer.

[0224] Alternatively, the electron injection layer may be formed using a material having electron transport properties. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring may be used as the material having electron transport properties. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring may be used.

[0225] The organic compound having an unshared electron pair preferably has a lowest unoccupied molecular orbital (LUMO) of -3.6 eV to -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0226] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used as the organic compound having an unshared electron pair. Note that NBPhen has a higher glass transition point (Tg) and is superior in heat resistance compared to BPhen.

[0227] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0228] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0229] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0230] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0231] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material can be used.

[0232] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth, allowing for efficient emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting device.

[0233] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0234] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0235] Embodiment 3 In this embodiment, structural examples of electronic devices to which a display device of one embodiment of the present invention is applied will be described.

[0236] The display device and the display module of one embodiment of the present invention can be applied to a display portion of an electronic device having a display function, etc. Examples of such electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound players.

[0237] In particular, the display device and the display module according to one embodiment of the present invention can have high resolution and can therefore be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), VR devices such as head-mounted displays, and head-mountable wearable devices such as glasses-type AR devices.

[0238] 18A shows a perspective view of an eyeglass-type electronic device 800. The electronic device 800 has a pair of display panels 801, a pair of housings 802, a pair of optical members 803, a pair of mounting portions 804, and the like.

[0239] The electronic device 800 can project an image displayed on the display panel 801 onto a display area 806 of the optical member 803. Furthermore, since the optical member 803 is translucent, the user can see the image displayed in the display area 806 superimposed on a transmitted image visually recognized through the optical member 803. Therefore, the electronic device 800 is an electronic device capable of AR display.

[0240] One of the housings 802 is provided with a camera 805 that can capture an image of the front. Although not shown, one of the housings 802 is provided with a connector to which a wireless receiver or a cable can be connected, and a video signal or the like can be supplied to the housing 802. By providing an acceleration sensor such as a gyro sensor in the housing 802, the orientation of the user's head can be detected and an image corresponding to that orientation can be displayed in the display area 806. The housing 802 is preferably provided with a battery, which can be charged wirelessly or via a wired connection.

[0241] 18B , a method for projecting an image onto display area 806 of electronic device 800 will be described. Display panel 801, lens 811, and reflector 812 are provided inside housing 802. In addition, a portion of optical member 803 corresponding to display area 806 has reflecting surface 813 that functions as a half mirror.

[0242] Light 815 emitted from the display panel 801 passes through the lens 811 and is reflected by the reflector 812 toward the optical member 803. Inside the optical member 803, the light 815 is repeatedly totally reflected at the end surface of the optical member 803 and reaches the reflecting surface 813, whereby an image is projected onto the reflecting surface 813. This allows the user to view both the light 815 reflected by the reflecting surface 813 and the transmitted light 816 that has passed through the optical member 803 (including the reflecting surface 813).

[0243] 18 shows an example in which the reflector 812 and the reflecting surface 813 each have a curved surface. This allows for greater freedom in optical design and allows for a thinner optical member 803 than when these surfaces are flat. Note that the reflector 812 and the reflecting surface 813 may also be flat.

[0244] A member having a mirror surface, preferably one with high reflectivity, can be used as the reflector 812. Furthermore, a half mirror utilizing reflection from a metal film may be used as the reflecting surface 813, but the transmittance of the transmitted light 816 can be increased by using a prism or the like utilizing total reflection.

[0245] Here, the housing 802 preferably has a mechanism for adjusting the distance between the lens 811 and the display panel 801 or the angle therebetween. This makes it possible to adjust the focus, enlarge or reduce the size of an image, etc. For example, one or both of the lens 811 and the display panel 801 may be configured to be movable in the optical axis direction.

[0246] Furthermore, the housing 802 preferably has a mechanism that can adjust the angle of the reflector 812. By changing the angle of the reflector 812, it is possible to change the position of the display area 806 where an image is displayed. This makes it possible to position the display area 806 at an optimal position according to the position of the user's eyes.

[0247] The display device or the display module of one embodiment of the present invention can be applied to the display panel 801. Therefore, the electronic device 800 can provide an extremely high-definition display.

[0248] 19A and 19B show perspective views of a goggle-type electronic device 850. Fig. 19A is a perspective view showing the front, top, and left side of electronic device 850, and Fig. 19B is a perspective view showing the back, bottom, and right side of electronic device 850.

[0249] The electronic device 850 includes a pair of display panels 851, a housing 852, a pair of mounting portions 854, a buffer member 855, and a pair of lenses 856. The pair of display panels 851 are provided inside the housing 852 at positions that can be seen through the lenses 856.

[0250] The electronic device 850 is an electronic device for VR. A user wearing the electronic device 850 can view an image displayed on a display panel 851 through a lens 856. Also, by displaying different images on the pair of display panels 851, a three-dimensional display using parallax can be performed.

[0251] An input terminal 857 and an output terminal 858 are provided on the rear side of the housing 852. A cable for supplying a video signal from a video output device or the like, or for supplying power for charging a battery provided in the housing 852, can be connected to the input terminal 857. The output terminal 858 functions as, for example, an audio output terminal, and earphones, headphones, or the like can be connected. Note that if the device is configured to be capable of outputting audio data via wireless communication or if audio is output from an external video output device, the audio output terminal does not need to be provided.

[0252] The housing 852 preferably has a mechanism for adjusting the left-right positions of the lens 856 and the display panel 851 so that they are optimally positioned according to the position of the user's eyes. Also, the housing 852 preferably has a mechanism for adjusting the focus by changing the distance between the lens 856 and the display panel 851.

[0253] The display device or the display module of one embodiment of the present invention can be applied to the display panel 851. Therefore, the electronic device 850 can display images with extremely high definition. This allows a user to feel a high sense of immersion.

[0254] The buffer member 855 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The close contact of the buffer member 855 with the user's face prevents light leakage and enhances the sense of immersion. The buffer member 855 is preferably made of a soft material so that it can be in close contact with the user's face when the user wears the electronic device 850. Materials such as rubber, silicone rubber, urethane, and sponge can be used. Furthermore, using a sponge or the like with its surface covered with cloth, leather (natural leather or synthetic leather), or the like can reduce the likelihood of gaps between the user's face and the buffer member 855, thereby effectively preventing light leakage. Furthermore, using such materials is preferable because they are pleasant to the touch and do not cause the user to feel cold when worn in cold seasons. It is preferable that components that come into contact with the user's skin, such as the buffer member 855 or the attachment portion 854, be removable for easy cleaning or replacement.

[0255] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0256] In this example, a display device according to one embodiment of the present invention was manufactured. The pixel circuit shown in FIG. 3C in Embodiment 1 was used for the pixel of the manufactured display device. Transistors M1 to M4 each include a transistor having a channel formed therein, the transistor M1, the transistor M3, and the transistor M4. The transistor M1, the transistor M3, and the transistor M4 each have a channel length of 200 nm and a channel width of 60 nm. Eight of these transistors were connected in series to form the transistor M2. The cross-sectional structure of the manufactured display device can be seen in FIG. 14.

[0257] First, the electrical characteristics of a transistor applied to a display device are described. The transistor has a trench-gate-self-aligned (TGSA) structure manufactured using an LSI process node, and is formed so that a channel of an oxide semiconductor (OS) is covered from above and below by a top gate electrode and a back gate electrode. A CAAC-OS film was used as the oxide semiconductor. The measured transistor has a channel length of approximately 200 nm and a channel width of approximately 60 nm. Here, the measurement was performed on eight such transistors connected in series, similar to the transistor used for transistor M2.

[0258] The measured Id-Vg characteristics are shown in Fig. 20A. Two Id-Vg characteristics are shown in Fig. 20A, one for a drain voltage of 0.1 V and the other for a drain voltage of 1.2 V. Despite being a miniaturized transistor, as shown in Fig. 20A, it exhibits normally-off characteristics, and the off-current is below the lower detection limit of the measuring instrument (1 × 10 −１２ A) The following was true.

[0259] Fig. 20B shows the Id-Vd characteristics, which are obtained when the gate voltage is 0.9 V, 1.7 V, 2.5 V, and 3.3 V. As shown in Fig. 20B, the transistor exhibits high saturation characteristics despite being a miniaturized transistor.

[0260] The fabricated display device had a stacked structure of a circuit (SiLSI) made up of Si transistors (SiFETs), a circuit (OSLSI) made up of OS transistors (OSFETs), and an OLED element. The specifications of the fabricated display device are shown in Table 1. Table 1 lists, from top to bottom, the size of the display area, resolution, pixel size, pixel density, aperture ratio, pixel arrangement, colorization method, emission method, frame frequency, source driver, scan driver (gate driver), and stacked structure.

[0261]

[0262] In particular, the colorization method used was a side-by-side method in which light-emitting elements were separately formed for red (R), green (G), and blue (B) by photolithography without using a metal mask. The pixel circuits were formed using OS transistors, and driver circuits such as a source driver and a scan driver were formed using Si transistors.

[0263] A display photograph of the prototype display device is shown in Figure 21. It was confirmed that a good image could be displayed on a display device with an extremely high resolution of 2731 ppi, in which an OS transistor was stacked on a Si transistor and the channel length was reduced to 200 nm.

[0264] Next, the viewing angle dependence of the chromaticity of each of the R, G, and B components of the fabricated display device was measured. Figures 22A and 22B show the results of the measurement of the viewing angle dependence. Schematic diagrams of the measurement directions are also shown in Figures 22A and 22B. Figure 22A shows the results for the horizontal viewing angle, and Figure 22B shows the results for the vertical viewing angle. In each figure, the horizontal axis represents the angle (horizontal viewing angle or vertical viewing angle) when the normal direction to the display surface is set to 0 degrees, and the vertical axis represents the rate of change in chromaticity (Δu'v') when 0 degrees represents 0.

[0265] As shown in FIGS. 22A and 22B, it was confirmed that Δu′v′ took small values ​​of 0.03 or less within the viewing angle range of ±60 degrees in both the horizontal and vertical directions.

[0266] Next, a block diagram of the driver circuit section of the fabricated display device is shown in Figure 23. Here, eight source drivers (2 x 4) with 360 channel output terminals are arranged below the display area. Each of the eight circuits is connected to a controller (CNTR) via a bus wiring (BUS). In addition, the driver circuit section includes a scan driver, a 1-input 2-output DeMUX circuit, input / output (IO), an LVDS circuit, a debug circuit (Pixel debug), and so on.

[0267] The manufactured display device can be duty driven as shown in Embodiment Mode 1, FIGS. 3 and 4. FIG. 24 shows the measurement results of the change in luminance when the manufactured display device is driven with the duty ratio changed. In FIG. 24, the horizontal axis represents the duty ratio (Duty [%]) and the vertical axis represents the luminance (Luminance [cd / m ２ ]). In the figure, the dashed line represents the ideal value, and the plot represents the measured value. As shown in FIG. 24, it was confirmed that the luminance changes linearly with respect to the duty ratio, and is almost consistent with the ideal value. Furthermore, when the duty ratio is set to 100%, the luminance is 5000 cd / m ２ It was confirmed that the above brightness was achieved.

[0268] A display device according to one embodiment of the present invention not only allows various functional circuits other than a driver circuit to be arranged under a display area, but also enables higher functionality, a narrower frame, a smaller chip size, and a reduced number of external terminals compared to conventional display devices.

[0269] 10: transistor, 10a-h: transistor, 11: dummy transistor, 12B: light-emitting element, 12G: light-emitting element, 12R: light-emitting element, 20: pixel, 20B: sub-pixel, 20G: sub-pixel, 20R: sub-pixel, 20X: sub-pixel, 21: conductive layer, 22: conductive layer, 23: conductive layer, 24: pixel electrode, 29: dummy layer, 30a-d: transistor, 31: semiconductor layer, 31a: semiconductor layer, 31b: semiconductor layer, 31i: region, 31n: region, 32: dummy layer, 41: contact portion, 42: contact portion, 51: insulating layer, 52: insulating layer

Claims

1. a first wiring, a second wiring, a first transistor, and a plurality of second transistors; the first wiring extends in a first direction and receives a gate signal; the second wiring extends in a second direction intersecting the first direction, and a source signal is applied to the second wiring; the first transistor has a gate electrically connected to the first wiring, one of a source and a drain electrically connected to the second wiring, and the other of the source and the drain electrically connected to each gate of the plurality of second transistors; the plurality of second transistors are configured by connecting q units (q is an integer of 2 or more) in parallel, each unit having p transistors (p is an integer of 2 or more) connected in series; the first transistor has a first semiconductor layer through which a current flows in the first direction or the second direction; The display device, wherein each of the second transistors has a second semiconductor layer through which a current flows in the first direction or the second direction.

2. a first wiring, a second wiring, a first transistor, and a plurality of second transistors; the first wiring extends in a first direction and receives a gate signal; the second wiring extends in a second direction intersecting the first direction, and a source signal is applied to the second wiring; the first transistor has a gate electrically connected to the first wiring, one of a source and a drain electrically connected to the second wiring, and the other of the source and the drain electrically connected to a first gate of each of the plurality of second transistors; the plurality of second transistors are configured by connecting q units (q is an integer of 2 or more) in parallel, each unit having p transistors (p is an integer of 2 or more) connected in series; a second gate of each of the plurality of second transistors is electrically connected to a first gate of the second transistor; the first transistor has a first semiconductor layer through which a current flows in the first direction or the second direction; The display device, wherein each of the second transistors has a second semiconductor layer through which a current flows in the first direction or the second direction.

3. In claim 1 or 2, A light-emitting element is provided. The light-emitting element has an anode and a cathode, A display device, wherein one of the second transistors has one of a source and a drain electrically connected to the anode or the cathode.

4. In claim 1 or 2, A display device, wherein the second transistors each have a substantially equal channel length and a substantially equal channel width.

5. In claim 1 or 2, The first transistor and the second transistors have substantially equal channel lengths and substantially equal channel widths.

6. In claim 1 or 2, A display device, wherein two adjacent second transistors among the plurality of second transistors each have a channel formation region in one island-shaped second semiconductor layer.

7. In claim 1 or 2, each of the second transistors has the second semiconductor layer; A display device, wherein the second semiconductor layers are arranged at equal intervals in the first direction or the second direction.

8. In claim 1 or 2, The second semiconductor layer comprises a metal oxide containing one or both of indium and zinc.

9. In claim 8, The first semiconductor layer contains the same metal oxide as the second semiconductor layer.

10. In claim 1 or 2, a third transistor; the third transistor has a third semiconductor layer; the third semiconductor layer includes the same semiconductor material as the first semiconductor layer and has a portion having a top surface shape substantially the same as that of the first semiconductor layer; At least one of a gate, a source, and a drain of the third transistor is electrically floating.