Semiconductor device and method for semiconductor device fabrication

Abstract

The present invention has a first memory cell, a second memory cell on the first memory cell, a first conductor, and a second conductor on the first conductor, the first memory cell and the second memory cell each having a transistor, a capacitive element, and a first insulator on the transistor, the transistor having a metal oxide, a third conductor, fourth conductor, and second insulator on the metal oxide, a fifth conductor on the second insulator, a third insulator under the metal oxide, and a sixth conductor under the third insulator, the capacitive element having a seventh conductor, a fourth insulator on the seventh conductor, and an eighth conductor on the fourth insulator, the fourth conductor and the seventh conductor being in contact via an opening provided in the first insulator, the first conductor and the second conductor each having a portion in contact with the third conductor, one side end part of the third conductor substantially coinciding with one side end part of the metal oxide, and one side end part of the fourth conductor substantially coinciding with the other side end part of the metal oxide.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), graphic processing units (GPU), and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. In addition, memories of various storage types have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage types include dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as the amount of data handled increases, semiconductor devices with larger storage capacities are required. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors.

[0006] International Publication No. 2021 / 053473

[0007] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0008] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with large on-state current.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.An object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0009] An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.An object of one embodiment of the present invention is to provide a storage device with a small occupation area.An object of one embodiment of the present invention is to provide a storage device with high reliability.An object of one embodiment of the present invention is to provide a storage device with low power consumption.An object of one embodiment of the present invention is to provide a novel storage device.An object of one embodiment of the present invention is to provide a method for manufacturing a storage device with high productivity.An object of one embodiment of the present invention is to provide a method for manufacturing a novel storage device.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One aspect of the present invention provides a memory cell including a first memory cell, a second memory cell on the first memory cell, a first conductor, and a second conductor on the first conductor, wherein the first memory cell and the second memory cell each include a transistor, a capacitor, and a first insulator on the transistor, wherein the transistor includes a metal oxide, a third conductor, a fourth conductor, and a second insulator on the metal oxide, a fifth conductor on the second insulator, a third insulator under the metal oxide, and a sixth conductor under the third insulator, and the capacitor includes a seventh conductor, a fourth insulator on the seventh conductor, and an eighth conductor on the fourth insulator, wherein the seventh conductor, the fourth insulator, and the eighth conductor are disposed on the first insulator. and a part of an eighth conductor are located, the fourth conductor and the seventh conductor are in contact with each other through an opening provided in the first insulator, the first conductor has a portion in contact with the third conductor of the first memory cell, the top surface of the first conductor has a portion in contact with the bottom surface of the second conductor, the second conductor has a portion in contact with the third conductor of the second memory cell, the sixth conductor of the second memory cell is made of the same material as the eighth conductor of the first memory cell, and in a cross-sectional view of the transistor, one side edge of the third conductor roughly coincides with one side edge of the metal oxide, and one side edge of the fourth conductor roughly coincides with the other side edge of the metal oxide.

[0012] In the above, it is preferable that the first conductor contacts a part of the top surface and one of the side edges of the third conductor of the first memory cell.

[0013] In the above, it is preferable that the side edge of the third insulator substantially coincides with the side edge of the metal oxide.

[0014] In the above, it is preferable that the third conductor and the fourth conductor each have a first layer and a second layer on the first layer, the first layer having a metal nitride, and the second layer having a higher conductivity than the first layer.In the above, it is preferable that the first layer has tantalum nitride, and the second layer has tungsten.

[0015] Furthermore, in the above, it is preferable that there is a fifth insulator in contact with the upper surface of the third conductor, and a sixth insulator in contact with the upper surface of the fourth conductor, and that the side end of the sixth insulator roughly coincides with the side end of the fourth conductor.

[0016] Furthermore, in the above, it is preferable that the semiconductor device has a seventh insulator covering the third conductor, the fourth conductor, the metal oxide, and the third insulator, and that the seventh insulator has a first opening overlapping the region sandwiched between the third conductor and the fourth conductor and a second opening overlapping the opening of the first insulator, and that at least a portion of the second insulator and the fifth conductor are arranged in the first opening of the seventh insulator, and that at least a portion of the seventh conductor, the fourth insulator, and the eighth conductor are arranged in the second opening of the seventh insulator.

[0017] In the above, it is preferable that an eighth insulator is provided on the first insulator, a part of the fourth insulator is in contact with an upper surface of the eighth insulator, and the eighth insulator has an opening overlapping the opening of the first insulator. In the above, it is preferable that a film thickness of the eighth insulator is 50 nm or more and 250 nm or less. In the above, it is preferable that the first insulator contains aluminum oxide.

[0018] Furthermore, in the above, it is preferable that the second memory cell has a ninth insulator in contact with the lower surface of the sixth conductor, the ninth insulator of the second memory cell is in contact with the upper surface of the eighth insulator of the first memory cell, and the ninth insulator of the second memory cell has the same material as the fourth insulator of the first memory cell.

[0019] In the above, it is preferable that a side end of the seventh conductor is covered with a fourth insulator, and that the fourth insulator has one or both of zirconium oxide and aluminum oxide.

[0020] In the above, the sixth conductor preferably overlaps with the fifth conductor with a metal oxide interposed therebetween.

[0021] In the above, it is preferable that a tenth insulator be provided in contact with a side surface of the first conductor, and at least a portion of the third conductor be exposed from the tenth insulator and in contact with the first conductor. In the above, it is preferable that the tenth insulator include one or both of aluminum oxide and silicon nitride.

[0022] Another embodiment of the present invention includes forming a first insulator, a second insulator, a metal oxide, a second conductor, and a third insulator in this order over a first conductor; processing the second insulator, the metal oxide, the second conductor, and the third insulator to form an island-shaped second insulator, an island-shaped metal oxide, an island-shaped second conductor, and an island-shaped third insulator; forming a fourth insulator to cover the first insulator, the island-shaped second insulator, the island-shaped metal oxide, the island-shaped second conductor, and the island-shaped third insulator; forming a first opening in the fourth insulator; dividing the island-shaped third insulator so as to overlap the first opening to form a fifth insulator and a sixth insulator; and dividing the island-shaped second conductor to form the third conductor and the fourth conductor. a sixth conductor is formed in the second opening; a ninth insulator and a seventh conductor are formed to cover the sixth conductor; and the ninth insulator and the seventh conductor are formed by processing the ninth insulator and the seventh conductor to form a tenth insulator and an eleventh insulator, an eighth conductor on the tenth insulator, and a ninth conductor on the eleventh insulator, the eighth conductor overlapping with the tenth insulator and the sixth conductor, and the ninth conductor overlapping with a metal oxide and the fifth conductor.

[0023] In the above-mentioned method for manufacturing a semiconductor device, it is preferable that before forming the second opening, a third opening is formed through the eighth insulator, the fourth insulator, the sixth insulator, and the first insulator, and a tenth conductor is formed in the third opening, and the tenth conductor is in contact with a portion of the fourth conductor.

[0024] Furthermore, in the above-described method for manufacturing a semiconductor device, it is preferable that, before processing the second insulator, the metal oxide, the second conductor, and the third insulator, a metal film is formed on the third insulator, an organic coating film is formed on the metal film, and a capacitively coupled plasma etching apparatus is used to process the second insulator, the metal oxide, the second conductor, and the third insulator.

[0025] In the method for fabricating a semiconductor device, it is preferable that, when processing the second conductor, the power of the lower electrode of the chamber of the capacitively coupled plasma etching apparatus is set to 10 W or less. In the method for fabricating a semiconductor device, it is preferable that, when processing the second conductor, the island-shaped second conductor is formed before the organic coating film disappears.

[0026] In the above-described method for manufacturing a semiconductor device, the first conductor preferably overlaps with the metal oxide and the fifth conductor.

[0027] In the above-described method for manufacturing a semiconductor device, the first insulator preferably contains hafnium oxide.

[0028] In the above-described method for manufacturing a semiconductor device, the second insulator preferably contains silicon oxide.

[0029] In the above-described method for manufacturing a semiconductor device, the metal oxide preferably contains indium, gallium, and zinc.

[0030] In the above-described method for manufacturing a semiconductor device, the second conductor preferably has a stacked structure of a layer containing tantalum nitride and a layer containing tungsten over the layer containing tantalum nitride.

[0031] In the above-described method for manufacturing a semiconductor device, the eighth insulator preferably has a thickness of 50 nm to 250 nm.

[0032] In the above-described method for manufacturing a semiconductor device, the tenth insulator preferably has the same material as the eleventh insulator, and the eighth conductor preferably has the same material as the ninth conductor.

[0033] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0034] According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a small occupation area can be provided. According to one embodiment of the present invention, a storage device with high reliability can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel storage device can be provided. According to one embodiment of the present invention, a method for manufacturing a storage device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel storage device can be provided.

[0035] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0036] FIG. 1 is a cross-sectional view showing an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIG. 5 is a cross-sectional view showing an example of a semiconductor device. FIGS. 6A and 6B are top views showing an example of a semiconductor device. FIGS. 7A to 7C are diagrams showing an example of a method for manufacturing a semiconductor device. FIGS. 8A to 8F are diagrams showing an example of a method for manufacturing a semiconductor device. FIGS. 9A to 9C are diagrams showing an example of a method for manufacturing a semiconductor device. FIGS. 10A to 10C are diagrams showing an example of a method for manufacturing a semiconductor device. FIGS. 11A to 11C are diagrams showing an example of a method for manufacturing a semiconductor device. FIGS. 12A to 12C are diagrams showing an example of a method for manufacturing a semiconductor device. FIGS. 13A and 13B are diagrams showing an example of a method for manufacturing a semiconductor device. FIG. 14 is a diagram showing an example of a method for manufacturing a semiconductor device. FIG. 15 is a block diagram showing an example of a memory device. FIGS. 16A and 16B are a schematic diagram and a circuit diagram showing an example of a memory device. FIGS. 17A and 17B are schematic diagrams showing an example of a memory device. FIG. 18 is a circuit diagram showing an example of a memory device. FIG. 19 is a timing chart showing an example of the operation of a memory device. FIGS. 20A and 20B are circuit diagrams showing an example of a memory device. FIGS. 21A and 21B are circuit diagrams showing an example of a memory device. FIGS. 22A and 22B are diagrams showing an example of a semiconductor device. FIGS. 23A and 23B are diagrams showing an example of an electronic component. FIGS. 24A to 24J are diagrams showing an example of an electronic device. FIGS. 25A to 25E are diagrams showing an example of an electronic device. FIGS. 26A to 26C are diagrams showing an example of an electronic device. FIG. 27 is a diagram showing an example of space equipment. FIGS. 28A and 28B are graphs according to this example. FIGS. 29A and 29B are cross-sectional SEM images according to this example. FIGS. 30A and 30B are cross-sectional SEM images according to this example.

[0037] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0038] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0039] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0040] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0041] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0042] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0043] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is approximately perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0044] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0045] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0046] One aspect of the present invention provides a memory cell including a first memory cell, a second memory cell on the first memory cell, a first conductor, and a second conductor on the first conductor, wherein the first memory cell and the second memory cell each include a transistor, a capacitor, and a first insulator on the transistor, wherein the transistor includes a metal oxide, a third conductor, a fourth conductor, and a second insulator on the metal oxide, a fifth conductor on the second insulator, a third insulator under the metal oxide, and a sixth conductor under the third insulator, and the capacitor includes a seventh conductor, a fourth insulator on the seventh conductor, and an eighth conductor on the fourth insulator, wherein the seventh conductor, the fourth insulator, and the eighth conductor are disposed on the first insulator. and a part of an eighth conductor are located, the fourth conductor and the seventh conductor are in contact with each other through an opening provided in the first insulator, the first conductor has a portion in contact with the third conductor of the first memory cell, the top surface of the first conductor has a portion in contact with the bottom surface of the second conductor, the second conductor has a portion in contact with the third conductor of the second memory cell, the sixth conductor of the second memory cell is made of the same material as the eighth conductor of the first memory cell, and in a cross-sectional view of the transistor, one side edge of the third conductor roughly coincides with one side edge of the metal oxide, and one side edge of the fourth conductor roughly coincides with the other side edge of the metal oxide.

[0047] A semiconductor device according to one embodiment of the present invention includes a transistor having a metal oxide in a channel formation region (OS transistor). Because the off-state current of an OS transistor is low, stored data can be retained for a long time when used in a storage device. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, reading and writing data from and to the storage device can be performed at high speed.

[0048] Furthermore, the first conductor and the second conductor included in the semiconductor device of one embodiment of the present invention can each function as part of a write and read bit line (also simply referred to as a bit line) in the memory device. That is, in a memory device to which one embodiment of the present invention is applied, a structure in which the third conductor is directly in contact with the bit line can be applied. With such a structure, there is no need to provide a separate electrode for connection between the third conductor and the bit line, and the degree of integration of memory cells can be increased.

[0049] In a semiconductor device according to one embodiment of the present invention, a plurality of memory cells are stacked, and a bit line has a stacked structure of a plurality of conductors. The first conductor has a portion in contact with the third conductor included in the first memory cell, and the second conductor has a portion in contact with the third conductor included in the second memory cell. The top surface of the first conductor has a portion in contact with the bottom surface of the second conductor. By using a stacked structure of a plurality of conductors as a conductor functioning as a bit line, the manufacturing yield of the semiconductor device according to one embodiment of the present invention can be increased compared to the case where a single conductor is used for the bit line.

[0050] In addition, in the manufacturing method of a semiconductor device of one embodiment of the present invention, the sixth conductor of the second memory cell and the eighth conductor of the first memory cell can be formed in the same layer and in the same process. In this case, the sixth conductor of the second memory cell has the same material as the eighth conductor of the first memory cell. With this structure, the manufacturing method of a semiconductor device of one embodiment of the present invention can improve productivity compared to a case in which the sixth conductor of the second memory cell and the eighth conductor of the first memory cell are formed in different processes.

[0051] Furthermore, in a method for manufacturing a semiconductor device according to one embodiment of the present invention, an island-shaped metal oxide and a conductor on the island-shaped metal oxide (which will become a third conductor and a fourth conductor in a later step) can be processed into an island shape in the same step. Through these steps, one side edge of the third conductor roughly coincides with one side edge of the metal oxide, and one side edge of the fourth conductor roughly coincides with the other side edge of the metal oxide. This structure enables the method for manufacturing a semiconductor device according to one embodiment of the present invention to achieve higher productivity than when the island-shaped metal oxide and the conductor on the island-shaped metal oxide are formed in separate steps.

[0052] <Cross-sectional Structure Example 1 of Semiconductor Device> Cross-sectional structure examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0053] 1 to 4, the X direction is parallel to the channel length direction of the transistor shown, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0054] 1 includes an insulator 210, a conductor 209 embedded in the insulator 210, an insulator 212 on the insulator 210, an insulator 214 on the insulator 212, m (m is an integer of 1 or more) layers (a first layer 11_1 to an m-th layer 11_m) on the insulator 214, m conductors 240 (conductors 240_1 to conductor 240_m) extending in the Z direction so as to penetrate the m layers and electrically connected to the conductor 209, an insulator 286 on the m-th layer 11_m, and an insulator 287 on the insulator 286. Note that each of the components included in the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0055] Note that the conductor 240 preferably includes a conductor 240a and a conductor 240b. As shown in FIG. 1 , for example, the conductor 240_1 includes a conductor 240a1 and a conductor 240b1, and the conductor 240_m includes a conductor 240am and a conductor 240bm. Hereinafter, the conductors 240a1 to 240am may be collectively referred to as the conductor 240a. The conductors 240b1 to 240bm may be collectively referred to as the conductor 240b.

[0056] The conductor 209 functions as a part, wiring, electrode, or terminal of a circuit element such as a switch, a transistor, a capacitor, an inductor, a resistor, or a diode.

[0057] 1 shows, of the m layers, a first layer 11_1 which is the bottom layer, a second layer 11_2 on the first layer 11_1, a third layer 11_3 on the second layer 11_2, and an m-th layer 11_m which is the top layer. Also, of the m conductors 240, FIG. 1 shows a conductor 240_1 which is the bottom layer, a conductor 240_2 on the conductor 240_1, a conductor 240_3 on the conductor 240_2, and a conductor 240_m which is the top layer.

[0058] In this embodiment, an example having m layers and m conductors 240 is shown, but the present invention is not limited to this. For example, the number of conductors 240 can be 2 or more and m or less. This can increase the yield of semiconductor devices compared to when there is one conductor 240 (when there is one conductor 240a and one conductor 240b).

[0059] The semiconductor device of this embodiment can be used as a memory cell (or memory array) of a memory device. Each of the m layers corresponds to the memory array 20[i] in the memory device described in embodiment 2. A plurality of memory cells are provided in each of the m layers. The conductor 209 is electrically connected to a drive circuit for driving the memory cell, which is provided below the conductor 209. By increasing the number of stacked layers in the memory array (by increasing the value of m), the memory capacity of the memory device can be increased without increasing the area occupied by the memory cells. Therefore, the area occupied per bit is reduced, and a small memory device with a large memory capacity can be realized.

[0060] Of the m layers, the second layer and the subsequent layers have the same configuration, and therefore, in this embodiment, the second layer 11_2 will be mainly described as an example. Regarding the first layer 11_1, the description of the same parts as the second layer 11_2 will be omitted, and the description will focus on the parts that are different from the second layer 11_2.

[0061] The first layer 11_1 includes transistors 202a and 202b and capacitors 101a and 101b.

[0062] The second layer 11_2 includes transistors 201a and 201b and capacitors 101a and 101b. Each of the third layer 11_3 to the m-th layer 11 — m also includes transistors 201a and 201b and capacitors 101a and 101b.

[0063] 1, the first layer 11_1 and the second layer 11_2 are symmetrical between the right and left sides of the conductor 240. That is, in FIG. 1, the transistors 201a and 201b are symmetrical, the transistors 202a and 202b are symmetrical, and the capacitors 101a and 101b are symmetrical. In this embodiment, the left-side structures of the first layer 11_1 and the second layer 11_2 (the transistors 201a and 202a, and the capacitor 101a) will be mainly described as an example.

[0064] The transistor 202a included in the first layer 11_1 is provided over the insulator 214. A conductor 205 (conductors 205a and 205b) is provided as a lower gate electrode of the transistor 202a. One electrode (lower electrode) of the capacitor 101a is physically and electrically connected to one of the source and drain of the transistor 202a.

[0065] One electrode (bottom electrode) of the capacitor 101a included in the second layer 11_2 is physically and electrically connected to one of the source and drain of the transistor 201a included in the second layer 11_2. A conductor 261 (conductor 261a and conductor 261b) is provided as a lower gate electrode of the transistor 201a. In the second layer 11_2, the conductor 261 included in the transistor 201a is formed in the same layer as the other electrode (top electrode) of the capacitor 101a included in the first layer 11_1. The conductor 261 of the transistor 201a included in the second layer 11_2 and the other electrode of the capacitor 101a included in the first layer 11_1 can be formed in the same process.

[0066] Similarly, the upper electrode of the capacitor 101a included in the second layer 11_2 is formed in the same layer as the conductor 261 of the transistor 201a included in the third layer 11_3.

[0067] In this way, in the first layer 11_1, the upper electrode of the capacitor element is not formed in the same layer as the conductor 205, but in the layers above the second layer 11_2, the conductor 261 is formed in the same layer as the upper electrode of the capacitor element 101a in the layer immediately below. In this respect, the first layer 11_1 and the layers above the second layer 11_2 are different from each other.

[0068] The other of the source and the drain of the transistor 202a included in the first layer 11_1 is connected to a conductor 240_1, and the other of the source and the drain of the transistor 201a included in the second layer 11_2 is connected to a conductor 240_2.

[0069] Here, when an opening for providing the conductor 240 is provided in the stacked structure of the insulator after stacking m layers of memory cells, the opening needs to be deep, which may increase the difficulty of processing or reduce the manufacturing yield. Specifically, it may be difficult to maintain the width of the opening (which may also be referred to as the opening diameter; in FIG. 1 etc., this corresponds to the length in the X-axis direction) constant. For example, the width of the upper side of the opening (the mth layer side) tends to be wide, while the width of the lower side of the opening (the first layer side) tends to be narrow.

[0070] Therefore, in the method for manufacturing the semiconductor device of this embodiment, after forming the transistors 202a and 202b included in the first layer 11_1, an opening for providing the conductor 240_1 is provided in the stacked layer structure of insulators, and the conductor 240_1 is embedded in the opening. Furthermore, after forming the conductor 240_1, the capacitors 101a and 101b are formed. Then, the transistors 201a and 201b included in the second layer 11_2 are formed, and an opening for providing the conductor 240_2 is provided in the stacked layer structure of insulators, and the conductor 240_2 is embedded in the opening. Furthermore, after forming the conductor 240_2, the capacitors 101a and 101b are formed. By repeating these steps, m layers and m conductors can be electrically connected. By using multiple conductors, the depth of each opening can be made shallow, which facilitates processing and increases the manufacturing yield.

[0071] 2A shows an enlarged view of the second layer 11_2 and the left half of its vicinity in FIG. 1 (the conductor 240_2 and the configuration shown to the left of it). Also, FIG. 2B shows a modified example of FIG. 2A. Also, FIG. 3A shows an enlarged cross-sectional view of the transistor 201a in the channel length direction, and FIG. 3B shows an enlarged cross-sectional view of the transistor 201a in the channel width direction. Also, FIGS. 4A and 4B show enlarged views of a region where the conductor 240_2 and the other of the source and drain of the transistor 201a contact each other and its vicinity in the configuration shown in FIG. 1. FIG. 4A is an enlarged cross-sectional view of the transistor 201a in the channel length direction, and FIG. 4B is an enlarged cross-sectional view of the transistor 201a in the channel width direction.

[0072] As shown in FIG. 2A, the second layer 11_2 includes a transistor 201a and a capacitor 101a.

[0073] The transistor 201a includes a conductor 261 (conductor 261a and conductor 261b) embedded in the insulator 284, an insulator 222 on the conductor 261, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

[0074] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are embedded inside openings provided in the insulator 280 and the insulator 275. An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282, and an insulator 285 is provided on the insulator 283. An insulator 284 is provided on the insulator 285.

[0075] The oxide 230 has a region that functions as a channel formation region of the transistor 201a.

[0076] The conductor 242a has a region which functions as one of the source electrode and the drain electrode of the transistor 201a. The conductor 242b has a region which functions as the other of the source electrode and the drain electrode of the transistor 201a.

[0077] As shown in FIG. 2A , in a cross-sectional view of the transistor 201a, it is preferable that one side edge of the conductor 242a roughly coincides with one side edge of the oxide 230, and one side edge of the conductor 242b roughly coincides with the other side edge of the oxide 230. Furthermore, it is preferable that the side edge of the insulator 224 roughly coincides with the side edge of the oxide 230. In one embodiment of the present invention, the insulator 224, the oxide 230, and the conductors that will become the conductors 242a and 242b in a later process can be processed into island shapes all at once. This allows the semiconductor device according to one embodiment of the present invention to be manufactured with good productivity. When processed as described above, the side edges of the insulator 224, the oxide 230, the conductor 242a, and the conductor 242b are shaped so that they roughly coincide with each other, as described above.

[0078] Furthermore, the insulators 271a and 271b are films that protect the conductors 242a and 242b during the island-shaped processing. For example, the insulators 271a and 271b function as etching stoppers when removing a hard mask during processing of the conductors 242a and 242b. Therefore, as shown in FIG. 2A , in a cross-sectional view of the transistor 201a, it is preferable that the side end of the insulator 271a on the insulator 250 side roughly coincides with the side end of the conductor 242a on the insulator 250 side, and both side ends of the insulator 271b roughly coincide with the side ends of the conductor 242b.

[0079] In addition, when the side edges are aligned or approximately aligned in a cross-sectional view, and when the top surface shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a top view. For example, this includes a case where the lower portion of the side edge of the upper layer contacts the upper portion of the side edge of the lower layer. It also includes a case where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and a portion of the upper layer may be located inside the lower layer, or a portion of the upper layer may be located outside the lower layer. In this case, too, it is said that the side edges are approximately aligned or the top surface shapes are approximately aligned.

[0080] The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 201a. The insulator 250 has a region that functions as a first gate insulator of the transistor 201a. The conductor 261 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 201a. The insulator 224 and the insulator 222 each have a region that functions as a second gate insulator of the transistor 201a.

[0081] The capacitor 101a includes a conductor 153 over the conductor 242b, an insulator 154 over the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) over the insulator 154.

[0082] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the openings formed in the insulators 271b, 275, 280, 282, 283, and 285. The ends of the conductors 153, 154, and 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is disposed so as to cover the end of the conductor 153. This allows the conductors 153 and 160 to be electrically insulated from each other.

[0083] The capacitance of the capacitor 101a can be increased by increasing the depth of the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 (i.e., increasing the thickness of one or more of the insulators 271b, 275, 280, 282, 283, and 285). Increasing the capacitance per unit area of ​​the capacitor 101a allows for miniaturization or high integration of semiconductor devices.

[0084] The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitor 101a. The insulator 154 has a region that functions as a dielectric of the capacitor 101a. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitor 101a. The capacitor 101a constitutes a metal-insulator-metal (MIM) capacitor.

[0085] Here, the conductor 160 that functions as the upper electrode of the capacitor 101a in the lower layer (e.g., the first layer 11_1) and the conductor 261 that functions as the second gate electrode of the transistor 201a in the upper layer (e.g., the second layer 11_2) are formed in the same layer. In other words, the conductor 160 of the capacitor 101a in the lower layer and the conductor 261 of the transistor 201a in the upper layer are formed so as to be embedded in openings formed in the same insulator 284. The conductor 160 of the capacitor 101a in the lower layer and the conductor 261 of the transistor 201a in the upper layer are formed by processing one conductive film, thereby achieving the above-described structure. In this case, the conductor 160 of the capacitor 101a in the lower layer has the same material as the conductor 261 of the transistor 201a in the upper layer.

[0086] Furthermore, an insulator 263 is preferably provided in contact with the underside of the conductor 261. In the above process, the insulator 263 is formed simultaneously with the insulator 154, which functions as a dielectric film of the lower capacitor 101a, when the conductor 160 of the lower capacitor 101a and the conductor 261 of the upper transistor 201a are formed. That is, the insulator 154 of the capacitor 101a in the lower layer (e.g., the first layer 11_1) and the insulator 263 of the transistor 201a in the upper layer (e.g., the second layer 11_2) are formed in the same layer. In other words, the insulator 154 of the lower capacitor 101a and the insulator 263 of the upper transistor 201a are formed so as to be embedded in openings formed in the same insulator 284. Here, the insulator 154 of the lower capacitor 101a has the same material as the insulator 263 of the upper transistor 201a.

[0087] As described above, by simultaneously forming the conductor 160 and the insulator 154 of the capacitor 101a in the lower layer and the conductor 261 and the insulator 263 of the transistor 201a in the upper layer, the manufacturing process of the semiconductor device according to this embodiment can be reduced, and the productivity of the semiconductor device can be improved.

[0088] 2A illustrates a configuration in which the upper electrode (conductor 160) of the capacitor 101a in the lower layer (e.g., the first layer 11_1) and the second gate electrode (conductor 261) of the transistor 201a in the upper layer (e.g., the second layer 11_2) are separately provided, but the present invention is not limited to this. As illustrated in FIG. 2B , the conductor 160 may serve as both the upper electrode of the capacitor 101a in the lower layer (e.g., the first layer 11_1) and the second gate electrode of the transistor 201a in the upper layer (e.g., the second layer 11_2).

[0089] The conductor 242b provided over and overlapping the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 101a.

[0090] In addition, the conductor 242a provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 240. For example, in FIG. 2A , the top surface and side end portions of the conductor 242a are electrically connected to the conductor 240_2 extending in the Z direction.

[0091] By directly contacting the conductor 240_2 with at least one of the top surface and side end of the conductor 242a, there is no need to provide a separate electrode for connection, which reduces the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, allowing for increased storage capacity. It is preferable that the conductor 240_2 contact a portion of the top surface and side end of the conductor 242a. By contacting multiple surfaces of the conductor 242a with the conductor 240_2, the contact resistance between the conductor 240_2 and the conductor 242a can be reduced.

[0092] 4A , the conductor 240_2 has a region having a width W1 and a region having a width W2. The width W1 corresponds to the distance of the opening between the conductor 242a of the transistor 201a and the conductor 242a of the transistor 201b. The width W2 corresponds to the diameter of the opening provided in the insulator 285 at the top surface, and corresponds to, for example, the distance between the interface between the insulator 285 and the conductor 240a2 on the transistor 201a side and the interface between the insulator 285 and the conductor 240a2 on the transistor 201b side.

[0093] As shown in FIG. 4A, the width W2 is preferably larger than the width W1. In this configuration, the conductor 240_2 contacts at least a portion of the top surface and a portion of the side edge of the conductor 242a. Therefore, the area of ​​the region where the conductor 240_2 and the conductor 242a contact can be increased. Note that in this specification and the like, the contact between the conductor 240_2 and the conductor 242a shown in FIG. 4A and the like may be referred to as a top-side contact.

[0094] With the conductor 242a of the transistor 201a and the conductor 242b of the transistor 201b each formed into an island shape, openings can be formed in the insulators 285 to 284. In this case, as shown in FIG. 4B , the conductor 242a may not overlap the opening in the cross section of the opening taken along the YZ plane.

[0095] Furthermore, an insulator 241 is preferably provided in contact with a side surface of the conductor 240 (for example, the conductor 240_2 in FIGS. 4A and 4B ). As shown in FIGS. 4A and 4B , the insulator 241 is preferably provided between the conductor 240_2 and the insulators 284, 222, 224, the oxide 230, 271a, 275, 280, 282, 283, and 285. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240_2. With this structure, the insulator 241 can prevent impurities such as hydrogen and oxygen contained in the conductor 240_2 from diffusing to the oxide 230. This can improve the electrical characteristics and reliability of the transistor 201a.

[0096] Next, a transistor included in the semiconductor device of this embodiment mode will be described in detail.

[0097] Note that, although the following description will be mainly given taking the components of the transistor 201a as an example, the same can also be applied to the components of the transistor 202a.

[0098] The oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By including the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0099] In this embodiment, the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b, but is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b, or a stacked structure of three or more layers.

[0100] 3A, the oxide 230b includes a region 230bc in the transistor 201a, and regions 230ba and 230bb sandwiching the region 230bc. The region 230bc functions as a channel formation region. The region 230ba functions as one of a source region and a drain region, and the region 230bb functions as the other of the source region and the drain region. At least a portion of the region 230bc overlaps with the conductor 260. The region 230ba overlaps with the conductor 242a, and the region 230bb overlaps with the conductor 242b.

[0101] The region 230bc has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a lower carrier concentration. Therefore, the region 230bc can be said to be i-type (intrinsic) or substantially i-type.

[0102] Furthermore, the regions 230ba and 230bb are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the regions 230ba and 230bb are n-type regions (low-resistance regions) with higher carrier concentrations than the region 230bc.

[0103] The carrier concentration of the region 230bc is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration of the region 230bc is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0104] Note that when the carrier concentration of the oxide 230b is reduced, the impurity concentration in the oxide 230b is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0105] In order to stabilize the electrical characteristics of the transistor 201a, it is effective to reduce the impurity concentration in the oxide 230b. Furthermore, in order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0106] In addition, the regions 230bc, 230ba, and 230bb may each be formed with not only the oxide 230b but also the oxide 230a.

[0107] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the region 230bc.

[0108] The oxide 230 (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0109] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of a transistor.

[0110] The oxide 230 is preferably a metal oxide such as indium oxide, gallium oxide, or zinc oxide. The oxide 230 is preferably a metal oxide containing two or three elements selected from indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. The element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. A metal oxide containing indium, element M, and zinc may be referred to as an In-M-Zn oxide.

[0111] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0112] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 201a can have large on-state current and high frequency characteristics.

[0113] Furthermore, since the oxide 230 a and the oxide 230 b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230 a and the oxide 230 b can be reduced, which reduces the effect of interface scattering on carrier conduction, and the transistor 201 a can have a large on-state current and high frequency characteristics.

[0114] Specifically, the oxide 230a can be a metal oxide having an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b can be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, when a single layer of oxide 230b is provided as oxide 230, the metal oxide that can be used for oxide 230a may be used for oxide 230b. Furthermore, the compositions of metal oxides that can be used for oxide 230a and oxide 230b are not limited to those described above. For example, the composition of a metal oxide that can be used for oxide 230a may be used for oxide 230b. Similarly, the composition of a metal oxide that can be used for oxide 230b may be used for oxide 230a.

[0115] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0116] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0117] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0118] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0119] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed, and thus even when heat treatment is performed, extraction of oxygen from the oxide 230b can be suppressed, so that the transistor 201a is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0120] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region 230bc in the oxide semiconductor where a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region 230bc in the oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, the region 230bc in the oxide semiconductor has a reduced carrier concentration and is preferably i-type (intrinsic) or substantially i-type.

[0121] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the region 230ba or the region 230bb, the on-state current or the field-effect mobility of the transistor 201a may decrease. Furthermore, if the amount of oxygen supplied to the region 230ba or the region 230bb varies within the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, and the conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0122] Therefore, in the oxide semiconductor, the region 230bc preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb preferably have a high carrier concentration and are n-type. Ｏ It is preferable to reduce H. It is also preferable to prevent an excessive amount of oxygen from being supplied to the regions 230ba and 230bb, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0123] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in region 230bc, suppress oxidation of conductor 242a, conductor 242b, and conductor 260, and suppress the reduction in the hydrogen concentration in regions 230ba and 230bb.

[0124] The insulator 250 in contact with the region 230bc of the oxide 230b preferably has the function of capturing and fixing hydrogen. This reduces the hydrogen concentration in the region 230bc of the oxide 230b. Therefore, the V Ｏ H can be reduced to make the region 230bc i-type or substantially i-type.

[0125] 3A, the insulator 250 preferably has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In this case, it is preferable that the insulator 250a has the function of capturing and fixing hydrogen.

[0126] Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides with an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 250a. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0127] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulator 250a makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0128] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250a, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use hafnium oxide having an amorphous structure. In this embodiment, hafnium oxide is used as the insulator 250a. In this case, the insulator 250a becomes an insulator containing at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 250a has an amorphous structure.

[0129] Next, it is preferable to use an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride, for the insulator 250b. The insulator 250b may also have a layered structure. In this case, the insulator 250b may have a layered structure in which an insulator that can be used for the insulator 250a is provided on silicon oxide or silicon oxynitride. For example, the insulator 250 may have a layered structure including silicon oxide or silicon oxynitride and hafnium oxide on the silicon oxide or silicon oxynitride.

[0130] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0131] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250c, and the insulator 275.

[0132] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0133] Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, and 275 each preferably have a single-layer structure or a stacked-layer structure of the above oxygen barrier insulators.

[0134] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a having a barrier property against oxygen can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or field-effect mobility of the transistor 201a.

[0135] Furthermore, the insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. Because the insulator 250a has barrier properties against oxygen, it can suppress oxygen from being desorbed from the region 230bc of the oxide 230b when heat treatment or the like is performed. Therefore, it is possible to reduce the formation of oxygen vacancies in the oxide 230a and the oxide 230b.

[0136] Conversely, even if the insulator 280 contains an excessive amount of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 230a and the oxide 230b. Therefore, excessive oxidation of the regions 230ba and 230bb can be prevented, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 201a.

[0137] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 250a.

[0138] The insulator 250c preferably has a barrier property against oxygen. The insulator 250c is provided between the region 230bc of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This configuration can prevent oxygen contained in the region 230bc of the oxide 230 from diffusing into the conductor 260 and forming oxygen vacancies in the region 230bc of the oxide 230. Furthermore, it can prevent oxygen contained in the oxide 230 and oxygen contained in the insulator 280 from diffusing into the conductor 260 and oxidizing the conductor 260. The insulator 250c is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 250c. In this case, the insulator 250c becomes an insulator containing at least nitrogen and silicon.

[0139] The insulator 250c preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0140] The insulator 275 preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This configuration can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to prevent the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, thereby increasing their resistivity and reducing their on-state current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0141] To prevent a decrease in the hydrogen concentration in the regions 230ba and 230bb in the oxide 230, it is preferable to provide a barrier insulator against hydrogen near each of the regions 230ba and 230bb. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, an insulator 275.

[0142] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0143] The insulator 275 preferably has a barrier property against hydrogen. When the insulator 275 has a barrier property against hydrogen, the insulator 250 can be prevented from capturing and fixing hydrogen in the regions 230ba and 230bb. Therefore, the regions 230ba and 230bb can be made n-type.

[0144] With the above configuration, the region 230bc can be made i-type or substantially i-type, and the regions 230ba and 230bb can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above configuration, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 201a can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0145] The insulators 250a to 250c function as part of the first gate insulator. The insulators 250a to 250c, together with the conductor 260, are provided in openings formed in the insulator 280 or the like. To miniaturize the transistor 201a, the insulators 250a to 250c preferably have a small thickness. The thicknesses of the insulators 250a to 250c are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that the insulators 250a to 250c may each have a region with the above thickness at least in part.

[0146] To thin the thicknesses of the insulators 250a to 250c as described above, it is preferable to form the insulators by atomic layer deposition (ALD). ALD methods include thermal ALD, which uses only thermal energy to react a precursor and a reactant, and plasma-enhanced ALD, which uses plasma-excited reactants. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0147] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280, etc., and on the side ends of the conductors 242a and 242b, etc., with a thin film thickness as described above.

[0148] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0149] Although the above description has been given of a structure in which the insulator 250 has a three-layer structure of insulators 250a to 250c, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250c. By configuring the insulator 250 as one or two layers of the insulators 250a to 250c, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0150] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that suppresses hydrogen from being mixed into the transistors 201a, 202a, etc. For example, an insulator having a function of suppressing hydrogen diffusion is preferably provided so as to cover one or both of the top and bottom of the transistors 201a, 202a, etc. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 286, etc.

[0151] It is preferable that one or more of the insulators 212, 214, 282, 283, 286, and 287 function as barrier insulators that suppress diffusion of impurities such as water and hydrogen from the substrate side or from above the transistors 201a, 202a, etc. to the transistors 201a, 202a, etc. Therefore, one or more of the insulators 212, 214, 282, and 286 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0152] The insulators 212, 214, 282, 283, 286, and 287 each preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulators 212, 283, and 287. Furthermore, for example, the insulators 214, 282, and 286 each preferably have aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistors 201a, 202a, etc. through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 283 or the insulator 287 to the transistors 201a, 202a, etc. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc. toward the substrate side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistors 201a, 202a, etc. via the insulator 282, etc. In this way, it is preferable to have a structure in which the transistors 201a, 202a, etc. are surrounded from above and below by insulators that have a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0153] In the transistors 201a and 201b, the conductor 261 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 261 is preferably provided by being embedded in an opening formed in the insulator 284. Furthermore, as shown in FIG. 3B , the conductor 261 is preferably provided to extend in the channel width direction (the Y direction shown in FIG. 3B ). With this structure, the conductor 261 functions as a wiring and as a second gate electrode in multiple transistors arranged in the Y direction.

[0154] The conductor 261 may have a single-layer structure or a laminated structure. In FIG. 1 and other figures, the conductor 261 includes a conductor 261a and a conductor 261b. The conductor 261a is provided in contact with the bottom surface and sidewall of the opening. The conductor 261b is provided in contact with the top surface of the conductor 261a and in contact with the sidewall of the opening. Here, the height of the top surface of the conductor 261b is approximately the same as the height of the top surface of the insulator 284.

[0155] Here, the conductor 261a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0156] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 261a, it is possible to prevent impurities such as hydrogen contained in the conductor 261b from diffusing into the oxide 230 via the insulator 284 or the like. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 261a, it is possible to suppress oxidation of the conductor 261b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 261a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 261a preferably contains titanium nitride.

[0157] The conductor 261b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 261b preferably contains tungsten.

[0158] The conductor 261 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 201a can be controlled by changing the potential applied to the conductor 261 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 261 can increase the Vth of the transistor 201a and reduce its off-state current. Therefore, applying a negative potential to the conductor 261 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0159] Furthermore, the electrical resistivity of the conductor 261 is designed taking into consideration the potential applied to the conductor 261, and the film thickness of the conductor 261 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 284 is approximately the same as that of the conductor 261. Here, it is preferable to make the film thicknesses of the conductor 261 and the insulator 284 thin within the range permitted by the design of the conductor 261. By making the film thickness of the insulator 284 thin, the absolute amount of impurities such as hydrogen contained in the insulator 264 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0160] As described above, the conductor 261 is formed in the same layer as the conductor 160, so the conductor 261a can have the same configuration as the conductor 160a, and the conductor 261b can have the same configuration as the conductor 160b. In this case, an insulator 263 having the same configuration as the insulator 154 is provided in contact with the lower surface of the conductor 261.

[0161] Note that in the transistors 202a and 202b, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Part of the conductor 205 may be embedded in the insulator 214. The conductor 205 includes a conductor 205a and a conductor 205b over the conductor 205a. The conductor 205 may have a structure similar to that of the conductor 261, the conductor 205a may have a structure similar to that of the conductor 261a, and the conductor 205b may have a structure similar to that of the conductor 261b.

[0162] However, since it is not necessary to provide the upper electrode of the capacitor in the same layer as the conductor 205, unlike the conductor 261, it is not necessary to provide the conductor 205 with an insulator similar to the insulator 154. Therefore, the lower surface of the conductor 205 is in contact with the insulator 214. The conductor 205 can also be formed by depositing a conductive film so as to fill the opening provided in the insulator 216 and then removing the upper part of the conductive film. In this case, the conductor 205a is provided in contact with the lower surface and side surface of the conductor 205b.

[0163] Insulator 222 and insulator 224 function as a second gate insulator.

[0164] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0165] The insulator 222 preferably includes an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistors 201a and 202a to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistors 201a and 202a and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 or the conductor 160 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230.

[0166] Alternatively, the insulator may be doped with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

[0167] The insulator 222 may have a single-layer structure or a multilayer structure of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the second gate insulator. By using a high-k material for the insulator that functions as the second gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may also be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0168] The insulator 224 in contact with the oxide 230 preferably comprises, for example, silicon oxide or silicon oxynitride.

[0169] Each of the insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials.

[0170] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0171] The conductors 242a and 242b may have a single-layer structure or a multi-layer structure, and the conductor 260 may have a single-layer structure or a multi-layer structure.

[0172] In FIG. 2A, the conductors 242a and 242b are shown as a two-layer structure. The conductor 242a is a laminated film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the layers in contact with the oxide 230b (the conductors 242a1 and 242b1). This can prevent the conductivity of the conductors 242a and 242b from decreasing. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide 230b (the conductors 242a1 and 242b1), as this can reduce the hydrogen concentration in the oxide 230.

[0173] For the conductors 242a1 and 242b1, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may also be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0174] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, by using a nitride containing tantalum for the conductors 242a1 and 242b1, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0175] Furthermore, it is preferable that the conductors 242a2 and 242b2 have higher conductivity than the conductors 242a1 and 242b1. For example, it is preferable that the film thickness of the conductors 242a2 and 242b2 be greater than the film thickness of the conductors 242a1 and 242b1. Conductors that can be used for the conductor 261b may be used for the conductors 242a2 and 242b2. By using the above structure, it is possible to reduce the contact resistance between the conductor 242a2 and the conductor 240 and the contact resistance between the conductor 242b2 and the conductor 153. This makes it possible to improve the operating speed of the semiconductor device according to this embodiment.

[0176] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0177] To prevent the conductivity of the conductors 242a and 242b from decreasing, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. This can also prevent the conductivity of the conductors 242a and 242b from decreasing.

[0178] The insulators 271a and 271b are inorganic insulators that function as etching stoppers when the conductors 242a and 242b are processed. The insulator 271a contacts the upper surface of the conductor 242a and the lower surface of the insulator 275, and the insulator 271b contacts the upper surface of the conductor 242b and the lower surface of the insulator 275. The insulators 271a and 271b can be one or more of the insulators that can be used for the insulators 250a to 250c. For example, the insulators 271a and 271b can be stacked films of a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0179] 3A and 3B , the conductor 260 is disposed within an opening formed in the insulator 280, the insulator 275, the insulators forming the insulators 271a and 271b, the conductors forming the conductors 242a and 242b, the oxide 230, and the insulator 224. The conductor 260 is disposed within the opening so as to cover the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. The conductor 260 is also disposed so that its top surface is approximately flush with the height of the top of the insulator 250 and the top surface of the insulator 280.

[0180] In the openings provided in the insulator 280 or the like in which the conductor 260 and the insulator 250 are disposed, the side walls of the openings may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By making the side walls tapered, the coverage of the insulator 250 or the like provided in the openings of the insulator 280 can be improved, and defects such as voids can be reduced.

[0181] The conductor 260 functions as a first gate electrode of the transistor 201a. Here, as shown in FIG. 3B, the conductor 260 is preferably provided so as to extend in the channel width direction (the Y direction shown in FIG. 3B). With this configuration, the conductor 261 functions as a wiring and functions as a first gate electrode in a plurality of transistors arranged in the Y direction.

[0182] 3B , in a cross-sectional view of the transistor 201a in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as a rounded shape).

[0183] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. By using such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0184] In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin structure. In this specification, a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0185] By forming the transistor 201a in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 201a in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0186] 3B illustrates an example of a transistor having an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0187] 2, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0188] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0189] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0190] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0191] In the transistor 201a, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0192] The insulators 216, 280, 285, and 284 preferably have a dielectric constant lower than that of the insulator 214. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0193] For example, it is preferable that insulators 216, 280, 285, and 284 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0194] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0195] Furthermore, the top surfaces of the insulators 216, 280, 285, and 284 may each be flattened.

[0196] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0197] The conductor 153 and the conductor 160 included in the capacitor 101a can be formed using any of the conductors that can be used for the conductor 205, the conductor 242, or the conductor 260. The conductor 153 and the conductor 160 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductor 153 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0198] The upper surface of the conductor 242b2 is in contact with the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b2, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0199] For example, the conductor 160a can be made of titanium nitride formed by ALD or CVD, and the conductor 160b can be made of tungsten formed by CVD. Note that if the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten formed by CVD.

[0200] A high-k material (a material with a high relative dielectric constant) is preferably used for the insulator 154 of the capacitor 101a. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0201] Examples of high-dielectric-constant (high-k) insulators include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0202] For example, examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-k materials, the insulator 154 can be made thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor element 101a.

[0203] Furthermore, it is preferable to use a laminated structure of insulators made of the above materials, and it is preferable to use a laminated structure of a high-dielectric constant (high-k) material and a material having a higher dielectric strength than the high-dielectric constant (high-k) material. For example, the insulator 154 can be an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, it can be an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. Alternatively, it can be an insulator laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By using a laminated structure of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 101a can be suppressed.

[0204] The deeper the openings in the insulators 271b, 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 101a can be. Here, since the insulators 271b, 275, 282, and 283 function as barrier insulators, it is preferable to set their thicknesses according to the barrier properties required for the semiconductor device. Furthermore, since the thickness of the insulator 280 determines the thickness of the conductor 260 that functions as a gate electrode, it is preferable to set the thickness of the insulator 280 according to the thickness of the conductor 260 required for the semiconductor device.

[0205] Therefore, it is preferable to set the capacitance of the capacitor 101a by adjusting the thickness of the insulator 285. For example, the thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm. Forming the capacitor 101a in such a range allows the capacitor 101a to have sufficient capacitance and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that a configuration may be adopted in which the capacitance of the capacitor provided in each memory cell is different in each of the multiple memory cell layers. In such a configuration, for example, the thickness of the insulator 285 provided in each memory cell layer may be different.

[0206] In the opening provided in the insulator 285 or the like in which the capacitor 101a is disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.

[0207] The conductor 240 is provided in openings formed in the insulators 284, 222, 275, 280, 282, 283, and 285. Note that in the opening where the conductor 240_1 is formed, openings are also formed in the insulators 212, 214, and 216. The conductor 240 is in contact with the top surface and side end portions of the conductor 242a and the top surface of the underlying conductor 240. The conductor 240_1 is in contact with the top surface of the conductor 209.

[0208] The conductor 240 functions as a plug or wiring for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wiring, electrodes, or terminals to the transistors 201a and 202a.

[0209] For example, in the memory device described in Embodiment 2, the conductor 240 functions as a write and read bit line.

[0210] The conductor 240 preferably has a layered structure of the conductor 240a and the conductor 240b. For example, as shown in Figures 4A and 4B, the conductor 240_2 can have a structure in which the conductor 240a2 is provided in contact with the inner wall of the opening, and the conductor 240b2 is provided further inside. In other words, the conductor 240a2 is arranged closer to the insulators 222, 275, 280, 282, 283, 285, and 284 than the conductor 240b2. The conductor 240a2 also contacts the top surface and side end of the conductor 242a.

[0211] The conductor 240a is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. The conductor 240a can have a single-layer structure or a multi-layer structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. This can suppress impurities such as water and hydrogen from entering the oxide 230 through the conductor 240.

[0212] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0213] For example, it is preferable to use titanium nitride as the conductor 240a and tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0214] The conductor 240 may have a single layer structure or a laminated structure of three or more layers.

[0215] As shown in FIG. 2A , the insulator 241 is preferably provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 284, 222, 275, 280, 282, 283, 285, 216, 214, and 212. The insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a, which are formed to protrude into the openings. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the interior of the opening via the insulator 241.

[0216] 4A, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has an area that contacts the side surface of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240.

[0217] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. This structure can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from mixing into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0218] 2A shows the insulator 241 as a single layer, the present invention is not limited to this. The insulator 241 may have a stacked structure of two or more layers.

[0219] For example, in FIGS. 4A and 4B, the insulator 241 is shown as having a two-layer structure of an insulator 241a and an insulator 241b on the insulator 241a.

[0220] 4A and 4B , when the insulator 241 has a two-layer stacked structure, it is preferable that the insulator 241a in contact with the inner wall of the opening of the insulator 280, etc., and the insulator 241b inside it are made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen. For example, the insulator 241a may be made of aluminum oxide formed by the ALD method, and the insulator 241b may be made of silicon nitride formed by the PEALD method. This configuration suppresses oxidation of the conductor 240 and further reduces the intrusion of hydrogen from the conductor 240 into the oxide 230, etc.

[0221] In the opening where the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, coverage of the insulator 241 and the like provided in the opening is improved.

[0222] <Cross-Sectional Structure Example 2 of Semiconductor Device> A cross-sectional structure example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0223] 5, a layer including transistors 202c to 202e and the like (corresponding to the functional layer 50 described in Embodiment 2) is provided over a layer including transistors 310 and the like (corresponding to the driver circuit 21 described in Embodiment 2), and a stacked layer structure similar to the stacked layer structure shown in FIG. 1 (corresponding to the plurality of memory cells 10 included in the memory array 20 described in Embodiment 2) is provided thereover. The structure of the layers above the insulator 210 in FIG. 5 is similar to that in FIG. 1, and therefore detailed description thereof will be omitted.

[0224] 5 illustrates a transistor 310 included in the driver circuit 21 described in Embodiment 2. The transistor 310 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 310 may be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0225] Here, in the transistor 310 shown in FIG. 5 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0226] Note that the transistor 310 illustrated in FIG. 5 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or the driving method.

[0227] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0228] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0229] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0230] 5 illustrates transistors 202c, 202d, and 202e included in the functional layer 50 described in Embodiment 2. The transistors 202c, 202d, and 202e have the same configuration as the transistors 202a and 202b included in the memory cell 10. The transistors 202c, 202d, and 202e correspond to the transistors 52, 53, and 55 shown in FIG. 20A and the like. The transistors 202c, 202d, and 202e have their sources and drains connected in series, similar to the transistors 52, 53, and 55.

[0231] An insulator 208 is provided over the transistors 202c, 202d, and 202e, and a conductor 207 is provided in an opening formed in the insulator 208. The insulator 208 can be an insulator similar to the insulator 210, and the conductor 207 can be a conductor similar to the conductor 209.

[0232] The bottom surface of the conductor 207 is in contact with the top surface of the conductor 260 of the transistor 202d. The top surface of the conductor 207 is in contact with the bottom surface of the conductor 209. With this structure, the conductor 240, which corresponds to the wiring BL that functions as a bit line, can be electrically connected to the gate of the transistor 202c, which corresponds to the transistor 52.

[0233] <Top Structure Example of Semiconductor Device> A top structure example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 6A and 6B. FIG.

[0234] 6A and 6B, the X direction is parallel to the channel length direction of the transistor shown in the figure, the Y direction is parallel to the channel width direction of the transistor shown in the figure, and the Z direction is perpendicular to the X direction and the Y direction. For simplification, some components, such as insulators, are not shown in Figures 6A and 6B. Also, the frame surrounded by the two-dot chain line shown in Figures 6A and 6B represents a memory cell including one transistor and one capacitor.

[0235] 6A and 6B show layouts applicable to the second layer 11_2 and the subsequent layers, and illustrate transistors 201a and 201b, capacitors 101a and 101b, and the like. For example, when Figure 6A is a top surface layout of the second layer 11_2, Figure 6A illustrates the conductor 160 of the second layer 11_2 (i.e., the upper electrodes of the capacitors 101a and 101b in the second layer 11_2) and the conductor 261 of the third layer 11_3 (i.e., the back gate electrodes of the transistors 201a and 201b in the third layer 11_3), and Figure 6B illustrates the conductor 160 of the first layer 11_1 (i.e., the back gate electrodes of the transistors 201a and 201b in the second layer 11_2) and the conductor 261 of the second layer 11_2 (i.e., the back gate electrodes of the transistors 201a and 201b in the second layer 11_2).

[0236] 6A and 6B, the conductor 160, the conductor 260, and the conductor 261 are provided extending in the Y direction. The conductor 160, the conductor 260, and the conductor 261 are shared with memory cells adjacent in the Y direction, and each function as wiring.

[0237] 6A and 6B, the conductor 240 and the conductor 153 are depicted as being circular in top view, but this is not limiting. For example, the conductor 240 may be substantially circular, such as an ellipse, polygonal, such as a rectangle, or polygonal, such as a rectangle, with rounded corners, in top view.

[0238] 6A and 6B show a configuration in which two adjacent memory cells are provided with independent conductors 160 without an intervening conductor 240, but the present invention is not limited to this. For example, two adjacent memory cells may be configured to share one conductor 160 without an intervening conductor 240.

[0239] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0240] <<Substrate>> Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulator region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0241] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0242] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0243] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0244] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0245] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0246] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0247] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0248] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0249] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0250] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0251] <<Metal Oxide>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 of one embodiment of the present invention are described below.

[0252] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0253] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, the element M may be a combination of two or more of the above-mentioned elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0254] In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (In—Ga—Zn oxide, also referred to as IGZO) is preferably used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used for the semiconductor layer. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (In—Ga—Zn—Sn oxide, also referred to as IGZTO) may be used for the semiconductor layer.

[0255] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0256] Hereinafter, an In—Ga—Zn oxide will be described as an example of a metal oxide.

[0257] Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0258] Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0259] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0260] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0261] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0262] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0263] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

[0264] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.

[0265] Next, the above-mentioned CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0266] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0267] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0268] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions (first regions) mainly containing In and regions (second regions) mainly containing Ga is randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0269] The CAC-OS can be formed by sputtering without heating the substrate, for example. When forming the CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas can be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0270] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0271] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0272] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0273] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0274] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0275] <<Other Semiconductor Materials>> A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer of a transistor. For example, a semiconductor of a simple element such as silicon or a compound semiconductor such as gallium arsenide may be used.

[0276] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer of the transistor. Specifically, molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-described transition metal chalcogenide to the semiconductor layer of a transistor, a semiconductor device with a large on-state current can be provided.

[0277] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described with reference to Figures 7 to 14. Here, the case of manufacturing the semiconductor device illustrated in Figure 1 will be described as an example.

[0278] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0279] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0280] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0281] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0282] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0283] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0284] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0285] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0286] First, a substrate (not shown) is prepared, and an insulator 210 and a conductor 209 are formed on the substrate. Next, an insulator 212 is formed on the insulator 210 and the conductor 209, and an insulator 214 is formed on the insulator 212 (FIG. 7A).

[0287] The insulators 212 and 214 are preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 212 or the insulator 214 can be reduced. However, the deposition method for the insulators 212 and 214 is not limited to sputtering, and for example, CVD, MBE, PLD, or ALD may also be used.

[0288] The insulators 212 and 214 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus is preferably used. This allows the insulators 212 and 214 to be formed with reduced hydrogen content and also reduces hydrogen contamination between film formation steps.

[0289] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. The use of pulsed DC sputtering can suppress particle generation due to arcing on the target surface, resulting in a more uniform film thickness distribution. Furthermore, the use of pulsed voltage can make the rise and fall of discharge steeper than with high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0290] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used in a conductor (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0291] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power may be, for example, 0 W / cm. ２ More than 1.86 W / cm ２ The following is true. That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0292] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high ability to capture and fix hydrogen, as the insulator 214. This allows hydrogen contained in the insulator 216 or the like to be captured or fixed and prevents the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor and semiconductor device with favorable characteristics.

[0293] Next, a conductive film that becomes the conductor 205a is formed on the insulator 214. The conductive film that becomes the conductor 205a preferably includes a conductor that has a function of suppressing oxygen permeation. The conductive film preferably includes, for example, one or more of tantalum nitride, tungsten nitride, and titanium nitride. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0294] Next, a conductive film to become the conductor 205b is formed on the conductive film to become the conductor 205a. The conductive film to become the conductor 205b preferably contains one or more of, for example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy. The conductive film can be formed by, for example, a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, tungsten is formed as the conductive film to become the conductor 205b.

[0295] Next, a conductive film to be the conductor 205a and a conductive film to be the conductor 205b are processed by lithography to form the conductor 205 (FIG. 7A). Dry etching or wet etching can be used to form the conductor 205. Dry etching is preferable because it is suitable for fine processing.

[0296] Next, an insulating film that will become the insulator 216 is formed to cover the conductor 205. The insulating films that will become the insulators 216 are preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulator 216 can be reduced. However, the method for forming the insulators 216 is not limited to a sputtering method, and for example, a CVD method, an MBE method, a PLD method, or an ALD method may also be used.

[0297] In this embodiment, a silicon oxide film is formed as the insulator 216 by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0298] Next, CMP treatment is performed to remove a part of the insulating film that will become the insulator 216, thereby exposing the conductor 205. As a result, the insulator 216 remains in contact with the side surface of the conductor 205 (FIG. 7A).

[0299] Although the above description describes a method in which the conductor 205 is formed first and then the insulator 216 is formed, the present invention is not limited to this. For example, the insulator 216 having an opening formed therein may be formed first, and then the conductor 205 may be formed so as to be embedded in the opening.

[0300] Next, an insulator 222 is formed on the insulator 216 and the conductor 205 (FIG. 7B).

[0301] The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. As the insulator containing one or both of aluminum and hafnium oxides, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0302] Alternatively, the insulator 222 can be a stacked film of an insulator containing an oxide of one or both of aluminum and hafnium, and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.

[0303] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method. Alternatively, the insulator 222 may be a stack of silicon nitride formed by a PEALD method and hafnium oxide formed by an ALD method.

[0304] Subsequently, heat treatment is preferably performed. The temperature of the heat treatment is preferably 250°C or higher and 650°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0305] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the insulator 222 as much as possible.

[0306] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0307] Next, an insulating film 224f is formed on the insulator 222 (FIG. 7B).

[0308] The insulating film 224f can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is formed as the insulating film 224f by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f will come into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0309] Next, an oxide film 230af is formed on the insulating film 224f, and an oxide film 230bf is formed on the oxide film 230af (FIG. 7B). It is preferable to form the oxide films 230af and 230bf consecutively without exposing them to the atmospheric environment. By forming the films without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230af and 230bf, and to keep the vicinity of the interface between the oxide films 230af and 230bf clean.

[0310] The oxide film 230af and the oxide film 230bf can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the oxide film 230af and the oxide film 230bf are formed by a sputtering method.

[0311] For example, when the oxide film 230af and the oxide film 230bf are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, an In-M-Zn oxide target or the like can be used.

[0312] In particular, during the formation of the oxide film 230af, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f. Therefore, the proportion of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.

[0313] When the oxide film 230bf is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0314] In this embodiment, the oxide film 230af is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4 or an oxide target with an atomic ratio of In:Ga:Zn = 1:3:2. The oxide film 230bf is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. The oxide films 230a and 230b can be formed according to the desired characteristics of the oxides 230a and 230b by appropriately selecting the deposition conditions and atomic ratios.

[0315] Note that the insulating film 224f, the oxide film 230af, and the oxide film 230bf are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus is preferably used. This can reduce the inclusion of hydrogen in the insulating film 224f, the oxide film 230af, and the oxide film 230bf between film formation steps.

[0316] Next, heat treatment is preferably performed within a temperature range in which the oxide film 230af and the oxide film 230bf are not polycrystallized. The temperature of the heat treatment is preferably 100° C. or higher, 250° C. or higher, or 350° C. or higher, and 650° C. or lower, 600° C. or lower, or 550° C. or lower.

[0317] Note that the atmosphere for the heat treatment may be the same as the atmosphere that can be applied to the heat treatment performed after the formation of the insulator 222.

[0318] Furthermore, it is preferable that the gas used in the heat treatment be highly purified, similar to the heat treatment performed after the formation of the insulator 222. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented as much as possible from being absorbed into the oxide film 230af, the oxide film 230bf, and the like.

[0319] In this embodiment, the heat treatment is performed at 400° C. for 1 hour with a nitrogen gas / oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. Reducing the impurities in the film in this manner improves the crystallinity of the oxide film 230bf, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide film 230af and the oxide film 230bf, reducing the in-plane variation of the crystalline regions in the oxide film 230af and the oxide film 230bf. This reduces the in-plane variation of the electrical characteristics of the transistor.

[0320] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decrease.

[0321] In particular, the insulating film 224f (later the insulator 224) functions as a second gate insulator of the transistor 202a, and the oxide film 230af and the oxide film 230bf (later the oxide 230a and the oxide 230b) function as a channel formation region of the transistor 202a. The transistor 202a formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf in which the hydrogen concentrations are reduced has good reliability and is therefore preferable.

[0322] Next, a conductive film 242_1f is formed on the oxide film 230bf, and a conductive film 242_2f is formed on the conductive film 242_1f (FIG. 7B). After the oxide film 230bf is formed, the conductive film 242_1f is formed on and in contact with the oxide film 230bf without an etching step or the like. This makes it possible to protect the top surface of the oxide film 230bf with the conductive film 242_1f. This can reduce diffusion of impurities into the oxide 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0323] The conductive films 242_1f and 242_2f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0324] In this embodiment, tantalum nitride is deposited as the conductive film 242_1f by a sputtering method, and tungsten is deposited as the conductive film 242_2f. Note that heat treatment may be performed before the formation of the conductive film 242_1f. The heat treatment may be performed under reduced pressure, and the conductive film 242_1f may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0325] Next, an insulating film 271f is formed over the conductive film 242_2f (FIG. 7B). The insulating film 271f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271f is preferably an insulating film that has a function of suppressing oxygen permeation. For example, the insulating film 271f may be formed by a sputtering method to form a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0326] Next, using lithography, the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f are processed into island shapes to form the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 (Figure 7C).

[0327] Here, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are preferably processed collectively into an island shape. In this case, the side ends of the conductor 242_1 and the conductor 242_2 preferably roughly coincide with the side ends of the oxide 230a and the oxide 230b. Furthermore, the side ends of the insulator 224 preferably roughly coincide with the side ends of the oxide 230. Furthermore, the side ends of the insulator 271 preferably roughly coincide with the side ends of the conductor 242. With this structure, a semiconductor device according to one embodiment of the present invention can be manufactured with good productivity.

[0328] The insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are formed so as to at least partially overlap with the conductor 205. The insulator 222 is formed so as to at least partially overlap with the conductor 209. The insulator 222 is exposed in a region that does not overlap with the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, or the insulator 271.

[0329] 7C , the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be substantially perpendicular to the top surface of the insulator 222. With such a structure, a smaller area and higher density can be achieved when providing multiple transistors.

[0330] Furthermore, without being limited to the above, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0331] 7C , the conductor 242, the oxide 230, and the insulator 224 are preferably formed into two island shapes. However, this is not limited thereto, and the conductor 242, the oxide 230, and the insulator 224 may be formed into a single island shape having an opening at a position overlapping with the conductor 209.

[0332] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. The insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f may be processed under different conditions.

[0333] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process a conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0334] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the oxide film 230bf, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. Etching of the oxide film 230bf or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the oxide film 230bf or the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0335] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３ Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing no halogen gas but hydrocarbon gas or hydrogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0336] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0337] Specific examples of processing the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f will be described below with reference to FIGS. 8A to 8F.

[0338] First, a hard mask layer 276f is formed on the insulating film 271f (FIG. 8A). The hard mask layer 276f can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The hard mask layer 276f functions as a hard mask for forming the conductor 242 and the oxide 230 in a later process. A metal material, an inorganic insulating material, or the like may be used as the hard mask layer 276f. For example, tungsten formed by sputtering may be used as the hard mask layer 276f. Alternatively, the hard mask layer 276f may be formed successively after the insulating film 271f is formed without exposure to the atmosphere.

[0339] Next, an organic coating film 277f is formed on the hard mask layer 276f, and then an organic coating film 278f is formed ( FIG. 8A ). The organic coating film 277f and the organic coating film 278f may have the function of improving adhesion between the hard mask and the resist mask, which will be described later. The organic coating film 277f and the organic coating film 278f may be formed, for example, using a spin coating method. A non-photosensitive organic resin may be used as the organic coating film 277f and the organic coating film 278f. In this embodiment, an SOC (Spin On Carbon) film is formed as the organic coating film 277f, and an SOG (Spin On Glass) film is formed as the organic coating film 278f. Here, the organic coating film 277f and the organic coating film 278f contain an organic solvent such as alcohol during application, but the contained organic matter may be reduced or removed during subsequent processes or when the semiconductor device is completed. The organic coating film may be provided as needed, and may be configured as a single layer, or may not be provided if only a resist mask, which will be described later, is sufficient.

[0340] Next, a resist mask 279 is formed on the organic coating film 278f using lithography (FIG. 8A). The resist mask 279 may be a photosensitive organic resin also known as photoresist. For example, a positive photoresist or a negative photoresist may be used. The photoresist that will become the resist mask 279 can be formed to a uniform thickness by using, for example, a spin coating method.

[0341] In the following steps according to FIGS. 8B to 8F, a dry etching apparatus is used to etch the stacked film shown in FIG. 8A. The steps according to FIGS. 8B to 8F are preferably performed consecutively without exposure to the outside air. For example, a multi-chamber etching apparatus may be used to perform the process without exposure to the outside air. The dry etching apparatus may be a CCP etching apparatus that applies high-frequency voltages of different frequencies to parallel plate electrodes in the chamber. In this case, a high-frequency voltage may be applied to the upper electrode, and a low-frequency voltage may be applied to the lower electrode on which the substrate is placed.

[0342] First, using a resist mask 279, the organic coating film 278f is processed into an island shape to form the organic coating film 278, and then the organic coating film 277f is processed into an island shape to form the organic coating film 277 (FIG. 8B). For example, when an SOG film is used for the organic coating film 278f, ３ and O ２ For example, when an SOC film is used as the organic coating film 277f, H ２ and N ２ can be used as the etching gas.

[0343] The resist mask 279 may disappear before the organic coating film 277 is formed. If the resist mask 279 remains after the organic coating film 277 is formed, the resist mask 279 may be removed.

[0344] Next, using the organic coating film 277 as a mask, the hard mask layer 276f is processed into an island shape to form the hard mask layer 276, the insulating film 271f is further processed into an island shape to form the insulator 271, and the conductive film 242_2f and the conductive film 242_1f are further processed into an island shape to form the conductor 242_2 and the conductor 242_1 (FIG. 8C). For example, when a tungsten film is used for the hard mask layer 276f, CF ４ and Cl ２ For example, when a laminated film of silicon nitride and silicon oxide is used for the insulating film 271f, CHF ３ and O ２ For example, in the case of a stacked film in which a tungsten film is used as the conductive film 242_2f and a tantalum nitride film is used as the conductive film 242_1f, CHF can be used as an etching gas. ３ and Cl ２ and Ar can be used as etching gases.

[0345] Here, the hard mask layer 276 and the conductive film 242_2f may be made of the same metal material (for example, tungsten). If the organic coating film 277 functioning as a mask disappears during etching of the conductive films 242_2f and 242_1f, the hard mask layer 276 is exposed to the etching. As a result, the conductive films 242_2f and 242_1f may be etched excessively, and the width of the conductor 242 may become narrower than designed.

[0346] Therefore, in the etching process of the conductive films 242_2f and 242_1f, it is preferable to perform the etching under conditions in which the etching rates of the conductive films 242_2f and 242_1f are higher than the etching rate of the organic coating film 277. For example, in the etching process of the conductive films 242_2f and 242_1f, it is preferable to lower the power of the lower electrode on which the substrate is placed. For example, the power of the lower electrode on which the substrate is placed may be lower than the power of the lower electrode when the above-mentioned hard mask layer 276f is etched, and is preferably set to less than 25 W, and more preferably to 10 W or less. By performing etching under such conditions, even a semiconductor device having a fine structure can be processed as designed.

[0347] Next, the oxide film 230bf and the oxide film 230af are processed into an island shape using the hard mask layer 276 to form the oxide film 230b and the oxide film 230a (FIG. 8D). For example, when the oxide film 230bf and the oxide film 230af are made of oxides containing one or more elements selected from In, Ga, and Zn, CH ４ and Ar can be used as etching gases. Oxides containing In, Ga, and Zn can be etched using CH ３ It reacts with radicals to form highly volatile metal complexes. Therefore, even if the substrate temperature is relatively low, ４ By using a gas containing In, Ga, and Zn, it is possible to easily process oxides containing In, Ga, and Zn, which are difficult-to-etch materials.

[0348] If the organic coating film 277 remains after the process shown in FIG. 8D , it may be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0349] Next, the insulating film 224f is processed into an island shape using the hard mask layer 276 to form the insulator 224 (FIG. 8E). For example, when a silicon oxide film is used for the insulating film 224f, the insulating film 224f is formed by etching with CHF ３ and Ar can be used as etching gases.

[0350] Here, it is preferable that the insulator 222 is not over-etched during processing of the insulating film 224f. Therefore, it is preferable to perform etching under conditions that provide a high etching selectivity relative to the insulator 222. For example, when the insulating film 224f contains silicon oxide and is etched with a gas containing fluorine, it is preferable that the insulator 222 contains hafnium oxide. By etching in this manner, insulator 275 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222 in a process described below. In other words, the insulator 224 can be separated from the insulator 280 by the insulator 275. This configuration can prevent excessive amounts of impurities such as oxygen and hydrogen from being mixed into the oxide 230 from the insulator 280 via the insulator 224.

[0351] Finally, the hard mask layer 276 is removed (FIG. 8F). For example, if a tungsten film is used for the hard mask layer 276, CF ４ and Cl ２ and O ２ In addition, if the material of the hard mask layer 276 does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask layer 276.

[0352] Furthermore, in the process of removing the hard mask layer 276, the insulator 271 functions as a mask for the conductor 242_2, so that the conductor 242_2 does not have a curved surface between its side surface and top surface. As a result, the conductors 242a and 242b have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, allowing the on-state current of the transistor to be increased.

[0353] In the above manner, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 can be collectively processed into island shapes. This reduces the number of steps compared to when the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are individually processed into island shapes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0354] Next, an insulator 275 is deposited to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271, and then an insulator 280 is deposited over the insulator 275.

[0355] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0356] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0357] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0358] The insulator 275 is preferably an insulator having a function of suppressing oxygen permeation. For example, the insulator 275 is preferably formed by depositing a silicon nitride film by a PEALD method. Alternatively, the insulator 275 is preferably formed by depositing an aluminum oxide film by a sputtering method and then depositing a silicon nitride film thereon by a PEALD method. By forming the insulator 275 with such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen can be improved.

[0359] In this manner, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275, which has a function of suppressing oxygen diffusion. This reduces direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 in a later process.

[0360] For example, it is preferable to form a silicon oxide film as the insulator 280 by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0361] Next, the conductor 242_1, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 are processed by lithography to form an opening that reaches the oxide 230b (FIG. 9A). The opening that reaches the oxide 230b is provided in a region where the oxide 230b and the conductor 205 overlap.

[0362] The above processing can be performed by a dry etching method or a wet etching method. The conductor 242_1, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 may be processed under different conditions.

[0363] By this processing, the conductor 242_1 is divided into island-shaped conductors 242a1 and 242b1. Similarly, the conductor 242_2 is divided into island-shaped conductors 242a2 and 242b2. Similarly, the insulator 271 is divided into island-shaped insulators 271a and 271b.

[0364] The etching process may result in impurities adhering to or diffusing into the side surfaces of the oxide 230a, the top surface and side surfaces of the oxide 230b, the side surfaces of the conductors 242a and 242b, the side surfaces of the insulators 271a and 271b, the side surfaces of the insulator 275, and the side surfaces of the insulator 280. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulators 280, 275, 271a and 271b, and the conductors 242a and 242b, components contained in the components of the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0365] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the oxide 230b and its vicinity. It is also preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on the surface of the oxide 230b and its vicinity is preferably 5.0 atomic % or less, more preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0366] In addition, in the region where the crystallinity of the oxide 230b is low due to impurities such as aluminum and silicon, the density of the crystal structure is reduced. Ｏ A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the oxide 230b be reduced or removed.

[0367] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom end of the drain. Here, in the transistor, the conductor 242a or the conductor 242b functions as the drain. In other words, it is preferable that the oxide 230b near the bottom end of the conductor 242a or the conductor 242b has the CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor can be further suppressed. Furthermore, the reliability of the transistor can be improved.

[0368] A cleaning process is performed to remove impurities and the like that have adhered to the surface of the oxide 230b during the etching process. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0369] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0370] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0371] In addition, ultrasonic cleaning preferably uses a frequency of 200 kHz or more, and more preferably uses a frequency of 900 kHz or more, since use of such a frequency can reduce damage to the oxide 230b and the like.

[0372] The cleaning process may be repeated multiple times, and different cleaning solutions may be used for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0373] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0374] Heat treatment may be performed after the etching or cleaning. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide 230b. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230a and the oxide 230b, converting the hydrogen into H. ２ As a result, hydrogen remaining in the oxide 230a and the oxide 230b is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0375] When heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide 230b, the sheet resistance may decrease in the region of the oxide 230b that overlaps with the conductor 242a and the region of the oxide 230b that overlaps with the conductor 242b. The carrier concentration may also increase. Therefore, the resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region of the oxide 230b that overlaps with the conductor 242b can be reduced in a self-aligned manner.

[0376] Next, an insulating film and a conductive film are formed and processed to fill the openings, thereby providing an insulator 250, a conductor 260a, and a conductor 260b in positions overlapping with the conductor 205 (FIG. 9B).

[0377] First, an insulating film that will become the insulator 250 is formed. The insulating film can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. The insulating film is preferably formed using ALD. Like the insulator 250 described above, the insulator 250 is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method that alternately introduces a precursor and a reactant (e.g., an oxidizer). The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIG. 9B , the insulator 250 must be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening, allowing the insulator 250 to be formed with good coverage on the opening.

[0378] When the insulating film that becomes the insulator 250 is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) as an oxidizing agent, hydrogen diffusing into the oxide 230b can be reduced.

[0379] The insulator 250 can have a stacked structure as shown in FIGS. 3A and 3B. In this case, aluminum oxide can be deposited by thermal ALD as the insulating film that becomes the insulator 250a, silicon oxide can be deposited by PEALD as the insulating film that becomes the insulator 250b, and silicon nitride can be deposited by PEALD as the insulating film that becomes the insulator 250c. Furthermore, the insulator 250b can have a stacked structure. In that case, silicon oxide can be deposited by PEALD as the insulating film that becomes the insulator 250b, and hafnium oxide can be deposited thereon by thermal ALD.

[0380] Next, it is preferable to perform microwave treatment in an atmosphere containing oxygen. Here, microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. Furthermore, in this specification and the like, microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. However, when the insulator 250 has a layered structure, the microwave treatment does not necessarily need to be performed after forming all of the insulating films that will become the insulator 250. For example, microwave treatment may be performed after forming the insulating films that will become the insulator 250a and the insulating films that will become the insulator 250b, and then the insulating film that will become the insulator 250c may be formed.

[0381] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W or more and 10,000 W or less, and preferably 2000 W or more and 5,000 W or less. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide 230b.

[0382] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0383] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. In this way, by performing microwave treatment in an atmosphere containing oxygen, the carrier concentration in the oxide 230b can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the oxide 230b can be prevented.

[0384] By performing microwave processing in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region of the oxide 230b between the conductors 242a and 242b. Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Ｏ Therefore, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0385] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0386] On the other hand, the oxide 230b has a region that overlaps with either the conductors 242a or 242b. This region can function as a source region or a drain region. Here, the conductors 242a and 242b preferably function as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when performing microwave treatment in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0387] Conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach the regions of oxide 230b that overlap with either of conductors 242a and 242b. This allows microwave processing to prevent V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0388] Furthermore, an insulator 250 having a barrier property against oxygen is provided in contact with the side surfaces of the conductors 242 a and 242 b, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductors 242 a and 242 b by microwave processing.

[0389] Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0390] In this manner, oxygen vacancies and V ＯBy removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low resistance region state) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0391] In microwave treatment, thermal energy may be transferred directly to the oxide 230b due to electromagnetic interaction between the microwaves and molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave treatment in an oxygen-containing atmosphere may produce an effect equivalent to oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 230b, thereby activating and releasing the hydrogen from the oxide 230b.

[0392] Note that the microwave treatment may be performed before the formation of the insulating film that will become the insulator 250, rather than after the formation of the insulating film.

[0393] Furthermore, after the microwave treatment following the formation of the insulating film that becomes the insulator 250, a heat treatment may be performed while maintaining a reduced pressure. By performing such a treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. Some of the hydrogen may be gettered to the conductors 242a and 242b. Alternatively, a step of performing a heat treatment while maintaining a reduced pressure after the microwave treatment may be repeated multiple times. Repeated heat treatments can more efficiently remove hydrogen from the insulating film, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0394] Furthermore, by performing microwave treatment to modify the film quality of the insulating film that becomes insulator 250, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into oxide 230b, oxide 230a, etc. via insulator 250 by a post-process such as film formation of a conductive film that becomes conductor 260 or a post-treatment such as heat treatment.

[0395] Next, a conductive film to become the conductor 260a and a conductive film to become the conductor 260b are formed in this order. The conductive film to become the conductor 260a and the conductive film to become the conductor 260b can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a titanium nitride film to become the conductor 260a is formed using an ALD method, and a tungsten film to become the conductor 260b is formed using a CVD method.

[0396] Next, the insulating film that will become the insulator 250, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulating film that will become the insulator 250, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b that are exposed from the openings are removed. This forms the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) in the openings that overlap with the conductor 205 ( FIG. 9B ).

[0397] As a result, the insulator 250 is provided in contact with the inner wall and side surface of the opening overlapping the oxide 230b. The conductor 260 is arranged to fill the opening with the insulator 250 interposed therebetween. In this manner, the transistors 202a and 202b are formed. As described above, the transistors 202a and 202b can be fabricated in parallel using the same process.

[0398] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulator 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0399] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 ( FIG. 9C ). The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0400] In this embodiment, an aluminum oxide film is formed as the insulator 282 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. In addition, the RF power applied to the substrate is 1.86 W / cm. ２ Preferably, 0 W / cm ２ 0.62W / cm or more ２ The RF power is set to 0 W / cm or less. ２ This is synonymous with not applying RF power to the substrate. The amount of oxygen implanted into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is implanted into the layer below the insulator 282, and the amount of oxygen is more likely to saturate even if the film thickness of the insulator 282 is thin. Also, the greater the RF power, the more oxygen is implanted into the layer below the insulator 282. By reducing the RF power, the amount of oxygen implanted into the insulator 280 can be suppressed. Alternatively, the insulator 282 may be formed in a two-layer laminate structure. In this case, for example, the lower layer of the insulator 282 may be formed by applying 0 W / cm RF power to the substrate. ２ The upper layer of the insulator 282 was formed as follows: the RF power applied to the substrate was 0.62 W / cm ２ The film is formed as follows.

[0401] The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0402] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0403] Next, an insulator 283 is formed over the insulator 282 ( FIG. 9C ). The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0404] Next, an insulator 285 is formed over the insulator 283 ( FIG. 9C ). The insulator 285 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 285 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 285 can be reduced by using a sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas. In this embodiment, silicon oxide is formed as the insulator 285 by a sputtering method.

[0405] Here, it is preferable to set the capacitance of the capacitor 101a by adjusting the thickness of the insulator 285. For example, the thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening for forming the capacitor 101a may be set to approximately 150 nm to 350 nm. Forming the capacitor 101a in such a range allows the capacitor 101a to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked.

[0406] Next, lithography is used to process the insulators 285, 283, 282, 280, 275, 271a, 222, 216, 214, and 212 to form an opening that exposes a portion of the upper surface of the conductor 209 ( FIG. 10A ). The opening is preferably formed so that a portion of the upper surface of the conductor 242a is exposed in top view. The opening may also be circular, approximately circular such as elliptical, polygonal such as rectangular, or polygonal such as rectangular with rounded corners in top view.

[0407] The openings can be formed by dry etching or wet etching. Dry etching is preferable because it is suitable for fine processing. The above-mentioned gases can be used as the etching gas.

[0408] Here, aluminum oxide and hafnium oxide may be more difficult to etch than silicon oxide or silicon oxynitride, and it can be said that aluminum oxide and hafnium oxide are each difficult-to-etch materials.

[0409] When the above-mentioned difficult-to-etch materials are used for the insulators 282, 222, etc., by opening the insulators in advance, the processing step in Fig. 10A can be performed with a high yield and the productivity of the semiconductor device can be improved. On the other hand, when opening the insulators 282, 222 in the processing step in Fig. 10A, the number of masks can be reduced, which is preferable.

[0410] 10A shows an example in which the widths of the openings in the insulators 285, 283, 282, 280, 275, and 271a are roughly the same, but this is not limiting. If the etching rates of one or more of the insulators 285, 283, 282, 280, 275, and 271a are different, even if openings are made all at once, the ends of the insulators 285, 283, 282, 280, 275, and 271a may not be aligned in cross section.

[0411] 10A shows an example in which the end of the conductor 242a roughly coincides with the end of each of the insulators 212, 214, 216, and 222 in the opening, but this is not limiting. Depending on the etching conditions, one or more of the insulators 212, 214, 216, and 222 may be side-etched, resulting in the end being positioned more inward (closer to the transistor) than the end of the conductor 242a.

[0412] For example, it is preferable to form openings by anisotropic etching in the insulators 212, 214, 216, 222, 271a, 275, 280, 282, 283, and 285. It is preferable to use a dry etching method for the anisotropic etching. This makes it possible to form openings having the shape shown in FIG. 1, for example.

[0413] Next, an insulating film 241A is formed ( FIG. 10B ). It is preferable to use an insulating film that has the function of suppressing the diffusion of at least one of oxygen and hydrogen as the insulating film 241A. For example, it is preferable to form a silicon nitride film using the PEALD method. Silicon nitride is preferable because it has high blocking properties against oxygen and hydrogen. The insulating film 241A may have a stacked structure. For example, an aluminum oxide film may be formed as the insulating film 241A using the ALD method, and a silicon nitride film may be formed thereon using the PEALD method. When the insulating film 241A is formed using the ALD method, an aluminum oxide film can be formed at a lower temperature than a silicon nitride film. Therefore, by forming an aluminum oxide film before forming the silicon nitride film, oxidation of the conductors 260, 242, and the like can be suppressed.

[0414] Next, the insulating film 241A is anisotropically etched to form an insulator 241 in contact with the sidewalls of the openings formed in the insulators 285, 283, 282, 280, 275, 271a, 222, 216, 214, and 212 ( FIG. 10C ). At this point, at least a portion of the conductor 242a is exposed from the insulator 241. The anisotropic etching of the insulating film 241A may be performed, for example, by dry etching. By providing the insulator 241 on the sidewalls of the openings, oxygen penetration from the outside can be suppressed, preventing oxidation of the conductor 240 to be formed next. Furthermore, impurities such as water and hydrogen contained in the conductor 240, the insulator 280, etc. can be prevented from diffusing into the oxide 230.

[0415] Next, a conductive film 240a1f and a conductive film 240b1f are formed in this order ( FIG. 11A ). Here, a portion of the conductive film 240a1f is in contact with the conductor 242a through the opening in the insulator 241. The conductive film 240a1f preferably has a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum nitride or titanium nitride can be used as the conductive film 240a1f. Furthermore, for example, tungsten, molybdenum, or copper can be used as the conductive film 240b1f. These conductive films can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0416] Next, CMP treatment is performed to remove part of the conductive film 240a1f and part of the conductive film 240b1f, thereby exposing the top surface of the insulator 285. As a result, these conductive films remain only in the openings, and a conductor 240_1 (conductor 240a1 and conductor 240b1) having a flat top surface can be formed ( FIG. 11B ). Note that the CMP treatment may remove part of the top surface of the insulator 285.

[0417] This allows the formation of a conductor 240 electrically connected to the conductor 209 and the conductor 242a.

[0418] Next, the insulators 285, 283, 282, 280, 275, and 271b are processed using lithography to form openings that reach the conductor 242b (FIG. 11C).

[0419] The width of the opening provided in this step is preferably minute. For example, the width of the opening is preferably 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more. In order to form such minute openings, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam. Furthermore, the openings can be circular, approximately circular such as elliptical, polygonal such as rectangular, or polygonal such as rectangular with rounded corners, when viewed from above.

[0420] Because the openings provided in this step have a large aspect ratio, it is preferable to use anisotropic etching to process a portion of the insulator 285, a portion of the insulator 283, a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 275, and a portion of the insulator 271b. In particular, processing by dry etching is preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions.

[0421] Next, a conductive film 153A to be the conductor 153 is formed so as to cover the opening and the insulator 285 ( FIG. 12A ). The conductive film 153A is preferably formed in contact with the side and bottom surfaces of the opening. For this reason, the conductive film 153A is preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method. For example, it is preferable to form a film of titanium nitride or tantalum nitride using an ALD method or a CVD method.

[0422] Next, a resist mask is provided over the conductive film 153A, and the conductive film 153A is processed by lithography to form the conductor 153 (FIG. 12B). As a result, part of the conductor 153 is formed inside the opening, and the other part is in contact with part of the top surface of the insulator 282.

[0423] The conductive film 153A may also be processed by CMP. In this case, the top of the conductor 153 can be formed to have a shape that is roughly flush with the top surface of the insulator 282.

[0424] Next, an insulating film 154A that will become the insulator 154 is formed on the conductor 153 ( FIG. 12C ). The insulating film 154A is preferably formed in contact with the conductor 153 provided inside the opening. For this reason, the insulating film 154A is preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method. The insulating film 154A is preferably formed using the above-mentioned high-k material.

[0425] Next, a conductive film 160A to become the conductor 160a and a conductive film 160B to become the conductor 160b are formed in this order ( FIG. 12C ). The conductive film 160A is preferably formed in contact with the insulating film 154A provided inside the opening, and the conductive film 160B is preferably formed so as to fill the opening. For this reason, the conductive films 160A and 160B are preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method. For example, it is preferable to form titanium nitride as the conductive film 160A using an ALD method or a CVD method, and tungsten as the conductive film 160B using a CVD method.

[0426] When the conductive film 160B is formed by the CVD method, the average surface roughness of the upper surface of the conductive film 160B may become large as shown in Fig. 12C. In this case, it is preferable to planarize the conductive film 160B by the CMP method as shown in Fig. 13A.

[0427] Next, the insulating film 154A, the conductive film 160A, and the conductive film 160B are processed by lithography to form the insulator 154, the conductor 160a, the conductor 160b, the insulator 263, the conductor 261a, and the conductor 261b ( FIG. 13B ). At this time, it is preferable that the insulator 154, the conductor 160a, and the conductor 160b are formed so as to cover the side end portion of the conductor 153. With this structure, the conductor 160 and the conductor 153 can be separated by the insulator 154, and short-circuiting between the conductor 160 and the conductor 153 can be suppressed.

[0428] As described above, the lower layer conductor 160 (i.e., the upper electrodes of the capacitors 101a and 101b shown in FIG. 13B ) and the upper layer conductor 261 (i.e., the back gate electrodes of the transistors 201a and 201b shown in FIG. 14 ) are formed from the conductive films 160A and 160B, and therefore the lower layer conductor 160 has the same material as the upper layer conductor 261. Furthermore, the lower layer insulator 154 and the upper layer insulator 263 are formed from the insulating film 154A, and therefore the lower layer insulator 154 has the same material as the upper layer insulator 263.

[0429] As described above, by simultaneously forming the conductor 160 and the insulator 154 in the lower layer and the conductor 261 and the insulator 263 in the upper layer, the manufacturing process of the semiconductor device according to this embodiment mode can be reduced, and the productivity of the semiconductor device can be improved.

[0430] Although the insulating film 154A is processed in the above example, the present invention is not limited to this. Only the conductive films 160A and 160B may be processed, and the insulating film 154A may be left as it is. This can reduce the number of processing steps for the insulator 154 and improve productivity.

[0431] Although the above description shows a structure in which the upper electrode (conductor 160) of the capacitor 101a and the second gate electrode (conductor 261) of the transistor 201a are provided separately, the present invention is not limited to this. As shown in FIG. 2B , only the insulator 154, the conductor 160a, and the conductor 160b can be formed from the insulating film 154A, the conductive film 160A, and the conductive film 160B. In this case, the conductor 160 serves as both the upper electrode of the capacitor 101a and the second gate electrode of the transistor 201a.

[0432] In this manner, the capacitor elements 101a and 101b can be formed.

[0433] After that, it is preferable to provide an insulator 284 to fill the spaces between the adjacent conductors 160 and 261 (FIG. 13B). It is also preferable to planarize the insulator 284 by using a CMP method.

[0434] After that, the above-described steps from the formation of the insulator 222 ( FIG. 7B ) to the formation of the capacitors 101a and 101b ( FIG. 13B ) are repeated to form layers above the second layer 11_2. For example, FIG. 14 shows an example of a cross-sectional structure at the time when the formation of the insulator 285 of the second layer 11_2 is completed. As shown in FIG. 14 , the conductor 261 formed in the step of FIG. 13B is disposed so as to overlap with the first gate electrodes of the transistors 201a and 201b, and functions as the second gate electrodes of the transistors 201a and 201b.

[0435] In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0436] The semiconductor device of this embodiment includes an OS transistor. The OS transistor has a small off-state current, which enables a semiconductor device or storage device with low power consumption. Furthermore, the OS transistor has high frequency characteristics, which enables a semiconductor device or storage device with high operation speed. Furthermore, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in the electrical characteristics of transistors, a semiconductor device with large on-state current, and a highly reliable semiconductor device or storage device can be realized.

[0437] Furthermore, in the semiconductor device of this embodiment, the conductor 240 has a stacked structure of a plurality of conductors, and therefore the manufacturing yield can be increased compared to the case where one conductor is used.

[0438] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0439] Embodiment 2 In this embodiment, a memory device of one embodiment of the present invention will be described with reference to FIGS.

[0440] This embodiment will describe a configuration example of a memory device using the semiconductor device described in the above embodiment as a memory cell, in which a layer having a functional circuit that has a function of amplifying and outputting a data potential held in the memory cell is provided between layers having stacked memory cells.

[0441] [Configuration Example of Storage Device] FIG. 15 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0442] 15 includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 including a plurality of functional circuits 51.

[0443] 15 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Also, Fig. 15 shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has a plurality of functional circuits 51 provided corresponding to the n wirings BL.

[0444] In FIG. 15 , the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In addition, in the present embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In addition, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 or more than n.

[0445] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0446] The memory cells 10 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 10 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0447] The memory array 20 may be configured with a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM with 1T (transistor) 1C (capacitor) type memory cells, where the access transistor is an OS transistor. The current flowing between the source and drain of an OS transistor in the off state, i.e., leakage current, is extremely small. By turning off (non-conducting) the access transistor, DOSRAM can retain charge corresponding to data stored in the capacitance element (capacitor) for a long period of time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM configured with transistors having silicon in the channel formation region (Si transistors). As a result, power consumption can be reduced.

[0448] Furthermore, as described in Embodiment 1 and the like, by stacking OS transistors, the memory cells 10 can be stacked. For example, in the memory array 20 shown in FIG. 15, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, thereby improving the memory density of the memory cells 10. Furthermore, the memory array 20 can be fabricated by repeatedly fabricating the same manufacturing process in the vertical direction. The memory device 300 can reduce the manufacturing cost of the memory array 20.

[0449] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conduction state or non-conduction state) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring CL (not shown) can be separately provided as a wiring that has a function of transmitting a back-gate potential to the back-gate of an OS transistor that is an access transistor. The wiring PL may also have a function of transmitting the back-gate potential.

[0450] The memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged in a direction perpendicular to the substrate surface on which the driver circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. This shortens the signal propagation distance between two circuits connected to the bit line, significantly reducing the resistance and parasitic capacitance of the bit line, thereby realizing reduced power consumption and signal delay. Furthermore, the memory cells 10 can be operated even if the capacitance of the capacitive element included in the memory cell 10 is reduced.

[0451] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via a wiring GBL (not shown), which will be described later. This configuration allows a slight potential difference in the wiring BL to be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, similar to the wiring BL. By arranging the wirings BL and GBL extending from the memory cells 10 of the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby realizing reduced power consumption and signal delay.

[0452] The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0453] The memory array 20 can be provided overlapping the drive circuit 21. By providing the drive circuit 21 and the memory array 20 overlapping, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby realizing reductions in power consumption and signal delay. In addition, the storage device 300 can be made smaller.

[0454] The functional circuit 51 is configured with OS transistors similar to the transistors included in the DOSRAM memory cells 10, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 20[1] to 20[m], thereby facilitating integration. The signal amplification configuration in the functional circuit 51 allows for the miniaturization of subsequent circuits such as the sense amplifier 46, thereby enabling the miniaturization of the memory device 300.

[0455] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0456] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0457] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0458] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0459] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0460] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0461] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of holding the read data, etc.

[0462] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0463] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW22 is controlled by the signal PON1, and the on / off of the PSW23 is controlled by the signal PON2. In FIG. 15, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0464] The memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a drive circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Figure 16A shows a perspective view of a storage device 300 having a functional layer 50 and five layers (m = 5) of memory arrays 20[1] to 20[5] stacked on a drive circuit 21.

[0465] 16A, the memory array 20 provided in the first layer is shown as memory array 20[1], the memory array 20 provided in the second layer is shown as memory array 20[2], and the memory array 20 provided in the fifth layer is shown as memory array 20[5]. Also shown in FIG. 16A are wiring WL, wiring PL, and wiring CL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that, to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 20 are partially omitted.

[0466] 16B is a schematic diagram illustrating a configuration example of a functional circuit 51 connected to the wiring BL illustrated in FIG. 16A and memory cells 10 included in memory arrays 20[1] to 20[5] connected to the wiring BL. Also, FIG. 16B illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0467] 16B illustrates an example of a circuit configuration of a memory cell 10 connected to a wiring BL. The memory cell 10 includes a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and each wiring (such as a wiring BL and a wiring WL) may also be referred to as a wiring BL[1] and a wiring WL[1], for example. An example of a cross-sectional configuration of the memory cell 10 corresponding to the circuit configuration can be found in Embodiment 1.

[0468] The transistor 11 corresponds to the transistor 201a or 201b described in Embodiment 1. The capacitor 12 corresponds to the capacitor 101a or 101b described in Embodiment 1. The wiring BL corresponds to the conductor 240 described in Embodiment 1.

[0469] As described in Embodiment 1, in the semiconductor device of one embodiment of the present invention, the wiring BL (the conductor 240) is directly in contact with at least one of the top surface, the side surface, and the bottom surface of the conductor 242a including a region functioning as one of the source electrode and the drain electrode of the transistor 11 (the transistor 201a). This eliminates the need to provide a separate electrode for connection, thereby reducing the area occupied by the memory array 20. Furthermore, the degree of integration of the memory cells 10 can be improved, and the storage capacity of the storage device 300 can be increased.

[0470] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to a wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of a capacitor 12. The other electrode of the capacitor 12 is connected to a wiring PL. The gate of the transistor 11 is connected to a wiring WL. The back gate of the transistor 11 is connected to a wiring CL.

[0471] The wiring PL is a wiring that applies a constant potential to maintain the potential of the capacitor 12. The wiring CL is a constant potential to control the threshold voltage of the transistor 11. The wiring PL and the wiring CL may have the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.

[0472] The wiring GBL shown in Fig. 16B is provided to electrically connect the driver circuit 21 and the functional layer 50. Fig. 17A is a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a repeating unit 70. Note that although Fig. 17A shows one wiring GBL, the wiring GBL may be provided as needed depending on the number of functional circuits 51 provided in the functional layer 50.

[0473] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or the drain of a transistor included in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.

[0474] The repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as shown in FIG. 17B . The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.

[0475] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged in a direction perpendicular to the surface of a substrate on which the driver circuit 21 is provided. By providing the wirings functioning as bit lines extending from the memory array 20 in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit lines can be significantly reduced.

[0476] In one embodiment of the present invention, a layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting a data potential held in the memory cell 10. With this configuration, a slight potential difference of the wiring BL that functions as a bit line can be amplified when reading data, and the sense amplifier 46 included in the driver circuit 21 can be driven. Since circuits such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. Furthermore, the memory device 300 can operate even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0477] 18 will be used to describe a configuration example of the functional circuit 51 described with reference to FIGS. 15 to 17 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21. FIG. 18 illustrates a driver circuit 21 connected to wirings GBL (wirings GBL_A and GBL_B) that are connected to functional circuits 51 (functional circuits 51_A and 51_B) that are connected to memory cells 10 (memory cells 10_A and 10_B) that are connected to different wirings BL (wirings BL_A and BL_B). As the driver circuit 21 illustrated in FIG. 18, in addition to the sense amplifier 46, precharge circuits 71_A, precharge circuits 71_B, switch circuits 72_A, switch circuits 72_B, and a write / read circuit 73 are illustrated.

[0478] 18 are OS transistors similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked in the same manner as the memory arrays 20[1] to 20[m].

[0479] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the sources or drains of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the sources or drains of the transistors 53_b and 54_b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors included in the driver circuit 21. As shown in FIG. 18 , the selection signal MUX, the control signal WE, and the control signal RE are applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.

[0480] 18, transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B are configured with Si transistors. Switches 83_A to 83_D constituting the switch circuits 72_A and 72_B can also be configured with Si transistors. One of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuits 71_A, 71_B, sense amplifier 46, and switch circuit 72_A.

[0481] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal applied to a precharge line PCL1.

[0482] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal applied to a precharge line PCL2.

[0483] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to a wiring VHH or a wiring VLL. The wiring VHH or the wiring VLL has a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors that form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cells 10_A and 10_B are selected, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D and the write / read circuit 73. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs. The write / read circuit 73 controls the writing of data signals in response to the signal EN_data.

[0484] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wirings GBL_A and GBL_B. The switch circuit 72_A is switched on or off under the control of a switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of a switching signal CSEL2. The switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.

[0485] 18 , the memory device 300 can be configured such that the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 50 including transistors that configure the functional circuit 51 increases, the load on the wirings BL is reduced, which shortens the write time and makes it easier to read data.

[0486] 18 , each transistor included in the functional circuits 51_A and 51_B is controlled in response to control signals WE and RE and a selection signal MUX. In response to the control signal and the selection signal, each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL. The functional circuits 51_A and 51_B can function as sense amplifiers including OS transistors. This configuration allows a slight potential difference in the wiring BL to be amplified during read operation, thereby driving the sense amplifier 46 using Si transistors.

[0487] [Example of Operation of Memory Cell 20, Functional Circuit 51, and Sense Amplifier 46] Fig. 19 shows a timing chart for explaining the operation of the circuit diagram shown in Fig. 18. In the timing chart shown in Fig. 19, a period T11 corresponds to a write operation, a period T12 corresponds to a precharge operation of the wiring BL, a period T13 corresponds to a precharge operation of the wiring GBL, a period T14 corresponds to a charge sharing operation, a period T15 corresponds to a read standby operation, and a period T16 corresponds to a read operation.

[0488] In the period T11, the potential of the wiring WL connected to the gate of the transistor 11 included in the memory cell 10 to which a data signal is to be written is set to high. At this time, the control signal WE and the signal EN_data are set to high, and the data signal is written to the memory cell through the wiring GBL and the wiring BL.

[0489] During the period T12, in order to precharge the wiring BL, the precharge line PCL1 is set to high level while the control signal WE is set to high level. The wiring BL is precharged to the precharge potential. During the period T12, it is preferable that the wiring VHH or the wiring VLL that supplies the power supply voltage to the sense amplifier 46 be set to VDD / 2 to suppress power consumption due to a through current.

[0490] In the period T13, the precharge line PCL2 is set to high level to precharge the wiring GBL. The wiring GBL is precharged to the precharge potential. In the period T13, the potentials of the wiring VHH and the wiring VLL are both set to VDD, so that the wiring GBL, which has a large load, can be precharged in a short time.

[0491] During the period T14, the potential of the wiring WL is set to a high level for charge sharing to balance the charges held in the memory cell 10 and the charges precharged to the wiring BL. During the period T14, the potential of the wiring VHH or the wiring VLL that supplies the power supply voltage to the sense amplifier 46 is preferably set to VDD / 2 to suppress power consumption due to a through current.

[0492] In the period T15, the control signal RE and the selection signal MUX are set to high level. Current flows through the transistor 52 depending on the potential of the wiring BL, and the potential of the wiring GBL fluctuates depending on the amount of current. The switching signal CSEL1 is set to low level to prevent fluctuations in the potential of the wiring GBL from being affected by the sense amplifier 46. The wiring VHH or the wiring VLL is the same as in the period T14.

[0493] During a period T16, the switching signal CSEL1 is set to a high level, and the fluctuation in the potential of the wiring GBL is amplified by the bit line pair connected to the sense amplifier 46, thereby reading out the data signal written in the memory cell.

[0494] [Configuration Example of Functional Circuit] Next, a specific configuration example of the functional circuit 51 functioning as a sense amplifier, which is formed using OS transistors included in the functional layer 50, will be described with reference to FIGS. 20A and 20B and FIGS. 21A and 21B.

[0495] 20A illustrates a functional circuit 51A that corresponds to the functional circuit 51_A or 51_B illustrated in FIG. 18. The functional circuit 51A illustrated in FIG. 20A includes transistors 52 to 55. The transistors 52 to 55 can each be formed using OS transistors and are illustrated as n-channel transistors.

[0496] The transistor 52 is a transistor constituting a source follower for amplifying the wiring GBL to a potential corresponding to the potential of the wiring BL during a period in which a data signal is read from the memory cell 10. The transistor 53 is a transistor that functions as a switch that receives a selection signal MUX at its gate and is controlled to be turned on or off between its source and drain in accordance with the selection signal MUX. The transistor 54 is a transistor that receives a control signal WE at its gate and is controlled to be turned on or off between its source and drain in accordance with the control signal WE. The transistor 55 is a transistor that receives a control signal RE at its gate and is controlled to be turned on or off between its source and drain in accordance with the control signal RE. Note that, for example, a ground potential GND, which is a fixed potential, is applied to the source side of the transistor 55.

[0497] 20B, 21A, and 21B can be applied to the configuration of the functional circuit 51A shown in FIG. 20A. In the functional circuit 51B of FIG. 20B, the connection of one of the source or drain of the transistor 54 is switched from the wiring GBL to one of the source or drain of the transistor 52. In the functional circuit 51C of FIG. 21A, the function of the transistor 53 is performed by the driver circuit 21, which corresponds to a configuration in which the transistor 53 is omitted. In the functional circuit 51D of FIG. 21B, the transistor 55 is omitted.

[0498] In one embodiment of the present invention, a semiconductor device uses OS transistors with extremely low off-state current as transistors provided in a memory array 20. The OS transistors can be stacked on a substrate on which a driver circuit 21 including Si transistors is provided. Therefore, the same manufacturing process can be repeatedly used in the vertical direction, thereby reducing manufacturing costs. Furthermore, in one embodiment of the present invention, the transistors constituting the memory cell 10 can be arranged vertically instead of planarly, thereby improving memory density and enabling miniaturization of the memory device.

[0499] Additionally, one embodiment of the present invention includes a functional layer 50 having a functional circuit 51. The functional circuit connects a wiring BL to a gate of a transistor 52, allowing the transistor 52 to function as an amplifier. With this configuration, a slight potential difference of the wiring BL can be amplified during reading to drive a sense amplifier 46 using a Si transistor. Circuits such as the sense amplifier 46 using a Si transistor can be miniaturized, thereby enabling miniaturization of the memory device. Furthermore, the memory cell 10 can operate even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0500] This embodiment mode can be combined with other embodiment modes as appropriate.

[0501] Embodiment 3 In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIGS.

[0502] 22A and 22B, multiple circuits (systems) are implemented on a chip 1200. The technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0503] As shown in FIG. 22A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0504] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201 as shown in Fig. 22B. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0505] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0506] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. Providing an image processing circuit or a multiply-and-accumulate operation circuit using OS transistors in the GPU 1212 enables image processing or multiply-and-accumulate operations to be performed with low power consumption.

[0507] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0508] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0509] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0510] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0511] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0512] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0513] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0514] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0515] This embodiment mode can be combined with other embodiment modes as appropriate.

[0516] Embodiment 4 In this embodiment, an example of an electronic component in which a memory device of one embodiment of the present invention is incorporated will be described.

[0517] [Electronic Component] FIG. 23A is a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 23A includes a memory device 300, which is a memory device of one embodiment of the present invention, in a mold 711. FIG. 23A omits some parts of the electronic component 700 in order to show the interior of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 300 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0518] As shown in the above embodiment, the storage device 300 includes a drive circuit 21 and a memory array 20 .

[0519] 23B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 300 provided on the interposer 731.

[0520] The electronic component 730 shows an example in which the storage device 300 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0521] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0522] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may also be used as the through electrode.

[0523] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0524] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0525] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0526] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 300 and the height of the semiconductor device 735.

[0527] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 23B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0528] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0529] This embodiment mode can be combined with other embodiment modes as appropriate.

[0530] Embodiment 5 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0531] The storage device of one embodiment of the present invention can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles). The storage device can also be used in image sensors, IoT (Internet of Things), healthcare-related devices, and the like. This can reduce the power consumption of electronic devices. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0532] 24A to 24J and 25A to 25E illustrate examples of electronic devices including the memory device of one embodiment of the present invention. Each electronic device includes an electronic component 700 or an electronic component 730 including the memory device described in the previous embodiment.

[0533] 24A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0534] By applying the storage device of one embodiment of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0535] 24B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0536] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying the storage device of one embodiment of the present invention.

[0537] 24C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0538] The desktop information terminal 5300, like the information terminal 5500 described above, can hold temporary files generated when an application is executed by applying the storage device of one embodiment of the present invention.

[0539] In Figures 24A to 24C, smartphones, wearable terminals, and desktop information terminals have been described as electronic devices, but other information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0540] 24D shows an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0541] The storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the storage device of one embodiment of the present invention.

[0542] In Figure 24D, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0543] 24E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0544] FIG. 24F also shows a home-use game console 7500, which is an example of a game console. The home-use game console 7500 can be particularly referred to as a home-use game console. The home-use game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in FIG. 24F , the controller 7522 can include a display unit for displaying game images and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 24F , and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in shooting games such as FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In music games, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with one or more of a camera, a depth sensor, and a microphone, and may be operated by the game player's gestures or voice.

[0545] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0546] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500. Furthermore, the reduced power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0547] Furthermore, by applying a storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations that occur during game execution can be stored.

[0548] In Figures 24E and 24F, portable game machines and home-use stationary game machines are described as examples of game machines, but other game machines include, for example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0549] [Mobile Body] A storage device according to one embodiment of the present invention can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0550] FIG. 24G illustrates an automobile 5700 as an example of a moving object.

[0551] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A storage device that displays this information may also be provided around the driver's seat.

[0552] In particular, the display device can enhance safety by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for a field of view obstructed by a pillar or the like, a blind spot on the driver's seat, etc. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0553] The storage device of one embodiment of the present invention can temporarily store information and thus can be used to temporarily store information required in a system that performs autonomous driving, road guidance, hazard prediction, or the like of the automobile 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Furthermore, the display device may be configured to store video images from a driving recorder installed in the automobile 5700.

[0554] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0555] [Camera] The storage device according to one embodiment of the present invention can be applied to a camera.

[0556] 24H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0557] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the digital camera 6240. Furthermore, the reduced power consumption can reduce heat generation from a circuit, and the influence of heat on the circuit itself, peripheral circuits, and modules can be reduced.

[0558] [Video Camera] The storage device of one embodiment of the present invention can be applied to a video camera.

[0559] 24I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0560] When recording video captured by the video camera 6300, the video needs to be encoded according to the data recording format. By using the storage device of one embodiment of the present invention, the video camera 6300 can store temporary files generated during encoding.

[0561] [ICD] The storage device according to one aspect of the present invention can be applied to an implantable cardioverter defibrillator (ICD).

[0562] 24J is a cross-sectional schematic diagram showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0563] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0564] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0565] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration of the treatment, and the like.

[0566] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0567] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0568] [Expansion Device for PC] A storage device according to one aspect of the present invention can be applied to an expansion device for computers such as PCs (Personal Computers) and information terminals.

[0569] Figure 25A shows an example of such an expansion device: a portable expansion device 6100 equipped with a chip capable of storing information and externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). While Figure 25A shows a portable expansion device 6100, the expansion device of one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0570] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. A circuit for driving the storage device of one embodiment of the present invention is provided on the board 6104. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0571] [SD Card] A storage device according to one embodiment of the present invention can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0572] FIG. 25B is a schematic diagram of the external appearance of an SD card, and FIG. 25C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a memory device and a circuit for driving the memory device. For example, an electronic component 700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0573] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0574] [SSD] A storage device according to one embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0575] FIG. 25D is a schematic diagram of the SSD's exterior, and FIG. 25E is a schematic diagram of the SSD's internal structure. The SSD 5150 includes a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the circuit board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing the electronic component 700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC (Error Check and Correct) circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0576] 26A is an example of a large-scale computer. The computer 5600 has a rack 5610 and multiple rack-mounted computers 5620 stored in it.

[0577] The computer 5620 can have the configuration shown in the perspective view in Fig. 26B, for example. In Fig. 26B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0578] PC card 5621 shown in Figure 26C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 26C illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0579] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0580] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0581] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0582] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0583] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0584] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0585] By using a storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller and consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which can reduce heat generation from a circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0586] This embodiment mode can be combined with other embodiment modes as appropriate.

[0587] Embodiment 6 In this embodiment, a specific example in which a semiconductor device of one embodiment of the present invention is applied to space equipment will be described with reference to FIGS.

[0588] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0589] Fig. 27 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 27, a planet 6804 is shown in space as an example.

[0590] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0591] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0592] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0593] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0594] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0595] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0596] Alternatively, for example, the OS transistor can be used as a transistor for a semiconductor device provided in a robot for working at a nuclear power plant or a radioactive waste treatment or disposal site, and particularly as a transistor for a semiconductor device provided in a remote-controlled robot that is remotely operated to dismantle a nuclear reactor facility, remove nuclear fuel or fuel debris, or conduct on-site inspections of spaces containing a lot of radioactive material.

[0597] This embodiment mode can be combined with other embodiment modes as appropriate.

[0598] In this example, a structure including an oxide 230 shown in FIGS. 8A to 8F was fabricated, and the results of cross-sectional SEM observation will be described.

[0599] In this example, a sample was prepared in which a base silicon oxide film, a hafnium oxide film (hereinafter referred to as an HfOx film), a silicon oxide film (hereinafter referred to as an SiOx film), an In—Ga—Zn oxide film (hereinafter referred to as an IGZO film), a stacked film of tantalum nitride and tungsten (hereinafter referred to as a TaNx\W film), a stacked film of silicon nitride and silicon oxide (hereinafter referred to as an SiNx\SiOx film), a tungsten film (hereinafter referred to as a W film), an SOC film, and an SOG film were stacked in this order on a silicon substrate. A resist mask was provided on the sample, and the etching process shown in FIGS. 8A to 8F was performed.

[0600] Here, the underlying silicon oxide film corresponds to the insulator 216 shown in FIGS. 8A to 8F. The HfOx film corresponds to the insulator 222. The SiOx film corresponds to the insulating film 224f and the insulator 224. The IGZO film corresponds to the stacked film of the oxide film 230af and the oxide film 230bf, and the stacked film of the oxide 230a and the oxide 230b. The TaNx\W film corresponds to the stacked film of the conductive film 242_1f and the conductive film 242_2f, and the stacked film of the conductor 242_1 and the conductor 242_2. The SiNx\SiOx film corresponds to the insulating film 271f and the insulator 271. The W film corresponds to the hard mask layer 276f and the hard mask layer 276. The SOC film corresponds to the organic coating film 277f and the organic coating film 277. The SOG film corresponds to the organic coating film 278 f and the organic coating film 278 .

[0601] First, the etching conditions required for the steps shown in Figures 8A to 8F were selected. As in Figure 8C, when etching the TaNx\W film, the SOC film must function as a mask. If the SOC film is removed during etching of the TaNx\W film, the W film provided below the SOC film will also be removed.

[0602] Therefore, dry etching was performed on the SOC film and the TaNx film and W film constituting the TaNx\W film, and the etching rates of each were measured. Furthermore, the etching selectivity of the TaNx film to the SOC film (hereinafter referred to as the TaNx / SOC selectivity) and the etching selectivity of the W film to the SOC film (hereinafter referred to as the W / SOC selectivity) were calculated.

[0603] The dry etching process was performed using a CCP etching apparatus. The etching conditions were: CHF as an etching gas; ３ Gas 35 sccm, Cl ２ The etching rate was measured under the following conditions: 15 sccm of gas and 10 sccm of Ar gas, a pressure of 0.6 Pa, an inter-electrode distance of 80 mm, an upper electrode power of 1000 W, and a substrate temperature of 60° C. The lower electrode power was set to 10 W, 25 W, 50 W, and 100 W, and the etching rate was measured under each condition.

[0604] The measurement results of the etching rate are shown in Figure 28A, and the etching selectivity is shown in Figure 28B. In Figure 28A, the horizontal axis represents the lower electrode power (Btm Power [W]) and the vertical axis represents the etching rate [nm / min]. In Figure 28B, the horizontal axis represents the lower electrode power (Btm Power [W]) and the vertical axis represents the etching selectivity.

[0605] As shown in Figure 28A, under the condition of a lower electrode power of 25 W or more, the etching rates of the TaNx film and the W film were approximately equal to or less than the etching rate of the SOC film. In Figure 28B, the TaNx / SOC selectivity and the W / SOC selectivity were 1.0 or less. In contrast, under the condition of a lower electrode power of 10 W, the etching rates of the TaNx film and the W film were greater than the etching rate of the SOC film. Under the condition of a lower electrode power of 10 W, the TaNx / SOC selectivity was 1.38, and the W / SOC selectivity was 1.42.

[0606] Thus, in etching the TaNx\W film, the lower electrode power should be at least less than 25 W, preferably 10 W or less. By etching the TaNx\W film under these conditions, the TaNx\W film can be removed without losing the SOC film.

[0607] Next, a method for manufacturing Sample 1A and Sample 1B, which have the above structures, will be described.

[0608] First, a silicon substrate was prepared, and a silicon oxide base film was formed on the silicon substrate by CVD. Next, a 20 nm thick HfOx film was formed on the silicon oxide base film by ALD.

[0609] Next, a SiOx film was formed on the HfOx film, and then an IGZO film was formed on the SiOx film. The SiOx film and the IGZO film were formed consecutively without exposure to the outside air. The SiOx film was formed to a thickness of 20 nm by sputtering using a Si target.

[0610] Here, the IGZO film has a laminated structure of a 10 nm thick IGZO (132) film and a 15 nm thick IGZO (111) film on the IGZO (132) film. The IGZO (132) film corresponds to the oxide film 230af and oxide 230a shown in FIGS. 8A to 8F. The IGZO (111) film corresponds to the oxide film 230bf and oxide 230b shown in FIGS. 8A to 8F. The IGZO film (132) was formed by sputtering using a target with an In:Ga:Zn = 1:3:2 [atomic ratio], and the IGZO film (111) was formed by sputtering using a target with an In:Ga:Zn = 1:1:1.2 [atomic ratio].

[0611] Next, a TaNx\W film was formed on the IGZO film using a sputtering method. The TaNx\W film was a stacked film consisting of a 5 nm thick TaNx film and a 15 nm thick W film on the TaNx film. The TaNx film was formed using a tantalum target in an atmosphere containing nitrogen gas. The W film was formed using a tungsten target.

[0612] Next, a SiNx\SiOx film was formed on the TaNx\W film using a sputtering method. The SiNx\SiOx film was a laminated film consisting of a 5 nm thick SiNx film and a 10 nm thick SiOx film on the SiNx film. The SiNx film was formed using a silicon target in an atmosphere containing nitrogen gas. The SiOx film was formed using a silicon target in an atmosphere containing oxygen gas.

[0613] Next, a 15 nm thick W film was formed on the SiNx\SiOx film by sputtering. Next, a SOC film was formed on the W film by spin coating. Next, a SOG film was formed on the SOC film by spin coating.

[0614] A negative resist film was formed on the stacked film prepared as described above, as in FIG. 8A . The resist film was irradiated with an electron beam to form island-shaped resist masks. In Sample 1A and Sample 1B, island-shaped resist masks were formed in regions with a width of 30 nm and regions with a width of 60 nm.

[0615] Next, using an island-shaped resist mask, dry etching processes corresponding to FIGS. 8B to 8F were performed. The dry etching processes were performed using a CCP etching device. The conditions for the dry etching processes are shown in Table 1. Table 1 shows the electrode distance (Gap (mm)), upper electrode power (Top Power (W)), lower electrode power (Btm Power (W)), pressure (Press (Pa)), gas flow rate (Gas (sccm)), and substrate temperature (Tsub (°C)) for the dry etching of each film.

[0616]

[0617] First, similarly to FIG. 8B, the SOG film was etched under the conditions shown in Table 1, and then the SOC film was etched.

[0618] 8C, the W film was etched (denoted as W_1 in Table 1) under the conditions shown in Table 1, followed by etching of the SiNx\SiOx film and then etching of the TaNx\W film. Here, the lower electrode power was set to 10 W for etching the TaNx\W film of sample 1A, and the lower electrode power was set to 25 W for etching the TaNx\W film of sample 1B.

[0619] Next, similarly to Fig. 8D, the IGZO film was etched under the conditions shown in Table 1. Next, similarly to Fig. 8E, the SiOx film was etched under the conditions shown in Table 1.

[0620] Finally, similarly to FIG. 8F, the W film remaining on the SiNx\SiOx film was removed by etching under the conditions shown in Table 1 (denoted as W_2 in Table 1).

[0621] Cross-sectional SEM images were taken of Sample 1A and Sample 1B prepared as described above. The cross-sectional SEM images were taken using Hitachi High-Tech's "SU8030" at an acceleration voltage of 5 kV.

[0622] Cross-sectional SEM images of sample 1A and sample 1B are shown in Figures 29 and 30. Here, Figure 29A is a cross-sectional SEM image of a region of sample 1A where the structure width is 30 nm, and Figure 29B is a cross-sectional SEM image of a region of sample 1B where the structure width is 30 nm. Also, Figure 30A is a cross-sectional SEM image of a region of sample 1A where the structure width is 60 nm, and Figure 30B is a cross-sectional SEM image of a region of sample 1B where the structure width is 60 nm.

[0623] 29A to 30B , in Sample 1B, in which the lower electrode power was set to 25 W, the TaNx\W film receded significantly, and the width of the structure was narrower than in Sample 1A, in which the lower electrode power was set to 10 W. In other words, as shown in FIGS. 28A and 28B , it is presumed that by lowering the lower electrode power, the SOC film remained even during etching of the TaNx\W film, and the W film was not etched. Therefore, one embodiment of the present invention can improve the productivity of semiconductor devices by simultaneously processing the TaNx\W film and the IGZO film using the method shown in FIGS. 8A to 8F .

[0624] In particular, the recession of the TaNx\W film was greater in the region where the structure width of sample 1B was 30 nm, but the recession of the TaNx\W film was suppressed in the region where the structure width of sample 1A was 30 nm. Therefore, as shown in the previous embodiment, even in a semiconductor device having a fine structure, processing can be performed as designed by processing under the conditions shown in this example.

[0625] This embodiment can be combined with any of the embodiment modes as appropriate.

[0626] BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GND: ground potential, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA: signal, RE: control signal, T11: period, T12: period, T13: period, T14: period, T15: period, T16: period, VHH: wiring, VLL: wiring, VPC: intermediate potential, WAKE : signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10[1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 11_1: first layer, 11_2: second layer, 11_3: third layer, 11_m: layer, 11: transistor, 12: capacitor, 20[1]: memory array, 20[2]: memory array, 20[5]: memory array, 20[i]: memory array, 20[m]: memory array, 20: Memory array, 21: driver circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51A: functional circuit, 51B: functional circuit, 51C: functional circuit, 51D: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 52: transistor, 53_a: transistor, 53 _b: transistor, 53: transistor, 54_a: transistor, 54_b: transistor, 54: transistor, 55_a: transistor, 55_b: transistor, 55: transistor, 70[1]: repeat unit, 70: repeat unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write / read circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor,82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 101a: capacitor, 101b: capacitor, 153A: conductive film, 153: conductor, 154A: insulating film, 154: insulator, 160a: conductor, 160A: conductive film, 160b: conductor, 160B: conductive film, 160: conductor, 201a: transistor, 201b: transistor, 202a: transistor, 202b: transistor, 202c: transistor, 202d: transistor, 202e: transistor, 205 a: conductor, 205b: conductor, 205: conductor, 207: conductor, 208: insulator, 209: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224f: insulating film, 224: insulator, 230a: oxide, 230af: oxide film, 230b: oxide, 230ba: region, 230bb: region, 230bc: region, 230bf: oxide film, 230: oxide, 240_1: conductor, 240_2: conductor, 240_3: conductor, 240_m: conductor, 240a: conductor, 240am: conductor, 240b: conductor, 240b m: conductor, 240: conductor, 241a: insulator, 241A: insulating film, 241b: insulator, 241: insulator, 242_1: conductor, 242_1f: conductive film, 242_2: conductor, 242_2f: conductive film, 242a: conductor, 242b: conductor, 242: conductor, 250a: insulator, 250b: insulator, 250c: insulator, 250: insu...

Claims

1. It comprises a first memory cell, a second memory cell on the first memory cell, a first conductor, and a second conductor on the first conductor. The first memory cell and the second memory cell each have a transistor, a capacitive element, and a first insulator on the transistor. The transistor comprises a metal oxide, a third conductor, a fourth conductor, and a second insulator on the metal oxide, a fifth conductor on the second insulator, a third insulator beneath the metal oxide, and a sixth conductor beneath the third insulator. The capacitive element comprises a seventh conductor, a fourth insulator on the seventh conductor, and an eighth conductor on the fourth insulator. A portion of the seventh conductor, the fourth insulator, and the eighth conductor are located on the first insulator. The fourth conductor and the seventh conductor are in contact through an opening provided in the first insulator. The first conductor has a portion that contacts the third conductor of the first memory cell, The upper surface of the first conductor has a portion that is in contact with the lower surface of the second conductor. The fifth conductor of the second memory cell has a region located on the fourth insulator and the eighth conductor of the first memory cell, and does not have a region located on the seventh conductor of the first memory cell. The second conductor has a portion that contacts the third conductor, the second memory cell. The sixth conductor of the second memory cell is made of the same material as the eighth conductor of the first memory cell. A semiconductor device wherein, in a cross-sectional view of the transistor, one side end of the third conductor substantially coincides with one side end of the metal oxide, and one side end of the fourth conductor substantially coincides with the other side end of the metal oxide.

2. In claim 1, The first conductor is in contact with a part of the upper surface and one of the side edges of the third conductor having the first memory cell, in a semiconductor device.

3. In claim 1, A semiconductor device wherein the side edge of the third insulator substantially coincides with the side edge of the metal oxide.

4. In claim 1, The third conductor and the fourth conductor each have a first layer and a second layer on the first layer, The first layer has a metal nitride, The second layer is a semiconductor device having higher conductivity than the first layer.

5. In claim 4, The first layer has tantalum nitride, The semiconductor device comprises a second layer made of tungsten.

6. In claim 1, The third conductor has a fifth insulator in contact with its upper surface, The fourth conductor has a sixth insulator in contact with the upper surface of the fourth conductor, A semiconductor device wherein the side end of the sixth insulator substantially coincides with the side end of the fourth conductor.

7. In any one of claims 1 to 6, The present invention comprises a third conductor, a fourth conductor, a metal oxide, and a seventh insulator covering the third insulator, The seventh insulator has a first opening superimposed on the region sandwiched between the third conductor and the fourth conductor, and a second opening superimposed on the opening of the first insulator. At least a portion of the second insulator and the fifth conductor is placed within the first opening of the seventh insulator. A semiconductor device in which at least a portion of the seventh conductor, the fourth insulator, and the eighth conductor are disposed within the second opening of the seventh insulator.

8. In claim 7, The first insulator has an eighth insulator on it, A portion of the fourth insulator is in contact with the upper surface of the eighth insulator. The eighth insulator is superimposed on the opening of the first insulator, and the semiconductor device has an opening.

9. In claim 8, A semiconductor device wherein the thickness of the eighth insulator is 50 nm or more and 250 nm or less.

10. In claim 8, The sixth conductor has a ninth insulator in contact with its lower surface, The ninth insulator of the second memory cell is in contact with the upper surface of the eighth insulator of the first memory cell. A semiconductor device wherein the ninth insulator of the second memory cell is made of the same material as the fourth insulator of the first memory cell.

11. In claim 7, A semiconductor device in which the side end of the seventh conductor is covered with the fourth insulator.

12. In claim 7, The semiconductor device comprises one or both of the fourth insulator, zirconium oxide and aluminum oxide.

13. In claim 7, A semiconductor device wherein the sixth conductor is superimposed on the fifth conductor via the metal oxide.

14. In claim 7, The first conductor has a tenth insulator in contact with its side surface, A semiconductor device wherein at least a portion of the third conductor is exposed from the tenth insulator and in contact with the first conductor.

15. In claim 14, The semiconductor device comprises one or both of the tenth insulator, aluminum oxide and silicon nitride.

16. In claim 7, The semiconductor device comprises aluminum oxide as the first insulator.

17. A first insulator, a second insulator, a metal oxide, a second conductor, and a third insulator are deposited on a first conductor in this order. The second insulator, the metal oxide, the second conductor, and the third insulator are processed to form island-shaped second insulators, island-shaped metal oxides, island-shaped second conductors, and island-shaped third insulators. A fourth insulator is formed by covering the first insulator, the island-shaped second insulator, the island-shaped metal oxide, the island-shaped second conductor, and the island-shaped third insulator. A first opening is formed in the fourth insulator, and the island-shaped third insulator is divided by superimposing it on the first opening to form a fifth insulator and a sixth insulator, and the island-shaped second conductor is divided to form a third conductor and a fourth conductor, A seventh insulator and a fifth conductor are formed within the first opening, An eighth insulator is formed on the fourth insulator and the fifth conductor. A second opening is formed in the eighth insulator, the fourth insulator, and the fifth insulator, reaching the third conductor. A sixth conductor is formed within the second opening. The ninth insulator and the seventh conductor are formed by covering the sixth conductor, The ninth insulator and the seventh conductor are processed to form a tenth insulator and an eleventh insulator, an eighth conductor on the tenth insulator, and a ninth conductor on the eleventh insulator. The eighth conductor overlaps with the tenth insulator and the sixth conductor. The ninth conductor overlaps with the metal oxide and the fifth conductor. Method for manufacturing semiconductor devices.

18. In claim 17, Before forming the second opening, a third opening is formed by penetrating the eighth insulator, the fourth insulator, the sixth insulator, and the first insulator. A tenth conductor is formed in the third opening. The tenth conductor is in contact with a part of the fourth conductor. Method for manufacturing semiconductor devices.

19. In claim 17, Before processing the second insulator, the metal oxide, the second conductor, and the third insulator, a metal film is formed on the third insulator, and an organic coating film is formed on the metal film. A capacitively coupled plasma etching apparatus is used to process the second insulator, the metal oxide, the second conductor, and the third insulator. Method for manufacturing semiconductor devices.

20. In claim 19, When processing the second conductor, the island-shaped second conductor is formed before the organic coating film disappears. Method for manufacturing semiconductor devices.

21. In claim 19, During the processing of the second conductor, the power of the lower electrode of the chamber of the capacitively coupled plasma etching apparatus is set to 10W or less. Method for manufacturing semiconductor devices.

22. In claim 17, A method for manufacturing a semiconductor device, wherein the first conductor overlaps with the metal oxide and the fifth conductor.

23. In claim 17, A method for manufacturing a semiconductor device, wherein the first insulator is hafnium oxide.

24. In claim 17, A method for manufacturing a semiconductor device, wherein the second insulator is silicon oxide.

25. In claim 17, A method for manufacturing a semiconductor device, wherein the metal oxides are indium, gallium, and zinc.

26. In claim 17, A method for manufacturing a semiconductor device, wherein the second conductor has a laminated structure comprising a layer containing tantalum nitride and a layer containing tungsten on the layer containing tantalum nitride.

27. In claim 17, A method for manufacturing a semiconductor device, wherein the film thickness of the eighth insulator is 50 nm or more and 250 nm or less.

28. In claim 17, The tenth insulator has the same material as the eleventh insulator, A method for manufacturing a semiconductor device, wherein the eighth conductor is made of the same material as the ninth conductor.