Semiconductor device

Abstract

A semiconductor device according to the present invention is provided with a gate trench that is formed in a semiconductor layer, and a gate electrode that is embedded in the gate trench, with an insulating layer interposed therebetween. The gate trench includes a first outer peripheral gate trench section that is provided in an outer peripheral region thereof, and a second outer peripheral gate trench section that is provided outward of the first outer peripheral gate trench section. The semiconductor device is provided with, in the semiconductor layer, a first floating trench that is formed in a region between the first outer peripheral gate trench section and the second outer peripheral gate trench section, and a first floating electrode that is embedded in the first floating trench, with an insulating layer interposed therebetween, and that is in an electrically floating state.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device having a trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) as a basic structure, which includes an active region set in a region covered with a source electrode, a gate trench formed in the active region, and a polysilicon gate embedded in the gate trench.

[0003] Japanese Patent Application Laid-Open No. 2020-194881

[0004] However, in a trench gate MOSFET, there is a risk of the so-called walk-in phenomenon occurring, in which the drain-source breakdown voltage decreases.

[0005] a gate electrode formed on the insulating layer and electrically connected to the gate electrode; a first floating trench formed in the semiconductor layer in a region between the first and second peripheral gate trench portions; and a floating electrode embedded in the first floating trench via the insulating layer. The semiconductor layer includes a peripheral region that includes an outer edge of the semiconductor layer in a planar view. The gate trench includes a first peripheral gate trench portion provided in the peripheral region and a second peripheral gate trench portion provided outward from the first peripheral gate trench portion. The semiconductor device also includes a first floating trench formed in a region of the semiconductor layer between the first peripheral gate trench portion and the second peripheral gate trench portion.

[0006] A semiconductor device according to an aspect of the present disclosure includes a semiconductor layer, a gate trench formed in the semiconductor layer, an insulating layer formed on the semiconductor layer, a gate electrode embedded in the gate trench with the insulating layer interposed therebetween, a gate wiring formed on the insulating layer and electrically connected to the gate electrode, a plurality of protection trenches formed in the semiconductor layer, and a protection electrode embedded in the protection trench with the insulating layer interposed therebetween, wherein the semiconductor layer includes an outer periphery region that includes an outer edge of the semiconductor layer in a plan view and in which the protection trench is disposed, and the gate trench is disposed in the outer periphery region and is interposed between the gate trench and the protection trench in a plan view. a first floating trench and a second floating trench formed in a region of the semiconductor layer between the peripheral gate trench portion and the protection trench, a first floating electrode embedded in the first floating trench via the insulating layer and in an electrically floating state, and a second floating electrode embedded in the second floating trench via the insulating layer and in an electrically floating state, wherein the first floating trench is positioned closer to the second floating trench than the peripheral gate trench portion.

[0007] According to the semiconductor device of the present disclosure, the occurrence of the walk-in phenomenon can be suppressed.

[0008] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view illustrating metal layers of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic plan view illustrating a configuration formed in a semiconductor layer of the semiconductor device shown in FIG. 1. FIG. 4 is a partial enlarged view of the area indicated by F4 in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 4. FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. 4. FIG. 7 is a partial enlarged view of the area indicated by F7 in FIG. 6. FIG. 8 is a partial enlarged view of the area indicated by F8 in FIG. 6. FIG. 9 is a graph showing the relationship between the distance between the second floating trench and the protection trench and the drain-source breakdown voltage. FIG. 10 is a graph showing the relationship between the distance between the first outer periphery gate trench portion and the first floating trench and the drain-source breakdown voltage. FIG. 11 is a graph showing the relationship between the distance between the second outer periphery gate trench portion and the first floating trench and the drain-source breakdown voltage. FIG. 12 is a partial enlarged view of a schematic planar structure of a configuration formed in a semiconductor layer of a semiconductor device of a comparative example. FIG. 13 is a graph showing the IV characteristics of the semiconductor device of the comparative example. FIG. 14 is a graph showing the IV characteristics of the semiconductor device of the first embodiment. FIG. 15 is a partial enlarged view of a schematic planar structure of a configuration formed in a semiconductor layer of a semiconductor device of a second embodiment. FIG. 16 is a schematic cross-sectional view of the semiconductor device taken along line F16-F16 in FIG. 15. FIG. 17 is a partial enlarged view of the area indicated by F17 in FIG. 16. FIG. 18 is a graph showing the relationship between the distance between the first floating trench and the second floating trench and the drain-source breakdown voltage. FIG. 19 is a graph showing the relationship between the distance between the outer gate trench portion and the first floating trench and the drain-source breakdown voltage. FIG. 20 is a graph showing the IV characteristics of the semiconductor device of the second embodiment.

[0009] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] First Embodiment [Plane Layout of Semiconductor Device] FIGS. 1 to 3 are schematic plan views of a semiconductor device 10 according to a first embodiment. Some components of the semiconductor device 10 in FIG. 1 are transparently illustrated in FIGS. 2 and 3 . More specifically, FIG. 2 is a schematic plan view of the semiconductor device 10, in which a passivation layer 12 (described later) is transparently illustrated in FIGS. 1 and 3 . FIG. 3 is a schematic plan view of the semiconductor device 10, in which a metal layer 18 (source wiring 20, gate wiring 22, and peripheral electrode 24) (described later) is transparently illustrated in FIGS. 2 and 3 . For ease of understanding, the metal layer 18 is indicated by a dashed line in FIG. 3 . Also, for ease of understanding, a first floating trench 52A and a second floating trench 52B (described later) are omitted from FIGS. 1 to 3 .

[0012] The term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Figure 1. Unless explicitly stated otherwise, "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0013] As shown in FIG. 1 , the semiconductor device 10 may have a rectangular shape in a plan view. In one example, the semiconductor device 10 may have a rectangular parallelepiped shape. In one example, the semiconductor device 10 may be formed in a flat plate shape with the Z-axis direction as the thickness direction. The semiconductor device 10 may include a passivation layer 12. The passivation layer 12 may be made of any material that can protect the structure below it. In one example, the passivation layer 12 may be made of a silicon nitride film (SiN). The passivation layer 12 may include pad openings 14 and 16. Note that the constituent material of the passivation layer 12 can be changed as desired. In one example, the passivation layer 12 may be made of a silicon oxide film (SiO ２ The passivation layer 12 may be formed of a SiN film and a SiO ２ It may be configured by a laminated structure of films.

[0014] The semiconductor device 10 may further include a metal layer 18. The passivation layer 12 at least partially covers the metal layer 18. The metal layer 18 may be formed of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy. In one example, the metal layer 18 may be formed of an AlCu alloy.

[0015] The metal layer 18 may include a source wiring 20, a gate wiring 22, and a peripheral electrode 24. The source wiring 20, the gate wiring 22, and the peripheral electrode 24 are spaced apart from one another. The gate wiring 22 is spaced apart from the source wiring 20 and surrounds it. The peripheral electrode 24 is spaced apart from the gate wiring 22 and surrounds it. Further details of the source wiring 20, the gate wiring 22, and the peripheral electrode 24 will be described below with reference to FIG. 2 .

[0016] The pad opening 14 can at least partially expose the source wiring 20. The pad opening 16 can at least partially expose the gate wiring 22. The pad openings 14 and 16 can be provided to enable external connection to the source wiring 20 and the gate wiring 22, respectively. On the other hand, the peripheral electrode 24 may be completely covered by the passivation layer 12. The configurations (e.g., position, shape, size, number, etc.) of the pad openings 14 and 16 can be determined appropriately depending on, for example, the design and usage mode of the semiconductor device 10, and are not limited to the example of FIG. 1 .

[0017] As shown in Fig. 2, the semiconductor device 10 may include a semiconductor layer 26. The metal layer 18 is formed on the semiconductor layer 26. The semiconductor layer 26 includes a first surface 26A and a second surface 26B opposite the first surface 26A (see Fig. 5). The Z-axis direction shown in Fig. 2 corresponds to a direction perpendicular to the first surface 26A and the second surface 26B of the semiconductor layer 26.

[0018] The semiconductor layer 26 can be formed of at least one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). In one example, the semiconductor layer 26 may be formed of Si. The second surface 26B of the semiconductor layer 26 includes two sides 26X1 and 26X2 extending along the X-axis direction and two sides 26Y1 and 26Y2 extending along the Y-axis direction. The outer edge of the semiconductor layer 26 can include four sides 26X1, 26X2, 26Y1, and 26Y2 in a plan view. The area defined by the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 can correspond to one chip (die).

[0019] The semiconductor layer 26 may include, in plan view, a peripheral region 28 and an active region 30 surrounded by the peripheral region 28. The boundary between the peripheral region 28 and the active region 30 is indicated by a two-dot chain line in FIG.

[0020] The active region 30 is a region that contributes to the operation of the semiconductor device 10 as a transistor. The peripheral region 28 is a region that does not contribute to the operation of the semiconductor device 10 as a transistor. The peripheral region 28 may include four sides 26X1, 26X2, 26Y1, and 26Y2 that form the outer edges of the semiconductor layer 26. The peripheral region 28 may have a rectangular frame shape that surrounds the active region 30 in a plan view. Further details of the semiconductor layer 26 will be described later with reference to FIG. 5 .

[0021] The source wiring 20 may include a recess 20A by having a cutout that is substantially rectangular in plan view. The recess 20A may be formed at an end of the source wiring 20 that is close to any of the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In the example of FIG. 2 , the recess 20A may be formed at the center in the X-axis direction of the source wiring 20 that is close to the side 26X2 of the semiconductor layer 26. The recess 20A may be open toward the side 26X2.

[0022] The gate wiring 22 may include gate finger portions 32 and a gate pad portion 34. The gate finger portions 32 may be arranged in the periphery region 28. The gate finger portions 32 may extend along at least parts of the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26, thereby at least partially surrounding the source wiring 20. The gate pad portion 34 may be arranged in the periphery region 28. The gate pad portion 34 may be at least partially arranged within the recess 20A of the source wiring 20. The gate pad portion 34 may be integrally connected to the gate finger portions 32. In the example of FIG. 2 , the gate pad portion 34 may be arranged to connect two portions of the gate finger portions 32 extending along the side 26X2 in a plan view.

[0023] The peripheral electrode 24 may have a closed ring shape in a plan view. The peripheral electrode 24 may extend along four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. The peripheral electrode 24 may be spaced apart from the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26.

[0024] 3 schematically shows several components formed in the semiconductor layer 26. The semiconductor device 10 may further include a gate trench 36 formed in the semiconductor layer 26. The gate trench 36 is formed in both the periphery region 28 and the active region 30 of the semiconductor layer 26. The gate trench 36 may include a periphery gate trench portion 38 disposed in the periphery region 28, an inner gate trench portion 40 (see FIG. 4) disposed in the active region 30, and a connecting gate trench portion 42 that connects the periphery gate trench portion 38 to the inner gate trench portion 40.

[0025] The active region 30 may be formed at a position overlapping the source wiring 20 in a planar view. The active region 30 may have a similar shape to the source wiring 20 including the recess 20A in a planar view. The active region 30 may be slightly smaller than the source wiring 20 including the recess 20A in a planar view. The active region 30 is covered by the source wiring 20 but is not covered by the gate pad portion 34. The inner gate trench portion 40 may be disposed in the active region 30. Therefore, the inner gate trench portion 40 may be disposed at a position overlapping the source wiring 20 in a planar view. The connection gate trench portion 42 connected to the inner gate trench portion 40 may be disposed at a position partially overlapping the source wiring 20 in a planar view.

[0026] The peripheral region 28 can have a shape similar to that of the gate finger portions 32 and the gate pad portion 34 in a plan view. The peripheral region 28 can include a region that extends into the recess 20A of the source wiring 20 in a plan view. The peripheral region 28 is covered by the gate finger portions 32 and the gate pad portion 34.

[0027] The peripheral gate trench 38 disposed in the peripheral region 28 can have a shape that surrounds the source wiring 20. In one example, the peripheral gate trench 38 can have a shape similar to that of the source wiring 20, including the recess 20A, in a planar view in the peripheral region 28. The peripheral gate trench 38 may be slightly larger than the source wiring 20, including the recess 20A, in a planar view. In this manner, the peripheral gate trench 38 can be formed in a closed ring shape having a recess that conforms to the recess 20A in a planar view. The peripheral gate trench 38 is disposed in a position that does not overlap with both the gate finger 32 and the gate pad 34 in a planar view. Furthermore, the peripheral gate trench 38 is disposed in a position that does not overlap with the source wiring 20 in a planar view. In other words, the peripheral gate trench 38 is disposed between the source wiring 20 and the gate finger 32 and the gate pad 34 in a planar view.

[0028] The semiconductor device 10 may further include a protection trench 44 formed in the semiconductor layer 26. The protection trench 44 may be arranged to surround the outer periphery gate trench portion 38. The protection trench 44 may have a shape similar to that of the outer periphery gate trench portion 38 in a plan view. It can also be said that the outer periphery gate trench portion 38 is surrounded by the protection trench 44 in a plan view. The semiconductor device 10 may include multiple protection trenches 44.

[0029] [Arrangement of Gate Trenches and Protection Trenches Around Gate Finger Portions] Fig. 4 is a partially enlarged view of Fig. 3, showing an enlarged portion F4 surrounded by a dashed line in Fig. 3. For ease of understanding, the source wiring 20, the gate wiring 22 (gate finger portions 32), and the peripheral electrode 24 are indicated by dot hatching in Fig. 4.

[0030] 4, the inner gate trench portions 40 arranged in the active region 30 may be formed in a grid pattern. The semiconductor device 10 may further include source contact portions 46 connected to the source wiring 20. The source contact portions 46 may be arranged in multiple rectangular regions of the semiconductor layer 26 surrounded by the inner gate trench portions 40. In another example, the inner gate trench portions 40 may be formed in a stripe pattern, for example.

[0031] The perimeter gate trenches 38 arranged in the perimeter region 28 may include a first perimeter gate trench 38A and a second perimeter gate trench 38B located further outward than the first perimeter gate trench 38A. In plan view, the second perimeter gate trench 38B may be located on the opposite side of the first perimeter gate trench 38A from the active region 30. In plan view, the second perimeter gate trench 38B may be located farther from the active region 30 than the first perimeter gate trench 38A. In other words, the first perimeter gate trench 38A may be located closer to the active region 30 than the second perimeter gate trench 38B. The first perimeter gate trench 38A and the second perimeter gate trench 38B may have similar shapes in plan view.

[0032] Each of the outer periphery gate trenches 38A, 38B can have a width greater than that of the inner gate trench 40. Here, the width of the first outer periphery gate trench 38A refers to the dimension in a direction perpendicular to the extension direction of the first outer periphery gate trench 38A in a planar view. The width of the first outer periphery gate trench 38A can also be referred to as the length in the short direction of the first outer periphery gate trench 38A in a planar view. For example, the first outer periphery gate trench 38A shown in FIG. 4 extends in the Y-axis direction, and therefore has a width in the X-axis direction. Similarly, the width of the second outer periphery gate trench 38B refers to the dimension in a direction perpendicular to the extension direction of the second outer periphery gate trench 38B in a planar view. The width of the second outer periphery gate trench 38B can also be referred to as the length in the short direction of the second outer periphery gate trench 38B in a planar view. For example, the second outer periphery gate trench 38B shown in FIG. 4 extends in the Y-axis direction, and therefore has a width in the X-axis direction. Furthermore, the width of the inner gate trench 40 refers to the dimension in a direction perpendicular to the extension direction of the inner gate trench 40 in a plan view. In other words, the width of the inner gate trench 40 can also be said to be the length in the short direction of the inner gate trench 40 in a plan view.

[0033] The semiconductor device 10 may further include a gate contact portion 48 connected to the gate wiring 22 (gate finger portion 32). The gate contact portion 48 may be disposed in a region overlapping with each of the outer periphery gate trench portions 38A, 38B in plan view. The semiconductor device 10 may include multiple gate contact portions 48.

[0034] The connection gate trench 42, which connects the first outer periphery gate trench 38A to the inner gate trench 40, is located closer to the active region 30 than the first outer periphery gate trench 38A. The connection gate trench 42 is connected to the first outer periphery gate trench 38A. On the other hand, the connection gate trench 42 is not connected to the second outer periphery gate trench 38B. The connection gate trench 42 is disposed across both the outer periphery region 28 and the active region 30. The connection gate trench 42 can extend in a direction (X-axis direction in FIG. 4 ) that intersects with the direction in which the first outer periphery gate trench 38A extends (Y-axis direction in FIG. 4 ). A plurality of connection gate trenches 42 may be provided and arranged in a striped pattern.

[0035] A plurality of protection trenches 44 (16 in the example of FIG. 4 ) surrounding each of the peripheral gate trench portions 38A, 38B are arranged in the peripheral region 28. The semiconductor device 10 may include one or a plurality of protection trenches 44. The number of protection trenches 44 can be set appropriately depending on the desired performance and layout of the semiconductor device 10. In the example of FIG. 4 , the plurality of protection trenches 44 are arranged at equal pitches. Note that the arrangement of the plurality of protection trenches 44 can be changed as desired. In one example, at least some of the plurality of protection trenches 44 may be arranged at different pitches.

[0036] 4 , when a plurality of protective trenches 44 are provided, some of the protective trenches 44 may be arranged at positions overlapping the gate finger portions 32 in a plan view. Alternatively, all of the plurality of protective trenches 44 may be arranged at positions overlapping the gate finger portions 32 in a plan view.

[0037] The semiconductor device 10 may further include a peripheral contact portion 50 connected to the peripheral electrode 24. The peripheral contact portion 50 may be formed in a closed ring shape. The ring-shaped peripheral contact portion 50 may surround the protection trench 44 in a plan view. The semiconductor device 10 may include multiple peripheral contact portions 50.

[0038] The source contact portion 46, the gate contact portion 48, and the peripheral contact portion 50 may be formed of any metallic material. In one example, each of the contact portions 46, 48, and 50 may be formed of at least one of tungsten (W), Ti, and titanium nitride (TiN).

[0039] The semiconductor device 10 may include a first floating trench 52A and a second floating trench 52B disposed between the connection gate trench portion 42 and the protection trench 44. Further details of each of the floating trenches 52A, 52B will be described below with reference to Figures 4-6 and 8.

[0040] 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 4. The semiconductor layer 26 can include a semiconductor substrate 54 including a first surface 26A of the semiconductor layer 26, and an epitaxial layer 56 formed on the semiconductor substrate 54 and including a second surface 26B of the semiconductor layer 26. In this embodiment, the semiconductor substrate 54 can be a Si substrate. The semiconductor substrate 54 can correspond to the drain region of the MISFET. The drain region (semiconductor substrate 54) can be a p-type impurity-containing epitaxial layer 56. ＋ The impurity concentration of the semiconductor substrate 54 may be 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The semiconductor substrate 54 may have a thickness of 50 μm or more and 450 μm or less. The epitaxial layer 56 may be a Si layer epitaxially grown on a Si substrate. Further details of the epitaxial layer 56 will be described below with reference to FIGS. 7 and 8.

[0041] The semiconductor device 10 may further include a drain electrode 58 formed on the first surface 26A of the semiconductor layer 26. The drain electrode 58 is electrically connected to the drain region (semiconductor substrate 54). The drain electrode 58 may be made of at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy.

[0042] The semiconductor device 10 may further include an insulating layer 60 formed on the semiconductor layer 26. In one example, the insulating layer 60 may be made of SiO ２ The insulating layer 60 can additionally or alternatively be formed by SiO ２ The insulating layer 60 may include a film formed of an insulating material different from the insulating layer 60, such as SiN. ２ It may be configured by a laminated structure of films.

[0043] The insulating layer 60 is in contact with the second surface 26B of the semiconductor layer 26. The source wiring 20, the gate wiring 22, and the peripheral electrode 24 are formed on the insulating layer 60. The passivation layer 12 at least partially covers the source wiring 20, the gate wiring 22, and the peripheral electrode 24 formed on the insulating layer 60. Portions of the insulating layer 60 that are not covered by the source wiring 20, the gate wiring 22, and the peripheral electrode 24 may also be covered by the passivation layer 12.

[0044] The gate trench 36 has an opening in the second surface 26B of the semiconductor layer 26 and a depth in the Z-axis direction. Similarly, the protection trench 44 has an opening in the second surface 26B of the semiconductor layer 26 and a depth in the Z-axis direction. In the illustrated example, the gate trench 36 and the protection trench 44 are shown to have approximately the same depth, but in other examples, they may have different depths. For example, the protection trench 44 may be formed deeper in the semiconductor layer 26 than the gate trench 36. Alternatively, the protection trench 44 may be formed shallower in the semiconductor layer 26 than the gate trench 36. In yet another example, the outer periphery gate trench portions 38A, 38B and the inner gate trench portion 40 may have different depths. For example, the outer periphery gate trench portions 38A, 38B may be formed deeper than the inner gate trench portion 40.

[0045] 5 shows a cross section along the longitudinal direction of one connection gate trench portion 42. The two ends of the connection gate trench portion 42 are respectively connected to the first outer periphery gate trench portion 38A and the inner gate trench portion 40. In this manner, the gate trench 36 can be configured by the first outer periphery gate trench portion 38A, the inner gate trench portion 40, and the connection gate trench portion 42 being connected to each other, and by the second outer periphery gate trench portion 38B spaced outward from the first outer periphery gate trench portion 38A.

[0046] 7 and 8 are embedded in each of the outer periphery gate trenches 38A, 38B, the inner gate trench 40, and the connection gate trench 42, with an insulating layer 60 interposed therebetween. Because the first outer periphery gate trench 38A, the inner gate trench 40, and the connection gate trench 42 are interconnected, the integrally formed gate electrode 62 can be embedded across the first outer periphery gate trench 38A, the inner gate trench 40, and the connection gate trench 42. A gate electrode 62 separate from the integrally formed gate electrode 62 can be embedded in the second outer periphery gate trench 38B.

[0047] The source contact portion 46 extends through the insulating layer 60 between the source wiring 20 and the semiconductor layer 26, thereby connecting the source wiring 20 to the semiconductor layer 26. The peripheral contact portion 50 extends through the insulating layer 60 between the peripheral electrode 24 and the semiconductor layer 26, thereby connecting the peripheral electrode 24 to the semiconductor layer 26.

[0048] 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in FIG. 4, showing the region between two adjacent connection gate trench portions 42. In FIG. 6, descriptions of the same configuration as in FIG. 5 will be omitted.

[0049] 6 shows the portion of the first perimeter gate trench portion 38A that is not in direct communication with the connecting gate trench portion 42, and the second perimeter gate trench portion 38B. As described above and shown, each perimeter gate trench portion 38A, 38B can have a width greater than that of the inner gate trench portion 40. In one example, each perimeter gate trench portion 38A, 38B can have a width that is at least 1.2 times and at most 2.5 times the width of the inner gate trench portion 40.

[0050] The gate contact portions 48 extend through the insulating layer 60 to connect the gate finger portions 32 to the gate electrodes 62 embedded in the outer gate trench portions 38A, 38B (see FIG. 8). Therefore, the gate wiring 22 is electrically connected to the gate electrodes 62.

[0051] FIG. 7 is a partially enlarged view of FIG. 6 , showing an enlarged portion F7 surrounded by a dashed line in FIG. 6 . FIG. 7 shows a cross-sectional view of the active region 30 (see FIG. 3 ). The semiconductor device 10 may further include a gate electrode 62 embedded in the gate trench 36 via an insulating layer 60. In one example, the gate electrode 62 may be formed of conductive polysilicon. The insulating layer 60 may include a gate insulating film 64 interposed between the gate electrode 62 and the semiconductor layer 26 and covering the gate trench 36, and an interlayer insulating film 66 formed between the metal layer 18 and the semiconductor layer 26. The gate electrode 62 is separated from the semiconductor layer 26 by the gate insulating film 64.

[0052] FIG. 7 shows a gate insulating film 64 interposed between the gate electrode 62 and the semiconductor layer 26 and covering the inner gate trench portion 40, and an interlayer insulating film 66 formed between the source wiring 20 and the semiconductor layer 26.

[0053] The semiconductor layer 26 (epitaxial layer 56) may include a drift region 68, a body region 70 formed on the drift region 68, and a source region 72 formed on the body region 70. The source region 72 may include a second surface 26B of the semiconductor layer 26. The semiconductor layer 26 (epitaxial layer 56) may further include a contact region 74 located below the source contact portion 46. The source wiring 20 is electrically connected to the contact region 74 via the source contact portion 46.

[0054] The drift region 68 is a p-type impurity region containing a lower concentration of p-type impurities than the drain region (semiconductor substrate 54). － The impurity concentration of the drift region 68 may be 1×10 １５ cm －３ 1x10 or more １８ cm －３ The drift region 68 may have a thickness of not less than 1 μm and not more than 25 μm.

[0055] The body region 70 is an n-type impurity-containing － The impurity concentration of the body region 70 may be 1×10 １６ cm －３ 1x10 or more １８ cm －３ The body region 70 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0056] The source region 72 is a p-type impurity region containing a higher concentration of p-type impurities than the drift region 68. ＋ The impurity concentration of the source region 72 may be higher than that of the body region 70. The impurity concentration of the source region 72 may be 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The source region 72 may have a thickness of not less than 0.1 μm and not more than 1 μm.

[0057] The contact region 74 is an n-type impurity-containing ＋ The impurity concentration of the contact region 74 is higher than that of the body region 70, and is 1×10 １９cm －３ 1x10 or more ２１ cm －３ It can be as follows:

[0058] In this disclosure, p-type is also referred to as the first conductivity type, and n-type is also referred to as the second conductivity type. P-type impurities may be, for example, boron (B) or aluminum (Al). N-type impurities may be, for example, phosphorus (P) or arsenic (As).

[0059] The inner gate trench 40 has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating both the source region 72 and the body region 70. The sidewalls of the inner gate trench 40 may extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (the Z-axis direction). In the illustrated example, the inner gate trench 40 may have side surfaces that are slightly inclined with respect to the Z-axis direction. In the illustrated example, the bottom wall of the inner gate trench 40 is formed into an overall curved shape, but this is not limited thereto. For example, the bottom wall of the inner gate trench 40 may have both ends in the X-axis direction that are curved, or may have a flat surface along the XY plane.

[0060] When a predetermined voltage is applied to the gate electrode 62, the n － A channel is formed in the body region 70 of the semiconductor device 10. ＋ type source region 72 and p － The flow of holes in the Z-axis direction to and from the drift region 68 of the mold can be controlled.

[0061] Fig. 8 is a partially enlarged view of Fig. 6, and shows an enlarged portion F8 surrounded by a dashed line in Fig. 6. Fig. 8 shows a cross-sectional view of the outer peripheral region 28 (see Fig. 3), particularly the region covered by the gate finger portion 32.

[0062] Each of the outer peripheral gate trenches 38A, 38B has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating the body region 70. The sidewalls of each of the outer peripheral gate trenches 38A, 38B may extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (the Z-axis direction). In the illustrated example, each of the outer peripheral gate trenches 38A, 38B may have side surfaces that are slightly inclined with respect to the Z-axis direction. In the illustrated example, both ends of the bottom wall of each of the outer peripheral gate trenches 38A, 38B in the X-axis direction are curved, but this is not limited thereto. For example, the bottom wall of each of the outer peripheral gate trenches 38A, 38B may be curved overall, or may have a flat surface that is generally along the XY plane.

[0063] As described above, the gate electrode 62 is also embedded in each of the outer periphery gate trenches 38A, 38B via the insulating layer 60. Because each of the outer periphery gate trenches 38A, 38B has a width greater than that of the inner gate trench 40, the gate insulating film 64 may be formed thicker in each of the outer periphery gate trenches 38A, 38B than in the inner gate trench 40. This allows the gate electrode 62 in the outer periphery gate trench 38 to have the same thickness as the gate electrode 62 in the inner gate trench 40. Note that the gate electrode 62 in each of the outer periphery gate trenches 38A, 38B may have a width greater than or smaller than that of the gate electrode 62 in the inner gate trench 40.

[0064] The gate contact portion 48 extends through the insulating layer 60 (interlayer insulating film 66) located between the gate electrode 62 and the gate finger portion 32, thereby connecting the gate electrode 62 embedded in each outer gate trench portion 38A, 38B to the gate finger portion 32.

[0065] The protective trench 44 can be disposed at a distance from each of the outer periphery gate trench portions 38A, 38B. When multiple protective trenches 44 are provided, the multiple protective trenches 44 can also be disposed at a distance from one another. The protective trench 44 may be disposed outward from the second outer periphery gate trench portion 38B. The protective trench 44 is disposed so as to surround the second outer periphery gate trench portion 38B. In plan view, the protective trench 44 can also be said to be disposed on the opposite side of the second outer periphery gate trench portion 38B from the active region 30. In plan view, the protective trench 44 can also be said to be disposed at a position farther from the active region 30 than the second outer periphery gate trench portion 38B. In other words, in plan view, the second outer periphery gate trench portion 38B can also be said to be disposed closer to the active region 30 than the protective trench 44.

[0066] As shown in the example, the protection trench 44 can have a width that is smaller than that of each of the perimeter gate trench portions 38A, 38B. In another example, the protection trench 44 can have the same width as each of the perimeter gate trench portions 38A, 38B, or it can have a width that is larger than that of each of the perimeter gate trench portions 38A, 38B.

[0067] Also, the protection trench 44 can have the same width as the inner gate trench portion 40 (see FIG. 7 ). In another example, the protection trench 44 can have a width smaller than the inner gate trench portion 40, or a width larger than the inner gate trench portion 40.

[0068] The protective trench 44 has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating the body region 70. The sidewalls of the protective trench 44 may extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (the Z-axis direction). In the illustrated example, the protective trench 44 may have side surfaces that are slightly inclined with respect to the Z-axis direction. In the illustrated example, the bottom wall of the protective trench 44 is formed in an overall curved shape, but this is not limited thereto. For example, the bottom wall of the protective trench 44 may have both ends in the X-axis direction that are curved, or may have a flat surface along the XY plane.

[0069] The semiconductor device 10 may further include a shielding electrode 76 embedded in the protection trench 44 with the insulating layer 60 interposed therebetween. The shielding electrode 76 may be formed of conductive polysilicon, for example. Since the protection trench 44 is formed in a closed ring shape in plan view, the shielding electrode 76 may also be formed in a closed ring shape in plan view.

[0070] The insulating layer 60 may further include a protective insulating film 78 interposed between the shielding electrode 76 and the semiconductor layer 26 and covering the shielding trench 44. The shielding electrode 76 is separated from the semiconductor layer 26 by the protective insulating film 78. The shielding electrode 76 embedded in the shielding trench 44 may not be connected to other metal members (e.g., the gate finger portion 32) and may be in an electrically floating state. In one example, the shielding electrode 76 may have the same width as the gate electrode 62 in the inner gate trench portion 40. Note that the shielding electrode 76 may have a width larger than or smaller than the gate electrode 62 in the inner gate trench portion 40.

[0071] 8, in a region other than the active region 30 (see FIG. 3), the semiconductor layer 26 does not include the source region 72 (see FIG. 7), but includes the drift region 68 and the body region 70. Therefore, in the region shown in FIG. 8, the second surface 26B of the semiconductor layer 26 is included in the body region 70.

[0072] 4, 6, and 8, the configuration between the connection gate trench portion 42 and the protection trench 44 will be described. In the following description, the protection trench 44 that is closest to the second outer periphery gate trench portion 38B among the multiple protection trenches 44 will be referred to as the "end protection trench 44E."

[0073] 4, a first floating trench 52A and a second floating trench 52B are arranged between the connection gate trench portion 42 and the protection trench 44. In the example of FIG. 4, the first floating trench 52A and the second floating trench 52B are arranged alternately with the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B.

[0074] More specifically, the first floating trench 52A is disposed between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B. The first floating trench 52A can also be said to be disposed outward from the first outer periphery gate trench portion 38A. In plan view, the first floating trench 52A can also be said to be disposed on the opposite side of the first outer periphery gate trench portion 38A from the active region 30. In plan view, the first floating trench 52A can also be said to be disposed farther from the active region 30 than the first outer periphery gate trench portion 38A.

[0075] The first floating trench 52A may be positioned closer to the second outer periphery gate trench 38B than to the first outer periphery gate trench 38A. That is, the distance DGF12 between the first floating trench 52A and the second outer periphery gate trench 38B is smaller than the distance DGF11 between the first floating trench 52A and the first outer periphery gate trench 38A. In one example, the distance DGF11 can be 1 μm or more and 10 μm or less. In one example, the distance DGF12 can be 1 μm or more and 4.6 μm or less. The relationship between the distance DGF12 and the distance DGF11 can be changed as desired.

[0076] The second floating trench 52B is disposed outward from the second outer periphery gate trench portion 38B. In plan view, the second floating trench 52B can also be said to be disposed on the opposite side of the second outer periphery gate trench portion 38B from the first floating trench 52A. In one example, the second floating trench 52B may be disposed between the second outer periphery gate trench portion 38B and the edge protection trench 44E. In the example of FIG. 4 , the second floating trench 52B is disposed in the center between the second outer periphery gate trench portion 38B and the edge protection trench 44E. In other words, the distance DGF22 between the second outer periphery gate trench portion 38B and the second floating trench 52B is equal to the distance DFP between the second floating trench 52B and the edge protection trench 44E. In one example, the distance DGF22 can be set to be 1 μm or more and 7 μm or less.

[0077] The position of the second floating trench 52B can be changed as desired between the second outer periphery gate trench portion 38B and the edge protection trench 44E. In one example, the second floating trench 52B may be located closer to the second outer periphery gate trench portion 38B than the edge protection trench 44E. In another example, the second floating trench 52B may be located closer to the edge protection trench 44E than the second outer periphery gate trench portion 38B.

[0078] In the example of FIG. 4, the distance DGF12 is greater than the distance DPP between adjacent protection trenches 44. In one example, the distance DPP is 1 μm. That is, in the example of FIG. 4, the distance DGF12 is greater than 1 μm. In one example, the distance DGF12 is equal to or less than twice the distance DPP. In one example, the distance DGF12 is equal to or less than three times the distance DPP. Note that the distance DGF12 may be equal to the distance DPP or may be smaller than the distance DPP.

[0079] In the example of FIG. 4 , the distance DGF11 is greater than the distance DPP. In one example, the distance DGF11 is two or more times the distance DPP. Note that the relationship between the distance DGF11 and the distance DPP can be changed as desired. In one example, the distance DGF11 is three or more times the distance DPP. In one example, the distance DGF11 is four or more times the distance DPP. In one example, the distance DGF11 is five or more times the distance DPP. In one example, the distance DGF11 is six or more times the distance DPP. In one example, the distance DGF11 is seven or more times the distance DPP. In one example, the distance DGF11 is eight or more times the distance DPP. In one example, the distance DGF11 is nine or more times the distance DPP. In one example, the distance DGF11 is ten or less times the distance DPP.

[0080] The distance DGF11 may be smaller than the distance DGF22 between the second outer periphery gate trench portion 38B and the second floating trench 52B. Furthermore, the distance DGF12 may be smaller than the distance DGF22.

[0081] In another example, the distance DGF11 may be the same as the distance DGF22 or may be greater than the distance DGF22. In yet another example, the distance DGF12 may be the same as the distance DGF22 or may be greater than the distance DGF22.

[0082] The distance DGF11 may be greater than the distance DFP between the second floating trench 52B and the edge protection trench 44E. In another example, the distance DGF11 may be the same as the distance DFP or may be less than the distance DFP.

[0083] The distance DGF22 may be the same as the distance DFP. In another example, the distance DGF22 may be greater than the distance DFP or less than the distance DFP. Both the distance DGF22 and the distance DFP may be greater than the distance DPP.

[0084] The distance DFF between the first floating trench 52A and the second floating trench 52B is greater than the distance DPP between two adjacent protection trenches 44. The distance DFF is greater than the distance DGF12. The distance DFF is greater than the distance DGF11. The distance DFF is greater than the distance DFP.

[0085] The first floating trench 52A may have a shape that surrounds the first outer periphery gate trench portion 38A in a plan view. In one example, the first floating trench 52A may have a similar shape to the first outer periphery gate trench portion 38A in a plan view. The second outer periphery gate trench portion 38B may have a shape that surrounds the first floating trench 52A in a plan view. In one example, the second outer periphery gate trench portion 38B may have a similar shape to the first floating trench 52A in a plan view. Therefore, the first floating trench 52A may have a closed ring shape that includes a shape that follows the recess 20A (see FIG. 2 ) in a plan view.

[0086] The second floating trench 52B may have a shape that surrounds the second outer periphery gate trench portion 38B in a plan view. In one example, the second floating trench 52B may have a shape similar to that of the second outer periphery gate trench portion 38B in a plan view. Therefore, the second floating trench 52B may have a closed ring shape that includes a shape that follows the recess 20A in a plan view.

[0087] Each of the floating trenches 52A, 52B is disposed at a position where it does not overlap with either the gate finger portion 32 or the gate pad portion 34 in a plan view. Furthermore, each of the floating trenches 52A, 52B is disposed at a position where it does not overlap with the source wiring 20 in a plan view. In other words, each of the floating trenches 52A, 52B is disposed between the source wiring 20 and the gate finger portion 32 and the gate pad portion 34 in a plan view.

[0088] 5 and 6, the first floating trench 52A can have the same width as each of the outer gate trench portions 38A, 38B, i.e., the first floating trench 52A can have a width greater than the width of the inner gate trench portion 40 and the width of the protection trench 44.

[0089] In another example, the first floating trench 52A may have a width greater than or less than the respective outer periphery gate trench portions 38A, 38B. In another example, the first floating trench 52A may have a width the same as or less than the inner gate trench portion 40. In another example, the first floating trench 52A may have a width the same as or less than the protection trench 44.

[0090] The second floating trench 52B may have a width smaller than that of each of the outer periphery gate trench portions 38A, 38B. In one example, the second floating trench 52B may have the same width as the inner gate trench portion 40. The second floating trench 52B may have the same width as the protection trench 44. In other words, the width of the second floating trench 52B is smaller than that of the first floating trench 52A. In other words, the width of the first floating trench 52A is larger than that of the second floating trench 52B.

[0091] In another example, the second floating trench 52B may have the same width as the outer periphery gate trench portions 38A, 38B or may have a width greater than the outer periphery gate trench portions 38A, 38B. In another example, the second floating trench 52B may have a width greater than the inner gate trench portion 40 or may have a width smaller than the inner gate trench portion 40. In another example, the second floating trench 52B may have a width greater than the protection trench 44 or may have a width smaller than the protection trench 44.

[0092] 5 and 6, the first floating trench 52A can have the same depth as the second floating trench 52B. Each floating trench 52A, 52B can have the same depth as each outer gate trench portion 38A, 38B. Also, each floating trench 52A, 52B can have the same depth as the inner gate trench portion 40 and the protection trench 44.

[0093] The depth of each floating trench 52A, 52B can be changed as desired. In one example, the first floating trench 52A may be deeper than the second floating trench 52B, or may be shallower than the second floating trench 52B. In another example, each floating trench 52A, 52B may be deeper than the outer periphery gate trench portions 38A, 38B, or may be shallower than the outer periphery gate trench portions 38A, 38B. In another example, each floating trench 52A, 52B may be deeper than the inner gate trench portion 40, or may be shallower than the inner gate trench portion 40. In another example, each floating trench 52A, 52B may be deeper than the protection trench 44, or may be shallower than the protection trench 44.

[0094] As shown in FIG. 8 , the first floating trench 52A has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating the body region 70. The sidewalls of the first floating trench 52A may extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (the Z-axis direction). In the illustrated example, the first floating trench 52A may have side surfaces that are slightly inclined with respect to the Z-axis direction. In the illustrated example, both ends of the bottom wall of the first floating trench 52A in the X-axis direction are curved, but this is not limited thereto. For example, the bottom wall of the first floating trench 52A may be formed in an overall curved shape or may have a flat surface along the XY plane. In the example of FIG. 8 , in the cross-sectional view of FIG. 8 , the first floating trench 52A has the same cross-sectional shape as the cross-sectional shapes of the outer periphery gate trench portions 38A and 38B. The first floating trench 52A may have a cross-sectional shape different from the cross-sectional shapes of the outer periphery gate trench portions 38A, 38B.

[0095] The second floating trench 52B has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating the body region 70. The sidewalls of the second floating trench 52B may extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (the Z-axis direction). In the illustrated example, the second floating trench 52B may have side surfaces that are slightly inclined with respect to the Z-axis direction. In the illustrated example, the bottom wall of the second floating trench 52B is formed into an overall curved shape, but this is not limited thereto. For example, the bottom wall of the second floating trench 52B may have both ends in the X-axis direction that are curved, or may have a flat surface along the XY plane. In the example of FIG. 8, in the cross-sectional view of FIG. 8, the second floating trench 52B has the same cross-sectional shape as the protective trench 44. Note that the second floating trench 52B may have a cross-sectional shape different from the cross-sectional shape of the protective trench 44.

[0096] The semiconductor device 10 may further include a first floating electrode 80A embedded in the first floating trench 52A via an insulating layer 60, and a second floating electrode 80B embedded in the second floating trench 52B via an insulating layer 60. Here, in this embodiment, the first floating electrode 80A corresponds to a "floating electrode."

[0097] In one example, the floating electrodes 80A, 80B can be formed of conductive polysilicon. Since the floating trenches 52A, 52B are formed in a shape similar to that of the outer periphery gate trench portions 38A, 38B in plan view, the floating electrodes 80A, 80B can also be formed in a shape similar to that of the outer periphery gate trench portions 38A, 38B in plan view.

[0098] The insulating layer 60 may further include a first floating insulating film 82A and a second floating insulating film 82B. The first floating insulating film 82A is formed in the first floating trench 52A and interposed between the first floating electrode 80A and the semiconductor layer 26. The second floating insulating film 82B is formed in the second floating trench 52B and interposed between the second floating electrode 80B and the semiconductor layer 26. Therefore, the first floating electrode 80A is separated from the semiconductor layer 26 by the first floating insulating film 82A. The second floating electrode 80B is separated from the semiconductor layer 26 by the second floating insulating film 82B. Each of the floating electrodes 80A, 80B is not connected to another metal member (e.g., the gate finger portion 32) and is in an electrically floating state.

[0099] 8 , the width of the first floating trench 52A is the same as that of each of the outer gate trench portions 38A, 38B, and therefore the thickness of the first floating insulating film 82A is the same as that of the gate insulating film 64 of each of the outer gate trench portions 38A, 38B. On the other hand, the width of the first floating trench 52A is greater than that of the inner gate trench portion 40, and therefore the thickness of the first floating insulating film 82A is greater than that of the gate insulating film 64 of the inner gate trench portion 40.

[0100] Because the width of the second floating trench 52B is smaller than the width of each of the outer gate trench portions 38A, 38B, the thickness of the second floating insulating film 82B is thinner than the thickness of the gate insulating film 64 of each of the outer gate trench portions 38A, 38B. In other words, the thickness of the gate insulating film 64 of each of the outer gate trench portions 38A, 38B is thicker than the thickness of the second floating insulating film 82B. On the other hand, because the width of the second floating trench 52B is the same as the width of the inner gate trench portion 40, the thickness of the second floating insulating film 82B is the same as the thickness of the gate insulating film 64 of the inner gate trench portion 40.

[0101] Since the width of the first floating trench 52A is greater than the width of the second floating trench 52B, the thickness of the first floating insulating film 82A is greater than the thickness of the second floating insulating film 82B.

[0102] The first floating electrode 80A may have the same width as the gate electrodes 62 embedded in each of the outer gate trench portions 38A and 38B. In other words, the first floating electrode 80A may have the same width as the gate electrodes 62 and the protective electrode 76 embedded in the inner gate trench portion 40.

[0103] In another example, the first floating electrode 80A may have a width greater than or less than the gate electrode 62 in each of the outer gate trench portions 38A, 38B. In another example, the first floating electrode 80A may have a width greater than or less than the gate electrode 62 in each of the inner gate trench portions 40. In another example, the first floating electrode 80A may have a width greater than or less than the shielding electrode 76.

[0104] The second floating electrode 80B may have the same width as the gate electrode 62 in each of the outer gate trench portions 38A, 38B. In one example, the second floating electrode 80B may have the same width as the gate electrode 62 in the inner gate trench portion 40. The second floating electrode 80B may have the same width as the shielding electrode 76. The second floating electrode 80B may have the same width as the first floating electrode 80A.

[0105] In another example, the second floating electrode 80B may have a width greater than or less than the gate electrode 62 in each of the outer gate trench portions 38A, 38B. In another example, the second floating electrode 80B may have a width greater than or less than the gate electrode 62 in each of the inner gate trench portions 40. In another example, the second floating electrode 80B may have a width greater than or less than the shielding electrode 76. In another example, the second floating electrode 80B may have a width smaller than the first floating electrode 80A. In other words, the first floating electrode 80A may have a width greater than the second floating electrode 80B. In another example, the second floating electrode 80B may have a width greater than the first floating electrode 80A.

[0106] Next, referring to FIGS. 9 to 11, the positional relationship between the outer gate trench portions 38A, 38B and the floating trenches 52A, 52B, and the drain-source breakdown voltage (BV ＤＳＳ ) and its relationship with

[0107] FIG. 9 shows the relationship between the distance DFP between the second floating trench 52B and the edge protection trench 44E and the drain-source breakdown voltage BV ＤＳＳ As can be seen from FIG. 9, even if the distance DFP is changed, the drain-source breakdown voltage BV ＤＳＳIn the range where the distance DFP is less than 2.16 μm, the drain-source breakdown voltage BV ＤＳＳ As a result, the distance DFP is ＤＳＳ However, the drain-source breakdown voltage BV ＤＳＳ If even a slight decrease in the distance DFP is not acceptable, it is preferable to set the distance DFP to 2.16 μm or more.

[0108] FIG. 10 shows the relationship between the distance DGF11 between the first outer periphery gate trench portion 38A and the first floating trench 52A and the drain-source breakdown voltage BV when the distance DFP is set to 4.16 μm and the distance DGF12 between the second outer periphery gate trench portion 38B and the first floating trench 52A is set to 4 μm. ＤＳＳ 10 is a graph showing the relationship between

[0109] As can be seen from FIG. 10, in the range where the distance DGF11 is 1.56 μm or more and 4.56 μm or less, the drain-source breakdown voltage BV ＤＳＳ In the range where the distance DGF11 is 4.56 μm or more, the drain-source breakdown voltage BV ＤＳＳ is approximately constant. As a result, it is preferable that the distance DGF11 is set to 4.56 μm or more. In this case, the distance DGF11 is greater than the distance DFP.

[0110] FIG. 11 shows the relationship between the distance DGF12 and the drain-source breakdown voltage BV ＤＳＳ 11, the graph indicated by the solid line and black dots plots the relationship between the distance DGF12 and the drain-source breakdown voltage BV when the distance DGF11 is set to 3.56 μm. ＤＳＳ The graph shown by the dashed line and the triangular plot is a graph showing the relationship between the distance DGF12 and the drain-source breakdown voltage BV when the distance DGF11 is set to 2.56 μm. ＤＳＳ 10 is a graph showing the relationship between

[0111] As can be seen from FIG. 11, in both the case where the distance DGF11 is 2.56 μm and the case where the distance DGF11 is 3.56 μm, the drain-source breakdown voltage BV ＤＳＳ In addition, when the distance DGF11 is 3.56 μm, the drain-source breakdown voltage BV is lower than when the distance DGF11 is 2.56 μm. ＤＳＳ As a result, the drain-source breakdown voltage BV ＤＳＳ 10 and 11, it is preferable that the distance DGF11 is large in order to increase the drain-source breakdown voltage BV ＤＳＳ In order to increase the capacitance, it is preferable to arrange the first floating trench 52A closer to the second outer periphery gate trench portion 38B than to the first outer periphery gate trench portion 38A.

[0112] [Operation] The operation of the semiconductor device 10 of this embodiment will be described below. Fig. 12 is a schematic plan view showing a part of the outer periphery region 28 of a semiconductor device of a comparative example (hereinafter referred to as "comparative semiconductor device 10X").

[0113] 12 , the comparative semiconductor device 10X has a configuration in which the first floating trench 52A, the first floating electrode 80A, and the first floating insulating film 82A are omitted from the semiconductor device 10. Due to the omission of these components, the second outer periphery gate trench 38B is positioned closer to the first outer periphery gate trench 38A than the second outer periphery gate trench 38B of the present embodiment.

[0114] 13 is a graph showing the I-V characteristics of the comparative semiconductor device 10X. In FIG. 13, the horizontal axis represents the drain-source voltage VD applied to the drain of the comparative semiconductor device 10X, and the vertical axis represents the current ID flowing through the drain of the comparative semiconductor device 10X. The graph consisting of a solid line and black dot plots shows the results of the first I-V characteristics measurement. The graph consisting of a dot-dash line and triangle plots shows the results of the second I-V characteristics measurement.

[0115] In FIG. 13, the drain-source breakdown voltage BV ＤＳＳis the voltage BVT, while the drain-source breakdown voltage BV ＤＳＳ becomes a voltage BVL lower than the voltage BVT. Therefore, the walk-in phenomenon occurs in the comparative semiconductor device 10X. This is because, for example, the depletion layer spreads in the corner portions where the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B are curved, differently from the depletion layer spread in the straight portions of the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B extending along the X-axis direction or the Y-axis direction. As a result, the drain-source current flows in the corner portions differently from the drain-source current in the straight portions. As a result, the drain-source breakdown voltage BV ＤＳＳ After the first measurement, the breakdown voltage performance of the corner portion becomes lower than that of the straight portion, so the drain-source breakdown voltage BV ＤＳＳ is expected to decrease.

[0116] 14 is a graph showing the I-V characteristics of the semiconductor device 10 of this embodiment. In FIG. 14, the horizontal axis represents the drain-source voltage VD applied to the drain of the semiconductor device 10 of this embodiment, and the vertical axis represents the current ID flowing through the drain of the semiconductor device 10 of this embodiment. The graph consisting of a solid line and black circle plots shows the results of the first I-V characteristics measurement. The graph consisting of a dashed line and triangle plots shows the results of the second I-V characteristics measurement.

[0117] In FIG. 14, the drain-source breakdown voltage BV ＤＳＳ is the voltage BVT, while the drain-source breakdown voltage BV ＤＳＳ becomes a voltage BVH higher than the voltage BVT. Therefore, the walk-out phenomenon occurs in the semiconductor device 10 of this embodiment. In other words, the walk-in phenomenon does not occur in the semiconductor device 10 of this embodiment. This is because the withstand voltage performance of the corner portions where the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B are curved by the first floating trench 52A is lower than the drain-source breakdown voltage BVＤＳＳ It is believed that this prevents the capacitance from decreasing after being measured once. In this way, by forming the first floating trench 52A (first floating electrode 80A) between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B, the occurrence of the walk-in phenomenon can be prevented.

[0118] [Effects] The semiconductor device 10 of this embodiment has the following effects. (1-1) The semiconductor device 10 includes a semiconductor layer 26, a gate trench 36 formed in the semiconductor layer 26, an insulating layer 60 formed on the semiconductor layer 26, a gate electrode 62 embedded in the gate trench 36 with the insulating layer 60 interposed therebetween, and a gate wiring 22 formed on the insulating layer 60 and electrically connected to the gate electrode 62. The semiconductor layer 26 includes a peripheral region 28 that includes the outer edge of the semiconductor layer 26 in a plan view and in which a peripheral gate trench 38 is provided, and an active region 30 surrounded by the peripheral region 28. The peripheral gate trench 38 includes a first peripheral gate trench 38A and a second peripheral gate trench 38B that is provided outward from the first peripheral gate trench 38A. The semiconductor device 10 comprises a first floating trench 52A formed in a region of the semiconductor layer 26 between the first outer gate trench portion 38A and the second outer gate trench portion 38B, and a first floating electrode 80A embedded in the first floating trench 52A via an insulating layer 60 and in an electrically floating state.

[0119] While the walk-in phenomenon occurred in the comparative semiconductor device 10X, which did not include the first floating trench 52A and the first floating electrode 80A, the walk-out phenomenon occurred in the semiconductor device 10 of this embodiment due to the inclusion of the first floating trench 52A and the first floating electrode 80A. Therefore, the semiconductor device 10 of this embodiment can suppress the occurrence of the walk-in phenomenon.

[0120] (1-2) The semiconductor device 10 further includes a protective trench 44 formed in the peripheral region 28. The width of the first floating trench 52A is greater than the width of the protective trench 44. The thickness of the first floating insulating film 82A, which is the portion of the insulating layer 60 formed in the first floating trench 52A, is greater than the thickness of the protective insulating film 78, which is the portion of the insulating layer 60 formed in the protective trench 44.

[0121] With this configuration, the thickness of the first floating insulating film 82A is increased, which can mitigate electric field concentration at the corners formed by bending the first floating trench 52A in plan view, thereby improving the breakdown voltage of the semiconductor device 10.

[0122] (1-3) The first floating trench 52A is disposed closer to the second outer periphery gate trench 38B than to the first outer periphery gate trench 38A. With this configuration, the distance DGF11 between the first floating trench 52A and the first outer periphery gate trench 38A is increased, and the distance DGF12 between the first floating trench 52A and the second outer periphery gate trench 38B is decreased. Therefore, as shown in the graphs of FIGS. 10 and 11, the drain-source breakdown voltage BV ＤＳＳ can be increased.

[0123] (1-4) The width of the first outer gate trench portion 38A and the width of the second outer gate trench portion 38B are greater than the width of the protective trench 44. With this configuration, the gate insulating film 64 formed in each outer gate trench portion 38A, 38B can be made thicker than the protective insulating film 78 formed in the protective trench 44. This makes it possible to mitigate electric field concentration at the corners formed by bending each outer gate trench portion 38A, 38B in plan view. This therefore makes it possible to improve the breakdown voltage of the semiconductor device 10.

[0124] (1-5) The peripheral electrode 24 is spaced apart from the gate wiring 22 and surrounds the gate wiring 22. This configuration can reduce electric field concentration in the area surrounded by the peripheral electrode 24, thereby improving the breakdown voltage of the semiconductor device 10.

[0125] (1-6) The distance DGF22 between the second outer periphery gate trench portion 38B and the second floating trench 52B may be smaller than the distance DGF11 between the first outer periphery gate trench portion 38A and the first floating trench 52A.

[0126] According to this configuration, as shown in the graph of FIG. 9, even if the distance DGF22 is reduced, the drain-source breakdown voltage BV ＤＳＳ Since the distance DGF22 is approximately constant, the semiconductor device 10 can be miniaturized by reducing the distance DGF22, and the drain-source breakdown voltage BV ＤＳＳ This can suppress the decline in

[0127] (1-7) The distance DGF11 between the first outer gate trench portion 38A and the first floating trench 52A may be 4.56 μm or more. According to this configuration, as shown in the graph of FIG. 10, in the range where the distance DGF11 is less than 4.56 μm, the drain-source breakdown voltage BV ＤＳＳ decreases, and when the distance DGF11 is 4.56 μm or more, the drain-source breakdown voltage BV ＤＳＳ Therefore, when the distance DGF11 is 4.56 μm or more, the drain-source breakdown voltage BV ＤＳＳ Furthermore, by setting the distance DGF11 to about 4.56 μm, the drain-source breakdown voltage BV ＤＳＳ Therefore, the semiconductor device 10 can be miniaturized while suppressing the decrease in the capacitance.

[0128] 15 to 20, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the configuration of the outer periphery gate trench portion 38 and the configuration between the connection gate trench portion 42 and the protection trench 44. Below, differences from the semiconductor device 10 according to the first embodiment will be described in detail, and components common to the semiconductor device 10 according to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0129] As shown in FIG. 15 , the semiconductor device 10 of this embodiment includes a perimeter gate trench 90 instead of the perimeter gate trench 38 (see FIG. 4 ). The perimeter gate trench 90 corresponds to the first perimeter gate trench 38A (see FIG. 4 ) of the first embodiment. That is, the semiconductor device 10 of this embodiment does not include the second perimeter gate trench 38B (see FIG. 4 ). The perimeter gate trench 90 is disposed in the perimeter region 28 and is surrounded by the protection trench 44 in plan view. As shown in FIGS. 16 and 17 , the configuration of the perimeter gate trench 90 is the same as the configuration of the first perimeter gate trench 38A. Therefore, components common to the first perimeter gate trench 38A are designated by the same reference numerals and detailed description thereof will be omitted.

[0130] 15 , the gate trench 36 of this embodiment can include an inner gate trench portion 40, a connection gate trench portion 42, and an outer periphery gate trench portion 90. The connection gate trench portion 42 connects the inner gate trench portion 40 and the outer periphery gate trench portion 90.

[0131] The first floating trench 52A and the second floating trench 52B are arranged between the outer periphery gate trench portion 90 and the protection trench 44. The second floating trench 52B is arranged further outward than the first floating trench 52A. It can also be said that the second floating trench 52B is arranged on the opposite side of the first floating trench 52A from the outer periphery gate trench portion 90. In one example, the second floating trench 52B is arranged between the first floating trench 52A and the edge protection trench 44E. The first floating trench 52A is arranged between the outer periphery gate trench portion 90 and the second floating trench 52B.

[0132] 15 , the first floating trench 52A is disposed closer to the second floating trench 52B than the outer periphery gate trench portion 90. That is, the distance DGF between the outer periphery gate trench portion 90 and the first floating trench 52A is greater than the distance DFF between the first floating trench 52A and the second floating trench 52B. In one example, the distance DGF can be set to 2 μm or more and 4.6 μm or less. In another example, the distance DFF can be set to 1 μm or more and 3.7 μm or less.

[0133] In another example, the distance DGF may be smaller than the distance DFF. That is, the first floating trench 52A may be disposed closer to the outer periphery gate trench portion 90 than the second floating trench 52B. In another example, the distance DGF may be the same as the distance DFF.

[0134] Both the distance DGF and the distance DFF may be greater than the distance DPP between two adjacent protection trenches 44. In one example, the distance DGF is greater than or equal to twice the distance DPP. In one example, the distance DGF is greater than or equal to three times the distance DPP. In one example, the distance DGF is less than or equal to four times the distance DPP. Also, in one example, the distance DFF is greater than or equal to twice the distance DPP. In one example, the distance DFF is greater than or equal to three times the distance DPP. In one example, the distance DFF is greater than or equal to four times the distance DPP. In one example, the distance DFF is less than or equal to five times the distance DPP.

[0135] The distance DGF may be greater than the distance DFP between the second floating trench 52B and the edge protection trench 44E. In another example, the distance DGF may be the same as the distance DFP or may be smaller than the distance DFP. Also, the distance DFF may be smaller than the distance DFP. In another example, the distance DFF may be the same as the distance DFP or may be greater than the distance DFP.

[0136] Each of the floating trenches 52A, 52B can have a shape that surrounds the outer periphery gate trench portion 90 in a plan view. In one example, each of the floating trenches 52A, 52B can have a shape similar to that of the outer periphery gate trench portion 90 in a plan view in the outer periphery region 28. Therefore, the first floating trench 52A can have a closed annular shape that includes a shape that follows the recess 20A (see FIG. 2 ) in a plan view.

[0137] Each of the floating trenches 52A, 52B is disposed at a position where it does not overlap with either the gate finger portion 32 or the gate pad portion 34 in a plan view. Furthermore, each of the floating trenches 52A, 52B is disposed at a position where it does not overlap with the source wiring 20 in a plan view. In other words, each of the floating trenches 52A, 52B is disposed between the source wiring 20 and the gate finger portion 32 and the gate pad portion 34 in a plan view.

[0138] 17, a first floating electrode 80A and a first floating insulating film 82A are provided in the first floating trench 52A, as in the first embodiment. A second floating electrode 80B and a second floating insulating film 82B are provided in the second floating trench 52B, as in the first embodiment.

[0139] Next, referring to FIGS. 18 and 19, the positional relationship between the outer gate trench portion 90 and each floating trench 52A, 52B and the drain-source breakdown voltage BV ＤＳＳ The relationship between these two will be explained.

[0140] FIG. 18 shows the relationship between the distance DFF between the first floating trench 52A and the second floating trench 52B and the drain-source breakdown voltage BV ＤＳＳ As can be seen from FIG. 18, as the distance DFF becomes smaller, the drain-source breakdown voltage BV ＤＳＳ As a result, it is preferable that the distance DFF is small within the above-mentioned range of 1 μm or more and 3.7 μm or less.

[0141] FIG. 19 shows the relationship between the distance DGF between the outer gate trench portion 90 and the first floating trench 52A and the drain-source breakdown voltage BV ＤＳＳ 19 is a graph showing the relationship between the distance DGF and the drain-source breakdown voltage BV when the distance DFF is set to 3.72 μm. ＤＳＳ 10 is a graph showing the relationship between

[0142] As can be seen from FIG. 19, as the distance DGF increases, the drain-source breakdown voltage BV ＤＳＳ As a result, the drain-source breakdown voltage BV ＤＳＳ 18 and 19, it is preferable that the distance DGF is large in order to increase the drain-source breakdown voltage BV ＤＳＳ In order to increase the capacitance, it is preferable to arrange the first floating trench 52A closer to the second floating trench 52B than the outer periphery gate trench portion 90.

[0143] 20 is a graph showing the I-V characteristics of the semiconductor device 10 of this embodiment. In FIG. 20, the horizontal axis represents the drain-source voltage VD applied to the drain of the semiconductor device 10 of this embodiment, and the vertical axis represents the current ID flowing through the drain of the semiconductor device 10 of this embodiment. The graph consisting of a solid line and black circle plots shows the results of the first I-V characteristics measurement. The graph consisting of a dashed line and triangle plots shows the results of the second I-V characteristics measurement.

[0144] In FIG. 20, the drain-source breakdown voltage BV ＤＳＳis the voltage BVS, while the drain-source breakdown voltage BV ＤＳＳ becomes a voltage BVU higher than the voltage BVS. Thus, the walk-out phenomenon occurs in the semiconductor device 10 of this embodiment. That is, the walk-in phenomenon does not occur in the semiconductor device 10 of this embodiment. In this way, the first floating trench 52A (first floating electrode 80A) is formed between the outer periphery gate trench portion 90 and the protection trench 44, thereby suppressing the occurrence of the walk-in phenomenon.

[0145] The voltage BVS is the drain-source breakdown voltage BV ＤＳＳ The voltage BVU is lower than the drain-source breakdown voltage BV ＤＳＳ is lower than the voltage BVH.

[0146] [Effects] According to the semiconductor device 10 of this embodiment, in addition to the effect (1-5) of the first embodiment, the following effect can be obtained.

[0147] (2-1) The semiconductor device 10 includes a semiconductor layer 26, a gate trench 36 formed in the semiconductor layer 26, an insulating layer 60 formed on the semiconductor layer 26, a gate electrode 62 embedded in the gate trench 36 with the insulating layer 60 interposed therebetween, a gate wiring 22 formed on the insulating layer 60 and electrically connected to the gate electrode 62, a plurality of protection trenches 44 formed in the semiconductor layer 26, and a protection electrode 76 embedded in the protection trench 44 with the insulating layer 60 interposed therebetween. The semiconductor layer 26 includes a peripheral region 28 that includes the outer edge of the semiconductor layer 26 in a planar view and in which the protection trench 44 is disposed, and an active region 30 surrounded by the peripheral region 28. The gate trench 36 includes a peripheral gate trench portion 90 that is disposed in the peripheral region 28 and is surrounded by the protection trench 44 in a planar view. The semiconductor device 10 includes a first floating trench 52A and a second floating trench 52B formed in a region of the semiconductor layer 26 between the peripheral gate trench portion 90 and the protection trench 44, a first floating electrode 80A embedded in the first floating trench 52A via an insulating layer 60 and in an electrically floating state, and a second floating electrode 80B embedded in the second floating trench 52B via the insulating layer 60 and in an electrically floating state. The first floating trench 52A is located closer to the second floating trench 52B than the peripheral gate trench portion 90.

[0148] 20, the provision of the first floating trench 52A and the first floating electrode 80A causes the walk-out phenomenon to occur. Therefore, the semiconductor device 10 of this embodiment can suppress the occurrence of the walk-in phenomenon.

[0149] (2-2) The width of the first floating trench 52A is greater than the width of the protective trench 44. The thickness of the first floating insulating film 82A, which is the portion of the insulating layer 60 formed in the first floating trench 52A, is greater than the thickness of the protective insulating film 78, which is the portion of the insulating layer 60 formed in the protective trench 44.

[0150] With this configuration, the thickness of the first floating insulating film 82A is increased, which can mitigate electric field concentration at the corners formed by bending the first floating trench 52A in plan view, thereby improving the breakdown voltage of the semiconductor device 10.

[0151] (2-3) The width of the peripheral gate trench portion 90 is greater than the width of the protective trench 44. With this configuration, the gate insulating film 64 formed in the peripheral gate trench portion 90 can be made thicker than the protective insulating film 78 formed in the protective trench 44. This makes it possible to alleviate electric field concentration at the corners formed by bending the peripheral gate trench portion 90 in plan view. This therefore makes it possible to improve the breakdown voltage of the semiconductor device 10.

[0152] <Modifications> The above-described embodiments can be further modified as follows: In each embodiment, the outer periphery gate trench portions 38A, 38B may be formed in the outer periphery region 28 in the shape of a closed ring along the four sides 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26.

[0153] In each embodiment, the protective trench 44 may be formed in the outer circumferential region 28 in a closed ring shape along the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. That is, the protective trench 44 may extend along the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26.

[0154] In each embodiment, the floating trenches 52A, 52B may be formed in the outer periphery region 28 in the shape of a closed ring along the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26.

[0155] In each embodiment, the peripheral electrode 24 may be omitted. In each embodiment, the protective trench 44, the protective electrode 76, and the protective insulating film 78 may be omitted.

[0156] In each embodiment, the position of the gate pad portion 34 can be changed as desired. For example, the gate pad portion 34 may be located at any one of the four corners of the semiconductor layer 26 in plan view.

[0157] In each of the above embodiments, a structure may be adopted in which the conductivity types of the regions in the semiconductor layer 26 are reversed. That is, a p-type region may be an n-type region, and an n-type region may be a p-type region.

[0158] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B."

[0159] As used herein, the term "on" includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0160] Directional terms used herein, such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "forward," "rearward," "sideways," "left," "right," "front," "rear," etc., depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0161] For example, the Z-axis direction used in this specification does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 5 ) are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0162] <Supplementary Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numbers of the corresponding components in the embodiments. The reference numbers are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numbers.

[0163] (Supplementary Note 1) A semiconductor device comprising: a semiconductor layer (26); a gate trench (36) formed in the semiconductor layer (26); an insulating layer (60) formed on the semiconductor layer (26); a gate electrode (62) embedded in the gate trench (36) via the insulating layer (60); and a gate wiring (22) formed on the insulating layer (60) and electrically connected to the gate electrode (62), wherein the semiconductor layer (26) includes a peripheral region (28) including an outer edge of the semiconductor layer (26) in a plan view, and the gate trench (36) includes: a first peripheral gate trench portion (38A) provided in the peripheral region (28); and a second peripheral gate trench portion (38B) provided outward of the first peripheral gate trench portion (38A), a first floating trench (52A) formed in a region of the semiconductor layer (26) between the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B); and a floating electrode (80A) embedded in the first floating trench (52A) via the insulating layer (60) and in an electrically floating state.

[0164] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, further comprising a protective trench (44) provided outward from the second outer peripheral gate trench portion (38B), wherein the width of the first floating trench (52A) is greater than the width of the protective trench (44), and the thickness of a portion (82A) of the insulating layer (60) formed within the first floating trench (52A) is greater than the thickness of a portion (78) of the insulating layer (60) formed within the protective trench (44).

[0165] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the first floating trench (52A) is disposed closer to the second outer periphery gate trench portion (38B) than to the first outer periphery gate trench portion (38A).

[0166] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, further comprising: a protective trench (44) formed in the outer periphery region (28); and a second floating trench (52B) provided between the second outer periphery gate trench portion (38B) and the protective trench (44).

[0167] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein the width of the first floating trench (52A) is greater than the width of the second floating trench (52B), and the thickness of a portion (82A) of the insulating layer (60) formed in the first floating trench (52A) is greater than the thickness of a portion (82B) of the insulating layer (60) formed in the second floating trench (52B).

[0168] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5, further comprising a plurality of protection trenches (44) formed in the outer periphery region (28), wherein a distance (DFF) between the second outer periphery gate trench portion (52B) and the first floating trench (52A) is greater than a distance (DPP) between two adjacent protection trenches (44).

[0169] (Supplementary Note 7) The semiconductor device according to Supplementary Note 4 or 5, wherein a plurality of the protection trenches (44) are provided, and a distance (DGF22) between the second outer periphery gate trench portion (38B) and the second floating trench (52B) is greater than a distance (DPP) between two adjacent protection trenches (44).

[0170] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 4, 5, and 7, wherein a plurality of the protection trenches (44) are provided, the plurality of protection trenches (44) includes an edge protection trench (44E) as a protection trench (44) closer to the second floating trench (52B) among the plurality of protection trenches (44), and a distance (DFP) between the second floating trench (52B) and the edge protection trench (44E) is greater than a distance (DPP) between two adjacent protection trenches (44).

[0171] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the semiconductor layer (26) includes an active region (30) surrounded by the outer periphery region (28), and the gate trench (36) includes: an inner gate trench portion (40) provided in the active region (30); and a connection trench (42) connecting the inner gate trench portion (40) and the first outer periphery gate trench portion (38A).

[0172] (Supplementary Note 10) A semiconductor device comprising: a semiconductor layer (26); a gate trench (36) formed in the semiconductor layer (26); an insulating layer (60) formed on the semiconductor layer (26); a gate electrode (62) embedded in the gate trench (36) via the insulating layer (60); a gate wiring (22) formed on the insulating layer (60) and electrically connected to the gate electrode (62); a plurality of protection trenches (44) formed in the semiconductor layer (26); and a protection electrode (78) embedded in the protection trench (44) via the insulating layer (60); the semiconductor layer (26) includes a peripheral region (28) that includes an outer edge of the semiconductor layer (26) in a planar view and in which the protection trench (44) is disposed; the gate trench (36) includes a peripheral gate trench portion (90) that is disposed in the peripheral region (28) and is surrounded by the protection trench (44) in a planar view; The semiconductor device (10) comprises: a first floating trench (52A) and a second floating trench (52B) formed in a region of the semiconductor layer (26) between the peripheral gate trench portion (90) and the protection trench (44); a first floating electrode (80A) embedded in the first floating trench (52A) via the insulating layer (60) and in an electrically floating state; and a second floating electrode (80B) embedded in the second floating trench (52B) via the insulating layer (60) and in an electrically floating state, wherein the first floating trench (52A) is positioned closer to the second floating trench (52B) than the peripheral gate trench portion (90).

[0173] (Appendix 11) The semiconductor device according to appendix 10, wherein the width of the first floating trench (52A) is greater than the width of the protection trench (44), and the thickness of a portion (82A) of the insulating layer (60) formed in the first floating trench (52A) is greater than the thickness of a portion (78) of the insulating layer (60) formed in the protection trench (44).

[0174] (Appendix 12) The semiconductor device described in Appendix 10 or 11, wherein the width of the outer peripheral gate trench portion (90) is greater than the width of the protection trench (44), and the thickness of the portion (64) of the insulating layer (60) formed in the outer peripheral gate trench portion (90) is greater than the thickness of the portion (78) of the insulating layer (60) formed in the protection trench (44).

[0175] (Appendix 13) The semiconductor device according to any one of Appendices 10 to 12, wherein the width of the first floating trench (52A) is equal to the width of the peripheral gate trench portion (90), and the thickness of a portion (82A) of the insulating layer (60) formed within the first floating trench (52A) is equal to the thickness of a portion (64) of the insulating layer (60) formed within the peripheral gate trench portion (90).

[0176] (Appendix 14) The semiconductor device according to any one of Appendices 10 to 13, wherein the width of the first floating trench (52A) is greater than the width of the second floating trench (52B), and the thickness of a portion (82A) of the insulating layer (60) formed in the first floating trench (52A) is greater than the thickness of a portion (82B) of the insulating layer (60) formed in the second floating trench (52B).

[0177] (Supplementary Note 15) The semiconductor device according to any one of Supplementary Notes 10 to 14, wherein a plurality of the protection trenches (44) are provided, and a distance (DGF) between the outer periphery gate trench portion (90) and the first floating trench (52A) is greater than a distance (DPP) between two adjacent protection trenches (44).

[0178] (Supplementary Note 16) The semiconductor device according to any one of Supplementary Notes 10 to 15, wherein a plurality of the protection trenches (44) are provided, and a distance (DFF) between the first floating trench (52A) and the second floating trench (52B) is greater than a distance (DPP) between two adjacent protection trenches (44).

[0179] (Supplementary Note 17) The semiconductor device according to any one of Supplementary Notes 10 to 16, wherein a plurality of the protection trenches (44) are provided, the plurality of protection trenches (44) includes an edge protection trench (44E) as a protection trench (44) closer to the second floating trench (52B) among the plurality of protection trenches (44), and a distance (DFP) between the second floating trench (52B) and the edge protection trench (44E) is greater than a distance (DPP) between two adjacent protection trenches (44).

[0180] (Supplementary Note 18) The semiconductor device according to any one of Supplementary Notes 10 to 17, wherein the semiconductor layer (26) includes an active region (30), and the gate trench (36) includes: an inner gate trench portion (40) provided in the active region (30); and a connection trench (42) connecting the inner gate trench portion (40) and the outer periphery gate trench portion (90).

[0181] (Supplementary Note 19) The semiconductor device according to any one of Supplementary Notes 2 and 4 to 8, wherein the width of the first outer periphery gate trench portion (38A) and the width of the second outer periphery gate trench portion (38B) are greater than the width of the protection trench (44).

[0182] (Supplementary Note 20) The semiconductor device according to any one of Supplementary Notes 1 to 19, further comprising a peripheral electrode (24) formed on the insulating layer (60) and spaced apart from the gate wiring (22), the peripheral electrode (24) surrounding the gate wiring (22).

[0183] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0184] REFERENCE SIGNS LIST 10...Semiconductor device 10X...Comparative semiconductor device 12...Passivation layer 14, 16...Pad opening 18...Metal layer 20...Source wiring 20A...Recess 22...Gate wiring 24...Peripheral electrode 26...Semiconductor layer 26X1, 26X2, 26Y1, 26Y2...Side 26A...First surface 26B...Second surface 28...Peripheral region 30...Active region 32...Gate finger portion 34...Gate pad portion 36...Gate trench 38...Peripheral gate trench portion 38A...First peripheral gate trench portion 38B...Second peripheral gate trench portion 40...Inner gate trench portion 42...Connection gate trench portion 44...Protection trench 44E...End protection trench 46...Source contact portion 48...Gate contact portion 50...Peripheral contact portion 52A...First floating trench 52B...Second floating trench 54...Semiconductor substrate 56...Epitaxial layer 58...Drain electrode 60...Insulating layer 62...Gate electrode 64...Gate insulating film 66...Interlayer insulating film 68...Drift region 70...Body region 72...Source region 74...Contact region 76...Protective electrode 78...Protective insulating film 80A...First floating electrode 80B...Second floating electrode 82A...First floating insulating film 82B...Second floating insulating film 90...Peripheral gate trench portion DGF11...Distance between first peripheral gate trench portion and first floating trench DGF12...Distance between second peripheral gate trench portion and first floating trench DGF22...Distance between second peripheral gate trench portion and second floating trench DFP...Distance between second floating trench and end protective trench DPP...Distance between two adjacent protective trenches DGF: distance between the outer gate trench portion and the first floating trench DFF: distance between the first floating trench and the second floating trench

Claims

1. A semiconductor layer; a gate trench formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a gate electrode embedded in the gate trench via the insulating layer; a gate wiring formed on the insulating layer and electrically connected to the gate electrode; Equipped with the semiconductor layer includes a peripheral region including an outer edge of the semiconductor layer in a plan view, The gate trench is a first outer periphery gate trench portion provided in the outer periphery region; a second outer periphery gate trench portion provided outwardly of the first outer periphery gate trench portion, a first floating trench formed in a region of the semiconductor layer between the first outer periphery gate trench portion and the second outer periphery gate trench portion; a floating electrode embedded in the first floating trench via the insulating layer and in an electrically floating state; Semiconductor device.

2. The semiconductor device further includes a protection trench provided outside the second outer periphery gate trench portion, The width of the first floating trench is greater than the width of the protection trench; The thickness of the insulating layer in the first floating trench is greater than the thickness of the insulating layer in the protection trench. The semiconductor device according to claim 1 .

3. The first floating trench is disposed closer to the second outer periphery gate trench portion than to the first outer periphery gate trench portion. The semiconductor device according to claim 1 .

4. a protective trench formed in the outer periphery region; a second floating trench provided between the second outer periphery gate trench portion and the protection trench. The semiconductor device according to claim 1 .

5. The width of the first floating trench is greater than the width of the second floating trench; A thickness of the insulating layer in the first floating trench is greater than a thickness of the insulating layer in the second floating trench. The semiconductor device according to claim 4.

6. further comprising a plurality of protection trenches formed in the perimeter region; The distance between the second floating trench and the first floating trench is greater than the distance between two adjacent protection trenches. The semiconductor device according to claim 1 .

7. The protection trench is provided in plurality, The distance between the second outer periphery gate trench portion and the second floating trench is greater than the distance between two adjacent protection trenches. The semiconductor device according to claim 4.

8. The protection trench is provided in plurality, The plurality of protection trenches include 2. Including an end protection trench as a protection trench closer to the floating trench; The distance between the second floating trench and the edge protection trench is greater than the distance between two adjacent protection trenches. The semiconductor device according to claim 4.

9. the semiconductor layer includes an active region surrounded by the peripheral region, The gate trench is an inner gate trench portion provided in the active region; a connection trench connecting the inner gate trench portion and the first outer periphery gate trench portion. The semiconductor device according to any one of claims 1 to 8.

10. A semiconductor layer; a gate trench formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a gate electrode embedded in the gate trench via the insulating layer; a gate wiring formed on the insulating layer and electrically connected to the gate electrode; a protection trench formed in the semiconductor layer; a protection electrode embedded in the protection trench via the insulating layer; Equipped with the semiconductor layer includes a peripheral region that includes an outer edge of the semiconductor layer in a plan view and in which the protection trench is disposed, the gate trench includes a peripheral gate trench portion that is disposed in the peripheral region and is surrounded by the protection trench in a plan view; a first floating trench and a second floating trench formed in a region of the semiconductor layer between the outer periphery gate trench portion and the protection trench; a first floating electrode embedded in the first floating trench via the insulating layer and in an electrically floating state; a second floating electrode embedded in the second floating trench via the insulating layer and in an electrically floating state; The first floating trench is disposed closer to the second floating trench than the outer periphery gate trench portion. Semiconductor device.

11. The width of the first floating trench is greater than the width of the protection trench; The thickness of the insulating layer in the first floating trench is greater than the thickness of the insulating layer in the protection trench. The semiconductor device according to claim 10.

12. The width of the outer periphery gate trench portion is greater than the width of the protection trench, The thickness of the insulating layer in the outer periphery gate trench portion is greater than the thickness of the insulating layer in the protection trench portion. The semiconductor device according to claim 10.

13. The width of the first floating trench is equal to the width of the outer periphery gate trench portion, The thickness of the insulating layer in the first floating trench is equal to the thickness of the insulating layer in the outer periphery gate trench portion. The semiconductor device according to claim 10.

14. The width of the first floating trench is greater than the width of the second floating trench; A thickness of the insulating layer in the first floating trench is greater than a thickness of the insulating layer in the second floating trench. The semiconductor device according to claim 10.

15. The protection trench is provided in plurality, The distance between the outer periphery gate trench portion and the first floating trench is greater than the distance between two adjacent protection trenches. The semiconductor device according to claim 10.

16. The protection trench is provided in plurality, The distance between the first floating trench and the second floating trench is greater than the distance between two adjacent protection trenches. The semiconductor device according to claim 10.

17. The protection trench is provided in plurality, the plurality of protection trenches include an end protection trench as a protection trench closer to the second floating trench among the plurality of protection trenches, The distance between the second floating trench and the edge protection trench is greater than the distance between two adjacent protection trenches. The semiconductor device according to claim 10.

18. the semiconductor layer includes an active region; The gate trench is an inner gate trench portion provided in the active region; a connection trench connecting the inner gate trench portion and the outer periphery gate trench portion. The semiconductor device according to any one of claims 10 to 17.