Semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device comprises: a first conductor; a second conductor that is above the first conductor; a third conductor that contacts an upper surface of the second conductor; a fourth conductor that is above the third conductor; a fifth conductor that is above the second conductor and the fourth conductor; first and second oxides; and fourth and fifth insulators. The fourth insulator and the first oxide are disposed inside a first opening provided in the fourth conductor and the like. The first oxide has a region that is opposite from the fourth conductor with the fourth insulator therebetween, a region that contacts an upper surface of the third conductor, and a region that contacts a lower surface of the fifth conductor. The fifth insulator and the second oxide are disposed inside a second opening that is provided in the second conductor and the like. The second oxide has a region that is opposite from the second conductor with the fifth insulator therebetween, a region that contacts an upper surface of the first conductor, and a region that contacts the lower surface of the fifth conductor.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic units, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing unit (CPU), and memory (storage device) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as the amount of data handled increases, semiconductor devices with larger storage capacities are required. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors.

[0006] Furthermore, miniaturization of transistors included in semiconductor devices has been progressing in order to increase the storage capacity of the semiconductor devices. To achieve miniaturization of transistors, research into vertical structure transistors has been actively conducted. For example, Non-Patent Documents 2 and 3 disclose vertical structure transistors having a metal oxide in a region where a channel is formed (also referred to as a channel formation region).

[0007] International Publication No. 2021 / 053473

[0008] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53X. Duan et al. , “Novel Vertical Channel-All-Around (CAA) IGZO FETs for 2T0C DRAM with High Density beyond 4F▲2▼ by Monolithic Stacking”, IEDM Tech. Dig. , 2021, pp. 222-225H. Fujiwara et al. , “Surrounding Gate Vertical-Channel FET with Gate Length of 40nm Using BEOL Compatible High-Thermal-Tolerance In-Al-Zn Oxide Channel”, 2020 Symposium on VLSI Technology, TH2.2

[0009] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with large on-state current.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.An object of one embodiment of the present invention is to provide a storage device with a small occupation area.An object of one embodiment of the present invention is to provide a storage device with high reliability.An object of one embodiment of the present invention is to provide a storage device with low power consumption.An object of one embodiment of the present invention is to provide a novel storage device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including a first conductor, a first insulator on the first conductor, a second conductor on the first insulator, a third conductor on the second conductor, a second insulator on the first insulator, and the third conductor, a fourth conductor on the second insulator, a third insulator on the fourth conductor, a fifth conductor on the third insulator, a first oxide, a second oxide, a fourth insulator, and a fifth insulator. A first opening reaching the third conductor is provided in the second insulator, the fourth conductor, and the third insulator. The fourth insulator has a region in contact with a side surface of the fourth conductor in the first opening. The first oxide has a region facing the fourth conductor via the fourth insulator, a region in contact with at least a portion of the upper surface of the third conductor, and a region in contact with at least a portion of the lower surface of the fifth conductor. A second opening reaching the first conductor is provided in the first insulator, the second conductor, the second insulator, and the third insulator. The fifth insulator has a region in contact with a side surface of the second conductor in the second opening. The second oxide has a region facing the second conductor via the fifth insulator, a region in contact with at least a portion of the upper surface of the first conductor, and a region in contact with at least a portion of the lower surface of the fifth conductor.

[0013] In the semiconductor device, the direction in which the fourth conductor extends is preferably parallel to the direction in which the first conductor extends.

[0014] In the semiconductor device, the second opening preferably has a larger diameter than the first opening in a plan view.

[0015] In addition, in a cross-sectional view of the semiconductor device, the sidewalls of the first opening and the sidewalls of the second opening preferably have a tapered shape.

[0016] One embodiment of the present invention is a semiconductor device including a first insulator, a first conductor and a second conductor on the first insulator, a second insulator on the first insulator, the first conductor, and the second conductor, a third conductor on the second insulator, a fourth conductor on the third conductor, a third insulator on the second insulator, the third conductor, and the fourth conductor, a fifth conductor on the third insulator, a fourth insulator on the fifth conductor, a sixth conductor on the fourth insulator, a first oxide, a second oxide, a fifth insulator, and a sixth insulator. The first conductor has a region overlapping with the third conductor via the second insulator. A first opening reaching the fourth conductor is provided in the third insulator, the fifth conductor, and the fourth insulator. The fifth insulator has a region in contact with a side surface of the fifth conductor in the first opening. The first oxide has a region facing the fifth conductor via the fifth insulator, a region in contact with at least a portion of the upper surface of the fourth conductor, and a region in contact with at least a portion of the lower surface of the sixth conductor. A second opening reaching the second conductor is provided in the second insulator, the third conductor, the third insulator, and the fourth insulator. The sixth insulator has a region in contact with a side surface of the third conductor in the second opening. The second oxide has a region facing the third conductor via the sixth insulator, a region in contact with at least a portion of the upper surface of the second conductor, and a region in contact with at least a portion of the lower surface of the sixth conductor.

[0017] In the above semiconductor device, it is preferable that the direction in which the first conductor extends is parallel to the direction in which the second conductor extends, and the direction in which the fifth conductor extends is parallel to the direction in which the second conductor extends.

[0018] In the semiconductor device, the first conductor is preferably provided in the same layer as the second conductor.

[0019] One embodiment of the present invention is a semiconductor device including a first insulator, a first conductor and a second conductor on the first insulator, a second insulator on the first insulator, the first conductor, and the second conductor, a third conductor on the second insulator, a fourth conductor on the third conductor, a third insulator on the second insulator, the third conductor, and the fourth conductor, a fifth conductor on the third insulator, a fourth insulator on the fifth conductor, a sixth conductor and a seventh conductor on the fourth insulator, a first oxide, a second oxide, a fifth insulator, and a sixth insulator. The first conductor has a region overlapping with the third conductor via the second insulator. A first opening reaching the fourth conductor is provided in the third insulator, the fifth conductor, and the fourth insulator. The fifth insulator has a region in contact with a side surface of the fifth conductor in the first opening. The first oxide has a region facing the fifth conductor via the fifth insulator, a region in contact with at least a portion of the upper surface of the fourth conductor, and a region in contact with at least a portion of the lower surface of the sixth conductor. A second opening reaching the second conductor is provided in the second insulator, the third conductor, the third insulator, and the fourth insulator. The sixth insulator has a region in contact with a side surface of the third conductor in the second opening. The second oxide has a region facing the third conductor via the sixth insulator, a region in contact with at least a portion of the upper surface of the second conductor, and a region in contact with at least a portion of the lower surface of the seventh conductor.

[0020] In the above semiconductor device, it is preferable that the direction in which the first conductor extends is parallel to the direction in which the second conductor extends, the direction in which the fifth conductor extends is parallel to the direction in which the second conductor extends, and the direction in which the sixth conductor extends is parallel to the direction in which the seventh conductor extends.

[0021] In the semiconductor device, it is preferable that the first conductor is provided in the same layer as the second conductor, and the sixth conductor is provided in the same layer as the seventh conductor.

[0022] In addition, in the above semiconductor device, it is preferable that the metal oxide contains two or three elements selected from indium, an element M, and zinc, and that the element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0023] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in the electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0024] According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a small occupation area can be provided. According to one embodiment of the present invention, a storage device with high reliability can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel storage device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIG. 1A is a perspective view showing a configuration example of a semiconductor device. FIG. 1B is a top view showing a configuration example of a semiconductor device. FIG. 2A is a top view showing a configuration example of a semiconductor device. FIGS. 2B to 2D are cross-sectional views showing a configuration example of a semiconductor device. FIG. 2E is a circuit diagram for explaining a configuration of a semiconductor device. FIG. 3A is a top view showing a configuration example of a semiconductor device. FIGS. 3B to 3D are cross-sectional views showing a configuration example of a semiconductor device. FIG. 4A is a top view showing a configuration example of a semiconductor device. FIGS. 4B to 4D are cross-sectional views showing a configuration example of a semiconductor device. FIG. 5A is a top view showing a configuration example of a semiconductor device. FIGS. 5B to 5D are cross-sectional views showing a configuration example of a semiconductor device. FIG. 6A is a top view showing a configuration example of a semiconductor device. FIGS. 6B to 6D are cross-sectional views showing a configuration example of a semiconductor device. FIG. 7A is a top view showing a configuration example of a semiconductor device. FIGS. 7B to 7D are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 8A and 8B are top views showing a configuration example of a semiconductor device. FIG. 9A is a top view showing a configuration example of a semiconductor device. 9B to 9D are cross-sectional views showing a structural example of a semiconductor device. FIG. 9E is a circuit diagram illustrating a structure of a semiconductor device. FIG. 10A is a top view showing a structural example of a semiconductor device. FIGS. 10B to 10D are cross-sectional views showing a structural example of a semiconductor device. FIG. 10E is a circuit diagram illustrating a structure of a semiconductor device. FIG. 11A is a top view showing a structural example of a semiconductor device. FIGS. 11B to 11D are cross-sectional views showing a structural example of a semiconductor device. FIG. 12A is a top view showing a structural example of a semiconductor device. FIGS. 12B to 12D are cross-sectional views showing a structural example of a semiconductor device. FIG. 12E is a circuit diagram illustrating a structure of a semiconductor device. FIG. 13A is a top view showing a structural example of a semiconductor device. FIGS. 13B to 13D are cross-sectional views showing a structural example of a semiconductor device. FIG. 13E is a circuit diagram illustrating a structure of a semiconductor device. FIGS. 14A, 14C, and 14E are top views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B, 14D, and 14F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 15A and 15C are top views illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 15B and 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.16A and 16C are top views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16B and 16D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 17A is a block diagram illustrating an example of a configuration of a memory device. FIG. 17B is a perspective view illustrating an example of a configuration of a memory device. FIGS. 18A to 18E are circuit diagrams illustrating an example of a configuration of a memory cell. FIGS. 18F and 18G are perspective views illustrating an example of a configuration of a memory device. FIG. 19 is a cross-sectional view illustrating an example of a configuration of a memory device. FIG. 20 is a cross-sectional view illustrating an example of a configuration of a memory device. FIGS. 21A to 21E are diagrams for explaining an example of a memory device. FIGS. 22A and 22B are diagrams illustrating an example of an electronic component. FIGS. 23A and 23B are diagrams illustrating an example of electronic equipment, and FIGS. 23C to 23E are diagrams illustrating an example of a mainframe computer. FIG. 24 is a diagram illustrating an example of space equipment. FIG. 25 is a diagram illustrating an example of a storage system applicable to a data center.

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0028] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, they are not necessarily limited to the scale. Note that the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may unintentionally be thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions in different drawings, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular symbol may be assigned.

[0029] In particular, in perspective views or top views (also called "plan views"), some components may be omitted to facilitate understanding of the invention. Also, some hidden lines may be omitted. Drawings may also omit notations such as hatching patterns. For the same component, the hatching pattern in the top view may differ from the hatching pattern in the cross-sectional view.

[0030] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number assigned to a component in one part of this specification may not match an ordinal number assigned to the same component in another part of this specification or in the claims.

[0031] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0033] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0034] In this specification, terms indicating position, such as "above," "below," "upward," or "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in this specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located above a conductor" can be rephrased as "insulator located below a conductor" by rotating the orientation of the drawing 180 degrees.

[0035] In this specification, "equal heights" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a chemical mechanical polishing (CMP) process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces treated by the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the treated surface during the CMP process. In this specification, this case is also considered to be "equal heights." For example, when there are two layers (here, a first layer and a second layer) having different heights relative to the reference surface, and the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "equal heights."

[0036] In this specification, "edges coincide" means that at least a portion of the contours of stacked layers overlap when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges coincide" is also used.

[0037] Generally, it is difficult to clearly distinguish between an "exact match" and an "approximate match." For this reason, in this specification, "match" includes both an exact match and an approximate match.

[0038] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0039] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described with reference to drawings.

[0040] One embodiment of the present invention relates to a semiconductor device provided over a substrate. The semiconductor device includes a first transistor and a second transistor, which can form a memory cell. The semiconductor device of one embodiment of the present invention has a function of storing data because it includes a memory cell. Thus, the semiconductor device of one embodiment of the present invention can be referred to as a memory device. Note that the semiconductor device of one embodiment of the present invention may further include a capacitor, or may further include a third transistor and a capacitor.

[0041] The semiconductor device of one embodiment of the present invention preferably includes a transistor including an oxide semiconductor (OS transistor) in a channel formation region. The off-state current of an OS transistor is low. Therefore, by using an OS transistor in a semiconductor device that can be used as a memory device, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the semiconductor device can be sufficiently reduced. Therefore, a semiconductor device with low power consumption can be provided. Furthermore, the high frequency characteristics of an OS transistor enable the semiconductor device to read and write data at high speed. Therefore, a semiconductor device with high operating speed can be provided.

[0042] Each of the first transistor and the second transistor has a configuration in which one of the source electrode and the drain electrode is located below and the other is located above, so that current flows vertically. In other words, the channel length direction of the first transistor and the second transistor is vertical. That is, the first transistor and the second transistor are vertically structured transistors. Compared to a so-called horizontally structured transistor in which current flows horizontally, a vertically structured transistor can be miniaturized. Therefore, by using a vertical structure for the first transistor and the second transistor, the transistors can be arranged at high density, thereby achieving high integration in a semiconductor device. Furthermore, compared to a horizontally structured transistor, a vertically structured transistor can have a larger channel width per unit area. Therefore, the current density flowing through the transistor is increased, the on-current of the transistor is increased, and frequency characteristics are improved.

[0043] Furthermore, OS transistors are resistant to the short-channel effect. Therefore, compared with transistors having silicon in their channel formation regions (also referred to as Si transistors), OS transistors are less susceptible to the floating substrate effect even when they have a vertical structure, and their channel length can be easily shortened even when their gate insulating film is thick. In other words, the gate leakage current can be reduced, thereby improving the retention characteristics of a memory device.

[0044] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Examples of short-channel effects include drain-induced barrier lowering, electron velocity saturation, and hot carrier degradation. Specific examples of short-channel effects include a decrease in threshold voltage, an increase in subthreshold swing, and an increase in leakage current. Here, the subthreshold swing refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0045] Furthermore, since the channel length of a vertical transistor can be controlled by the thickness of the film between the source and drain electrodes, the processing variation of the channel length can be reduced compared to a horizontal transistor. In other words, the variation of the current density flowing through the transistor can be suppressed, and the frequency characteristics can be improved.

[0046] Furthermore, when a memory cell is formed using a first transistor and a second transistor, one of the first transistor and the second transistor functions as a write transistor, and the other functions as a read transistor. The read transistor preferably has high on-state current characteristics. The write transistor preferably has low off-state current characteristics. That is, to manufacture a memory device with excellent performance, it is desirable to separately manufacture transistors to have required characteristics. The first transistor and the second transistor, which are vertical transistors, can adjust the channel width related to the on-state current of the transistor by changing the size (also referred to as diameter) of an opening in which a part of the transistor's components is provided in a plan view (also referred to as top view). Therefore, by differentiating the opening in which a part of the first transistor's components is provided from the opening in which a part of the second transistor's components is provided, a memory device with excellent performance can be manufactured.

[0047] Furthermore, the semiconductor device according to one embodiment of the present invention has a structure in which one of the source electrode and the drain electrode of the first transistor is directly connected to the gate electrode of the second transistor. Therefore, there is no need to provide an electrode for connecting one of the source electrode and the drain electrode of the first transistor to the gate electrode of the second transistor, and a memory cell can be formed without reducing the transistor density. Therefore, the degree of integration of the memory cell can be increased, and the memory capacity can be increased. Furthermore, the number of steps in the manufacturing process of the semiconductor device can be reduced.

[0048] <Structural Example of Semiconductor Device> A structural example of a semiconductor device according to one embodiment of the present invention will be described below. Note that each of the components included in the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0049] 1A and 1B are a perspective view and a top view illustrating a structural example of a semiconductor device according to one embodiment of the present invention, respectively. Fig. 1A is a perspective view of a semiconductor device 10, and Fig. 1B is a top view of the semiconductor device 10.

[0050] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0051] The semiconductor device 10 has a plurality of memory cells 100. Fig. 1A shows an example in which the semiconductor device 10 has a plurality of memory cells 100 arranged in a matrix of m rows and n columns (m and n are each independently an integer of 2 or greater). By arranging the memory cells 100 in a matrix, a memory cell array can be configured.

[0052] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction is referred to as the "rows" and the Y direction is referred to as the "columns." Alternatively, the X direction may be referred to as the "columns" and the Y direction may be referred to as the "rows."

[0053] 1A, the memory cell 100 in the first row and first column is designated as memory cell 100[1,1], the memory cell 100 in the second row and first column is designated as memory cell 100[2,1], and the memory cell 100 in the mth row and first column is designated as memory cell 100[m,1]. Also, the memory cell 100 in the first row and second column is designated as memory cell 100[1,2], and the memory cell 100 in the first row and nth column is designated as memory cell 100[1,n]. Also, the memory cell 100 in the mth row and nth column is designated as memory cell 100[m,n].

[0054] Furthermore, in the present embodiment and the like, an arbitrary row may be referred to as row i. An arbitrary column may be referred to as column j. Thus, i is an integer between 1 and m, and j is an integer between 1 and n. Furthermore, in the present embodiment and the like, the memory cell 100 in the i-th row and j-th column is referred to as memory cell 100[i, j]. Note that in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is used, "j+α" is not less than 1 and does not exceed n.

[0055] The semiconductor device 10 also has m conductors 262 extending in the row direction, m conductors 242 extending in the row direction, and n conductors 246 extending in the column direction. In this embodiment and the like, the i-th conductor 262 (i-th row) is referred to as conductor 262[i], and the i-th conductor 242 (i-th row) is referred to as conductor 242[i]. Similarly, the j-th conductor 246 (j-th column) is referred to as conductor 246[j].

[0056] Memory cell 100[i,j] is electrically connected to each of conductor 262[i], conductor 242[i], and conductor 246[j]. In other words, conductor 262[i] is electrically connected to n memory cells (memory cell 100[i,1] to memory cell 100[i,n]), conductor 242[i] is electrically connected to n memory cells (memory cell 100[i,1] to memory cell 100[i,n]), and conductor 246[j] is electrically connected to m memory cells (memory cell 100[1,j] to memory cell 100[m,j]).

[0057] Hereinafter, the conductor 262 refers to one or more of the conductors 262[1] to 262[m], and the conductor 242 refers to one or more of the conductors 242[1] to 242[m]. Similarly, the conductor 246 refers to one or more of the conductors 246[1] to 246[n]. Similarly, the memory cell 100 refers to one or more of the memory cells 100[1,1] to 100[m,n].

[0058] The conductor 262, the conductor 242, and the conductor 246 function as wiring. When the semiconductor device 10 is used as a memory device, the direction in which the conductor 262 extends is preferably different from the direction in which the conductor 246 extends, and more preferably perpendicular to the direction in which the conductor 246 extends. Furthermore, the direction in which the conductor 242 extends is preferably different from the direction in which the conductor 246 extends, and more preferably perpendicular to the direction in which the conductor 242 extends.

[0059] [Memory Cell 100] Figures 2A to 2D are top views and cross-sectional views illustrating a configuration example of a memory cell included in a semiconductor device of one embodiment of the present invention. Figure 2A is a top view of the memory cell 100. Figure 2B is a cross-sectional view of the memory cell 100, also a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in Figure 2A. Figure 2C is a cross-sectional view of the memory cell 100, also a cross-sectional view of a portion indicated by a dashed dotted line B1-B2 in Figure 2A. Figure 2D is a cross-sectional view of the memory cell 100, also a cross-sectional view of a portion indicated by a dashed dotted line B3-B4 in Figure 2A. Note that some elements are omitted from the top view in Figure 2A for clarity.

[0060] Since the memory cells 100[1,1] to 100[m,n] have the same configuration, they are represented as memory cells 100 in FIG. 2A and other figures, and no identifying symbols are added.

[0061] As shown in Figures 2A to 2D, a semiconductor device of one embodiment of the present invention has an insulator 212 on a substrate (not shown), a memory cell 100 on the insulator 212, an insulator 270 on the insulator 212, an insulator 272 on the insulator 270, and an insulator 274 on the insulator 272.

[0062] 2A to 2D includes a transistor 200a and a transistor 200b. The transistors 200a and 200b are provided over an insulator 212.

[0063] The transistor 200a includes an oxide 230a, an insulator 250a, a conductor 244, a conductor 262 on the conductor 244, and a conductor 246 on the conductor 262. The insulator 272 has a region located between the conductor 244 and the conductor 262, and the insulator 274 has a region located between the conductor 262 and the conductor 246.

[0064] The insulator 272, the conductor 262, and the insulator 274 have first openings that reach the conductor 244. The first openings have regions that overlap with the conductor 244 in a planar view. It can be said that the first openings include an opening in the insulator 272, an opening in the conductor 262, and an opening in the insulator 274. It can also be said that the conductor 262 has an opening that overlaps with the conductor 244 in a planar view.

[0065] An insulator 250a and an oxide 230a are arranged inside the first opening. The insulator 250a has a region that contacts the side surface of the conductor 262 in the first opening. The insulator 250a also has a region that contacts the side surface of the insulator 272 in the first opening and a region that contacts the side surface of the insulator 274 in the first opening. The insulator 250a has a region that contacts the side surface of the oxide 230a, a region that contacts the side surface of the conductor 262, a region that contacts at least a portion of the side surface of the insulator 272, and a region that contacts at least a portion of the side surface of the insulator 274. The insulator 250a can be said to have a cylindrical shape with a hollow portion. The oxide 230a is provided so as to fill the first opening via the insulator 250a. The oxide 230a has a region in contact with the side surface of the insulator 250a, a region in contact with at least a portion of the upper surface of the conductor 244, and a region in contact with at least a portion of the lower surface of the conductor 246. The oxide 230a has a region facing the conductor 262 with the insulator 250a interposed therebetween.

[0066] 2A shows a configuration in which the top surface shape of the first opening where the oxide 230a and the insulator 250a are provided has a circular shape, but the present invention is not limited to this. For example, the top surface shape of the first opening may be an ellipse, a polygon, or a polygon with rounded corners. Here, a polygonal shape refers to a triangle, a rectangle, a pentagon, a hexagon, etc.

[0067] The conductor 262 has a region that functions as the gate electrode of the transistor 200a. The insulator 250a has a region that functions as the gate insulator of the transistor 200a. Note that a gate insulator may also be referred to as a gate insulating layer or a gate insulating film. The conductor 244 has a region that functions as one of the source electrode and drain electrode of the transistor 200a. The conductor 246 has a region that functions as the other of the source electrode and drain electrode of the transistor 200a. A region of the oxide 230a that faces the conductor 262 with the insulator 250a interposed therebetween functions as a channel formation region of the transistor 200a.

[0068] The transistor 200b includes an oxide 230b, an insulator 250b, a conductor 242, a conductor 260 on the conductor 242, and a conductor 246 on the conductor 260. The insulator 270 has a region located between the conductor 242 and the conductor 260, and the insulators 272 and 274 have regions located between the conductor 260 and the conductor 246.

[0069] Second openings reaching the conductor 242 are provided in the insulator 270, the conductor 260, the insulator 272, and the insulator 274. The second openings have regions that overlap with the conductor 242 in a planar view. The second openings can be said to include an opening in the insulator 270, an opening in the conductor 260, an opening in the insulator 272, and an opening in the insulator 274. The conductor 260 can also be said to have an opening that overlaps with the conductor 242 in a planar view.

[0070] An insulator 250b and an oxide 230b are arranged inside the second opening. The insulator 250b has a region that contacts the side surface of the conductor 260 in the second opening. The insulator 250b also has a region that contacts the side surface of the insulator 270 in the second opening, a region that contacts the side surface of the insulator 272 in the second opening, and a region that contacts the side surface of the insulator 274 in the second opening. The insulator 250b has a region that contacts the side surface of the oxide 230b, a region that contacts the side surface of the conductor 260, a region that contacts at least a portion of the side surface of the insulator 270, a region that contacts at least a portion of the side surface of the insulator 272, and a region that contacts at least a portion of the side surface of the insulator 274. The insulator 250b can be said to have a cylindrical shape with a hollow portion. The oxide 230b is provided so as to fill the second opening with the insulator 250b interposed therebetween. The oxide 230b has a region in contact with the side surface of the insulator 250b, a region in contact with at least a portion of the upper surface of the conductor 242, and a region in contact with at least a portion of the lower surface of the conductor 246. The oxide 230b has a region facing the conductor 260 with the insulator 250b interposed therebetween.

[0071] 2A shows the second opening, in which the oxide 230b and the insulator 250b are provided, as having a circular top view, but the present invention is not limited thereto. For example, the top view of the opening may be an ellipse, a polygon, or a polygon with rounded corners.

[0072] The conductor 260 has a region that functions as the gate electrode of the transistor 200b. The insulator 250b has a region that functions as the gate insulator of the transistor 200b. The conductor 242 has a region that functions as one of the source electrode and drain electrode of the transistor 200b. The conductor 246 has a region that functions as the other of the source electrode and drain electrode of the transistor 200b. A region of the oxide 230b that faces the conductor 260 with the insulator 250b interposed therebetween functions as a channel formation region of the transistor 200b.

[0073] Hereinafter, when describing matters common to components distinguished by alphabets, the components may be described using symbols without the alphabet. For example, when describing matters common to transistors 200a and 200b, the transistor may be referred to as transistor 200. When describing matters common to oxides 230a and 230b, the oxide may be referred to as oxide 230. When describing matters common to insulators 250a and 250b, the insulator may be referred to as insulator 250.

[0074] The transistor 200 is a so-called vertical transistor in which one of the source electrode and the drain electrode is located below the channel formation region and the other is located above the channel formation region, allowing current to flow vertically. The transistor 200 also has a structure in which the gate electrode surrounds the channel formation region. Therefore, the transistor 200 can be said to be a transistor with a GAA (Gate-All-Around) structure or a vertical GAA (Vertical GAA) structure.

[0075] The channel length of the transistor 200 refers to the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode face each other in a cross-sectional view, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region.

[0076] The channel length of the transistor 200a corresponds to the length of the oxide 230a in the Z direction, and the length of the oxide 230a in the Z direction is equal to or approximately equal to the depth (length in the Z direction) of the first opening in which the oxide 230a is provided. Therefore, the channel length of the transistor 200a can be adjusted by the depth (length in the Z direction) of the first opening. Note that, if the conductor 244 does not have a recess in the region overlapping the first opening, the channel length of the transistor 200a can sometimes be considered to be the shortest distance from the upper surface of the conductor 244 to the lower surface of the conductor 246 in a cross-sectional view. In other words, the depth (length in the Z direction) of the first opening is equal to or approximately equal to the sum of the film thickness of the insulator 272 in the region overlapping the conductor 244 and the film thickness of the insulator 274. In other words, the channel length of the transistor 200a can be adjusted by the film thicknesses of the insulator 272, the conductor 262, and the insulator 274. For example, by reducing the thicknesses of the insulators 272 and 274, the transistor 200a with a short channel length can be manufactured.

[0077] The channel length of the transistor 200b corresponds to the length of the oxide 230b in the Z direction, and the length of the oxide 230b in the Z direction is equal to or approximately equal to the depth (length in the Z direction) of the second opening in which the oxide 230b is provided. Therefore, the channel length of the transistor 200b can be adjusted by the depth (length in the Z direction) of the second opening. Note that, if the conductor 242 does not have a recess in the region overlapping the second opening, the channel length of the transistor 200b can sometimes be considered to be the shortest distance from the upper surface of the conductor 242 to the lower surface of the conductor 246 in a cross-sectional view. In other words, the depth (length in the Z direction) of the second opening is equal to or approximately equal to the sum of the film thickness of the insulator 270 in the region overlapping the conductor 242, the film thickness of the insulator 272, and the film thickness of the insulator 274. In other words, the channel length of the transistor 200b can be adjusted by the film thickness of the insulator 270, the film thickness of the insulator 272, and the film thickness of the insulator 274. For example, by reducing the thicknesses of the insulators 270, 272, and 274, the transistor 200b with a short channel length can be manufactured.

[0078] Note that an OS transistor has extremely low off-state current; therefore, the off-state current of the transistor 200 can be reduced even if the channel length is short.

[0079] On the other hand, when a transistor is operated in the saturation region, the channel length of the transistor may be increased to improve the electrical characteristics in the saturation region. Because the transistor 200 is a vertical transistor, the area occupied by the transistor 200 in a plan view does not depend on the film thickness. Therefore, the channel length of the transistor 200 may be increased.

[0080] From the above, the channel length of the transistor 200 is set to 10 nm to 200 nm, preferably 20 nm to 150 nm, and more preferably 30 nm to 100 nm.

[0081] The channel width of the transistor 200 refers to the length of a region where the semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and the gate electrode face each other in a plan view, or the length of the channel formation region in a direction perpendicular to the channel length direction (Z direction) in the channel formation region. That is, the channel width of the transistor 200 corresponds to the outer periphery of the oxide 230 in a plan view. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be fixed to a single value. For example, as described below, this is the case when the side surface of the oxide 230 has a tapered shape in a cross-sectional view of the transistor. Therefore, in this specification and the like, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0082] The channel length and channel width can be determined by, for example, analyzing a cross-sectional TEM image.

[0083] When a memory cell is configured using a first transistor and a second transistor, one of the source electrode and the drain electrode of the first transistor needs to be connected to the gate electrode of the second transistor. When an electrode (also referred to as a connection electrode) for connecting one of the source electrode and the drain electrode of the first transistor to the gate electrode of the second transistor is provided, providing a region for arranging the connection electrode may increase the area occupied by the memory cell and reduce the degree of integration of the memory cell.

[0084] In one embodiment of the present invention, the conductor 244 has a region in contact with the conductor 260. For example, the conductor 244 has a region in contact with the top surface of the conductor 260. The conductor 244 has a region in contact with the conductor 260, which allows one of the source electrode and the drain electrode of the transistor 200a to be directly connected to the gate electrode of the transistor 200b. Therefore, there is no need to provide an electrode for connecting one of the source electrode and the drain electrode of the transistor 200a to the gate electrode of the transistor 200b, and a memory cell can be formed without reducing the transistor density. This allows the degree of integration of the memory cell to be increased, thereby increasing the storage capacity. Furthermore, the number of steps in the manufacturing process of the semiconductor device can be reduced.

[0085] 2B , the Z-direction length of the oxide 230b is longer than the Z-direction length of the oxide 230a by the thickness of the insulator 270 in the region overlapping with the conductor 242, the film thickness of the conductor 260, and the film thickness of the conductor 244. Increasing the channel length of the transistor 200b reduces the variation in the threshold voltage (Vth) of the transistor 200b functioning as a read transistor. Therefore, a memory cell and a semiconductor device with high read accuracy can be realized. Furthermore, shortening the channel length of the transistor 200a functioning as a write transistor can realize a memory cell and a semiconductor device with high write speed.

[0086] 2A, the conductor 262 and the conductor 242 are arranged to extend in the X direction. That is, the direction in which the conductor 262 extends is parallel to the direction in which the conductor 242 extends. Furthermore, the conductor 246 is arranged to extend in the Y direction. That is, the conductor 246 extends in a direction perpendicular to the direction in which the conductor 262 extends. Furthermore, the conductor 246 extends in a direction perpendicular to the direction in which the conductor 242 extends.

[0087] In the transistor 200, a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 including the channel formation region.

[0088] The oxide 230 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0089] The oxide 230 may be, for example, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also written as GZO), aluminum zinc oxide (Al—Zn oxide), or indium aluminum zinc oxide. Examples of usable materials include In-Al-Zn oxide (IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (IGZO), indium gallium tin zinc oxide (IGZTO), and indium gallium aluminum zinc oxide (IGAZO or IAGZO). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) can be used.

[0090] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0091] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0092] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0093] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0094] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0095] Specifically, the oxide 230 may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0096] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0097] When silicon is used in the channel formation region of a transistor with a short channel length, the floating body effect occurs, making the electrical characteristics of the transistor unstable. On the other hand, metal oxides such as IGZO, IAZO, and IAGZO have a large hole effective mass. Therefore, by using such a metal oxide in the channel formation region, hole accumulation in the channel formation region can be suppressed, and a transistor with little or no influence of the floating body effect can be manufactured. In other words, even when the channel length of a transistor is short, stable electrical characteristics can be imparted to the transistor by using such a metal oxide in the channel formation region. Therefore, a transistor with good electrical characteristics and a semiconductor device including such a transistor can be provided. Furthermore, a transistor with little variation in electrical characteristics and a semiconductor device including such a transistor can be provided.

[0098] In a transistor using an oxide semiconductor, impurities and oxygen vacancies are present in a channel formation region of the oxide semiconductor, which may cause fluctuations in electrical characteristics and reduce reliability. ＯH) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0099] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V Ｏ H can be reduced.

[0100] In order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide 230. In addition, in order to reduce the impurity concentration of the oxide 230, it is preferable to also reduce the impurity concentration in adjacent films.

[0101] A crystalline oxide semiconductor is preferably used for the oxide 230. Examples of crystalline oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductor, single-crystalline oxide semiconductor, and the like. For the oxide 230, it is preferable to use CAAC-OS or nc-OS, and it is particularly preferable to use CAAC-OS.

[0102] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0103] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0104] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230, it is possible to suppress the conductors 242, 244, 246, 260, and 262 from extracting oxygen from the oxide 230. This suppresses the extraction of oxygen from the oxide 230 even when heat treatment is performed, and therefore the transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process. Furthermore, it is possible to suppress the decrease in the conductivity of the conductors 242, 244, 246, 260, and 262.

[0105] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals (also referred to as nanocrystals). Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals, and therefore does not exhibit orientation throughout the film. That is, when the nc-OS is used as the oxide 230, the film characteristics of the oxide 230 are constant regardless of the direction of carriers flowing through the oxide 230, and thus the electrical characteristics of the transistor are stable.

[0106] The oxide 230 may include two or more of a CAAC-OS, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and a cloud-aligned composite oxide semiconductor (CAC-OS).

[0107] When a CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. The position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS. Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that one spot and another spot are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has transmitted through the sample (also referred to as the direct spot).

[0108] Furthermore, when electron beam diffraction (also called nanobeam electron beam diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm or more and 30 nm or less) equal to or smaller than the size of the nanocrystal, an electron beam diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0109] The oxide 230 can be rephrased as a semiconductor layer including a channel formation region of the transistor 200. Note that a material applicable to the semiconductor layer is not limited to a metal oxide (oxide semiconductor) that functions as a semiconductor. For example, a semiconductor such as single crystal silicon, polycrystalline silicon, or amorphous silicon may be used as the semiconductor layer, and low temperature polysilicon (LTPS) may also be used.

[0110] Alternatively, a transition metal chalcogenide that functions as a semiconductor may be used as the semiconductor layer. For example, molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc. may also be used.

[0111] The insulator 250 may have a single layer structure or a multilayer structure.

[0112] The insulator 250 can be made of, for example, silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250 contains at least oxygen and silicon.

[0113] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 be reduced.

[0114] As will be described in detail later, the insulators 250a and 250b are formed in the same process. Therefore, the insulator 250a has the same insulating material as the insulator 250b. The thickness of the insulator 250a is equal to the thickness of the insulator 250b.

[0115] Note that an insulator having a barrier property against oxygen may be provided between the insulator 250 and the oxide 230. The insulator is provided in contact with the side surface of the insulator 250 and the side surface of the oxide 230. When the insulator has a barrier property against oxygen, oxygen contained in the insulator 250 can be supplied to the channel formation region and the oxygen contained in the insulator 250 can be prevented from being excessively supplied to the channel formation region. Therefore, when heat treatment or the like is performed, oxygen can be prevented from being released from the oxide 230 and the formation of oxygen vacancies in the oxide 230 can be prevented. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0116] As an insulator having a barrier property against oxygen, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). It is more preferable to use aluminum oxide as the insulator. In this case, the insulator contains at least oxygen and aluminum. Note that the insulator may be less permeable to oxygen than the insulator 250, for example. Alternatively, the insulator may be made of a material that is less permeable to oxygen than the insulator 250, for example. Alternatively, the insulator may be made of, for example, magnesium oxide, gallium oxide, gallium zinc oxide, or indium gallium zinc oxide, for example.

[0117] To form the oxide 230 and the insulator 250 in the openings provided in the insulators 272 and 274, etc., it is preferable to form the films using an atomic layer deposition (ALD) method. The ALD method includes a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma excited reactant is used. The PEALD method may be preferable in some cases because it uses plasma, which allows film formation at a lower temperature.

[0118] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures, etc. Therefore, the oxide 230 and the insulator 250 can be formed with good coverage on the side surfaces of the openings provided in the insulators 272 and 274, etc.

[0119] Note that some precursors used in the ALD method contain, for example, carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0120] The conductor 242 is provided on the insulator 212. The conductor 244 is provided on the conductor 260. The conductor 246 is provided on the insulator 274.

[0121] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen for the conductors 242, 244, and 246. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. By using such conductive materials, it is possible to suppress a decrease in the conductivity of the conductors 242, 244, and 246. When a conductive material containing metal and nitrogen is used for the conductors 242, 244, and 246, each of the conductors 242, 244, and 246 contains at least metal and nitrogen.

[0122] For the conductors 242, 244, and 246, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Furthermore, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may also be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain their conductivity even when they absorb oxygen.

[0123] 2B to 2D show a structure in which the conductor 242, the conductor 244, and the conductor 246 are each a single layer. Note that one or more of the conductor 242, the conductor 244, and the conductor 246 may have a stacked structure of two or more layers.

[0124] For example, each of the conductors 242 and 246 may have a two-layer structure of a first conductor and a second conductor. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the first conductor of the conductors 242 and 246 that contacts the oxide 230. This can suppress a decrease in the conductivity of the conductors 242 and 246.

[0125] Furthermore, since the conductors 242 and 246 also function as wiring, it is preferable to use conductors with high conductivity. Therefore, it is preferable that the second conductors of the conductors 242 and 246, which are located on the side not in contact with the oxide 230, have higher conductivity than the first conductors of the conductors 242 and 246. For example, the second conductors of the conductors 242 and 246 can be made of a conductive material containing tungsten, copper, or aluminum as a main component. It is also preferable that the film thickness of the second conductors of the conductors 242 and 246 is greater than the film thickness of the first conductors of the conductors 242 and 246.

[0126] For example, tantalum nitride or titanium nitride can be used as the first conductor of the conductor 242 and the conductor 246, and tungsten can be used as the second conductor of the conductor 242 and the conductor 246. When the conductor 244 has a layered structure, it may have the same structure as the layered structure of the conductor 242 and the conductor 246.

[0127] 2B and 2C show a configuration in which the conductor 244 does not have a recess in the region overlapping with the first opening in which the oxide 230a and the insulator 250a are provided. Note that the present invention is not limited to this. The conductor 244 may have a recess in the region overlapping with the first opening. In other words, a portion of the top surface of the conductor 244 in the region overlapping with the first opening may be removed.

[0128] 2B and 2D show a configuration in which the conductor 242 does not have a recess in the region overlapping with the second opening in which the oxide 230b and the insulator 250b are provided. Note that the present invention is not limited to this. The conductor 242 may have a recess in the region overlapping with the second opening. In other words, a portion of the top surface of the conductor 242 in the region overlapping with the second opening may be removed.

[0129] The conductor 260 is provided on an insulator 270. The conductor 262 is provided on an insulator 272.

[0130] It is preferable to use a highly conductive conductor for the conductor 260 and the conductor 262. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used for each of the conductor 260 and the conductor 262.

[0131] 2B to 2D show a structure in which the conductor 260 and the conductor 262 are single layers, but the present invention is not limited to this. One or both of the conductor 260 and the conductor 262 may have a stacked structure of two or more layers.

[0132] The insulator 212 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor. Therefore, the insulator 212 is a barrier insulating film that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0133] The insulator 212 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used as the insulator 212. Furthermore, the insulator 212 preferably includes, for example, aluminum oxide, magnesium oxide, or the like, which has a high function of capturing and fixing hydrogen. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor through the insulator 212. Alternatively, the diffusion of oxygen contained in the insulator 270 or the like toward the substrate side can be suppressed.

[0134] In this specification and the like, a barrier insulating film refers to an insulating film having a barrier property. In this specification and the like, the barrier property refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0135] The insulator 270 is provided over the insulator 212 and the conductor 242. The insulator 272 is provided over the insulator 270, the conductor 260, and the conductor 244. The insulator 274 is provided over the insulator 272 and the conductor 262.

[0136] It is preferable to use an insulator containing excess oxygen as the insulator 270, insulator 272, and insulator 274, which have openings where the insulator 250 and the oxide 230 are disposed. For the insulator 270, insulator 272, and insulator 274, it is preferable to use an oxide containing silicon, such as silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they allow for easy formation of a region containing excess oxygen. By providing an insulator containing excess oxygen near the oxide 230 and performing heat treatment, oxygen is supplied from the insulator to the oxide 230, and oxygen vacancies and V are reduced. Ｏ H can be reduced.

[0137] It is also preferable that the concentrations of impurities such as water and hydrogen be reduced in the insulators 270, 272, and 274. For example, the insulators 270, 272, and 274 preferably include an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0138] The insulators 270, 272, and 274 function as interlayer films. The insulators 270, 272, and 274 preferably have a lower dielectric constant than the insulator 212. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced.

[0139] For example, it is preferable that insulators 270, 272, and 274 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0140] Furthermore, the top surfaces of the insulators 270, 272, and 274 may each be flattened.

[0141] A semiconductor device having the memory cell 100 can be used as a memory device. A circuit diagram of a semiconductor device having the memory cell 100 used as a memory device is shown in Fig. 2E. The memory cell 100 includes a transistor 200a and a transistor 200b.

[0142] 2E, the gate of the transistor 200a is electrically connected to the wiring WOL, one of the source and drain of the transistor 200a is electrically connected to the gate of the transistor 200b, and the other of the source and drain of the transistor 200b is electrically connected to the wiring BIL. One of the source and drain of the transistor 200b is electrically connected to the wiring SL, and the other of the source and drain of the transistor 200b is electrically connected to the wiring BIL.

[0143] The wiring WOL functions as a word line, the wiring BIL functions as a bit line, and the wiring SL functions as a selection line.

[0144] The wiring WOL corresponds to the conductor 262, the wiring BIL corresponds to the conductor 246, and the wiring SL corresponds to the conductor 242. That is, the conductor 262 has a region that functions as a word line, the conductor 246 has a region that functions as a bit line, and the conductor 242 has a region that functions as a select line.

[0145] Note that a structure of a memory cell and a memory device having the memory cell will be described in Embodiment 2.

[0146] 2B to 2D, the side surface of the opening of the conductor 260 contacts the insulator 250b. At this time, an insulator may be formed between the conductor 260 and the insulator 250b. Furthermore, the side surface of the opening of the conductor 262 contacts the insulator 250a. At this time, an insulator may be formed between the conductor 262 and the insulator 250a.

[0147] Figure 3A is a top view of memory cell 100. Figure 3B is a cross-sectional view of memory cell 100, also a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 3A. Figure 3C is a cross-sectional view of memory cell 100, also a cross-sectional view of the portion indicated by dashed line B1-B2 in Figure 3A. Figure 3D is a cross-sectional view of memory cell 100, also a cross-sectional view of the portion indicated by dashed line B3-B4 in Figure 3A. Note that some elements have been omitted from the top view of Figure 3A for clarity.

[0148] In the memory cell 100 shown in FIGS. 3A to 3D, an insulator 261 is provided between the conductor 260 and the insulator 250b, and an insulator 263 is provided between the conductor 262 and the insulator 250a.

[0149] The insulator 261 functions as a gate insulator for the transistor 200b. Therefore, in addition to taking into consideration the size of the insulator 261 in the A1-A2 direction, it is preferable to appropriately set the thickness of the insulator 250b, the size of the second opening where the insulator 250b is provided, and the like, according to the characteristics desired for the transistor 200b. The insulator 263 functions as a gate insulator for the transistor 200a. Therefore, in addition to taking into consideration the size of the insulator 263 in the A1-A2 direction, it is preferable to appropriately set the thickness of the insulator 250a, the size of the first opening where the insulator 250a is provided, and the like, according to the characteristics desired for the transistor 200a.

[0150] The insulator 261 contains oxygen and an element contained in the conductor 260. Similarly, the insulator 263 contains oxygen and an element contained in the conductor 262. For example, when a material containing a metal element is used for the conductors 260 and 262, the insulators 261 and 263 contain the metal element and oxygen. Furthermore, for example, when a conductive material containing a metal element and nitrogen is used for the conductors 260 and 262, the insulators 261 and 263 contain the metal element, oxygen, and nitrogen.

[0151] 2B to 2D show a configuration in which the sidewalls of the openings in which the oxide 230 and the insulator 250 are provided are perpendicular to the substrate surface (not shown), but the present invention is not limited to this. The sidewalls of the openings may have a tapered shape with respect to the substrate surface. Note that in this specification and the like, the sidewalls of the openings refer to the side surfaces of the openings in the structure in which the openings are provided. Therefore, the "sidewalls of the openings" described in this specification and the like can be rephrased as the side surfaces of the openings in the structure in which the openings are provided. For example, the sidewalls of the first openings can be rephrased as the side surfaces of at least one of the insulator 272, the conductor 262, and the insulator 274 in the first opening. Furthermore, for example, the sidewalls of the second openings can be rephrased as the side surfaces of at least one of the insulator 270, the conductor 260, the insulator 272, and the insulator 274 in the second opening. Furthermore, the "sidewalls of the openings" described in this specification and the like may be referred to as the "sidewalls of the openings."

[0152] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface on which the structure is to be formed is less than 90 degrees. Note that the side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0153] Figure 4A is a top view of memory cell 100. Figure 4B is a cross-sectional view of memory cell 100, also a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 4A. Figure 4C is a cross-sectional view of memory cell 100, also a cross-sectional view of the portion indicated by dashed line B1-B2 in Figure 4A. Figure 4D is a cross-sectional view of memory cell 100, also a cross-sectional view of the portion indicated by dashed line B3-B4 in Figure 4A. Note that some elements have been omitted from the top view of Figure 4A for clarity.

[0154] 4B and 4D , in a cross-sectional view, the sidewalls of the second openings provided in the insulator 270, the conductor 260, the insulator 272, and the insulator 274 may have a tapered shape with a taper angle θ. Here, the taper angle θ is the angle between the sidewall of the second opening and the substrate surface. However, one of the two sides extending from the vertex of the taper angle θ is not limited to the substrate surface, and may be the top surface of the conductor 242. In other words, the taper angle θ may be the angle between the sidewall of the second opening and the top surface of the conductor 242.

[0155] The tapered sidewall of the second opening improves the coverage of the insulator 250b provided inside the second opening, thereby reducing defects such as voids. In addition, the coverage of the oxide 230b provided on the insulator 250b improves, thereby reducing defects such as voids.

[0156] In the above configuration, the sidewalls of the first openings provided in the insulator 272, the conductor 262, and the insulator 274 have a tapered shape in a cross-sectional view. The angle between the sidewalls of the first openings and the substrate surface matches or approximately matches the taper angle θ. Depending on the combination of the materials used for the insulator 270 and the insulator 272, the angle between the sidewalls of the first openings and the substrate surface may not match the taper angle θ.

[0157] The tapered sidewall of the first opening improves the coverage of the insulator 250a provided inside the first opening, reducing defects such as voids. Also, the coverage of the oxide 230a provided on the insulator 250a improves, reducing defects such as voids.

[0158] Note that the closer the taper angle θ is to 90 degrees, the smaller the area occupied by the transistor 200. For example, the taper angle θ is preferably 80 degrees or more, 85 degrees or more, or 87 degrees or more, and less than 90 degrees.

[0159] [Modifications of Memory Cell 100] Modifications of the memory cell 100 shown in FIGS. 2A to 2D will be described below with reference to FIGS. 5A to 8A.

[0160] Modifications of the memory cell 100 shown in Figures 2A to 2D are shown in Figures 5A to 5D. Figure 5A is a top view of the memory cell 100. Figure 5B is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 5A. Figure 5C is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line B1-B2 in Figure 5A. Figure 5D is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line B3-B4 in Figure 5A. Note that some elements have been omitted from the top view of Figure 5A for clarity.

[0161] The memory cell 100 shown in Figures 5A to 5D differs from the memory cell 100 shown in Figures 2A to 2B in that the size of the first opening in which the oxide 230a and the insulator 250a are provided is different from the size of the second opening in which the oxide 230b and the insulator 250b are provided.

[0162] 5B , the width of the first opening (the first opening formed in the insulator 272, the conductor 262, and the insulator 274) in which the oxide 230a and the insulator 250a are provided is defined as width R1, and the width of the second opening (the second opening formed in the insulator 270, the conductor 260, the insulator 272, and the insulator 274) in which the oxide 230b and the insulator 250b are provided is defined as width R2. Note that width R1 can be considered to be the diameter of the first opening in a planar view. Also, width R2 can be considered to be the diameter of the second opening in a planar view.

[0163] The width R2 is preferably larger than the width R1. As will be described in detail later, the insulators 250a and 250b are formed from the same insulating film and therefore have the same film thickness. Therefore, by making the width R2 larger than the width R1, the width of the oxide 230b becomes larger than the width of the oxide 230a. In other words, the channel width of the transistor 200b can be made larger than the channel width of the transistor 200a. Increasing the channel width can increase the on-state current. For example, by increasing the width R2, the on-state current of the transistor 200b functioning as a read transistor increases, thereby realizing a memory cell and a semiconductor device with high read speed.

[0164] 5A to 5D , depending on the film thickness of the insulating film that becomes the insulator 250a and the insulator 250b and the film thickness of the oxide film that becomes the oxide 230a and the oxide 230b, the second opening in which the oxide 230b and the insulator 250b are provided may not be filled. Furthermore, the oxide 230b may have a recess that reflects the shape of the second opening. In this case, it is preferable to provide an insulator in the region between the oxide 230b and the conductor 246.

[0165] Modifications of the memory cell 100 shown in Figures 5A to 5D are shown in Figures 6A to 6D. Figure 6A is a top view of the memory cell 100. Figure 6B is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 6A. Figure 6C is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line B1-B2 in Figure 6A. Figure 6D is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line B3-B4 in Figure 6A. Note that some elements have been omitted from the top view of Figure 6A for clarity.

[0166] 6A to 6D, an insulator 275 is provided in a region surrounded by the oxide 230b and the conductor 246. The insulator 275 is provided so as to fill a recess formed in the oxide 230b. The insulator 275 has a region in contact with the top surface of the oxide 230b. The insulator 275 can be made of an insulating material applicable to the insulator 212, the insulator 250, or the like. By providing the insulator 275, it is possible to prevent the conductor 246 from being formed in the recess formed in the oxide 230b.

[0167] Depending on the width (length in the A1-A2 direction) of the recess in the oxide 230b and the method for forming the conductor 246, the conductor 246 may not be formed in the recess in the oxide 230b even if the insulator 275 is not provided in the recess in the oxide 230b. For example, this occurs when the width (length in the A1-A2 direction) of the recess in the oxide 230b is small. In this case, the region between the oxide 230b and the conductor 246 becomes a void. The void contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.).

[0168] Another variation of the memory cell 100 shown in Figures 2A to 2D is shown in Figures 7A to 7D. Figure 7A is a top view of the memory cell 100. Figure 7B is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 7A. Figure 7C is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line B1-B2 in Figure 7A. Figure 7D is a cross-sectional view of the memory cell 100, also showing the cross-sectional view of the portion indicated by the dashed line B3-B4 in Figure 7A. Note that some elements have been omitted from the top view of Figure 7A for clarity.

[0169] As shown in Figures 7B and 7C, it is preferable to provide an insulator 254a having barrier properties against oxygen between the conductor 262 and the insulator 250a. By providing the insulator 254a, it is possible to prevent oxygen contained in the insulator 250a from diffusing into the conductor 262. In other words, it is possible to prevent a decrease in the amount of oxygen supplied to the oxide 230a. It is also possible to prevent oxidation of the conductor 262 due to oxygen contained in the insulator 250a. It is also possible to prevent the formation of the insulator 263 shown in Figures 3B and 3C.

[0170] As shown in Figures 7B and 7D, it is preferable to provide an insulator 254b having barrier properties against oxygen between the conductor 260 and the insulator 250b. By providing the insulator 254b, it is possible to prevent oxygen contained in the insulator 250b from diffusing into the conductor 260. In other words, it is possible to prevent a decrease in the amount of oxygen supplied to the oxide 230b. It is also possible to prevent oxidation of the conductor 260 due to oxygen contained in the insulator 250b. It is also possible to prevent the formation of the insulator 261 shown in Figures 3B and 3D.

[0171] The insulators 254a and 254b may be made of the above-described insulators having oxygen barrier properties. Note that the insulators 254a and 254b are formed in the same process. Therefore, the insulator 254a has the same insulating material as the insulator 254b. The thickness of the insulator 254a is equal to the thickness of the insulator 254b.

[0172] Furthermore, it is preferable to provide an insulator having the above-described oxygen barrier properties between the conductor and the oxygen-containing insulator. By providing an insulator having oxygen barrier properties between the conductor and the oxygen-containing insulator, it is possible to prevent the oxygen contained in the insulator from diffusing into the conductor. In other words, it is possible to prevent a decrease in the amount of oxygen supplied to the oxide 230. It is also possible to prevent the conductor from being oxidized by the oxygen contained in the insulator.

[0173] 7A to 7D , for example, an insulator 281 is provided between the conductor 242 and the insulator 270. An insulator 282 is provided between the conductor 260 and the insulator 270. An insulator 283 is provided between the conductor 244 and the conductor 260 and the insulator 272. An insulator 284 is provided between the conductor 262 and the insulator 272. An insulator 285 is provided between the conductor 262 and the insulator 274. An insulator 286 is provided between the conductor 246 and the insulator 274. The insulators 281 to 286 are insulators having a barrier property against oxygen.

[0174] Note that it is not necessary to provide all of the insulators 281 to 286 in the memory cell 100. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion may be used as a conductor included in the memory cell 100. Therefore, it is preferable to provide one or more of the insulators 281 to 286.

[0175] 2A shows a configuration in which the conductor 246 extends in the Y direction. However, the present invention is not limited to this as long as the direction in which the conductor 246 extends is different from the direction in which the conductor 262 and the conductor 242 extend.

[0176] Figure 8A shows another modification of the memory cell 100 shown in Figure 2A. Figure 8A is a top view of a semiconductor device having the memory cell 100. Note that Figure 8A shows an area including memory cell 100[i,j], memory cell 100[i+1,j], memory cell 100[i,j+1], and memory cell 100[i+1,j+1].

[0177] 8A , the conductor 262 and the conductor 242 may extend in the X direction, and the conductor 246 may extend at an angle to the X direction. In this case, in a plan view, the line segment connecting the transistor 200a and the transistor 200b included in one memory cell 100 is parallel to the direction in which the conductor 246 extends. In other words, in a plan view, the line segment connecting the center of the first opening and the center of the second opening included in one memory cell 100 is parallel to the direction in which the conductor 246 extends. In other words, the number of conductors 246 connected to one memory cell 100 is one.

[0178] 8A , the transistors 200 are arranged in a zigzag pattern along the Y direction. For example, the transistors 200a and 200b in the memory cell 100[i,j] and the transistors 200a and 200b in the memory cell 100[i+1,j] are arranged in a zigzag pattern along the Y direction.

[0179] The configuration shown in FIG. 8A may enable a semiconductor device to have a higher memory density.

[0180] Note that some of the configurations described in [Memory Cell 100] and [Modification of Memory Cell 100] may be applied to memory cells described below.

[0181] [Memory Cell 100A] An example of a configuration different from the memory cell 100 described above is shown in Figure 8B and Figures 9A to 9D. Note that in the memory cells described below, structures having the same functions as structures constituting the memory cell 100 described above are denoted by the same reference numerals. In the following, differences from the memory cell 100 described above will be mainly described, and descriptions of overlapping portions will be omitted.

[0182] 8B is a top view of a semiconductor device having memory cell 100 A. Note that Fig. 8B shows a region including memory cell 100A[i, j], memory cell 100A[i+1, j], memory cell 100A[i, j+1], and memory cell 100A[i+1, j+1].

[0183] 8A in that the line segment connecting transistor 200a and transistor 200b is not parallel to the direction in which conductor 246 extends. In other words, memory cell 100A differs from memory cell 100 shown in FIG. 8A in that the number of conductors 246 connected to one memory cell 100A is two.

[0184] 8B , memory cell 100A[i,j] is connected to conductor 246[j] and conductor 246[j+1]. Specifically, transistor 200a included in memory cell 100A[i,j] is connected to conductor 246[j+1], and transistor 200b included in memory cell 100A[i,j] is connected to conductor 246[j]. In other words, the conductor 246 connected to transistor 200a and the conductor 246 connected to transistor 200b have different configurations.

[0185] 9A is a top view of memory cell 100A. FIG. 9B is a cross-sectional view of memory cell 100A, also a cross-sectional view of the portion indicated by dashed line A1-A2 in FIG. 9A. FIG. 9C is a cross-sectional view of memory cell 100A, also a cross-sectional view of the portion indicated by dashed line B1-B2 in FIG. 9A. FIG. 9D is a cross-sectional view of memory cell 100A, also a cross-sectional view of the portion indicated by dashed line B3-B4 in FIG. 9A. Note that some elements have been omitted from the top view of FIG. 9A for clarity.

[0186] Memory cell 100A differs from memory cell 100 shown in FIGS. 2A to 2D in that it has conductors 246a and 246b instead of conductor 246.

[0187] The conductor 246a is electrically connected to the oxide 230a, and the conductor 246b is electrically connected to the oxide 230b. Specifically, the conductor 246a has a region in contact with the upper surface of the oxide 230a, and the conductor 246b has a region in contact with the upper surface of the oxide 230b. The direction in which the conductor 246a extends is parallel to the direction in which the conductor 246b extends. The direction in which the conductor 246a extends is different from the direction in which the conductor 262 extends. The direction in which the conductor 246b extends is different from the direction in which the conductor 242 extends.

[0188] The conductor 246a functions as the other of the source electrode and drain electrode of the transistor 200a and as a wiring. The conductor 246b functions as the other of the source electrode and drain electrode of the transistor 200b and as a wiring.

[0189] 9B, the conductor 246a is preferably provided in the same layer as the conductor 246b. The conductor 246a is preferably formed of the same material and in the same process as the conductor 246b. In this case, the conductor 246a has the same conductive material as the conductor 246b. By forming the conductor 246a from the same material and in the same process as the conductor 246b, a semiconductor device including the memory cell 100A can be manufactured without increasing the number of processes.

[0190] For example, if the conductor 246[j+1] shown in Fig. 8B is the conductor 246a, the conductor 246b corresponds to the conductor 246[j] shown in Fig. 8B. Also, if the conductor 246[j+1] shown in Fig. 8B is the conductor 246b, the conductor 246b corresponds to the conductor 246[j+2] shown in Fig. 8B.

[0191] A semiconductor device including the memory cell 100A can be used as a memory device. A circuit diagram of a semiconductor device including the memory cell 100A used as a memory device is shown in FIG. 9E. The memory cell 100A includes a transistor 200a and a transistor 200b.

[0192] 9E, the gate of the transistor 200a is electrically connected to the wiring WOL, one of the source and drain of the transistor 200a is electrically connected to the gate of the transistor 200b, and the other of the source and drain of the transistor 200a is electrically connected to the wiring WBL. One of the source and drain of the transistor 200b is electrically connected to the wiring SL, and the other of the source and drain of the transistor 200b is electrically connected to the wiring RBL.

[0193] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0194] The wiring WOL corresponds to the conductor 262, the wiring WBL corresponds to the conductor 246a, the wiring RBL corresponds to the conductor 246b, and the wiring SL corresponds to the conductor 242. In other words, the conductor 262 has a region that functions as a word line, the conductor 246a has a region that functions as a write bit line, the conductor 246b has a region that functions as a read bit line, and the conductor 242 has a region that functions as a select line.

[0195] One of the source and drain of the transistor 200b may be electrically connected to a wiring RBL, and the other of the source and drain of the transistor 200b may be electrically connected to a wiring SL. In this case, the wiring RBL corresponds to the conductor 242, and the wiring SL corresponds to the conductor 246b. That is, the conductor 242 has a region that functions as a read bit line, and the conductor 246b has a region that functions as a select line.

[0196] By adopting the above configuration, the write bit line and the read bit line of the memory cell can be made independent.

[0197] Note that a structure of a memory cell and a memory device having the memory cell will be described in Embodiment 2.

[0198] [Memory Cell 100B] Examples of configurations different from the memory cell 100 described above are shown in Figures 10A to 10D. Note that in the memory cells described below, structures having the same functions as structures constituting the memory cell 100 described above are denoted by the same reference numerals. In the following, differences from the memory cell 100 described above will be mainly described, and descriptions of overlapping portions will be omitted.

[0199] Figure 10A is a top view of memory cell 100B. Figure 10B is a cross-sectional view of memory cell 100B, also a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 10A. Figure 10C is a cross-sectional view of memory cell 100B, also a cross-sectional view of the portion indicated by the dashed line B1-B2 in Figure 10A. Figure 10D is a cross-sectional view of memory cell 100B, also a cross-sectional view of the portion indicated by the dashed line B3-B4 in Figure 10A. Note that some elements have been omitted from the top view of Figure 10A for clarity.

[0200] 2A to 2D in that the memory cell 100B has a capacitor 201 below the transistor 200a. The memory cell 100B has a transistor 200a, a transistor 200b, and a capacitor 201.

[0201] 2A to 2D in that the memory cell 100B includes a conductor 242c. Note that in FIGS. 10A to 10D, an identification symbol is added to the conductor 242 that functions as one of the source electrode and drain electrode of the transistor 200b. Specifically, the conductor that functions as one of the source electrode and drain electrode of the transistor 200b is referred to as the conductor 242b. Therefore, for the conductor 242b, the description of the conductor 242 described above in [Memory Cell 100] can be referred to.

[0202] The capacitor 201 has a conductor 242c, an insulator 270 on the conductor 242c, and a conductor 260 on the insulator 270. The conductor 242c has a region that functions as one electrode of the capacitor 201, the conductor 260 has a region that functions as the other electrode of the capacitor 201, and the insulator 270 has a region that functions as a dielectric of the capacitor 201. The capacitor 201 constitutes a metal-insulator-metal (MIM) capacitor.

[0203] The conductor 242c is provided on the insulator 212. The conductor 242c has a region that overlaps with the conductor 260 via the insulator 270. The conductor 242c is provided extending in the X direction. In other words, the direction in which the conductor 242c extends is parallel to the direction in which the conductor 242b extends. The conductor 242c functions as a wiring.

[0204] 10B, the conductor 242c is preferably provided in the same layer as the conductor 242b. The conductor 242c is preferably formed of the same material and in the same process as the conductor 242b. In this case, the conductor 242c has the same conductive material as the conductor 242b. By forming the conductor 242c from the same material and in the same process as the conductor 242b, a capacitance can be formed without increasing the number of steps in the manufacturing process of a semiconductor device.

[0205] As described above, the channel length of the transistor 200b is longer than that of the transistor 200a. Therefore, the channel capacitance (capacitance between the gate electrode and the channel formation region) of the transistor 200b is larger than that of the transistor 200a. Therefore, the capacitance of the capacitor 201 may be smaller.

[0206] A semiconductor device having memory cell 100B can be used as a memory device. FIG. 10E shows a circuit diagram of a semiconductor device having memory cell 100B used as a memory device. Memory cell 100B has transistor 200a, transistor 200b, and capacitor 201. In other words, memory cell 100B can be said to be a memory cell composed of two transistors and one capacitor. A memory cell composed of two transistors and one capacitor is also called a 2Tr1C type memory cell. Therefore, memory cell 100B is a 2Tr1C type memory cell.

[0207] 10E, the gate of the transistor 200a is electrically connected to the wiring WOL, one of the source and drain of the transistor 200a is electrically connected to one electrode of the capacitor 201, and the other of the source and drain of the transistor 200a is electrically connected to the wiring BIL. The gate of the transistor 200b is electrically connected to one electrode of the capacitor 201, one of the source and drain of the transistor 200b is electrically connected to the wiring SL, and the other of the source and drain of the transistor 200b is electrically connected to the wiring BIL. The other electrode of the capacitor 201 is electrically connected to the wiring CAL.

[0208] The wiring CAL functions as a capacitance line.

[0209] The wiring WOL corresponds to the conductor 262, the wiring BIL corresponds to the conductor 246, the wiring SL corresponds to the conductor 242b, and the wiring CAL corresponds to the conductor 242c. In other words, the conductor 262 has a region that functions as a word line, the conductor 246 has a region that functions as a bit line, the conductor 242b has a region that functions as a select line, and the conductor 242c has a region that functions as a capacitance line.

[0210] Note that a structure of a memory cell and a memory device having the memory cell will be described in Embodiment 2.

[0211] Modifications of the memory cell 100B shown in FIGS. 10A to 10D are shown in FIGS. 11A to 11D. FIG. 11A is a top view of the memory cell 100B. FIG. 11B is a cross-sectional view of the memory cell 100B, also showing the portion indicated by the dashed line A1-A2 in FIG. 11A. FIG. 11C is a cross-sectional view of the memory cell 100B, also showing the portion indicated by the dashed line B1-B2 in FIG. 11A. FIG. 11D is a cross-sectional view of the memory cell 100B, also showing the portion indicated by the dashed line B3-B4 in FIG. 11A. Note that some elements have been omitted from the top view of FIG. 11A for clarity.

[0212] 11A to 11D, the memory cell 100B may further include a conductor 243. The conductor 243 is provided over the conductor 242c and has a region overlapping with the conductor 260. In this case, the conductor 243 functions as one electrode of the capacitor 201, and the conductor 242c functions as a wiring. By providing the conductor 243, the distance between the pair of electrodes of the capacitor 201 can be shortened. Therefore, the capacitance of the capacitor 201 can be increased. Furthermore, by separating the conductor that functions as one electrode of the capacitor 201 from the conductor that functions as a wiring, a semiconductor device can be manufactured using materials suitable for each.

[0213] 11B shows a configuration in which the Y-direction end of the conductor 243 coincides with the Y-direction end of the conductor 242. However, the present invention is not limited to this. For example, the Y-direction end of the conductor 243 may be located more inward than the Y-direction end of the conductor 242.

[0214] 11C shows a configuration in which the X-direction end of the conductor 243 coincides with the X-direction end of the conductor 260. However, the present invention is not limited to this. For example, the X-direction end of the conductor 243 may be located inside the X-direction end of the conductor 260, or may be located outside the X-direction end of the conductor 260.

[0215] 11B to 11D , an insulator 271 may be provided on the insulator 270. The insulator 271 is provided between a pair of electrodes of the capacitor 201 and has a region that functions as a dielectric of the capacitor 201. In FIGS. 11B to 11D , the insulator 271 is provided between the conductor 243 and the conductor 260.

[0216] It is preferable to use a high-dielectric-constant (high-k) material (a material with a high relative dielectric constant) for the insulator 271. Examples of high-dielectric-constant (high-k) materials include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the above oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0217] Specific examples of high-dielectric-constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using an insulator made of such a high-k material, it is possible to thicken the insulator 271 to a degree that can suppress leakage current and ensure sufficient capacitance of the capacitor 201.

[0218] It is also preferable to use a laminated structure of insulators made of the above materials, and it is preferable to use a laminated structure of a high-dielectric constant (high-k) material and a material having a higher dielectric strength than the high-dielectric constant (high-k) material. For example, an insulator formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulator 271. Alternatively, an insulator formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order can be used. Alternatively, an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order can be used. By using a laminated structure of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 201 can be suppressed.

[0219] 11A to 11D show structures in which the conductor 243 and the insulator 271 are provided, but the present invention is not limited to this. The memory cell 100B may include either the conductor 243 or the insulator 271.

[0220] [Memory Cell 100C] Examples of configurations different from the memory cell 100A and memory cell 100B described above are shown in Figures 12A to 12D. Note that in the memory cells described below, structures having the same functions as the structures constituting the memory cell 100A or memory cell 100B described above are denoted by the same reference numerals. In the following, differences from the memory cell 100A or memory cell 100B described above will be mainly described, and descriptions of overlapping portions will be omitted.

[0221] 12A is a top view of memory cell 100C. FIG. 12B is a cross-sectional view of memory cell 100C, also a cross-sectional view of the portion indicated by dashed line A1-A2 in FIG. 12A. FIG. 12C is a cross-sectional view of memory cell 100C, also a cross-sectional view of the portion indicated by dashed line B1-B2 in FIG. 12A. FIG. 12D is a cross-sectional view of memory cell 100C, also a cross-sectional view of the portion indicated by dashed line B3-B4 in FIG. 12A. Note that some elements have been omitted from the top view of FIG. 12A for clarity.

[0222] 9A to 9D in that the memory cell 100C has a capacitor 201 below the transistor 200a. Therefore, the memory cell 100C can be said to be a modified example of the memory cell 100A shown in FIGS. 9A to 9D. The memory cell 100C has a transistor 200a, a transistor 200b, and a capacitor 201. Therefore, the memory cell 100C is a 2Tr1C type memory cell.

[0223] 10A to 10D in that the memory cell 100C has conductors 246a and 246b instead of the conductor 246. Therefore, the memory cell 100C can be said to be a modified example of the memory cell 100B shown in FIGS.

[0224] For details of the configuration examples of the transistor 200a and the transistor 200b, the description of the memory cell 100A can be referred to. For details of the configuration example of the capacitor 201, the description of the memory cell 100B can be referred to.

[0225] A semiconductor device including the memory cell 100C can be used as a memory device. A circuit diagram of a semiconductor device including the memory cell 100C used as a memory device is shown in FIG. 12E. The memory cell 100C includes a transistor 200a, a transistor 200b, and a capacitor 201.

[0226] 12E, the gate of the transistor 200a is electrically connected to the wiring WOL, one of the source and drain of the transistor 200a is electrically connected to one electrode of the capacitor 201, and the other of the source and drain of the transistor 200a is electrically connected to the wiring WBL. The gate of the transistor 200b is electrically connected to one electrode of the capacitor 201, one of the source and drain of the transistor 200b is electrically connected to the wiring SL, and the other of the source and drain of the transistor 200b is electrically connected to the wiring RBL. The other electrode of the capacitor 201 is electrically connected to the wiring CAL.

[0227] The wiring WOL corresponds to the conductor 262, the wiring WBL corresponds to the conductor 246a, the wiring RBL corresponds to the conductor 246b, the wiring SL corresponds to the conductor 242b, and the wiring CAL corresponds to the conductor 242c. In other words, the conductor 262 has a region that functions as a word line, the conductor 246a has a region that functions as a write bit line, the conductor 246b has a region that functions as a read bit line, the conductor 242b has a region that functions as a select line, and the conductor 242c has a region that functions as a capacitance line.

[0228] One of the source and drain of the transistor 200b may be electrically connected to a wiring RBL, and the other of the source and drain of the transistor 200b may be electrically connected to a wiring SL. In this case, the wiring RBL corresponds to the conductor 242, and the wiring SL corresponds to the conductor 246b. That is, the conductor 242 has a region that functions as a read bit line, and the conductor 246b has a region that functions as a select line.

[0229] Note that a structure of a memory cell and a memory device having the memory cell will be described in Embodiment 2.

[0230] [Memory Cell 100D] An example of a configuration different from the memory cell 100B described above is shown in Figures 13A to 13D. Note that in the memory cells described below, structures having the same functions as those constituting the memory cell 100B described above are denoted by the same reference numerals. In the following, differences from the memory cell 100B described above will be mainly described, and overlapping portions will not be described.

[0231] Figure 13A is a top view of memory cell 100D. Figure 13B is a cross-sectional view of memory cell 100D, also a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 13A. Figure 13C is a cross-sectional view of memory cell 100D, also a cross-sectional view of the portion indicated by the dashed line B1-B2 in Figure 13A. Figure 13D is a cross-sectional view of memory cell 100D, also a cross-sectional view of the portion indicated by the dashed line B3-B4 in Figure 13A. Note that some elements have been omitted from the top view of Figure 13A for clarity.

[0232] 10A to 10D in that the memory cell 100D includes a transistor 200c instead of the transistor 200b. The memory cell 100D includes a transistor 200a, a transistor 200c, and a capacitor 201.

[0233] The memory cell 100D differs from the memory cell 100B shown in FIGS. 10A to 10D in that a conductor 262c is included between the conductor 260 and the conductor 246. Note that in FIGS. 13A to 13D, an identification symbol is added to the conductor 262 that functions as the gate electrode of the transistor 200a. Specifically, the conductor that functions as the gate electrode of the transistor 200a is referred to as the conductor 262a. Therefore, for the conductor 262a, refer to the description of the conductor 262 described above in [Memory Cell 100].

[0234] The transistor 200c includes a conductor 242, a conductor 260 above the conductor 242, a conductor 262c above the conductor 260, a conductor 246 above the conductor 262c, an oxide 230b, and an insulator 250b. The insulator 272 has a region located between the conductor 260 and the conductor 262c, and the insulator 274 has a region located between the conductor 262c and the conductor 246.

[0235] The insulator 270, the conductor 260, the insulator 272, the conductor 262c, and the insulator 274 have openings that reach the conductor 242. The insulator 250b and the oxide 230b are disposed inside the openings. The insulator 250b has a region in contact with a side surface of the oxide 230b, a region in contact with a side surface of the conductor 260, a region in contact with a side surface of the conductor 262c, a region in contact with at least a portion of a side surface of the insulator 270, a region in contact with at least a portion of a side surface of the insulator 272, and a region in contact with at least a portion of a side surface of the insulator 274. The oxide 230b has a region in contact with a side surface of the insulator 250b, a region in contact with at least a portion of the upper surface of the conductor 242, and a region in contact with at least a portion of the lower surface of the conductor 246.

[0236] The conductor 260 has a region that functions as a first gate electrode of the transistor 200c. The conductor 262c has a region that functions as a second gate electrode of the transistor 200c. The insulator 250b has a region that functions as a gate insulator of the transistor 200c. The conductor 242 has a region that functions as one of the source and drain electrodes of the transistor 200c. The conductor 246 has a region that functions as the other of the source and drain electrodes of the transistor 200c. A region of the oxide 230b facing the conductor 260 with the insulator 250b interposed therebetween and a region of the oxide 230b facing the conductor 262c with the insulator 250b interposed therebetween function as a channel formation region of the transistor 200c.

[0237] The conductor 260 and the conductor 262c may be electrically connected, and the conductor 262c and the conductor 260 may be set to the same potential. In this case, the transistor 200c can be said to be a double-gate transistor. Note that in this specification and the like, a double-gate transistor refers to a transistor that has two gates, and the two gates are electrically connected. By using a double-gate transistor, more current can be passed. Therefore, the on-state current of the transistor 200c that functions as a read transistor is increased, and a memory cell and a semiconductor device with a high read speed can be realized.

[0238] 13A to 13D, when the conductor 260 and the conductor 262c are electrically connected, the conductor 242b and the conductor 242c shown in FIGS. 10A to 10D may be provided instead of the conductor 242. This makes it possible to configure a memory cell having the circuit configuration shown in FIG. 10E. In this case, the transistor 200b shown in FIG. 10E becomes a double-gate transistor.

[0239] 10A to 10D, the conductor 262a and the conductor 262c shown in Fig. 13A to 13D may be provided instead of the conductor 262 of the memory cell 100B shown in Fig. 10A to 10D. In this configuration, the conductor 260 and the conductor 262c are electrically connected to each other, thereby forming a memory cell 100B including a transistor 200b with a double-gate structure.

[0240] Alternatively, the potential of the conductor 262c may be changed independently of the potential of the conductor 260. In this case, the transistor 200c can be said to have a configuration in which two transistors are connected in series. In other words, the memory cell 100D can be said to be a memory cell composed of three transistors and one capacitor. A memory cell composed of three transistors and one capacitor is also called a 3Tr1C type memory cell. Therefore, the memory cell 100D is a 3Tr1C type memory cell.

[0241] When the potential of the conductor 262c is changed independently of the potential of the conductor 260, the conductor 262c has a region that functions as a wiring. In this case, the direction in which the conductor 262c extends is preferably different from the direction in which the conductor 246 extends, and more preferably perpendicular to the direction in which the conductor 262a extends. Furthermore, the direction in which the conductor 262a extends is the same as the direction in which the conductor 262c extends.

[0242] 13B, the conductor 262c is preferably provided in the same layer as the conductor 262a. The conductor 262c is preferably formed using the same material and in the same process as the conductor 262a. In this case, the conductor 262c has the same conductive material as the conductor 262a. By forming the conductor 262c using the same material and in the same process as the conductor 262a, the second gate electrode can be formed without increasing the number of steps in the manufacturing process of the semiconductor device.

[0243] A semiconductor device having the memory cell 100D can be used as a memory device. A circuit diagram of a semiconductor device having the memory cell 100D used as a memory device is shown in FIG. 13E. The memory cell 100D includes a transistor 200a, a transistor 200c, and a capacitor 201. The transistor 200c is configured with a transistor 200c1 and a transistor 200c2 connected in series.

[0244] When the transistor 200c is configured with the transistors 200c1 and 200c2 connected in series, the conductor 260 has a region that functions as the gate electrode of the transistor 200c1, and the conductor 262c has a region that functions as the gate electrode of the transistor 200c2. The insulator 250b has a region that functions as the gate insulator of the transistor 200c1 and a region that functions as the gate insulator of the transistor 200c2. The conductor 242 has a region that functions as one of the source and drain electrodes of the transistor 200c1, and the conductor 246 has a region that functions as the other of the source and drain electrodes of the transistor 200c2.

[0245] 13E, the gate of the transistor 200a is electrically connected to the wiring WWL, one of the source and drain of the transistor 200a is electrically connected to one electrode of the capacitor 201, and the other of the source and drain of the transistor 200a is electrically connected to the wiring BIL. The gate of the transistor 200c1 is electrically connected to one electrode of the capacitor 201, one of the source and drain of the transistor 200c1 is electrically connected to the wiring GNDL, and the other of the source and drain of the transistor 200c1 is electrically connected to one of the source and drain of the transistor 200c2. The gate of the transistor 200c2 is electrically connected to the wiring RWL, and the other of the source and drain of the transistor 200c2 is electrically connected to the wiring BIL. The other electrode of the capacitor 201 is electrically connected to the wiring GNDL.

[0246] The wiring WWL functions as a write word line, the wiring RWL functions as a read word line, and the wiring GNDL functions as a wiring that applies a low-level potential.

[0247] The wiring WWL corresponds to the conductor 262a, the wiring RWL corresponds to the conductor 262c, the wiring BIL corresponds to the conductor 246, and the wiring GNDL corresponds to the conductor 242. That is, the conductor 262a has a region that functions as a write word line, the conductor 262c has a region that functions as a read word line, the conductor 246 has a region that functions as a bit line, and the conductor 242 has a region that functions as a wiring that applies a low-level potential.

[0248] Note that a structure of a memory cell and a memory device having the memory cell will be described in Embodiment 2.

[0249] [Constituent Materials of Semiconductor Device] Constituent materials that can be used in the semiconductor device will be described below.

[0250] <Substrate> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0251] <Insulator> Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0252] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0253] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0254] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0255] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0256] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0257] Conductor: As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0258] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0259] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0260] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. Alternatively, the conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0261] [Example of Manufacturing Method of Semiconductor Device] Next, a manufacturing method of a semiconductor device including the memory cell 100 shown in FIGS. 2A to 2D will be described with reference to FIGS. 14A to 16D.

[0262] 14A to 16D, A, C, and E in each figure are top views. Also, B, D, and F in each figure are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A1-A2 in A, C, and E in each figure. Note that in the top views of A, C, and E in each figure, some elements are omitted for clarity.

[0263] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0264] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, and DC sputtering, which uses a direct current power supply. DC sputtering also includes pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0265] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be classified into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0266] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, and elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0267] As the ALD method, a thermal ALD method, a PEALD method, or the like can be used.

[0268] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0269] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0270] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0271] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate.

[0272] The conductor 242 is formed over the insulator 212, and the insulator 270 is formed over the conductor 242 and the insulator 212. Note that the insulator 270 preferably has a flat top surface. For example, the top surface of the insulator 270 may be planarized by performing CMP treatment after the insulator 270 is formed.

[0273] The conductor 260 is formed over the insulator 270, the conductor 244 is formed over the conductor 260, and the insulator 272 is formed over the conductor 260, the conductor 244, and the insulator 270 (FIGS. 14A and 14B). Note that the insulator 272 preferably has a flat top surface. For example, the top surface of the insulator 272 may be planarized by performing CMP treatment after the insulator 272 is formed.

[0274] The conductor 262 is formed over the insulator 272, and the insulator 274 is formed over the conductor 262 and the insulator 272 (FIGS. 14C and 14D). Note that the insulator 274 preferably has a flat top surface. For example, the top surface of the insulator 274 may be planarized by performing CMP treatment after the insulator 274 is formed.

[0275] Next, lithography and etching are used to process the insulator 270, the conductor 260, the insulator 272, the conductor 262, and the insulator 274 to form an opening 258a that reaches the conductor 244 and an opening 258b that reaches the conductor 242 (FIGS. 14E and 14F). The opening 258a corresponds to the first opening described above, and the opening 258b corresponds to the second opening described above. The openings 258a and 258b may be formed using wet etching, but dry etching is preferable for fine processing.

[0276] It is preferable to use a material different from that of the conductor 260 for the conductor 244 and to select an etching method that provides a high etching rate selectivity between the conductors 244 and 260. Increasing the etching selectivity between the conductor 244 and the conductor 260 allows the conductor 244 to function as an etching stop film when the openings 258a and 258b are formed. This prevents the opening 258a from becoming excessively deep.

[0277] Furthermore, it is preferable to use a material different from that of the conductor 262 for the conductor 244 and to select an etching method that provides a high etching rate selectivity between the conductors. It is also preferable to use a material different from that of the conductor 260 for the conductor 242 and to select an etching method that provides a high etching rate selectivity between the conductors. This allows the openings 258a and 258b to be formed under the same conditions. This simplifies the manufacturing process of the semiconductor device and improves productivity.

[0278] Next, an insulating film 250A is formed (FIGS. 15A and 15B). The insulating film 250A is preferably formed using the ALD method. The insulator 250 is preferably formed to a thin film thickness, and it is preferable to minimize film thickness variation. The ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIG. 15B, the insulating film 250A is preferably formed with good coverage on the bottom and side surfaces of the openings 258a and 258b. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the openings 258a and 258b. Therefore, the insulators 250a and 250b can be formed with good coverage on the openings 258a and 258b, respectively.

[0279] When the insulating film 250A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), or water (H ２ O) and the like can be used. ３ ), or oxygen (O ２ ) as an oxidizing agent, the amount of hydrogen that diffuses into the oxide 230 that will be formed later can be reduced.

[0280] Next, the insulating film 250A is anisotropically etched to form the insulator 250a in contact with the side surfaces of the insulator 272, the conductor 262, and the insulator 274 in the opening 258a, and the insulator 250b in contact with the side surfaces of the insulator 270, the conductor 260, the insulator 272, and the insulator 274 in the opening 258b (FIGS. 15C and 15D). The anisotropic etching of the insulating film 250A may be performed, for example, by dry etching. By anisotropically etching the insulating film 250A, a portion of the top surface of the conductor 242 and a portion of the top surface of the conductor 244 can be exposed.

[0281] When forming the insulators 254a and 254b shown in Figure 7B, after forming the openings 258a and 258b, it is advisable to sequentially deposit insulating films that will become the insulators 254a and 254b, and the insulating film 250A, and then perform the above-mentioned anisotropic etching.

[0282] Next, an oxide film 230A is formed on the insulators 250a and 250b (FIGS. 16A and 16B). The oxide film 230A is preferably formed using the ALD method. By using the ALD method, a film with a uniform thickness can be formed even in a trench or opening with a large aspect ratio. Furthermore, by using the PEALD method, the oxide film 230A can be formed at a lower temperature than by the thermal ALD method. The oxide film 230A may also be formed using the sputtering method.

[0283] After the oxide film is formed by the ALD method, it is preferable to perform a microwave treatment, and it is more preferable to perform the microwave treatment in an atmosphere containing oxygen.

[0284] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be converted into plasma using high-frequency waves such as microwaves and RF, and the oxygen plasma can be applied to the oxide film. At this time, high-frequency waves such as microwaves and RF can also be irradiated onto the oxide film. In other words, high-frequency waves such as microwaves and RF, oxygen plasma, etc. can be applied to the oxide film.

[0285] The impurity concentration in the oxide film can be reduced by the action of high frequency, oxygen plasma, etc. For example, hydrogen in the oxide film can be desorbed as water molecules. In addition, carbon in the oxide film can be desorbed as oxocarbons (CO and / or CO ２ In addition, oxygen radicals generated by oxygen plasma are supplied to the oxide film, and oxygen vacancies in the oxide film and V Ｏ H etc. can be reduced.

[0286] Furthermore, the action of high frequency waves, oxygen plasma, etc. provides atoms in the oxide film with energy higher than the processing temperature of microwave treatment. This promotes rearrangement of metal atoms and oxygen atoms in the oxide film, improving the crystallinity of the oxide film. The impurity concentration and defects (oxygen vacancies and V Ｏ The crystallinity of the oxide film tends to improve as the amount of oxygen (H, etc.) is reduced. In other words, microwave treatment in an oxygen-containing atmosphere reduces the impurity concentration and defect amount in the oxide film and improves the crystallinity of the oxide film.

[0287] Subsequently, a CMP process is performed to remove a portion of the oxide film 230A and expose the insulator 274. As a result, the oxide 230a is formed to fill the opening 258a, and the oxide 230b is formed to fill the opening 258b (FIGS. 16C and 16D). Note that the CMP process may remove a portion of the insulator 274. This allows the insulator 274 to be planarized. In this way, the top surfaces of the oxide 230a, the oxide 230b, the insulator 250a, the insulator 250b, and the insulator 274 are all at the same height.

[0288] When forming the insulator 275 shown in FIG. 6B, it is preferable to form the oxide film 230A, then form an insulating film to become the insulator 275, and then perform the CMP process.

[0289] Alternatively, the microwave treatment may be performed after the CMP treatment described above, rather than after the oxide film 230A is formed.

[0290] Next, the conductor 246 is formed over the oxide 230a, the oxide 230b, the insulator 250a, the insulator 250b, and the insulator 274. Through the above steps, the memory cell 100 shown in Figures 2A to 2D can be manufactured. Also, a semiconductor device including the memory cell 100 shown in Figures 2A to 2D can be manufactured.

[0291] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0292] In this embodiment, a memory device according to one embodiment of the present invention will be described with reference to drawings. The memory device according to one embodiment of the present invention is a memory device (hereinafter also referred to as an OS memory device) including a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor).

[0293] 17A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 is a circuit that has a function of writing data to memory cells included in the memory cell array 1470 and reading data from the memory cells included in the memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0294] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to access.

[0295] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside as power supply voltages. Control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0296] The control logic circuit 1460 processes control signals (CE, WE, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0297] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0298] 17A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited to this. For example, as shown in FIG. 17B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0299] 18A to 18E, an example of the configuration of a memory cell that can be applied to the above-described memory cell MC will be described.

[0300] 18A shows an example of a circuit configuration of a two-transistor gain cell type memory cell. The memory cell 1471 shown in FIG. 18A includes a transistor M1 and a transistor M2. Note that the transistors M1 and M2 are single-gate transistors.

[0301] A first terminal of the transistor M1 is connected to the gate of the transistor M2, a second terminal of the transistor M1 is connected to the wiring BIL, a gate of the transistor M1 is connected to the wiring WOL, a first terminal of the transistor M2 is connected to the wiring BIL, and a second terminal of the transistor M2 is connected to the wiring SL.

[0302] The wiring BIL functions as a bit line, the wiring WOL functions as a word line, and the wiring SL functions as a selection line.

[0303] In the memory cell 1471, the gate capacitance of the transistor M2 is used as a storage capacitance. That is, the memory cell 1471 can be said to be a capacitor-less memory cell. Therefore, it can be said to be a gain cell type memory cell with two transistors and no capacitance element.

[0304] By using an OS transistor as the transistor M1, when the transistor M1 is turned off, charge at a node where one of the source and drain of the transistor M1 and the gate of the transistor M2 are electrically connected can be held for an extremely long time, thereby realizing a nonvolatile memory cell.

[0305] 2A to 2D, etc., can be applied as the memory cell 1471 shown in FIG. 18A. In this case, the transistor M1 corresponds to the transistor 200a, and the transistor M2 corresponds to the transistor 200b. The wiring BIL corresponds to the conductor 246, the wiring WOL corresponds to the conductor 262, and the wiring SL corresponds to the conductor 242.

[0306] 18B shows another example of the circuit configuration of a two-transistor gain cell type memory cell. The memory cell 1472 shown in FIG. 18B includes a transistor M1 and a transistor M2. Note that the transistors M1 and M2 are single-gate transistors.

[0307] A first terminal of the transistor M1 is connected to the gate of the transistor M2, a second terminal of the transistor M1 is connected to the wiring WBL, a gate of the transistor M1 is connected to the wiring WOL, a first terminal of the transistor M2 is connected to the wiring RBL, and a second terminal of the transistor M2 is connected to the wiring SL.

[0308] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0309] Like the memory cell 1471, the memory cell 1472 uses the gate capacitance of the transistor M2 as a storage capacitance. By using an OS transistor as the transistor M1, when the transistor M1 is turned off, charge at a node where one of the source and drain of the transistor M1 and the gate of the transistor M2 are electrically connected can be held for an extremely long time. Therefore, a nonvolatile memory cell can be realized.

[0310] 9A to 9D can be used as the memory cell 1472 shown in FIG. 18B. In this case, the transistor M1 corresponds to the transistor 200a, and the transistor M2 corresponds to the transistor 200b. The wiring WBL corresponds to the conductor 246a, the wiring RBL corresponds to the conductor 246b, the wiring WOL corresponds to the conductor 262, and the wiring SL corresponds to the conductor 242.

[0311] Furthermore, the memory cell MC is not limited to the memory cell 1471 or the memory cell 1472, and the circuit configuration can be changed as appropriate. For example, the transistor M1 and the transistor M2 may have a back gate. When the transistor M1 has a back gate, the back gate may be electrically connected to the gate of the transistor M1 or may be electrically connected to a wiring for applying a potential to the back gate. The same applies when the transistor M2 has a back gate.

[0312] 18C and 18D show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1473 shown in FIG. 18C includes a transistor M3, a transistor M4, and a capacitor CA. Note that the transistors M3 and M4 have single-gate structures. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as at least the transistor M3 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0313] The first terminal of transistor M3 is connected to the first terminal of capacitor CA, the second terminal of transistor M3 is connected to wiring WBL, and the gate of transistor M3 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL. The first terminal of transistor M4 is connected to wiring RBL, the second terminal of transistor M4 is connected to wiring SL, and the gate of transistor M4 is connected to the first terminal of capacitor CA.

[0314] The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, a high-level potential is preferably applied to the wiring CAL. When holding data, a low-level potential is preferably applied to the wiring CAL.

[0315] Furthermore, the memory cell MC is not limited to the memory cell 1473, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1474 shown in FIG. 18D. Furthermore, for example, the transistor M3 may have a back gate. When the transistor M3 has a back gate, the back gate may be electrically connected to the gate of the transistor M3 or may be electrically connected to a wiring for applying a potential to the back gate.

[0316] When the semiconductor device described in the above embodiment is used for the memory cell 1473 or the like, the transistor 200 can be used as the transistor M3. By using an OS transistor as the transistor M3, the leakage current of the transistor M3 can be made very small. This allows written data to be held by the transistor M3 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multilevel data or analog data can be held in the memory cell 1473. The same applies to the memory cell 1474.

[0317] An OS transistor can be used as the transistor M4. For example, the transistor 200a can be used as the transistor M3, and the transistor 200b or the double-gate transistor 200c can be used as the transistor M4. When OS transistors are used as the transistors M3 and M4, the memory cell array 1470 can be configured using only n-channel transistors.

[0318] 12A to 12D can be used as the memory cell 1473 shown in FIG. 18C. In this case, the transistor M3 corresponds to the transistor 200a, and the transistor M4 corresponds to the transistor 200b. The wiring WBL corresponds to the conductor 246a, the wiring RBL corresponds to the conductor 246b, the wiring WOL corresponds to the conductor 262, the wiring SL corresponds to the conductor 242b, and the wiring CAL corresponds to the conductor 242c.

[0319] 10A to 10D can be used as the memory cell 1474 shown in FIG. 18D. In this case, the transistor M3 corresponds to the transistor 200a, and the transistor M4 corresponds to the transistor 200b. The wiring BIL corresponds to the conductor 246, the wiring WOL corresponds to the conductor 262, the wiring SL corresponds to the conductor 242b, and the wiring CAL corresponds to the conductor 242c.

[0320] Note that the transistor M4 may be a transistor having silicon in a channel formation region (hereinafter, sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M4 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M4, the transistor M3 can be stacked on top of the transistor M4, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0321] 18E shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1475 shown in FIG. 18E includes transistors M5 to M7 and a capacitor CB. The capacitor CB is provided as appropriate. The memory cell 1475 is electrically connected to wirings BIL, RWL, WWL, and GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1475 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0322] The transistor M5 is a single-gate OS transistor. The transistor M5 may have a back gate. In the case where the transistor M5 has a back gate, the back gate may be electrically connected to the gate of the transistor M5 or to a wiring for applying a potential to the back gate.

[0323] When the semiconductor device described in the above embodiment is used for the memory cell 1475, the transistor M5 can be the transistor 200. By using an OS transistor as the transistor M5, leakage current of the transistor M5 can be made extremely small.

[0324] Further, OS transistors can be used as the transistors M5 to M7. For example, the transistor 200a can be used as the transistor M5, and the transistor 200c, which has a configuration in which two transistors are connected in series, can be used as the transistors M6 and M7. In this case, the memory cell array 1470 can be configured using only n-channel transistors. Note that the transistors M6 and M7 may each be an n-channel Si transistor or a p-channel Si transistor.

[0325] 13A to 13D can be used as the memory cell 1475 shown in Figure 18E. In this case, the transistor M5 corresponds to the transistor 200a, the transistor M6 corresponds to one of the two transistors connected in series, and the transistor M7 corresponds to the other of the two transistors connected in series. The wiring BIL corresponds to the conductor 246, the wiring WWL corresponds to the conductor 262a, the wiring RWL corresponds to the conductor 262c, and the wiring GNDL corresponds to the conductor 242.

[0326] Furthermore, the memory cells MC are not limited to the memory cells 1471 to 1475, and the circuit configuration can be changed.

[0327] By using an OS transistor as the transistor M1, the transistor M1 can be formed during a back-end-of-line (BEOL) process for forming wiring of a memory device. Furthermore, when a Si transistor is used in the peripheral circuit 1411 that overlaps the memory cell array 1470, a technique for forming an OS transistor directly above a Si transistor (referred to as a BEOL-Tr technique) can be applied. By using this technique, a 3D functional circuit can be constructed while maintaining the design rules, and advanced functionality can be achieved with low power consumption and low cost.

[0328] Fig. 18F shows a perspective view of the memory device 1400. The memory device 1400 has a layer 1480 and a layer 1490. Fig. 18G is a perspective view for explaining the configuration of the memory device 1400, showing the layers 1480 and 1490 separately.

[0329] The layer 1480 is a layer including a transistor. A semiconductor layer including a channel formation region of the transistor may be formed using a semiconductor material such as a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, either singly or in combination. Examples of the semiconductor material include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. Gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like, which are applicable to a high electron mobility transistor (HEMT), may also be used.

[0330] The layer 1490 is a layer including a transistor. A semiconductor layer including a channel formation region of the transistor may be formed using a semiconductor material that can be formed into a thin film, such as an oxide semiconductor or silicon. By using a BEOL-Tr technique, the layer 1490 can be provided over the layer 1480. Thus, a miniaturized memory device 1400 can be realized.

[0331] For example, the transistors included in the layer 1480 are Si transistors. In this case, a peripheral circuit 1411 can be provided in the layer 1480. The transistors included in the layer 1490 are OS transistors. In this case, a memory cell array 1470 can be provided in the layer 1480.

[0332] As described above, the memory device 1400 can be fabricated using the BEOL-Tr technology, and therefore the area occupied by the memory device 1400 can be reduced.

[0333] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0334] Fig. 19 shows an example of a cross-sectional configuration of the storage device 1400 shown in Fig. 17A. Fig. 19 shows a part of the storage device 1400 shown in Fig. 17A.

[0335] 19 , the memory device 1400 includes a layer 1480 and a layer 1490 over the layer 1480. A peripheral circuit 1411 is provided in the layer 1480. That is, the layer 1480 can be said to include the peripheral circuit 1411. The layer 1490 includes a memory cell array 1470. The semiconductor device described in the above embodiment can be used for memory cells included in the memory cell array 1470. That is, the layer 1480 is located below the semiconductor device described in the above embodiment.

[0336] 19 shows the transistor 300 included in the layer 1480. The transistor 300 functions as a part of the sense amplifier described above. In this case, the layer 1480 can be regarded as a substrate on which a semiconductor circuit including a transistor is formed.

[0337] 19 also shows a part of the memory cell array 1470 provided in the layer 1490. Specifically, two memory cells MC provided in the layer 1490 are shown in FIG.

[0338] The conductor 262 corresponds to the wiring WOL, the conductor 244 corresponds to the wiring BIL, and the conductor 246 corresponds to the wiring SL.

[0339] 19 shows a configuration in which one layer 1490 including the memory cell array 1470 is provided, but the present invention is not limited to this. For example, a plurality of layers including the memory cell array 1470 may be stacked.

[0340] 20 shows a stacked structure of a layer 1490_1 including a memory cell array and a layer 1490_2 including a memory cell array. Note that the number of stacked layers may be three or more. In this manner, by using OS transistors as the transistors constituting the memory cell 100, a plurality of memory cell arrays 1470 can be stacked. In other words, the amount of data that can be stored per unit area can be increased.

[0341] The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region and a drain region. The transistor 300 may be either a p-channel or n-channel transistor.

[0342] Here, in the transistor 300 shown in FIG. 19 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0343] Note that the transistor 300 illustrated in FIG. 19 is just an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0344] <Wiring Layer> A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as the wiring, and cases where a portion of the conductor functions as the plug.

[0345] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330, which are electrically connected to the transistor 200, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0346] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0347] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 19, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0348] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0349] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0350] For example, the insulators 322, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulators preferably include silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin. Alternatively, the insulators preferably have a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore, by combining them with resin, a thermally stable layered structure with a low dielectric constant can be achieved. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0351] Furthermore, when a transistor including an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used as the insulator 350 or the like.

[0352] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0353] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0354] For example, the conductors 328, 330, and 356 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum that have both heat resistance and conductivity are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce wiring resistance.

[0355] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0356] (Embodiment 3) In this embodiment, an application example of a semiconductor device using the memory device described in the previous embodiment will be described. The memory device described in the previous embodiment can be applied to various removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (Solid State Drives). Figures 21A to 21E schematically show several configuration examples of removable memory devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0357] 21A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory chip 1105 or the like can be incorporated with the storage device or the semiconductor device described in the above embodiments.

[0358] FIG. 21B is a schematic diagram of the appearance of an SD card, and FIG. 21C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1114 or the like.

[0359] FIG. 21D is a schematic diagram of the appearance of an SSD, and FIG. 21E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of the board 1153, the capacity of the SSD 1150 can be increased. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1154 or the like.

[0360] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0361] In this embodiment, a transistor having an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that in the description of the OS transistor, a comparison with a transistor having silicon in a channel formation region (also referred to as a Si transistor) will also be briefly described.

[0362] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0363] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0364] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0365] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0366] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0367] Furthermore, in Si transistors, a short channel effect (also referred to as SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0368] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0369] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0370] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0371] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0372] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation.

[0373] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0374] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0375] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0376] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0377] [Electronic Component] FIG. 22A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 22A has semiconductor device 710 inside mold 711. FIG. 22A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0378] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0379] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0380] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0381] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0382] 22B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0383] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0384] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0385] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0386] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0387] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0388] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0389] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0390] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 22B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0391] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0392] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 23A . The electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0393] 23B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0394] 23C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 23C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0395] The computer 5620 can have the configuration shown in the perspective view in Fig. 23D, for example. In Fig. 23D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0396] PC card 5621 shown in Figure 23E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 23E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

[0397] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0398] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0399] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0400] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0401] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0402] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0403] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0404] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0405] Fig. 24 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 24, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0406] 24 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0407] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0408] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0409] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0410] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The change in electrical characteristics of an OS transistor due to radiation exposure is smaller than that of a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0411] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0412] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0413] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0414] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0415] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0416] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0417] Fig. 25 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 25 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0418] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0419] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0420] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0421] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0422] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0423] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0424] [Explanation of symbols] ADDR: Address signal, BIL: Wiring, CA: Capacitor element, CAL: Wiring, CB: Capacitor element, CE: Control signal, GNDL: Wiring, MC: Memory cell, RBL: Wiring, RDATA: Data signal, RES: Control signal, RWL: Wiring, SL: Wiring, WBL: Wiring, WDATA: Data signal, WE: Control signal, WOL: Wiring, WWL: Wiring, 10: Semiconductor device, 100A: Memory cell, 100B: Memory cell, 100C: Memory cell, 100D: Memory cell, 100: Memory cell, 200a: Transistor, 200b: Transistor, 200c: Transistor, 200c1: Transistor Transistor, 200c2: transistor, 200: transistor, 201: capacitor, 212: insulator, 230a: oxide, 230A: oxide film, 230b: oxide, 230: oxide, 242b: conductor, 242c: conductor, 242: conductor, 243: conductor, 244: conductor, 246a: conductor, 246b: conductor, 246: conductor, 250a: insulator, 250A: insulating film, 250b: insulator, 250: insulator, 254a: insulator, 254b: insulator, 258a: opening, 258b: opening, 260: conductor, 261: insulator, 262a: conductor, 26 2c: conductor, 262: conductor, 263: insulator, 270: insulator, 271: insulator, 272: insulator, 274: insulator, 275: insulator, 281: insulator, 282: insulator, 283: insulator, 284: insulator, 285: insulator, 286: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354 : insulator, 356: conductor, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card,1111: housing, 1112: connector, 1113: board, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: board, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control circuit SIC circuit, 1470: memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell, 1474: memory cell, 1475: memory cell, 1480: layer, 1490_1: layer, 1490_2: layer, 1490: layer, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 56 26: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 661 3: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001sb: server, 7001: host, 7002: storage control circuit, 7003md: storage device, 7003: storage,

Claims

1. A first conductor and The first insulator on the first conductor, The second conductor on the first insulator, The third conductor on the second conductor, The first insulator, the second conductor, and the second insulator on the third conductor, The fourth conductor on the second insulator, The third insulator on the fourth conductor, The fifth conductor on the third insulator, The first oxide and, The second oxide and, A fourth insulator, It has a fifth insulator, The second insulator, the fourth conductor, and the third insulator are provided with a first opening that reaches the third conductor. The fourth insulator has a region that is in contact with the side surface of the fourth conductor in the first opening. The first oxide has a region facing the fourth conductor via the fourth insulator, a region in contact with the upper surface of the third conductor, and a region in contact with the lower surface of the fifth conductor. The first insulator, the second conductor, the second insulator, and the third insulator are provided with a second opening that reaches the first conductor. The fifth insulator has a region that is in contact with the side surface of the second conductor in the second opening, The second oxide has a region facing the second conductor via the fifth insulator, a region in contact with the upper surface of the first conductor, and a region in contact with the lower surface of the fifth conductor. In a plan view, the fourth conductor extends along the first direction, A semiconductor device in which, in a plan view, the first conductor extends along the first direction.

2. In claim 1, A semiconductor device in which, in a plan view, the diameter of the second aperture is larger than the diameter of the first aperture.

3. In claim 1, In cross-sectional view, each of the side surfaces of the second insulator in the first opening, the side surface of the fourth conductor in the first opening, and the side surface of the third insulator in the first opening has a tapered shape. A semiconductor device wherein, in a cross-sectional view, each of the side surfaces of the first insulator in the second opening, the second conductor in the second opening, the second insulator in the second opening, and the third insulator in the second opening each have a tapered shape.

4. A first insulator and A first conductor and a second conductor on the first insulator, The first insulator, the first conductor, and the second insulator on the second conductor, The third conductor on the second insulator, The fourth conductor on the third conductor, The second insulator, the third conductor, and the third insulator on the fourth conductor, The fifth conductor on the third insulator, The fourth insulator on the fifth conductor, The sixth conductor on the fourth insulator, The first oxide and, The second oxide and, A fifth insulator, It has a sixth insulator, The first conductor has a region that overlaps with the third conductor via the second insulator. The third insulator, the fifth conductor, and the fourth insulator are provided with a first opening that reaches the fourth conductor. The fifth insulator has a region that is in contact with the side surface of the fifth conductor in the first opening, The first oxide has a region facing the fifth conductor via the fifth insulator, a region in contact with the upper surface of the fourth conductor, and a region in contact with the lower surface of the sixth conductor. The second insulator, the third conductor, the third insulator, and the fourth insulator are provided with a second opening that reaches the second conductor. The sixth insulator has a region that is in contact with the side surface of the third conductor in the second opening, The second oxide has a region facing the third conductor via the sixth insulator, a region in contact with the upper surface of the second conductor, and a region in contact with the lower surface of the sixth conductor. In a plan view, the first conductor extends along a first direction, In a plan view, the second conductor extends along the first direction, A semiconductor device in which, in a plan view, the fifth conductor extends along the first direction.

5. In claim 4, The first conductor is provided in the same layer as the second conductor, and the semiconductor device is provided in this same layer.

6. A first insulator and A first conductor and a second conductor on the first insulator, The first insulator, the first conductor, and the second insulator on the second conductor, The third conductor on the second insulator, The fourth conductor on the third conductor, The second insulator, the third conductor, and the third insulator on the fourth conductor, The fifth conductor on the third insulator, The fourth insulator on the fifth conductor, The sixth conductor and the seventh conductor on the fourth insulator, The first oxide and, The second oxide and, A fifth insulator, It has a sixth insulator, The first conductor has a region that overlaps with the third conductor via the second insulator. The third insulator, the fifth conductor, and the fourth insulator are provided with a first opening that reaches the fourth conductor. The fifth insulator has a region that is in contact with the side surface of the fifth conductor in the first opening, The first oxide has a region facing the fifth conductor via the fifth insulator, a region in contact with the upper surface of the fourth conductor, and a region in contact with the lower surface of the sixth conductor. The second insulator, the third conductor, the third insulator, and the fourth insulator are provided with a second opening that reaches the second conductor. The sixth insulator has a region that is in contact with the side surface of the third conductor in the second opening, The second oxide has a region facing the third conductor via the sixth insulator, a region in contact with the upper surface of the second conductor, and a region in contact with the lower surface of the seventh conductor. In a plan view, the first conductor extends along a first direction, In a plan view, the second conductor extends along the first direction, In a plan view, the fifth conductor extends along the first direction, In a plan view, the sixth conductor extends along a second direction intersecting the first direction, A semiconductor device in which, in a plan view, the seventh conductor extends along the second direction.

7. In claim 6, The first conductor is provided on the same layer as the second conductor, The sixth conductor is provided in the same layer as the seventh conductor, and the semiconductor device is provided in this same layer.