Quantum device and method for manufacturing quantum device

Abstract

This quantum device comprises a higher-order topological insulator layer and a superconductor layer. The higher-order topological insulator layer has: a first surface and a second surface which are parallel to each other; a third surface intersecting the second surface and positioned closer to the first surface than to the second surface; and a fourth surface intersecting the third surface and parallel to the first surface and the second surface. The superconductor layer is formed on a line of intersection between a plane including the third surface and the first surface.

Description

Quantum device and method for manufacturing the same

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to quantum devices and methods for manufacturing quantum devices.

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure that generates Majorana particles. WTe, a layered material of transition metal ditellurides, is one of the two-dimensional topological insulators. ２ A single layer of WTe is used. ２ Research is also being conducted on higher-order topological insulator layers consisting of

[0003] Japanese Patent Publication No. 2020-96107 Japanese Patent Publication No. 2020-511780 Japanese Patent Publication No. 2013-247267 U.S. Patent Application No. 2021 / 0257536 U.S. Patent Application No. 2019 / 0013457

[0004] Z. Wang, et al., Phys. Rev. Lett. 123, 186401 (2019)Y.-B. Choi et al., Nat. Mater. 19, 974 (2020)

[0005] Previous studies on high-order topological insulator layers have focused on Majorana particles that appear in one-dimensional conduction channels (hinge helical channels) that arise on the edges of rectangular parallelepiped high-order topological insulator layers. However, when a high-order topological insulator layer is actually formed, the atomic arrangement at the edges is more likely to be disordered than the arrangement inside or on the surfaces. Therefore, there is a risk that the Majorana particles that appear on the edges may become unstable.

[0006] An object of the present disclosure is to provide a quantum device and a method for manufacturing the quantum device that can obtain stable Majorana particles.

[0007] According to one aspect of the present disclosure, there is provided a quantum device comprising a high-order topological insulator layer and a superconductor layer, wherein the high-order topological insulator layer has a first surface and a second surface that are parallel to each other, a third surface that intersects with the second surface and is located closer to the first surface than the second surface, and a fourth surface that intersects with the third surface and is parallel to the first surface and the second surface, and the superconductor layer is formed on an intersection line between a plane including the third surface and the first surface.

[0008] According to the present disclosure, stable Majorana particles can be obtained.

[0009] FIG. 1 is a plan view showing a quantum device according to the first embodiment. FIG. 2 is a cross-sectional view (part 1) showing a quantum device according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing a quantum device according to the first embodiment. FIG. 4 is a perspective view showing a high-order topological insulator layer according to the first embodiment. FIG. 5 is a bottom view showing a high-order topological insulator layer and a superconductor layer according to the first embodiment. FIG. 6 is a cross-sectional view (part 1) showing a method for manufacturing a quantum device 1 according to the first embodiment. FIG. 7 is a cross-sectional view (part 2) showing a method for manufacturing a quantum device 1 according to the first embodiment. FIG. 8 is a cross-sectional view (part 3) showing a method for manufacturing a quantum device 1 according to the first embodiment. FIG. 9 is a cross-sectional view (part 4) showing a method for manufacturing a quantum device 1 according to the first embodiment. FIG. 10 is a cross-sectional view (part 5) showing a method for manufacturing a quantum device 1 according to the first embodiment. FIG. 11 is a diagram (part 1) showing a model used in calculations of a one-dimensional conduction channel. FIG. 12 is a diagram (part 2) showing a model used in calculations of a one-dimensional conduction channel. FIG. 13 is a diagram (part 1) showing the results of calculations on a high-order topological insulator layer. FIG. 14 is a diagram (part 2) showing the results of calculations on a high-order topological insulator layer. FIG. 15 is a plan view showing a quantum device according to a second embodiment. FIG. 16 is a cross-sectional view showing a quantum device according to the second embodiment. FIG. 17 is a cross-sectional view showing a quantum device according to a third embodiment. FIG. 18 is a perspective view showing a high-order topological insulator layer in a fourth embodiment. FIG. 19 is a bottom view showing a high-order topological insulator layer and a superconductor layer in the fourth embodiment.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0011] (First Embodiment) A first embodiment will be described. The first embodiment relates to a quantum device. FIG. 1 is a plan view showing a quantum device according to the first embodiment. FIGS. 2 and 3 are cross-sectional views showing the quantum device according to the first embodiment. FIG. 4 is a perspective view showing a high-order topological insulator layer in the first embodiment. FIG. 5 is a bottom view showing a high-order topological insulator layer and a superconductor layer in the first embodiment. In FIG. 1, a protective layer is seen through. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 1.

[0012] The quantum device 1 according to the first embodiment mainly includes a substrate 300 , a superconductor layer 200 , and a high-order topological insulator layer 100 .

[0013] The substrate 300 includes, for example, a silicon (Si) substrate 310 and an insulating film 320. The insulating film 320 is formed on the silicon substrate 310. The insulating film 320 is, for example, a silicon oxide film. The substrate 300 is a so-called substrate with an oxide film. The shape of the substrate 300 is, for example, a rectangular parallelepiped having two planes parallel to the XY plane, two planes parallel to the YZ plane, and two planes parallel to the ZX plane, with the X1-X2 direction as the longitudinal direction and the Y1-Y2 direction as the lateral direction.

[0014] The superconductor layer 200 is provided on the insulating film 320. The shape of the superconductor layer 200 is, for example, a rectangular parallelepiped having two planes parallel to the XY plane, two planes parallel to the YZ plane, and two planes parallel to the ZX plane, with the X1-X2 direction as the longitudinal direction and the Y1-Y2 direction as the lateral direction. The superconductor layer 200 is, for example, an aluminum (Al) layer or a niobium (Nb) layer.

[0015] The high-order topological insulator layer 100 has a first surface 111, a second surface 112, and a fourth surface 114 parallel to the XY plane, a third surface 113, a fifth surface 115, and a sixth surface 116 parallel to the YZ plane, and a seventh surface 117 and an eighth surface 118 parallel to the ZX plane. ２ (tungsten ditelluride) layer. ２ The a-axis is parallel to the Y1-Y2 direction, the b-axis is parallel to the X1-X2 direction, and the c-axis is parallel to the Z1-Z2 direction. Here, the a-axis, b-axis, and c-axis are defined as shown in Figure 1(a) of Non-Patent Document 2.

[0016] The first surface 111, the second surface 112, and the fourth surface 114 are shaped like a rectangle having two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction. The X2-side side of the first surface 111 and the X2-side side of the second surface 112 are located at the same position in the X1-X2 direction. The Y1-side side of the first surface 111 and the Y1-side side of the second surface 112 are located at the same position in the Y1-Y2 direction, and the Y2-side side of the first surface 111 and the Y2-side side of the second surface 112 are located at the same position in the Y1-Y2 direction. The X1-side side of the first surface 111 and the X1-side side of the fourth surface 114 are located at the same position in the X1-X2 direction. The Y1-side edge of the first surface 111 and the Y1-side edge of the fourth surface 114 are at the same position in the Y1-Y2 direction, and the Y2-side edge of the first surface 111 and the Y2-side edge of the fourth surface 114 are at the same position in the Y1-Y2 direction. In the Z1-Z2 direction, the fourth surface 114 is closer to the first surface 111 than the second surface 112, and closer to the second surface 112 than the first surface 111. In other words, the fourth surface 114 is located closer to the first surface 111 than the second surface 112.

[0017] The third surface 113, the fifth surface 115, and the sixth surface 116 are shaped like a rectangle having two sides parallel to the Y1-Y2 direction and two sides parallel to the Z1-Z2 direction. The third surface 113 intersects with the second surface 112 and the fourth surface 114. The third surface 113 intersects with the second surface 112 and the fourth surface 114, for example, at a right angle. The fifth surface 115 intersects with the first surface 111 and the second surface 112. The fifth surface 115 intersects with the first surface 111 and the second surface 112, for example, at a right angle. The sixth surface 116 intersects with the first surface 111 and the fourth surface 114. The sixth surface 116 intersects with the first surface 111 and the fourth surface 114, for example, at a right angle.

[0018] The seventh surface 117 and the eighth surface 118 are hexagonal in shape, with three sides parallel to the Z1-Z2 direction and three sides parallel to the X1-X2 direction. The seventh surface 117 and the eighth surface 118 intersect with the first surface 111, the second surface 112, the third surface 113, the fourth surface 114, the fifth surface 115, and the sixth surface 116. The seventh surface 117 and the eighth surface 118 intersect with the first surface 111, the second surface 112, the third surface 113, the fourth surface 114, the fifth surface 115, and the sixth surface 116, for example, at right angles. The seventh surface 117 is on the Y1 side of the eighth surface 118.

[0019] As described above, the high-order topological insulator layer 100 has a three-dimensional shape resembling a rectangular parallelepiped with steps. In the high-order topological insulator layer 100, one-dimensional conduction channels are generated along the edges 121, 122, and 123 indicated by bold lines in FIG. 4 . That is, one-dimensional conduction channels are generated along the edge 121 corresponding to the intersection of the first surface 111 and the fifth surface 115, the edge 122 corresponding to the intersection of the fourth surface 114 and the sixth surface 116, and the edge 123 corresponding to the intersection of the second surface 112 and the third surface 113. Furthermore, in the high-order topological insulator layer 100, a one-dimensional conduction channel is also generated along the intersection 124 between the first surface 111 and a plane including the third surface 113.

[0020] The high-order topological insulator layer 100 is provided above the substrate 300 so that the first surface 111 is in contact with the top surface of the superconductor layer 200. The seventh surface 117 is located closer to the Y1 side than the Y1-side plane of the superconductor layer 200, and the eighth surface 118 is located closer to the Y2 side than the Y2-side plane of the superconductor layer 200. The fifth surface 115 is located closer to the X1 side than the X2-side plane of the superconductor layer 200, and the sixth surface 116 is located closer to the Y2 side than the Y1-side plane of the superconductor layer 200. The superconductor layer 200 is close to the intersection line 124. In other words, the intersection line 124 is within the range of the proximity effect of the superconductor layer 200. In other words, the superconductor layer 200 is formed on the intersection line 124 between the plane including the third surface 113 and the first surface 111. Furthermore, when viewed in a direction perpendicular to the first surface 111 , the intersection line 124 has a portion that protrudes from the superconductor layer 200 .

[0021] A protective layer 131 is formed to cover the surface of the high-order topological insulator layer 100. The protective layer 131 is made of, for example, WTe ２ This is a natural oxide film.

[0022] In this embodiment, a one-dimensional conduction channel is generated at the intersection 124 between the plane including the third surface 113 of the higher-order topological insulator layer 100 and the first surface 111. Furthermore, since the superconductor layer 200 is close to the intersection 124, Majorana particles 11 appear at the intersection 124. For example, the Majorana particles 11 appear in the portion of the intersection 124 that protrudes from the superconductor layer 200.

[0023] One-dimensional conduction channels are also generated at the edges 121, 122, and 123, but the atomic arrangement is easily disordered at the edges 121, 122, and 123. In contrast, the atomic arrangement on the intersection line 124 is stable because it is located inside the first surface 111. Therefore, according to the first embodiment, a stable Majorana particle can be obtained.

[0024] Next, a method for manufacturing the quantum device 1 according to the first embodiment will be described. Figures 6 to 10 are cross-sectional views showing the method for manufacturing the quantum device 1 according to the first embodiment.

[0025] First, as shown in Fig. 6, a substrate 300 is prepared, and a superconductor layer 200 is formed on an insulating film 320 of the substrate 300. The superconductor layer 200 can be formed by, for example, a lift-off method using a mask. Examples of the material for the mask include polymethyl methacrylate (PMMA).

[0026] Next, a high-order topological insulator layer 100A is provided on the superconductor layer 200. The high-order topological insulator layer 100A will later become the high-order topological insulator layer 100. The high-order topological insulator layer 100A can be provided on the superconductor layer 200, for example, as follows.

[0027] First, tungsten (W) and tellurium (Te) are reacted in a vacuum sealed tube to produce WTe ２ Then, by repeatedly cleaving using adhesive tape, a single crystal of WTe ２ The single crystal is thinned. As a result of thinning, multiple single crystals dispersed in island-like shapes are obtained from a single single crystal. These multiple single crystals are then pressed onto a silicon substrate with an oxide film (different from substrate 300) and heated. This results in a sample consisting of multiple micron-sized single crystals scattered on the silicon substrate with an oxide film. From the multiple single crystals, one suitable for forming the high-order topological insulator layer 100 in terms of thickness and planar shape is selected as the high-order topological insulator layer 100A. Next, the high-order topological insulator layer 100A is attached to a polymer dome tool with an adhesive layer and lifted up. The polymer dome tool with an adhesive layer is, for example, made by dripping a droplet of polydimethylsiloxane (PDMS) onto a glass substrate to form a dome shape, and then attaching a polymer film on top of it. The polymer film is, for example, a polycarbonate (PC) film.

[0028] Next, the highly-ordered topological insulator layer 100A adhered to the polymer dome tool with an adhesive layer is pressed onto the superconductor layer 200, and the polymer film is melted by heating. If the polymer film is a PC film, the heating temperature is, for example, 180°C. As a result, the highly-ordered topological insulator layer 100A is provided on the superconductor layer 200 together with the polymer film. Thereafter, the polymer film is removed. If the polymer film is a PC film, the polymer film can be removed by dissolving it in chloroform, for example.

[0029] The highly-ordered topological insulator layer 100A may be directly formed by, for example, molecular beam epitaxy (MBE) or pulsed laser deposition (PLD), using, for example, a contact mask or the like to ensure that the highly-ordered topological insulator layer 100A is formed only in desired locations.

[0030] After providing the high-order topological insulator layer 100A on the superconductor layer 200, an electron beam resist film 50 covering the high-order topological insulator layer 100A and the superconductor layer 200 is formed on the insulating film 320, as shown in Fig. 7. The material of the electron beam resist film 50 is, for example, ZEP-520A manufactured by Zeon Corporation or XR-1541 manufactured by Dow Corning. The electron beam resist film 50 can be formed by, for example, spin coating.

[0031] Next, as shown in FIG. 8, an opening 51 exposing the region where the fourth surface 114 is to be formed is formed in the electron beam resist film 50 by exposure and development using an electron beam lithography device.

[0032] 9, a reactive ion etching apparatus is used to perform milling with argon (Ar) molecules to form a third surface 113, a fourth surface 114, and a sixth surface 116 on the high-order topological insulator layer 100A. The remaining portion of the high-order topological insulator layer 100A becomes the second surface 112. As a result, the high-order topological insulator layer 100 is obtained from the high-order topological insulator layer 100A. During milling, recesses may be formed in the superconductor layer 200 and the substrate 300.

[0033] 10 , the electron beam resist film 50 is removed, and a protective layer 131 is formed on the surface of the higher-order topological insulator layer 100. The protective layer 131 can be formed by, for example, natural oxidation. If the sixth surface 116 does not become flat in the process shown in FIG. 9 , the sixth surface 116 may be made flat by processing using another mask after the electron beam resist film 50 is removed.

[0034] In this manner, the quantum device 1 according to the first embodiment can be manufactured.

[0035] Here, the WTe ２ In this calculation, the Hamiltonian H(k) of Equation (1) is used (see Non-Patent Documents 1 and 2). Here, m １ , m ２ , m ３ , ν ａ , ν ｂ , ν ｃ , λ ｂ , λ ｃ , γ ｘ , γ ｚ and β ａ are material-specific parameters, and μi, τi and σi are 2×2 Pauli matrices.

[0036]

[0037] As shown in Figure 11, the Hamiltonian H(k) is calculated by the tight-binding approximation ２ The number of sites parallel to the b axis of ｂ , the number of sites parallel to the c-axis is N ｃ The size is finite to the size of (see Equation 2).

[0038]

[0039] Next, the matrix H in Equation (2) ｌａｔｔｉｃｅ (k ａ ) was diagonalized. １ , m ２ , m ３ , ν ａ , ν ｂ , ν ｃ , λ ｂ , λ ｃ, γ ｘ , γ ｚ and β ａ WTe ２ In this way, the wave number k ａ For 8 x N ｂ ×N ｃ Eigenvalues ​​E ｎ (k ａ ) and the eigenvector Ψ ｎ (k ａ ) is obtained.

[0040] Then, the eigenenergy (eigenvalue E ｎ (k ａ )) with wave number k ａ Plotting the energy dispersion of the entire system as a function of wavenumber gives the energy dispersion of the entire system. ｎ (k ａ ) ∝ k ａ ) is the square of the absolute value of the eigenvector corresponding to state n (|Ψ ｎ (k ａ ) | ２ ) is plotted as a contour line. ２ It is clear where the electron is located.

[0041] The calculation results for the higher-order topological insulator layer 100 are shown in Figures 13 and 14. In Figures 13 and 14, the brighter the area, the more likely electrons are to exist. In this calculation, as shown in Figure 12, the number of sites N, which corresponds to the distance between the third surface 113 and the fifth surface 115, ｂ１ is 50, and the number of sites N corresponding to the distance between the third surface 113 and the sixth surface 116 is ｂ２ is 50, and the number of sites N corresponding to the distance between the first surface 111 and the second surface 112 is ｃ１ 5, and the number of sites N corresponding to the distance between the first surface 111 and the fourth surface 114 ｃ２ was set to 2. As shown in Fig. 13, electrons are likely to exist not only in the portion corresponding to side 121 and the portion corresponding to side 122, but also in the portion corresponding to side 123 and the portion corresponding to intersection line 124, as shown in Fig. 14. This calculation result also shows that a one-dimensional conduction channel is generated at intersection line 124.

[0042] Second Embodiment A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration between the substrate 300 and the superconductor layer 200. FIG. 15 is a plan view showing a quantum device according to the second embodiment. FIG. 16 is a cross-sectional view showing a quantum device according to the second embodiment. In FIG. 15, the protective layer is seen through. FIG. 16 corresponds to a cross-sectional view taken along line XVI-XVI in FIG. 15.

[0043] In the quantum device 2 according to the second embodiment, a hexagonal boron nitride (h-BN) layer 400 is provided on an insulating film 320 of a substrate 300, and a superconductor layer 200 and a higher-order topological insulator layer 100 are provided on the hexagonal boron nitride layer 400. The hexagonal boron nitride layer 400 can be fabricated from a single crystal of h-BN, for example, by a method similar to that for the higher-order topological insulator layer 100A in the first embodiment. The hexagonal boron nitride layer 400 may also be fabricated by chemical vapor deposition (CVD).

[0044] The other configurations are the same as those of the first embodiment.

[0045] The second embodiment can also achieve the same effects as the first embodiment. Furthermore, according to the second embodiment, the hexagonal boron nitride layer 400 is provided, which can improve the electron transport properties of the higher-order topological insulator layer 100.

[0046] Third Embodiment A third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the protective layer. Fig. 17 is a cross-sectional view showing a quantum device according to the third embodiment.

[0047] The quantum device 3 according to the third embodiment has a protective layer 132 instead of the protective layer 131. In addition, the electron beam resist film 50 used during the manufacturing process of the first embodiment remains without being removed. The protective layer 132 has a portion that fills the inside of the opening 51 and a portion on top of the electron beam resist film 50. The protective layer 131 is, for example, a parylene layer.

[0048] The other configurations are the same as those of the first embodiment.

[0049] The third embodiment can also achieve the same effects as the first embodiment. Furthermore, even if the electron beam resist film 50 is difficult to remove, it does not need to be removed. Therefore, damage and the like that may occur when removing the electron beam resist film 50 can be avoided.

[0050] (Fourth Embodiment) A fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the configuration of the high-order topological insulator layer. Fig. 18 is a perspective view showing a high-order topological insulator layer in the fourth embodiment. Fig. 19 is a bottom view showing a high-order topological insulator layer and a superconductor layer in the fourth embodiment.

[0051] In the fourth embodiment, the high-order topological insulator layer 100 has multiple sets (three sets in this case) of the second surface 112, the third surface 113, and the fourth surface 114. Therefore, there are multiple (three in this case) intersection lines 124 between the plane including the third surface and the first surface. The superconductor layer 200 is adjacent to each of the intersection lines 124.

[0052] The other configurations are the same as those of the first embodiment.

[0053] The fourth embodiment can also achieve the same effects as the first embodiment. Furthermore, in the fourth embodiment, a plurality of one-dimensional conduction channels can be formed on one first surface 111 of the higher-order topological insulator layer 100. Therefore, a large number of Majorana particles 11 can appear. Therefore, the fourth embodiment is suitable for increasing the number of quantum bits and increasing the density.

[0054] It is not necessary that one superconductor layer 200 is adjacent to all of the intersections 124, and the superconductor layers adjacent to the respective intersections 124 may be independently spaced apart from each other. For example, three superconductor layers 200 may be provided.

[0055] The material of the high-order topological insulator layer 100 is WTe ２ For example, the material of the high-order topological insulator layer 100 is MoTe ２ The high-order topological insulator layer 100 may be a multilayer MoTe ２ layer, the intersection line 124 is MoTe ２Furthermore, when the high-order topological insulator layer 100 is a multilayer Bi layer, the intersection line 124 is preferably parallel to the

[111] axis of Bi.

[0056] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0057] 1, 2, 3: Quantum device 11: Majorana particle 100, 100A: High-order topological insulator layer 121, 122, 123: Edge 124: Intersection 200: Superconductor layer 300: Substrate 400: Hexagonal boron nitride layer

Claims

1. A layer of a high-order topological insulator; A superconductor layer; having The high-order topological insulator layer is a first surface and a second surface that are parallel to each other; a third surface that intersects with the second surface and is located closer to the first surface than the second surface; a fourth surface that intersects with the third surface and is parallel to the first surface and the second surface; having A quantum device, characterized in that the superconductor layer is formed on an intersection line between a plane including the third surface and the first surface.

2. 2. The quantum device according to claim 1, wherein, when viewed in a direction perpendicular to the first surface, the intersection line has a portion that protrudes from the superconductor layer.

3. The quantum device according to claim 1 or 2, wherein the third surface intersects with the second surface at a right angle.

4. The quantum device according to claim 1 or 2, wherein the fourth surface intersects with the third surface at a right angle.

5. the high-order topological insulator layer has a plurality of sets of the second surface, the third surface, and the fourth surface; 3. The quantum device according to claim 1, wherein the superconductor layer is adjacent to an intersection line between the first surface and a plane including each of the third surfaces.

6. The high-order topological insulator layer is a multi-layer WTe ２ Layer or multi-layer MoTe ２ 3. The quantum device of claim 1, further comprising a layer.

7. By processing a high-order topological insulator layer having a first surface, a second surface parallel to the first surface; a third surface that intersects with the second surface and is located closer to the first surface than the second surface; a fourth surface that intersects with the third surface and is parallel to the first surface and the second surface; and forming forming a superconductor layer on an intersection line between a plane including the third surface and the first surface; A method for manufacturing a quantum device comprising the steps of: