Method for manufacturing semiconductor device

Abstract

This method for manufacturing semiconductor device includes: forming an oxide semiconductor layer on a substrate through the sputtering method; placing the substrate having the oxide semiconductor layer formed thereon in a heating furnace with a heating medium maintained at a set temperature in advance to apply first heating processing to the oxide semiconductor layer; forming a gate insulation layer on the oxide semiconductor layer after the first heating processing; and forming a gate electrode on the gate insulation layer. During the placement of the substrate in the heating furnace, a temperature decrease of the heating medium is suppressed within 15% of the set temperature.

Description

Semiconductor device manufacturing method

[0001] One embodiment of the present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device using an oxide semiconductor as a channel.

[0002] In recent years, development of semiconductor devices using oxide semiconductors for the channel instead of amorphous silicon, polysilicon, and single-crystal silicon has been progressing (e.g., Patent Documents 1 to 6). Semiconductor devices using oxide semiconductors can be formed using a simple structure and a low-temperature process, similar to semiconductor devices using amorphous silicon for the channel. It is known that semiconductor devices using oxide semiconductors for the channel have higher field-effect mobility than semiconductor devices using amorphous silicon for the channel.

[0003] JP 2021-141338 A JP 2014-099601 A JP 2021-153196 A JP 2018-006730 A JP 2016-184771 A JP 2021-108405 A

[0004] As the oxide semiconductor, either an amorphous semiconductor or a crystalline semiconductor can be used. In particular, a crystalline semiconductor has the advantage that oxygen vacancies are less likely to be formed than in an amorphous semiconductor. Therefore, in recent years, the development of a semiconductor device using a crystalline oxide semiconductor has attracted attention. Since the characteristics of a semiconductor device using a crystalline oxide semiconductor vary significantly depending on the crystallinity of the channel portion, there is an urgent need to establish a process for forming an oxide semiconductor with good crystallinity.

[0005] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high reliability and field-effect mobility.

[0006] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming an oxide semiconductor layer on a substrate by a sputtering method, placing the substrate on which the oxide semiconductor layer has been formed in a heating furnace having a heating medium maintained at a preset temperature, performing a first heating treatment on the oxide semiconductor layer, forming a gate insulating layer on the oxide semiconductor layer after the first heating treatment, and forming a gate electrode on the gate insulating layer, and when placing the substrate in the heating furnace, suppressing a temperature drop of the heating medium to within 15% of the preset temperature.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer by a sputtering method, and placing the substrate on which the oxide semiconductor layer has been formed in a heating furnace having a heating medium maintained at a preset temperature to perform a heat treatment on the oxide semiconductor layer, wherein when placing the substrate in the heating furnace, a temperature drop of the heating medium is kept to within 15% of the preset temperature.

[0008] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; FIG. 3 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 8 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 12 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; 1 is a diagram showing electrical characteristics (Id-Vg characteristics) of a semiconductor device according to one embodiment of the present invention; 2 is a diagram showing electrical characteristics (Id-Vg characteristics) of a semiconductor device according to one embodiment of the present invention; 3 is a diagram showing electrical characteristics (Id-Vg characteristics) of a semiconductor device according to one embodiment of the present invention; 4 is a diagram showing electrical characteristics of a semiconductor device when OS annealing is performed under different conditions;10A and 10B are diagrams showing electrical characteristics of semiconductor devices when OS annealing is performed under different conditions.

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." For convenience of explanation, the terms "up" and "downward" are used in the following description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. The expression "pixel electrode above a transistor" may refer to a positional relationship in which the transistor and the pixel electrode do not overlap in a planar view. On the other hand, the expression "pixel electrode vertically above a transistor" refers to a positional relationship in which the transistor and the pixel electrode overlap in a planar view.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] 1 to 11, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to the following embodiment may be a transistor used in a display device, or may be a transistor used in an integrated circuit (IC) such as a microprocessor (MPU), or a memory circuit.

[0015] [Configuration of Semiconductor Device 10] The configuration of a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view showing an overview of a semiconductor device 10 according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of a semiconductor device 10 according to one embodiment of the present invention.

[0016] 1 , a semiconductor device 10 is provided above a substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer (also referred to as a metal oxide layer) 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not distinguished from each other, they may be collectively referred to as a source-drain electrode 200.

[0017] The gate electrode 105 is provided on the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the metal oxide layer 130 is referred to as the lower surface 142. The edge of the metal oxide layer 130 is approximately aligned with the edge of the oxide semiconductor layer 140.

[0018] In this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100 .

[0019] In this embodiment, a configuration in which the metal oxide layer 130 is in contact with the gate insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is exemplified, but the present invention is not limited to this configuration. Another layer may be provided between the gate insulating layer 120 and the metal oxide layer 130. Another layer may be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0020] 1, the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140 are aligned in a straight line, but this configuration is not limiting. The angle of the side surface of the metal oxide layer 130 with respect to the main surface of the substrate 100 may be different from the angle of the side surface of the oxide semiconductor layer 140. The cross-sectional shape of the side surface of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0021] The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the major surfaces of the oxide semiconductor layer 140, the surface in contact with the gate insulating layer 150 is referred to as an upper surface 141. The surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 have openings 171 and 173 that reach the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0022] The gate electrode 105 functions as a bottom gate of the semiconductor device 10 and as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 functions as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 function as gate insulating layers for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide mainly composed of aluminum, and functions as a gas barrier film that blocks gases such as oxygen and hydrogen.

[0023] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 140 vertically below the gate electrode 160. The source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has the physical properties of a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has the physical properties of a conductor.

[0024] The gate electrode 160 functions as a light-shielding film for the top gate of the semiconductor device 10 and the oxide semiconductor layer 140. The gate insulating layer 150 functions as a gate insulating layer for the top gate and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layers 170 and 180 insulate the gate electrode 160 from the source / drain electrodes 200 and have a function of reducing parasitic capacitance between them. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, when the gate electrode 105 is used simply as a light-shielding film, the gate electrode 105 may be in a floating state without being supplied with a specific voltage. In other words, the gate electrode 105 may be simply a "light-shielding film."

[0025] In this embodiment, a dual-gate transistor in which gate electrodes are provided both above and below the oxide semiconductor layer is exemplified as the semiconductor device 10, but the present invention is not limited to this configuration. For example, the semiconductor device 10 may be a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0026] As shown in FIG. 2 , in a plan view, the plane pattern of the metal oxide layer 130 is substantially the same as the plane pattern of the oxide semiconductor layer 140. Referring to FIGS. 1 and 2 , the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In particular, in this embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In the D1 direction, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of a region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0027] In the present embodiment, a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130 has been exemplified, but the present invention is not limited to this configuration. For example, a portion of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered with the metal oxide layer 130, and all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered with the metal oxide layer 130. In other words, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a portion of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered with the metal oxide layer 130, and the other portion of the lower surface 142 may be in contact with the metal oxide layer 130.

[0028] In this embodiment, a configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are provided in the gate insulating layer 150 has been exemplified, but the present invention is not limited to this configuration. That is, the gate insulating layer 150 may be patterned into a shape different from the shape shown in FIG. 1 . For example, the gate insulating layer 150 may be patterned so as to expose all or part of the oxide semiconductor layer 140 in the source region S and the drain region D. That is, the gate insulating layer 150 may be removed from the source region S and the drain region D, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact with each other in these regions.

[0029] 2 illustrates a configuration in which the source / drain electrode 200 does not overlap the gate electrode 105 or the gate electrode 160 in a plan view, but the present invention is not limited to this configuration. For example, the source / drain electrode 200 may overlap at least one of the gate electrode 105 or the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0030] [Materials of Each Component of the Semiconductor Device 10] The substrate 100 may be a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate. When the substrate 100 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, may be used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emission display, the substrate 100 does not need to be transparent, and therefore impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit other than a display device, the substrate 100 may be a non-optically transparent substrate, such as a semiconductor substrate, such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate, such as a stainless steel substrate.

[0031] Common metal materials are used for the gate electrode 105, the gate electrode 160, and the source / drain electrodes 200. Examples of materials that can be used for these components include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The above materials may be used for the gate electrode 105, the gate electrode 160, and the source / drain electrodes 200 in a single layer or a stacked layer.

[0032] Common insulating materials are used for the gate insulating layers 110, 120 and the insulating layers 170, 180. For example, inorganic insulating layers such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), and aluminum nitride (AlNx) are used for these insulating layers.

[0033] Of the above insulating layers, an insulating layer containing oxygen is used as the gate insulating layer 150. For example, an inorganic insulating layer such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), or aluminum oxynitride (AlOxNy) is used as the gate insulating layer 150.

[0034] An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 120. The temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 120 releases oxygen at the temperature of the heat treatment performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100, for example.

[0035] An insulating layer with few defects is used as the gate insulating layer 150. For example, when the oxygen composition ratio in the gate insulating layer 150 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiOx) is used for each of the gate insulating layer 150 and the insulating layer 180, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating layer 150.

[0036] The above-mentioned SiOxNy and AlOxNy are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio (x>y) smaller than that of oxygen (O). SiNxOy and AlNxOy are silicon compounds and aluminum compounds containing oxygen in a ratio (x>y) smaller than that of nitrogen.

[0037] The metal oxide layer 130 is made of a metal oxide (metal oxide) containing aluminum as a primary component. For example, an inorganic insulating layer such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx) is used as the metal oxide layer 130. The term "metal oxide layer containing aluminum as a primary component" means that the proportion of aluminum contained in the metal oxide layer 130 is 1% or more of the entire metal oxide layer 130. The proportion of aluminum contained in the metal oxide layer 130 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0038] The oxide semiconductor layer 140 may be made of a metal oxide having semiconductor properties. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 140. The ratio of indium to the entire oxide semiconductor layer 140 is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanoid may be used as the oxide semiconductor layer 140. Elements other than those listed above may also be used as the oxide semiconductor layer 140.

[0039] In this embodiment, the oxide semiconductor layer 140 has a polycrystalline structure. That is, the oxide semiconductor layer 140 in this embodiment is formed using an oxide semiconductor formed using a polycrystalline oxide semiconductor (poly-OS) technique. The poly-OS technique refers to a technique for forming an oxide semiconductor layer having a polycrystalline structure. In this embodiment, as will be described later, the oxide semiconductor layer 140 formed by a sputtering method is subjected to heat treatment to crystallize the oxide semiconductor layer 140.

[0040] The oxide semiconductor layer 140 of this embodiment has an indium ratio of 50% or more, and therefore oxygen vacancies are easily formed. On the other hand, oxygen vacancies are less likely to form in a crystalline oxide semiconductor than in an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 140 has the advantage that oxygen vacancies are less likely to form, even though the indium ratio is 50% or more.

[0041] [Manufacturing Method of Semiconductor Device 10] A manufacturing method of the semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 3 to 11. Figure 3 is a sequence diagram showing a manufacturing method of the semiconductor device 10 according to one embodiment of the present invention. Figures 4 to 11 are cross-sectional views showing a manufacturing method of the semiconductor device 10 according to one embodiment of the present invention. In the following description of the manufacturing method, a manufacturing method of the semiconductor device 10 in which aluminum oxide is used as the metal oxide layer 130 will be described.

[0042] 3 and 4 , a gate electrode 105 is formed on a substrate 100 as a bottom gate, and gate insulating layers 110 and 120 are formed on the gate electrode 105 (step S1001 in FIG. 3 ). For example, silicon nitride is formed as the gate insulating layer 110. For example, silicon oxide is formed as the gate insulating layer 120. The gate insulating layers 110 and 120 are formed by a chemical vapor deposition (CVD) method. In this specification, forming a film on a substrate by a method such as sputtering or CVD is expressed as "forming a thin film," but this expression is used in the same sense as "forming a thin film."

[0043] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities diffusing from, for example, the substrate 100 side toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide that has the physical property of releasing oxygen by heat treatment.

[0044] 3 and 5, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 (step S1002 in FIG. 3). In this embodiment, the metal oxide layer 130 and the oxide semiconductor layer 140 are formed by a sputtering method. In particular, the oxide semiconductor layer 140 is formed by sputtering using a target formed of a crystalline oxide semiconductor.

[0045] The thickness of the metal oxide layer 130 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has high gas barrier properties.

[0046] In this embodiment, aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

[0047] As described above, the oxide semiconductor layer 140 of this embodiment has an indium ratio of 50% or more, which allows for the realization of a high-mobility semiconductor device 10. However, oxygen is easily reduced, and oxygen vacancies are easily formed in the layer. Therefore, using the metal oxide layer 130 to block hydrogen released from the gate insulating layer 120 is preferable in terms of suppressing the reduction of the oxide semiconductor layer 140.

[0048] Furthermore, after the oxide semiconductor layer 140 is formed, various manufacturing processes (such as a patterning step or an etching step) may cause more oxygen vacancies to form in the upper layer of the oxide semiconductor layer 140 than in the lower layer. In other words, the oxygen vacancies in the oxide semiconductor layer 140 are distributed unevenly in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen vacancies formed in the upper layer of the oxide semiconductor layer 140, excessive oxygen is supplied to the lower layer of the oxide semiconductor layer 140. As a result, the excessive supply of oxygen may form defect levels different from the oxygen vacancies, which may lead to phenomena such as fluctuations in characteristics in reliability tests or a decrease in field-effect mobility. Therefore, it can be said that blocking oxygen released from the gate insulating layer 120 by the metal oxide layer 130 is also preferable in terms of suppressing excessive oxygen supply to the lower layer of the oxide semiconductor layer 140.

[0049] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. The oxide semiconductor layer 140 is amorphous before heat treatment (OS annealing) described later.

[0050] When the oxide semiconductor layer 140 is crystallized by OS annealing, which will be described later, the oxide semiconductor layer 140 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after being formed by sputtering and before being subjected to OS annealing. That is, the oxide semiconductor layer 140 is preferably formed under conditions that prevent the oxide semiconductor layer 140 from crystallizing immediately after formation as much as possible. For example, when the oxide semiconductor layer 140 is formed by sputtering, it is desirable to form the oxide semiconductor layer 140 while controlling the temperature of a target object (including the substrate 100 and a structure formed thereon). Note that, although the target object is actually subjected to temperature control, the temperature of the target object can be considered to be substantially controlled because the structure formed on the substrate 100 is very thin. Therefore, in the following description, the target object may be simply referred to as a "substrate."

[0051] When a thin film is formed on a substrate by sputtering, ions generated in plasma and atoms recoiled from the sputtering target collide with an object to be formed (specifically, a structure formed on the substrate 100), causing the temperature of the substrate to rise during the thin film formation process. If the temperature of the substrate rises during the thin film formation process, the oxide semiconductor layer 140 contains microcrystals immediately after the formation, which inhibits crystallization by subsequent OS annealing.

[0052] In order to control the temperature of the substrate when the oxide semiconductor layer 140 is formed (hereinafter referred to as the "film formation temperature"), for example, the thin film can be formed while cooling the substrate. For example, the substrate can be cooled from the surface opposite to the formation surface so that the film formation temperature becomes 100°C or lower, 70°C or lower, 50°C or lower, or 30°C or lower. In particular, the film formation temperature of the oxide semiconductor layer 140 in this embodiment is preferably 50°C or lower. In this embodiment, the oxide semiconductor layer 140 is formed at a film formation temperature of 50°C or lower, and OS annealing, which will be described later, is performed at a heating temperature of 400°C or higher. As described above, in this embodiment, the difference between the temperature when the oxide semiconductor layer 140 is formed and the temperature when the oxide semiconductor layer 140 is subjected to OS annealing is preferably 350°C or higher. By forming the oxide semiconductor layer 140 while cooling the substrate, the oxide semiconductor layer 140 containing few crystalline components immediately after formation can be obtained.

[0053] Next, as shown in FIGS. 3 and 6 , a pattern (OS pattern) including the oxide semiconductor layer 140 is formed (Step S1003 in FIG. 3 ). Although not shown, a resist mask is formed over the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 may be etched by wet etching or dry etching. In the wet etching, for example, an acidic etchant can be used. Specifically, oxalic acid or hydrofluoric acid can be used as the etchant.

[0054] After the oxide semiconductor layer 140 is patterned, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 (Step S1004 in FIG. 3 ). In the OS annealing, the oxide semiconductor layer 140 is subjected to heat treatment in an air atmosphere at a temperature of 400° C. to 450° C., thereby crystallizing the amorphous oxide semiconductor layer 140. The heating atmosphere is not limited to the air atmosphere, but is preferably an oxidizing atmosphere (an atmosphere containing oxygen). The oxidizing atmosphere is more preferably a moist atmosphere containing water vapor (specifically, a moist air atmosphere). The heat treatment may be performed for 60 minutes or more, and may be performed for 60 minutes to 90 minutes.

[0055] In this embodiment, a substrate on which a patterned oxide semiconductor layer 140 has been formed is placed in a heating furnace having a heating medium (a support plate in this embodiment) maintained at a preset temperature (400° C. or higher and 450° C. or lower). In this embodiment, the set temperature of the heating medium is 400° C. The support plate as a heating medium has the roles of supporting the substrate and heating the substrate and the coating (including the oxide semiconductor layer 140) formed on the substrate. When the substrate on which the oxide semiconductor layer 140 has been formed is placed on the support plate, the oxide semiconductor layer 140 is rapidly heated.

[0056] In this embodiment, when the substrate is placed in the heating furnace, the temperature drop of the support plate is suppressed to within 15%, 10%, or 5% of the set temperature. That is, in this embodiment, when OS annealing is performed on the oxide semiconductor layer 140, the temperature of the support plate is controlled so that the oxide semiconductor layer 140 reaches the set temperature in as short a time as possible. In this way, in this embodiment, heat treatment (specifically, furnace annealing) accompanied by a rapid temperature rise is performed on the oxide semiconductor layer 140.

[0057] As described above, to prevent the temperature drop of the support plate, it is preferable to create an environment in which the support plate of the heating furnace is kept out of contact with room-temperature air as much as possible. For example, by using a deep tubular heating furnace and placing the support plate far from the furnace opening, which is open to the atmosphere, a drop in the set temperature of the support plate can be prevented. Furthermore, by providing a preliminary chamber upstream of the heating furnace and setting the preliminary chamber to a temperature between 350°C and 450°C (preferably the same temperature as the set temperature of the heating furnace), a drop in the temperature of the support plate in the heating furnace can be prevented. In this case, when the substrate is loaded into the heating furnace, it is loaded without leaving the preliminary chamber. This is to prevent the temperature of the substrate from rising in the preliminary chamber.

[0058] Although the above measures focus on preventing a temperature decrease of the support plate due to a decrease in the internal temperature (environmental temperature) of the heating furnace, it is also preferable to suppress a direct temperature decrease of the support plate caused by placing the substrate. For example, by increasing the heat capacity of the support plate as much as possible, a temperature decrease of the support plate when it comes into contact with the substrate can be suppressed. Furthermore, for example, the substrate can be preheated before being placed on the support plate. In this case, the set temperature (heating temperature) of the preheating is preferably within a temperature range in which crystallization of the oxide semiconductor layer 140 does not start. The reason for setting the preheating temperature within the above temperature range is to suppress the formation of microcrystals inside the oxide semiconductor layer 140 before the actual OS annealing.

[0059] Furthermore, when placing a substrate on the support plate, the temperature of the support plate may be temporarily increased by 15%, 10%, or 5%. That is, the temperature of the support plate may be set higher in advance in anticipation of a temperature drop in the support plate due to the placement of the substrate. In this case, the time required for the substrate to reach the heating temperature can be shortened by returning the set temperature of the support plate to a predetermined set temperature (400°C in this embodiment) when the substrate is placed. The support plate may also be divided into blocks, and the temperature may be set for each block. In this case, the temperature of the entire support plate may be controlled collectively, or each block may be controlled individually. For example, since the temperature drop in the center of the support plate is particularly large, the temperature of only the center of the support plate may be set higher in advance as described above.

[0060] As described above, in this embodiment, when the substrate is placed in the heating furnace, the temperature drop of the support plate is suppressed to within 15%, 10%, or 5% of the set temperature, thereby rapidly heating and crystallizing the oxide semiconductor layer 140. By making the gradient of the temperature increase of the oxide semiconductor layer 140 during OS annealing as steep as possible, the field-effect mobility and reliability of the semiconductor device 10 can be improved. This point will be described later.

[0061] Although this embodiment shows an example in which OS annealing is performed after the OS pattern is formed, the present invention is not limited to this example, and OS annealing may be performed on the oxide semiconductor layer 140 before the OS pattern is formed. In this case, dry etching is preferably used for the etching process because the OS pattern is formed by etching the crystallized oxide semiconductor layer 140.

[0062] In this embodiment, an example in which a support plate is used as a heating medium for heating the oxide semiconductor layer 140 during OS annealing has been described. However, the present invention is not limited to this example, and the heating medium may be air. Specifically, a support member for supporting the substrate is provided in a heating furnace, and the substrate is supported in a state in which most of the substrate is in contact with air, so that the substrate can be heated using the heated air as a heating medium. In this case, the support member may be, for example, a pin-shaped member that supports the substrate from below in point contact, or a frame-shaped member that supports the edge of the substrate.

[0063] Next, as shown in FIGS. 3 and 7 , a pattern (AlO pattern) composed of the metal oxide layer 130 is formed (step S1005 in FIG. 3 ). The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. The metal oxide layer 130 may be etched by wet etching or dry etching. For wet etching, diluted hydrofluoric acid (DHF) is used, for example. By etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted.

[0064] Although this embodiment shows an example in which an AlO pattern is formed after an OS pattern is formed using the OS pattern as a mask, it is also possible to form the OS pattern and the AlO pattern at the same time. In this case, the oxide semiconductor layer 140 and the metal oxide layer 130 may be etched at the same time using the same resist mask in step S1003 of FIG. 3. However, the present invention is not limited to this example, and it is also possible to omit the formation of the AlO pattern and leave the metal oxide layer 130 as it is.

[0065] Next, as shown in FIGS. 3 and 8 , a gate insulating layer 150 is formed (step S1006 in FIG. 3 ). For example, a silicon oxide layer is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as the gate insulating layer 150 as described above, the gate insulating layer 150 may be formed at a temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0066] Next, in this embodiment, after the gate insulating layer 150 is formed, oxygen is implanted into a part of the gate insulating layer 150. Specifically, after the gate insulating layer 150 is formed, a metal oxide layer 190 is formed on the gate insulating layer 150 (step S1007 in FIG. 3). The metal oxide layer 190 is formed by a sputtering method. By forming the metal oxide layer 190, oxygen is implanted into the gate insulating layer 150.

[0067] The thickness of the metal oxide layer 190 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 190. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the metal oxide layer 190 prevents oxygen implanted into the gate insulating layer 150 from diffusing outward during the heat treatment described below.

[0068] When the metal oxide layer 190 is formed by sputtering, the process gas used in the sputtering remains in the film of the metal oxide layer 190. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 190. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 190.

[0069] Next, with the metal oxide layer 190 formed on the gate insulating layer 150, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 (step S1008 in FIG. 3 ). In other words, the heat treatment (oxidation annealing) is performed on the metal oxide layer 130 and the oxide semiconductor layer 140 patterned as described above. During the process from when the oxide semiconductor layer 140 is formed until when the gate insulating layer 150 is formed on the oxide semiconductor layer 140, oxygen vacancies may occur on the top surface 141 and the side surface 143 of the oxide semiconductor layer 140. By the oxidation annealing, oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired.

[0070] Oxygen released from the gate insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130, and therefore oxygen is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layer 120 diffuses from an area where the metal oxide layer 130 is not formed to the gate insulating layer 150 provided on the gate insulating layer 120, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, the oxygen released from the gate insulating layer 120 is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140, and is supplied mainly to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. Furthermore, oxygen released from the gate insulating layer 150 by the oxidation annealing is supplied to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. Although hydrogen may be released from the gate insulating layers 110 and 120 by the oxidation annealing, the hydrogen is blocked by the metal oxide layer 130.

[0071] As described above, oxidation annealing can suppress the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140, which has a small amount of oxygen vacancies, while supplying oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140, which have a relatively large amount of oxygen vacancies.

[0072] Similarly, during the oxidation annealing, oxygen implanted into the gate insulating layer 150 is blocked by the metal oxide layer 190, and is therefore prevented from being released into the atmosphere. Therefore, oxygen is efficiently supplied to the oxide semiconductor layer 140 by the oxidation annealing, and oxygen vacancies are repaired.

[0073] Next, as shown in FIGS. 3 and 9 , after the oxidation annealing, the metal oxide layer 190 is etched (removed) (step S1009 in FIG. 3 ). The etching of the metal oxide layer 190 may be wet etching or dry etching. In wet etching, diluted hydrofluoric acid (DHF) is used, for example. The metal oxide layer 190 is removed without using a mask. That is, the entire metal oxide layer 190 is removed by the etching process. In other words, the etching process removes all of the metal oxide layer 190 in the region that overlaps with the oxide semiconductor layer 140 formed in a certain pattern in a plan view.

[0074] 3 and 10, a gate electrode 160 is formed on the gate insulating layer 150 (step S1010 in FIG. 3). The gate electrode 160 is formed by patterning a metal layer formed by sputtering or atomic layer deposition. As described above, the gate electrode 160 is formed so as to contact the gate insulating layer 150 exposed by removing the metal oxide layer 190.

[0075] With the gate electrode 160 formed, the resistance of the source region S and the drain region D of the oxide semiconductor layer 140 is reduced (step S1011 in FIG. 3 ). Specifically, impurities are implanted into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), or boron (B) is implanted into the oxide semiconductor layer 140 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 140. Because the gate electrode 160 is provided above the oxide semiconductor layer 140, which functions as the channel region CH of the semiconductor device 10, impurities are not implanted into the oxide semiconductor layer 140 in the channel region CH.

[0076] Next, as shown in FIGS. 3 and 11 , insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 (step S1012 in FIG. 3 ). The insulating layers 170 and 180 are formed by a CVD method. For example, a silicon nitride layer is formed as the insulating layer 170, and a silicon oxide layer is formed as the insulating layer 180. The materials used for the insulating layers 170 and 180 are not limited to the above materials. In this embodiment, the thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0077] 3 and 12, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 (step S1013 in FIG. 3). The opening 171 exposes the oxide semiconductor layer 140 in the source region S. The opening 173 exposes the oxide semiconductor layer 140 in the drain region D. Source and drain electrodes 200 are formed on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 (step S1014 in FIG. 3), thereby completing the semiconductor device 10 shown in FIG.

[0078] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the field effect mobility is 50 cm ２ / Vs or more, 55cm ２ / Vs or more, or 60 cm ２ In this embodiment, the "field effect mobility" refers to the field effect mobility in the saturation region of the semiconductor device 10, and refers to the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate electrode.

[0079] Second Embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the first embodiment will be described. The structure of the semiconductor device 10 of this embodiment is identical in appearance to the semiconductor device 10 described in the first embodiment. In this embodiment, the description will focus on the differences from the first embodiment.

[0080] 13 is a sequence diagram showing a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. As shown in FIG. 13, in this embodiment, two steps, namely, step S1007 (AlOx formation) and step S1009 (AlOx removal) shown in FIG. 3, are omitted. That is, in this embodiment, after the gate insulating layer 150 is formed, oxidation annealing is performed in this state. By this oxidation annealing, oxygen released from the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and oxygen vacancies contained in the oxide semiconductor layer 140 are repaired. The role of the metal oxide layer 130 in this process is the same as in the first embodiment, and therefore will not be described here.

[0081] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 30 cm ２ / Vs or more, 35cm ２ / Vs or more, or 40 cm ２ In this embodiment, the field-effect mobility is defined in the same way as in the first embodiment.

[0082] Third Embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the first embodiment will be described. The structure of a semiconductor device 10a of this embodiment is a structure in which the metal oxide layer 130 is omitted from the semiconductor device 10 described in the first embodiment. In this embodiment, the description will focus on differences from the first embodiment, and the same components will be denoted by the same reference numerals and detailed description thereof will be omitted.

[0083] [Method of Manufacturing Semiconductor Device 10a] A method of manufacturing the semiconductor device 10a according to one embodiment of the present invention will be described with reference to Figures 14 to 22. Figure 14 is a sequence diagram showing the method of manufacturing the semiconductor device 10a according to one embodiment of the present invention. Figures 15 to 22 are cross-sectional views showing the method of manufacturing the semiconductor device 10a according to one embodiment of the present invention.

[0084] 14 and 15 , a gate electrode 105 is formed as a bottom gate on a substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 (step S1001 in FIG. 14 ). The process of step S1001 is the same as that of the first embodiment. In this embodiment, after the gate insulating layer 120 is formed, an oxide semiconductor layer 140 is formed on the gate insulating layer 120 (step S3002 in FIG. 14 ).

[0085] In this embodiment, the oxide semiconductor layer 140 is formed by sputtering. Specifically, the oxide semiconductor layer 140 is formed by sputtering using a target formed of a crystalline oxide semiconductor. In this embodiment, the formation process and configuration of the oxide semiconductor layer 140 are the same as those in the first embodiment, and therefore detailed description thereof will be omitted. For example, in this embodiment, the oxide semiconductor layer 140 is formed by sputtering while cooling the object to be formed (the substrate 100 and the structure formed thereon) so that the temperature thereof is 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less.

[0086] 14 and 16, a pattern (OS pattern) including an oxide semiconductor layer 140 is formed (Step S1003 in FIG. 14). After the pattern formation of the oxide semiconductor layer 140 is completed, the oxide semiconductor layer 140 is subjected to heat treatment (OS annealing) (Step S1004 in FIG. 14). The processes of Steps S1003 and S1004 are the same as those in the first embodiment.

[0087] Through the above steps, the process up to the step of crystallizing the oxide semiconductor layer 140 is completed. The manufacturing process from step S1004 onwards is the same as steps S1006 to S1014 described with reference to FIG. 3 in the first embodiment, and therefore redundant description will be omitted. When the manufacturing process up to step S1014 is completed, the semiconductor device 10a having the structure shown in FIG. 17 is completed. Compared to the semiconductor device 10 of the first embodiment, the semiconductor device 10a of this embodiment does not have the metal oxide layer 130 below the oxide semiconductor layer 140. However, since the oxygen vacancies contained in the oxide semiconductor layer 140 are sufficiently repaired by the steps S1007 to S1009 of FIG. 14, the field-effect mobility and reliability of the semiconductor device 10a are improved.

[0088] In the semiconductor device 10a manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the field effect mobility is 30 cm ２ / Vs or more, 35cm ２ / Vs or more, or 40 cm ２ In this embodiment, the field-effect mobility is defined in the same way as in the first embodiment.

[0089] 18 to 22, a display device using a semiconductor device according to one embodiment of the present invention will be described. In the following embodiment, a configuration in which each of the semiconductor devices described in the first to third embodiments is applied to the circuitry of a liquid crystal display device will be described.

[0090] [Overview of Display Device 20] Fig. 18 is a plan view showing an overview of a display device 20 according to one embodiment of the present invention. As shown in Fig. 18, the display device 20 has an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. A plurality of pixel circuits 301 are arranged in a matrix in a liquid crystal region 22 surrounded by the seal portion 310. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 311, which will be described later, in a plan view.

[0091] The seal region 24 in which the seal portion 310 is provided is the region surrounding the liquid crystal region 22. The FPC 330 is provided in the terminal region 26. The terminal region 26 is a region of the array substrate 300 that is exposed from the counter substrate 320, and is provided outside the seal region 24. The outside of the seal region 24 means the outside of the region in which the seal portion 310 is provided and the region surrounded by the seal portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0092] [Circuit Configuration of Display Device 20] Figure 19 is a block diagram showing the circuit configuration of a display device 20 according to one embodiment of the present invention. As shown in Figure 19, a source driver circuit 302 is provided adjacent to the liquid crystal region 22 in the direction D1 (column direction) in which the pixel circuits 301 are arranged. Furthermore, a gate driver circuit 303 is provided adjacent to the liquid crystal region 22 in the direction D2 (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the sealing region 24. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 301 are provided.

[0093] Source wiring 304 extends from the source driver circuit 302 in the D1 direction and is connected to a plurality of pixel circuits 301 arranged in the D1 direction. Gate wiring 305 extends from the gate driver circuit 303 in the D2 direction and is connected to a plurality of pixel circuits 301 arranged in the D2 direction.

[0094] A terminal portion 306 is provided in the terminal region 26. The terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected by a connection wiring 308. When the FPC 330 is connected to the terminal portion 306, an external device and the display device 20 are connected via the FPC 330, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0095] The semiconductor device 10 shown in the first and second embodiments and the semiconductor device 10 a shown in the third embodiment are used as transistors included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0096] [Pixel Circuit 301 of Display Device 20] Fig. 20 is a circuit diagram showing a pixel circuit 301 of a display device 20 according to one embodiment of the present invention. As shown in Fig. 20, the pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311. Note that while Fig. 20 shows an example in which the semiconductor device 10 shown in the first and second embodiments is used, the semiconductor device 10a shown in the third embodiment may also be used.

[0097] The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to a gate wiring 305. The source electrode 201 is connected to a source wiring 304. The drain electrode 203 is connected to a storage capacitor 350 and a liquid crystal element 311. In this embodiment, for convenience of explanation, the electrode indicated by the reference numeral "201" is called a source electrode, and the electrode indicated by the reference numeral "203" is called a drain electrode, but the electrode indicated by the reference numeral "201" may function as a drain electrode, and the electrode indicated by the reference numeral "203" may function as a source electrode.

[0098] [Cross-sectional structure of display device 20] Fig. 21 is a cross-sectional view of a display device 20 according to one embodiment of the present invention. As shown in Fig. 21, the display device 20 is a display device that uses a semiconductor device 10. In this embodiment, a configuration in which the semiconductor device 10 is used in a pixel circuit 301 is illustrated, but the semiconductor device 10 may also be used in a peripheral circuit including a source driver circuit 302 and a gate driver circuit 303. In the following description, the configuration of the semiconductor device 10 is the same as that of the semiconductor device 10 shown in Fig. 1, and therefore a detailed description thereof will be omitted.

[0099] An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370 that is provided in common to a plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided in the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0100] 22 is a plan view of a pixel electrode 390 and a common electrode 370 of a display device 20 according to one embodiment of the present invention. As shown in FIG. 22 , the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a horizontal electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. This horizontal electric field causes liquid crystal molecules contained in the liquid crystal element 311 to operate, thereby determining the grayscale of the pixel.

[0101] Fifth Embodiment A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 23 and 24. In the following embodiment, a configuration in which each of the semiconductor devices described in the first to third embodiments is applied to the circuit of an organic EL display device will be described. The outline and circuit configuration of a display device 20a are similar to those shown in Figures 18 and 19, and therefore will not be described here.

[0102] [Pixel Circuit 301 of Display Device 20] Fig. 23 is a circuit diagram showing a pixel circuit 301a of a display device 20a according to one embodiment of the present invention. As shown in Fig. 23, the pixel circuit 301a includes elements such as a drive transistor 11, a selection transistor 12, a storage capacitor 210, and a light-emitting element DO. Note that while Fig. 23 shows an example in which the semiconductor device 10 shown in the first and second embodiments is used, the semiconductor device 10a shown in the third embodiment may also be used.

[0103] The drive transistor 11 and the select transistor 12 have the same configuration as in the semiconductor device 10. The source electrode of the select transistor 12 is connected to a signal line 211, and the gate electrode of the select transistor 12 is connected to a gate line 212. The source electrode of the drive transistor 11 is connected to an anode power line 213, and the drain electrode of the drive transistor 11 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to a cathode power line 214. The gate electrode of the drive transistor 11 is connected to the drain electrode of the select transistor 12. The storage capacitor 210 is connected to the gate and drain electrodes of the drive transistor 11. A gradation signal that determines the light emission intensity of the light-emitting element DO is supplied to the signal line 211. A signal that selects the pixel row to which the gradation signal is written is supplied to the gate line 212.

[0104] [Cross-sectional structure of display device 20] Figure 24 is a cross-sectional view of a display device 20a according to one embodiment of the present invention. The configuration of the display device 20a shown in Figure 24 is similar to that of the display device 20 shown in Figure 21, but the structure above the insulating layer 360 of the display device 20a shown in Figure 24 is different from the structure above the insulating layer 360 of the display device 20 shown in Figure 21. Below, a description of the configuration of the display device 20a shown in Figure 24 that is similar to that of the display device 20 shown in Figure 21 will be omitted, and the differences between the two will be described.

[0105] As shown in FIG. 24 , the display device 20 a has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 above an insulating layer 360. The pixel electrode 390, the light-emitting layer 392, and the common electrode 394 constitute a light-emitting element DO. The pixel electrode 390 is provided on the insulating layer 360 and inside an opening 381. An insulating layer 362 is provided on the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to a light-emitting region. In other words, the insulating layer 362 defines a pixel. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common to multiple pixels. Different materials are used for the light-emitting layer 392 depending on the display color of the pixel.

[0106] In the fourth and fifth embodiments, the semiconductor devices described in the first to third embodiments are applied to a liquid crystal display device and an organic EL display device, but each semiconductor device may also be applied to a display device other than these display devices (for example, a self-luminous display device other than an organic EL display device or an electronic paper display device). Furthermore, each of the semiconductor devices can be applied to a variety of display devices, from small and medium-sized display devices to large display devices, without any particular limitations.

[0107] The results of verification experiments carried out on the semiconductor device 10 manufactured by the method shown in the second embodiment will be described below.

[0108] Figure 25 is a graph showing the temperature tracking of the substrate relative to the support plate placed in the heating furnace. The graph shown in Figure 25 plots the temperature measured by a thermocouple placed on the formation surface (the surface on which the structure is formed) of a glass substrate placed on a support plate against time. The thermocouple was placed approximately in the center of the formation surface of the glass substrate. The set temperature of the support plate was 400°C. The thickness of the glass substrate was 0.5 mm.

[0109] 25, it can be seen that the temperature of the substrate surface of the glass substrate placed on the support plate closely follows the temperature of the support plate. Specifically, the temperature of the substrate surface reaches 370°C in about 10 seconds after the glass substrate is placed on the support plate. Thereafter, the temperature of the substrate surface gradually rises, and after about 100 seconds, it reaches the set temperature of 400°C.

[0110] In this verification experiment, the temperature of the support plate, which had been heated to 400°C, dropped slightly when the glass substrate was placed on the support plate. However, because the temperature drop of the support plate was kept within 10% (i.e., the temperature of the support plate was maintained at 360°C or higher at the time the substrate was placed), it was possible to rapidly raise the temperature of the surface of the glass substrate to 370°C. In the results shown in Figure 25, the reason the temperature of the surface of the glass substrate to be formed rose gradually to 400°C is thought to be because after the glass substrate was placed, the temperature of the support plate, which had temporarily dropped to around 370°C, took time to rise to 400°C.

[0111] As described above, the temperature of the formation surface of the glass substrate placed on the support plate rises rapidly in accordance with the temperature of the support plate. In other words, it can be said that the temperature of the oxide semiconductor layer 140 formed on the substrate 100 rises rapidly in accordance with the temperature of the support plate.

[0112] Next, we will explain the effects on the semiconductor device of this embodiment when the temperature drop of the support plate is kept within 10% of the set temperature when placing the substrate in the heating furnace for OS annealing, and when it is not kept within 10%.

[0113] [Electrical Characteristics of Semiconductor Device 10] The influence of temperature rise during OS annealing will be described using the electrical characteristics of a semiconductor device having the same structure as the semiconductor device 10 according to the second embodiment as an example.

[0114] 26 to 28 are diagrams showing the electrical characteristics (Id-Vg characteristics) of semiconductor devices when OS annealing is performed under different conditions. Specifically, FIG. 26 shows a reference example in which the present invention is not applied during OS annealing. FIGS. 27 and 28 each show an example in which the temperature drop of the support plate during OS annealing is suppressed to within 10%. Note that the results in FIG. 27 are for a case in which the heating atmosphere is a dry atmosphere. The results in FIG. 28 are for a case in which the heating atmosphere is a wet atmosphere.

[0115] The conditions for measuring the electrical characteristics shown in Figures 26 to 28 are as follows: Size of channel region CH: W / L = 4.5 μm / 3.0 μm Source-drain voltage: 0.1 V, 10 V Gate voltage: -15 V to +15 V Measurement environment: room temperature, dark room Number of measurement points: 26 points The gate voltage is applied to both gate electrode 105 and gate electrode 160 in the semiconductor device having the structure shown in Figure 2. In other words, the results shown in Figures 26 to 28 are the results when the semiconductor device is dual-gate driven.

[0116] As indicated by the arrows in the graphs of Figures 26 to 28, the vertical axis corresponding to the drain current (ID) is shown on the left side of the graph, and the vertical axis corresponding to the field-effect mobility (μsat) calculated from the drain current is shown on the right side of the graph. Of the two drain currents, the graph with the larger value is for a source-drain voltage of 10 V, and the graph with the smaller value is for a source-drain voltage of 0.1 V. The electrical characteristics of Figures 26 to 28 show so-called normally-off characteristics, in which the drain current Id begins to flow when the gate voltage Vg is slightly higher than 0 V.

[0117] In the graphs shown in FIGS. 26 to 28, the average values ​​of the field-effect mobilities calculated from the drain currents are 37.6 cm ２ / Vs, 40.5 cm ２ / Vs, and 39.9 cm ２ / Vs. That is, compared to the reference example shown in FIG. 26, the field-effect mobility values ​​of the examples shown in FIGS. 27 and 28 were improved by about 10%. Thus, it was found that whether or not the temperature drop of the support plate during substrate placement during OS annealing is kept within 10% significantly affects the magnitude of field-effect mobility. Furthermore, the results shown in FIGS. 27 and 28 revealed that when the heating atmosphere was a humid air atmosphere, the variation in field-effect mobility could be reduced compared to when the heating atmosphere was a dry air atmosphere.

[0118] 29 and 30 are diagrams showing electrical characteristics of semiconductor devices when OS annealing is performed under different conditions. In FIGS. 29 and 30, "Sample 1" shows a reference example in which the present invention is not applied during OS annealing (an example under the same conditions as the graph shown in FIG. 26). "Sample 2" shows an example in which OS annealing is performed in a dry air atmosphere and the temperature drop of the support plate during OS annealing is suppressed to within 10% (the same conditions as the graph shown in FIG. 27). "Sample 3" shows an example in which OS annealing is performed in a humid air atmosphere and the temperature drop of the support plate during OS annealing is suppressed to within 10% (the same conditions as the graph shown in FIG. 28). FIGS. 29 and 30 are so-called "box-and-whisker plots."

[0119] 29 is a graph showing the effect of a temperature decrease of the support plate during OS annealing on the threshold voltage (Vth) of a semiconductor device. As shown in FIG. 29, no significant change in threshold voltage was observed between Sample 1 and Sample 3, but a decrease in threshold voltage was observed in Sample 2. Specifically, the average threshold values ​​of Samples 1 to 3 were 0.42 V, 0.26 V, and 0.39 V, respectively.

[0120] 30 is a graph showing the effect of a temperature decrease of the support plate during OS annealing on the field-effect mobility of a semiconductor device. As described above, Sample 2 and Sample 3 showed improved field-effect mobility compared to Sample 1. Furthermore, the results of Sample 2 and Sample 3 confirmed that creating a humid air atmosphere in the heating furnace during OS annealing is effective in reducing variations in field-effect mobility.

[0121] As described above, it was confirmed that the field-effect mobility was improved when the temperature drop of the support plate was kept within 10% during OS annealing.

[0122] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0123] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0124] 10, 10a... semiconductor device, 11... driving transistor, 12... selection transistor, 20... display device, 22... liquid crystal region, 24... sealing region, 26... terminal region, 100... substrate, 105, 160... gate electrode, 110, 120, 150... gate insulating layer, 130, 190... metal oxide layer, 140... oxide semiconductor layer, 141... upper surface, 142... lower surface, 143... side surface, 170, 180... insulating layer, 171, 173... opening, 200... source / drain electrode, 201... source electrode, 203... drain electrode, 210... storage capacitor, 211... signal line, 212... gate line, 21 3...anode power line, 214...cathode power line, 300...array substrate, 301...pixel circuit, 302...source driver circuit, 303...gate driver circuit, 304...source wiring, 305...gate wiring, 306...terminal portion, 307, 308...connection wiring, 310...sealing portion, 311...liquid crystal element, 320...opposite substrate, 330...flexible printed circuit board (FPC), 340...IC chip, 350...storage capacitor, 360, 362...insulating layer, 363, 381...opening, 370...common electrode, 380...insulating layer, 390...pixel electrode, 392...light-emitting layer, 394...common electrode

Claims

1. An oxide semiconductor layer is formed on the substrate by sputtering. The substrate on which the oxide semiconductor layer is formed is placed in a heating furnace having a heating medium maintained at a predetermined temperature, and the oxide semiconductor layer is subjected to a first heat treatment. After the first heat treatment, a gate insulating layer is formed on the oxide semiconductor layer. This includes forming a gate electrode on the gate insulating layer, A method for manufacturing a semiconductor device, wherein when the substrate is placed in the heating furnace, the temperature drop of the heating medium is kept within 15% of the set temperature.

2. Before forming the oxide semiconductor layer, a first metal oxide layer mainly composed of aluminum is formed on the substrate. A method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed on the first metal oxide layer so as to be in contact with the first metal oxide layer.

3. After forming the gate insulating layer, a metal oxide layer mainly composed of aluminum is formed on the gate insulating layer. With the second metal oxide layer formed on the gate insulating layer, the second heat treatment is performed. After the second heat treatment, the second metal oxide layer is removed. A method for manufacturing a semiconductor device according to claim 2, wherein the gate electrode is formed on the gate insulating layer after the second metal oxide layer has been removed.

4. After forming the gate insulating layer, a metal oxide layer mainly composed of aluminum is formed on the gate insulating layer. With the metal oxide layer formed on the gate insulating layer, the second heat treatment is performed. After the second heat treatment, the metal oxide layer is removed. A method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode is formed on the gate insulating layer after the metal oxide layer has been removed.

5. A gate electrode is formed on the substrate. A gate insulating layer is formed on the gate electrode, An oxide semiconductor layer is formed on the gate insulating layer by sputtering, The process includes placing the substrate on which the oxide semiconductor layer is formed in a heating furnace having a heating medium maintained at a predetermined temperature, and performing a first heat treatment on the oxide semiconductor layer. A method for manufacturing a semiconductor device, wherein when the substrate is placed in the heating furnace, the temperature drop of the heating medium is kept within 15% of the set temperature.

6. Before forming the oxide semiconductor layer, a first metal oxide layer mainly composed of aluminum is formed on the gate insulating layer. A method for manufacturing a semiconductor device according to claim 5, wherein the oxide semiconductor layer is formed on the first metal oxide layer so as to be in contact with the first metal oxide layer.

7. After the oxide semiconductor layer is subjected to the first heat treatment, an insulating layer is formed on the oxide semiconductor layer. A metal oxide layer mainly composed of aluminum is formed on the insulating layer. With the second metal oxide layer formed on the insulating layer, the second heat treatment is performed. A method for manufacturing a semiconductor device according to claim 6, wherein the second metal oxide layer is removed after the second heat treatment.

8. After the oxide semiconductor layer is subjected to the first heat treatment, an insulating layer is formed on the oxide semiconductor layer. A metal oxide layer mainly composed of aluminum is formed on the insulating layer. With the metal oxide layer formed on the insulating layer, the second heat treatment is performed. The method for manufacturing a semiconductor device according to claim 5, wherein the metal oxide layer is removed after the second heat treatment.

9. The heating medium is a support plate, The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the substrate is placed on the support plate maintained at the set temperature.

10. The heating medium is air. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the substrate is supported by a support member and placed in air maintained at the set temperature.

11. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the atmosphere inside the heating furnace is a humid atmospheric atmosphere.

12. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the set temperature is 400°C or higher and 450°C or lower.

13. A method for manufacturing a semiconductor device according to claim 1 or 5, wherein when forming the oxide semiconductor layer by the sputtering method, the sputtering is performed while cooling the substrate.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the difference between the temperature at which the oxide semiconductor layer is formed and the temperature at which the first heat treatment is performed is 350°C or more.

15. A method for manufacturing a semiconductor device according to claim 14, wherein the temperature at which the oxide semiconductor layer is formed is 50°C or lower, and the temperature at which the first heat treatment is performed is 400°C or higher.

16. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the first heat treatment is performed after patterning the oxide semiconductor layer.

17. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the oxide semiconductor layer contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more.