Semiconductor device and storage device

Abstract

Provided is a semiconductor device having favorable electrical characteristics. This semiconductor device has: a first layered body; a semiconductor layer having a channel-forming region under the first layered body; and a second layered body under the semiconductor layer. The first layered body and the second layered body each have at least a first insulator and a second insulator. At such a time, the first insulator of the first layered body and the first insulator of the second layered body have regions that overlap each other with the channel-forming region therebetween, and the second insulator of the first layered body and the second insulator of the second layered body have regions that overlap each other with the first insulator of the first layered body, the channel-forming region, and the first insulator of the second layered body therebetween. Furthermore, the first insulator included in the first layered body and the first insulator included in the second layered body share a function, and the second insulator included in the first layered body and the second insulator included in the second layered body share a function.

Description

Semiconductor device, memory device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of the semiconductor device and the memory device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object is to provide a semiconductor device which can be miniaturized or highly integrated. Another object is to provide a semiconductor device with high operating speed. Another object is to provide a semiconductor device with high on-state current. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device. Another object is to provide a method for manufacturing a semiconductor device with high productivity. Another object is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a storage device with a large storage capacity, a storage device with high operation speed, a storage device with low power consumption, a novel storage device, or a manufacturing method of a novel storage device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including a first stack, a semiconductor layer below the first stack, and a second stack below the semiconductor layer. The semiconductor layer includes a first region and a second region and a third region sandwiching the first region. The first stack and the second stack are symmetrically arranged with respect to the first region. The first stack includes a first insulator and a second insulator on the first insulator. The second stack includes a third insulator and a fourth insulator below the third insulator. The second insulator is less permeable to hydrogen than the first insulator. The fourth insulator is less permeable to hydrogen than the third insulator. Each of the first insulator and the third insulator includes silicon and oxygen. Each of the second insulator and the fourth insulator includes silicon and nitrogen.

[0013] In the semiconductor device, it is preferable that the third insulator has an island shape, and that a side edge of the third insulator coincides with a side edge of the semiconductor layer in a cross-sectional view.

[0014] Furthermore, in the above-mentioned semiconductor device, it is preferable that the first stack further has a fifth insulator below the first insulator, the second stack further has a sixth insulator on the third insulator, the fifth insulator being less permeable to oxygen than the first insulator, the sixth insulator being less permeable to oxygen than the second insulator, and each of the fifth insulator and the sixth insulator contains aluminum.

[0015] In addition, in the above semiconductor device, it is preferable that the third insulator and the sixth insulator have a laminated structure, the laminated structure is island-shaped, and in a cross-sectional view, the side edges of the laminated structure coincide with the side edges of the semiconductor layer.

[0016] Another embodiment of the present invention is a semiconductor device including a first stack, a semiconductor layer below the first stack, and a second stack below the semiconductor layer. The semiconductor layer includes a first region and a second region and a third region sandwiching the first region. The first stack and the second stack are arranged symmetrically with respect to the first region. The first stack includes a first insulator, a second insulator on the first insulator, and a third insulator on the second insulator. The second stack includes a first metal oxide, a fourth insulator below the first metal oxide, and a fifth insulator below the fourth insulator. The first insulator is less permeable to oxygen than the second insulator. The third insulator is less permeable to hydrogen than the second insulator. The first metal oxide is less permeable to oxygen than the fourth insulator. The fifth insulator is less permeable to hydrogen than the fourth insulator. Each of the first insulator and the first metal oxide contains at least one of gallium and aluminum. Each of the second insulator and the fourth insulator contains silicon and oxygen. Each of the third insulator and the fifth insulator contains silicon and nitrogen.

[0017] In the above semiconductor device, it is preferable that the semiconductor layer contains a second metal oxide, each of the first metal oxide and the second metal oxide contains indium, and the atomic ratio of at least one of gallium and aluminum to indium in the first metal oxide is larger than the atomic ratio of at least one of gallium and aluminum to indium in the second metal oxide.

[0018] Preferably, the semiconductor device further includes a sixth insulator between the fourth insulator and the fifth insulator, and the sixth insulator has a function of capturing or fixing hydrogen.

[0019] Preferably, the semiconductor device further includes a seventh insulator between the second insulator and the third insulator, and the seventh insulator has a function of capturing or fixing hydrogen.

[0020] Furthermore, it is preferable that the above-mentioned semiconductor device further includes a first conductor and a second conductor, the first conductor being located above the first stack and the second conductor being located below the second stack.

[0021] Furthermore, it is preferable that the above semiconductor device further includes a third conductor and a fourth conductor, the second region overlapping with the third conductor, and the third region overlapping with the fourth conductor.

[0022] Another embodiment of the present invention is a memory device including the semiconductor device and a capacitor, wherein the capacitor is a ferroelectric capacitor.

[0023] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with little variation in the electrical characteristics of transistors can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with high operating speed can be provided. Alternatively, a semiconductor device with high on-state current can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a method for manufacturing a semiconductor device with high productivity can be provided. Alternatively, a method for manufacturing a novel semiconductor device can be provided.

[0024] According to one embodiment of the present invention, a storage device with a large storage capacity, a storage device with high operating speed, a storage device with low power consumption, a novel storage device, or a method for manufacturing a novel semiconductor device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of a semiconductor device. FIG. 3A is a top view showing an example of a semiconductor device. FIGS. 3B and 3C are cross-sectional views showing an example of a semiconductor device. FIGS. 4A to 4D are cross-sectional views showing an example of a semiconductor device. FIGS. 5A to 5D are cross-sectional views showing an example of a semiconductor device. FIG. 6A is a top view showing an example of a semiconductor device. FIGS. 6B and 6C are cross-sectional views showing an example of a semiconductor device. FIGS. 7A to 7D are cross-sectional views showing an example of a semiconductor device. FIG. 8A is a top view showing an example of a semiconductor device. FIGS. 8B and 8C are cross-sectional views showing an example of a semiconductor device. FIGS. 9A to 9F are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10F are cross-sectional views showing an example of a semiconductor device. FIGS. 11A to 11D are cross-sectional views showing an example of a semiconductor device. FIGS. 12A to 12D are cross-sectional views showing an example of a semiconductor device. FIGS. 13A to 13F are cross-sectional views showing an example of a semiconductor device. FIGS. 14A to 14F are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a top view illustrating an example of a semiconductor device. FIGS. 15B to 15D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views illustrating an example of a semiconductor device. FIG. 19A is a top view illustrating an example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views illustrating an example of a semiconductor device. FIG. 20A is a top view illustrating an example of a semiconductor device. FIG. 20B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 21 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 22 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 23A is a top view illustrating an example of a semiconductor device. FIG. 23B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 24A is a top view illustrating an example of a semiconductor device. FIG. 24B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 25A is a top view illustrating an example of a semiconductor device. FIG. 25B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 26 is a cross-sectional view illustrating an example of a memory device. FIG. 27 is a cross-sectional view illustrating an example of a memory device. FIG. 28A is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.FIG. 28B is a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. FIGS. 29A to 29I are circuit diagrams illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 30 is a cross-sectional view illustrating an example of a memory device. FIG. 31A is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 31B is a graph illustrating an example of hysteresis characteristics. FIG. 31C is a timing chart illustrating an example of a method for driving a memory cell. FIGS. 32A and 32B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. FIGS. 33A to 33E are diagrams illustrating an example of a memory device. FIGS. 34A and 34B are diagrams illustrating an example of an electronic component. FIGS. 35A and 35B are diagrams illustrating an example of an electronic device, and FIGS. 35C to 35E are diagrams illustrating an example of a mainframe computer. FIG. 36 is a diagram illustrating an example of space equipment. FIG. 37 is a diagram illustrating an example of a storage system applicable to a data center. FIG. 38 is a diagram illustrating a GIXRD measurement result. FIGS. 39A and 39B are diagrams illustrating the results of surface observation using an AFM. 39C and 39D are diagrams showing the results of image analysis. 39E and 39F are diagrams showing the results of evaluating particle size distribution. 40A is a diagram showing an input voltage waveform. 40B is a diagram showing P-E characteristics. 41A is a diagram showing an input voltage waveform. 41B is a diagram showing fatigue characteristics. 42A and 42B are diagrams showing fatigue characteristics. 43A and 43B are diagrams showing a method of retention measurement. 44 is a diagram showing the results of retention measurement. 45 is a diagram showing J-V characteristics. 46 is a cross-sectional STEM image of a fabricated sample. 47A is a diagram explaining a memory cell circuit. 47B is an optical microscope photograph. 48 is a diagram showing source follower characteristics. 49A and 49B are diagrams explaining a method for evaluating positive polarization write and read. 50A and 50B are diagrams explaining a method for evaluating positive polarization write and read. 51 is a diagram showing voltage waveforms. Figure 52 shows ΔV. ＢＬ FIG. 53 shows the transition of ΔV ＢＬ54A and 54B are graphs showing the transition of fatigue characteristics. FIGS. 55A and 55B are graphs showing the results of retention measurements. FIG. 56A is a schematic diagram of a sample, and FIG. 56B is a cross-sectional view of the sample. FIG. 57 is a cross-sectional STEM image of the fabricated sample. FIG. 58 is a graph showing the Id-Vg characteristics of the sample. FIG. 59 is a graph showing threshold voltage. FIG. 60 is a graph showing the Id-Vg characteristics of the sample. FIG. 61A is a graph showing threshold voltage of the sample. FIG. 61B is a graph showing sheet resistance of the sample. FIG. 61C is a graph showing contact resistance of the sample. FIG. 62 is a graph showing Id-Vg characteristics of the sample. FIGS. 63A to 63C are graphs showing contact resistance of the sample. FIG. 64A is a circuit diagram showing the circuit configuration of the sample. FIG. 64B is a graph showing the measurement results of leakage current. FIG. 65A is a circuit diagram showing the circuit configuration of the sample. FIG. 65B is a graph showing the Id-Vg characteristics of the sample. ＣＷＬ FIG. 65C is a diagram showing the potential Vsh of the sample. FIG. 66A is a diagram showing the results of a data retention evaluation test of the sample. FIG. 66B is a diagram showing the results of a data rewrite evaluation test of the sample. FIG. 67A is a diagram showing contact resistance. FIG. 67B is a diagram showing sheet resistance. FIG. 68 is a cross-sectional STEM image according to the example. FIGS. 69A and 69B are diagrams showing the results of a drain breakdown voltage test. FIG. 70 is a diagram showing the results of a drain breakdown voltage test. FIG. 71 is a diagram showing P-V characteristics. FIG. 72 is a diagram showing fatigue characteristics. FIG. 73 is a diagram showing ΔV ＢＬ 74 is a diagram showing the results of retention measurement.

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0030] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0031] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0032] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0033] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is approximately perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0034] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0035] In this specification, "equal heights" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP (Chemical Mechanical Polishing) process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also considered to be "equal heights." For example, when there are two layers (here, a first layer and a second layer) with different heights relative to the reference surface, and the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "equal heights."

[0036] In this specification, "edges coincide" means that at least a portion of the contours of stacked layers overlap when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges coincide" is also used.

[0037] Generally, it is difficult to clearly distinguish between an "exact match" and an "approximate match." For this reason, in this specification, "match" includes both an exact match and an approximate match.

[0038] In this specification, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification, the term "off-state current" may refer to, for example, a current that flows between the source and drain of a transistor when the transistor is in an off state.

[0039] 1A to 25B, a structural example of a semiconductor device according to one embodiment of the present invention will be described. Note that the semiconductor device according to one embodiment of the present invention includes a transistor.

[0040] 1A to 1C will be used to describe a structural example of a semiconductor device according to one embodiment of the present invention. FIG. 1A is a top view of the semiconductor device, and FIGS. 1B and 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0041] 1A to 1C include a transistor 200A. Therefore, FIG. 1B can also be considered a cross-sectional view of the transistor 200A in the channel length direction, and FIG. 1C can also be considered a cross-sectional view of the transistor 200A in the channel width direction.

[0042] Transistor 200A has a conductor 205, an insulator 222 (insulator 222b and insulator 222a) on the conductor 205, an oxide 230 on the insulator 222, a conductor 242a and a conductor 242b on the oxide 230, an insulator 250 (insulator 250a and insulator 250b) on the oxide 230, and a conductor 260 on the insulator 250.

[0043] An insulator 280 is provided on the insulator 222, the conductor 242a, and the conductor 242b. The top surface of the insulator 280 may be flattened. The insulator 250 and the conductor 260 are provided so as to fill openings formed in the insulator 280.

[0044] The oxide 230 has a region that functions as a channel formation region. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode). The insulator 250 has a region that functions as a first gate insulator. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode). The insulator 222 has a region that functions as a second gate insulator. The conductor 242a has a region that functions as one of a source electrode and a drain electrode. The conductor 242b has a region that functions as the other of the source electrode and the drain electrode.

[0045] Since the oxide 230 has a region that functions as a channel formation region, in this specification and the like, the oxide 230 can be referred to as a semiconductor layer of the transistor 200A. Also, the semiconductor layer can be referred to as the oxide 230.

[0046] 1B, the oxide 230 includes a region 230i and regions 230na and 230nb sandwiching the region 230i. Here, the region 230i functions as a channel formation region. The region 230na functions as one of a source region and a drain region, and the region 230nb functions as the other of the source region and the drain region. At least a portion of the region 230i overlaps with the conductor 260 and the conductor 205. The region 230na overlaps with the conductor 242a, and the region 230nb overlaps with the conductor 242b.

[0047] The region 230i has fewer oxygen vacancies or a lower impurity concentration than the regions 230na and 230nb, and is therefore a high-resistivity region with a low carrier concentration. Therefore, the region 230i can be said to be i-type (intrinsic) or substantially i-type.

[0048] The regions 230na and 230nb have more oxygen vacancies or higher impurity concentrations such as hydrogen, nitrogen, and metal elements than the region 230i, and are therefore low-resistivity regions with high carrier concentrations. That is, the regions 230na and 230nb are n-type regions (low-resistivity regions) with higher carrier concentrations than the region 230i.

[0049] The carrier concentration of the region 230i is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration of the region 230i is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0050] To reduce the carrier concentration of the oxide 230, the impurity concentration in the oxide 230 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0051] In order to stabilize the electrical characteristics of the transistor 200A, it is effective to reduce the impurity concentration in the oxide 230. Furthermore, in order to reduce the impurity concentration in the oxide 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide 230 refer to, for example, elements other than the main components constituting the oxide 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0052] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, the concentrations of impurity elements such as hydrogen and nitrogen may decrease in regions closer to the region 230i.

[0053] The oxide 230 may have a single layer structure or a multilayer structure.

[0054] The oxide 230 is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0055] The band gap of a metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region like this is called an OS transistor. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0056] The oxide 230 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0057] The oxide 230 may be, for example, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum Examples of usable materials include zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable materials include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0058] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0059] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0060] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0061] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0062] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0063] Furthermore, by increasing the ratio of the number of In atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0064] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0065] Specifically, the oxide 230 may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a composition close thereto, an atomic ratio of In:M:Zn = 1:1:1.2 or a composition close thereto, an atomic ratio of In:M:Zn = 1:1:2 or a composition close thereto, or an atomic ratio of In:M:Zn = 4:2:3 or a composition close thereto. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use at least one of gallium and aluminum as the element M.

[0066] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0067] In a transistor using an oxide semiconductor, impurities and oxygen vacancies are present in a channel formation region of the oxide semiconductor, which may cause fluctuations in electrical characteristics and reduce reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0068] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the region 230na or the region 230nb, the on-state current or the field-effect mobility of the transistor 200A may decrease. Furthermore, if the amount of oxygen supplied to the region 230na or the region 230nb varies across the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0069] Therefore, in the oxide semiconductor, the region 230i preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230na and 230nb preferably have a high carrier concentration and are n-type. Ｏ It is preferable to reduce H. In addition, it is preferable to prevent an excessive amount of oxygen from being supplied to the regions 230na and 230nb, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0070] Therefore, in this embodiment, the semiconductor device is configured to supply oxygen to the region 230i and suppress diffusion of hydrogen into the region 230i. The semiconductor device is also configured to suppress oxidation of the conductors 242a, 242b, and 260. The semiconductor device is also configured to reduce the hydrogen concentration in the region 230i.

[0071] As shown in FIG. 1C , in a cross-sectional view of the transistor 200A in the channel width direction, the conductor 260 covers the side and top surfaces of the oxide 230. With this structure, the channel formation region can be electrically surrounded by the electric field of the gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. By using the S-channel structure for the transistor 200A, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0072] As described above, the transistor 200A has a structure in which the channel formation region is surrounded by the electric field of the gate electrode. Therefore, it is preferable to uniformly supply oxygen to the entire channel formation region (top, side, and bottom surfaces of the channel formation region) and suppress hydrogen diffusion. For example, it is preferable to provide a first insulator containing a material that easily transmits oxygen so as to surround the channel formation region, and further provide a second insulator that has the function of suppressing hydrogen diffusion so as to surround the channel formation region and the first insulator. Specifically, it is preferable to provide first insulators above and below the region 230i, and then provide second insulators above and below them. Here, a stack of the first insulator over the channel formation region and the second insulator over the first insulator is referred to as a first stack. Furthermore, a stack of the first insulator under the region 230i and the second insulator under the first insulator is referred to as a second stack. In this case, the first stacked body and the second stacked body are provided symmetrically with respect to the channel formation region as a reference or axis. In other words, the first stacked body and the second stacked body are provided symmetrically with respect to a plane or line passing through the channel formation region. Furthermore, the first stacked body and the second stacked body are provided symmetrically with respect to the channel formation region as a center.

[0073] In this specification, a configuration in which the first stack and the second stack are arranged symmetrically with respect to the structure refers to a configuration in which the first stack and the second stack are arranged so as to sandwich the structure, and the stacking order of the layers included in the first stack and the stacking order of the layers included in the second stack are the same when the structure is used as a reference. In other words, a configuration in which the first stack and the second stack are arranged so as to sandwich the structure, and the stacking order of the layers included in the first stack is reversed to the stacking order of the layers included in the second stack in the direction from the first stack to the second stack via the structure. The first stack, the structure, and the second stack may be arranged in this order vertically or horizontally with respect to the substrate surface. When the first stack, the structure, and the second stack are arranged in this order vertically with respect to the substrate surface, the first stack and the second stack can be said to be arranged above and below the structure.

[0074] It should be noted that the first stack and the second stack each have two or more layers. It is also preferable that the number of layers included in the first stack is the same as the number of layers included in the second stack. A single layer included in the first stack may also have the functions of multiple layers included in the second stack, and vice versa. A structure comprised of multiple layers included in the first stack may also have the function of a single layer included in the second stack, and vice versa. Therefore, the number of layers included in the first stack and the number of layers included in the second stack may differ in some cases. The contours of one layer and another layer included in the first stack do not necessarily need to overlap. The same is true for the second stack.

[0075] The semiconductor device described in this embodiment includes a first stack, a metal oxide having a channel formation region below the first stack, and a second stack below the metal oxide. Each of the first stack and the second stack includes at least a first insulator and a second insulator. In this case, the first insulator of the first stack and the first insulator of the second stack overlap each other through a channel formation region, and the second insulator of the first stack and the second insulator of the second stack overlap each other through the first insulator, the channel formation region, and the first insulator of the second stack.

[0076] Note that the first insulator included in the first stack and the first insulator included in the second stack may have different film thicknesses, materials, formation methods, etc., as long as they have common properties or functions. Specifically, the first insulator included in the first stack and the first insulator included in the second stack only need to have the property of easily transmitting oxygen, and the film thicknesses, materials, formation methods, etc. may be different. Note that the common property or function may be one or more. The same applies to the second insulator included in the first stack and the second insulator included in the second stack. Specifically, the second insulator included in the first stack and the second insulator included in the second stack only need to have the function of suppressing hydrogen diffusion, and the film thicknesses, materials, formation methods, etc. may be different.

[0077] 1B and 1C, the insulator 250 preferably has a layered structure of an insulator 250a and an insulator 250b on the insulator 250a. The insulator 222 preferably has a layered structure of an insulator 222a and an insulator 222b below the insulator 222a. That is, the insulators 250a and 222a are preferably provided to sandwich the region 230i of the oxide 230, and the insulators 250b and 222b are preferably provided to sandwich the insulator 250a, the region 230i, and the insulator 222a. In other words, the insulators 250a and 222a have a region where they overlap with each other via the region 230i, and the insulators 250b and 222b have a region where they overlap with each other via the insulator 250a, the region 230i, and the insulator 222a.

[0078] 1B and 1C, the insulator 250 corresponds to the first stacked body described above, and the insulator 222 corresponds to the second stacked body described above. Furthermore, the insulators 250a and 222a correspond to the first insulator described above, and the insulators 250b and 222b correspond to the second insulator described above. In this case, the conductor 260 can be said to be located above the first stacked body. Furthermore, the conductor 205 can be said to be located below the second stacked body.

[0079] 1B and 1C, it is preferable that the insulator 250a and the insulator 222a have a region where they are in contact with each other in a region that does not overlap with the oxide 230. With this configuration, the oxide 230 can be surrounded by the insulator 250a and the insulator 222a.

[0080] The insulators 250a and 222a are preferably made of insulators that are easily permeable to oxygen. With this configuration, oxygen contained in the insulator 280 can be supplied to the region 230i via the insulators 250a and 222a. Alternatively, the insulators 250a and 222a may be made of insulators containing excess oxygen. With this configuration, oxygen contained in the insulators 250a and 222a can be supplied to the region 230i.

[0081] The insulator 250a and the insulator 222a can be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. Alternatively, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, or silicon oxide doped with carbon and nitrogen can be used. Alternatively, for example, silicon oxide having vacancies can be used. These silicon oxides may contain nitrogen. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250a and the insulator 222a contain at least oxygen and silicon.

[0082] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0083] It is also preferable that the concentrations of impurities such as water and hydrogen in the insulators 250a and 222a be reduced.

[0084] The insulators 250b and 222b preferably have barrier properties against hydrogen. This can suppress the diffusion of impurities such as hydrogen contained in the conductors 260 and 205 into the region 230i. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide is preferably used as the insulators 250b and 222b. Silicon nitride is particularly suitable for use as the insulators 250b and 222b because it has high hydrogen barrier properties. In this case, the insulators 250b and 222b contain at least nitrogen and silicon.

[0085] The insulator 250b may be made of a material that is less permeable to hydrogen than the insulator 250a, for example. The insulator 250b may be made of a material that is less permeable to hydrogen than the insulator 250a, for example. Similarly, the insulator 222b may be made of a material that is less permeable to hydrogen than the insulator 222a, for example. The insulator 222b may be made of a material that is less permeable to hydrogen than the insulator 222a, for example.

[0086] In this specification and the like, the term "barrier property" refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). Alternatively, the term refers to a function of capturing or fixing (also referred to as gettering) a corresponding substance. In addition, in this specification and the like, an insulator having barrier property may be referred to as a barrier insulator.

[0087] It is preferable that the insulator 250b and the insulator 222b further have a barrier property against oxygen. The insulator 250b is provided between the insulator 250a and the conductor 260. Therefore, the oxygen contained in the insulator 250a can be prevented from diffusing to the conductor 260, and the conductor 260 can be prevented from being oxidized. Furthermore, a decrease in the amount of oxygen supplied to the region 230i can be suppressed. Furthermore, the insulator 222b is provided between the insulator 222a and the conductor 205. Therefore, the oxygen contained in the insulator 222a can be prevented from diffusing to the conductor 205, and the conductor 205 can be prevented from being oxidized. Furthermore, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.

[0088] The insulator 250b may be made of, for example, a material that is less permeable to oxygen than the insulator 250a. The insulator 250b may be made of, for example, a material that is less permeable to oxygen than the insulator 250a. Similarly, the insulator 222b may be made of, for example, a material that is less permeable to oxygen than the insulator 222a. The insulator 222b may be made of, for example, a material that is less permeable to oxygen than the insulator 222a.

[0089] Silicon nitride has barrier properties against oxygen and can therefore be suitably used for the insulators 250b and 222b.

[0090] The above-described structure can improve the electrical characteristics and reliability of the transistor 200. Therefore, a semiconductor device with good electrical characteristics and high reliability can be realized. The insulators 250a and 222a have the same function, and the insulators 250b and 222b have the same function. Therefore, the first stacked body and the second stacked body can be provided symmetrically with respect to the channel formation region.

[0091] The insulator 280 functions as an interlayer film. It is preferable that the insulator 280 be made of a material with a low dielectric constant. It is preferable that the insulator 280 have a lower dielectric constant than the insulator 250b, for example. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0092] The ratio of the dielectric constant of a medium to the dielectric constant of a vacuum is called the relative permittivity. In other words, the relative permittivity is the dielectric constant made dimensionless by the electric constant. Therefore, the dielectric constant can be rephrased as the relative permittivity.

[0093] For example, an insulator that can be used for the insulator 250a and the insulator 222a can be used for the insulator 280. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing excess oxygen.

[0094] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon such as silicon oxide or silicon oxynitride.

[0095] The conductor 260 and the insulator 250 are arranged so as to fill the opening formed in the insulator 280. The conductor 260 is provided in the opening so as to cover at least a part of the side surface and at least a part of the top surface of the oxide 230 via the insulator 250. The conductor 260 is also arranged so that its top surface is flush with the top surfaces of the insulator 250 and the insulator 280.

[0096] In the opening formed in the insulator 280, in which the conductor 260 and the insulator 250 are disposed, the sidewall of the insulator 280 may be approximately perpendicular to the upper surface of the insulator 222, or may have a tapered shape. By tapering the sidewall of the insulator 280 in the opening, the coverage of the insulator 250 and the like provided in the opening can be improved, and defects such as voids can be reduced.

[0097] 1A and 1C, the conductor 260 preferably extends in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0098] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the conductor 260, the conductor 242a, the conductor 242b, and the conductor 205. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the conductor 205. When a conductive material containing a metal and nitrogen is used for the conductor 260, the conductor 242a, the conductor 242b, and the conductor 205, the conductor 260, the conductor 242a, the conductor 242b, and the conductor 205 contain at least the metal and nitrogen.

[0099] The conductor 260 may have a single-layer structure or a multi-layer structure. The conductor 242a and the conductor 242b may have a single-layer structure or a multi-layer structure.

[0100] For the conductor 242a and the conductor 242b, it is preferable to use a conductive material containing nitrogen, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or that maintain their conductivity even when they absorb oxygen.

[0101] Note that hydrogen contained in the oxide 230 and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230 and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230 and the like may be absorbed by the conductor 242a or the conductor 242b.

[0102] The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided so as to extend in the channel width direction, as shown in Figures 1A and 1C. With this structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0103] The conductor 205 may have a single layer structure or a multilayer structure.

[0104] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0105] Note that the potential applied to the conductor 205 may be the same as the potential applied to the conductor 260. In this case, the electric field of the conductor 260 and the conductor 205 can be applied to the entire channel formation region of the oxide 230. Therefore, the channel width can be increased without increasing the size of the transistor. Therefore, the on-state current of the transistor can be increased while miniaturizing the transistor. Furthermore, the increased on-state current of the transistor can improve the frequency characteristics.

[0106] 1B and 1C show a configuration in which the second gate insulator has a stacked structure of the insulator 222b and the insulator 222a, but the present invention is not limited to this. For example, the second gate insulator may have a stacked structure of the insulator 222 and an island-shaped insulator on the insulator 222. In other words, an island-shaped insulator may be provided between the insulator 222 and the oxide 230.

[0107] In this specification and the like, the term "island-like" refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

[0108] 2A and 2B show examples of a structure different from those shown in FIGS. 1B and 1C. FIGS. 2A and 2B are cross-sectional views of a semiconductor device including a transistor 200A. Here, FIG. 2A is a cross-sectional view of the transistor 200A in the channel length direction, and FIG. 2B is a cross-sectional view of the transistor 200A in the channel width direction. For top views of the semiconductor device shown in FIGS. 2A and 2B, refer to FIG. 1A.

[0109] The transistor 200A shown in FIGS. 2A and 2B differs from the transistor 200A shown in FIGS. 1B and 1C mainly in that the insulator 222 is a single layer and that an island-shaped insulator 224 is provided.

[0110] 2A and 2B, an island-shaped insulator 224 is provided between the insulator 222 and the oxide 230. As shown in FIGS. 2A and 2B, in a cross-sectional view of the transistor 200A, the side edges of the insulator 224 coincide with the side edges of the oxide 230.

[0111] Each of the insulators 222 and 224 has a region that functions as a second gate insulator.

[0112] The insulator 250a has a region in contact with the top surface of the insulator 222, a region in contact with the side surface of the insulator 224, a region in contact with the side surface of the oxide 230, and a region in contact with the top surface of the oxide 230. In this case, the region 230i of the oxide 230 is surrounded by the insulator 250a and the insulator 224.

[0113] The insulator 222 is preferably made of a material that can be used for the insulator 222b. The insulator 224 is preferably made of a material that can be used for the insulator 222a. In this structure, the stack of the insulator 222 and the island-shaped insulator 224 can be considered as a second stack. In this case, the transistor 200A shown in FIGS. 2A and 2B can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0114] <Configuration Example 2> A configuration example different from the above-described transistor 200A is shown in FIGS. 3A to 3C. FIG. 3A is a top view of a semiconductor device, and FIGS. 3B and 3C are cross-sectional views of the semiconductor device. FIG. 3B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 3A. FIG. 3C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 3A. Note that some elements are omitted from the top view of FIG. 3A for clarity.

[0115] 3A to 3C include a transistor 200B. Therefore, Fig. 3B can also be considered a cross-sectional view of the transistor 200B in the channel length direction, and Fig. 3C can also be considered a cross-sectional view of the transistor 200B in the channel width direction.

[0116] 3B and 3C differs from the transistor 200A shown in FIGS. 1B and 1C mainly in that the insulator 222 and the insulator 250 each have a three-layer stacked structure. Specifically, the transistor 200B shown in FIGS. 3B and 3C differs from the transistor 200A shown in FIGS. 1B and 1C mainly in that the insulator 250 further includes an insulator 250c below the insulator 250a and that the insulator 222 further includes an insulator 222c above the insulator 222a. Hereinafter, differences from the above-described Configuration Example 1 will be mainly described, and descriptions of overlapping parts will be omitted.

[0117] The insulator 250 includes an insulator 250c, an insulator 250a on the insulator 250c, and an insulator 250b on the insulator 250a. The insulator 222 includes an insulator 222b, an insulator 222a on the insulator 222b, and an insulator 222c on the insulator 222a. In this case, the insulators 250c and 222c have an overlapping region via the region 230i, the insulators 250a and 222a have an overlapping region via the insulator 250c, the region 230i, and the insulator 222c, and the insulators 250b and 222b have an overlapping region via the insulator 250a, the insulator 250c, the region 230i, the insulator 222c, and the insulator 222a. Furthermore, it can be said that the insulator 250c is located between the insulator 250a and the region 230i, and the insulator 222c is located between the insulator 222a and the region 230i.

[0118] The insulator 250c and the insulator 222c preferably have oxygen barrier properties. The insulator 250c has a region in contact with the side surface of the conductor 242a and a region in contact with the side surface of the conductor 242b. The oxygen barrier properties of the insulator 250c can prevent the side surfaces of the conductors 242a and 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200B. Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0119] The insulator 250c and the insulator 222c preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen barrier insulators. Note that the insulator 250c only needs to be less permeable to oxygen than the insulator 250a, for example. The insulator 250c may be made of a material that is less permeable to oxygen than the insulator 250a, for example. Similarly, the insulator 222c only needs to be less permeable to oxygen than the insulator 222a, for example. The insulator 222c may be made of a material that is less permeable to oxygen than the insulator 222a, for example.

[0120] The insulator 250c is provided in contact with the top surface and side surfaces of the oxide 230 and the top surface of the insulator 222c. That is, the region 230i is surrounded by the insulator 250c and the insulator 222c. The insulators 250c and the insulator 222c have barrier properties against oxygen, which can prevent oxygen from being released from the region 230i when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in the region 230i can be prevented.

[0121] Furthermore, by providing the insulators 250c and 222c, even if an excessive amount of oxygen is contained in the insulator 280, the excessive supply of the oxygen to the region 230i can be suppressed, and an appropriate amount of oxygen can be supplied to the region 230i. Therefore, it is possible to suppress the regions 230na and 230nb from being excessively oxidized, which can reduce the on-state current of the transistor 200B or decrease the field-effect mobility.

[0122] Furthermore, the insulator 222c is provided between the insulator 222a and the region 230na or the region 230nb. This can suppress the diffusion of oxygen from below the insulator 222c to the region 230na and the region 230nb. Furthermore, the conductor 242a is provided on the region 230na, and the conductor 242b is provided on the region 230nb. Therefore, in this embodiment, an excessive amount of oxygen is not supplied to the region 230na and the region 230nb.

[0123] The insulators 250c and 222c are preferably insulators containing an oxide containing one or both of aluminum and hafnium. In this embodiment, aluminum oxide is used for the insulators 250c and 222c. In this case, the insulators 250c and 222c each contain at least oxygen and aluminum.

[0124] With the above structure, the insulator 250c and the insulator 222c have the same function. Therefore, the first stacked body and the second stacked body can be provided symmetrically with respect to the channel formation region.

[0125] Note that, similar to the configuration shown in FIGS. 2A and 2B, the second gate insulator may be formed of a stack of an insulator 222 and an island-shaped insulator 224.

[0126] 4A and 4B show examples of a structure different from those shown in FIGS. 3B and 3C. FIGS. 4A and 4B are cross-sectional views of a semiconductor device including a transistor 200B. Here, FIG. 4A is a cross-sectional view of the transistor 200B in the channel length direction, and FIG. 4B is a cross-sectional view of the transistor 200B in the channel width direction. For top views of the semiconductor device shown in FIGS. 4A and 4B, refer to FIG. 3A.

[0127] The transistor 200B shown in FIGS. 4A and 4B differs from the transistor 200B shown in FIGS. 3B and 3C mainly in that the insulator 222 has a two-layer structure and that an island-shaped insulator 224 is included.

[0128] 4A and 4B , the insulator 222 has a stacked-layer structure of an insulator 222b and an insulator 222a over the insulator 222b. An island-shaped insulator 224 is provided between the insulator 222 and the oxide 230.

[0129] The insulator 250c has a region in contact with the top surface of the insulator 222a, a region in contact with the side surface of the insulator 224, a region in contact with the side surface of the oxide 230, and a region in contact with the top surface of the oxide 230. In this case, the region 230i of the oxide 230 is surrounded by the insulator 250c and the insulator 224.

[0130] The insulator 224 is preferably made of a material that can be used for the insulator 222c described above.

[0131] Note that the structures of the insulator 222 and the insulator 224 are not limited to those shown in FIGS. 4A and 4B. Examples of structures different from those shown in FIGS. 4A and 4B are shown in FIGS. 4C and 4D. FIGS. 4C and 4D are cross-sectional views of a semiconductor device including a transistor 200B. Here, FIG. 4C is a cross-sectional view of the transistor 200B in the channel length direction, and FIG. 4D is a cross-sectional view of the transistor 200B in the channel width direction. Note that FIG. 3A can be referred to for top views of the semiconductor device shown in FIGS. 4C and 4D.

[0132] 4C and 4D, the insulator 222 may have a single-layer structure, and the insulator 224 may have a laminated structure of an insulator 224a and an insulator 224c on the insulator 224a. In this case, it is preferable that the insulator 222 is made of a material that can be used for the insulator 222b described above. It is also preferable that the insulator 224a is made of a material that can be used for the insulator 222a described above, and the insulator 224c is made of a material that can be used for the insulator 222c described above.

[0133] With the above-described structure, the stack including the insulator 222 and the insulator 224 can be regarded as a second stack. In this case, the transistor 200B shown in Figures 4A and 4B and the transistor 200B shown in Figures 4C and 4D can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0134] 4A and 4B show a configuration in which the insulator 224 having an oxygen barrier property is provided between the region 230i and the insulator 222a, but the present invention is not limited to this. An example of a configuration different from the configuration shown in FIGS. 4A and 4B is shown in FIGS. 5A and 5B.

[0135] 5A and 5B are cross-sectional views of a semiconductor device including a transistor 200B. Here, Fig. 5A is a cross-sectional view of the transistor 200B in the channel length direction, and Fig. 5B is a cross-sectional view of the transistor 200B in the channel width direction. Note that Fig. 3A can be referred to for top views of the semiconductor device shown in Figs. 5A and 5B.

[0136] The transistor 200B shown in FIGS. 5A and 5B differs from the transistor 200B shown in FIGS. 4A and 4B mainly in that the insulator 222 has a two-layer stacked structure, the insulator 224 is not included, and the oxide 230 has a two-layer stacked structure.

[0137] 5A and 5B, the insulator 222 has a stacked structure of an insulator 222b and an insulator 222a over the insulator 222b. The oxide 230 has a stacked structure of an oxide 230a and an oxide 230b over the oxide 230a. It is preferable that the oxide 230a be made of a semiconductor material having a barrier property against oxygen, and the oxide 230b be made of a material that can be used for the oxide 230 described above.

[0138] Note that the oxide 230a may be made of a material that is less permeable to oxygen than the insulator 222a, for example.

[0139] For example, it is preferable to use a metal oxide containing at least the element M as the oxide 230a. Note that the oxide 230b may or may not contain the element M. In this case, it is preferable that the atomic ratio of the element M to the metal element that is the main component in the oxide 230a is larger than the atomic ratio of the element M to the metal element that is the main component in the oxide 230b. Furthermore, when the oxide 230a and the oxide 230b each contain In, it is preferable that the atomic ratio of the element M to In in the oxide 230a is larger than the atomic ratio of the element M to In in the oxide 230b. With this configuration, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b.

[0140] As the oxide 230a, for example, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto can be used.

[0141] It is also preferable to use at least one of gallium and aluminum as the element M. As described above, when aluminum oxide is used as the insulator 250c, each of the oxide 230a and the insulator 250c contains at least one of gallium and aluminum.

[0142] In the above-described structure, the stack of the insulator 222 and the oxide 230a can be regarded as the second stack. In this case, the transistor 200B shown in Figures 5A and 5B can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0143] In addition, when oxide 230 has a stacked structure of oxide 230a and oxide 230b, regions 230i, 230na, and 230nb may be formed not only in oxide 230b but also in oxide 230a.

[0144] 5C and 5D show examples of a structure different from those shown in FIGS. 5A and 5B. FIGS. 5C and 5D are cross-sectional views of a semiconductor device including a transistor 200B. Here, FIG. 5C is a cross-sectional view of the transistor 200B in the channel length direction, and FIG. 5D is a cross-sectional view of the transistor 200B in the channel width direction. For top views of the semiconductor device shown in FIGS. 5C and 5D, refer to FIG. 3A.

[0145] 5C and 5D , the insulator 222 may have a single-layer structure, and the insulator 224 may be provided between the insulator 222 and the oxide 230a. In this case, the insulator 250c and the oxide 230a have an overlapping region via the region 230i, the insulator 250a and the insulator 224 have an overlapping region via the insulator 250c, the region 230i, and the oxide 230a, and the insulator 250b and the insulator 222 have an overlapping region via the insulator 250a, the insulator 250c, the region 230i, the oxide 230a, and the insulator 224.

[0146] The insulator 222 is preferably made of a material that can be used for the insulator 222b described above. The insulator 224 is preferably made of a material that can be used for the insulator 222a described above. In this configuration, a structure consisting of the insulator 222, the insulator 224, and the oxide 230a can be considered a second stack. The second stack includes the oxide 230a, the insulator 224 below the oxide 230a, and the insulator 222 below the insulator 224. The transistor 200B shown in FIGS. 5C and 5D can be said to have a configuration in which the first stack and the second stack are arranged symmetrically with respect to the channel formation region.

[0147] <Configuration Example 3> Configuration examples different from the above-described transistor 200A are shown in FIGS. 6A to 6C. FIG. 6A is a top view of a semiconductor device, and FIGS. 6B and 6C are cross-sectional views of the semiconductor device. FIG. 6B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 6A. FIG. 6C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 6A. Note that some elements are omitted from the top view of FIG. 6A for clarity.

[0148] 6A to 6C include a transistor 200C. Therefore, Fig. 6B can also be considered a cross-sectional view of the transistor 200C in the channel length direction, and Fig. 6C can also be considered a cross-sectional view of the transistor 200C in the channel width direction.

[0149] 6B and 6C differs from the transistor 200A shown in FIGS. 1B and 1C mainly in that the insulator 222 and the insulator 250 each have a three-layer stacked structure. Specifically, the transistor 200C shown in FIGS. 6B and 6C differs from the transistor 200A shown in FIGS. 1B and 1C mainly in that the transistor 200C has an insulator 250d between the insulator 250a and the insulator 250b and an insulator 222d between the insulator 222a and the insulator 222b. Hereinafter, differences from the above-described Configuration Example 1 will be mainly described, and descriptions of overlapping parts will be omitted.

[0150] The insulator 250 includes an insulator 250a, an insulator 250d on the insulator 250a, and an insulator 250b on the insulator 250d. The insulator 222 includes an insulator 222b, an insulator 222d on the insulator 222b, and an insulator 222a on the insulator 222d. In this case, the insulators 250a and 222a have an overlapping region via the region 230i, the insulators 250d and 222d have an overlapping region via the insulator 250a, the region 230i, and the insulator 222a, and the insulators 250b and 222b have an overlapping region via the insulator 250d, the insulator 250a, the region 230i, the insulator 222a, and the insulator 222d.

[0151] It is preferable that the insulators 250d and 222d have the function of capturing or fixing hydrogen. By providing an insulator having the function of capturing or fixing hydrogen inside the region surrounded by the insulators 250b and 222b, the hydrogen inside the region can be more effectively captured or fixed. In other words, the hydrogen contained in the insulator 250a, the region 230i of the oxide 230b, and the insulator 222a can be more effectively captured or fixed. Therefore, the hydrogen concentration in the region 230i can be reduced. Therefore, the V in the region 230i Ｏ H can be reduced to make region 230i i-type or substantially i-type.

[0152] Examples of insulators capable of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulator 250d and the insulator 222d, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0153] Furthermore, it is preferable to use a high-k material with a high relative dielectric constant (high-k) for the insulators 250d and 222d. Examples of high-k materials include oxides containing one or both of aluminum and hafnium, tantalum oxide, zirconium oxide, and hafnium zirconium oxide. As transistors become more miniaturized and highly integrated, thinning of the gate insulator can cause problems such as leakage current. Using high-k materials for the insulators 250d and 222d makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator. Examples of high-k materials for the insulators 250d and 222d include lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0154] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250d and the insulator 222d, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. In this embodiment, hafnium oxide is used as the insulator 250d and the insulator 222d. In this case, the insulator 250d and the insulator 222d each contain at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 250d and the insulator 222d have an amorphous structure.

[0155] With the above-described structure, the insulator 250d and the insulator 222d have the same function. Therefore, the first stacked body and the second stacked body can be provided symmetrically with respect to the channel formation region.

[0156] Note that, similar to the configuration shown in FIGS. 2A and 2B, the second gate insulator may be formed of a stack of an insulator 222 and an island-shaped insulator 224.

[0157] 7A and 7B show examples of a structure different from those shown in FIGS. 6B and 6C. FIGS. 7A and 7B are cross-sectional views of a semiconductor device including a transistor 200C. Here, FIG. 7A is a cross-sectional view of the transistor 200C in the channel length direction, and FIG. 7B is a cross-sectional view of the transistor 200C in the channel width direction. For top views of the semiconductor device shown in FIGS. 7A and 7B, refer to FIG. 6A.

[0158] The transistor 200C shown in FIGS. 7A and 7B differs from the transistor 200C shown in FIGS. 6B and 6C mainly in that the insulator 222 has a two-layer structure and that an island-shaped insulator 224 is included.

[0159] 7A and 7B , the insulator 222 has a stacked-layer structure of an insulator 222b and an insulator 222d over the insulator 222b. An island-shaped insulator 224 is provided between the insulator 222 and the oxide 230.

[0160] The insulator 250a has a region in contact with the upper surface of the insulator 222d, a region in contact with the side surface of the insulator 224, a region in contact with the side surface of the oxide 230, and a region in contact with the upper surface of the oxide 230. In this case, the region 230i of the oxide 230 is surrounded by the insulator 250a and the insulator 224.

[0161] The insulator 224 is preferably made of a material that can be used for the insulator 222a described above.

[0162] Note that the structures of the insulator 222 and the insulator 224 are not limited to those shown in FIGS. 7A and 7B. Examples of structures different from those shown in FIGS. 7A and 7B are shown in FIGS. 7C and 7D. FIGS. 7C and 7D are cross-sectional views of a semiconductor device including a transistor 200C. Here, FIG. 7C is a cross-sectional view of the transistor 200C in the channel length direction, and FIG. 7D is a cross-sectional view of the transistor 200C in the channel width direction. Note that FIG. 6A can be referred to for top views of the semiconductor device shown in FIGS. 7C and 7D.

[0163] 7C and 7D, the insulator 222 may have a single-layer structure, and the insulator 224 may have a laminated structure of an insulator 224d and an insulator 224a on the insulator 224d. In this case, it is preferable that the insulator 222 is made of a material that can be used for the insulator 222b described above. It is also preferable that the insulator 224d is made of a material that can be used for the insulator 222d described above, and the insulator 224a is made of a material that can be used for the insulator 222a described above.

[0164] With the above-described structure, the stack of the insulators 222 and 224 can be regarded as a second stack. In this case, the transistor 200C shown in Figures 7A and 7B and the transistor 200C shown in Figures 7C and 7D can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0165] <Configuration Example 4> Configuration examples different from the above-described transistors 200A to 200C are shown in FIGS. 8A to 8C. FIG. 8A is a top view of a semiconductor device, and FIGS. 8B and 8C are cross-sectional views of the semiconductor device. FIG. 8B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 8A. FIG. 8C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 8A. Note that some elements are omitted from the top view of FIG. 8A for clarity.

[0166] 8A to 8C include a transistor 200D. Therefore, Fig. 8B can also be considered a cross-sectional view of the transistor 200D in the channel length direction, and Fig. 8C can also be considered a cross-sectional view of the transistor 200D in the channel width direction.

[0167] 8B and 8C differs from the transistors 200A to 200C mainly in that the insulator 222 and the insulator 250 each have a four-layer stacked structure. The transistor 200D shown in FIGS. 8B and 8C can be considered to have a configuration in which the insulator 250d and the insulator 222d are added to the transistor 200B shown in FIGS. 3A to 3C. Alternatively, the transistor 200D can be considered to have a configuration in which the insulator 250c and the insulator 222c are added to the transistor 200C shown in FIGS. 6A to 6C. Hereinafter, differences from the above-described Configuration Examples 1 to 3 will be mainly described, and descriptions of overlapping parts will be omitted.

[0168] The insulator 250 includes an insulator 250c, an insulator 250a on the insulator 250c, an insulator 250d on the insulator 250a, and an insulator 250b on the insulator 250d. The insulator 222 includes an insulator 222b, an insulator 222d on the insulator 222b, an insulator 222a on the insulator 222d, and an insulator 222c on the insulator 222a. In this case, insulators 250c and 222c have an overlapping region via region 230i, insulators 250a and 222a have an overlapping region via insulator 250c, region 230i, and insulator 222c, insulators 250d and 222d have an overlapping region via insulator 250a, insulator 250c, region 230i, insulator 222c, and insulator 222a, and insulators 250b and 222b have an overlapping region via insulator 250d, insulator 250a, insulator 250c, region 230i, insulator 222c, insulator 222a, and insulator 222d.

[0169] By adopting the above-described structure, the first stacked body and the second stacked body can be provided symmetrically with respect to the channel forming region.

[0170] Note that the second gate insulator may be configured of an insulator 222 and an island-shaped insulator 224, similar to the configuration shown in FIGS. 2A and 2B.

[0171] 9A and 9B, 9C and 9D, and 9E and 9F show examples of structures different from those shown in FIGS. 8B and 8C. FIGS. 9A and 9B, 9C and 9D, and 9E and 9F are cross-sectional views of a semiconductor device including a transistor 200D, respectively. Here, FIGS. 9A, 9C, and 9E are cross-sectional views of the transistor 200D in the channel length direction, and FIGS. 9B, 9D, and 9F are cross-sectional views of the transistor 200D in the channel width direction. For top views of the semiconductor devices shown in FIGS. 9A and 9B, the semiconductor devices shown in FIGS. 9C and 9D, and the semiconductor devices shown in FIGS. 9E and 9F, refer to FIG. 8A.

[0172] The transistor 200D shown in Figures 9A and 9B, the transistor 200D shown in Figures 9C and 9D, and the transistor 200D shown in Figures 9E and 9F differ from the transistor 200D shown in Figures 8B and 8C mainly in that the transistor 200D has an island-shaped insulator 224 between the insulator 222 and the oxide 230.

[0173] 9A and 9B , the insulator 222 has a stacked-layer structure of the insulator 222b, the insulator 222d over the insulator 222b, and the insulator 222a over the insulator 222d, and the insulator 224 has a single-layer structure. The insulator 224 is preferably made of a material that can be used for the insulator 222c.

[0174] 9C and 9D , the insulator 222 has a stacked structure of an insulator 222b and an insulator 222d on the insulator 222b, and the insulator 224 has a stacked structure of an insulator 224a and an insulator 224c on the insulator 224a. It is preferable that the insulator 224a be made of a material that can be used for the insulator 222a, and that the insulator 224c be made of a material that can be used for the insulator 222c.

[0175] 9E and 9F , the insulator 222 has a single-layer structure, and the insulator 224 has a stacked structure of an insulator 224d, an insulator 224a on the insulator 224d, and an insulator 224c on the insulator 224a. The insulator 222 is preferably made of a material that can be used for the insulator 222b. The insulator 224d is preferably made of a material that can be used for the insulator 222d, the insulator 224a is preferably made of a material that can be used for the insulator 222a, and the insulator 224c is preferably made of a material that can be used for the insulator 222c.

[0176] With the above-described structure, the stack including the insulator 222 and the insulator 224 can be regarded as a second stack. In this case, the transistor 200D shown in Figures 9A and 9B, the transistor 200D shown in Figures 9C and 9D, and the transistor 200D shown in Figures 9E and 9F can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0177] Note that, similar to the structure shown in Figures 5A and 5B, the oxide 230 may have a stacked structure of oxide 230a and oxide 230b, and the oxide 230a may be made of a semiconductor material having a barrier property against oxygen.

[0178] 10A and 10B, 10C and 10D, and 10E and 10F show examples of structures different from those shown in FIGS. 8B and 8C. FIGS. 10A and 10B, 10C and 10D, and 10E and 10F are cross-sectional views of a semiconductor device including a transistor 200D. Here, FIGS. 10A, 10C, and 10E are cross-sectional views of the transistor 200D in the channel length direction, and FIGS. 10B, 10D, and 10F are cross-sectional views of the transistor 200D in the channel width direction. For top views of the semiconductor devices shown in FIGS. 10A and 10B, the semiconductor devices shown in FIGS. 10C and 10D, and the semiconductor devices shown in FIGS. 10E and 10F, refer to FIG. 8A.

[0179] 10A and 10B differs from the transistor 200D shown in Figures 8B and 8C mainly in that the oxide 230 has a two-layer stacked structure. The transistor 200D shown in Figures 10C and 10D and the transistor 200D shown in Figures 10E and 10F differ from the transistor 200D shown in Figures 8B and 8C mainly in that the transistor 200D has an island-shaped insulator 224 and that the oxide 230 has a two-layer stacked structure.

[0180] 10A and 10B , the insulator 222 has a stacked structure of an insulator 222b, an insulator 222d on the insulator 222b, and an insulator 222a on the insulator 222d, and the oxide 230 has a stacked structure of an oxide 230a and an oxide 230b on the oxide 230a. In this structure, the stack of the insulator 222 and the oxide 230a can be considered as a second stack. In this case, the transistor 200D shown in FIGS. 10A and 10B can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0181] 10C and 10D , the insulator 222 has a stacked-layer structure of an insulator 222b and an insulator 222d over the insulator 222b. The oxide 230 has a stacked-layer structure of an oxide 230a and an oxide 230b over the oxide 230a. The insulator 224 is preferably made of a material that can be used for the insulator 222a.

[0182] 10E and 10F, the insulator 224 includes an insulator 224d and an insulator 224a over the insulator 224d. The oxide 230 has a stacked structure of an oxide 230a and an oxide 230b over the oxide 230a. The insulator 222 is preferably made of a material that can be used for the insulator 222b. The insulator 224d is preferably made of a material that can be used for the insulator 222d, and the insulator 224a is preferably made of a material that can be used for the insulator 222a.

[0183] With the above-described structure, the stack of the insulator 222, the insulator 224, and the oxide 230a can be regarded as a second stack. In this case, the transistor 200D shown in Figures 10C and 10D and the transistor 200D shown in Figures 10E and 10F can be said to have a structure in which the first stack and the second stack are provided symmetrically with respect to the channel formation region.

[0184] Note that if the hydrogen concentration in the insulator 250a, the insulator 222a, or the region 230i is sufficiently low, one of the insulator 250d and the insulator 222d may be provided.

[0185] 11A and 11B, 11C and 11D, 12A and 12B, and 12C and 12D are cross-sectional views of a semiconductor device including a transistor 200D. Here, FIGS. 11A, 11C, 12A, and 12C are cross-sectional views of the transistor 200D in the channel length direction, and FIGS. 11B, 11D, 12B, and 12D are cross-sectional views of the transistor 200D in the channel width direction. For top views of the semiconductor devices shown in FIGS. 11A and 11B and 11C and 11D, refer to FIG. 3A. For top views of the semiconductor devices shown in FIGS. 12A and 12B and 12C and 12D, refer to FIG. 8A.

[0186] For example, the transistor 200D shown in FIGS. 11A and 11B and the transistor 200D shown in FIGS. 11C and 11D include the insulator 222d but do not include the insulator 250d.

[0187] 11A and 11B differs from the transistor 200B shown in FIGS. 4C and 4D in that it includes an insulator 222d. The transistor 200D shown in FIGS. 11A and 11B also differs from the transistor 200D shown in FIGS. 9C and 9D in that it does not include an insulator 250d. Therefore, the transistor 200D shown in FIGS. 11A and 11B can be considered a modified example of the transistor 200B shown in FIGS. 4C and 4D or a modified example of the transistor 200D shown in FIGS. 9C and 9D.

[0188] 11C and 11D differs from the transistor 200B shown in FIGS. 5C and 5D in that the transistor 200D shown in FIGS. 11C and 11D includes an insulator 222d between the insulator 222b and the insulator 224. The transistor 200D shown in FIGS. 11C and 11D also differs from the transistor 200D shown in FIGS. 10C and 10D in that the transistor 200D does not include the insulator 250d. Therefore, the transistor 200D shown in FIGS. 11C and 11D can be considered a modified example of the transistor 200B shown in FIGS. 5C and 5D or a modified example of the transistor 200D shown in FIGS. 10C and 10D. The transistor 200D shown in FIGS. 10C and 10D has a configuration in which the insulator 250d is provided between the insulator 250a and the insulator 250b in the transistor 200D shown in FIGS. 11C and 11D.

[0189] Furthermore, for example, the transistor 200D illustrated in FIGS. 12A and 12B and the transistor 200D illustrated in FIGS. 12C and 12D include the insulator 250d but do not include the insulator 222d.

[0190] 12A and 12B differs from the transistor 200B shown in FIGS. 4C and 4D in that it includes an insulator 250d. The transistor 200D shown in FIGS. 12A and 12B also differs from the transistor 200D shown in FIGS. 9C and 9D in that it does not include the insulator 222d. Therefore, the transistor 200D shown in FIGS. 12A and 12B can be considered a modified example of the transistor 200B shown in FIGS. 4C and 4D or a modified example of the transistor 200D shown in FIGS. 9C and 9D.

[0191] The transistor 200D shown in FIGS. 12C and 12D differs from the transistor 200B shown in FIGS. 5C and 5D in that it includes an insulator 250d. In other words, the transistor 200D shown in FIGS. 12C and 12D has a configuration in which the insulator 250d is added to the transistor 200B shown in FIGS. 5C and 5D. The transistor 200D shown in FIGS. 12C and 12D differs from the transistor 200D shown in FIGS. 10C and 10D in that it does not include the insulator 222d. Thus, the transistor 200D shown in FIGS. 12C and 12D can be considered a modified version of the transistor 200B shown in FIGS. 5C and 5D or a modified version of the transistor 200D shown in FIGS. 10C and 10D.

[0192] Note that the insulator 222 of the transistor 200D shown in Figures 12A and 12B and the transistor 200D shown in Figures 12C and 12D may be made of a material that can be used for the insulator 222b described above, or may be made of a material that can be used for the insulator 222d described above.

[0193] When the insulator 222 of the transistor 200D illustrated in FIGS. 12A and 12B and the transistor 200D illustrated in FIGS. 12C and 12D is made of a material that can be used for the insulator 222d, the insulator 222 preferably also has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of hydrogen better than the insulator 224 (the insulator 224a in the transistor 200D illustrated in FIGS. 12A and 12B). The insulator 222 may also have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). In this case, the insulator 222 preferably has a function of suppressing the diffusion of oxygen better than the insulator 224 (the insulator 224a in the transistor 200D illustrated in FIGS. 12A and 12B).

[0194] 12A and 12B and the transistor 200D shown in FIGS. 12C and 12D, the insulator 222 preferably uses an oxide of one or both of aluminum and hafnium, or an oxide containing hafnium and zirconium. When such an oxide is used as the insulator 222, the insulator 222 functions as a layer that suppresses the diffusion of impurities such as hydrogen from the substrate side to the oxide 230 and suppresses the release of oxygen from the oxide 230 to the substrate side. Therefore, the diffusion of impurities such as hydrogen into the inside of the transistor 200D can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the conductor 205 can be suppressed from reacting with oxygen contained in the oxide 230.

[0195] The insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided.

[0196] For example, when an oxide of one or both of aluminum and hafnium is used as the insulator 222, it is preferable to increase the film thickness of the insulator 222. For example, the film thickness of the insulator 222 is preferably greater than the film thickness of the insulator 250d, and more preferably greater than the sum of the film thicknesses of the insulators 250d and 250b. By increasing the film thickness of the insulator 222, the insulator 222 may have the function of capturing or fixing hydrogen and the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). In this case, the insulator 222 can have both the function of the material applicable to the insulator 222b described above and the function of the material applicable to the insulator 222d described above. With this structure, the transistor 200D shown in Figures 12A and 12B and the transistor 200D shown in Figures 12C and 12D can be said to have a structure in which the first stack and the second stack are arranged symmetrically with respect to the channel formation region.

[0197] <Application Example> In a semiconductor device according to one embodiment of the present invention, an insulator having a barrier property against hydrogen may be provided above the first gate electrode and / or below the second gate electrode.

[0198] 13A and 13B, 13C and 13D, and 13E and 13F are cross-sectional views of a semiconductor device including a transistor 200E. Here, FIGS. 13A, 13C, and 13E are cross-sectional views of the transistor 200E in the channel length direction, and FIGS. 13B, 13D, and 13F are cross-sectional views of the transistor 200E in the channel width direction. Note that FIG. 1A can be referred to for top views of the semiconductor device shown in FIGS. 13A and 13B, the semiconductor device shown in FIGS. 13C and 13D, and the semiconductor device shown in FIGS. 13E and 13F. Hereinafter, differences from the above-described Configuration Examples 1 to 4 will be mainly described, and descriptions of overlapping parts will be omitted.

[0199] 13A and 13B, an insulator 283 is provided above the conductor 260. In addition, in the transistor 200E shown in Figures 13C and 13D, an insulator 215 is provided below the conductor 205. In addition, in the transistor 200E shown in Figures 13E and 13F, an insulator 283 is provided above the conductor 260 and an insulator 215 is provided below the conductor 205.

[0200] The insulator 283 preferably has a barrier property against hydrogen, similar to the insulator 250b. Providing the insulator 283 can prevent impurities such as hydrogen contained in structures provided above the insulator 283 from diffusing into the region 230i. Similarly to the insulator 222b, the insulator 215 preferably has a barrier property against hydrogen. Providing the insulator 215 can prevent impurities such as hydrogen contained in structures provided below the insulator 215 from diffusing into the region 230i.

[0201] In the transistor 200E including the insulator 215, the insulator 216 is provided over the insulator 215, and the conductor 205 is arranged to fill an opening formed in the insulator 216. The height of the top surface of the conductor 205 is flush with the height of the top surface of the insulator 216.

[0202] Furthermore, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby suppressing the diffusion of the impurities into the oxide 230.

[0203] The insulator 216 preferably has a lower dielectric constant than the insulator 215. For example, the insulator 216 may be an insulator that can be used for the insulator 280.

[0204] Note that if providing the insulator 283 having a function similar to that of the insulator 250b can sufficiently suppress diffusion of hydrogen from above the transistor 200 to the region 230i, the insulator 250b may not be provided. If providing the insulator 215 having a function similar to that of the insulator 222b can sufficiently suppress diffusion of hydrogen from below the transistor 200 to the region 230i, the insulator 222b may not be provided.

[0205] 14A and 14B, 14C and 14D, and 14E and 14F are cross-sectional views of a semiconductor device including a transistor 200E. Here, FIGS. 14A, 14C, and 14E are cross-sectional views of the transistor 200E in the channel length direction, and FIGS. 14B, 14D, and 14F are cross-sectional views of the transistor 200E in the channel width direction. For top views of the semiconductor devices shown in FIGS. 14A and 14B and 14C and 14D, refer to FIG. 8A. For top views of the semiconductor devices shown in FIGS. 14E and 14F, refer to FIG. 3A.

[0206] The transistor 200E shown in Figures 14A and 14B differs from the transistor 200D shown in Figures 9C and 9D in that it has an insulator 215 but does not have an insulator 222b. The transistor 200E shown in Figures 14C and 14D differs from the transistor 200D shown in Figures 10C and 10D. The transistor 200E shown in Figures 14E and 14F differs from the transistor 200E shown in Figures 11C and 11D in that it has an insulator 215 but does not have an insulator 222b.

[0207] Even when the insulator 222b is not provided as shown in Figures 14A to 14F, the increase in the hydrogen concentration in region 230i can be suppressed by providing an insulator having the function of capturing or fixing hydrogen between the conductor 205 and the insulator 216 and the oxide 230.

[0208] 12A and 12B, and the transistor 200D shown in Figures 12C and 12D, the transistor 200E shown in Figures 14A and 14B, the transistor 200E shown in Figures 14C and 14D, and the transistor 200E shown in Figures 14E and 14F can be considered to have a structure in which the first stack and the second stack are arranged symmetrically with respect to the channel formation region by forming a thick insulator 222 using a material that can be used for the above-mentioned insulator 222b.

[0209] <Detailed Configuration Example> A detailed configuration example of a semiconductor device including a transistor will be described with reference to FIGS. 15A to 15D. FIG.

[0210] FIG. 15A is a top view of a semiconductor device including a transistor 200, and FIGS. 15B to 15D are cross-sectional views of the semiconductor device. Here, FIG. 15B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 15A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 15C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 15A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 15D is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 15A and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view of FIG. 15A for clarity. Hereinafter, differences from the above description will be mainly described, and overlapping portions will not be described.

[0211] The transistor 200 includes an insulator 216 on the insulator 215, a conductor 205 (conductor 205a and conductor 205b) embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230 on the insulator 224, conductors 242a and 242b on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

[0212] An insulator 275 is provided on the insulator 271a and the insulator 271b, and an insulator 280 is provided on the insulator 275. An insulator 250 and a conductor 260 are embedded inside openings formed in the insulator 280 and the insulator 275. An insulator 282 is provided on the insulator 280, the conductor 260, and the insulator 250. An insulator 283 is provided on the insulator 282.

[0213] 15B , in a cross-sectional view of the transistor 200, it is preferable that one side edge of the conductor 242a coincides with one side edge of the oxide 230, and one side edge of the conductor 242b coincides with the other side edge of the oxide 230. Furthermore, it is preferable that the side edge of the insulator 224 coincides with the side edge of the oxide 230. By processing the insulator 224, the oxide 230, and the conductive layers that will become the conductors 242a and 242b together into an island shape, a semiconductor device can be manufactured with good productivity. At this time, the side edges of the insulator 224, the oxide 230, the conductor 242a, and the conductor 242b coincide with each other, as described above.

[0214] The transistor 200 illustrated in FIGS. 15A to 15D may have any one of the structures of the transistors 200A to 200E described above.

[0215] 16A and 16B show an example in which the structure of the transistor 200D shown in FIGS. 11C and 11D is applied to the transistor 200 shown in FIGS. 15A to 15D. FIG. 16A is an enlarged cross-sectional view of the transistor 200 in the channel length direction, and FIG. 16B is an enlarged cross-sectional view of the transistor 200 in the channel width direction.

[0216] 17A and 17B show an example in which the structure of the transistor 200E shown in FIGS. 14C and 14D is applied to the transistor 200 shown in FIGS. 15A to 15D. FIG. 17A is an enlarged cross-sectional view of the transistor 200 in the channel length direction, and FIG. 17B is an enlarged cross-sectional view of the transistor 200 in the channel width direction.

[0217] As shown in FIGS. 16A to 17B, the oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a.

[0218] The oxide 230a and the oxide 230b preferably have different chemical compositions. When the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230a and the oxide 230b can be reduced. The density of defect states at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0219] The oxide 230b is preferably a crystalline oxide semiconductor. Examples of crystalline oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductors, single-crystalline oxide semiconductors, and the like. The oxide 230b is preferably a CAAC-OS or nc-OS, and particularly preferably a CAAC-OS.

[0220] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0221] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0222] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, oxygen can be prevented from being extracted from the oxide 230b by the conductor 242a or the conductor 242b. Therefore, even when heat treatment is performed, oxygen can be prevented from being extracted from the oxide 230b, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process. Furthermore, a decrease in the conductivity of the conductors 242a and 242b can be prevented.

[0223] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals (also referred to as nanocrystals). Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals, and therefore does not exhibit orientation throughout the film. That is, when the nc-OS is used as the oxide 230b, the film characteristics of the oxide 230b are constant regardless of the direction of carriers flowing through the oxide 230b, and thus the electrical characteristics of the transistor are stable.

[0224] The oxide 230b may include two or more of a CAAC-OS, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and a cloud-aligned composite oxide semiconductor (CAC-OS).

[0225] When a CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. The position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS. Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that one spot and another spot are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has transmitted through the sample (also referred to as the direct spot).

[0226] Furthermore, when electron beam diffraction (also called nanobeam electron beam diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm or more and 30 nm or less) equal to or smaller than the size of the nanocrystal, an electron beam diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0227] 16A and 17A, the oxide 230b has a region 230bi and regions 230bna and 230bnb that are provided to sandwich the region 230bi. Note that for the region 230bi, the region 230bna, and the region 230bnb, the above-mentioned descriptions of the region 230i, the region 230na, and the region 230nb can be referred to.

[0228] 16A to 17B show an example in which the oxide 230 has a two-layer structure of oxide 230a and oxide 230b, but this is not limiting. The oxide 230 may have a single-layer structure, for example, as shown in FIGS. 1B and 1C. Alternatively, one or both of the oxide 230a and the oxide 230b may have a stacked structure of two or more layers. When the oxide 230 has a single-layer structure, the oxide 230 may be made of a metal oxide that can be used for the oxide 230a.

[0229] 16A and 16B, it is preferable that the insulator 250 has a layered structure of an insulator 250c in contact with the oxide 230, an insulator 250a on the insulator 250c, and an insulator 250b on the insulator 250a. Alternatively, it is preferable that the insulator 250 has a layered structure of an insulator 250c in contact with the oxide 230, an insulator 250a on the insulator 250c, an insulator 250d on the insulator 250a, and an insulator 250b on the insulator 250d, as shown in FIGS.

[0230] The insulators 250a to 250d, together with the conductor 260, are provided inside openings formed in the insulator 280 or the like. To miniaturize the transistor 200, the insulators 250a to 250d preferably have thin film thicknesses. The insulators 250a to 250d each have a film thickness of preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region with the above film thickness at least in part.

[0231] To thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to form the insulators using an atomic layer deposition (ALD) method. ALD methods include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0232] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling extremely thin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulators 280 and 275, and the side ends of the conductors 242a and 242b, and with the thin film thickness described above.

[0233] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0234] Although the above description has been given of a structure in which the insulator 250 has a three-layer structure of insulators 250a to 250c or a four-layer structure of insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can also have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0235] As shown in Figures 16A and 16B, the insulator 222 preferably has a layered structure of an insulator 222b on the insulator 216 and the conductor 205, and an insulator 222d on the insulator 222b.

[0236] The insulator 222b is provided between the insulator 216 and the conductor 205 and the insulator 222d. The insulator 222b preferably has a function of suppressing hydrogen diffusion. This can suppress hydrogen diffusion from below the insulator 222b to the transistor 200. Note that the insulator 222b can also have the function of the insulator 215. In such a case, by not providing the insulator 215, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0237] The insulator 222b is preferably made of silicon nitride formed by, for example, the ALD method (particularly the PEALD method). By using the ALD method to form the insulator 222b, the insulator 222b can be formed with good coverage even if unevenness is formed between the insulator 216 and the conductor 205. Therefore, the formation of pinholes or discontinuities in the insulator 222d formed on the insulator 222b can be suppressed.

[0238] 17A and 17B, the insulator 222 preferably has a single-layer structure. Note that, similar to the transistor 200D illustrated in FIGS. 12A and 12B and the transistor 200D illustrated in FIGS. 12C and 12D, the insulator 222 is preferably formed to have a large thickness using a material that can be used for the insulator 222b.

[0239] Although the insulator 222 has been described above as having a single-layer structure or a two-layer structure of the insulators 222b and 222d, the present invention is not limited to this. The insulator 222 may have a stacked structure of three or more layers.

[0240] The insulator 224 is preferably processed into an island shape, similar to the oxide 230. As a result, when multiple transistors 200 are provided, the insulators 224 are provided with approximately the same size for each transistor 200. As a result, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0241] The insulator 224 may have a layered structure of two or more layers. In this case, the layered structure is not limited to layers made of the same material, and may be a layered structure made of different materials. Furthermore, as shown in FIG. 1B , the insulator 224 may not be provided.

[0242] The insulator 275 preferably has barrier properties against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. Providing the insulator 275 can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to prevent the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, thereby increasing their resistivity and reducing their on-state current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 contains at least nitrogen and silicon.

[0243] The insulator 275 is provided between the insulator 280 and the region 230bna, and between the insulator 280 and the region 230bnb. In other words, the region 230bna and the region 230bnb are surrounded by the insulator 275 and the oxide 230a. This prevents oxygen contained in the insulator 280 from diffusing into the region 230bna and the region 230bnb.

[0244] The insulator 275 preferably has a barrier property against hydrogen. When the insulator 275 has a barrier property against hydrogen, a decrease in the hydrogen concentration in the regions 230bna and 230bnb can be suppressed.

[0245] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0246] By using the above-described configuration, the region 230bi can be made i-type or substantially i-type, and the regions 230bna and 230bnb can be made n-type. Therefore, a semiconductor device with good electrical characteristics can be provided. Furthermore, even if the semiconductor device is miniaturized or highly integrated, good electrical characteristics can be maintained. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0247] The insulator 271a contacts the upper surface of the conductor 242a and the lower surface of the insulator 275, and the insulator 271b contacts the upper surface of the conductor 242b and the lower surface of the insulator 275.

[0248] The insulators 271a and 271b function as etching stoppers that protect the conductors 242a and 242b. Therefore, as shown in FIG. 15B , in a cross-sectional view of the transistor 200, it is preferable that the side edge of the insulator 271a coincides with the side edge of the conductor 242a, and the side edge of the insulator 271b coincides with the side edge of the conductor 242b.

[0249] The insulators 271a and 271b are preferably inorganic insulators that are unlikely to oxidize the conductors 242a and 242b because they are in contact with the conductors 242a and 242b, respectively. For example, the insulators 271a and 271b are preferably made of a nitride insulator that can be used for the insulator 250b.

[0250] 15B, the insulators 271a and 271b are shown as single layers, but the present invention is not limited to this. Each of the insulators 271a and 271b may have a layered structure.

[0251] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that suppresses hydrogen from being mixed into the transistor 200 and the like. For example, an insulator that has a function of suppressing hydrogen diffusion is preferably provided so as to cover one or both of the top and bottom of the transistor 200 and the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 215, the insulator 282, the insulator 283, or the like. Note that the insulator 215 provided under the transistor 200 may have a structure similar to one or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom. When the insulator 215 is configured with the insulator 282 on top and the insulator 283 on the bottom, the insulator 215, the insulator 282, and the insulator 283 are arranged symmetrically with respect to the channel formation region.

[0252] It is preferable that one or both of the insulators 282 and 283 function as a barrier insulator that prevents impurities such as water and hydrogen from diffusing from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or both of the insulators 282 and 283 can prevent impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0253] The insulators 282 and 283 preferably have an insulator that has a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulator 283 is preferably made of silicon nitride, which has a higher hydrogen barrier property. Furthermore, the insulator 282 preferably includes aluminum oxide or magnesium oxide, which has a high function of capturing or fixing hydrogen. This can suppress diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 283 to the transistor 200 or the like. Furthermore, oxygen contained in the insulator 280 or the like can be suppressed from diffusing upward from the transistor 200 or the like through the insulator 282 or the like. Furthermore, by using the insulator 215 with a structure similar to one or both of the insulators 282 and 283, diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 or the like through the insulator 215 can be suppressed. Furthermore, oxygen contained in the insulator 224 can be prevented from diffusing toward the substrate. In this manner, it is preferable to have a structure in which the top and bottom of the transistor 200 and the like are surrounded by insulators that have a function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0254] The conductor 205 may have a single-layer structure or a multilayer structure. In Figures 15B and 15C, the conductor 205 has a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening formed in the insulator 216. The conductor 205b is provided so as to fill a recess of the conductor 205a formed along the opening.

[0255] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0256] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0257] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0258] The conductor 242a and the conductor 242b each have a region in contact with the oxide 230b. The conductor 242a and the conductor 242b may have a single-layer structure or a stacked structure. For example, as shown in FIG. 16A, the conductor 242a and the conductor 242b may each have a two-layer structure. In this case, the conductor 242a is a stacked structure of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b is a stacked structure of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. In this case, it is preferable to use the above-mentioned conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the layer in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1). This prevents the conductor 242a and the conductor 242b from being excessively oxidized by the oxygen contained in the oxide 230b. In addition, the conductivity of the conductors 242a and 242b can be prevented from decreasing.

[0259] Furthermore, the conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1. For example, the film thicknesses of the conductors 242a2 and 242b2 are preferably larger than the film thicknesses of the conductors 242a1 and 242b1. Conductors applicable to the conductor 205b may be used for the conductors 242a2 and 242b2. The above structure can reduce the resistance of the conductors 242a2 and 242b2. This allows the conductors 242a and 242b to function as wirings or electrodes with high conductivity. Furthermore, the operating speed of the transistor 200 can be improved.

[0260] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0261] 16A to 17B, the conductor 260 is arranged so as to fill the openings formed in the insulator 280 and the insulator 275. The conductor 260 is provided in the openings so as to cover, via the insulator 250, the side surfaces of the insulator 224, the side surfaces of the oxide 230a, and the side surfaces and top surface of the oxide 230b.

[0262] 16B and 17B , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end portions of the side surface and the top surface may be curved (hereinafter also referred to as rounded). Such a shape can improve the coverage of the oxide 230b with the insulator 250 and the conductor 260.

[0263] 16B and 17B , in a configuration in which the island-shaped insulator 224 is provided, at least a portion of the lower surface of the conductor 260 can be provided below the lower surface of the oxide 230b. This allows the conductor 260 to be provided facing the upper surface and side surface of the oxide 230b, so that the electric field of the conductor 260 can be applied to the upper surface and side surface of the oxide 230b. In this way, by providing the insulator 224 in an island-like configuration, a transistor with an S-channel structure can be easily realized.

[0264] The S-channel structure disclosed in this specification and the like has a structure different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification and the like can also be regarded as a type of Fin structure. In this specification and the like, the Fin structure refers to a structure in which a gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin structure and the S-channel structure, it is possible to increase resistance to the short channel effect, in other words, to obtain a transistor in which the short channel effect is less likely to occur.

[0265] The S-channel structure of the transistor 200 allows the channel formation region to be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure.

[0266] 16B and 17B illustrate an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0267] 16A and 17A show the conductor 260 as having a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0268] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0269] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0270] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0271] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242 a and the conductor 242 b without alignment.

[0272] 16A shows a configuration in which the insulator 250c contacts the side surfaces of the conductor 242a2 and the conductor 242b2, but the present invention is not limited to this. For example, an insulator 255 may be provided between the insulator 250c and the conductor 242a2 and between the insulator 250c and the conductor 242b2.

[0273] 18A and 18B are enlarged cross-sectional views of the transistor 200 in the channel length direction. The semiconductor device shown in FIG. 18A and the semiconductor device shown in FIG. 18B are modifications of the semiconductor device shown in FIG. 16A. Specifically, the semiconductor device shown in FIG. 18A and the semiconductor device shown in FIG. 18B differ from the semiconductor device shown in FIG. 16A in that an insulator 255 is provided between the insulator 250c and the conductor 242a2 and between the insulator 250c and the conductor 242b2.

[0274] 18A, in a cross-sectional view of the transistor 200 in the channel length direction, the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0275] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and functions to protect the conductors 242a2 and 242b2. Because the insulator 255 is exposed to an oxidizing atmosphere, an inorganic insulator that is resistant to oxidation is preferable. Furthermore, because the insulator 255 is in contact with the conductors 242a2 and 242b2, an inorganic insulator that is resistant to oxidation is preferable. Therefore, the insulator 255 is preferably an insulating material that has barrier properties against oxygen. For example, silicon nitride can be used as the insulator 255.

[0276] The transistor 200 shown in FIG. 18A is formed by forming openings in the insulators 280 and 275, forming an insulator 255 in contact with the sidewalls of the openings, and then separating the conductors 242a1 and 242b1 using a mask. The openings overlap with the region between the conductors 242a2 and 242b2. Parts of the conductors 242a1 and 242b1 protrude into the openings. Therefore, the insulator 255 is in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 in the openings. The insulator 250 is in contact with the top surface of the oxide 230 in the region between the conductors 242a1 and 242b1.

[0277] After separating the conductor 242a1 from the conductor 242b1, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen vacancies. Furthermore, by forming the insulator 255 in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented. As a result, the electrical characteristics and reliability of the transistor can be improved. Furthermore, variation in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed.

[0278] 18A shows a configuration in which the insulator 250 has a region overlapping with the conductor 242a1 and the conductor 242b1 via the insulator 255, but the present invention is not limited to this. For example, as shown in FIG. 18B , in openings formed in the insulator 280 and the insulator 275, a side surface of the insulator 255 may coincide with a side surface of the conductor 242a1, and a side surface of the insulator 255 may coincide with a side surface of the conductor 242b1. With such a configuration, the above-described step of separating the conductor 242a1 and the conductor 242b1 using a mask can be omitted, thereby simplifying the manufacturing process of the semiconductor device and improving productivity.

[0279] Note that although Figures 18A and 18B show an example in which the structure of transistor 200D shown in Figures 11C and 11D is applied as the first stack and the second stack, it is preferable to apply the structure of any one of transistors 200A to 200E described above.

[0280] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0281] <<Substrate>> Examples of substrates for forming transistors include insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulator region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, substrates having a conductor or semiconductor provided on an insulator substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0282] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0283] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0284] Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0285] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having pores, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Note that materials with a low relative dielectric constant also have a high dielectric strength.

[0286] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0287] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0288] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0289] When a conductor with a layered structure is used, for example, a layered structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a layered structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a layered structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be applied.

[0290] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0291] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the above-mentioned conductive materials containing the metal element and nitrogen may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0292] The semiconductor device according to this embodiment includes an OS transistor. The OS transistor has a small off-state current, which allows a semiconductor device with low power consumption to be realized. Furthermore, the OS transistor has high frequency characteristics, which allows a semiconductor device with high operating speed to be realized. Furthermore, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in the electrical characteristics of transistors, a semiconductor device with large on-state current, and a highly reliable semiconductor device can be realized.

[0293] <Application Example of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 19A to 19C.

[0294] FIG. 19A shows a top view of the semiconductor device 500. The x-axis in FIG. 19A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis. FIG. 19B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in FIG. 19A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 19C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in FIG. 19A and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted from the top view in FIG. 19A for clarity.

[0295] 19A to 19C, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Detailed Configuration Example>. Note that, in this section as well, the materials described in detail in <Detailed Configuration Example> can be used as the constituent materials of the semiconductor device.

[0296] 19A to 19C is a modified example of the semiconductor device shown in Figures 15A to 15D. The semiconductor device 500 shown in Figures 19A to 19C differs from the semiconductor device shown in Figures 15A to 15D in that an opening region 400 is formed in the insulator 282 and the insulator 280. The semiconductor device 500 also differs from the semiconductor device shown in Figures 15A to 15D in that a sealing portion 265 is formed so as to surround the multiple transistors 200.

[0297] The semiconductor device 500 has a plurality of transistors 200 and a plurality of opening regions 400 arranged in a matrix. Furthermore, a plurality of conductors 260 functioning as gate electrodes of the transistors 200 are provided extending in the y-axis direction. The opening regions 400 are formed in regions that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed so as to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of opening regions 400. Note that the number, arrangement, and size of the transistors 200, the conductors 260, and the opening regions 400 are not limited to the structures shown in FIGS. 19A to 19C , and may be set appropriately in accordance with the design of the semiconductor device 500.

[0298] An insulator 285 is provided over the insulator 283. As the insulator 285, an insulator similar to the insulator 280 can be used.

[0299] 19B and 19C , the sealing portion 265 is provided to surround the plurality of transistors 200, the insulators 216, 222, 275, 280, and 282. In other words, the insulator 283 is provided to cover the plurality of transistors 200, the insulators 216, 222, 275, 280, and 282. Furthermore, in the sealing portion 265, the insulator 283 is in contact with the upper surface of the insulator 215b. Furthermore, above the sealing portion 265, an insulator 274 is provided between the insulators 283 and 285. The upper surface of the insulator 274 is flush with the uppermost surface of the insulator 283. Furthermore, the insulator 274 may be made of the same insulator as the insulator 280.

[0300] With this structure, the multiple transistors 200 can be enclosed by the insulator 283, the insulator 215b, and the insulator 215a. Here, it is preferable that one or more of the insulators 283, 215b, and 215a function as a barrier insulator against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from mixing into the region of the sealing portion 265.

[0301] 19C , insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove in opening region 400, overlapping the opening of insulator 282. The depth of the groove in insulator 280 may be at most deep enough to expose the top surface of insulator 275, and may be, for example, approximately ¼ to ½ of the maximum film thickness of insulator 280.

[0302] 19C , insulator 283 contacts the side surface of insulator 282, the side surface of insulator 280, and the top surface of insulator 280 inside opening region 400. In addition, a portion of insulator 274 may be formed within opening region 400 so as to fill a recess formed in insulator 283. In this case, the height of the top surface of insulator 274 formed within opening region 400 may coincide with the height of the top surface of insulator 283.

[0303] By performing heat treatment in a state where the opening region 400 is formed and the insulator 280 is exposed through the opening of the insulator 282, oxygen can be supplied to the oxide 230 while some of the oxygen contained in the insulator 280 diffuses outward from the opening region 400. This allows sufficient oxygen to be supplied from the insulator 280, which contains oxygen released by heating, to a region in the oxide semiconductor that functions as a channel formation region and its vicinity, while preventing excessive oxygen from being supplied.

[0304] At this time, the hydrogen contained in the insulator 280 can be bonded with oxygen and released to the outside through the opening region 400. The hydrogen bonded with oxygen is released as water. Therefore, the hydrogen contained in the insulator 280 can be reduced, and the hydrogen contained in the insulator 280 can be prevented from mixing with the oxide 230.

[0305] 19A , the shape of the opening region 400 in a top view is substantially rectangular, but the present invention is not limited to this. For example, the shape of the opening region 400 in a top view may be rectangular, elliptical, circular, diamond-shaped, or a combination thereof. The area and spacing of the opening regions 400 can be appropriately set in accordance with the design of the semiconductor device including the transistors 200. For example, in a region where the density of the transistors 200 is low, the area of ​​the opening regions 400 can be increased or the spacing between the opening regions 400 can be narrowed. For example, in a region where the density of the transistors 200 is high, the area of ​​the opening regions 400 can be narrowed or the spacing between the opening regions 400 can be widened.

[0306] According to one embodiment of the present invention, a novel transistor can be provided. Alternatively, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a semiconductor device with favorable reliability can be provided. Alternatively, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, a semiconductor device with high on-state current can be provided. Alternatively, a semiconductor device with high field-effect mobility can be provided. Alternatively, a semiconductor device with favorable frequency characteristics can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[0307] 20A and 20B show a semiconductor device including the above-described transistor 200 and capacitor 100. Fig. 20A is a top view of the semiconductor device. Fig. 20B is a cross-sectional view of a portion indicated by the dashed dotted line A1-A2 in Fig. 20A and is also a cross-sectional view of the transistor 200 in the channel length direction. Note that some elements are omitted from the top view in Fig. 20A for clarity.

[0308] 20A and 20B , the capacitor 100 and the conductor 112 are arranged over the transistor 200. Here, it is preferable that the overlapping area between the capacitor 100 and the transistor 200 is large when viewed from above. With such a configuration, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced. This allows miniaturization or high integration of the semiconductor device to be achieved.

[0309] The semiconductor device includes a conductor 240a and a conductor 240b that function as plugs. The conductor 240a is provided inside an opening formed in the insulators 285, 283, 282, 280, 275, and 271a, and the conductor 240b is provided inside an opening formed in the insulators 285, 283, 282, 280, 275, and 271b.

[0310] 20B , the conductor 240a has a region in contact with the conductor 242a and a region in contact with at least a part of the bottom surface of the conductor 112. The conductor 240b has a region in contact with the conductor 242b and a region in contact with at least a part of the bottom surface of the conductor 110 of the capacitor 100. In other words, the conductor 240a is electrically connected to one of the source and drain of the transistor 200, and the conductor 240b is electrically connected to the other of the source and drain of the transistor 200.

[0311] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, etc. Each of the conductors 240a and 240b may have a laminated structure of a first conductor provided along the side and bottom surfaces of the opening and a second conductor on the first conductor.

[0312] When the conductor 240a and the conductor 240b have a layered structure, the first conductor disposed near the insulator 285 and the insulator 280 is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. This structure can prevent impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. Since the second conductor also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum may be used as the second conductor.

[0313] 20B shows a structure in which a first conductor and a second conductor are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0314] An insulator 241a is provided in contact with the inner walls of openings formed in insulators 285, 283, 282, 280, 275, and 271a, as well as with the side surfaces of conductor 240a. An insulator 241b is provided in contact with the inner walls of openings formed in insulators 285, 283, 282, 280, 275, and 271b, as well as with the side surfaces of conductor 240b. Each of insulators 241a and 241b has a structure in which a first insulator is provided in contact with the inner walls of the openings, and a second insulator is further provided inside.

[0315] The insulators 241a and 241b may be barrier insulators against one or both of hydrogen and oxygen. For example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide is preferably used for the insulators 241a and 241b. Other examples of usable materials include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide. The insulators 241a and 241b are provided in contact with the insulators 283, 282, and 275, respectively, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from being mixed into the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because of its high barrier properties against hydrogen.

[0316] The insulator 241a is provided between the insulator 280 and the conductor 240a, and the insulator 241b is provided between the insulator 280 and the conductor 240b. The insulator 280 contains excess oxygen and is provided near the oxide semiconductor. By using a barrier insulator against oxygen as the insulators 241a and 241b, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0317] When the insulators 241a and 241b are formed into a layered structure as shown in Figure 20B, it is preferable that the first insulator in contact with the inner wall of the opening formed in the insulator 280, etc., and the second insulator inside it be made of a combination of a barrier insulator against oxygen and a barrier insulator against hydrogen.

[0318] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. This configuration can prevent the conductors 240 a and 240 b from being oxidized and can also prevent hydrogen from being mixed into the conductors 240 a and 240 b.

[0319] <Capacitor 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode (also referred to as a lower electrode), a conductor 120 that functions as a second electrode (also referred to as an upper electrode), and an insulator 132 that functions as a dielectric. A pair of electrodes of the capacitor 100 is formed of the first electrode and the second electrode.

[0320] The conductor 110 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the alloy containing the above metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0321] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0322] The conductor 120 may be made of a conductive material that can be used for the conductor 110 .

[0323] For example, the conductor 112 provided over the conductor 240a and the conductor 110 provided over the conductor 240b can be formed at the same time. In this case, the conductor 112 has the same conductive material as the conductor 110. Note that the conductor 112 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 200.

[0324] 20B shows that the conductor 112 and the conductor 110 have a single-layer structure, but the present invention is not limited to this. For example, the conductor 112 and the conductor 110 may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0325] The insulator 132 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer. Further, for example, the insulator 132 can be formed using an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0326] Furthermore, for example, it is preferable to use a layered structure of an insulator containing a material with high dielectric strength (a material with a low dielectric constant) and an insulator containing a material with a high dielectric constant (high-k) for the insulator 132. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator containing a high-k material, and the capacitor 100 can improve its dielectric strength by having an insulator containing a material with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitor 100.

[0327] An insulator 150 is provided over the conductor 120 and the insulator 132. The insulator 150 functions as an interlayer film.

[0328] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0329] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select the material depending on the function of the insulator.

[0330] For example, the insulator 150 preferably includes the above-described material having a low dielectric constant. Alternatively, the insulator 150 preferably has a layered structure of an insulator containing the above-described inorganic insulating material and an insulator containing the above-described resin. Because silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can provide a thermally stable layered structure having a low dielectric constant.

[0331] 20A and 20B, the shape of the capacitor element 100 is planar, but the present invention is not limited to this. For example, the shape of the capacitor element 100 may be cylindrical, as shown in Fig. 21. The configuration below the insulator 150 of the semiconductor device shown in Fig. 21 is the same as that of the semiconductor device shown in Fig. 20A and 20B.

[0332] 21, an insulator 150 is disposed on an insulator 132, and an insulator 142 is disposed on the insulator 150. An opening 168 reaching the conductor 110 is formed in the insulators 132, 150, and 142.

[0333] 21 includes a conductor 115, an insulator 145 on the conductor 115 and the insulator 142, and a conductor 125 on the insulator 145. Here, at least a portion of each of the conductor 115, the insulator 145, and the conductor 125 is disposed inside the opening 168.

[0334] An insulator 151 is disposed on the conductor 125 and the insulator 145, an insulator 154 is disposed on the insulator 151, and a conductor 153 and an insulator 156 are disposed on the insulator 154. Furthermore, a conductor 140 is provided inside openings formed in the insulators 132, 150, 142, 145, 151, and 154.

[0335] The conductor 115 functions as a first electrode of the capacitor 100, the conductor 125 functions as a second electrode of the capacitor 100, and the insulator 145 functions as a dielectric of the capacitor 100. The capacitor 100 has a configuration in which the first electrode and the second electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface inside the opening 168, which allows for a larger capacitance per unit area. Therefore, the deeper the opening 168, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0336] The insulator 151 may be an insulator that can be used for the insulator 150. The insulator 142 may be an insulator that can be used for the insulator 282.

[0337] The shape of the opening 168 as viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area where the opening 168 and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0338] The conductor 115 is disposed in contact with the side surfaces of the insulator 150 and the insulator 142 in the opening 168. The upper surface of the conductor 115 is preferably at the same height as the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening 168. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0339] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. The insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 can be formed using any of the insulators that can be used for the insulator 132.

[0340] The conductor 125 is disposed so as to fill the opening 168. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0341] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be a conductor that can be used for the conductor 112. The insulator 156 may be an insulator that can be used for the insulator 150. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100 or the transistor 200.

[0342] 21 shows a configuration in which the cylindrical lower electrode of the capacitor 100 is electrically connected to the other of the source electrode and the drain electrode of the transistor 200 through the conductor 240b, but the present invention is not limited to this. For example, as shown in FIG. 22, the cylindrical lower electrode of the capacitor may be in contact with the other of the source electrode and the drain electrode of the transistor 200.

[0343] 22 shows a semiconductor device having the above-described transistor 200 and a cylindrical capacitor element 100. In FIG. 22, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions. Hereinafter, differences from the semiconductor device shown in FIG. 21 will be mainly described, and descriptions of overlapping parts will be omitted.

[0344] An insulator 284 is provided over the insulator 285. The insulator 284 may be any insulator that can be used for the insulator 216.

[0345] The capacitor 100 includes a conductor 153 over the conductor 242b, an insulator 154 over the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) over the insulator 154.

[0346] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the openings formed in the insulators 271b, 275, 280, 282, 283, and 285, respectively. The ends of the conductors 153, 154, and 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is provided so as to cover the end of the conductor 153. This allows the conductors 153 and 160 to be electrically insulated from each other.

[0347] The conductor 153 has a region that functions as a first electrode (lower electrode) of the capacitor 100. The insulator 154 has a region that functions as a dielectric of the capacitor 100. The conductor 160 has a region that functions as a second electrode (upper electrode) of the capacitor 100. The capacitor 100 forms a metal-insulator-metal (MIM) capacitor.

[0348] The conductor 242 b provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 100 .

[0349] The conductor 153 and the conductor 160 included in the capacitor 100 can be formed using a conductor that can be used for the conductor 205, the conductor 242a, the conductor 242b, or the conductor 260. The conductor 153 and the conductor 160 are preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductor 153 can be formed using titanium nitride or tantalum nitride formed using an ALD method or a CVD method.

[0350] The upper surface of the conductor 242b contacts the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0351] Alternatively, the conductor 160a may be made of titanium nitride formed by ALD or CVD, and the conductor 160b may be made of tungsten formed by CVD. Note that if the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten formed by CVD.

[0352] A material with a high dielectric constant (high-k) is preferably used for the insulator 154 of the capacitor 100. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0353] Furthermore, it is preferable to use a laminated structure of a material with a high dielectric constant (high-k) and a material with high dielectric strength as the insulator 154. For example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used as the insulator 154. Alternatively, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Alternatively, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By using a laminated structure of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0354] Furthermore, the insulator 154 may be made of a material that can have ferroelectricity, which will be described later.

[0355] The deeper the depth of the openings formed in the insulators 271b, 275, 280, 282, 283, and 285 (that is, the thicker the thickness of one or more of the insulators 271b, 275, 280, 282, 283, and 285), the larger the capacitance of the capacitor 100. Increasing the capacitance per unit area of ​​the capacitor 100 allows for miniaturization or high integration of semiconductor devices.

[0356] Here, since the insulators 271b, 275, 282, and 283 function as barrier insulators, it is preferable to set their thicknesses according to the barrier properties required for the semiconductor device. Furthermore, since the thickness of the insulator 280 determines the thickness of the conductor 260 that functions as a gate electrode, it is preferable to set the thickness of the insulator 280 according to the thickness of the conductor 260 required for the semiconductor device.

[0357] Therefore, it is preferable to set the capacitance of the capacitor 100 by adjusting the film thickness of the insulator 285. For example, the film thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm. Forming the capacitor 100 in such a range allows the capacitor 100 to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple layers including the capacitor 100 are stacked. Note that the capacitance of the capacitor may be different for each of the multiple layers. In this configuration, for example, the film thickness of the insulator 285 provided in each layer may be different.

[0358] In the opening provided in the insulator 285 or the like in which the capacitor 100 is disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening can be improved, and defects such as voids can be reduced.

[0359] The conductor 240 is provided inside openings formed in the insulators 216, 222, 275, 280, 282, 283, 285, and 284. The conductor 240 is provided in contact with one of the source electrode and drain electrode (conductor 242a) of the transistor 200. The conductor 240 is provided extending in the Z direction.

[0360] Furthermore, the conductor 242a provided on the oxide 230 has a region that functions as wiring electrically connected to the conductor 240. For example, in FIG. 22, the upper surface and side end of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. Since the conductor 240 directly contacts at least one of the upper surface and side end of the conductor 242a, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the semiconductor device. It is preferable that the conductor 240 contacts a portion of the upper surface and the side end of the conductor 242a. By having the conductor 240 contact multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced.

[0361] The conductor 240 preferably has a layered structure of a first conductor and a second conductor. For example, as shown in FIG. 22 , the conductor 240 can have a structure in which the first conductor is provided in contact with the inner wall of the opening, and the second conductor is provided further inside. That is, the first conductor is disposed closer to the insulators 216, 222, 275, 280, 282, 283, 285, and 284 than the second conductor. The first conductor also contacts the top surface and side end of the conductor 242a.

[0362] The first conductor of conductor 240 may be a conductive material that can be used as the first conductor of conductor 240a or conductor 240b described above, and the second conductor of conductor 240 may be a conductive material that can be used as the second conductor of conductor 240a or conductor 240b described above.

[0363] For example, it is preferable to use titanium nitride as the first conductor of the conductor 240 and tungsten as the second conductor of the conductor 240. In this case, the first conductor of the conductor 240 includes titanium and nitrogen, and the second conductor of the conductor 240 includes tungsten.

[0364] The conductor 240 may have a single layer structure or a laminated structure of three or more layers.

[0365] 22 , the insulator 241 is preferably provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings provided in the insulators 216, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a, which are formed to protrude into the openings. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the interior of the opening via the insulator 241.

[0366] 22, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has an area that contacts the side surface of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from being mixed into the oxide 230 through the conductor 240.

[0367] The insulator 241 may be a barrier insulator that can be used for the above-described insulators 241a and 241b.

[0368] 22 shows the structure in which the insulator 241 is a single layer, the present invention is not limited to this. The insulator 241 may have a stacked structure of two or more layers.

[0369] When the insulator 241 has a two-layer stacked structure, a first layer in contact with the inner wall of the opening of the insulator 280 or the like may be a barrier insulating film against oxygen, and a second layer inside the first layer may be a barrier insulating film against hydrogen. For example, the first layer may be made of aluminum oxide deposited by the ALD method, and the second layer may be made of silicon nitride deposited by the PEALD method. This structure can prevent the conductor 240 from being oxidized and can also reduce the amount of hydrogen that enters the oxide 230 or the like from the conductor 240. This can improve the electrical characteristics and reliability of the transistor 200.

[0370] In the opening where the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, coverage of the insulator 241 and the like provided in the opening is improved.

[0371] A semiconductor device having a transistor 200 and a capacitor 100, in which one of the source and drain of the transistor 200 is electrically connected to one of a pair of electrodes of the capacitor 100, can function as, for example, a memory cell of a memory device.

[0372] 23A and 23B show a semiconductor device including the above-described transistor 200 and capacitor 100A. Fig. 23A is a top view of the semiconductor device. Fig. 23B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 23A and is also a cross-sectional view of the transistor 200 in the channel length direction. Note that some elements are omitted from the top view in Fig. 23A for clarity.

[0373] 23A and 23B , a capacitor 100A and a conductor 246 are disposed over a transistor 200. The conductor 246 functions as a wiring. Here, it is preferable that the overlapping area between the capacitor 100A and the transistor 200 is large when viewed from above. With this structure, the area occupied by a semiconductor device including the capacitor 100A and the transistor 200 can be reduced. This allows miniaturization or high integration of the semiconductor device to be achieved.

[0374] 23A and 23B has the same configuration below the insulator 285 as the semiconductor device shown in Figures 20A and 20B. Hereinafter, differences from the semiconductor device shown in Figures 20A and 20B will be mainly described, and descriptions of overlapping parts will be omitted.

[0375] The semiconductor device shown in FIGS. 23A and 23B has an insulator 287 on an insulator 285 .

[0376] The conductor 240a is provided inside openings formed in the insulators 287, 285, 283, 282, 280, 275, and 271a, and the conductor 240b is provided inside openings formed in the insulators 287, 285, 283, 282, 280, 275, and 271b. As shown in Figure 23B, the conductor 240a has a region in contact with the conductor 242a and a region in contact with at least a portion of the lower surface of the conductor 246. The conductor 240b has a region in contact with the conductor 242b and a region in contact with at least a portion of the lower surface of the conductor 110 of the capacitor 100A.

[0377] The conductor 246 may be disposed in contact with the upper surface of the conductor 240a. The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 246 may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor 246 is preferably formed in the same layer and made of the same material as the conductor 110.

[0378] <Capacitor 100A> The capacitor 100A includes a conductor 110, a conductor 120, and an insulator 130 sandwiched between the conductors 110 and 120. For example, the conductor 110 is disposed over the insulator 287 and the conductor 240b, the insulator 130 is disposed over the conductor 110, and the conductor 120 is disposed over the insulator 130. Here, the conductor 110 functions as a first electrode of the capacitor 100A, the conductor 120 functions as a second electrode of the capacitor 100A, and the insulator 130 functions as a dielectric of the capacitor 100A. Note that, as will be described in detail later, the capacitor 100A is a capacitor using a material that can have ferroelectricity as a dielectric.

[0379] The conductor 110 may be a conductor that can be used for the conductor 110 of the capacitor 100. The conductor 120 may be an insulator that can be used for the conductor 120 of the capacitor 100.

[0380] The conductor 110 may have a single layer structure or a multilayer structure. The conductor 110 may be any conductor that can be used for the conductor 110 of the capacitor element 100 described above.

[0381] In FIG. 23B, the conductor 120 has a layered structure of a conductor 120a and a conductor 120b provided on and in contact with the conductor 120a.

[0382] The conductor 120a may be formed by depositing a conductor applicable to the above-described conductor 120 using a sputtering method, an ALD method, a CVD method, or the like. The conductor 120a may be formed by depositing titanium nitride using a sputtering method, for example.

[0383] Alternatively, the conductor 120a may be formed by depositing titanium nitride using, for example, a thermal ALD method. Here, the deposition of the conductor 120a is preferably performed using a method in which the substrate is heated, such as the thermal ALD method. For example, the deposition may be performed by setting the substrate temperature to room temperature or higher, preferably 300°C or higher, more preferably 325°C or higher, and even more preferably 350°C or higher. Alternatively, the deposition may be performed by setting the substrate temperature to 500°C or lower, preferably 450°C or lower. For example, the substrate temperature may be set to about 400°C.

[0384] By forming the conductor 120a within the temperature range described above, it is possible to impart ferroelectricity to the insulator 130 without performing a high-temperature bake treatment (e.g., a bake treatment at a heat treatment temperature of 400°C or higher or 500°C or higher) after the formation of the conductor 120a. Furthermore, by forming the conductor 120a using the ALD method, which causes relatively little damage to the base, as described above, it is possible to prevent excessive destruction of the crystalline structure of the insulator 130, thereby enhancing the ferroelectricity of the insulator 130. Note that improving the crystallinity or ferroelectricity of the insulator 130 by utilizing the temperature during the formation of the conductor 120, without performing annealing after the formation of the conductor 120a, is sometimes referred to as self-annealing.

[0385] The conductor 120b may be formed by depositing a conductor applicable to the above-described conductor 120 by a sputtering method, an ALD method, a CVD method, or the like. For example, a tungsten film may be formed by a sputtering method.

[0386] The conductor 120 is not limited to the above, and may have a single layer structure or a structure of three or more layers.

[0387] It is preferable that the insulator 130 be made of a material that can have ferroelectricity. Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 may be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0388] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al １−ａ Sc ａ N ｂ(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1.)), metal nitrides such as Al-Ga-Sc nitride and Ga-Sc nitride are examples of materials that can have ferroelectricity. Examples of materials that can have ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, element M2 is one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. The element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

[0389] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0390] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0391] Furthermore, the material capable of exhibiting ferroelectricity may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulator 130 may have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0392] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material capable of exhibiting ferroelectricity, since it can be processed into a thin film of a few nanometers and still retain ferroelectricity. The film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. For example, the film thickness is preferably 5 nm to 15 nm, and more preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100A can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that, in this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.

[0393] Furthermore, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable because it can have ferroelectricity even in a small area. For example, when the area (occupied area) of the ferroelectric layer in a top view is 10,000 μm ２ Below, 1000 μm ２ Below, 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２The ferroelectric layer can have ferroelectricity even if the thickness is less than 100 nm. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100A can be reduced.

[0394] Ferroelectric materials are insulators that exhibit polarization when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses such a material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain terminals of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, the capacitance element 100A described in this embodiment is a ferroelectric capacitor, and a semiconductor device including the capacitance element 100A and the above-described transistor 200 can function as a ferroelectric memory.

[0395] Ferroelectricity is believed to be manifested by the displacement of oxygen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulator 130 to manifest ferroelectricity, the insulator 130 must contain crystals. In particular, the insulator 130 preferably contains crystals having an orthorhombic crystal structure, since this manifests ferroelectricity. The crystal structure of the crystals contained in the insulator 130 may be one or more selected from the group consisting of tetragonal, orthorhombic, and monoclinic. The insulator 130 may also have an amorphous structure. In this case, the insulator 130 may have a composite structure having an amorphous structure and a crystalline structure.

[0396] To form the insulator 130 containing crystals, it is preferable that impurities such as hydrogen or chlorine are reduced in the insulator 130. Here, the impurities do not only refer to single atoms. It is preferable that substances bonded to the above-mentioned impurities are also reduced in the insulator 130. For example, it is preferable that substances bonded to hydrogen (e.g., OH − It is also preferable that impurities such as hydrogen and chlorine are reduced. These impurities may form oxygen vacancies in the crystals of the insulator 130. Furthermore, impurities such as hydrogen may bond to the oxygen vacancies, which may reduce the crystallinity of the insulator 130. Therefore, the presence of these impurities in the insulator 130 may inhibit the crystallization of the insulator 130. Therefore, to improve the ferroelectricity of the insulator 130, it is preferable to reduce impurities such as hydrogen and chlorine.

[0397] 23B , it is preferable to provide an insulator 152 to cover the capacitor 100A and to provide an insulator 155 between the insulator 152 and the insulator 130. In this case, it is preferable that the insulator 155 be in contact with the insulator 287 in a region that does not overlap with the conductor 110.

[0398] The insulators 152 and 155 function as a barrier insulator against hydrogen. The insulator 152 is a barrier insulator against hydrogen and substances to which hydrogen is bonded (e.g., OH − Therefore, the insulator 152 has a function of suppressing the diffusion of at least one of hydrogen and substances to which hydrogen is bonded (for example, OH − The insulator 155 preferably has a high ability to suppress the diffusion of at least one of hydrogen and a substance to which hydrogen is bonded. The insulator 155 also has a function of capturing or fixing at least one of hydrogen and a substance to which hydrogen is bonded. Therefore, the insulator 155 preferably has a higher ability to capture or fix at least one of hydrogen and a substance to which hydrogen is bonded than the insulator 130.

[0399] The insulator 152 and the insulator 155 can be formed using, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide. As the insulator 152, which has a high ability to suppress diffusion of impurities such as hydrogen, it is preferable to use, for example, silicon nitride. In this case, the insulator 152 contains at least nitrogen and silicon.

[0400] Furthermore, it is preferable to use an oxide having an amorphous structure as the insulator 155, which has a high ability to capture or fix impurities such as hydrogen. For example, it is preferable to use a metal oxide such as aluminum oxide or magnesium oxide. When aluminum oxide is used for the insulator 155, the insulator 155 contains at least oxygen and aluminum. As described above, a metal oxide having an amorphous structure may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the capacitor 100A or providing it around the capacitor 100A, hydrogen contained in the capacitor 100A or hydrogen present around the capacitor 100A can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the insulator 130.

[0401] Note that the insulator 155 preferably has an amorphous structure, but may have a crystalline region formed in part thereof. Alternatively, the insulator 155 may have a multilayer structure in which a layer having an amorphous structure and a layer having a crystalline region are stacked. For example, the insulator 155 may have a stacked structure in which a layer having a crystalline region, typically a layer having a polycrystalline structure, is formed on a layer having an amorphous structure.

[0402] The insulator 152 can prevent impurities such as hydrogen from diffusing from the outside of the insulator 152 into the insulator 130. Furthermore, the insulator 155 can capture or fix impurities such as hydrogen present inside the region surrounded by the insulator 152, thereby reducing the concentration of impurities such as hydrogen contained in the insulator 130. In this way, by eliminating or extremely reducing impurities such as hydrogen in the insulator 130, the crystallinity of the insulator 130 can be improved, and a structure with high ferroelectricity can be obtained.

[0403] 23B, the insulator 155 has a layered structure of an insulator 155a and an insulator 155b provided on and in contact with the insulator 155a. The insulator 152 has a layered structure of an insulator 152a and an insulator 152b provided on and in contact with the insulator 152a. Note that the above is not limitative, and one or both of the insulator 155 and the insulator 152 may have a single-layer structure or a three-layer or more structure.

[0404] The insulator 155a is preferably formed by depositing an insulator applicable to the insulator 155 described above using an ALD method, particularly a thermal ALD method. For example, aluminum oxide deposited by an ALD method can be used as the insulator 155a. This allows the insulator 155a to be deposited with good coverage, so that even if a pinhole or a discontinuity is formed in the insulator 155b deposited by a sputtering method, diffusion of impurities from outside the insulator 155b to the insulator 130 through the pinhole or discontinuity can be suppressed.

[0405] The insulator 155b may be formed by sputtering using any of the insulators that can be used for the insulator 155. For example, aluminum oxide formed by sputtering can be used as the insulator 155b. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore the hydrogen concentration in the insulator 155b can be reduced. This allows more impurities, such as hydrogen, contained in the insulator 130 to be captured or fixed.

[0406] The insulator 152a may be formed by sputtering using any of the insulators that can be used for the insulator 152. For example, silicon nitride formed by sputtering can be used as the insulator 152a. Sputtering does not require the use of hydrogen-containing molecules in a deposition gas, and therefore the hydrogen concentration in the insulator 152a can be reduced.

[0407] The insulator 152b is preferably formed by depositing the above-described insulator that can be used for the insulator 152 using an ALD method, particularly a PEALD method. For example, silicon nitride deposited by a PEALD method can be used as the insulator 152b. As a result, even if pinholes or discontinuities are formed in the insulator 152a deposited by a sputtering method, the portions overlapping the pinholes or discontinuities can be sealed with silicon nitride deposited by an ALD method, which has good coverage. Furthermore, covering the pinholes or discontinuities with the insulator 152b can suppress diffusion of impurities from outside the insulator 152b into the insulator 130.

[0408] 23B , the insulator 155 and the insulator 152 are provided to cover not only the capacitor 100A but also the conductor 246. This can prevent impurities such as hydrogen from diffusing into the oxide 230 through the capacitor 100A, the conductor 246, and the conductor 240 during heat treatment. As described above, the manufacturing process of a high-purity intrinsic ferroelectric capacitor in which impurities such as hydrogen are reduced and a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen are reduced are highly compatible. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0409] The insulator 287 is preferably an insulator with a high ability to suppress the diffusion of impurities such as hydrogen, similar to the insulator 152. By configuring the insulator 155 and the insulator 287 to be in contact with each other in a region that does not overlap with the capacitor element 100A, the capacitor element 100A is sealed by the insulator 287, the insulator 155, and the insulator 152. This suppresses the diffusion of hydrogen from outside the insulators 152 and 287 to the capacitor element 100A, and further captures or fixes hydrogen inside the region surrounded by the insulators 152 and 287, thereby reducing the hydrogen concentration in the insulator 130 of the capacitor element 100A. This can improve the ferroelectricity of the insulator 130.

[0410] 23B shows a configuration in which the insulator 287 is in contact with the insulator 155 in a region that does not overlap with the conductor 110, but the present invention is not limited to this. A configuration in which the lower surface of the conductor 246, the lower surface of the insulator 155a, and the lower surface of the conductor 110 are in contact with the upper surface of the insulator 285 may be used without providing the insulator 287.

[0411] Furthermore, a layer for increasing the crystallinity of the insulator 130 may be provided between the insulator 130 and the conductor 110 and / or between the insulator 130 and the conductor 120. As the layer for increasing the crystallinity, for example, a layer containing at least one of the elements contained in the insulator 130 is preferably used. Note that it is preferable that the composition of the layer for increasing the crystallinity is different from the composition of the insulator 130. For example, when the insulator 130 is made of HfZrO Ｘ When using a layer that enhances crystallinity, it is preferable to use, specifically, a metal oxide such as hafnium oxide or zirconium oxide, or a metal such as hafnium or zirconium.

[0412] The composition of the layer that enhances crystallinity does not need to contain any of the elements contained in the insulator 130. In this case, elements that can be used include silicon, yttrium, aluminum, and scandium. By providing a layer that enhances crystallinity, the crystallinity of the insulator 130 can be improved, and the ferroelectricity of the insulator 130 can be enhanced. Since the ferroelectricity of the insulator 130 can be enhanced by improving the crystallinity of the insulator 130, the layer that enhances crystallinity can be rephrased as a layer that increases the remanent polarization of the insulator 130.

[0413] 23A and 23B has a configuration in which the side surfaces of the conductor 110, the insulator 130, and the conductor 120 are flush with each other, but the present invention is not limited to this. Below, modifications of the capacitor 100A shown in FIGS. 23A and 23B are described using FIGS. 24A to 25B. Hereinafter, differences from the semiconductor device shown in FIGS. 23A and 23B will be mainly described, and descriptions of overlapping portions will be omitted.

[0414] Fig. 24A is a top view of the semiconductor device. Fig. 24B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 24A, and is also a cross-sectional view in the channel length direction of the transistor 200. Note that some elements are omitted from the top view of Fig. 24A for clarity.

[0415] 24B , the side surface of the conductor 110 may be located inside the side surfaces of the insulator 130 and the conductor 120. The insulator 130 is formed to cover the upper surface and side surfaces of the conductor 110, and the area of ​​the insulator 130 that does not overlap with the conductor 110 contacts the insulator 287. In this case, when viewed from above, the outer periphery of the conductor 110 is located inside the outer peripheries of the insulator 130 and the conductor 120. With this configuration, the insulator 130 can sufficiently separate the conductors 110 and 120.

[0416] Furthermore, by increasing the area of ​​the conductor 120 when viewed from above, sufficient design margin can be ensured when providing a conductor (not shown) that connects to the conductor 120 and functions as a plug or wiring.

[0417] 23B shows a configuration in which the conductor 110 is a single layer, but the present invention is not limited to this, and the conductor 110 may have a laminated structure of two or more layers. For example, as shown in FIG. 24B , the conductor 110 may have a two-layer laminated structure of a conductor 110a and a conductor 110b on the conductor 110a.

[0418] The conductor 110a may be formed by depositing a conductor applicable to the above-described conductor 110 by a sputtering method, an ALD method, a CVD method, or the like. For example, a tungsten film may be formed by a sputtering method or a CVD method.

[0419] The conductor 110b, which is in contact with at least a portion of the lower surface of the insulator 130, may be formed by depositing a conductor applicable to the conductor 110 described above using an ALD method, a CVD method, or the like. For example, a titanium nitride film may be formed using a thermal ALD method. Furthermore, it is preferable that the upper surface of the conductor 110b has good flatness. By improving the flatness of the upper surface of the conductor 110b, the crystallinity of the insulator 130 can be improved, and the ferroelectricity of the insulator 130 can be enhanced.

[0420] Fig. 25A is a top view of the semiconductor device. Fig. 25B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 25A, and is also a cross-sectional view in the channel length direction of the transistor 200. Note that some elements are omitted from the top view of Fig. 25A for clarity.

[0421] As shown in Figures 25A and 25B, an insulator 286 may be provided instead of the insulator 287 shown in Figure 23B, and a conductor 110 may be provided so as to fill the inside of the openings formed in the insulator 286 and the insulator 285.

[0422] The insulator 286 may be made of any of the insulating materials that can be used for the insulator 285 described above.

[0423] The conductor 110 is buried inside the openings formed in the insulators 286 and 285. The conductor 110 has a region in contact with the conductor 240b inside the openings formed in the insulators 286 and 285. By burying the conductor 110 inside the openings formed in the insulators 286 and 285, the conductor 110 and the conductor 120 can be sufficiently separated from each other. Therefore, the leakage current of the capacitor 100A can be suppressed.

[0424] Furthermore, the conductor 110 shown in FIG. 25B can be formed by forming openings in the insulators 286 and 285, depositing a conductive film to become the conductor 110, and performing planarization using a chemical mechanical polishing (CMP) method or the like until the insulator 286 is exposed. That is, the conductor 110 shown in FIG. 25B can be formed using a single damascene method. The formation process of such a conductor 110 also serves as a process for improving the planarity of the upper surface of the conductor 110. Therefore, since the insulator 130 is provided on the conductor 110 with good planarity, the planarity of the insulator 130 can also be improved. Therefore, even when the insulator 130 is formed using a thin ferroelectric layer, the leakage current of the capacitor element 100A can be suppressed. Furthermore, since the upper surface of the insulator 286 also has good planarity, this formation process of the conductor 110 is also suitable for the case where part of the insulator 130 is provided on the insulator 286.

[0425] 25B, the conductor 110 may have a layered structure of a conductor 110c, a conductor 110a on the conductor 110c, and a conductor 110b on the conductor 110a. The conductor 110c is provided inside an opening formed in the insulators 286 and 285, in contact with the side surface of the insulator 286, the side surface of the insulator 285, the top surface of the insulator 283, the side surface of the insulator 241b, and the top surface of the conductor 240b. The conductor 110a is provided so as to fill a portion of the recess formed in the conductor 110c. Here, the top surface of the conductor 110a is lower than the top surface of the conductor 110c and the top surface of the insulator 286. The conductor 110b is provided in contact with the top surface of the conductor 110a and the side surface of the conductor 110c. Here, the upper surface of the conductor 110b is flush with the upper surfaces of the conductor 110c and the insulator 286. In other words, the conductor 110a is surrounded by the conductors 110c and 110b.

[0426] When the conductor 110 has a three-layer structure of the conductor 110c, the conductor 110a, and the conductor 110b, the conductor 110 can be formed, for example, by forming an opening in the insulator 286 and the insulator 285, depositing a conductive film that will become the conductor 110c and a conductive film that will become the conductor 110a, performing a CMP process to expose the insulator 286 to form the conductor 110c and the conductor 110a, etching back a portion of the conductor 110a, and burying the conductor 110b.

[0427] The conductor 110c may be formed by depositing a conductor applicable to the above-described conductor 205a using a sputtering method, an ALD method, a CVD method, or the like. By using a conductive material that has a function of suppressing oxygen diffusion for the conductor 110c, it is possible to suppress a decrease in the conductivity of the conductor 110a due to oxidation. For example, the conductor 110c may be formed by depositing titanium nitride using a CVD method.

[0428] The conductor 110b may be formed by depositing a conductor applicable to the conductor 110 described above using an ALD method, a CVD method, or the like. When the conductor 110c is formed by performing a planarization process as described above, the conductor 110c may be formed by a sputtering method, a CVD method, or a PECVD method, which have a high deposition rate. This allows for high productivity in manufacturing semiconductor devices. For example, the conductor 110b may be formed by depositing titanium nitride using a CVD method.

[0429] In FIG. 25B , the side surface of the conductor 110 is located inside the side surface of the insulator 130. In this case, when viewed from above, the outer periphery of the conductor 110 is located inside the outer peripheries of the insulator 130 and the conductor 120. For example, the shortest distance from the side surface of the conductor 110 to the side surface of the insulator 130 is preferably equal to or greater than the film thickness of the insulator 130, and more preferably equal to or greater than twice the film thickness of the insulator 130. With this configuration, the insulator 130 can sufficiently separate the conductors 110 and 120. At this time, as shown in FIG. 25B , a portion of the region of the insulator 286 that does not overlap with the conductor 120 may be removed.

[0430] While FIG. 25B shows a configuration in which the side of the conductor 110 is located inside the side of the insulator 130, the present invention is not limited to this. For example, the side of the conductor 110 may be located outside the side of the insulator 130. With this configuration, the insulator 130 is surrounded by the conductor 110c, the insulator 155, and the insulator 152. By using a conductive material for the conductor 110c that has the function of reducing hydrogen diffusion, the diffusion of hydrogen from the outside of the insulator 152 and the conductor 110c to the insulator 130 is suppressed, and the hydrogen in the insulator 130 is captured or fixed, thereby reducing the hydrogen concentration in the insulator 130. This improves the ferroelectricity of the insulator 130. Note that the side of the conductor 110 may coincide with the side of the insulator 130.

[0431] The conductor 246 has a region in contact with the conductor 240a inside the openings formed in the insulator 286 and the insulator 285. The conductor 246 functions as a wiring or a terminal. The conductor 246 is preferably configured to be formed in the same layer and made of the same material as the conductor 110. As shown in FIG. 25B , when the conductor 110 has the above-described three-layer stacked structure, the conductor 246 and the conductor 110 are formed in the same layer and made of the same material, so that the conductor 246 has a three-layer stacked structure.

[0432] 25B shows the conductor 120 as having a single layer structure. The conductor 120 may have a two-layer stacked structure as shown in FIG. 23B, or a three-layer or more stacked structure. When the conductor 120 has a single layer structure, the conductor 120 may be made of a conductor that can be used for the conductor 120a or 120b described above. The conductor 120 may be formed using a method that can be used for the conductor 120a or 120b described above.

[0433] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0434] Embodiment 2 In this embodiment, a memory device which is one mode of a semiconductor device will be described with reference to FIGS. 26 and 27. FIG.

[0435] 26 illustrates an example of a memory device according to one embodiment of the present invention. In the memory device according to one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0436] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0437] 26 , a wiring 1001 is electrically connected to the source of the transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The other of the source and drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0438] Moreover, the memory device shown in FIG. 26 can be arranged in a matrix to form a memory cell array.

[0439] The capacitor 100 described in the previous embodiment can be used as the capacitor 100. Note that the capacitor 100A described in the previous embodiment may be used as the capacitor 100. When the capacitor 100A is used as the capacitor 100, the storage device shown in FIG. 26 has a ferroelectric memory.

[0440] The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region and a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0441] Here, in the transistor 300 shown in FIG. 26 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0442] Note that the transistor 300 illustrated in FIG. 26 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0443] <Wiring Layer> A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be collectively assigned the same reference symbol to multiple structures. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a portion of the conductor may function as the wiring, and a portion of the conductor may function as the plug.

[0444] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328 is embedded in the insulators 320 and 322, and a conductor 330 is embedded in the insulators 324 and 326. The conductors 328 and 330 function as plugs or wirings.

[0445] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0446] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 26, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0447] Similarly, a conductor 218 and a conductor (conductor 205) that constitutes the transistor 200 are embedded in the insulators 210, 215, and 216. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the transistor 300.

[0448] Here, similar to the insulators 241a and 241b described in the previous embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218. The insulator 217 is provided in contact with the inner walls of the openings formed in the insulators 210, 215, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 215, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0449] The insulator 217 may be, for example, an insulator that can be used for the insulators 241a and 241b described above. Because the insulator 217 is provided in contact with the insulators 215 and 222, it can prevent impurities such as water or hydrogen contained in the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0450] The insulator 217 can be formed by a method similar to that of the insulators 241a and 241b. For example, a silicon nitride film may be formed by a PEALD method, and an opening reaching the conductor 356 may be formed by anisotropic etching.

[0451] The insulators 210, 352, and 354, which function as interlayer films, can be formed using the same insulators that can be used for the insulator 150.

[0452] Furthermore, when a transistor including an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulator 215, the insulator 350, and the like may be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0453] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0454] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0455] For example, the conductors 328, 330, 356, conductor 218, and 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, they are preferably formed using a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

[0456] <Wiring or Plug in Layer Including Oxide Semiconductor> As described in the above embodiment, the transistor 200 may be sealed with the insulators 215 and 283. With such a structure, hydrogen contained in the insulators 274, 150, and the like can be prevented from entering the insulator 280 and the like.

[0457] 26 , the insulator 240 penetrates the insulator 283, and the conductor 218 penetrates the insulator 215. However, as shown in FIG. 26 , the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. By using a barrier insulator against hydrogen as the insulators 241 and 217, it is possible to prevent hydrogen from being mixed into the inside of the insulators 215 and 283 through the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 215, 283, 241, and 217, and it is possible to prevent impurities such as hydrogen contained in the insulator 274, etc. from being mixed in from the outside.

[0458] <Dicing Lines> The following describes dicing lines (which may also be referred to as scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, there is a case where grooves (dicing lines) for dividing the semiconductor elements are first formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0459] 26, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216 so that the region where the insulator 283 and the insulator 215 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 275, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0460] That is, the insulator 215 and the insulator 283 are in contact with each other through openings provided in the insulators 282 , 280 , 275 , 222 , and 216 .

[0461] Furthermore, for example, openings may be provided in the insulators 282, 280, 275, 222, 216, and the upper layer of the insulator 215. With this configuration, the insulators 215 and 283 are in contact with each other through the openings provided in the insulators 282, 280, 275, 222, and 216. In this case, the lower layer of the insulator 215 and the insulator 283 may be formed using the same material and the same method. By providing the lower layer of the insulator 215 and the insulator 283 using the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.

[0462] With this structure, the transistor 200 can be enclosed by the insulator 215 and the insulator 283. At least one of the insulator 215 and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200.

[0463] Furthermore, this structure can prevent oxygen from the insulator 280 from diffusing to the outside. Therefore, the oxygen from the insulator 280 is efficiently supplied to the channel formation region of the transistor 200. The oxygen can reduce oxygen vacancies in the channel formation region of the transistor 200. As a result, the oxide semiconductor including the channel formation region of the transistor 200 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0464] [Storage Device 2] An example of a configuration different from that of the storage device shown in Fig. 26 is shown in Fig. 27. Note that in the storage devices shown below, structures having the same functions as those constituting the storage devices described above are given the same reference numerals. In the following, differences from the storage device described above will be mainly described, and overlapping portions will not be described.

[0465] 27 is a cross-sectional view of a memory device. The memory device illustrated in FIG. 27 differs from the memory device illustrated in FIG. 26 in that the wiring 1007 is not included and the gate of the transistor 300 is electrically connected to the other of the source and drain of the transistor 200 and one electrode of the capacitor 100.

[0466] 27 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0467] The conductor 316 is electrically connected to the capacitor 100 or the transistor 200 through the conductor 328 , the conductor 330 , the conductor 356 , the conductor 218 , and the conductor 240 .

[0468] The memory device described in this embodiment can form a memory cell array by arranging memory cells in a matrix on the xy plane, similar to the plurality of transistors 200 shown in FIG. 19A . The memory device described in this embodiment can also have a stacked memory cell array. Stacking a plurality of memory cell arrays allows memory cells to be integrated and arranged without increasing the area occupied by the memory cell array. That is, a 3D cell array can be formed.

[0469] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0470] 28A to 31C , a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely small, the OS memory device has excellent storage characteristics and can function as a nonvolatile memory.

[0471] 28A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0472] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to access.

[0473] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside as power supply voltages. Control signals (CE, WEN, RES), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0474] The control logic circuit 1460 processes control signals (CE, WEN, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WEN is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0475] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0476] 28A illustrates an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited to this. For example, as shown in FIG. 28B , the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap below the memory cell array 1470. OS transistors can be formed during a back-end-of-line (BEOL) process in which wiring of a memory device is formed. Therefore, when OS transistors are used for the memory cell array 1470 and Si transistors are used for the peripheral circuit 1411 overlapping below the memory cell array 1470, a technique for forming OS transistors directly above Si transistors (referred to as a BEOL-Tr technique) can be applied.

[0477] Furthermore, a configuration in which a plurality of memory cell arrays 1470 are stacked may be used. Stacking a plurality of memory cell arrays 1470 allows memory cells to be integrated and arranged without increasing the area occupied by the memory cell array 1470. That is, a 3D cell array can be configured. In this manner, a semiconductor device with a large memory capacity can be provided by achieving high integration of memory cells. Note that a layer including an OS transistor is preferable because it can be stacked monolithically.

[0478] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

[0479] 29A to 29I and 31A, examples of the configuration of a memory cell that can be applied to the above-described memory cell MC will be described.

[0480] 29A to 29C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 29A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a top gate) and a back gate.

[0481] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitor CA is connected to a wiring LL.

[0482] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, the wiring LL may be at ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0483] 29A corresponds to the memory device shown in FIG 26. That is, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0484] Furthermore, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 29B. Furthermore, for example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 29C.

[0485] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0486] Furthermore, in the DOSRAM, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cell array 1470 as described above, which reduces the bit line capacitance and the storage capacitance of the memory cells.

[0487] 29D to 29G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 29D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0488] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0489] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. When writing and reading data, a high-level potential is preferably applied to the wiring CAL. Furthermore, when retaining data, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0490] 29D corresponds to the memory device shown in Fig. 27. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0491] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 29E. Furthermore, for example, the memory cell MC may be configured as a single-gate transistor, i.e., a memory cell configured with a transistor M2 that does not have a back gate, as in the memory cell 1476 shown in FIG. 29F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 29G.

[0492] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very small. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0493] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0494] In addition, the transistor M3 may be an OS transistor. When the transistors M2 and M3 are OS transistors, the memory cell array 1470 can be configured using only n-channel transistors.

[0495] 29H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 29H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0496] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0497] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-channel transistors.

[0498] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0499] 29I shows an example of a two-transistor gain cell memory cell. The memory cell 1479 shown in FIG. 29I includes a transistor M7 and a transistor M8. The memory cell 1479 is electrically connected to a wiring BIL, a wiring WWL, a wiring BGL, and a wiring SL.

[0500] The transistor M7 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M7 may be electrically connected to each other. Alternatively, the transistor M7 does not necessarily have a back gate.

[0501] 29I, the gate capacitance of transistor M8 is used as a storage capacitance. That is, memory cell 1479 can also be considered a capacitor-less memory cell. Memory cell 1479 can also be considered a configuration in which memory cell 1477 shown in FIG. 29G does not have capacitance element CB, and can also be considered a two-transistor, zero-capacitance gain cell type memory cell.

[0502] By using an OS transistor as the transistor M7, when the transistor M7 is turned off, charge at a node where one of the source electrode or the drain electrode of the transistor M7 is electrically connected to the gate electrode of the transistor M8 can be held for an extremely long time, thereby realizing a nonvolatile memory cell.

[0503] The transistor M8 may be an n-channel Si transistor or a p-channel Si transistor.

[0504] When the semiconductor device described in the above embodiment is used for the memory cell 1479, the transistor 200 can be used as the transistor M7 and the transistor 300 can be used as the transistor M8. By using an OS transistor as the transistor M7, the leakage current of the transistor M7 can be made extremely small.

[0505] Alternatively, the transistor M8 may be an OS transistor. In this case, the memory cell array 1470 can be configured using only n-channel transistors.

[0506] When the semiconductor device described in the above embodiment is used for the memory cell 1479, the transistor 200 can be used as the transistors M7 and M8. With this structure, the transistors M7 and M8 can be formed in the same layer. Therefore, compared to the case where the transistors M7 and M8 are provided in different layers, the manufacturing process for stacking layers including the memory cell 1479 can be simplified, and productivity can be improved.

[0507] When the transistor 200 is used as the transistor M7 and the transistor M8, the components of the transistor (including the channel length, channel width, cross-sectional shape, etc.) may be appropriately set according to the characteristics required for the transistor M7 and the transistor M8.

[0508] Regardless of the semiconductor material used for the transistor M8, the structure of the transistor M8 is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. The transistor M8 may have either a top-gate or bottom-gate structure. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0509] As described above, a configuration in which a plurality of memory cell arrays 1470 are stacked may be used. By stacking a plurality of memory cell arrays 1470, memory cells can be integrated and arranged without increasing the area occupied by the memory cell arrays 1470. In other words, a 3D cell array can be configured. An example of a memory device having a configuration in which a plurality of memory cell arrays 1470 are stacked is shown in FIG.

[0510] 30 includes a first layer including a transistor 300 and memory cell arrays 1470[1] to 1470[m] (only memory cell arrays 1470[1] and 1470[2] are shown in FIG. 30 ) on the first layer. Note that the structure below the insulator 326 of the memory device illustrated in FIG. 30 is similar to that of the memory device illustrated in FIG. 26 .

[0511] Each of the memory cell arrays 1470[1] to 1470[m] includes a plurality of memory cells MC. Each of the plurality of memory cells MC includes a transistor 200 and a capacitor 100. Here, the transistor 200 corresponds to the transistor 200 described in the above embodiment, and the capacitor 100 corresponds to the capacitor 100 or the capacitor 100A described in the above embodiment. Note that FIG. 30 illustrates an example in which the transistor 200 and the capacitor 100 shown in FIG. 22 are used as the transistor 200 and the capacitor 100.

[0512] A wiring layer including an interlayer film, wiring, plugs, and the like may be provided between the first layer and the memory cell array 1470, or between two memory cell arrays 1470. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of a conductor functions as a wiring, and cases where a part of a conductor functions as a plug.

[0513] An insulator 210 is provided above the insulator 326, and a conductor 209 is provided inside an opening formed in the insulator 210. Furthermore, an insulator 215 is provided on the insulator 210. A part of the conductor 240 provided in the memory cell array 1470[1] is buried in the opening formed in the insulator 215. Here, the insulator 210 can be an insulator that can be used for the insulator 216.

[0514] A conductor (not shown) is provided in contact with the lower surface of the conductor 209. The upper surface of the conductor 209 is provided in contact with the lower surface of the conductor 240 provided in the memory cell array 1470[1]. With this configuration, the conductor 240 functioning as the wiring BL can be electrically connected to circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes provided below the memory cell array 1470.

[0515] Each of the memory cell arrays 1470[1] to 1470[m] includes a plurality of memory cells MC. The conductor 240 included in each memory cell MC is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.

[0516] 30, adjacent memory cells MC share a conductor 240. In addition, in adjacent memory cells MC, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.

[0517] Here, the conductor 160 functioning as the upper electrode of the capacitor 100 in the lower layer (e.g., the layer of the memory cell array 1470[1]) and the conductor 261 functioning as the second gate electrode of the transistor 200 in the upper layer (e.g., the layer of the memory cell array 1470[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 100 in the lower layer and the conductor 261 of the transistor 200 in the upper layer can be formed so as to be embedded in openings formed in the same insulator 216. The conductor 160 of the capacitor 100 in the lower layer and the conductor 261 of the transistor 200 in the upper layer are formed by processing one conductive film, thereby achieving the above-described structure. In this case, the conductor 160 of the capacitor 100 in the lower layer has the same material as the conductor 261 of the transistor 200 in the upper layer.

[0518] As described above, by simultaneously forming the conductor 160 of the capacitor 100 in the lower layer and the conductor 261 of the transistor 200 in the upper layer, the manufacturing process of the memory device according to this embodiment can be reduced, and the productivity of the memory device can be improved.

[0519] In the memory cell array 1470 described above, a plurality of memory cell arrays (memory cell arrays 1470[1] to memory cell arrays 1470[m]) can be stacked. The memory cell arrays 1470[1] to 1470[m] included in the memory cell array 1470 are arranged in the vertical direction of the substrate surface, thereby improving the memory density of the memory cells. Furthermore, the memory cell array 1470 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The memory device shown in FIG. 30 can reduce the manufacturing cost of the memory cell array 1470.

[0520] [Ferroelectric Memory] Figure 31A shows an example of the circuit configuration of a memory cell using a ferroelectric capacitor. The memory cell 1480 has a transistor M9 and a capacitance element Cfe. Here, the semiconductor device having the transistor 200 and the capacitance element 100A shown in Figures 23A to 25B can be used as the memory cell 1480. In this case, the transistor M9 corresponds to the transistor 200, and the capacitance element Cfe corresponds to the capacitance element 100A. Note that the transistor M9 may or may not have a back gate.

[0521] The OS transistor described in the above embodiment is preferably used as the transistor M9. An OS transistor has a characteristic of high withstand voltage between the source and drain. That is, an OS transistor can be called a micro-high-voltage device. Therefore, by using an OS transistor as the transistor M9, a high voltage can be applied to the transistor M9 even when the transistor M9 is miniaturized. By miniaturizing the transistor M9, the area occupied by the semiconductor device can be reduced. Therefore, semiconductor devices can be arranged at high density. This allows a memory device with a large storage capacity to be realized.

[0522] One of the source and drain of the transistor M9 is electrically connected to the wiring BL. The other of the source and drain of the transistor M9 is electrically connected to one electrode of the capacitor Cfe. The gate of the transistor M9 is electrically connected to the wiring WL. The other electrode of the capacitor Cfe is electrically connected to the wiring PL.

[0523] The wiring WL functions as a word line, and the on / off state of the transistor M9 can be controlled by controlling the potential of the wiring WL. For example, the transistor M9 can be turned on by setting the potential of the wiring WL to a high potential (H), and the transistor M9 can be turned off by setting the potential of the wiring WL to a low potential (L). The wiring WL is electrically connected to a word line driver circuit included in the row circuit 1420, and the potential of the wiring WL can be controlled by the word line driver circuit.

[0524] The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to the potential of the wiring BL is supplied to one electrode of the capacitor Cfe. The wiring BL is electrically connected to a bit line driver circuit in the column circuit 1430. The bit line driver circuit has a function of generating data to be written to the memory cell MC. The bit line driver circuit also has a function of reading data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read using the sense amplifier.

[0525] The wiring PL functions as a plate line. A potential is supplied to the other electrode of the capacitor Cfe through the wiring PL.

[0526] The capacitor Cfe has a dielectric layer between two electrodes, which is made of a material that can have ferroelectricity. The material that can be used for the insulator 130 described above can be used as the ferroelectric material. By using a ferroelectric layer that can be thinned, a memory device can be combined with miniaturized transistors. Hereinafter, the dielectric layer of the capacitor Cfe will be referred to as the ferroelectric layer.

[0527] The ferroelectric layer of the capacitance element Cfe has a hysteresis characteristic. Fig. 31B is a graph showing an example of the hysteresis characteristic. In Fig. 31B, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe.

[0528] 31B, the vertical axis represents the polarization of the ferroelectric layer, and a positive value indicates that positive charges are biased toward one electrode of the capacitance element Cfe and negative charges are biased toward the other electrode of the capacitance element Cfe. On the other hand, a negative value indicates that positive charges are biased toward the other electrode of the capacitance element Cfe and negative charges are biased toward one electrode of the capacitance element Cfe.

[0529] The voltage shown on the horizontal axis of the graph in Fig. 31B may be the difference between the potential of the other electrode of the capacitance element Cfe and the potential of one electrode of the capacitance element Cfe. Also, the polarization shown on the vertical axis of the graph in Fig. 31B may be a positive value when positive charges are biased toward the other electrode of the capacitance element Cfe and negative charges are biased toward one electrode of the capacitance element Cfe, and a negative value when positive charges are biased toward one electrode of the capacitance element Cfe and negative charges are biased toward the other electrode of the capacitance element Cfe.

[0530] 31B, the hysteresis characteristic of the ferroelectric layer can be expressed by a curve 61 and a curve 62. The voltages at the intersections of the curve 61 and the curve 62 are defined as VSP and −VSP. It can be said that VSP and −VSP have opposite polarities.

[0531] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 61. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can each be referred to as a saturation polarization voltage. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Also, while FIG. 31B shows a case where the absolute values ​​of the first and second saturation polarization voltages are equal, the absolute values ​​of the two may be different.

[0532] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 61 and the polarization of the ferroelectric layer is 0. Furthermore, −Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 62 and the polarization of the ferroelectric layer is 0. Vc and Vc can be referred to as coercive voltages, respectively. The values ​​of Vc and Vc can be referred to as values ​​between −VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and −Vc may be referred to as the second coercive voltage. Although FIG. 31B shows that the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, their absolute values ​​may be different.

[0533] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "remanent polarization Pr" and the minimum value is called "remanent polarization -Pr". Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "remanent polarization 2Pr".

[0534] As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed by the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe. Also, as described above, the other electrode of the capacitance element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be controlled.

[0535] 31A , the voltage applied to the ferroelectric layer of the capacitance element Cfe is the difference (potential difference) between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode (wiring PL) of the capacitance element Cfe. Furthermore, the transistor M9 is an n-channel transistor.

[0536] 31C is a timing chart showing an example of a method for driving the memory cell 1480. FIG. 31C shows an example of writing and reading binary digital data to the memory cell 1480. Specifically, FIG. 31C shows an example in which data “1” is written to the memory cell 1480 from time T01 to time T02, read and rewrite are performed from time T03 to time T05, read and write data “0” to the memory cell 1480 from time T11 to time T13, read and rewrite are performed from time T14 to time T16, and read and write data “1” to the memory cell 1480 from time T17 to time T19.

[0537] A reference potential Vref is supplied to the sense amplifier electrically connected to the wiring BL. In the read operation shown in Figure 31C etc., when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0538] From time T01 to time T02, the potential of the wiring WL is set to a high potential. This turns on the transistor M9. Furthermore, the potential of the wiring BL is set to Vw. Since the transistor M9 is on, the potential of one electrode of the capacitor Cfe becomes Vw. Furthermore, the potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe becomes "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T01 to time T02 can be said to be a period during which a write operation is performed.

[0539] Here, Vw is preferably equal to or greater than VSP, for example, equal to VSP. Although GND is a ground potential in this specification and the like, it is not necessarily required to be a ground potential as long as the memory cell 1480 can be driven to satisfy the spirit of one embodiment of the present invention. For example, if the absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage are different and the absolute values ​​of the first coercive voltage and the second coercive voltage are different, GND can be a potential other than ground.

[0540] From time T02 to time T03, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. From time T01 to time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be set to VSP or higher, so from time T02 to time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 62 shown in FIG. 31B. As a result, from time T02 to time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

[0541] After the potentials of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor M9. This completes the write operation, and data "1" is stored in the memory cell 1480. Note that the potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., as long as the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage -Vc.

[0542] From time T03 to time T04, the potential of the wiring WL is set to a high potential. This turns on the transistor M9. The potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" from time T01 to time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in the memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may be higher than Vw, for example.

[0543] Since the above read is destructive read, the data "1" stored in the memory cell 1480 is lost. Therefore, from time T04 to time T05, the potential of the wiring BL is set to Vw, and the potential of the wiring PL is set to GND. As a result, the data "1" is rewritten to the memory cell 1480. Therefore, the period from time T04 to time T05 can be considered as a period in which a rewrite operation is performed.

[0544] From time T05 to time T11, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the rewriting operation is completed, and data "1" is held in the memory cell 1480.

[0545] From time T11 to time T12, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since data "1" is stored in the memory cell 1480, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the memory cell 1480 is read. Therefore, the period from time T11 to time T12 can be considered a period in which a read operation is performed.

[0546] From time T12 to time T13, the potential of the wiring BL is set to GND. Because the transistor M9 is on, the potential of one electrode of the capacitor Cfe is set to GND. The potential of the wiring PL is set to Vw. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe is "GND-Vw." This allows data "0" to be written to the memory cell 1480. Therefore, the period from time T12 to time T13 can be considered a period during which a write operation is performed.

[0547] From time T13 to time T14, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to the curve 61 shown in FIG. 31B from time T13 to time T14. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.

[0548] After the potentials of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor M9. This completes the write operation, and data "0" is stored in the memory cell 1480. Note that the potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0549] From time T14 to time T15, the potential of the wiring WL is set to a high potential. This turns on the transistor M9. The potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" from time T12 to time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Specifically, the potential of the wiring BL is equal to or lower than Vref. Therefore, the bit line driver circuit can read the data "0" stored in the memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0550] From time T15 to time T16, the potential of the wiring BL is set to GND, and the potential of the wiring PL is set to Vw, thereby rewriting data "0" to the memory cell 1480. Therefore, the period from time T15 to time T16 can be considered a period in which a rewriting operation is performed.

[0551] From time T16 to time T17, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the rewriting operation is completed, and data "0" is held in the memory cell 1480.

[0552] From time T17 to time T18, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since data "0" is stored in the memory cell 1480, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the memory cell 1480 is read. Therefore, the period from time T17 to time T18 can be considered a period in which a read operation is performed.

[0553] From time T18 to time T19, the potential of the wiring BL is set to Vw. Because the transistor M9 is on, the potential of one electrode of the capacitor Cfe is set to Vw. The potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe is "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T18 to time T19 can be considered a period during which a write operation is performed.

[0554] After time T19, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the write operation is completed, and data "1" is held in the memory cell 1480.

[0555] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0556] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, so power consumption can be reduced.

[0557] In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 １０ or more, preferably 1×10 １２ or more, more preferably 1×10 １５ The FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0558] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more in a temperature environment of 150°C or 200°C.

[0559] The FE memory can also be applied to cache memories and registers of a CPU, a GPU (Graphics Processing Unit), etc. By combining the FE memory with the cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0560] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0561] 32A and 32B show an example of a chip 1200 on which a semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0562] As shown in FIG. 32A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0563] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201 as shown in Fig. 32B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0564] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. Furthermore, for example, the NOSRAM described in the above embodiment can be used as the flash memory 1222.

[0565] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0566] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0567] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0568] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0569] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0570] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0571] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0572] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204 .

[0573] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0574] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification.

[0575] (Embodiment 5) In this embodiment, an application example of a semiconductor device using the memory device shown in the previous embodiment will be described. The memory device shown in the previous embodiment can be applied to various removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (Solid State Drives). Figures 33A to 33E schematically show several configuration examples of removable memory devices. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0576] 33A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory chip 1105 or the like can be incorporated with the storage device or the semiconductor device described in the above embodiments.

[0577] FIG. 33B is a schematic diagram of the external appearance of an SD card, and FIG. 33C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1114 or the like.

[0578] FIG. 33D is a schematic diagram of the appearance of an SSD, and FIG. 33E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of the board 1153, the capacity of the SSD 1150 can be increased. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1154 or the like.

[0579] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0580] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that the description of the OS transistor will be briefly compared with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0581] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0582] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0583] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0584] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0585] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0586] Furthermore, in Si transistors, a short channel effect (also referred to as SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0587] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0588] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0589] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0590] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n− / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0591] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation.

[0592] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0593] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0594] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0595] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0596] [Electronic Component] FIG. 34A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 34A has semiconductor device 710 inside mold 711. FIG. 34A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0597] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The memory layer 716 may have a configuration in which a single layer including a memory cell array is provided. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0598] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0599] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0600] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0601] 34B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0602] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM)...

Claims

1. The first laminate and The semiconductor layer beneath the first laminate, It comprises a second laminate beneath the semiconductor layer, The semiconductor layer has a first region and a second region and a third region provided so as to sandwich the first region. The first laminate and the second laminate are provided symmetrically with respect to the first region. The first laminate comprises a first insulator and a second insulator on the first insulator. The second laminate comprises a third insulator and a fourth insulator beneath the third insulator. The second insulator is less permeable to hydrogen than the first insulator. The fourth insulator is less permeable to hydrogen than the third insulator. Each of the first and third insulators comprises silicon and oxygen. Each of the second and fourth insulators comprises silicon and nitrogen, The third insulator is island-shaped, In a cross-sectional view, the side edge of the third insulator coincides with the side edge of the semiconductor layer, wherein the semiconductor device is configured to meet these conditions.

2. A first laminate, The semiconductor layer beneath the first laminate, It comprises a second laminate beneath the semiconductor layer, The semiconductor layer has a first region and a second region and a third region provided so as to sandwich the first region. The first laminate and the second laminate are provided symmetrically with respect to the first region. The first laminate comprises a first insulator, a second insulator on the first insulator, and a third insulator below the first insulator. The second laminate comprises a fourth insulator, a fifth insulator on the fourth insulator, and a sixth insulator below the fourth insulator. The second insulator is less permeable to hydrogen than the first insulator. The sixth insulator is less permeable to hydrogen than the fourth insulator. Each of the first and fourth insulators comprises silicon and oxygen. Each of the second and sixth insulators comprises silicon and nitrogen. The third insulator is less permeable to oxygen than the first insulator. The fifth insulator is less permeable to oxygen than the second insulator. A semiconductor device wherein each of the third and fifth insulators is made of aluminum.

3. In claim 2, The fourth insulator and the fifth insulator have a laminated structure. The aforementioned layered structure is island-like, A semiconductor device in which, in a cross-sectional view, the side edge of the stacked structure coincides with the side edge of the semiconductor layer.

4. The first laminate and The semiconductor layer beneath the first laminate, It comprises a second laminate beneath the semiconductor layer, The semiconductor layer has a first region and a second region and a third region provided so as to sandwich the first region. The first laminate and the second laminate are provided symmetrically with respect to the first region. The first laminate comprises a first insulator, a second insulator on the first insulator, and a third insulator on the second insulator. The second laminate comprises a first metal oxide, a fourth insulator beneath the first metal oxide, and a fifth insulator beneath the fourth insulator. The first insulator is less permeable to oxygen than the second insulator. The third insulator is less permeable to hydrogen than the second insulator. The first metal oxide is less permeable to oxygen than the fourth insulator. The fifth insulator is less permeable to hydrogen than the fourth insulator. Each of the first insulator and the first metal oxide comprises at least one of gallium and aluminum. Each of the second and fourth insulators comprises silicon and oxygen, A semiconductor device wherein each of the third and fifth insulators comprises silicon and nitrogen.

5. In claim 4, The semiconductor layer has a second metal oxide, Each of the first metal oxide and the second metal oxide contains indium, A semiconductor device wherein the atomic ratio of at least one of gallium and aluminum to indium in the first metal oxide is greater than the atomic ratio of at least one of gallium and aluminum to indium in the second metal oxide.

6. In claim 4, A sixth insulator is further provided between the fourth insulator and the fifth insulator. The sixth insulator is a semiconductor device having the function of capturing or fixing hydrogen.

7. In claim 6, A seventh insulator is further provided between the second insulator and the third insulator. The seventh insulator is a semiconductor device having the function of capturing or fixing hydrogen.

8. In any one of claims 1 to 7, The present invention further comprises a first conductor and a second conductor. The first conductor is located above the first laminate, The second conductor is a semiconductor device located below the second laminate.

9. In claim 8, It further comprises a third conductor and a fourth conductor, The second region overlaps with the third conductor, The third region overlaps with the fourth conductor, and is a semiconductor device.

10. The device comprises the semiconductor device described in claim 9 and a capacitive element, The aforementioned capacitive element is a ferroelectric capacitor, in a memory device.